Integrated circuits (ics) employing directly coupled metal lines between vertically-adjacent interconnect layers for reduced coupling resistance, and related methods
Номер патента: EP4402720A1
Опубликовано: 24-07-2024
Автор(ы): Giridhar Nallapati, John Jianhong ZHU, Junjing Bao
Принадлежит: Qualcomm Inc
Опубликовано: 24-07-2024
Автор(ы): Giridhar Nallapati, John Jianhong ZHU, Junjing Bao
Принадлежит: Qualcomm Inc
Реферат: Integrated circuits (ICs), including capacitors and inductors, employing directly coupled metal lines between vertically-adjacent interconnect layers for reduced coupling resistance, and related fabrication methods. By directly coupled, it is meant that there is not an intermediate vertical interconnect access (via) layer with a via(s) interconnecting the metal lines in vertically-adjacent interconnect layers. An overlying and underlying metal line in respective and vertically-adjacent overlying and underlying interconnect layers are directly coupled to each other without the need for an intermediate via layer. For example, directly coupled metal in adjacent interconnect layers of IC can reduce contact resistance between the metal lines and reduce the overall height of the IC. An insulating layer(s) can be disposed in select recessed regions between the overlying interconnect layer and the underlying interconnect layer to insulate an overlying metal line from another vertically-intersecting underlying metal line that are not intended to be electrically coupled together.
INTEGRATED CIRCUITS (ICs) EMPLOYING DIRECTLY COUPLED METAL LINES BETWEEN VERTICALLY-ADJACENT INTERCONNECT LAYERS FOR REDUCED COUPLING RESISTANCE, AND RELATED METHODS
Номер патента: US20240203866A1. Автор: John Jianhong ZHU,Giridhar Nallapati,Junjing Bao. Владелец: Qualcomm Inc. Дата публикации: 2024-06-20.