Systems and methods for selectively bypassing address-generation hardware in processor instruction pipelines
Номер патента: EP3841464A1
Опубликовано: 30-06-2021
Автор(ы): Andrej Kocev, Jay Fleischman, Johnny C. CHU, Kai Troester, Michael W. Long, Neil Marketkar, Tim J. Wilkens
Принадлежит: Advanced Micro Devices Inc
Опубликовано: 30-06-2021
Автор(ы): Andrej Kocev, Jay Fleischman, Johnny C. CHU, Kai Troester, Michael W. Long, Neil Marketkar, Tim J. Wilkens
Принадлежит: Advanced Micro Devices Inc
Реферат: Systems and methods selectively bypass address-generation hardware in processor instruction pipelines. In an embodiment, a processor includes an address-generation stage and an address-generation-bypass-determination unit (ABDU). The ABDU receives a load/store instruction. If an effective address for the load/store instruction is not known at the ABDU, the ABDU routes the load/store instruction via the address-generation stage of the processor. If, however, the effective address of the load/store instruction is known at the ABDU, the ABDU routes the load/store instruction to bypass the address-generation stage of the processor.
Systems and methods for selectively bypassing address-generation hardware in processor instruction pipelines
Номер патента: US20200065108A1. Автор: Michael W. Long,Jay Fleischman,Kai Troester,Andrej Kocev,Neil Marketkar,Johnny C. CHU,Tim J. Wilkens. Владелец: Advanced Micro Devices Inc. Дата публикации: 2020-02-27.