Virtual address translation hardware assist circuit and method
Номер патента: CA2173225A1
Опубликовано: 20-04-1995
Автор(ы): James B. MacDonald, Richard W. Lones, Stephen W. Olson
Принадлежит: James B. MacDonald, Lg Semicon Co., Ltd., Richard W. Lones, Stephen W. Olson, Wang Laboratories, Inc.
Опубликовано: 20-04-1995
Автор(ы): James B. MacDonald, Richard W. Lones, Stephen W. Olson
Принадлежит: James B. MacDonald, Lg Semicon Co., Ltd., Richard W. Lones, Stephen W. Olson, Wang Laboratories, Inc.
Реферат: A method, and circuitry that operates in accordance with the method, for generating an entry for a translation buffer in a data processor that employs virtual memory addressing. The method includes the first steps of storing a Faulted Virtual Address in a first register (96) and a Zone Table Address (ZTA) in a second register (94). In response to the execution of a micro-instruction, a next step forms an address in memory of a Zone Table Entry (ZTE) by selectively combining the content of the first register with the content of the second register, while simultaneously testing the ZTA for physical address mapping. In response to an execution of a next micro-instruction, a next step accesses the ZTE with the formed address, and forms an address in memory of a Segment Table Entry (STE) by selectively combining the content of the first register with a content of the ZTE, while simultaneoysly testing the ZTE for a Zone fault. In response to an execution of a next micro-instruction, a next step accesses the STE with the formed address, and forms an address in memory of a Page Table Entry (PTE) by selectively combining the content of the first register with a content of the STE, while simultaneously testing the STE for a Zone fault. In response to an execution of a next micro-instruction, a next step accesses the PTE with the formed address and selectively combines the content of the STE with the content of the PTE and outputs the combination as a translation buffer entry, while simultaneously testing the PTE for a Page fault.
Memory management apparatus and method
Номер патента: EP4127944A1. Автор: Jan-Erik Ekberg,Igor STOPPA. Владелец: Huawei Technologies Co Ltd. Дата публикации: 2023-02-08.