Quadrature amplitude demodulator comprising a combination of a full-wave rectifying circuit and binary detectors
Реферат: Abstract In a demodulator for use in deriving demodulated signals from a mod-ulated signal subjected to k-by-k quadrature amplitude-and-phase modulation where k is equal to 2N and N is an integer greater than unity, first and second detection signals, each having k-levels, are derived from the modulated signal by a coherent detecting circuit and processed by first and second processing circuits. Each of the first and the second processing circuits is implemented by a combination of (N-1) full-wave rectifier(s) and (N+2) binary detectors to produce each set of binary signals and each additional binary signal divis-ible into a pair of partial bit signals. Alternatively, each processing circuit is implemented by a combination of N full-wave rectifiers and first through (N+1)-th binary detectors. The first through the N-th detectors detect each set while the (N+1)-th detector, each additional binary signal. Anyway, each set serves to produce the demodulated signals while each addit-ional binary signal, an AGC signal and an APC signal.
Quadrature amplitude demodulator comprising a combination of a full-wave rectifying circuit and binary detectors
Номер патента: DE3371589D1. Автор: Toshihiko C O Nec Corporat Ryu. Владелец: NEC Corp. Дата публикации: 1987-06-19.