ПРОГРАММИРУЕМОЕ ЛОГИЧЕСКОЕ УСТРОЙСТВО

Изобретение относится к вычислительной технике и может быть использовано в отказоустойчивых, радиационно-стойких программируемых логических интегральных схемах (ПЛИС) для вычисления логических функций. Техническим результатом является повышение отказоустойчивости. Устройство содержит группу n инверторов переменных, n групп, n - число входных переменных, основных передающих транзисторов по 2, i=1, n транзисторов в группе, группу 2инверторов настройки, выходной инвертор, 2-1 подгрупп дополнительных передающих транзисторов для каждого основного четного и нечетного транзистора n групп передающих транзисторов, состоящих из трех транзисторов. В каждый инвертор из группы 2инверторов настройки, группы n инверторов переменных, выходной инвертор введены три дополнительных транзистора n-МОП и три дополнительных транзистора p-МОП. 5 ил., 3 табл.

ЛОГИЧЕСКИЙ ЭЛЕМЕНТ «ИСКЛЮЧАЮЩЕЕ ИЛИ»

Изобретение относится к элементам вычислительной техники. Технический результат - повышение надежности функционирования и быстродействия логических элементов. Это достигается тем, что в логический элемент «Исключающее ИЛИ» дополнительно введены первый и второй источники тока, причем первый вывод первого источника тока соединен с узлом соединения эмиттеров первого и второго транзисторов. Первый вывод второго источника тока соединен с узлом соединения эмиттеров четвертого и пятого транзисторов. Вторые выводы первого и второго источников тока соединены с шиной источника отрицательного напряжения питания. Базы второго и пятого транзисторов соединены с шиной подачи опорного напряжения. Коллектор второго транзистора соединен с узлом соединения коллектора четвертого транзистора, базы третьего транзистора и второго вывода третьего резистора. Коллектор пятого транзистора соединен с узлом соединения базы шестого транзистора, коллектора первого транзистора и второго вывода первого резистора. 2 ил.

РЕГУЛИРУЕМОЕ ВХОДНОЕ ПРИЕМНОЕ УСТРОЙСТВО ДЛЯ ВЫСОКОСКОРОСТНОГО ИНТЕРФЕЙСА С НИЗКИМ УРОВНЕМ МОЩНОСТИ

... 1. Входное приемное устройство с разрешением по логическому порогу переменного диапазона, при этом устройство содержит: ! - логический затвор; ! - конфигурацию логического порога, соединенную параллельно с логическим затвором и выполненную с возможностью принимать переменное значение логического порога и конфигурировать логическое устройство для значения логического порога; и ! - вспомогательное устройство, выполненное с возможностью принимать переменное значение логического порога и выполненное с возможностью предоставления тракта тока смещения логическому затвору, отличного от тракта тока смещения, предоставляемого логическому затвору посредством конфигурации логического порога. ! 2. Устройство по п.1, дополнительно содержащее детектор логического порога, выполненный с возможностью принимать значение логического порога и предоставлять тракт тока дополнительного смещения логическому затвору на основе переменного значения логического порога. ! 3. Устройство по п.2, в котором детектор логического ...

ПРОГРАММИРУЕМОЕ ЛОГИЧЕСКОЕ УСТРОЙСТВО

Программируемое логическое устройство, содержащее группу n инверторов переменных, n групп, n - число входных переменных, основных передающих транзисторов по 2, i=1, n транзисторов в группе, группу 2инверторов настройки, выходной инвертор, входы n переменных, 2входы настройки, выход устройства, причем входы настройки подключены ко входам соответствующих инверторов из группы 2инверторов настройки, входы i-x инверторов подключены к соответствующим к i-м входам входов n переменных, затвор каждого четного транзистора i-й группы из n групп передающих транзисторов подключен к i-му входу входов n переменных, затвор каждого нечетного транзистора i-й группы из n групп передающих транзисторов подключен к выходу i-го инвертора группы n инверторов переменных, входы которых подключены к i-му входу входов n переменных, стоки четных и нечетных - двух передающих транзисторов первой группы объединены и подключены ко входу выходного инвертора, выход которого является выходом устройства, каждый инвертор из ...

Integrierter Schaltkreis

LOGISCHE SCHALTUNG MIT GESCHALTETEM ANTISTRESSTRANSISTOR.

Circuit for an analog protection of digital information items of sequence circuits

The circuit according to the invention protects sequence circuits which contain digital information against disturbances which are higher than the technologically determined interference threshold of these circuits. The protective circuit does not depend on the accessibility of the sensitive points of the digital circuits, it does not reduce the logical value of the integrated circuits used and does not exert any influence on the normal operating speed of the circuits. ...

SEMI CONDUCTOR CHIP FOR PERFORMING BOTH DIGITAL AND ANALOG FUNCTIONS

Data output buffer

TENSION-STABILIZED LOW LEVEL DRIVER

INTEGRATED FLOATING POWER TRANSMISSION DEVICE WITH REDUCED ELEKROMAGNETI EMISSIONS

N-CHANNEL-ESD-CLAMP WITH IMPROVED ACHIEVEMENT

OUTPUT DRIVING CIRCUIT

Apparatus and method for bus signal termination compensation during detected quiet cycle

FUNCTIONALLY REDUNDANT LOGIC NETWORK ARCHITECTURES WITH LOGIC SELECTION MEANS

A SEMICONDUCTOR LOGIC ELEMENT AND LOGIC CIRCUITRIES

The invention relates to a semiconductor logic element comprising a field effect transistor of the first conductivity type and a field effect transistor of the second conductivity type. A gate of the first FET is an input of the semiconductor logic element, a drain of the second FET is referred to as the output of the semiconductor logic element and a source of the second FET is the source of the semiconductor logic element. By applying applicable potentials to the terminals of the field effect transistors it is possible to influence the state of the output of the logic element. The invention relates also to different kinds of logic circuitries comprising the described logic element.

Verfahren und Schaltungsanordnung zur Verringerung der Störanfälligkeit von integrierten Schaltkreisen

Baustein für digitale Signalverarbeitung

Device with a sensor and an actuator, in particular for use as a door contact switch, and method for testing the device.

Die Erfindung betrifft eine Vorrichtung (1), wie z.B. einen Türkontaktschalter, beinhaltend einen Sensor (4) und einen Betätiger (3), wobei der Sensor (4) einen Empfangskreis (5) mit einem Sensorelement (6) und einem Detektorelement (8) aufweist, sowie eine mit dem Detektorelement (8) verbundene Recheneinheit (10). Das Sensorelement (6) ist dazu ausgebildet, während eines Normalbetriebs bei Unterschreiten einer Schaltentfernung (2) zwischen Sensor (4) und Betätiger (3) mit dem Betätiger (3) zur Erzeugung eines ersten Empfangskreis-Signals (7a) zusammenzuwirken. Das Detektorelement (8) ist dazu ausgebildet, in Abhängigkeit des ersten Empfangskreis-Signals (7a) ein erstes Ausgangs-Signal zu erzeugen und an die Recheneinheit (10) zu übermitteln. Weiter enthält der Empfangskreis (5) einen Signalemulator (19) und ein Umschaltelement (17), wobei der Signalemulator (19) dazu ausgebildet ist, während eines Testbetriebs ein zweites Empfangskreis-Signal (7b) zu erzeugen. Das Detektorelement (8) ist ...

INSPECTING DEVICE FOR JUST AMPLIFIERS Of ATTACK

RANDOM NUMBER OF OSCILLATIONS

L'invention concerne un circuit (20) de génération d'un nombre d'oscillations comportant : une première branche comprenant au moins une ligne à retard (21) apportant des retards symétriques sur fronts montants et sur fronts descendants et au moins un élément retardateur asymétrique (22) apportant des retards différents sur fronts montants et sur fronts descendants ; une deuxième branche, rebouclée sur la première et comprenant au moins une ligne à retard (27) apportant des retards symétriques sur fronts montants et sur front descendants.

SYSTEM OF MEMORIZING Of a BREAKDOWN IN a POWER CIRCUIT

FIVE VOLT TOLERANT INTEGRATED CIRCUIT SIGNAL PAD WITH THREE VOLT ASSIST

Electrostatic discharge protective circuit having rise time detector and discharge sustaining circuitry

Methods and devices of the invention include an electrostatic discharge (ESD) protection circuit. This circuit includes rise time dependent activation circuitry capable of detecting a slew rate of an input signal and capable of determining whether the slew rate of the input signal is greater than a threshold value. For an ESD event said activation circuitry generates a trigger signal. Additionally, the activation circuitry is coupled with the ESD dissipation duration control circuitry which is further coupled with an ESD dissipation circuit. This arrangement enabling the duration control circuit to be activated by the trigger signal which responds by producing an activation signal that activates the ESD dissipation circuitry and that controls the length of time the dissipation circuit remains active. The ESD dissipation circuitry includes a shunt that redirects the ESD energy away from the protected internal circuit. The ESD dissipation duration circuitry further configured to maintain ...

Device with latch up detection circuit and method of forming the same

INTEGRATED CIRCUITS HAVING ACCESSIBLE AND INACCESSIBLE PHYSICALLY UNCLONABLE FUNCTIONS

An integrated circuit substrate of an aspect includes a plurality of exposed electrical contacts. The integrated circuit substrate also includes an inaccessible set of Physically Unclonable Function (PUF) cells to generate an inaccessible set of PUF bits that are not accessible through the exposed electrical contacts. The integrated circuit substrate also includes an accessible set of PUF cells to generate an accessible set of PUF bits that are accessible through the exposed electrical contacts. Other apparatus, methods, and systems are also disclosed.

PROGRAM BINDING SYSTEM, METHOD AND SOFTWARE FOR A RESILIENT INTEGRATED CIRCUIT ARCHITECTURE

The exemplary embodiments provide a program binder for a resilient integrated circuit. An exemplary IC comprises a plurality of composite circuit elements, a state machine element (SME), and a plurality of communication elements. Each composite circuit element comprises an element interface and a selected circuit element which may vary by element type, and which may be configurable. An exemplary program binding method includes assigning a first action to a first computational element having a first type; assigning a second action to a second computational element having a second type; and establishing a first data routing, through a selected communication element, between the first computational element and the second computational element. In the event of detection of a fault with a composite circuit element or a communication element, the various actions may be re¬ assigned and new data routings established.

CONTROLLER COMPUTING SYSTEM FOR PREVENTING MALICIOUS CONTROL OF A CONTROLLED MACHINERY SYSTEM

A controller computing system, including a plurality of controllers, each controller configured to i) calculate a respective output based on a current set point and ii) output a timer signal; a cyber security manager (CSM) computing module configured to: output a nominal signal indicating that the current set point is a non-malicious set point when the CSM computing module receives each of the timer signals from each of the plurality of controllers; and output a reset signal indicating that the current set point is a malicious set point when the CSM computing module receives less than each of the timer signals from the plurality of controllers.

Buffer protection against output-node voltage excursions

A three-state output buffer circuit with built-in protection against power-rail corruption by bus-imposed voltages when the buffer is in its high-impedance state. In particular the invention protects the high-potential power rail of the high-Z buffer against voltages appearing at the buffer's output node which exceed the voltage of the buffer's high-potential rail. It prevents this overvoltage from finding its way to the power-rail, and thus has application to those situations where a common bus is coupled to a variety of circuits including, for example, 3.3-volt buffers and 5-volt buffers. The invention provides this protection without the "dead zone" of prior-art and related-art circuits. Furthermore, the present invention also has application where it is the low-potential power rail that needs protecting, in situations where the bus may impose voltages at the buffer's output node that are lower than the voltage of the buffer's low-potential power rail. The protection circuit utilizes ...

SEMICONDUCTOR DEVICE AND ELECTRONIC DEVICE

To provide a semiconductor device that inhibits unexpected output of a high-level signal immediately after the rise of a power supply voltage. A semiconductor device includes a first buffer circuit, a level shifter circuit, and a second buffer circuit. A first potential is supplied to the first buffer circuit, and a second potential is supplied to the level shifter circuit and the second buffer circuit; consequently, the semiconductor device returns to a normal state. The first potential is supplied to the first buffer circuit before the second potential is supplied to the level shifter circuit and the second buffer circuit, whereby the operations of the level shifter circuit and the second buffer circuit can be controlled. This inhibits unexpected output of a high-level signal to a wiring connected to the second buffer circuit.

Temperature compensation circuit and testing apparatus

A temperature compensation circuit for effectively compensating the difference of a switching timing due to temperature change of a switching element included in a logic circuit is provided. The temperature compensation circuit includes a temperature detecting section for detecting a value corresponding to the temperature of the switching element, and a correction section for correcting the voltage of a logic signal inputted from a previous circuit to the logic circuit in order to reduce the difference of the switching timing due to the temperature change of the switching element based on the value corresponding to the temperature.

Majority logic gate fabrication

A new class of logic gates are presented that use non-linear polar material. The logic gates include multi-input majority gates and threshold gates. Input signals in the form of analog, digital, or combination of them are driven to first terminals of non-ferroelectric capacitors. The second terminals of the non-ferroelectric capacitors are coupled to form a majority node. Majority function of the input signals occurs on this node. The majority node is then coupled to a first terminal of a capacitor comprising non-linear polar material. The second terminal of the capacitor provides the output of the logic gate, which can be driven by any suitable logic gate such as a buffer, inverter, NAND gate, NOR gate, etc. Any suitable logic or analog circuit can drive the output and inputs of the majority logic gate. As such, the majority gate of various embodiments can be combined with existing transistor technologies.

Semiconductor memory device and method for operating the same

A semiconductor memory device includes an edge detector configured to receive two pairs of complementary clocks to detect edges of the clocks, a comparator configured to compare output signals of the edge detector to detect whether clocks of the same pair have a phase difference of 180 degrees and detect whether clocks of different pairs have a phase difference of 90 degrees, a control signal generator configured to generate a control signal for controlling phases of the clocks according to an output signal of the comparator, and a phase corrector configured to correct phases of the clocks in response to the control signal.

Controller computing system for preventing malicious control of a controlled machinery system

A controller computing system, including a plurality of controllers, each controller configured to i) calculate a respective output based on a current set point and ii) output a timer signal; a cyber security manager (CSM) computing module configured to: output a nominal signal indicating that the current set point is a non-malicious set point when the CSM computing module receives each of the timer signals from each of the plurality of controllers; and output a reset signal indicating that the current set point is a malicious set point when the CSM computing module receives less than each of the timer signals from the plurality of controllers.

INTEGRATED CIRCUIT PROTECTION AGAINST REVERSE ENGINEERING

A method for protecting an integrated circuit against reverse engineering including predefining a secret bit, forming a first clocked memory element having a first data input, a first data output and a first clock input in the integrated circuit, forming a second clocked memory element having a second data input, a second data output and a second clock input in the integrated circuit, forming a logic path in the integrated circuit and coupling the first data output to the second data input via the logic path and forming a clock signal line in the integrated circuit and coupling the first clock input to the second clock input via the clock signal line. The logic path and the clock signal line are formed such that their delays are such that, depending on a value of the secret bit, a logic level change of the first clocked memory element with a clock edge of a clock signal on the clock signal line affects a logic level output by the second clocked memory element with the same clock edge of ...

Analog macro embedded in a digital gate array

A single logic gate array chip (1) is disclosed having a first portion (2) dedicated to the generation of one or more clock signals and the remaining portion (3) occupied by logic circuits. The first portion (2) uses the same gate array cell design as embodied in the logic circuits of the remaining portion (3). Both portions are powered by similar gate array metallization patterns, although some of the cells of the clock signal sources are disconnected from the normal chip powering busses and are powered instead by respective control signal generators. Each control signal represents the frequency difference between a given clock signal and a reference signal. The cells which are powered by a given control signal introduce a commensurate signal delay to drive the clock signal frequency into a predetermined relationship with the frequency of the reference signal.

Output logic setting circuit in semiconductor integrated circuit.

PASSIVE DYNAMIC BIASING FOR MOSFET CASCODE

INPUT CIRCUIT FOR SETTING OPERATION MODE OF MICROCOMPUTER

PROBLEM TO BE SOLVED: To provide the input circuit equipped with a means which cuts off the current path from the pull-up element of an input terminal. SOLUTION: The potential of an input terminal I1 is pulled up to a power source potential VDD by a P channel MOS transistor(TR) P1 and connected to one input terminal of a NOR circuit 101 through an N channel MOS TR N1. The other input terminal of the NOR 101 is connected to an input terminal I2 and the output terminal of the NOR 101 is connected to the gate electrode of the P channel MOS TR P1 and the input terminal of an inverter 102 respectively. The output terminal of the inverter 102 is connected to one input terminal of the NOR 101 through a TR N2. The input terminal I2 is further connected to the gate electrode of the TR N1 and the input terminal of the inverter 104 through a delay circuit 103, and the output terminal of the inverter 104 is connected to the gate electrode of the TR N2. COPYRIGHT: (C)1997,JPO ...

Многовходовой логический элемент комплементарной металл-оксид-полупроводниковой структуры декодера

Изобретение относится к области вычислительной техники. Технический результат - повышение помехоустойчивости многовходового логического элемента при воздействии одиночной ядерной частицы. Для этого предложен многовходовой логический элемент комплементарной металл-оксид-полупроводниковой структуры декодера, который состоит из статических элементов ИЛИ-НЕ и статических элементов И-НЕ, соединенных между собой в цепочки чередующихся элементов так, что выходы элементов ИЛИ-НЕ соединены с входами последующих в цепочке элементов И-НЕ, выходы элементов И-НЕ соединены с входами последующих в цепочке элементов ИЛИ-НЕ. Многовходовой логический элемент снабжен компенсирующими транзисторами с каналами электронной проводимости и компенсирующими транзисторами с каналами дырочной проводимости. Стоковые области каждого компенсирующего транзистора размещены на кристалле интегральной микросхемы относительно стоковых областей транзисторов с каналами такой же проводимости каждого из предшествующих в цепочке ...

Способ и устройство защиты программируемых интегральных микросхем, например микроконтроллеров, от тиристорного эффекта

Изобретение относится к электронике интегральных микросхем (ИМС) и может быть использовано в составе радиоэлектронной аппаратуры для защиты микросхем от воздействия тяжелых заряженных частиц (ТЗЧ), высокоэнергетичных протонов (ВЭП), импульсного ионизирующего излучения, пучкового оружия. Технический результат - повышение в 10-15 раз точности детектирования факта ТЭ и надежности аппаратуры, содержащей программируемые ИМС при воздействии ТЗЧ. Для этого предложен способ, который заключается в измерении тока питания ИМС, ограничении и отключении тока питания ИМС при детектировании факта возникновения ТЭ, а возникновение ТЭ определяется по набросу тока при его возникновении. Устройство защиты (УЗ) ИМС от ТЭ содержит датчик тока, устройство защиты по максимальному току, а также усилитель разности текущего и предшествующего значений токов на двух интеграторах токов, устройство выделения тока ТЭ и таймеры, обеспечивающие требуемый алгоритм работы устройства. 2 н. и 1 з.п. ф-лы, 3 ил.

Триггерный логический элемент И/ИЛИ на полевых транзисторах

Изобретение относится к цифровой схемотехнике, автоматике и промышленной электронике. Технический результат: повышение нагрузочной способности триггерного логического элемента И/ИЛИ на полевых транзисторах. Сущность: триггерный логический элемент И/ИЛИ на полевых транзисторах содержит шесть полевых транзисторов, пять резисторов и источник питающего постоянного напряжения. Предложенное соединение элементов обеспечивает силу тока внешней нагрузки, равной сумме токов двух транзисторов, что обеспечивает достижение указанного результата. 3 ил.

Verfahren und Vorrichtung zur Beschaltung von Eingägnen bei Microcontrollern sowie entsprechender Microcontroller

Verfahren und Vorrichtung zur Beschaltung von Konfigurationseingängen (101-107) eines Mikrocontrollers, wobei die Vorrichtung derart ausgebildet ist, dass an jedem Konfigurationseingang (101-107) ein Signalzustand aus wenigstens zwei möglichen Signalzuständen einzustellen ist, dadurch gekennzeichnet, dass DOLLAR A mit jedem Konfigurationseingang (101-107) jeweils eine Energiequelle (121-127) verbunden ist, welche mindestens zwei Zustände einnehmen kann, um die wenigstens zwei Signalzustände an jedem Konfigurationseingang einzustellen, wobei Einstellmittel (109) vorgesehen sind, durch welche die Zustände jeder Energiequelle derart gesteuert werden, dass der vorgegebene Signalzustand für jeden Konfigurationseingang vorliegt.

Ausgangsschaltung für eine integrierte Halbleiterschaltung

HALBLEITERCHIP

Gemäß einer Ausführungsform ist ein Halbleiterchip beschrieben, der Folgendes umfasst: einen Chip mit wenigstens einen p-Kanal-Feldeffekttransistor (FET), wenigstens einem n-Kanal-FET, einem ersten und einem zweiten Leistungsversorgungsanschluss, wobei der wenigstens eine n-Kanal-FET, falls er mit dem oberen Versorgungspotential an seinem Gate versorgt wird, das untere Versorgungspotential an das Gate des wenigstens einen p-Kanal-FET liefert, und der wenigstens eine p-Kanal-FET, falls er mit dem unteren Versorgungspotential an seinem Gate versorgt wird, das obere Versorgungspotential an das Gate des wenigstens einen n-Kanal-FET liefert, einen Vorladungsschaltkreis, der zum Vorladen des Schaltkreises in einen ersten Zustand konfiguriert ist, in dem das Potential an dem Gate des wenigstens einen n-Kanal-FET niedriger als das obere Versorgungspotential ist und das Potential an dem Gate des wenigstens einen p-Kanal-FET höher als das untere Versorgungspotential ist, und einen Detektionsschaltkreis ...

MONITORING DEVICE DOR DRIVE AMPLIFIERS

DEVICE AND PROCEDURE FOR THE BUS SIGNAL CONCLUSION COMPENSATION DURING SEIZED PEACE CYCLE

SPARE CELL ARCHITECTURE FOR FIXING DESIGN ERRORS IN MANUFACTURED INTEGRATED CIRCUITS

FAULT MODE DETECTION SYSTEM

ALTERNATING CURRENT STATIC CONTROL SYSTEM

FAULT MODE DETECTION SYSTEM

DEVICE FORMING A LOGIC GATE FOR DETECTING A LOGIC ERROR

La présente invention concerne un dispositif formant circuit électrique, caractérisé par le fait qu'il comprend des moyens logiques (30) générant et exploitant des signaux faibles de niveaux intermédiaires entre les niveaux d'alimentation dudit dispositif et des moyens de détection de signaux sortant de la gamme de tels signaux faibles.

SECURE SWITCH ASSEMBLY

A secure switch assembly is provided and includes inputs respectively associated with at least first and second security levels, switch element outputs respectively associated with the at least first and second security levels and a field programmable gate array (FPGA) operably interposed between the inputs and the switch element outputs. The FPGA has a first side facing the inputs and a second side facing the switch element outputs and includes a gate array. The gate array is programmable to generate entirely separate physical interconnections extending from the first side to the second side by which each of the first security level associated inputs and switch element outputs are connectable and each of the second security level associated inputs and switch element outputs are connectable.

Current mode logic circuit

Test device

A test device comprises a first level conversion unit, a second level conversion unit, and a switching unit. The first level conversion unit is used for being connected with a first board to be tested. The second level conversion unit is used for being connected with a second board to be tested. The switching unit is connected with the first and second level conversion units and a test master. The first level conversion unit is used for converting the level of transmitted signals between the first board to be tested and the test master. The switching unit is used for switching the connection of the test master to the first level conversion unit and the connection of the test master to the second level conversion unit. The test device is capable of converting various levels.

Identification circuit and method for generating an identification bit using physical unclonable functions

SECURITY Of an ELEMENT OF MEMORIZING Of a BINARY DATA, SMART CARD AND CHECK REGISTER

Semiconductor integrated circuit device

Disclosed is a semiconductor integrated circuit device equipped with a buffer portion which includes a pair of an input buffer portion and an output buffer portion. When an input circuit equipped with an input protection circuit is formed at the input buffer portion, circuit elements for an output circuit disposed at the output buffer portion are used in order to constitute the input protection circuit.

Integrated circuit devices having metastability protection circuits therein

Integrated circuit devices having metastability protection circuits therein include a main active circuit and a metastability detection/prevention circuit. The main active circuit may comprise a comparator, a sense amplifier, a differential amplifier or a voltage generating circuit, for example. The metastability detection/prevention circuit performs the function of detecting whether an output of the main active circuit has been disposed in a metastable state for a duration in excess of a transition duration. The output of the main active circuit may be considered as being in a metastable state if a potential of the output signal equals VMS, where VMS is in a range between VIL, and VIH. If the output signal has been in a metastable state for a duration in excess of the transition duration, then the metastability detection/prevention circuit will generate a control signal at a designated logic level. This control signal is provided as an input to the main active circuit and causes the output ...

Semiconductor device and method for detecting state of input signal of semiconductor device

A semiconductor device includes a signal detection unit suitable for detecting a state of an input signal and generating a detection signal based on a detected result, and a signal transmission unit suitable for selectively transmitting the input signal in response to the detection signal, wherein the signal detection unit includes a state signal generation unit suitable for detecting a level shifting time of the input signal, and generating a state signal at a detected level shifting time, and a state determination unit suitable for comparing a voltage level of the input signal with a voltage level of a reference voltage in response to the state signal, and outputting the detection signal.

Analog compensation circuit

The present disclosure relates to a compensation circuit for providing compensation over PVT variations within an integrated circuit. Using a low voltage reference current source, the compensation circuit generates directly, from an on-chip reference low voltage supply (VDD), a reference current (Iref) that is constant over PVT variations, whereas a detection current (Iz) that is variable over PVT variations is generated by a sensing circuit, which is based on a current conveyor, from a low voltage supply (VDDEVDD) applied across a single diode-connected transistor (M10) corresponding to a voltage difference between two reference low voltage supplies. Both currents (Iref, Iz) are then compared inside a current mode analog-to-digital converter that outputs a plurality of digital bits. These digital bits can be subsequently used to compensate for PVT variations in an I/O buffer circuit.

LAYOUT CONNECTION ISOLATION TECHNIQUE FOR IMPROVING IMMUNITY TO JITTER AND VOLTAGE DROP IN A STANDARD CELL

A standard cell architecture provides an improved immunity to power-supply voltage-drop, does not induce power-supply voltage drop on a continuous-row power rail of a standard cell, and maintains standard-cell environment compatibility. A circuit includes a first metal layer and a second metal layer that are formed different distances above a substrate. At least one first standard cell drives a first timing signal and includes at least one transistor receiving power from a first power rail in the first metal layer. At least one second standard cell drives a second timing signal and includes at least one transistor receiving power from a second power rail in the second metal layer. The second power rail has both a low peak noise level and a resistance that is lower than that of the first metal layer.

Apparatus for configuring performance of field programmable gate arrays and associated methods

An apparatus includes a temperature sensor, a voltage regulator, and a field programmable gate array (FPGA). The temperature sensor and the voltage regulator are adapted, respectively, to provide a temperature signal, and to provide at least one output voltage. The FPGA includes at least one circuit adapted to receive the at least one output voltage of the voltage regulator, and a set of monitor circuits adapted to provide indications of process and temperature for the at least one circuit. The FPGA further includes a controller adapted to derive a body-bias signal and a voltage-level signal from the temperature signal, from the indications of process and temperature for the at least one circuit, and from the at least one output voltage of the voltage regulator. The controller is further adapted to provide the body-bias signal to at least one transistor in the at least one circuit, and to provide the voltage-level signal to the voltage regulator.

METHOD AND CIRCUIT ARRANGEMENT FOR SWITCHING A SEMICONDUCTOR SWITCH

SEMICONDUCTOR DEVICE

PROBLEM TO BE SOLVED: To solve a problem that a signal delay occurring in an output buffer is prevented from being accurately measured. SOLUTION: This semiconductor device comprises: an internal circuit for performing a prescribed process based on a signal inputted from the exterior; an output buffer 12 for driving wires connected to an output terminal based on a signal outputted by the internal circuit; feedback wires (comprising FL10 to FL13) provided by being branched from an intra-buffer signal wire for transmitting data signals to an output stage circuit 25 of the output buffer 12 in the output buffer 12; and a delay test circuit connected to the feedback wires (FL11 and FL13). COPYRIGHT: (C)2009,JPO&INPIT ...

SEMICONDUCTOR DEVICE

PROBLEM TO BE SOLVED: To effectively suppress the breakdown of an input circuit caused by applying an ESD surge voltage as it is to the input circuit through an output circuit, in a semiconductor device including the output circuit and the input circuit which are supplied with power source voltages from different power source systems. SOLUTION: The semiconductor device includes a first power source pad 11, a first ground pad 12, a first power source line 13, a first ground line 14, an output circuit 15, a second power source pad 21, a second ground pad 22, a second power source line 23, a second ground line 24, an input circuit 25, a signal line 20, a main ESD protection element 16, a protection diode pair D1, and a PMOS transistor P2. The output circuit 15 includes a PMOS transistor P3, and the input circuit includes an NMOS transistor N1. In the PMOS transistor P2, a source is connected to the signal line 20, a drain is connected to the second ground line 24, and a gate and a back gate ...

Малогабаритный информационно-стабильный R-S триггер

Полезная модель предназначена для использования в устройствах памяти, центральных процессорах и счетчиках. Устройство содержит два логических элемента, в качестве одного из которых использован логический элемент ИЛИ-НЕ, вход R (Reset) и вход S (Set), выходы прямой Q и инверсныйВыход логического элемента ИЛИ-НЕ соединен с инверсным выходомВ качестве другого логического элемента устройство содержит двухвходовой логический элемент И, один из входов которого является инверсным. Вход R (Reset) соединен с инверсным входом логического элемента И. Вход S (Set) соединен с анодом первого диода диодного коммутатора, катод которого соединен с узлом, связанным со вторым входом логического элемента И и с катодом второго диода диодного коммутатора. Выход логического элемента И соединен с прямым выходом Q и с анодом второго диода диодного коммутатора, а также со входом логического элемента ИЛИ-НЕ. Устройство позволяет обеспечить четкую работу в режимах памяти, запрета и единичной установки.

Устройство адаптивной коммутации

Изобретение относится к автоматике и телемеханике, может быть использовано в аппаратуре дискретного управления с повышенной надежностью, имеющей ограниченный доступ для контроля, например для автоматических космических аппаратов. Достигаемый технический результат - повышение надежности при резервировании релейных ячеек дистанционных переключателей. Устройство адаптивной коммутации содержит шины питания, n однотипных резервированных релейных ячеек, выполненных на трех двухконтактных дистанционных переключателях, контакты которых соединены в контактные группы, информационный контроллер, второй контроллер, первая и вторая группы силовых ключей, первая и вторая группы развязывающих диодов, два блока контроля состояния релейных ячеек, последовательно с первым датчиком тока включен второй датчик тока, выход которого соединен с информационным входом второго контроллера, вход-выход второго контроллера является вторым входом–выходом устройства. 1 з.п. ф-лы, 3 ил.

ИЗБЫТОЧНЫЕ БИТЫ ФИЗИЧЕСКИ НЕКЛОНИРУЕМОЙ ФУНКЦИИ

... 1. Интегральная схема, содержащая:массив ячеек физически неклонируемой функции (PUF) для обеспечения необработанного PUF значения, при этом массив PUF ячеек содержит множество избыточных ячеек; исхему избыточности для выработки списка перенаправления, используемого для замены каждого из битов необработанного PUF значения значением избыточного бита из одной из избыточных ячеек.2. Интегральная схема по п. 1, дополнительно содержащая энергонезависимую память, в которой сохраняют список перенаправления.3. Интегральная схема по п. 1, в которой схема избыточности содержит:первое место хранения для хранения первого необработанного PUF значения;второе место хранения для хранения второго необработанного PUF значения; иустройство сравнения для сравнения первого необработанного PUF значения и второго необработанного PUF значения.4. Интегральная схема по п. 3, в которой устройство сравнения должно идентифицировать PUF ячейку как плохой бит, если устройство сравнения определяет, что первое необработанное ...

Monolithic integrated logic and interface circuit - performs several logic operations and is also timing circuit and memory

The monolithic integrated logic and interface circuit has a wide range of applications and can accept high input signal voltages. It consists of several independent operation circuits. One operation circuit performs the logic operations AND, NAND and NOR. The circuit consists of the series combination of an input protection circuit, input current sinks, input logic which threshold, signal delay circuit with threshold output stage and output protection circuit. By connecting a capacitor the circuit can be made into a timing circuit or a memory. An internal diode acts as voltage limited at the output.

Vorrichtung zum Schutz von integrierten Schaltungen mittels Schutzbussen

Die Erfindung betrifft eine Mehrfachausgangstreiberschaltung für integrierte Schaltungen mit mindestens zwei Ausgängen (A51, A52, ... A5x) und mindestens zwei diesen zugeordneten Ausgangstreibern (DR51, DR52, ... DR5x) mit Schutzstrukturen dieser Ausgangstreiber (DR51, DR52, ... DR5x). Sie zeichnet sich durch einen ersten gemeinsamen Schutzbus (PB1) und einen zweiten gemeinsamen Schutzbus (PB2) aus. Jeder der mindestens zwei Ausgangstreiber (DR51, DR52, ... DR5x) weist einen oberen P-Kanaltransistor (T51a, T51b, ... T51x) und einen unteren N-Kanaltransistor (T52a, T52b ... T52x) auf, die eine Push-Pull-Stufe bilden. Die Vorrichtung weist Detektionsvorrichtungen auf, die zum Ersten bei einer Überspannung oder Unterspannung an einem ersten Anschluss den ersten und einen zweiten Anschluss voneinander trennen und bei einer Überspannung den ersten Anschluss mit einem zweiten Schutzbus (PB2) verbinden und bei einer Unterspannung den ersten Anschluss mit einem ersten Schutzbus (PB1) verbinden.

Inverter mit bipolarem Transistor und komplementären MOS-Transistoren.

LOGISCHE STEUERSCHALTUNG

ELEKTRISCHES SYSTEM

Ein elektrisches System kann eine elektrische Einheit umfassen, die eine Stromquelle, eine elektrisch mit der Stromquelle verbundene Schaltanordnung, einen elektrisch mit der Schaltanordnung verbundenen Aktivierungsteil, eine elektrisch mit einem Pulsgenerator und/oder der Schaltanordnung verbundene elektrische Verriegelung und/oder eine elektrisch mit der Schaltanordnung und der elektrischen Verriegelung verbundene Steuereinrichtung enthält. Eine Ausführungsform eines Verfahrens zum Betreiben des elektrischen Systems kann umfassen: Aktivieren des Aktivierungsteils; Aktivieren, über den Aktivierungsteil, der Schaltanordnung, um die Steuereinrichtung elektrisch mit der Stromquelle zu verbinden; Verriegeln der Schaltanordnung in einem aktivierten Zustand über die elektrische Verriegelung; und/oder Entriegeln der Schaltanordnung über die Steuereinrichtung, um die Steuereinrichtung elektrisch von der Stromquelle zu trennen.

Integrierte Schaltung mit Logikschaltungen und wenigstens einer Gegentaktstufe.

Temperature-compensated driver circuit

A temperature-compensated driver circuit which is relatively stabilized in waveform amplitude and output timing by detecting the power consumption of its output driver stage and correcting and controlling the power consumption. The driver circuit comprises a temperature detector for detecting the temperature changes of output elements (31 and 32), a temperature compensator for adjusting the timing of an output signal (3) against an input signal (1) in response to a temperature detecting signal from the temperature detector, and an amplitude/impedance temperature compensator for adjusting the output amplitude of the output signal (3) and the output impedance in response to the temperature detecting signal from the temperature detector.

Single event effect mitigation for silicon-on-insulator CMOS technology

A circuit and method for mitigating radiation-induced Single Event Effects (SEE) in Silicon-on-Insulator (SOI) Complementary MetalOxideSemiconductor (CMOS) integrated circuits, in which a primary logic output 122 is generated from a primary logic gate 102 in response to an input 126, 128; a redundant logic output 124 is generated from a redundant logic gate 104 that duplicates the primary logic output in response to the input if an SEE is not present and an interleaved C-gate output 130 is generated from an interleaved C-gate 106 that emulates an inverter output when the primary logic output and the redundant logic output match, and does not change its output when the primary logic output and the redundant logic output do not match during the SEE.

PROCEDURE AND DEVICE FOR THE WIRING OF ENTRANCES WITH MICROCONTROLLERN AS WELL AS EQUIVALENTS OF MICROCONTROLLER

INTERFACE FOR COUPLING A BUS PARTICIPANT TO THE BUS OF A BUS SYSTEM

Interface for coupling a bus node to the bus line of a bus system

MULTI-CHANNEL CONTROL CIRCUIT

SINGLE EVENT TRANSIENT AND UPSET MITIGATION FOR SILICON-ON-INSULATOR CMOS TECHNOLOGY

A circuit and methods for mitigating radiation-induced Single Event Effects (SEE) in Silicon-on-Insulator (SOI) Complementary Metal-Oxide-Semiconductor (CMOS) integrated circuits are presented. A primary logic output is generated from a primary logic gate in response to an input. A redundant logic output is generated from a redundant logic gate that duplicates the primary logic output in response to the input if an SEE is not present. An interleaved C-gate output is generated from an interleaved C-gate that emulates an inverter output when the primary logic output and the redundant logic output match, and does not changes its output when the primary logic output and the redundant logic output do not match during the SEE.

ADJUSTABLE INPUT RECEIVER FOR LOW POWER HIGH SPEED INTERFACE

A pseudo-differential input receiver is disclosed which is configured to support a wide-range of reference voltage Vref and a wide-range frequency interface with no parallel termination are described herein. The pseudo-differential receiver implementations described herein are very efficient in terms of area, power, and performance. A wide-frequency-range Vref-adjustable input receiver is described herein. The receiver can be configured with a Vref-monitoring PMOS helper FET or an enabled stacked PMOS helper FET to enable the receiver to work at Vref=0V like a conventional CMOS receiver. The receiver can also be configured with a Vref-monitoring NMOS helper FET to enable a Vref-based input receiver to work with programmability on bias currents & trip-point at Vref=(0.5~0.7)Vdd, depending on the ratio of output driver's impedance and parallel on/off-die termination impedance.

Data communication device, data communication system, and data communication method

A data communication device performs stable data communications without a malfunction in a system downsized by realizing bi-directional data communications using two terminals. The data communication device includes: a signal terminal (IN) for inputting a received signal having portions of different duty ratios and a constant pulse frequency; a reference voltage terminal (GND) for inputting a first reference voltage; a clock generation circuit (11) for generating a clock signal according to the received signal; a data signal generation circuit (12) for generating a data signal by identifying a duty ratio of the received signal; a transmission circuit for outputting a transmission signal to the signal terminal; and a regulator circuit (14) for generating power supply voltages of the clock generation circuit, the data signal generation circuit, and the transmission circuit on a basis of an internally generated second reference voltage, the received signal, and the first reference voltage.

Analog macro embedded in digital gate array

ALTERNATING CURRENT STATIC CONTROL SYSTEM

DEVICE FORMING LOGICAL DOOR ADAPTEE TO DETECT A LOGICAL FAULT

La présente invention concerne un dispositif formant circuit électrique, caractérisé par le fait qu'il comprend des moyens logiques (30) générant et exploitant des signaux faibles de niveaux intermédiaires entre les niveaux d'alimentation dudit dispositif et des moyens de détection de signaux sortant de la gamme de tels signaux faibles.

SEMICONDUCTOR CIRCUIT

RECEIVER RESILIENT TO NOISE INPUT

Element controller for a resilient integrated circuit architecture

COMPILER SYSTEM, METHOD AND SOFTWARE FOR A RESILIENT INTEGRATED CIRCUIT ARCHITECTURE

The exemplary embodiments provide a compiler for a resilient integrated circuit. An exemplary IC comprises a plurality of composite circuit elements, a state machine element (SME), and a plurality of communication elements. Each composite circuit element comprises an element interface and a selected circuit element which may vary by element type, and which may be configurable. An exemplary compiler converts an algorithm into a plurality of tasks; assigns a task identifier to each task; determines an action, of a plurality of actions, corresponding to a first task of the plurality of tasks; assigns a first action identifier to a first action; maps the first action to a first type of composite computational element; determines a data input linkage or a data output linkage for the first action; and generates a compilation designating the first type of computational element and the data input linkage or the data output linkage for the first action. For fault tolerance and resilience, the compilation ...

Clocked charge domain logic

Advantageous digital logic cells and methods of powering logic blocks using the same are provided. A digital logic cell can include a charge storage device, a logic block, and connections to a power supply. The charge storage device may be a capacitor. The capacitor or other charge storage device can be disconnected from the logic block and a power supply to discharge the capacitor, and then connected to the power supply, via the power supply connections, to charge the capacitor. The capacitor can be disconnected from a ground connection of the power supply while the capacitor is discharged. After being charged via the power supply, the capacitor can also be disconnected from the power supply (including ground) and connected to the logic block to power the logic block.

Apparatus and method for reducing electromigration

An apparatus and method therefor wherein instead of applying a high bias voltage 100 per cent of the time to leads susceptible to dendrite formation, the bias voltage is switched from a low bias voltage to a high voltage bias mode when the leads (19) are to be read or scanned by a microprocessor (14), and the bias voltage is then switched back to a low bias voltage mode when the lines are not being read, e.g., at other times, thereby greatly reducing the high bias "on" time and dramatically reducing the probability of dendrite formation. The reduction of high bias voltage "on" time is accomplished by programming the microprocessor (14) to switch the applicable input ports (16) to be output ports when the leads (19) are not to be read. As output ports, the output impedance and output voltage of the microprocessor are low as opposed to a high input impedance when the terminals are input terminals. When the leads are configured as output leads, the voltage division of the microprocessor low ...

SYSTEMS AND METHODS FOR CONTROLLING SEMICONDUCTOR DEVICE WEAR

Systems, methods, and devices are provided for increasing uniformity of wear in semiconductor devices due to, for example, negative-bias temperature instability (NBTI). The method may include receiving a first NBTI control signal. The method may involve receiving a second NBTI control signal based at least in part on the first NBTI control signal. The method may also involve asserting the first NBTI control signal at a clock input pin of a latch. Further, the method may include asserting the second NBTI control signal at a data input pin of the latch. The method may additionally involve toggling electrical elements downstream of the latch based at least in part on an output of the latch based on the first and second NBTI control signals to increase uniformity of wear on the electrical elements in a default low-power state during NBTI toggling mode.

Timing violation resilient asynchronous template

An asynchronous circuit may include a single-rail logic datapath; one or more error-detecting latches; a controller that controls the error-detecting latches; and delay lines. The controller and the delay lines may cooperate to communicate with one or more other controllers that the output of the controlled error-detecting latches may be valid prior to when the error-detecting latches indicate whether or not an error occurred.

COMPONENT AUTHENTICATION UTILIZING MULTI-LEVEL ARBITER

A method for component authentication includes delaying an input signal along a first propagation path and a second propagation path, each propagation path including a same number of delay stages. A plurality of control inputs alters the first propagation path to include at least one delay stage from the second propagation path, and alters the second propagation path to include at least one delay stage from the first propagation path. A time difference between a first output of the first propagation path and a second output of the second propagation path is quantized into a plurality of time bins represented by a multi-bit output. The multi-bit output is transformed with a non-linear transform to provide a response output.

Semiconductor integrated circuit and method for controlling semiconductor integrated circuit

To improve a timing error detection accuracy in a semiconductor integrated circuit provided with storage devices operating in synchronization with a clock signal.A delay part delays a data signal by two mutually-different delay times and outputs it as first and second delay signals. A holding part holds the first and second delay signals in synchronization with a timing signal for giving an instruction on a predetermined capture timing. A setup time detection part detects whether or not one of the first and second delay signals held within a setup-time detection period from a predetermined start timing to the predetermined capture timing has changed. A hold time detection part detects whether or not the other of the first and second delay signals held within a hold-time detection period from the predetermined capture timing to a predetermined end timing has changed.

Receiver circuit with high input voltage protection

An integrated circuit 2 includes a receiver circuit 4 for receiving an input signal PAD and converting this to an output signal OUT. Conduction path circuitry 14 couples an input 10 to a first node 16 . Buffer circuitry 18 is coupled between the first node 16 and an output 12 carrying the output signal Out. The conduction path circuitry comprises a first PMOS transistor 24 and a second PMOS transistor 26 connected between the input 10 and the first node 16 . A first NMOS transistor 28 is connected between the input 10 and the first node 16 . The gate of the second PMOS transistor 26 is coupled to the output 12 to directly receive the output signal and thereby achieve rapid cut off of the charging of the node 16 when the input voltage rises beyond a certain level which switches the buffer circuitry 18.

Securing a Storage Element for a Binary Datum, Control Register and Chip Card

Securing a storage element for a binary datum, control register and chip card. This element ( 60 ) for storing a binary datum (D) inputs a signal representative of said binary datum, said storage to be carried out when an enable signal (ENA) is at a first predetermined level, supplies an output signal (Q) the state whereof represents the datum stored in said storage element ( 10 ), and detects an attack aimed at said enable signal (ENA) or at a signal internal to said storage element.

Method and apparatus for preventing circuit failure

An embedded decoupling capacitor wearout monitor for power transmission line, which can be integrated and fabricated in any standard CMOS or BiCMOS circuits. The embedded noise monitor is employed to detect the degraded capacitor and disable it from further operation, which will extend the operation lifetime of the circuit system and prevent subsequent catastrophic failure as a result of hard-breakdown (or capacitor short). In one aspect, the monitor circuit and method detects early degradation signal before catastrophic decoupling capacitor failure and, further can pin-point a degraded decoupling capacitor and disable it, avoiding impact from decoupling capacitor breakdown failure. The monitor circuit and method provides for decoupling capacitor redundancy and includes an embedded and self-diagnostic circuit for functionality and reliability.

Highly efficient class-d amplifier

A simplistic low cost circuit that generates the necessary drive voltage for use in a source follower totem pole power switching circuit is described where the simplified gate drive circuit may have a dual charge pump and a complementary pair of low-power switching Mosfets.

Identification circuit and method for generating an identification bit using physical unclonable functions

An embodiment of the present invention is an identification circuit installed on an integrated circuit for generating an identification bit, comprising a first circuit to generate a first output signal that is based on random parametric variations in said first circuit, a second circuit to generate a second output signal that is based on random parametric variations in said second circuit, a third circuit capable to be operated in an amplification mode and in a latch mode, wherein in said amplification mode the difference between the first output signal and the second output signal is amplified to an amplified value and, wherein in said latch mode said amplified value is converted into a digital signal.

Low Voltage Electrostatic Discharge Protection

A protection circuit for protecting components from an electrostatic discharge at a node in an integrated circuit having a first set of electronic components of a first voltage sensitivity, the protection circuit comprising: detection circuitry arranged to detect an electrostatic discharge at the node; a first switching device connected between the first set of components and the node; and a second switching device connected between the node and ground; wherein, when an electrostatic discharge is detected at the node, the first switching device is configured to isolate the first set of components from the node and the second switching device is configured to provide a current path from said node to ground.

Resilient Integrated Circuit Architecture

The exemplary embodiments provide a resilient integrated circuit. An exemplary IC comprises a plurality of composite circuit elements, a state machine element (SME), and a plurality of communication elements. Each composite circuit element comprises an element interface and a selected circuit element which may vary by element type, and which may be configurable. The state machine element assigns various functions based on element type, such as assigning a first configuration to a first element type, assigning a second configuration to a second element type, and providing a first data link for the corresponding assignments. In response to detection of a fault or failure, the state machine element re-assigns the first configuration to another composite circuit element and creates a second data link for performance of the same function. The assignment, routing, fault detection, and re-assignment and data re-routing can occur in real time for a wide variety of programs and algorithms, providing for the IC to continue the same functioning despite defects which may arise during operation.

Element Controller for a Resilient Integrated Circuit Architecture

The exemplary embodiments provide a resilient integrated circuit. An exemplary IC comprises a plurality of composite circuit elements, a state machine element (SME), and a plurality of communication elements. Each composite circuit element comprises an element controller, an element interface and a selected circuit element which may vary by element type, and which may be configurable. The state machine element assigns various functions based on element type, such as assigning a first configuration to a first element type, assigning a second configuration to a second element type, and providing a first data link for the corresponding assignments. The element controller controls the execution of data operations by the circuit element. Function assignment, routing, fault detection, and re-assignment and data re-routing can occur in real time for a wide variety of programs and algorithms, providing for the IC to continue the same functioning despite defects which may arise during operation.

Driver circuit and video system

In a driver circuit in a transmission system, an output circuit outputs a differential signal based on input data signals. A current source control circuit controls a constant current source so that a common-mode potential of the differential signal becomes equal to a predetermined reference potential. An overshoot reduction circuit is connected to an input line of the common-mode potential of the current source control circuit, and reduces an overshoot of the common-mode potential based on the control signal.

Electrical Circuit For Transmitting Signals Between Two Masters And One Or More Slaves

An electrical circuit for transmitting signals between two masters and one or more slaves is described. The two masters and the slave or slaves are connected to one another via a bus system. At least one master data signal can be generated by each of the two masters, which signal can be received by the slave or slaves. A three-state gate is present at each of the outputs of the two masters at which the respective master data signal is present. The three-state gates are effective either as closed or as open switches. The three-state gates are activated in such a way that the three-state gate associated with the one of the two masters acts as a closed switch, and the three-state gate associated with the other of the two masters acts as an open switch.

Coupling Circuit, Driver Circuit and Method for Controlling a Coupling Circuit

A coupling circuit has a first and a second transistor (P 1, P 2 ) of a p-channel field-effect transistor type. A drain terminal of the first transistor (P 1 ) is connected to a signal input ( 1 ), source terminals of the first and the second transistor (P 1, P 2 ) are commonly connected to a signal output ( 2 ), bulk terminals of the first and the second transistor (P 1, P 2 ) are commonly connected to a drain terminal of the second transistor (P 2 ), and a gate terminal of the first transistor (P 1 ) is connected to a gate terminal of the second transistor (P 2 ). The coupling circuit further comprises a gate control circuit ( 10 ) with a charge pump circuit ( 110 ) which is configured to generate a negative potential. The gate control circuit ( 10 ) is configured to control a gate voltage at the gate terminals of the first and the second transistor (P 1, P 2 ) based on a negative potential.

Semiconductor integrated circuit device

A high-speed semiconductor integrated circuit device is achieved by adjusting an offset voltage. For example, dummy NMOS transistors MND 1 (MND 1 a and MND 1 b ) and MND 2 (MND 2 a and MND 2 b ) are connected to drain outputs of NMOS transistors MN 1 and MN 2 operated according to differential input signals Din_p and Din_n, respectively. The MND 1 is arranged adjacent to the MN 1, and a source of the MND 1 a and a drain of the MN 1 share a diffusion layer. The MND 2 is arranged adjacent to the MN 2, and a source of the MND 2 a and a drain of the MN 2 share a diffusion layer. The MND 1 and the MND 2 function as dummy transistors for suppressing variations in process of the MN 1 and the MN 2 and, and besides, they also function as means for adjusting the offset voltage by appropriately applying an offset-amount setting signal OFST to each gate to provide a capacitor to either the MN 1 or the MN 2.

High definition multimedia interface (hdmi) apparatus including termination circuit

A termination circuit for a HDMI transmitter includes a bias unit and a termination resistor unit connected in parallel between a positive transmission pin and a negative transmission pin. The bias unit generates a bias voltage by selecting the higher voltage among a first voltage received through the positive transmission pin and a second voltage received through the negative transmission pin. The termination resistor unit is formed on a well region biased by the bias voltage, and conditionally provides a termination resistance between the positive transmission pin and the negative transmission pin in response to a termination resistor control signal. The termination circuit conditionally provides a termination resistance without a leakage current. The termination resistance may be varied by using an n-bit control code.

Methods and structures for electrostatic discharge protection

A semiconductor device includes a first well region of a first conductivity type, a second well region of a second conductive type within the first well region. A first region of the first conductivity type and a second region of the second conductivity type are disposed within the second well region. A third region of the first conductivity type and a fourth region of the second conductivity type are disposed within the first well region, wherein the third region and the fourth region are separated by the second well region. The semiconductor device also includes a switch device coupled to the third region.

Driver Calibration Methods and Circuits

Described are amplifiers that facilitate high-speed communication with calibrated drive strength and termination impedance. Drivers and termination elements can be divided into a number N of parallel portions, one or more of which can be disabled and updated without interfering with signal (e.g., clock or data) transmission. Some embodiments identify inactive elements by examining incoming signals.

(n-1)-out-of-n voter mux with enhanced drive

This disclosure describes voting circuits where an output is generated based on a plurality of inputs. A first plurality of logic paths connects the output to a high voltage. Each logic path of the first plurality of logic paths includes two transistors. A second plurality of logic paths connects the output to the low voltage. Each logic path of the second plurality of logic paths comprises two transistors. Based on N or N−1 of the inputs agreeing, the output is driven to either the low voltage or the high voltage via a subset of logic paths of the first and second plurality of logic paths.

Integrated Circuit Elementary Cell with a Low Sensitivity to External Disturbances

The present invention relates to an integrated electronic circuit including elements enabling to implement a logic function and means for attenuating the sensitivity of said elements to external disturbances, said attenuation means being disconnectable during phases of intentional modification of the state of said elements.

Countermeasure method and device for protecting data circulating in an electronic microcircuit

The disclosure relates to a countermeasure method in an electronic microcircuit, comprising successive process phases executed by a circuit of the microcircuit, and adjusting a power supply voltage between power supply and ground terminals of the circuit, as a function of a random value generated for the process phase, at each process phase executed by the circuit.

Active clamp circuit

According to one embodiment, an active clamp circuit includes a first switch element, a first diode, a first resistance, a first control circuit and a second control circuit. The first diode is connected to the first switch element and breaks down by an overvoltage applied to the first switch element. The first resistance is connected to the first diode and detects a current through the first diode. The first control circuit is configured to amplify a voltage across the first resistance and controls a current through the first switch element. The second control circuit is configured to control a conduction of the first switch element in accordance with the voltage across the first resistance.

SIGNAL PROCESSING SYSTEM

A signal route of a PUF (Physical Uncloneable Function) circuit is configured in each device. The signal route of each device is connected by a connection route to form a transmission route. An arbiter is connected at the end of the transmission route. A signal is transmitted in the transmission route from a device to a device. The arbiter monitors the signal passed through the transmission route, and generates an output signal reflecting a characteristic unique to the transmission route, based on monitoring results. The authentication of identity among a combination of a plurality of devices is enabled by examining the output signal. 16-. (canceled)7. A signal processing system including a plurality of devices arranged in sequence on a predetermined substrate , comprising:a signal route of a PUF (Physical Uncloneable Function) circuit configured in each of the plurality of devices, the PUF circuit including the signal route through which signals flow, and an output signal generation circuit which terminates the signal route, monitors the signals passed through the signal route, and generates an output signal reflecting a characteristic unique to the signal route based on monitoring results of the signals passed through the signal route; anda connection route that connects the signal route in each device to the signal route in a subsequent device, and is formed by a wire on the substrate;wherein:the signal routes in the plurality of devices and the connection route between each device forms a transmission route,the signal processing system further comprising:the output signal generation circuit of the PUF circuit that is disposed in the last device in sequence of the plurality of devices, and terminates the transmission route,wherein:predetermined signals flow through the transmission route in accordance with a sequence of devices, and are inputted by the output signal generation circuit in the last device in sequence, andthe output signal generation circuit in the ...

Integrated circuit having latch-up recovery circuit

An integrated circuit includes first and second transistors, a switch, and a power-on reset (POR) circuit. The first transistor has a first current electrode, a second current electrode, and a control electrode. The second transistor has a first current electrode coupled to the second current electrode of the first transistor, a second current electrode, and a control electrode. The switch is for coupling the first and second transistors to receive a power supply voltage in response to an asserted bias control signal. The POR circuit has a latch-up detection circuit coupled to receive the power supply voltage and to a control terminal of the switch. The latch-up detection circuit is for detecting a low voltage condition of the power supply voltage, and in response, deasserting the bias control signal to decouple the first and second transistors from the power supply voltage.

Output buffer, operating method thereof and devices including the same

A method of buffering data from core circuitry includes generating a first sourcing control signal responsive to indication signals indicating an operating voltage and output data, generating a second sourcing control signal responsive to the indication signals, and applying the operating voltage to an output terminal in response to the first sourcing control signal and the second sourcing control signal. The first sourcing control signal swings between the operating voltage and a reference voltage. The reference voltage is a signal selected from among a plurality of internal voltages in response to selection signals generated as a result of decoding the indication signals.

Fault Tolerant Integrated Circuit Architecture

The exemplary embodiments provide a resilient integrated circuit. An exemplary IC comprises a plurality of composite circuit elements, a state machine element (SME), and a plurality of communication elements. Each composite circuit element comprises an element interface and a selected circuit element which may vary by element type, and which may be configurable. The state machine element assigns various functions based on element type, such as assigning a first configuration to a first element type, assigning a second configuration to a second element type, and providing a first data link for the corresponding assignments. In response to detection of a fault or failure, the state machine element re-assigns the first configuration to another composite circuit element and creates a second data link for performance of the same function. The assignment, routing, fault detection, and re-assignment and data re-routing can occur in real time for a wide variety of programs and algorithms, providing for the IC to continue the same functioning despite defects which may arise during operation. 1. An apparatus comprising:a communication element;a plurality of composite circuit elements coupled to the communication element, each composite circuit element comprising a uniform element interface and a circuit element of a plurality of circuit element types, a first composite circuit element of the plurality of composite circuit elements having a first action, a second composite circuit element of the plurality of composite circuit elements having a second action, a third composite circuit element of the plurality of composite circuit elements having the first action, wherein the second composite circuit element has a programmable first data link to the first composite circuit element for performance of a first function or has an programmable second data link to the third composite circuit element for performance of the first function.2. The apparatus of claim 1 , further comprising ...

SYSTEMS AND METHODS OF INTEGRATED CIRCUIT CLOCKING

Various systems and methods are provided for integrated circuit clocking. In one embodiment, an integrated circuit system includes a plurality of combinational logic groups, each combinational logic group having a propagation time; and means for delaying a synchronizing clock signal supplied to at least one of the plurality of combinational logic groups based upon a period of the synchronizing clock signal and the propagation time of the at least one combinational logic group. In another embodiment, a method includes delaying a clock signal to produce a delayed clock signal and communicating the clock signal and the delayed clock signal to separate groups of the combinational logic circuit during a clock cycle that results in a reduction in power consumption by the combinational logic circuit. 1. An integrated circuit system , comprising:a combinational logic group including combinational logic having a maximum propagation time within a propagation range associated with the combinational logic group;a controllable clock delay element configured to provide a delayed clock signal to the combinational logic group; anda delay controller configured to control the delayed clock signal of the clock delay element based upon a clock signal period of a synchronizing clock signal and upon a propagation time of the combinational logic group.2. The integrated circuit system of claim 1 , wherein the propagation time of the combinational logic group comprises propagation delay of a critical path of the combinational logic group.3. The integrated circuit system of claim 1 , wherein the propagation time of the combinational logic group comprises propagation delay along a digital logic path associated with the combinational logic group.4. The integrated circuit system of claim 3 , wherein propagation delay along the digital logic path accounts for IC bus resistance and inductance.5. The integrated circuit system of claim 3 , wherein propagation delay along the digital logic path ...

Switching circuit

A switching circuit suitable for a low power oscillator circuit includes control and output circuits, the control circuit arranged to control the output circuit, the control circuit having input and output terminals, the output circuit having input and output terminals and control terminals; wherein the input terminal of the control circuit is connected to the input terminal of the output circuit, and the control terminal of the output circuit is connected to the output terminal of the control circuit, the output circuit first switches connected in series and arranged such that in use at least one of the switches is in a low impedance state at any given time, and the control circuit has second switches connected in series and arranged such that in use at least one of the switches is in a low impedance state at any given time.

MEMORY CIRCUIT INCORPORATING RADIATION-HARDENED MEMORY SCRUB ENGINE

An example integrated circuit includes a first memory array including a first plurality of data groups, each such data group including a respective plurality of data bits. The integrated circuit also includes a first error detection and correction (EDAC) circuit configured to detect and correct an error in a data group read from the first memory array. The integrated circuit also includes a first scrub circuit configured to access in a sequence each of the first plurality of data groups to correct any detected errors therein. Both the first EDAC circuit and the first scrub circuit include spatially redundant circuitry. The first EDAC circuit and the first scrub circuit may include buried guard ring (BGR) structures, and may include parasitic isolation device (PID) structures. The spatially redundant circuitry may include dual interlocked storage cell (DICE) circuits, and may include temporal filtering circuitry. 1. An integrated circuit comprising:a first memory array comprising a first plurality of data groups, each such data group including a respective plurality of data bits;a first error detection and correction (EDAC) circuit configured to detect and correct an error in a data group read from the first memory array, said first EDAC circuit comprising spatially redundant circuitry; anda first scrub circuit configured to access in a sequence each of the first plurality of data groups to correct any detected errors therein, said first scrub circuit comprising spatially redundant circuitry.2. The integrated circuit as recited in wherein:the first EDAC circuit and the first scrub circuit each includes buried guard ring (BGR) structures.3. The integrated circuit as recited in wherein:the first EDAC circuit and the first scrub circuit each includes parasitic isolation device (PID) structures.4. The integrated circuit as recited in wherein:the spatially redundant circuitry comprises dual interlocked storage cell (DICE) circuits.5. The integrated circuit as recited in ...

System and method for reducing input current spike for drive circuitry

A circuit includes a plurality of logic gates and a drive circuit. The plurality of logic gates are coupled between a first supply node and a second supply node. Each logic gate has at least one input and consumes a short circuit current during a logic state transition. The drive circuit is coupled to the inputs of the plurality of logic gates to deliver a copy of an input signal to each logic gate, wherein the input signal copies arrive at the inputs of the logic gates at substantially different times. The circuit may be incorporated in a touch screen panel and a display.

GATE-STRESS TEST CIRCUIT WITHOUT TEST PAD

A high side driver circuit includes a driver stage having an input, an output, a first power terminal and a second power terminal, a transistor having a first power terminal, a second power terminal, and a control terminal coupled to the output of the driver stage, and a switch coupled between the second power terminal of the driver stage and the second power terminal of the transistor. 1. A high side driver circuit comprising:a driver stage having an input, an output, a first power terminal and a second power terminal;a transistor having a first power terminal, a second power terminal, and a control terminal coupled to the output of the driver stage; anda switch coupled between the second power terminal of the driver stage and the second power terminal of the transistor.2. The high side driver circuit of further comprising a diode coupled between the first power terminal of the driver stage and a voltage source.3. The high side driver circuit of claim 1 , wherein the transistor comprises a power MOS transistor.4. The high side driver circuit of claim 1 , wherein the switch is controlled by a gate stress control signal.5. A method of operating a driver circuit comprising:providing a driver stage having an input, an output, a first power terminal and a second power terminal;providing a transistor having a first power terminal, a second power terminal, and a control terminal coupled to the output of the driver stage; andproviding a switch coupled between the second power terminal of the driver stage and the second power terminal of the transistor.6. The method of further comprising claim 5 , in a normal operating mode claim 5 , opening the switch.7. The method of further comprising claim 5 , in a test mode claim 5 , closing the switch.8. The method of further comprising performing a first leakage current measurement at the first power terminal of the driver stage.9. The method of further comprising stressing the transistor.10. The method of further comprising ...

Gate driver with digital ground

Various exemplary embodiments relate to gate driver circuitry that compensate for parasitic inductances. Input buffers in the gate driver are grounded to an exposed die pad. Grounding may involve either a downbond or conductive glue.

DATA INTERFACE HAVING AN INTRINSICALLY SAFE, INTEGRATED ERROR DETECTION

An intrinsically safe digital circuit has at least two output signals and at least four input signals for detecting a potential error in the circuit and/or in one of its input signals, the at least four input signals forming two input signal pairs inverted in a double-track manner, and the at least two output signals forming an output signal pair inverted in a double-track manner. The output signal pair transmits a piece of information which is identical to the one of an input signal pair, when the error is not present. 16-. (canceled)7. An intrinsically safe digital circuit , comprising:means for receiving at least four input signals; andmeans for generating at least two output signals;wherein the at least four input signals form two input signal pairs inverted in a double-track manner, and the at least two output signals form an output signal pair inverted in a double-track manner, and wherein a potential error in at least one of the digital circuit and the input signals is able to be detected such that the output signal pair transmits an information item which is identical to one of the two input signal pairs when a potential error in at least one of the digital circuit and the input signals is not present.8. The intrinsically safe digital circuit as recited in claim 7 , wherein at least one additional output signal which is not used for error detection is generated claim 7 , and wherein the information item transmitted by the output signal pair is a parity piece of information of the at least one additional output signal.9. The intrinsically safe digital circuit as recited in claim 8 , wherein:the circuit internally has at least one doubled intrinsically safe digital subcircuit inverted in a double-track manner for detecting an error in at least one of (i) a first binary input signal pair including a first input signal and a second input signal, and (ii) a second binary input signal pair including a third input signal and a fourth input signal;the output signal ...

ENHANCED PERFORMANCE MEMORY SYSTEMS AND METHODS

Digital memory devices and systems, including memory systems and methods for operating such memory systems are disclosed. In the embodiments, a memory system may include a processor and a memory controller communicatively coupled to the processor. A memory bus communicates with at least two memory units through the memory bus. At least one divider unit may be interposed between the memory bus and the at least two memory units that is configured to approximately equally divide levels of received signals while matching an impedance of the memory bus to an impedance of the memory units. 1. A method of operating a memory system , the method comprising:adjusting a divider unit that is interposed between a memory bus and at least two memory units of the memory system to match an impedance of the at least two memory units to an impedance of the memory bus responsive to receiving address information of the at least two memory units.2. The method of claim 1 , further comprising dividing signal levels communicated along the memory bus to the at least two memory units by the divider unit so that approximately equivalent signal levels are transferred to the at least two memory units.3. The method of claim 2 , further comprising providing isolation between the signal levels by the divider unit.4. The method of claim 1 , wherein adjusting the divider unit comprises adjusting an impedance network of the divider unit.5. The method of claim 4 , wherein the impedance network of the divider unit comprises a wye-coupled network.6. The method of claim 4 , wherein the impedance network of the divider unit comprises a delta-coupled network.7. The method of claim 1 , wherein receiving the address information of the at least two memory units comprises receiving a particular address within one of the at least two memory units claim 1 , the particular address being a location where data is to be written to or read from.8. A method of configuring a memory system claim 1 , comprising:providing ...

SEQUENTIAL CIRCUIT WITH CURRENT MODE ERROR DETECTION

A sequential circuit with transition error detector including a sequential element with an input that is asserted to the output during the second clock phase of a two phase clock signal, a transition error detector coupled to the sequential element input to assert an error signal if a transition occurs at the sequential element input during the second clock phase but not to assert during the first clock phase, wherein a transition error detection circuit comprises a current mode circuit as a detection circuit for transition timing error detection from signals derived from the sequential element clock signal and input signals. 1. A sequential circuit with transition error detector comprising: a sequential element with an input that is asserted to the output during the second clock phase of a two phase clock signal , a transition error detector coupled to the sequential element input to assert an error signal if a transition occurs at the sequential element input during the second clock phase and not to assert the error signal during the first clock phase , wherein a transition error detection circuit coming comprises a current mode circuit as a detection circuit for transition timing error detection from signals derived from the sequential element clock signal and input signals.2. The sequential circuit of comprising a further delay line for generating delayed versions of the sequential element input signal for the detection circuit and a delay for generating a delayed clock for the detection circuit.3. The sequential circuit of claim 1 , wherein the current mode transition detection circuit comprises a differential transistor circuit.4. The sequential circuit of claim 3 , wherein the transition detection circuit comprises a source coupled current mode logic.5. The sequential circuit of claim 4 , wherein the transition detection circuit comprises a subthreshold source coupled current mode logic.6. The sequential circuit of claim 1 , wherein the sequential element ...

TERMINAL DEVICE AND METHOD FOR REALIZING ANALOGUE CIRCUIT IN TERMINAL DEVICE

Disclosed are a terminal device and a method for realizing an analogue circuit in the terminal device. The terminal device includes control device and programmable analogue circuit device. The control device includes: acquisition module, configured to acquire the configuration data information corresponding to the function index and the parameter index of a target analogue circuit, wherein the configuration data information is configured to indicate the on/off state of an interconnection switch between CABs; downloading module, configured to download the configuration data information to the programmable analogue circuit device; and restart module, configured to restart the programmable analogue circuit device. The programmable analogue circuit device includes: a configurable analogue array module, configured to configure the parameters and/or the connection relationship of the CABs by using the configuration data information. The disclosure enhances the fault tolerance of the system, and improves the resource utilization rate. 1. A terminal device , comprising a control device and a programmable analogue circuit device , whereinthe control device comprises: an acquisition module, configured to acquire configuration data information corresponding to a function index and a parameter index of a target analogue circuit, wherein the configuration data information is configured to indicate on/off state of an interconnection switch between Configurable Analogue Blocks (CABs); a downloading module, configured to download the configuration data information to the programmable analogue circuit device; and a restart module, configured to restart the programmable analogue circuit device; andthe programmable analogue circuit device comprises: a configurable analogue array module, configured to configure a parameter and/or a connection relationship of the CABs by using the configuration data information.2. The terminal device according to claim 1 , wherein the acquisition module ...

Semiconductor integrated circuit

A semiconductor integrated circuit includes a bypass circuit that forms a bypass path under a low voltage condition, and the bypass circuit includes first and second bypass MOS transistors respectively placed between drains of first and second PMOS transistors and a ground voltage terminal, each transistor having a gate to which a second power supply voltage is applied, and third and fourth bypass MOS transistors respectively placed between the first and second bypass MOS transistors and the ground voltage terminal, each transistor controlled to be ON and OFF in accordance with an input signal and a voltage condition.

Resilient Integrated Circuit Architecture

The exemplary embodiments provide a resilient integrated circuit. An exemplary IC comprises a plurality of composite circuit elements, a state machine element (SME), and a plurality of communication elements. Each composite circuit element comprises an element interface and a selected circuit element which may vary by element type, and which may be configurable. The state machine element assigns various functions based on element type, such as assigning a first configuration to a first element type, assigning a second configuration to a second element type, and providing a first data link for the corresponding assignments. In response to detection of a fault or failure, the state machine element re-assigns the first configuration to another composite circuit element and creates a second data link for performance of the same function. The assignment, routing, fault detection, and re-assignment and data re-routing can occur in real time for a wide variety of programs and algorithms, providing for the IC to continue the same functioning despite defects which may arise during operation.

FLOATING GATE DRIVER WITH BETTER SAFE OPERATION AREA AND NOISE IMMUNITY, AND METHOD FOR LEVEL SHIFTING A SWITCH SIGNAL

A floating gate driver includes a level shifter to transmit a set signal and a reset signal to a first output terminal and a second output terminal, respectively. The level shifter includes a first high-voltage transistor, a first current limiter and a first input transistor connected in series between the first output terminal and a ground terminal, and a second high-voltage transistor, a second current limiter and a second input transistor connected in series between the second output terminal and the ground terminal, and the first and second high-voltage transistors are remained on. With this arrangement, the level shifter can transmit signals from low side to high side under better safe operating area and has better noise immunity. 1. A floating gate driver , comprising:an edge pulse generator detecting a rising edge and a falling edge of a switch signal to trigger a set signal and a reset signal, respectively;a level shifter having a first input transistor and a second input transistor connected to the edge pulse generator for transmitting the set signal and the reset signal to a first output terminal and a second output terminal to generate a first negative voltage pulse and a second negative voltage pulse, respectively; anda logic regeneration circuit connected to the first output terminal and the second output terminal, responsive to the first negative voltage pulse and the second negative voltage pulse to generate a signal as being level shifted from the switch signal; a first high-voltage transistor and a second high-voltage transistor connected to the first output terminal and the second output terminal, respectively, and remained on;', 'a first current limiter connected between the first high-voltage transistor and the first input transistor; and', 'a second current limiter connected between the second high-voltage transistor and the second input transistor., 'wherein the level shifter further comprises2. The floating gate driver of claim 1 , wherein ...

Hysteresis-Based Latch Design for Improved Soft Error Rate with Low Area/Performance Overhead

A hysteresis-based logic element design for improved soft error rate with low area/performance overhead. In one embodiment, a hysteresis inverter block including one or more pairs of inverters can be coupled to a logic element to adjust a switching threshold of the logic element. 1. A logic apparatus , comprising: a first inverter having an input and an output, said input being coupled to said input of said logic block, said output being coupled to said output of said logic block, and', 'a digital logic component having an input and an output, said input of said digital logic component being coupled to said output of said first inverter, said output of said digital logic component being coupled to said input of said first inverter; and', 'an inverter block, said inverter block including one or more pairs of inverters, said one or more pairs of inverters being sequentially connected to form a loop, said loop of one or more pairs of inverters being coupled to one of said input and said output of said first inverter., 'a logic block having an input for receiving data and an output for producing data that has been stored in said logic block, said logic block including,'}2. The logic apparatus of claim 1 , wherein said digital logic component is a second inverter.3. The logic apparatus of claim 1 , wherein said digital logic component is a NAND gate having a second input for receiving a reset signal.4. The logic apparatus of claim 1 , wherein said inverter block includes one pair of inverters.5. The logic apparatus of claim 4 , wherein each of said inverters in said inverter block is smaller than said first inverter.6. The logic apparatus of claim 1 , wherein said inverter block includes two or more pairs of inverters.7. The logic apparatus of claim 1 , wherein said inverter block includes a transmission gate in said loop claim 1 , said transmission gate being responsive to an inverse of a clock signal that controls an application of data at said input of said logic ...

SCAN FLIP-FLOP CIRCUITS AND SCAN TEST CIRCUITS INCLUDING THE SAME

A scan flip-flop circuit includes an input unit and an output unit. The data output unit is configured to provide a data output terminal with a data output signal in response to a data input signal and a first control signal in a first operation mode, and the data output unit is configured to prohibit the data output terminal from being provided with a power supply voltage and a ground voltage applied to the scan flip-flop circuit in response to the data input signal and the first control signal in a second operation mode. The scan output unit is configured to provide a scan output terminal with a scan output signal in response to a scan input signal and a second control signal in the second operation mode. 120-. (canceled)21. A scan flip-flop circuit comprising:a data output unit configured to provide a data output terminal with a data output signal in response to a data input signal and a first control signal in a first operation mode, and the data output unit configured to prohibit the data output terminal from being provided with a power supply voltage and a ground voltage applied to the scan flip-flop circuit in response to the data input signal and the first control signal in a second operation mode; anda scan output unit configured to provide a scan output terminal with a scan output signal in response to a scan input signal and a second control signal in the second operation mode.22. The scan flip-flop circuit of claim 21 , wherein data output terminal is configured to output a voltage unidirectionally transitioning between a first voltage level and a second voltage level in the second operation mode claim 21 , and scan output terminal is configured to output a voltage level unidirectionally transitioning between the first voltage level and the second voltage level in the first operation mode.23. The scan flip-flop circuit of claim 21 , wherein the scan output unit is configured to prohibit the scan output terminal from being provided with the power supply ...

SEMICONDUCTOR DEVICE AND INPUT SIGNAL RECEPTION CIRCUIT

A semiconductor device according to the present invention includes an input circuit that is connected between an input node and an output node and that changes a level of the output node corresponding to a signal supplied to the input node, wherein when a control signal represents a first mode, a speed at which input circuit changes the level of the output node from a first level to a second level is greater than the speed at which input circuit changes the level of the output node from the second level to the first level and when the control signal represents a second mode, the speed at which input circuit changes the level of the output node from the second level to the first level is greater than the speed at which the input circuit changes the level of the output node from the first level to the second level. 1. A semiconductor device comprising:an input circuit that is connected between an input node and an output node and that changes a level of said output node corresponding to a signal supplied to said input node,wherein when a control signal represents a first mode, a speed at which said input circuit changes the level of said output node from a first level to a second level is greater than a speed at which said input circuit changes the level of said output node from said second level to said first level and when said control signal represents a second mode that is different from said first mode, the speed at which said input circuit changes the level of said output node from said second level to said first level is greater than the speed at which said input circuit changes the level of said output node from said first level to said second level.2. The semiconductor device according to claim 1 ,wherein said input circuit has a differential amplification circuit.3. The semiconductor device according to claim 2 ,wherein said differential amplification circuit has two terminals, one terminal being connected to said input node, a reference voltage being ...

Semiconductor device and information processing apparatus

A semiconductor device including an input terminal to receive an input signal and an output terminal to output an output signal includes delay elements connected in series with the input terminal and each to assign the delay to the input signal input from the input terminal, selectors connected to output sides of the delay elements and each to select one of output signals of the delay elements based on a selection signal for selecting the one of the output signals of the delay elements to return the selected one of the output signals to the output terminal, and delay circuits disposed corresponding to the selectors and each to cause switching of the selection signal input into a corresponding one of the selectors to occur after switching of a signal level of the input signal input into the corresponding one of the selectors serving as a signal turning point.

SOFT ERROR RESILIENT FPGA

A field programmable gate array (FPGA) includes configuration RAM (CRAM) including at least one non-hardened portion and at least one hardened portion having an SER resilience greater than an SER resilience of the non-hardened portion. 1. A field programmable gate array (FPGA) , comprising:configuration RAM (CRAM) including at least one non-hardened portion and at least one hardened portion having a soft error (SER) resilience greater than an SER resilience of the non-hardened portion.2. The FPGA of claim 1 , wherein the hardened portion is static random access memory (SRAM) and the hardened portion includes interleaved SRAM error correction coding (ECC) bits.3. The FPGA of claim 2 , wherein the non-hardened portion is SRAM and does not include interleaved SRAM ECC bits.4. The FPGA of claim 2 , wherein the hardened portion is formed as silicon on insulator (SOI) and includes in-line stacked transistors.5. The FPGA of claim 4 , wherein the non-hardened portion is not formed as SOI and does not include in-line stacked transistors.6. The FPGA of claim 1 , wherein the hardened portion comprises at least one SER tolerant device claim 1 , and the non-hardened portion does not include an SER tolerant device.7. The FPGA of claim 6 , wherein the SER tolerant device includes at least one of embedded dynamic random access memory (EDRAM) claim 6 , flash memory claim 6 , hardened latches claim 6 , and fuses.8. The FPGA of claim 1 , wherein memory cells of the hardened portion include hardened memory cells comprising pairs of interlocked memory cells claim 1 , and memory cells of the non-hardened portion do not include the hardened memory cells.9. The FPGA of claim 1 , wherein the hardened portion comprises half-hardened CRAM cells. This application is a divisional of U.S. patent application Ser. No. 13/352,900, filed Jan. 18, 2012, the disclosure of which is incorporated by reference herein in its entirety.The present invention relates to field programmable gate arrays (FPGAs), ...

Implementing voltage feedback gate protection for cmos output drivers

A method and circuit for implementing protection for complementary metal oxide semiconductor (CMOS) output drivers, and a design structure on which the subject circuit resides are provided. An output driver stage transistor stack includes a plurality of series connected PFETs series connected with a plurality of series connected NFETs connected between upper and lower voltage supply rails. A pair of offset DC voltage levels provides respective gate voltages of an intermediate PFET and an intermediate NFET in the output driver stage transistor stack. A pair of pre-driver circuits receiving voltage level translated logic signals drive respective gate inputs of the upper PFET and the lower NFET in the output driver stage transistor stack. A voltage feedback circuit provides respective gate voltages of the PFET and NFET connected together in the output driver stage transistor stack.

Channel skewing

Methods and systems for channel skewing are described. One or more methods for channel skewing includes providing a number of groups of data signals to a memory component, each of the number of groups corresponding to a respective channel, and adjusting a phase of a group of data signals corresponding to at least one of the number of channels such that the group of data signals are skewed with respect to a group of data signals corresponding to at least one of the other respective channels.

HOMOGENEOUS DUAL-RAIL LOGIC FOR DPA ATTACK RESISTIVE SECURE CIRCUIT DESIGN

Homogenous dual-rail logic for DPA attack resistive secure circuit design is disclosed. According to one embodiment, an HDRL circuit comprises a primary cell and a complementary cell, wherein the complementary cell is an identical duplicate of the primary cell. The HDRL circuit comprises a first set of inputs and a second set of inputs, wherein the second set of inputs are a negation of the first set of inputs. The HDRL circuit has a differential power at a level that is resistive to DPA attacks. 119-. (canceled)20. A method , comprising:inputting a first input to an individual one of one or more primary cells of a circuit, the circuit comprising one or more primary cells and a complementary cell positioned adjacent to the individual one of the one or more primary cells, wherein the complementary cell is a duplicate of the individual one of the one or more primary cells; andinputting a second input to the complementary cell, wherein the second input is a negation of the first input.21. The method of claim 20 , wherein the circuit has a differential power at a level that is resistive to DPA attacks.22. The method of claim 21 , wherein the differential power is a power consumption of the circuit.23. The method of claim 20 , wherein the complementary cell and primary cell share the same VSS and VDD.24. The method of claim 20 , wherein the circuit is includable into a cryptographic module that implements an algorithm selected from the group consisting of AES claim 20 , Blowfish claim 20 , DES claim 20 , Triple DES claim 20 , Serpent claim 20 , Twofish claim 20 , Camellia claim 20 , CAST-128 claim 20 , IDEA claim 20 , RC2 claim 20 , RC5 claim 20 , SEED claim 20 , Skipjack claim 20 , TEA claim 20 , and XTEA.25. The method of claim 20 , wherein the primary cell is selected from the group consisting of an AND cell claim 20 , an OR cell claim 20 , an XOR cell claim 20 , an XNOR cell claim 20 , and a NOT cell.26. The method of claim 20 , wherein the primary cell is any ...

BIT GENERATION APPARATUS AND BIT GENERATION METHOD

A bit generation apparatus includes a glitch generation circuit that generates glitch signals which include a plurality of pulses, and T-FF bit generation circuits which input the glitch signals, and based on either rising edges or falling edges of the plurality of pulses included in the glitch signals, generate a bit value of either 0 or 1. Each of the T-FF bit generation circuits generates a respective bit value based on either the parity of the number of rising edges or the parity of the number of falling edges of the plurality of pulses. As a result of employment of the T-FF bit generation circuits, circuits that are conventionally required but not essential for the glitch become unnecessary. This serves to prevent expansion in circuit scale and increase in processing time of bit generation for the bit generation circuit. 111-. (canceled)12. A bit generation apparatus comprising:a glitch generation section that generates a glitch signal including a plurality of pulses;a filter section configured to include series-connected N semiconductor devices (N is an integer of two or more), a first semiconductor device to an N-th semiconductor device, the filter section inputting via the first semiconductor device the glitch signal generated by the glitch generation section, removing a pulse whose width is less than a predetermined pulse width, by allowing the inputted glitch signal to pass through the first semiconductor device to the N-th semiconductor device, and outputting via the N-th semiconductor device the glitch signal from which the pulse whose width is less than the predetermined pulse width has been removed; anda bit value generation section that inputs the glitch signal outputted by the filter section, and generates a bit value of 0 or 1 based on rising edges or falling edges of the plurality of pulses included in the inputted glitch signal.13. The bit generation apparatus according to claim 12 , wherein the filter section is configured to include series- ...

FUEL DISPENSER INPUT DEVICE TAMPER DETECTION ARRANGEMENT

A system for detecting unauthorized removal or tampering. The system comprises a printed circuit board having tamper-response electronics and a flexible circuit assembly defining a connector portion, a switch portion, and a cable extending between the connector portion and the switch portion. The flexible circuit assembly is coupled with the printed circuit board at the connector portion. The flexible circuit assembly comprises a plurality of layers each comprising a flexible dielectric substrate and a switch disposed in the switch portion. The switch is in electrical communication with the tamper-response electronics of the printed circuit board via a conductive path. The flexible circuit assembly also comprises a tamper-responsive conductor circuit enclosing the conductive path. The tamper-responsive conductor circuit is in electrical communication with the tamper-response electronics of the printed circuit board. 1. A system for detecting unauthorized removal or tampering , said system comprising:a printed circuit board having tamper-response electronics; anda flexible circuit assembly defining a connector portion, a switch portion, and a cable extending between said connector portion and said switch portion, said flexible circuit assembly coupled with said printed circuit board at said connector portion; a plurality of layers each comprising a flexible dielectric substrate;', 'a switch disposed in said switch portion, said switch in electrical communication with said tamper-response electronics of said printed circuit board via a conductive path; and', 'a tamper-responsive conductor circuit enclosing said conductive path, said tamper-responsive conductor circuit in electrical communication with said tamper-response electronics of said printed circuit board., 'said flexible circuit assembly comprising2. The system of claim 1 , wherein said switch claim 1 , said conductive path claim 1 , and said tamper-response electronics comprise a removal detection circuit ...

Program Binding System, Method and Software for a Resilient Integrated Circuit Architecture

The exemplary embodiments provide a program binder for a resilient integrated circuit. An exemplary IC comprises a plurality of composite circuit elements, a state machine element (SME), and a plurality of communication elements. Each composite circuit element comprises an element interface and a selected circuit element which may vary by element type, and which may be configurable. An exemplary program binding method includes assigning a first action to a first computational element having a first type; assigning a second action to a second computational element having a second type; and establishing a first data routing, through a selected communication element, between the first computational element and the second computational element. In the event of detection of a fault with a composite circuit element or a communication element, the various actions may be re-assigned and new data routings established.

TAMPER RESISTANT IC

According to an aspect of the invention an integrated circuit is conceived which comprises a physical unclonable function which is at least partially implemented in a passivation layer of said integrated circuit. According to a further aspect of the invention, a corresponding method for manufacturing an integrated circuit is conceived. According to a further aspect of the invention, an electronic device is conceived which comprises an integrated circuit of the kind set forth. 1. (canceled)2. (canceled)3. (canceled)4. (canceled)5. (canceled)6. (canceled)7. A method for manufacturing an integrated circuit comprising implementing a physical unclonable function at least partially in a passivation layer of said integrated circuit comprising:(a) providing a basic structure which comprises a pad for external connections, internal connections and PUF detector connections;(b) covering the basic structure, except the PUF detector connections, with photoresist layer;(c) randomly distributing conducting particles over the entire resulting surface;(d) removing the photoresist layer such that only the particles which are substantially above the PUF detector connections remain on the surface;(e) depositing the passivation layer on all elements except the pad for the external connections.8. (canceled)9. A method for manufacturing an integrated circuit as claimed in claim 7 , wherein the randomly distributed conducting particles comprise aluminum.10. (canceled)11. (canceled)12. (canceled)13. An integrated circuit comprising a portion produced by the method as claimed in .14. An integrated circuit as claimed in claim 13 , the integrated circuit being arranged to evaluate the physical unclonable function by determining which of the PUF detector connections are shorted by the particles claim 13 , and wherein the integrated circuit is further arranged to produce a corresponding evaluation result.15. An integrated circuit as claimed in claim 14 , wherein the integrated circuit is ...

TEST SYSTEM AND LOGIC SIGNAL VOLTAGE LEVEL CONVERSION DEVICE

A test system includes a logic signal voltage level conversion device, a first integrated circuit board, a second integrated circuit board, and a test device. The logic signal voltage level conversion device is connected to the first integrated circuit board, the second integrated circuit board, and the test device. When the first integrated circuit board is tested, the logic signal voltage level conversion device converts voltage levels of logic signals transmitted between the first integrated circuit board and the test device, to enable the first integrated circuit board to communicate with the test device. When the second integrated circuit board is tested, the logic signal voltage level conversion device converts voltage levels of logic signals transmitted between the second integrated circuit board and the test device, to enable the second integrated circuit board to communicate with the test device. 1. A logic signal voltage level conversion device , to convert voltage levels of logic signals transmitted between a first integrated circuit board and a test device , and convert voltage levels of logic signals transmitted between a second integrated circuit board and the test device , the logic signal voltage level conversion device comprising:a first conversion unit connected to the first integrated circuit board;a second conversion unit connected to the second integrated circuit board; anda switch unit connected to the first conversion unit, the second conversion unit, and the test device;wherein the switch unit enables the test device to communicate with the first conversion unit in response to the first integrated circuit board being tested, and enables the test device to communicate with the second conversion unit in response to the second integrated circuit board being tested;wherein the first conversion unit converts voltage level of a first logic signal outputted from the test device to enable the first logic signal to be identified by the first ...

MAJORITY DOMINANT POWER SCHEME FOR REPEATED STRUCTURES AND STRUCTURES THEREOF

Methods and structures for configuring an integrated circuit including repeated cells that are divided into banks having a respective power assist and a respective operational assist are provided. A method includes configuring the banks without power assist and operational assist. The method further includes selecting the power assist for a bank based on a determination that a weak cell remains in the bank after configuring the bank with the respective operational assist. 1. A method for repairing and tuning an integrated circuit comprising:determining that a first bank of a plurality of banks of repeated structures in the integrated circuit includes a failure;determining that the failure of the first bank cannot be repaired; andconfiguring the first bank with an operational assist corresponding to the failure.2. The method of claim 1 , further comprising:determining that the first bank configured with the operational assist includes the failure or another failure; andconfiguring the first bank with a voltage assist.3. The method of claim 2 , further comprising determining that the first bank configured with the operational assist and the voltage assist can be repaired.4. The method of claim 1 , wherein the determining that the first bank of the plurality of banks includes the failure comprises:configuring the plurality of banks with minimum tuning adjustments; andtesting the plurality of banks; anddetermine the first bank includes one or more cells having a likelihood of failure for one or more operational characteristics that is above a threshold value.5. The method of claim 4 , wherein the configuring the plurality of banks with minimum tuning adjustments comprises configuring the plurality of banks without any power assist and without any operational assist.6. The method of claim 5 , wherein the testing the plurality of banks comprises:reading and writing test patterns to the integrated circuit; anddetermining that an error has occurred with respect one or more ...

Output driver circuit

An output driver circuit includes a driving control signal generation block configured to compare a power supply voltage and a reference voltage and generate first and second driving control signals and first and second inverted driving control signals; a preliminary driving block configured to drive a pull-up driving signal and a pull-down driving signal with driving strengths set according to the first and second driving control signals and the first and second inverted driving control signals; and a driving block configured to drive output data in response to the pull-up driving signal and the pull-down driving signal.

INPUT BUFFER

An input buffer includes a first buffer circuit to amplify a difference between a first input signal and a second input signal; a second buffer circuit formed of a replica circuit of the first buffer circuit to generate a common mode output signal in response to the first input signal; and a detector to compare the common mode output signal with a reference output signal and to control the first and second buffer circuits according to the comparison result such that a level of the common mode output signal coincides with a level of the reference output signal. 1. An input buffer comprising:a first buffer circuit to amplify a difference between a first input signal and a second input signal;a second buffer circuit formed of a replica circuit of the first buffer circuit to generate a common mode output signal in response to the first input signal; anda detector to compare the common mode output signal with a reference output signal and to control the first and second buffer circuits according to the comparison result such that a level of the common mode output signal coincides with a level of the reference output signal.2. The input buffer of claim 1 , wherein the detector provides the second buffer circuit with one of an up control signal to increase a level of the common mode output signal and a down control signal to decrease a level of the common mode output signal.3. The input buffer of claim 2 , wherein the detector provides the first buffer circuit with at least one of the up control signal and the down control signal when a level of the common mode output signal coincides with a level of the reference output signal.4. The input buffer of claim 3 , wherein the up and down control signals are formed of a digital value.5. The input buffer of claim 3 , wherein the first buffer circuit comprises:a differential amplifier to amplify a difference between the first input signal and the second input signal;an inverter circuit to invert an output signal of the ...

INPUT BUFFER

An input buffer which includes an amplification circuit configured to amplify a difference between a first input signal and a second input signal; and an inverter configured to invert an output signal of the amplification circuit. The amplification circuit provides the inverter with a bias voltage generated on the basis of one of the first and second input signals, and the inverter operates responsive to the bias voltage. 1. An input buffer comprising:an amplification circuit configured to amplify a difference between a first input signal and a second input signal; andan inverter configured to invert an output signal of the amplification circuit,wherein the amplification circuit provides the inverter with a bias voltage generated on the basis of one of the first and second input signals, and the inverter operates responsive to the bias voltage.2. The input buffer of claim 1 , wherein the amplification circuit comprises:a constant current source which operates responsive to the bias voltage; andan amplification unit which amplifies a difference between the first input signal and the second input signal.3. The input buffer of claim 2 , wherein the amplification unit comprises:a first PMOS transistor having a source connected with a power supply voltage, a gate, and a drain;a second PMOS transistor having a source connected with the power supply voltage, a gate, and a drain, the first and second PMOS transistors forming a current mirror;a first NMOS transistor having a drain connected with the drain and gate of the first PMOS transistor, a gate connected to receive the first input signal, and a source connected with the constant current source; anda second NMOS transistor having a drain connected with the drain of the second PMOS transistor, a gate connected to receive the second input signal, and a source connected with the constant current source.4. The input buffer of claim 3 , wherein the constant current source comprises:a third NMOS transistor having a drain ...

Voltage compensated level-shifter

Described herein is a voltage compensated level-shifter with nearly constant duty cycle and matching rise and fall slopes of the output of the level-shifter, no meta-stability, and nearly constant propagation delay across power supply levels. The voltage compensated level-shifter comprises a first inverter to receive an input signal for level shifting from a first power supply level to a second power supply level, and to generate a first inverted signal, the first inverter operating on the first power supply level; a second inverter to receive the input signal and to generate a second inverted signal, the second inverter operating on the second power supply level; and a NOR logical gate to receive the first and second inverted signals and to generate an output signal, the NOR logical gate operating on the second power supply level, wherein the output signal is level shifted to the second power supply level.

Device and method for interconnecting electronic systems having different reference potentials

A device is provided for interconnecting electronic systems having reference potentials separated by an alternating potential difference, the device includes a plurality of electrical connections that can electrically connect the electronic systems, and inductance coils arranged in series on the electrical connections, the inductance coils being electromagnetically coupled. Als provided is a method for interconnecting electronic systems.

Electric circuit

A transistor has variation in a threshold voltage or mobility due to accumulation of factors such as variation in a gate insulating film which is caused by a difference of a manufacturing process or a substrate to be used and variation in a crystal state of a channel formation region. The present invention provides an electric circuit which is arranged such that both electrodes of a capacitance device can hold a voltage between the gate and the source of a specific transistor. Further, the present invention provides an electric circuit which has a function capable of setting a potential difference between both electrodes of a capacitance device so as to be a threshold voltage of a specific transistor.

IDENTIFICATION CIRCUIT AND METHOD FOR GENERATING AN IDENTIFICATION BIT USING PHYSICAL UNCLONABLE FUNCTIONS

An embodiment of the present invention is an identification circuit installed on an integrated circuit for generating an identification bit, comprising a first circuit to generate a first output signal that is based on random parametric variations in said first circuit, a second circuit to generate a second output signal that is based on random parametric variations in said second circuit, a third circuit capable to be operated in an amplification mode and in a latch mode, wherein in said amplification mode the difference between the first output signal and the second output signal is amplified to an amplified value and, wherein in said latch mode said amplified value is converted into a digital signal. 1. An identification circuit installed on an integrated circuit for generating an identification bit , comprising:a first circuit to generate a first output signal that is based on random parametric variations in said first circuit,a second circuit to generate a second output signal that is based on random parametric variations in said second circuit,a third circuit capable to be operated in an amplification mode and in a latch mode, wherein in said amplification mode the difference between the first output signal and the second output signal is amplified to an amplified value and, wherein in said latch mode said amplified value is converted into a digital signal.2. The identification circuit of claim 1 , further comprising:a switching circuit, wherein the switching circuit is designed to switch between said amplification mode and said latch mode of the said third circuit.3. The identification circuit of claim 1 , further comprising:a first transistor in said first circuit, wherein said first output signal is an operating characteristic of said first transistor anda second transistor in said second circuit wherein said second output signal is an operating characteristic of said second transistor.4. The identification circuit of claim 1 , further comprising:a first ...

SECURE DIGEST FOR PLD CONFIGURATION DATA

A method for verifying that data is correctly loaded into an individual programmable logic device includes computing a reference digest of the data to be loaded into the individual programmable logic device, loading the data into the individual programmable logic device, computing inside the individual programmable logic device an as-programmed digest of the data that was loaded into the individual programmable logic device, reading the as-programmed digest out of the individual programmable logic device, comparing the as-programmed digest with the reference digest, and verifying the loaded data if the as-programmed digest matches the reference digest, and indicating an error if the as-programmed digest does not match the reference digest. 1. A method for verifying that data is correctly loaded into an individual programmable logic device , comprising:computing a reference digest of at least a portion of the data for the individual programmable logic device;loading the data into the individual programmable logic device;computing inside the individual programmable logic device a device digest of the at least the portion of the data that was loaded into the individual programmable logic device;reading the device digest out of the individual programmable logic device;comparing the device digest with the reference digest; andverifying the loaded data if the device digest matches the reference digest, and indicating an error if the device digest does not match the reference digest.2. The method of wherein the portion comprises the complete data for the individual programmable logic device.3. The method of claim 1 , further including encrypting the device digest prior to reading the device digest out of the individual programmable logic device.4. The method of wherein;the data for the individual programmable logic device includes common configuration data and data unique to the individual programmable logic device;computing a reference digest of the data to be loaded into ...

Output buffer and signal processing method

An output buffer comprises a series connection of a first field effect transistor and a second field effect transistor, wherein the first field effect transistor is connected to a first supply potential terminal and the second field effect transistor is connected to a second supply potential terminal. An output terminal is connected to a common connection of the first transistor and the second transistor. The output buffer has a series connection of a resistive element and a capacitive element, wherein the capacitive element is connected to the output terminal, and a control circuit, to which an input signal is provided. The control circuit controls the transistors in such a way that turning off of a transistor is performed immediately, while turning on of a transistor is performed depending on the charging or discharging of the capacitive element, thus achieving a defined slew rate of the output signal at the output terminal.

SEQUENTIAL STATE ELEMENTS FOR TRIPLE-MODE REDUNDANT STATE MACHINES, RELATED METHODS, AND SYSTEMS

The disclosure relates generally to sequential state elements (SSEs), triple-mode redundant state machines (TMRSMs), and methods and systems for testing triple-mode redundant pipeline stages (TMRPSs) within the TMRSMs using triple-mode redundant SSEs (TMRSSEs). The SSEs, TMRSMs, TMRPSs, and TMRSSEs may be formed as integrated circuits on a semiconductor substrate. Of particular focus in this disclosure are SSEs used to sample and hold bit states. Embodiments of the SSEs have a self-correcting mechanism to protect against radiation-induced soft errors. The SSE may be provided in a pipeline circuit of a TMRSM to receive and store a bit state of a bit signal generated by combinational circuits within the pipeline circuit. More specifically, the SSEs may be provided in a TMRSSE configured to perform self-correction. Also disclosed are methods for using the TMRSSE to test redundant pipeline stages of the TMRSM. 1. A sequential state element (SSE) comprising:a multiplexer operable to generate a first bit signal having a first bit state by being configured to select between setting the first bit state to a first logical bit value, setting the first bit state to a second logical bit value opposite the first logical bit value, and setting the first bit state in accordance with a first data bit state of a first data bit signal in response to a multiplexer test mode input; and receive the first feedback bit signal, a second feedback bit signal having a second feedback bit state, and a third feedback bit signal having a third feedback bit state; and', 'hold a first output bit state of a first output bit signal in accordance with a majority bit state of the first feedback bit signal, the second feedback bit signal, and the third feedback bit signal., 'a feedback stage operably associated with the multiplexer such that a first feedback bit state of a first feedback bit signal is set up in accordance with the first bit state of the first bit signal, the feedback stage being ...

BUFFER SYSTEM HAVING REDUCED THRESHOLD CURRENT

A buffer system is provided that reduces threshold current using a current source to provide power to one or more stages of the buffer system. The buffer system may also include delay management techniques that balances all of, or part of, a delay that may be imparted to an input signal by the current source. In addition, hysteresis techniques may be used to provide enhanced noise management of the input signal. 1. An input buffer system , comprising:first inverter stage circuitry configured to switch at a first switching speed based on a first reference current and a second switching speed based on a second reference current; wherein the second reference current is greater than the first reference current and wherein the second switching speed is greater than the first switching speed; andsecond inverter stage circuitry configured to invert an output of the first inverter stage circuitry, the second inverter stage circuitry configured to switch at a third switching speed based on a third reference current and a fourth switching speed based on a fourth reference current; wherein the fourth reference current is greater than the third reference current and wherein the fourth switching speed is greater than the third switching speed.2. The input buffer system of claim 1 , wherein:the first reference current is configured to impart a delay on an input digital signal being switched by the first inverter stage circuitry, anda delay imparted by the third reference current is substantially equal to the delay imparted by the first reference current.3. The input buffer system of claim 1 , further comprising:hysteresis circuitry, coupled to the first inverter stage circuitry, configured to control a switch transition threshold of the input digital signal by the first inverter stage circuitry so that the Low to High switch transition threshold is greater than a High to Low switch transition threshold.4. The input buffer system of claim 1 , further comprising:third and fourth ...

Medium-voltage drivers in a safety application

Various exemplary embodiments relate to a current driver for controlling a safety control device, including: a clamp circuit connected to a first output configured to clamp the voltage at the first output to a clamp voltage value, wherein the first output is configured to be connected to a high voltage switch; a plurality of medium voltage switches; a plurality of switch drivers, wherein each switch driver is connected to one of the medium voltage switches; a plurality of second outputs wherein each of the plurality of second outputs are configured to be connected across one of a plurality of loads; and a controller configured to control the high voltage switch.

Fault Tolerant Integrated Circuit Architecture

The exemplary embodiments provide a resilient integrated circuit. An exemplary IC comprises a plurality of composite circuit elements, a state machine element (SME), and a plurality of communication elements. Each composite circuit element comprises an element interface and a selected circuit element which may vary by element type, and which may be configurable. The state machine element assigns various functions based on element type, such as assigning a first configuration to a first element type, assigning a second configuration to a second element type, and providing a first data link for the corresponding assignments. In response to detection of a fault or failure, the state machine element re-assigns the first configuration to another composite circuit element and creates a second data link for performance of the same function. The assignment, routing, fault detection, and re-assignment and data re-routing can occur in real time for a wide variety of programs and algorithms, providing for the IC to continue the same functioning despite defects which may arise during operation. 1. An apparatus comprising:a plurality of circuit arrays, each circuit array of the plurality of circuit arrays comprising:a plurality of composite circuit elements, each composite circuit element comprising an element interface and a circuit element of a plurality of different circuit element types, each element interface comprising an element controller coupled to a circuit element; a plurality of input queues to store input data for the circuit element; a plurality of output queues to store data output from the circuit element; and one or more registers to store one or more designations of either or both a data input source or a data output destination;at least one data queue to store a data word for transfer between adjacent circuit arrays of the plurality of circuit arrays; anda full interconnect bus coupling the plurality of data output queues to the plurality of input queues and ...

ISOLATION RECEIVER

An isolation receiver includes at least one isolation capacitor to provide a first logic signal in response to a second logic signal that is provided by a transmitter. The receiver includes a signal processing circuit to amplify the first logic signal to generate an amplified signal, and the signal processing circuit includes a an amplifier to apply a nonlinear function. A comparator of the receiver provides a third logic signal in response to the amplified signal. 1. An isolation receiver comprising:at least one isolation capacitor to provide a first logic signal in response to a second logic signal that is provided by a transmitter;a signal processing circuit to apply a nonlinear function to the first logic signal to generate a transformed signal; anda comparator to provide a third logic signal in response to the transformed signal.2. The isolation receiver of claim 1 , wherein the signal processing circuit comprise an amplifier.3. The isolation receiver of claim 2 , wherein the amplifier comprises: an output port to provide an output signal for the first analog multiplier cell;', 'a first input port; and', 'a second input port; and, 'a first analog multiplier cell comprising an output port to provide an output signal for the second analog multiplier cell;', 'a first input port; and', 'a second input port,, 'a second analog multiplier cell comprisingwherein the first and second input ports of the first analog multiplier cell are coupled together, the first input port of the second analog multiplier cell is coupled to the output port of the first analog multiplier cell, and the second input port of the second analog multiplier cell is coupled to the first and second input ports of the first analog multiplier cell.4. The isolation receiver of claim 3 , wherein the first input ports of the first and second analog multiplier cells comprise radio frequency (RF) input ports of mixer cells claim 3 , and the second input ports of the first and second analog multiplier ...

SEMICONDUCTOR MEMORY DEVICE, MEMORY CONTROLLER AND MEMORY SYSTEM HAVING ON DIE TERMINATION AND ON DIE TERMINATION CONTROLLING METHOD

A semiconductor memory device includes a first memory chip including a first on die termination (ODT) unit electrically connected to a first pad, the first pad being connected to a first terminal to receive a first signal, and a second memory chip including a second ODT unit electrically connected to a second pad, the second pad being connected to the first terminal to receive the first signal, the first ODT unit being configured to turn on/off according to a memory operation, the second ODT unit being configured to turn off regardless of the memory operation, and the first and second ODT units are switchable. 1. A semiconductor memory device , comprising:a first memory chip including a first on die termination (ODT) unit electrically connected to a first pad, the first pad being connected to a first terminal to receive a first signal; anda second memory chip including a second ODT unit electrically connected to a second pad, the second pad being connected to the first terminal to receive the first signal,wherein the first ODT unit is configured to turn on/off according to a memory operation, the second ODT unit is configured to turn off regardless of the memory operation, and the first and second ODT are switchable.220.-. (canceled) This is a continuation application based on pending application Ser. No. 13/471,656, filed May 15, 2012, the entire contents of which is hereby incorporated by reference.This application claims the benefit of Korean Patent Application No. 10-2011-0064966, filed on Jun. 30, 2011, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference.1. FieldThe inventive concept relates to a semiconductor memory device, a memory controller, and a memory system, and more particularly, to a semiconductor memory device having a plurality of memory chips including an on-die termination, a memory controller, a memory system, and an on-die termination controlling method.2. Description of the ...

Impedance calibration circuit and method

An embodiment includes an impedance calibration circuit having a calibrator configured to compare voltage levels at an external node and an internal node of the impedance calibration circuit and to generate an output based on the comparison. The calibrator further includes respective filters coupled between the external node and a first input of the comparator, and between the internal node and a second input of the comparator. The filters are configured for symmetric noise injection into the comparator from a chip ground line to which a programmable resistor at the internal node is coupled.

TRANSMITTER SWING CONTROL CIRCUIT AND METHOD

Disclosed herein are embodiments of a swing compensation scheme for compensating errors in a transmitter driver. 1. A chip comprising:a differential driver to provide a differential output, the differential output having a first output signal with first swing level and a second output signal with second swing level; anda swing control circuit coupled to the differential driver, the swing control circuit including a selector unit which is operable to select one of a first signal, indicating a first difference between the first and second swing levels, and a second signal, indicating a second difference between the second and first swing levels.2. The chip of claim 1 , wherein the swing control circuit is operable to adjust current bias of the differential driver to maintain the first and second swing levels in a predetermined range according to the first and second differences.3. The chip of further comprises a logic unit to generate a select signal for the selector circuit claim 1 , wherein the logic unit to generate the select signal according to input data received by the differential driver for transmission by the differential driver.4. The chip of claim 1 , wherein the swing control circuit comprises:a first amplifier to receive first and second output signals, the first amplifier to generate the first signal indicating the first difference; anda second amplifier to receive first and second output signals, the second amplifier to generate the second signal indicating the second difference.5. The chip of further comprises a comparator coupled to the selector unit claim 4 , the comparator to compare an output of the selector unit with a reference signal.6. The chip of further comprises a sampler to sample an output of the comparator.7. The chip of further comprises a digital-to-analog converter (DAC) to adjust current bias of the differential driver to maintain the first and second swing levels in the predetermined range.8. The chip of further comprises a logic ...

SEMICONDUCTOR INTEGRATED CIRCUIT

A semiconductor integrated circuit includes a logic circuit, the logic circuit including an attack detection circuit for checking multi-bit storage. The attack detection circuit includes an error determination circuit capable of detection through a logic operation such as a code theory and a light irradiation detection circuit having light detection elements, and the light detection elements are arranged so that the light irradiation detection circuit can detect errors of the number of bits beyond the detection limit of the error determination circuit. Due to error detection by the error determination circuit and light irradiation detection by the light irradiation detection circuit, the circuits complementarily detect fault attacks from outside. 1. A semiconductor integrated circuit comprising a logic circuit including n storage elements (n is a positive integer) which can each store 1-bit information and an attack detection circuit ,the attack detection circuit comprising:an error determination circuit which can detect through a logic operation that k-bit or less errors (k is a positive integer) have occurred in n-bit codes stored in the n storage elements; anda light irradiation detection circuit which has light detection elements and can detect that light has been irradiated to (k+1) or more of the n storage elements,wherein it is determined that the logic circuit has been attacked from outside when the error determination circuit detects an error or the light irradiation detection circuit detects light irradiation.2. The semiconductor integrated circuit according to claim 1 ,wherein the n storage elements include m storage elements which can store m-bit error detection codes, andwherein the error determination circuit comprises an error detection code generation circuit for generating an error detection code from (n-m) storage elements of the n storage elements and a check circuit which can detect occurrence of an error in the n storage elements.3. The ...

Logic circuit device comprising at least one digital input

The invention pertains to a logic circuit device comprising at least one digital input furnished with a fuse (FUS) being, in the closed state, suitable for applying an electrical input voltage of the logic circuit corresponding to a first logic state from among the logic states 0 and 1, and, in the definitive open state, suitable for applying an electrical input voltage of the logic circuit corresponding to the second logic state from among the logic states 0 and 1, said fuse (FUS) being suitable for being placed definitively in the second logic state by injection of a current greater than a threshold current (CS).

INTEGRATED CIRCUITS HAVING ACCESSIBLE AND INACCESSIBLE PHYSICALLY UNCLONABLE FUNCTIONS

An integrated circuit substrate of an aspect includes a plurality of exposed electrical contacts. The integrated circuit substrate also includes an inaccessible set of Physically Unclonable Function (PUF) cells to generate an inaccessible set of PUF bits that are not accessible through the exposed electrical contacts. The integrated circuit substrate also includes an accessible set of PUF cells to generate an accessible set of PUF bits that are accessible through the exposed electrical contacts. Other apparatus, methods, and systems are also disclosed. 1. An integrated circuit substrate comprising:a plurality of exposed electrical contacts;an inaccessible set of Physically Unclonable Function (PUF) cells to generate an inaccessible set of PUF bits that are not accessible through the exposed electrical contacts; andan accessible set of PUF cells to generate an accessible set of PUF bits that are accessible through the exposed electrical contacts.2. The integrated circuit substrate of claim 1 , further comprising logic to allow the accessible set of PUF bits to be accessible through the exposed electrical contacts claim 1 , and wherein there is no logic to allow the inaccessible set of PUF bits to be accessible through the exposed electrical contacts.3. The integrated circuit substrate of claim 1 , wherein the inaccessible set of PUF bits are to be provided to security logic for use in security and the accessible set of PUF bits are not to be provided to the security logic for use in security.4. The integrated circuit substrate of claim 1 , further comprising:security logic;logic to provide the inaccessible set of PUF bits to the security logic, andwherein there is no logic to provide the accessible set of PUF bits to the security logic.5. The integrated circuit substrate of claim 1 , wherein the accessible set of PUF cells are within a region more enabled for debug than a region having the inaccessible set of PUF cells.6. The integrated circuit substrate of claim 1 , ...

Semiconductor integrated circuit and signal transmission method thereof

A semiconductor integrated circuit includes a plurality of semiconductor chips stacked in a multi-layer structure; a correction circuit in each semiconductor chip configured to reflect a delay time corresponding to the position of the chip in the stack into an input signal to output to each semiconductor chip; and a plurality of through-chip vias formed vertically through each of the semiconductor chips and configured to transmit the input signal to the semiconductor chip.

PREVENTING GLITCH PROPAGATION

When a signal glitches, logic receiving the signal may change in response, thereby charging and/or discharging nodes within the logic and dissipating power. Providing a glitch-free signal may reduce the number of times the nodes are charged and/or discharged, thereby reducing the power dissipation. A technique for eliminating glitches in a signal is to insert a storage element that samples the signal after it is done changing to produce a glitch-free output signal. The storage element is enabled by a “ready” signal having a delay that matches the delay of circuitry generating the signal. The technique prevents the output signal from changing until the final value of the signal is achieved. The output signal changes only once, typically reducing the number of times nodes in the logic receiving the signal are charged and/or discharged so that power dissipation is also reduced. 1. A circuit , comprising:a delay circuit configured to generate a ready signal that is negated at a first transition of a clock signal and asserted after a first delay relative to the first transition, wherein the first delay is at least as long as a second delay; and receive an input signal generated by combinational logic, wherein a change in a first signal received at an input of the combinational logic causes a corresponding change in the input signal at an output of the combinational logic after the second delay following the first transition of a clock signal; and', 'sample the input signal while the ready signal is asserted to transfer a level of the input signal to an output signal of the sampling circuit, wherein the input signal is unchanged from the second delay until the input signal is sampled., 'a sampling circuit configured to2. The circuit of claim 1 , wherein the sampling circuit is further configured to hold the output signal at a constant level from the first transition of the clock signal until the input signal is sampled.3. The circuit of claim 1 , wherein the sampling ...

QUBIT LEAKAGE ERROR REDUCTIONS

An arrangement, an apparatus, a quantum computing system, and a method are disclosed for reducing qubit leakage errors. In an example, an apparatus includes a qubit having a ground state and a plurality of excited states. The plurality of excited states include a lowest excited state. An energy difference between the ground state and the lowest excited state corresponds to a first frequency, and an energy difference between the lowest excited state and another excited state in the plurality of excited states corresponds to a second frequency. The apparatus also includes an energy dissipation structure to dissipate transferred energy, and a filter having a stopband and a passband. The filter is coupled to the qubit and to the energy dissipation structure. The stopband includes the first frequency and the passband includes the second frequency for reducing qubit leakage errors. 1. An apparatus for reducing qubit leakage errors comprising:at least one qubit having a ground state and a plurality of excited states, wherein the plurality of excited states includes a lowest excited state, wherein an energy difference between the ground state and the lowest excited state corresponds to a first frequency, and an energy difference between the lowest excited state and another excited state in the plurality of excited states corresponds to a second frequency;an energy dissipation structure configured to dissipate energy transferred to the energy dissipation structure; anda filter having at least one stopband and at least one passband, wherein the filter is coupled to the at least one qubit and to the energy dissipation structure, and wherein the at least one stopband includes the first frequency and the at least one passband comprises the second frequency.225. The apparatus according to claim 1 , wherein the energy dissipation structure comprises at least one normal metal—insulator—superconductor (NIS) junction.3. The apparatus according to claim 1 , wherein the energy ...

Mixed-Signal Integrated Circuit

A mixed-signal integrated circuit includes an analog circuit comprising at least one digital block embedded in the analog circuit, the at least one digital block comprising a plurality of functional bits and a plurality of configuration bits, the plurality of functional bits providing for a functionality of the analog circuit according to a designed functionality and the plurality of configuration bits being usable for configuring a plurality of operational modes of the analog circuit; and a digital circuit comprising a scan chain configured to scan at least part of the functional bits of the digital block embedded in the analog circuit with respect to the designed functionality, wherein the scan chain is further configured to set at least part of the configuration bits of the digital block embedded in the analog circuit according to a selected operational mode of the plurality of operational modes of the analog circuit.

DYNAMIC VOLTAGE-LEVEL CLOCK TUNING

Apparatus and methods are provided for improving yield and frequency performance of integrated circuit processors, such as multiple-core processors. In an example, an apparatus can include a plurality of clock buffers, each clock buffer of the plurality of clock buffers configured to receive a first clock signal and distribute a plurality of second clock signals, a one-time programmable locate critical path mechanism configured provide a plurality of indications to enable or disable a delay of each clock buffer of the plurality of clock buffers, and a power management control circuit configured to over-ride one or more of the plurality of indications in a first non-test mode of operation of the apparatus and to not over-ride the one or more indications in a second non-test mode of operation of the apparatus. 1. An apparatus comprising:a plurality of clock buffers, each clock buffer of the plurality of clock buffers configured to receive a first clock signal and distribute a plurality of second clock signals;a one-time programmable locate critical path mechanism configured provide a plurality of indications to enable or disable a first delay of each clock buffer of the plurality of clock buffers; anda power management control circuit configured to over-ride one or more of the plurality of indications in a first non-test mode of operation of the apparatus and to not over-ride the one or more indications in a second non-test mode of operation of the apparatus.2. The apparatus of claim 1 , wherein the one-time programmable locate critical path mechanism is programmed during a test mode of the apparatus.3. The apparatus of claim 1 , wherein the first non-test mode is defined by a first supply voltage of the apparatus and a first frequency of the first clock signal; andwherein the second non-test mode is defined by a second supply voltage of the apparatus and a second frequency of the first clock signal.4. The apparatus of claim 3 , including a plurality of delay ...

Logic Timing and Reliability Repair for Nanowire Circuits

A method for improving an integrated circuit design having transistors with nanowire channels comprises identifying a particular device having a particular transistor with a nanowire channel; and adding to the integrated circuit design a controller which, when activated, repairs the particular transistor by self-heating. A critical path in logic circuitry in the design can be determined including a particular device having a transistor with a nanowire channel. A repair circuit can be added to the design connected to the particular device, the repair circuit when activated applying a self-heating stress to the particular device. The repair circuit can include a selection block selecting among a plurality of signals as an input signal to the particular device. The plurality of signals include a repair signal and an operational logic signal, the repair signal being such as to apply the self-heating stress to the nanowire channel of the particular device when activated. 1. A method for improving an integrated circuit design which has transistors with nanowire channels , comprising:identifying a particular device having a particular transistor with a nanowire channel; andadding to the integrated circuit design a controller which, when activated, repairs the particular transistor by self-heating.2. A method for improving an integrated circuit design including logic circuitry with devices having transistors with nanowire channels , comprising:determining a critical path in the logic circuitry, the critical path including a particular device having a transistor with a nanowire channel; andadding a repair circuit to the integrated circuit design connected to the particular device in the critical path, the repair circuit when activated applying a self-heating stress to the particular device in the critical path.3. The method of claim 2 , the repair circuit including a selection block selecting among a plurality of signals as an input signal to the particular device claim 2 , ...

THRESHOLD LOGIC ELEMENT WITH STABILIZING FEEDBACK

Threshold logic elements and methods of operating the same are disclosed. In one embodiment, a threshold logic element includes a first input gate network configured to receive a first set of logical signals, a second input gate network configured to receive a second set of logical signals. The differential sense amplifier is operably associated with the first input gate network and the second input gate network such that the differential sense amplifier is configured to generate a differential logical output in accordance with a threshold logic function. In order to make the threshold logic element more robust, the differential sense amplifier is configured to feed back the differential logical output to the first input gate network and the second input gate network. By providing the differential logical output as feedback, floating node issues are avoided and the threshold logic element is more resistant to noise. 1. A threshold logic element comprising:a first input gate network configured to receive a first set of logical signals;a second input gate network configured to receive a second set of logical signals; anda differential sense amplifier operably associated with the first input gate network and the second input gate network such that the differential sense amplifier is configured to generate a differential logical output in accordance with a threshold logic function, wherein the differential sense amplifier is configured to feed back the differential logical output to the first input gate network and the second input gate network.2. The threshold logic element of wherein:the differential sense amplifier is operable to generate the differential logical output so that the differential logical output has a first logical output and a second logical output; andthe differential sense amplifier is configured to feedback the differential logical output to the first input gate network and the second input gate network by being configured to provide the first ...

SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE

A semiconductor integrated circuit device having a control signal system for avoiding failure to check an indefinite signal propagation prevention circuit, for facilitating a check included in an automated tool, and for facilitating a power shutdown control inside a chip. In the semiconductor integrated circuit device, power shutdown priorities are provided by independent power domains (Area A to Area I). A method for preventing a power domain having a lower priority from being turned OFF when a circuit having a high priority is turned ON is also provided. 14-. (canceled)5. A semiconductor integrated circuit device formed on one chip comprising:a first functional block connected to a first power supply line and a second power supply line;a second functional block connected to the first power supply line and a third power supply line and communicating with the first functional block;a third functional block connected to the first power supply line and a fourth power supply line and communicating with the first functional block;a first power switch shutting down the first functional block from power supply via the second power supply line;a second power switch shutting down the second functional block from power supply via the third power supply line; anda third power switch shutting down the third functional block from power supply via the fourth power supply line,wherein the first functional block is shut down by the first power switch when the second and the third functional blocks are shut down.6. A semiconductor integrated circuit device according to claim 5 ,wherein the first functional block is laid out inside each of the second and third functional blocks.7. A semiconductor integrated circuit device according to claim 6 ,wherein the first power switch to shut down the first functional block in the second functional block and the first power switch to shut down the first functional block in the third functional block are provided independently.8. A ...

APPARATUSES AND METHODS FOR PHASE INTERPOLATING CLOCK SIGNALS AND FOR PROVIDING DUTY CYCLE CORRECTED CLOCK SIGNALS

Apparatuses and methods for phase interpolating clock signals and for providing duty cycle corrected clock signals are described. An example apparatus includes a clock generator circuit configured to provide first and second clock signals responsive to an input clock signal. A duty phase interpolator circuit may be coupled to the clock generator circuit and configured to provide a first and second duty cycle corrected interpolated clock signals. A duty cycle adjuster circuit may be coupled to the duty phase interpolator circuit and configured to receive the first and second duty cycle corrected interpolated clock signals and provide a duty cycle corrected clock signal responsive thereto. A duty cycle detector may be coupled to the duty cycle adjuster circuit and configured to detect duty cycle error of the duty cycle corrected clock signal and provide the adjustment signals to correct the duty cycle error. 1. An apparatus , comprising: a delay generator circuit configured to provide a start signal and further configured to provide a stop signal following the start signal after one cycle of the input clock signal;', 'a first delay line coupled to the delay generator circuit and configured to delay the start signal through a plurality of first delay stages;', 'a delay control logic circuit coupled to the delay generator circuit and the first delay line, the delay control logic configured to activate the first delay line to delay the start signal, and the delay control logic further configured to determine a number of first delay stages of the plurality of first delay stages through which the start signal propagates responsive to the stop signal and to provide control signals representing the number of first delay stages of the plurality of delay stages;', 'a second delay line coupled to the delay control logic and configured to delay the input clock signal through a plurality of second delay stages to provide the second clock signal, a number of second delay stages of ...

SOFT ERROR-RESILIENT LATCH

A latch is provided. The latch includes a plurality of storage nodes including a plurality of data storage nodes configured to store a data bit having one of two states and a plurality of complementary data storage nodes configured to store a complement of the data bit. The latch includes a plurality of supply voltage multi-dependency stages respectively corresponding to the plurality of storage nodes. Each supply voltage multi-dependency stage has an output coupled to a storage node and at least two control inputs respectively coupled to at least two other storage nodes of the plurality of storage nodes. The supply voltage multi-dependency stage is configured to cause a state of the data bit stored in the storage node to change from a first state to a second state in response a change in both states of two data bits respectively stored in the at least two other storage nodes. 1. A circuit , comprising: [ a plurality of data storage nodes each configured to store a data bit having one of two states including a first state and a second state; and', 'a plurality of complementary data storage nodes each configured to store a complement of the data bit; and, 'a plurality of storage nodes including, 'a plurality of first voltage multi-dependency stages respectively corresponding to the plurality of storage nodes, each first voltage multi-dependency stage having an output coupled to a respective storage node of the plurality of storage nodes and at least two control inputs respectively coupled to at least two other storage nodes of the plurality of storage nodes, the first voltage multi-dependency stage configured to cause the state of the data bit stored in the storage node to change from the second state to the first state in response to a change in both states of two data bits respectively stored in the at least two other storage nodes., 'a first latch including2. The circuit of claim 1 , wherein the first latch includes:a plurality of second voltage multi-dependency ...

TWO BIT/CELL SRAM PUF WITH ENHANCED RELIABILITY

A method for detecting unreliable bits in transistor circuitry includes adjusting a value of a variable capacitor coupled to a physical unclonable function (PUF) cell of a transistor circuit. The adjusting includes tilting the PUF cell to either a zero or one state: if the PUF cell changes its state during the tilting it is deemed unstable, and if the PUF cell does not change its state during the tilting it is deemed stable. 1. A method for detecting unreliable bits in transistor circuitry comprising:adjusting a value of a variable capacitor coupled to a physical unclonable function (PUF) cell of a transistor circuit, wherein the adjusting comprises tilting the PUF cell to either a zero or one state, and if said PUF cell changes its state during the tilting it is deemed unstable, and if the PUF cell does not change its state during the tilting it is deemed stable.2. The method according to claim 1 , wherein adjusting the value of said variable capacitor is adjusted digitally.3. The method according to claim 1 , wherein said variable capacitor is coupled to said PUF cell via a switch.4. The method according to claim 1 , wherein said PUF cell comprises an SRAM (static random-access memory) PUF.5. The method according to claim 4 , wherein said SRAM PUF comprises two crisscrossed inverters claim 4 , wherein a first inverter has its input coupled to a node H and its output coupled to a node H_b claim 4 , and a second inverter has its input coupled to the node H_b and its output coupled to the node H.6. The method according to claim 5 , wherein said variable capacitor is coupled to the node H via a first switch and is coupled to the node H_b via a second switch claim 5 , or said variable capacitor comprises a first variable capacitor coupled to the node H via said first switch and a second variable capacitor coupled to the node H_b via said second switch.7. The method according to claim 6 , wherein the first and second capacitors are coupled to multiple PUF cells via ...

OUTPUT APPARATUS AND OUTPUT SYSTEM INCLUDING THE SAME

An output apparatus includes an output driving unit configured to drive a final output signal; an output compensating signal generation unit configured to generate a delayed output signal by delaying the output signal by a predetermined time, and generate an output compensating signal based on the delayed output signal and the output signal; and an output driving compensation unit configured to compensate for the final output signal to a level opposite to a level to which the final output signal is driven. 1. An output apparatus comprising:an output driving unit configured to drive a final output signal in response to an output signal;an output compensating signal generation unit configured to generate a delayed output signal by delaying the output signal by a predetermined time, and generate an output compensating signal based on the delayed output signal and the output signal; andan output driving compensation unit configured to compensate for the final output signal to a level opposite to a level to which the final output signal is driven, in response to the output compensating signal.2. The output apparatus according to claim 1 , wherein the output driving compensation unit compensates for the final output signal for the predetermined time.3. The output apparatus according to claim 1 , wherein the output compensating signal generation unit comprises:a low output compensating signal generating section configured to perform a logical operation for an output signal and the delayed output signal, and generate a low output compensating signal which is activated for the predetermined time when the final output signal is driven to a high level; anda high output compensating signal generating section configured to perform a logical operation for the output signal and the delayed output signal, and generate a high output compensating signal which is activated for the predetermined time when the final output signal is driven to a low level.4. The output apparatus ...

MULTI-CHANNEL DIGITAL ISOLATOR WITH INTEGRATED CONFIGURABLE PULSE WIDTH MODULATION INTERLOCK PROTECTION

A multi-channel digital isolator includes a digital isolator and an interlock circuit. The isolator includes a transmitter having a transmitter output, a receiver having a receiver input and a receiver output, an isolation barrier coupled between the transmitter output and the receiver input, and an output buffer having a buffer input and configured to output an isolated signal. The transmitter is configured to transmit an input signal across the isolation barrier. The interlock circuit has an interlock input coupled to the receiver output and an interlock output coupled to the buffer input. The interlock module is configured to prevent overlapping active states between the first isolated signal and a complementary isolated signal. In some implementations, the digital isolator also includes a dead-time insertion circuit. 1. A multi-channel digital isolator , comprising: a transmitter having a transmitter output;', 'a receiver having a receiver input and a receiver output;', 'an isolation barrier coupled between the transmitter output and the receiver input, the transmitter configured to transmit an input signal across the isolation barrier; and', 'an output buffer having a buffer input, the output buffer configured to output an isolated signal; and, 'a digital isolator comprisingan interlock circuit having an interlock input coupled to the receiver output and an interlock output coupled to the buffer input, the interlock circuit configured to prevent overlapping active states between the isolated signal and a complementary isolated signal.2. The multi-channel digital isolator of claim 1 , wherein: an inverter having an inverter input and an inverter output, the inverter input coupled to the receiver output; and', 'a complementary output buffer having a complementary buffer input, the complementary output buffer configured to output the complementary isolated signal; and, 'the digital isolator further comprisesthe interlock circuit further comprises a complementary ...

Semiconductor integrated circuit device having bulk bias control function and method of driving the same

A semiconductor integrated circuit device having a bulk bias control function is provided. The semiconductor integrated circuit device may be configured to output the first external voltage as a bulk voltage of a transistor in a power-up period, and to output a second external voltage having a higher level than the first external voltage as the bulk voltage of the transistor in a power-down mode.

INTEGRATED CIRCUIT AND SIGNAL TRANSMISSION METHOD THEREOF

An integrated circuit and a signal transmission method thereof are provided. The integrated circuit includes a first power domain, a second power domain, and a weakly pull circuit. The first power domain is powered by a first power source, the second power domain is powered by a second power source, and the second power domain transmits a signal to the first power domain through a transmission path. The weakly pull circuit is signally connected to the transmission path. When the second power domain is in a power-off mode, the weakly pull circuit maintains the transmission path stably at a logic level to prevent unknown signals from entering the first power domain from the second power domain and disturbing the normal operation of the first power domain. 1. An integrated circuit , comprising:a first power domain powered by a first power source;a second power domain powered by a second power source, the second power domain transmitting a signal to the first power domain through a transmission path; anda weakly pull circuit signally connected to the transmission path, when the second power domain is in a power-off mode, the weakly pull circuit maintaining the transmission path stably at a logic level.2. The integrated circuit according to claim 1 , wherein the first power domain has a first connection pad claim 1 , the second power domain has a second connection pad claim 1 , and the second connection pad is electrically connected to the first connection pad to form the transmission path.3. The integrated circuit according to claim 2 , wherein the weakly pull circuit is located in the first power domain and is electrically connected to the first connection pad.4. The integrated circuit according to claim 1 , wherein the weakly pull circuit is a weakly pull-high circuit or a weakly pull-low circuit.5. The integrated circuit according to claim 4 , wherein when the weakly pull circuit is the weakly pull-low circuit claim 4 , the logic level is a low logic level.6. The ...

HIGHLY EFFICIENT DOUBLE-SAMPLING ARCHITECTURES

Aggressive technology scaling impacts parametric yield, life span, and reliability of circuits fabricated in advanced nanometric nodes. These issues may become showstoppers when scaling deeper to the sub-10nm domain. To mitigate them various approaches have been proposed including increasing guard-bands, fault-tolerant design, and canary circuits. Each of them is subject to several of the following drawbacks; large area, power, or performance penalty; false positives; false negatives; and in sufficient coverage of the failures encountered in the deep nanometric domain. The invention presents a highly efficient double-sampling architecture, which allow mitigating all these failures at low area and performance penalties, and also enable significant power reduction. 2. The circuit protected against timing errors and parasitic disturbances of claim 1 , wherein: said fourth sampling element is driven by the opposite edge of the same clock signal as said first and second sampling elements delayed by a second predetermined delay claim 1 , say second predetermined delay is equal to said first predetermined delay minus the duration of the high level of said clock signal.3. A circuit protected against timing errors and parasitic disturbances claim 1 , the circuit comprising:a combinatory logic circuit having at least one input and one output;at least a first sampling element having its output connected to said at least one input and activated by the rising edge of a clock signal;at least a second sampling element having its input connected to said at least one output and activated by the rising edge of said clock signal;at least a third sampling element having its input connected to the input of said at least first sampling element and activated by the falling edge of said clock signal;at least a fourth sampling element having its input connected to the input of said at least second sampling element and activated by the falling edge of said clock signal;a comparator circuit ...

Electrostatic Discharge Protection for Level-Shifter Circuit

In some embodiments, a method includes providing an input voltage to a level-shifting circuit, where the input voltage is in a first power domain, shifting the input voltage to an output voltage using the level-shifting circuit, where the output voltage is in a second power domain different from the first power domain, and where the level-shifting circuit is coupled to power supply voltages in the second power domain. The method further includes in response to an electrostatic discharge (ESD) event, turning off a first transistor coupled between a first node of the level-shifting circuit and a reference low voltage level of the second power domain. 1. A method comprising:providing an input voltage to a level-shifting circuit, wherein the input voltage is in a first power domain;shifting the input voltage to an output voltage using the level-shifting circuit, wherein the output voltage is in a second power domain different from the first power domain, wherein the level-shifting circuit is coupled to power supply voltages in the second power domain; andin response to an electrostatic discharge (ESD) event, turning off a first transistor coupled between a first node of the level-shifting circuit and a reference low voltage level of the second power domain.2. The method of claim 1 , wherein the first transistor is an N-type transistor claim 1 , wherein the turning off comprises supplying a reference low voltage level of the second power domain to a gate of the first transistor.3. The method of claim 2 , further comprising detecting the ESD event using a control circuit.4. The method of claim 3 , wherein the control circuit is coupled to the power supply voltages of the second power domain claim 3 , wherein an output of the control circuit is coupled to the gate of the first transistor claim 3 , and wherein the control circuit outputs a reference low voltage level of the second power domain during an ESD event.5. The method of claim 4 , wherein the control circuit ...

METHOD AND APPARATUS TO EVALUATE AUDIO EQUIPMENT FOR DYNAMIC DISTORTIONS AND OR DIFFERENTIAL PHASE AND OR FREQUENCY MODULATION EFFECTS

A system is provided to analyze cross-modulation distortion in audio devices, which may include testing with audio frequencies. One or more distortion signals from the audio device may be measured for an amplitude, phase, and or frequency modulation effect. In another embodiment a musical signal may be used as a test signal. Providing additional test signals to the audio device can induce a time varying cross-modulation distortion signal from an output of the audio device. Also utilizing at least one additional filter, filter bank, demodulator and or frequency converter and or frequency multiplier provides extra examination of distortion. Also frequency and or phase response can be measured with the presence of a de-sensing signal and or another signal that induce near slew rate limiting or near overload condition of the device under test. 1. An apparatus for measuring a de-sensing effect on an audio device , wherein the audio device includes an input terminal and an output terminal , comprising:coupling to the input terminal of the audio device at least two signals including at least a first signal comprising a first amplitude, and a second signal comprising a second amplitude;wherein the first amplitude of the first signal is larger than the second amplitude of the second signal;wherein the second signal comprises a noise source;coupling an output signal from the output terminal of the audio device to an input terminal of an amplitude measuring system wherein an output terminal of the amplitude measuring system provides a measurement of a noise spectrum of the noise source;wherein when the first signal is adjusted to the first amplitude level to provide the de-sensing effect on the noise source, and wherein the de-sensing effect changes the noise spectrum of the signal related to the second signal at the output of the audio device.2. The apparatus of wherein the audio device includes one or more amplifying circuits.3. The apparatus of wherein the output signal of ...

DYNAMIC CIRCUITRY USING PULSE AMPLIFICATION TO REDUCE METASTABILITY

Synchronisation circuitry comprises a first dynamic circuit stage generating a first stage state signal which is pulse amplified by pulse amplifying circuitry to generate a pulse amplified signal. The pulse amplified signal is supplied to a second dynamic circuit stage where it is used to control generation of a second stage state signal. The pulse amplifying circuitry comprises a chain of serially connected skewed inverters The action of the pulse amplifying circuitry is to reduce the probability of metastability in the output of the second dynamic stage 1. Circuitry for receiving an input signal having an input signal value and for generating an output signal having an output signal value dependent upon said input signal value , said buffer circuit comprising:a first circuit stage configured to receive said input signal and to generate a first stage state signal in dependence upon said input signal;pulse amplifying circuitry configured to receive and to pulse amplify said first stage state signal to generate a pulse amplified signal having a pulse amplified signal value such that a pulse in said first stage state signal, during which said first stage state signal changes from a first state signal value toward a second state signal value and then returns to said first state signal value, is amplified; second stage reset circuitry configured to reset a second stage state signal to a second stage reset signal value during a second stage reset period;', (i) if said pulse amplified signal value has a first value, then to leave said second stage state signal at said second stage reset signal value; and', '(ii) if said pulse amplified signal value has a second value, then to change said second stage state signal from said second stage reset signal value to a second stage set signal value; and, 'output capture circuitry configured to receive said pulse amplified signal during a second stage evaluation period and], 'a second circuit stage comprisingoutput generating ...

Semiconductor apparatus

A semiconductor apparatus includes an internal circuit connected to a first power line to which a first power voltage is applied; a transistor including a first terminal, which is connected to a node to which an input voltage is applied, a second terminal connected to the internal circuit, and a control terminal to which a control voltage is applied; and a voltage control circuit, which is connected to the node, generating the control voltage. Further, the voltage control circuit includes a step-down circuit generating an internal voltage by lowering the input voltage applied to the node, and a switching circuit, which is connected to the first power line, generating the control voltage based on the first power voltage and the internal voltage.

Circuit and Method for Detection and Compensation of Transistor Mismatch

The present disclosure relates to a detection circuit formed as part of an integrated circuit. In one example, the detection circuit includes a signal generator configured to generate a reference signal, and an amplification circuit comprising a p-channel transistor and an n-channel transistor, wherein the amplification circuit is affected by a variability that also affects a functional circuit formed as part of the integrated circuit. The variability causes the p-channel transistor and the n-channel transistor to have different respective drive strengths. The amplification circuit is configured to receive the reference signal and to provide an amplified signal representative of a difference in the respective drive strengths, wherein the reference signal is more insensitive to the variability than the amplified signal. The present disclosure also relates to an integrated circuit and a method for detecting and compensating a transistor mismatch. 115.-. (canceled)16. A detection circuit formed as part of an integrated circuit , the detection circuit comprising:a signal generator configured to generate a reference signal; andan amplification circuit comprising a p-channel transistor and an n-channel transistor, the amplification circuit being affected by a variability also affecting a functional circuit formed as part of the integrated circuit, the variability causing the p-channel transistor and the n-channel transistor to have different respective drive strengths, and the amplification circuit being configured to receive the reference signal and to provide an amplified signal representative of a difference in the respective drive strengths,wherein the reference signal is more insensitive to the variability than the amplified signal.17. The detection circuit of claim 16 , wherein the variability includes at least one of a process variability claim 16 , a supply voltage variability claim 16 , or a temperature variability.18. The detection circuit of claim 16 , wherein ...

BREAKDOWN-BASED PHYSICAL UNCLONABLE FUNCTION

A device and a method for implementing a physically unclonable function is disclosed. In one aspect, the device includes at least one electronic structure including a dielectric. A conductive path is formed at a random position through the dielectric due to an electrical breakdown of the dielectric, or the electronic structure is adapted for generating an electrical breakdown of the dielectric such that the conductive path is formed through the dielectric at a random position. The at least one electronic structure is adapted for determining a distinct value of a set comprising at least two predetermined values. The distinct value is determined by the position of the conductive path through the dielectric. 1. A method of implementing a physically unclonable function , the method comprisingproviding a device comprising at least one electronic structure, each electronic structure comprising a dielectric,generating an electrical breakdown of the dielectric such that a conductive path is formed, in each of the at least one electronic structure, through the dielectric at a random position,determining, for each of the at least one electronic structure, a distinct value of a set comprising at least two predetermined values, wherein the distinct value is determined by the position of the conductive path through the dielectric of the electronic structure.2. The method of claim 1 , wherein the device comprises an array of transistors claim 1 , and wherein generating the electrical breakdown comprises applying a high gate bias on each transistor to form a conductive path between a gate and randomly either a source or a drain of the transistor.3. The method of claim 1 , further comprising generating plasma damage in the at least one electronic structure.4. A PUF device for implementing a physically unclonable function claim 1 , the device comprising:at least one electronic structure, each electronic structure comprising a dielectric; anda conductive path through the dielectric ...

APPARATUSES AND METHODS FOR PARTIAL BIT DE-EMPHASIS

Apparatuses and methods for partial bit de-emphasis are provided. An example apparatus includes an output driver and control circuit. The output driver includes a pull-up circuit including one or more pull-up legs, and a pull-down circuit including one or more pull-down legs. The control circuit may be coupled to the output driver and configured to receive an input signal having a first logical value and a second logical value, and in response to determining the logical transition has occurred from the second logic value to the first logic value, cause the pull-up circuit and pull-down circuit respectively to enter a first state for a duration of a first portion of a bit period and to enter a second state for a duration of a second portion of the bit period preceding the first portion. 1. An apparatus comprising:an external terminal; and receive a first signal having a first logical value,', 'receive a second signal following the first signal, the second signal having a second logical value different from the first logical value, and', 'drive, in response to receiving the second signal, the external terminal from a first voltage to a second voltage by way of a third voltage, wherein the third voltage is a de-emphasized first voltage based at least in part on a de-emphasis time., 'an output driver coupled to the external terminal, the output driver configured to2. The apparatus of claim 1 , wherein the output driver de-emphasizes the first voltage for two bit periods.3. The apparatus of claim 1 , further comprising a variable delay circuit to introduce a delay interval claim 1 , wherein the delay interval determines the de-emphasis time.4. The apparatus of claim 3 , wherein the delay interval comprises a half bit period to produce a half bit period de-emphasis.5. The apparatus of claim 3 , wherein the variable delay circuit is configured to receive an input signal having first and second logic values claim 3 , and generate a delayed signal that is delayed relative to ...

COMPENSATION CIRCUIT FOR USE WITH INPUT BUFFER AND METHOD OF OPERATING THE SAME

A compensation circuit for use with an input buffer includes an input buffer configured to amplify an input signal and output a compensated signal. A process detector includes a replica of the input buffer. The process detector is configured to output at least one comparison signal indicating a variation in the input buffer. The input buffer controls an output signal based on the at least one comparison signal. 1. A compensation circuit for use with an input buffer , the compensation circuit comprising:an input buffer configured to amplify an input signal and output a compensated signal; anda process detector including a replica of the input buffer, the process detector configured to output at least one comparison signal indicating a variation in the input buffer,wherein the input buffer is configured to control an output signal based on the at least one comparison signal.2. The compensation circuit of claim 1 , wherein the input buffer is configured to control a bias voltage of an output terminal according to the at least one comparison signal.3. The compensation circuit of claim 1 , wherein the input buffer comprises an input buffer differential amplifier configured to receive and differentially amplify a reference voltage and the input signal claim 1 , and the replica comprises a replica buffer differential amplifier including two input terminals to which the reference voltage is applied claim 1 , the replica buffer differential amplifier configured to output a replica voltage.4. The compensation circuit of claim 3 , wherein the input buffer further comprises an output adjust unit configured to decrease a bias voltage of an output terminal when the variation is slow-fast (SF) and to increase the bias voltage of the output terminal when the variation is fast-slow (FS).5. The compensation circuit of claim 3 , further comprising:a first comparator configured to compare the replica voltage with a first reference voltage and output a first comparison signal according ...

ANTI-INTERFERENCE INTEGRATED CIRCUIT

An anti-interference integrated circuit (IC) is adapted for avoiding an error in a frequency pulse caused by the interference of an adjacent IC. The anti-interference IC outputs a first time signal, and the adjacent IC outputs a second time signal. The anti-interference IC includes: a logic circuit, an adder, and a comparator. The logic circuit outputs a gate pulse according to a sequence of the second time signal. The adder adds the first time signal and the gate pulse. The comparator outputs the frequency pulse according to a signal adding result, where the period of the frequency pulse is the same as the period of the first time signal. 1. An anti-interference integrated circuit (IC) , adapted for avoiding an error in a frequency pulse caused by an interference of an adjacent IC , wherein the anti-interference IC outputs a first time signal , the adjacent IC outputs a second time signal , and the anti-interference IC comprises:a logic circuit, receiving the second time signal, and outputting a gate pulse according to a sequence of the second time signal;a comparator, comparing a reference signal with the first time signal, and when the reference signal has a voltage value greater than or equal to a voltage value of the first time signal, outputting a specific frequency pulse; anda logic controller, receiving the gate pulse and the specific frequency pulse, and performing an Exclusive OR operation on the gate pulse and the specific frequency pulse, wherein an operation result is the frequency pulse, and a period of the frequency pulse is the same as a period of the first time signal.2. The anti-interference IC according to claim 1 , further comprising:a constant-on-time (COT) control circuit, outputting a first original time signal according to the period of the frequency pulse, wherein the first original time signal is a digital signal, and is a time signal originally generated when the anti-interference IC is not interfered with by the adjacent IC.3. The anti- ...

COUNTERMEASURE METHOD AND DEVICE FOR PROTECTING DATA CIRCULATING IN AN ELECTRONIC MICROCIRCUIT

The disclosure relates to a countermeasure method in an electronic microcircuit, comprising successive process phases executed by a circuit of the microcircuit, and adjusting a power supply voltage between power supply and ground terminals of the circuit, as a function of a random value generated for the process phase, at each process phase executed by the circuit. 1. A method of making an electronic microcircuit , comprising: 'forming in a substrate an isolated well electrically isolated from an underlying portion of the substrate; and', 'forming a processing circuit configured to execute successive process phases, the forming includingforming a power supply terminal and a ground terminal of the processing circuit, wherein at least one of the power supply and ground terminals is formed in the isolated well; andforming a power supply circuit configured to, at or near each of the successive process phases, dynamically readjust a power supply voltage between the power supply and ground terminals of the processing circuit as a function of a randomly varying signal.2. A method according to claim 1 , wherein forming the power supply circuit includes forming the power supply circuit configured to:detect inactive phases between the successive active phases; andadjust the power supply voltage as a function of the randomly varying signal in response to detecting the inactive phases.3. (canceled)4. A method according to claim 1 , wherein forming the power supply circuit includes forming the power supply circuit configured to adjust a bias voltage between the ground terminal of the circuit and a ground terminal of the microcircuit as a function of a random value claim 1 , a voltage difference between a power supply voltage of the microcircuit and the power supply terminal of the processing circuit being fixed.5. A method according to claim 4 , wherein forming the power supply circuit includes forming the power supply circuit configured to adjust the power supply voltage ...

METHOD FOR MANUFACTURING A DIGITAL CIRCUIT AND DIGITAL CIRCUIT

A method for manufacturing a digital circuit is described including forming a plurality of field effect transistor pairs, connecting the field effect transistors of the field effect transistor pairs such that in response to a first transition from a first state of two nodes of the digital circuit and in response to a second transition from a second state of the nodes of the digital circuit the nodes each have an undefined logic state when, for each field effect transistor pair, the threshold voltages of the field effect transistors of the field effect transistor pair are equal and setting the threshold voltages of the field effect transistors of the field effect transistor pairs such that the nodes each have a predetermined defined logic state in response to the first transition and in response to the second transition. 1. A method for manufacturing a digital circuit comprising:forming a plurality of field effect transistor pairs;connecting the field effect transistors of the field effect transistor pairs such that in response to a first transition from a first state of two nodes of the digital circuit and in response to a second transition from a second state of the nodes of the digital circuit the nodes each have an undefined logic state when, for each field effect transistor pair, the threshold voltages of the field effect transistors of the field effect transistor pair are equal;setting the threshold voltages of the field effect transistors of the field effect transistor pairs such that the nodes each have a predetermined defined logic state in response to the first transition and in response to the second transition;forming one or more pairs of competing paths such that, for each field effect transistor pair, the two field effect transistors are in different competing paths of a pair of competing paths; andconnecting the one or more pairs of competing paths and the nodes such that for each pair of competing paths, the competing paths are connected to different ...

EMBEDDED VENTING SYSTEM

The embodiments relate to integrating a venting system in a circuit board. Three or more interconnected accesses (VIAs) are formed in a printed circuit board (PCB). The VIAs are interconnected by routing a bi-planar channel spanning through the VIAs. The channel includes at least two sections, including a first channel section at a first plane extending from the first VIA to the second VIA and a second channel section at a second plane extending from the second VIA to the third VIA. The first and second sections are at different planar levels. 1. (canceled)2. (canceled)3. (canceled)4. (canceled)5. (canceled)6. (canceled)7. (canceled)8. A system comprising:a printed circuit board (PCB) comprising a first area and a second area, and at least three interconnected accesses (VIAs) bounded by oppositely disposed sides of the PCB, wherein the VIAs are positioned with respect to the first and second areas; and an interconnection of the at least three VIAs; and', 'a channel spanning through the VIAs, the channel comprising at least two sections, including a first section extending from the first VIA to the second VIA and a second section extending from the second VIA to the third VIA, wherein at least one of the first and second sections are positioned within the oppositely disposed sides of the PCB., 'a venting system integrated within the PCB, the venting system comprising9. The system of claim 8 , further comprising the second VIA to connect the first section and the second section at a first bend orthogonal to a first plane associated with the first section claim 8 , and to a second plane associated with the second section.10. The system of claim 9 , wherein each VIA functions as a vent of the venting system claim 9 , and wherein the channel creates an isobaric venting system.11. The system of claim 8 , further comprising:an enclosure to receive at least part of the PCB, wherein the first area of the PCB is positioned within the enclosure and the second area of the PCB ...

Stable Supply-Side Reference Over Extended Voltage Range With Hot-Plugging Compatibility

In one embodiment, the operating range of an over-current detection circuit is extended to higher input voltage levels by providing a reference-voltage generation circuit for the detection circuit with voltage protection circuitry that applies an additional voltage drop to shield other vulnerable transistor devices from the higher input voltages. In addition, bypass circuitry is provided that is inactive at the highest input voltage levels, but actively bypasses at least some of the voltage protection circuitry at relatively low input voltage levels to apply a voltage drop that is sufficient to ensure proper operation of the vulnerable transistor devices at the low voltage levels. In one implementation, the vulnerable transistor devices are NFET devices in a programmable current minor of the reference-voltage generation circuit. In addition, a stiffened voltage divider helps to ensure sufficient voltage drop at the low voltage levels. The protection and bypass circuitry also enable hot-socketing operations. 1310. An integrated circuit having a reference-voltage generation circuit (e.g. , ) comprising:a reference resistor (e.g., Rtrip) connected to an input node (e.g., VIN);{'b': 211', '212', '1', '0', '1, 'a constant current source (e.g., , , NFET, R) configured to generate a constant current signal (e.g., I);'}{'b': 213', '214', '215, 'current mirror circuitry (e.g., , , ) configured to generate a reference current signal based on the constant current signal, wherein the reference current signal is applied to the reference resistor to generate a reference voltage signal (e.g., Vtrip);'}{'b': 320', '322, 'voltage-protection circuitry (e.g., and ) configured to shield the current mirror circuitry from relatively high voltage levels at the input node; and'}{'b': '323', 'bypass circuitry (e.g., ) configured to bypass at least some of the voltage-protection circuitry at relatively low voltage levels at the input node to ensure proper operation of the current mirror ...

SEMICONDUCTOR DEVICE

The disclosed invention provides a semiconductor device capable of suitably controlling the level of an enable signal to resolve NBTI in a PMOS transistor. An input node receives an input signal alternating between high and low levels during normal operation and fixed to a high level during standby. A detection unit receives a signal through the input node and outputs an enable signal. The detection unit sets the enable signal to a low level upon detecting that the input node remains at a high level for a predetermined period. A signal transmission unit includes a P-channel MOS transistor and transmits a signal input to the input node according to control by the enable signal. 16-. (canceled)8. The semiconductor device according to claim 7 ,wherein the charging unit comprises:a constant current source that supplies current to a first node;a MOS transistor that is installed between the first node and ground and on/off controlled in response to the first clock; anda capacitive element installed between the first node and ground,wherein the output unit comprises an inverter that receives a voltage of the first node and the predetermined threshold value is a logical threshold voltage of the inverter.9. A semiconductor device comprising:an input node that receives an input signal alternating between high and low levels during normal operation and fixed to a high level during standby;a detection unit that sets an enable signal to a low level upon detecting that the input node remains at a high level for a predetermined period; anda signal transmission unit that includes P-channel MOS transistors and transmits a signal input to the input node according to control by the enable signal,wherein the signal transmission unit comprises a plurality of stages of inverters to transmit a signal input to the input node, andwherein the semiconductor device further comprises a correction circuit that controls back gate voltages of PMOS transistors comprised in inverters at even stages ...