Level shift circuit

LEVEL SHIFTING CIRCUITRY

High-speed logic circuit

A high-speed logic circuit including a logic part formed of a differential transistor circuit and a feedback part for feeding the in-phase output of the differential transistor circuit back to the out-of-phase input terminal of the differential transistor circuit is disclosed in which a constant current source circuit is provided in the feedback part to keep constant a current flowing through the feedback part.

HIGH-SPEED LOGIC CIRCUIT

ELECTRONIC CIRCUIT

Electronic circuit

VOLTAGE TRANSLATOR

ABSTRACT: "Voltage translator." A bipolar voltage translator contains a pair of differentially-coupled transistors for converting an input voltage supplied to the base of a first (Q1) of the pair into an output voltage taken between a first resistor (R9) and the collector of the second (Q2) of the pair. A second resistor (R12) is coupled between a VEE supply and a current-source transistor (Q4) which supplies current to the differential pair. The current-source transistor is controlled by a reference voltage which equals VEE + (1 + ?) VBE where ? is in the range 0.2 to 3Ø The ratio of the first resistor to the second resistor is desirably .beta./? where .beta. VBE is the output voltage swing. Circuitry such as a Schottky diode (S4) is coupled between the emitters of the differential Pair to prevent the emitter-base junction of the second transistor from break-ing down. Where the transistors are NPN devices and .beta. equals 1, the output voltage is provided at levels suitable for current tree logic.

CIRCUIT DE DECALAGE DE NIVEAU POUR UN CONVERTISSEUR SERIE-PARALLELE

L'invention concerne les circuits de conversion de niveaux logiques TTL en niveaux ECL. Un circuit de conversion 10 conforme à l'invention comporte notamment deux transistors PNP latéraux 23, 25 connectés à une source de courant constant 22 et à deux diodes 28, 29, qui sont respectivement attaqués par une tension de référence et par le signal d'entrée CK ; une paire de transistors NPN miroirs de courant 41, 30 ; des circuits de charge 40, 32 connectés aux collecteurs des transistors NPN ; et des circuits de couplage 39, 35 qui fournissent des signaux de sortie ECL complémentaires CLK, CLK. Application au traitement numérique de signaux audio à haute fidélité. (CF DESSIN DANS BOPI) ...

CIRCUIT ECL POUR CONVERTISSEUR SERIE-PARALLELE

L'INVENTION CONCERNE LES CIRCUITS DE CONVERSION DE NIVEAUX LOGIQUES TTL EN NIVEAUX LOGIQUES ECL. UN CIRCUIT ECL SELON L'INVENTION COMPORTE NOTAMMENT UN PREMIER ETAGE COMPRENANT DES PREMIER ET SECOND TRANSISTORS 76, 77 AVEC DES PREMIERE ET SECONDE RESISTANCES DE CHARGE 78, 79 ET DES PREMIER ET SECOND CIRCUITS A CHARGE D'EMETTEUR 89, 85; UN SECOND ETAGE COMPRENANT DES TROISIEME ET QUATRIEME TRANSISTORS 70, 71 AVEC DES TROISIEME ET QUATRIEME RESISTANCES DE CHARGE 65, 66; AINSI QUE DES MOYENS POUR QUE LE SECOND ETAGE PRODUISE DES EXCURSIONS DE TENSION ECL SUR LES TRANSISTORS 70, 71. APPLICATION AU TRAITEMENT NUMERIQUE DE SIGNAUX AUDIO A HAUTE FIDELITE.

ECL-to-TTL translator circuit with ground bounce protection

An ECL-to-TTL translator circuit for converting ECL logic level signals to TTL logic level signals includes an active pull-down circuit (120), a high level voltage clamping circuit (122), and ground bounce protection circuit (124) so as to provide a higher speed of operation with minimal power dissipation and a significant reduction in ground bounce noise. The ground bounce protection circuit is formed of a voltage-independent current source, a reference resistor (R15), and a switching transistor (Q15).

Input circuit for level-shifting TTL or CMOS to ECL signals

An input circuit which converts an input signal to an output signal. A first level comparator has a first input to which the input signal is applied and a second input to which a first reference voltage is applied for comparison with the input signal, and an output which the output signal is manifested. A second level comparator has a first input connected to the first input of the first level comparator for application one input signal, and a second input to which a second reference voltage is applied for comparison with the input signal, with the second level comparator limiting the voltage at the first input of the first level comparator to substantially the second reference voltage whenever the input signal exceeds the second reference voltage as determined by the second level comparator.

Low frequency loop-back in a high speed optical transceiver

The invention relates to methods and apparatus that provide a low frequency data loop-back in a transceiver to advantageously provide built-in test capability with low overhead. The low frequency loop-back advantageously allows testing of a receiver and a transmitter of the transceiver through a high frequency serial interface while reducing the need to interface to a low frequency interface of the transceiver with expensive and specialized test equipment. One embodiment of the low frequency data loop-back includes a transceiver configured to select between a reference clock signal for normal use of the transceiver and a clock signal generated from serial data for test use in response to an activation of a loop-back test command. In one embodiment, a multiplexer selects between the reference clock signal and the generated clock signal.

LEVEL CONVERTING CIRCUIT

PURPOSE: To attain a circuit form possible for higher speed operation, by decreasing the delay from a TTL logical level to a differential logical level with a quickened output voltage change in a level converting circuit. CONSTITUTION: When an input voltage is a low level, a diode D12 is conductive and a voltage V0 is a low level. Since a voltage between a high and a low level is given to a base of a transistor (TR) Q13 as a reference voltage, a TRQ12 is interrupted and a current IQ12 is a low level. Thus, a voltage VD is a high level voltage VDE determined with the subtraction of a base-to-emitter voltage of the TRQ12 from a power supply voltage VCC (Fig. d). Thus, a high level output voltage VOH at high level is produced to the emitter of a TRQ15 (Fig. e). In this case, since the time constant is much decreased than that of a conventional circuit, high speed operation is made possible. COPYRIGHT: (C)1983,JPO&Japio ...

VOLTAGE CONVERTER

PURPOSE: To convert an ECL input signal into a TTL or a CMOS compatible level without introducing current spike into output signals by preventing the simultaneous conducting in a 1st and a 2nd switching means at the prescribed slew rates of a 1st and a 2nd drive signals. CONSTITUTION: The 1st and the 2nd switching circuit 81 and 110 supply output signals having the 2nd prescribed logic level responding to the 1st and the 2nd converted differentially relevant signals having the 1st and the 2nd single- terminated levels, respectively. Then, in this case, the slew rates of the 1st and the 2nd converted differentially relevant signals prevent simultaneously conducting through the 1st and the 2nd switching circuits 81 and 110. Thus, the ECL input signal is converted into the TTL or the CMOS compatible level without introducing current spike into the output signals. COPYRIGHT: (C)1991,JPO ...

Differentialschaltung mit Bipolartransistoren, die frei von einer Beanspruchung durch eine inverse Basis-Emitter-Überspannung sind

Interface circuit

An interface circuit, particularly for use between a high frequency sine wave and ECL (emitter-coupled logic) logic levels, which has an almost resistive input inpedance. The circuit may comprise an ECL OR/NOR gate (3) with the complementary outputs thereof having respective feedback paths (R2,R1; R3,R1). The high frequency sine wave is supplied via a coaxial cable (4) which is terminated via resistor R1. The feedback resistors R2 and R3 are of the same value. The mark-to-space ratio at the gate outputs is substantially maintained at 50/50. The gate may be AND/NAND rather than OR/NOR. The interface circuit is applicable to any logic family having a switching voltage at the mean of the "0" and "1" voltages.

PREVENTING SATURATION IN ECL LOGIC

An ECL master-slave flip-flop 17 is to be coupled to an ECL latch 7 without the use of the customary emitter follower. To prevent saturation in latch transistors 76, 77 driven by the outputs 13A, 13B of the master-slave flip-flop, diode 98 is connected between ground voltage rail 34 for the latch and voltage rail 97 for the master-slave flip-flop. Diode 98 simulates the effect of using an emitter follower in the output of master-slave flip-flop (that is the output voltage is dropped by one VBE), preventing saturation of transistors 76, 77 and thus increasing their speed. ...

SHIFT IN LEVEL CIRCUIT

INTERFACE CIRCUIT.

INTEGRATED CIRCUIT DEVICE, THE INPUT SIGNALS ACCEPTS AND OUTPUT SIGNALS PRODUCED ON THE HEIGHTS OF DIFFERENT OF LOGICAL CROWDS.

High frequency network transmitter

MULTIPLE SIGNAL LEVEL HIGH SPEED LOGIC CIRCUIT DEVICE

LEVEL SHIFTING CIRCUIT FOR SERIAL/PARALLEL CONVERTER

Data (DATA) and clock (CK) signals at TTL levels are converted to ECL logic levels by a pair of emitter-coupled differential lateral PNP transistors having their collectors coupled to a pair on NPN current mirror circuits. The outputs of the clock circuit drive the bases and emitters of a pair of NPN emitter follower tranistors. Master-slave ECL shift register bit outputs are directly coupled, without emitter followers, to ECL inputs of output latches that drive D/A converter current switches. An ECL one-short circuit produces internal complementary ECL enable signals that enable the output latches. Copyright 1997 KIPO ...

Trigger circuit

The invention relates to methods and apparatus that provide high-speed current pulses. In one embodiment, the trigger circuit provides a current sink pulse as an output. One embodiment of the trigger circuit includes a first input transistor and an output transistor that are emitter coupled to a common resistor. A collector of the first input transistor is alternating current (AC) coupled to a base of the output transistor to drive the output transistor. Advantageously, the AC coupling allows the first input transistor to powerfully drive the output transistor during logic state transitions and yet maintain a low average current. The resistor coupled to the emitter of the first input transistor and the emitter of the output transistor advantageously provides positive feedback or hysteresis feedback, thereby further enhancing the response of the trigger circuit.

Non-saturating bipolar transistor circuit

A non-saturating transistor circuit (11) having a first terminal (13), a control terminal (12), and a second terminal (14). The first terminal (13), control terminal (12), and second terminal (14) correspond respectively to a collector, base, and emitter of a transistor. The non-saturating transistor circuit (11) comprises a voltage divider (15), a diode (19), and a transistor (16). The voltage divider (15) enables the transistor (16) when a voltage is applied across the control terminal (12) and the second terminal (14) of non-saturating transistor circuit (11). The diode (19) removes current drive to the transistor (16) prior to the transistor (16) becoming saturated thus preventing the transistor (16) from saturating under all operating conditions.

APPARATUS FOR SHIFTING A SIGNAL FROM A FIRST REFERENCE LEVEL TO A SECOND REFERENCE LEVEL

SCHNELLE LOGISCHE SCHALTUNG

LEVEL SHIFTING CIRCUITRY FOR SERIAL TO PARALLEL CONVERTER

LOGIC LEVEL TRANSLATORS

... 1520131 Transistor circuits HONEYWELL INFORMATION SYSTEMS Inc 1 July 1975 [1 July 1974] 27676/75 Heading H3T A logic level translator uses a current switch, a current source and a plurality of emitter followers to convert TTL and DTL signal levels into CML and ECL signal levels. The translator provides isolation between the input and output logic earths so that noise in the output is reduced. In the described embodiment T2L signals switching between +0À4V (0 level) and +3À5V (1 level) are translated to CML sigals switching between -0À5V and 0V. When the input at 45 is at +0À4V transistor 24 is cut off and the current flow from T2L earth to -3À3V supply line through resistors 36, 35 produces a voltage difference between points V3, V4 which turns transistor 27 on and transistor 28 off, producing a voltage drop of 0À5V across resistor 39. When the input at 45 switches to +3À5 V transistor 24 turns on, and the current through the resistance network changes to produce a voltage ...

ECL INTERFACE CIRCUIT

SWITCHING CONFIGURATION FOR LEVEL CONVERSION.

MASK-PROGRAMMABLE BUS CONTROL HUSBAND FIELD

ECL CIRCUIT FOR SERIES-PARALLEL

CIRCUIT OF CONVERSION OF TRAINS Of IMPULSES OF DATA SERIES TO RECONSTITUTE an ANALOGICAL SIGNAL

L'INVENTION CONCERNE LA CONVERSION DE TRAINS D'IMPULSIONS REPRESENTANT UN SIGNAL ANALOGIQUE POUR RECONSTITUER UN TEL SIGNAL. LE CIRCUIT CONVERTISSEUR COMPREND NOTAMMENT : A. UN CIRCUIT CONVERTISSEUR NUMERIQUE-ANALOGIQUE A N BITS 3 COMPORTANT N ENTREES NUMERIQUES 8-1, ... 8-16 ET UNE SORTIE 3A; B. N CIRCUITS DE MEMORISATION 7-1, ... 17-16; C. UN REGISTRE A DECALAGE A N BITS 17, COMPRENANT N CIRCUITS DE BIT MAITRE-ESCLAVE 17-1, ... 17-16; D. DES MOYENS QUI REAGISSENT A UN SIGNAL D'HORLOGE CONTINU CK EN ATTAQUANT CONTINUELLEMENT LES ENTREES D'HORLOGE DES CIRCUITS DE BIT MAITRE-ESCLAVE 17-1, ... 17-16; E. UN CIRCUIT DE RETARD 16; ET F. DES MOYENS 5 DESTINES A VALIDER LES CIRCUITS DE MEMORISATION 7-1, ... 7-16. APPLICATION AU TRAITEMENT NUMERIQUE DES SIGNAUX AUDIO A HAUTE FIDELITE. THE INVENTION RELATES TO THE CONVERSION OF PULSE TRAINS REPRESENTING AN ANALOGUE SIGNAL TO RECONSTITUTE SUCH A SIGNAL. THE CONVERTER CIRCUIT INCLUDES IN PARTICULAR: A. A DIGITAL-ANALOGUE CONVERTER CIRCUIT WITH N BITS 3 INCLUDING N DIGITAL INPUTS 8-1, ... 8-16 AND ONE OUTPUT 3A; B. N MEMORIZATION CIRCUITS 7-1, ... 17-16; C. AN OFFSET REGISTER WITH N BITS 17, INCLUDING N MASTER-SLAVE BIT CIRCUITS 17-1, ... 17-16; D. MEANS THAT RESPOND TO A CONTINUOUS CLOCK SIGNAL CK BY CONTINUOUSLY ATTACKING THE CLOCK INPUTS OF THE MASTER-SLAVE BIT CIRCUITS 17-1, ... 17-16; E. A DELAY CIRCUIT 16; AND F. MEANS 5 DESTINES TO VALIDATE MEMORIZATION CIRCUITS 7-1, ... 7-16. APPLICATION TO DIGITAL PROCESSING OF HIGH-FIDELITY AUDIO SIGNALS.

CIRCUIT DE CONVERSION DE TRAINS D'IMPULSIONS DE DONNEES SERIE POUR RECONSTITUER UN SIGNAL ANALOGIQUE

L'INVENTION CONCERNE LA CONVERSION DE TRAINS D'IMPULSIONS REPRESENTANT UN SIGNAL ANALOGIQUE POUR RECONSTITUER UN TEL SIGNAL. LE CIRCUIT CONVERTISSEUR COMPREND NOTAMMENT : A. UN CIRCUIT CONVERTISSEUR NUMERIQUE-ANALOGIQUE A N BITS 3 COMPORTANT N ENTREES NUMERIQUES 8-1, ... 8-16 ET UNE SORTIE 3A; B. N CIRCUITS DE MEMORISATION 7-1, ... 17-16; C. UN REGISTRE A DECALAGE A N BITS 17, COMPRENANT N CIRCUITS DE BIT MAITRE-ESCLAVE 17-1, ... 17-16; D. DES MOYENS QUI REAGISSENT A UN SIGNAL D'HORLOGE CONTINU CK EN ATTAQUANT CONTINUELLEMENT LES ENTREES D'HORLOGE DES CIRCUITS DE BIT MAITRE-ESCLAVE 17-1, ... 17-16; E. UN CIRCUIT DE RETARD 16; ET F. DES MOYENS 5 DESTINES A VALIDER LES CIRCUITS DE MEMORISATION 7-1, ... 7-16. APPLICATION AU TRAITEMENT NUMERIQUE DES SIGNAUX AUDIO A HAUTE FIDELITE.

Circuit for converting a logical signal into two balanced logical signals

A circuit receives an input logical signal of one polarity and converts it into two balanced logical output signals of the opposite polarity. The circuit comprises two resistors connected between a reference potential source of the polarity of the output signals and the terminals at which the output signals are provided. The circuit also comprises a current source. Each resistor has a resistance value such that when it is traversed by the current from the current source the potential difference between its ends is equal to the difference between the two possible potential levels of the output signals. A differential switching device responds to the input signal being at a first potential level by connecting one of the output terminals to the current source and isolating the other output terminal from the current source, and vice versa when the input signal is at a second potential level.

Output circuit

In an output circuit, there are provided a first transistor connected to an output terminal and a first resistor element connected to the first transistor. A second transistor is connected in cascade to the first transistor. A second resistor element is connected between the second transistor and the ground. An emitter follower having a level shift function is connected to the first and second transistors. There are also provided an input circuit which inputs a first input signal and a second input signal to the emitter follower. The first and second input signals are opposite to each other in phase.

System and method of tuning a voltage controlled oscillator

A voltage controlled oscillator in a clock multiply unit includes a plurality of varactors controlled by a plurality of respective control voltage signals. The plurality of varactors allows for a combination of efficient methods to set an output signal frequency for the voltage controlled oscillator. For example, a pair of independent varactors are controlled by a differential control voltage signal. Differential control improves noise immunity and fine tuning ranges of the voltage controlled oscillator. The voltage controlled oscillator determines an operating frequency range automatically at start-up or upon reset. For example, a digital coarse tuning circuit starts the voltage controlled oscillator oscillating at a frequency corresponding to a frequency in a lowest range of operating frequencies, compares an output generated by the voltage controlled oscillator with a reference signal, increases the oscillation frequency to a frequency in the next higher range if the frequency of the ...

SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE

PURPOSE: To form an input buffer circuit and an output buffer circuit in a small occupation area by interposing a peripheral buffer circuit including a current- driven element between an internal logic circuit and an input terminal or an output terminal. CONSTITUTION: When an input logical signal of an ECL level is given to an input buffer circuit 30, which consists of a constant current circuit Is and a pair of bipolar transistors TRs Q1 and Q2 which have emitters coupled to each other and constitute a differential pair, through an input terminal pad Pin, this signal is inputted to a CMOS internal logic circuit 20 after input level conversion. Meanwhile, a CMOS level output logical signal from the internal logic circuit 20 is given to an output buffer circuit 40 consisting of a constant current circuit Is' and a pair of bipolar TRs Q3 and Q4 which have emitters coupled to each other and constitute a differential pair. The signal converted to an output signal of the ECL level is led out ...

SCHNITTSTELLENSCHALTUNG.

SWITCHING CONFIGURATION FOR THE REINFORCEMENT OF ELECTRICAL SIGNALS.

Level shift circuit

TTL-TO-ECL INPUT TRANSLATOR/DRIVER CIRCUIT

TTL-TO-ECL INPUT TRANSLATOR/DRIVER CIRCUIT The present invention provides a high speed low power electrical circuit for converting true TTL level signals to true ECL level signals. The circuit only has a single buffer delay with some small additional delay due to an input emitter follower stage. The circuit includes a clamped, switched emitter follower which acts as a level shifting comparator; a selfcentering reference threshold translator; a clamped level shifted input translator; and, an ECL Buffer Driver. The circuit also includes a TTL reference and an ECL reference which are tied together. If the TTL reference level shifts slightly due to temperature changes, supply voltage shifts or other factors, the ECL voltage reference will automatically shift by an appropriate percentage to compensate for the original shift in the TTL reference. T7/10577-131 ...

LOGIC LEVEL TRANSLATOR OR CML-T2L USED IN ALL CML TECHNOLOY

CIRCUIT CONVERTER OF LOGICAL LEVELS HAS THREE STATES

CIRCUIT SYSTEM

The invention relates to a circuit system comprising a device (102) for selecting a first and a second memory unit by means of a differential selection signal. Said differential selection signal comprises a first selection signal and a second selection signal inverted relative to the first selection signal. The circuit system also comprises a differential selection signal line (120) that has a first signal line (122) for guiding the first selection signal and a second signal line (124) for guiding the second selection signal. The first circuit unit (104) is linked with the device (102) for selection via the first signal line (122) and the second circuit unit (106) is linked therewith via the second signal line (124).

ECL-TTL level converting circuit

An ECL-TTL level converting circuit comprises a first transistor having a collector connected to a ground line and an emitter connected to a negative voltage line through a constant current source, and a second transistor having a collector connected to a positive voltage line through a first resistor and an emitter commonly connected to the emitter of the first transistor. The base of one of the first and second transistors is connected to receive a reference voltage, and the base of the other of the first and second transistors is connected to receive an input signal. A third transistor is connected at its base to the collector of the second transistor and at its collector to the positive voltage line through a second resistor. An emitter of the third transistor is connected to the ground line through a third resistor and also connected to a base of a fourth transistor having an emitter connected to the ground line. A collector of the third transistor is connected to a base of a fifth ...

Level shift circuit for interfacing between two different voltage levels using a current mirror circuit

A novel translator for translating linear logic signal levels to TTL-compatible levels in an integrated logic device having an I/O section including a mix of ECL and TTL circuit. The translator includes a resistive circuit connected to a current mirror and a linear buffer circuit connected between the resistive circuit and current mirror. The linear buffer responds to a linear logic signal by switching a current into and out of a portion of the resistive circuit which is added to or subtracted from the current mirror current flowing through the resistive network. The resulting variable current causes the resistive network to produce a TTL-compatible control voltage signal which drives a TTL buffer, causing it to produce standard TTL signals in response to linear logic signals applied to the linear buffer.

Common mode logic line driver switching stage

A line driver switching stage includes a terminal for a reference potential, a terminal for a supply potential, and an output terminal of the line driver switching stage. A differential amplifier has a first and a second amplifier branch. The first amplifier branch has a resistor with first and second terminals. The first terminal of the resistor is the terminal for the reference potential. An emitter follower transistor has an emitter and has a base-to-emitter path connected between the second terminal of the resistor and the output terminal. A saturation prevention element has a first terminal connected to the output terminal and a second terminal connected to the second amplifier branch. A bipolar transistor has a base-to-emitter path connected between the second terminal of the saturation prevention element and the terminal for the supply potential. The bipolar transistor has a collector connected to the emitter of the emitter follower transistor.

PROGRAMMABLE TERMINATION RESISTOR FOR HDMI TRANSMITTER OUTPUT

A supply-less transmitter output termination resistor with high accuracy is presented. This termination resistor can be used for applications with high supply voltage and low voltage devices. The termination resistor is programmable and includes many parallel branches. Each branch can be turned off or on with a switch. The biasing for the switch is in such a way that it keeps the resistance of the switch constant independent of the supply voltage or the output common mode voltage. This will increase the accuracy of the termination resistor. Besides HDMI this technique can be used for many other applications.

Logic translator circuit

A Logic translator circuit includes a TTL input stage (20), a translation chain (22), a first CML differential pair (24), a level shifter (26), and a second CML differential pair (28). The first CML differential pair (24) is coupled between a TTL ground potential (GTTL) and a negative supply potential (VEE). The second CML differential pair (28) is connected between a CML ground potential (GCML) and the negative supply potential. The level shifter (26) serves to electrically isolate the TTL ground potential and the CML ground potential, thereby producing relatively noise free CML-compatible output signals. ...

Circuit having level converting circuit for converting logic level

TTL-to-ECL input translator/driver circuit

The present invention provides a high speed low power electrical circuit for converting true TTL level signals to true ECL level signals. The circuit only has a single buffer delay with some small additional delay due to an input emitter follower stage. The circuit includes a clamped, switched emitter follower (R1, Q1, Q2, Q3) which acts as a level shifting comparator; a selfcentering reference threshold translator (Q7, Q8, Q10, Q15, R5, R6, R12); a clamped level shifted input translator (Q4, Q5, Q14, R3, R4, R10); and, an ECL Buffer Driver (Q11, Q12, Q13, R7, R8, R11). The circuit also includes a TTL reference (D2, Q6, Q9, R2) and an ECL reference (Q7, Q8, R5, R6) which are tied together. If the TTL reference level shifts slightly due to temperature changes, supply voltage shifts or other factors. the ECL voltage reference will automatically shift by an appropriate percentage to compensate for the original shift in the TTL reference.

SCHALTUNGSANORDNUNG ZUR VERSTAERKUNG VON ELEKTRISCHEN SIGNALEN

TRUE TTL TO TRUE ECL BI-DIRECTIONAL TRI-STATABLE TRANSLATOR DRIVER CIRCUIT

Abstract The present invention provides an integrated circuit that has both driver and receiver functions. The circuit of the present invention has two interrelated parts. The first part of the circuit converts true TTL signals to true ECL signals. The second part of the circuit accepts true ECL signals and drives a tri-state true TTL bus. The novel design of the present invention provides a common circuit that acts as an input reference for the circuit that converts true TTL signals to true ECL signals and as a tri-state clamp for the circuit that accepts true ECL signals and drives a tri state true TTL bus. Using the same circuit components to perform functions in two separate circuits reduces the component count of the resulting circuit and increases the circuit's power/device count figure of merit. File 10577-13B Page

TRUE TTL OUTPUT TRANSLATOR-DRIVER WITH TRUE ECL TRI-STATE CONTROL

The present invention provides a circuit for driving a TTL bus from an ECL circuit. The circuit of the present invention speeds up the "tri-state" to "active" transition by eliminating the need to pass the tri-state signal through a translator and buffer. A tri-state control circuit accepts true ECL input directly, thus eliminating the delay, power and density "cost" of the translator and buffer circuits. This circuit further improves the delay performance of tri-state/active transitions by restricting device saturation to low levels. File 10577-137 ...

LOGICAL CONVERTER OF LEVEL

VOLTAGE LEVEL CONVERTER

The TTL to ECL level converter whose input comprises emitter coupled pair to improve the level converting speed receives the TTL level input data whose level is medium state at base of a transistor (Q1). When the input TTL level is high, the current flows from an active pull-up transistor of the TTL circuit through a resistor (R3), but flows to an active pull-down transistor of the TTL circuit through a transistor (Q3) and resistor (R4) when the level is low. The TTL level received to the transistor (Q1) is compared with a reference level applied to base of a transistor (Q2) and converted to inner voltage level to provide the ECL level signal through a level shifting circuit, Copyright 1997 KIPO ...

Circuit for converting two balanced ECL level signals into an inverted TTL level signal

A circuit for converting ECL logical signals into TTL logical signals comprises a differential amplifier defining two current paths leading to a negative reference potential source. When the ECL input signal is logical zero, the first current path is closed and the second current path is open, and vice versa when the input signal is logical one. A first transistor has its base connected to the first current path and its emitter connected to a positive reference potential source, and is biased by a load resistor connected to the first current path. A second transistor has its emitter connected to the collector of the first transistor and its base connected to the second current path, and is biased by a second resistor. When the input ECL signal is logical one, the first current path is open and the first and second transistors are on and off respectively, the potential at the output terminal of the circuit being limited by a clamping diode connected between the base and collector of the ...

Input buffer circuit

An input buffer circuit. In one embodiment, the input buffer circuit includes a first transistor operable to receive a first input signal, a second transistor operable to receive a second input signal, and a first mechanism coupled to the first transistor and to the second transistor. The first mechanism is operable to control the first and second transistors such that the first and second transistors can receive either single-ended input signals or differential input signals. According to the embodiments disclosed herein, the input buffer combines single-ended input and differential input functionalities without compromising performance.

Bipolar receiver with ECL to CMOS logic level conversion

A bipolar receiver which generates relatively large output voltage transitions. Current mirror regulated current steered by an ECL switch is mirrored to output transistors, allowing the output node to operate within one Vbe of the supply without saturation of the receiver transistors.

Circuit for converting ECL level signals to MOS level signals

A transistor circuit has a first and a second transistor differentially connected with each other and having bases receiving an input signal therebetween; a first and a second resistor respectively connected between collectors of the first and second transistors and a first power supply terminal; a third transistor having an emitter receiving a voltage dropped by the first resistor and a collector connected to an output terminal; a fourth transistor having an emitter receiving a voltage dropped by the second resistor; and a fifth transistor having a collector connected to the output terminal and an emitter connected to the second power supply terminal. Biasing voltages are provided to bases of the third and fourth transistors thereby causing the fourth transistor to be conductive when the voltage dropped by the first resistor is larger than the voltage dropped by the second resistor and causing the third transistor to be conductive when the voltage dropped by the first resistor is smaller ...

Output circuit

In an output circuit, there are provided a first transistor connected to an output terminal and a first resistor element connected to the first transistor. A second transistor is connected in cascade to the first transistor. A second resistor element is connected between the second transistor and the ground. An emitter follower having a level shift function is connected to the first and second transistors. There are also provided an input circuit which inputs a first input signal and a second input signal to the emitter follower. The first and second input signals are opposite to each other in phase.

Phase frequency detector

A phase frequency detector in a clock multiply unit of a serial transmitter detects differences in phase and frequency between a reference clock and an internal clock generated by the clock multiply unit. The phase frequency detector includes a reset circuit which increases the sensitivity and reliability of the phase frequency detector, thereby allowing the phase frequency detector to operate at high speeds. The phase frequency detector produces a pair of output signals which have rising edges corresponding to rising edges of the reference clock and the internal clock respectively. The reset circuit activates a reset signal to reset the phase frequency detector when the output signals are both at logic high and continues to activate the reset signal until both of the output signals reach logic low.

Voltage Level Shifting Circuitry

Various implementations described herein refer to an integrated circuit having a first stage and a second stage. The first stage has first transistors arranged as a diode, a first latch and feedback assist to facilitate shifting an input voltage in a first voltage domain to an output voltage in a second voltage domain. The first stage uses the diode and the first latch to reduce contention between the first latch and input transistors. The diode, the first latch and the feedback assist enable activation of the input transistors with the input voltage. The second stage has second transistors arranged as a second latch followed by output buffers that provide a buffered output voltage as feedback to the feedback assist of the first stage. 1. An integrated circuit , comprising:a first stage having a diode, a first latch and a feedback assist circuit, wherein the first stage facilitates shifting an input voltage in a first voltage domain to an output voltage and a buffered output voltage, wherein the output voltage and the buffered output voltage are in a second voltage domain that is greater than the first voltage domain,wherein the diode is coupled between a source voltage and the first latch, wherein the first latch is coupled between the diode and first input transistors, wherein the feedback assist circuit is coupled between the source voltage and the first input transistors, wherein the first input transistors are activated by the input voltage, and wherein the feedback assist circuit provides the output voltage when activated by the buffered output voltage; anda second stage having second input transistors and a second latch along with output buffers that provide the buffered output voltage as feedback to enable activation of the feedback assist circuit of the first stage,wherein the second latch is coupled between the source voltage and the second input transistors, and wherein the second input transistors are activated by the output voltage from the first assist ...

Phase alignment of data to clock

A phase alignment circuit in a serial transmitter aligns a parallel input data stream to a first transmission clock before conversion to a serial output data stream using a second transmission clock which is a multiple of the first transmission clock. The phase alignment circuit introduces less delay, i.e., the output of the phase alignment circuit lags the input of the phase alignment by a few number of clock cycles (e.g., less than 2 clock cycles). The phase alignment circuit demultiplexes the input data stream into a plurality of intermediate data streams using a plurality of multi-phase clocks referenced to a data clock and multiplexes the plurality of intermediate data streams using sequence signals referenced to the first transmission clock. The sequence signals are initialized according to a reset condition and at least one of the multi-phase clocks.

TEMPERATURE COMPENSATED TTL TO ECL TRANSLATOR

A temperature compensated differential level shift circuit (Fig. 2). An ECL type buffered differential circuit employs a source of threshold voltage, VT (Fig. 3), which matches the temperature-dependent characteristic of the input section of the level shift circuit. In a preferred embodiment, s Schottky diode (52) is provided in the output section of a bandgap reference voltage generator (Fig. 3) which matches the temperature dependence of a Schottky diode (30) in the input section of the level shift circuit (Fig. 2). As temperature shifts, the threshold voltage will shift in a manner that tracks the temperature-produced shift in the input voltage as it passes through the Schottky diode in the input section of the level shift circuit. Matched PNP or NPN transistors (70, 72 and 71, 73 ) may also be used in the input section of the level shift circuit (Figs. 6A, 7A) and in the output section of the bandgap reference voltage generator (Figs. 6B, 7B).

Differential circuit implemented by bipolar transistors free from excess base-emitter reverse bias voltage

ELECTRONIC CIRCUIT

PURPOSE: To prevent malfunction due to potential fluctuations in signal transition, by providing a capacitor between a prescribed reference voltage terminal and an optional stable voltage terminal in a level converting circuit which includes a circuit performing level discrimination on the basis of a prescribed reference voltage and another circuit operating at a different power voltage from that of the said circuit. CONSTITUTION: Between reference potential terminal 0V and negative power voltage terminal -VEE, resistances R1 and R2, diodes Q7 and Q8, and resistance R3 are provided to constitute a voltage dividing circuit, and then a reference voltage for discrimination between Emitter Coupled Logic (ECL) levels [0] and [1] is obtained through the base and emitter of transistor TRQ5 whose base connects with the connection point of resistances R1 and R2 to discriminate level ECL applied to the base of TRQ2, so that a level conversion output will be obtained from the collector of output TRQ13 ...

ECL CLOCK DRIVE CIRCUIT

Logic interface circuit

Differential level shifting circuit

The invention relates to an electronic circuit, and in particular embodiments to a level shifting circuit having an output common mode voltage independent of the input common mode voltage, and unity differential signal gain. The circuit receives first and second input voltage V1,V2 referenced to a first voltage supply rail, and has first and second resistors 6,18 each connected to the first input terminal, and third and fourth resistors 20,10, each connected to the second input terminal, the second and third resistors having equal resistance values. The first resistor is also connected to a first output terminal, the fourth resistor is also connected to a second output terminal, and the second and third resistors 16,20 are also connected together at a reference node 16. A first current source 8 draws a current through the first resistor 6, a second current source 12 draws a current through the fourth resistor 10, and a third current IQ source draws a current through the ...

LOGIC INTERFACE CIRCUIT

LOGIC LEVEL TRANSLATORS

... 1518455 Transistor logic circuits HONEYWELL INFORMATION SYSTEMS Inc 25 March 1976 [26 March 1975] 12055/76 Heading H3T A logic level translating circuit comprises: an emitter coupled logic stage 1 fed with signals at the first logic level, energized from a logic level power supply and having an output transistor Q2; a TTL circuit 3 fed from the collector of Q2 and energized from a second logic level power supply; and a clamp circuit 4 connected to the collector of the transistor Q2 to limit current flow through that transistor. If a logical "I" at -0À5v is applied to V IN , Q1 is cut off, the Q2 conducts providing a current path from the + 5v supply line through R4, Q2 to the -3À3v supply line. Circuit 4 clamps point V2 to 0À3v so that transistor Q3 is off, thus turning off transistor Q6. The voltage at V3 turns on Q4 completing a current path from the + 5v line through R7, SD3, Q4, R9 to TTL earth to turn on Q5 and produce a TTL logic "1" level of 3À5v at V OUT . Since the lower value ...

LOGICAL CONVERTER OF LEVEL

High speed logic level converter

A two branch circuit for converting dual complementary signals characterizing emitter coupled logic to a single signal characterizing transitor-transistor logic. A two branch circuit supplies translation between ECL input signals, referenced to a voltage supply and TTL output signals, referenced to ground, using a current summing node receiving current from both branches and connected to a TTL output driver. A first circuit branch includes a feedback loop which generates a reference current summed with the current in the second branch.

Two-stage multiplier circuit

The invention relates to methods and apparatus that receive an integration result, receive logic states of data bits corresponding to the integration result, and perform a high-speed multiplication operation. Embodiments of the invention selectively multiply the integration result according to the logic states of the corresponding data bits. Advantageously, relatively large integration results corresponding to data bit transitions that do not include a change of logic states, such as logic 0 to logic 0 or logic 1 to logic 1, can be multiplied by zero (0). Relatively smaller integration results corresponding to integrations of data bit transitions including a change in logic states, such as from logic 0 to logic 1 or from logic 1 to logic 0, can be multiplied by one (1) and by negative one (−1).

LEVEL SHIFT CIRCUIT

PURPOSE: To make a level shift circuit that is adaptable for any kind of use and suitable for conversion into integrated circuit by constituting a level shift circuit which requires no bias power source and making it not to give influences to the dynamic range of the latter stage circuit. COPYRIGHT: (C)1977,JPO&Japio ...

CMOS-SCHALTSTUFE

Level shift circuit with feedback

A level shift circuit operates to shift the level of an input signal to produce a desired common mode signal level. A differential input circuit 12,14 is connected to a differential output circuit 26,28. The voltage detected at a node C connected to resistors 30,32 and transistor 34 represents the common mode level of the output signals and is fed back to one input of an operational amplifier 40 which also receives a reference voltage Ref which may be fixed or modulated. The feedback loop includes current mirrors 44,46,48 coupled to control nodes A,B. The output common mode level may alternatively be detected directly, and other circuit configurations are described. MOS transistors may be used.

INTERFACE TRANSMITTER

... 1277089 Computer interface transmitter MULLARD Ltd 23 May 1969 26507/69 Heading H3T A transistorized computer interface transmitter comprises an input long-tail pair phase splitter D.C. coupled to a long-tail pair output stage and means to cause the supply voltage for the loads of the phase splitter to follow variations relative to the earth rail of the emitter supply to the output stage. Variations in the earth rail voltage may thus be prevented from varying the biasing level of transistors. As shown, the input, which may be derived from a T.T.L. logic circuit, is applied via transistors TR1, TR2 and level shifter Z 1 to a long-tail pair phase splitter TR4, TR8, TR10, driving an output stage TR5, TR9, TR7 via an intermediate stage TR3, TR11 and level shifters Z2, Z5. The supply for the collectors of the phase splitter transistors is derived from the emitter of TR6, the base of which is held fixed in relation to the negative rail by diodes D8- D11 and Z7. The increase in saturation voltage ...

METHOD AND APPARATUS FOR COUPLING AN ECL OUTPUT SIGNAL USINGA CLAMPED CAPACITIVE BOOTSTRAP CIRCUIT

METHOD AND APPARATUS FOR COUPLING AN ECL OUTPUT SIGNAL USING A CLAMPED CAPACITIVE BOOTSTRAP CIRCUIT ABSTRACT A method and apparatus for providing ECL output signals to a capacitative load includes differential amplification of input signals with a first output of a differential amplifier connected for establishing a voltage level between voltage limits Vcc and Vee at the output of an output driver in response to variations in the first amplifier output. A pull-down transistor has a collector connected to the output driver output, an emitter connected to the Vee voltage source, and a base coupled through a boost capacitor to the second amplifier output. A voltage clamp embracing a clamp transistor with a base connected to receive a predetermined control voltage has an emitter connected to the boost capacitor and the pull-down transistor base and a collector connected to the Vcc voltage source. The clamp transistor is operated in Darlington configuration to provide a minimum discharge impedence to the base of the pull-down transistor. A recovery capacitor is connected between the clamp transister base and the first amplifier output to speed up the clamp transistor's operation.

LOGIC LEVEL TRANSLATOR OR CML-T2L USED IN ALL CML TECHNOLOY

LOGIC LEVEL TRANSLATOR A logic level translator utilizes a TTL logic gate, a current switch, and a clamp circuit to convert CML level binary signals into TTL level binary signals. The translator provides isolation between the TTL ground and the CML ground in order to reduce noise in the CML portion of the circuit. The clamp circuit prevents a switching transistor in the current switch from reaching saturation, therby increasing the speed of operation of the translator. A portion of the current switch provides a quick pulldown of a switching transistor in the TTL circuit to reduce noise in the TTL circuit.

DEVICE HAS JUST CIRCUITS HAS SEMICONDUCTOR

CIRCUIT OF SHIFT OF LEVEL FOR A PARALLEL SERIAL CONVERTER

L'invention concerne les circuits de conversion de niveaux logiques TTL en niveaux ECL. Un circuit de conversion 10 conforme à l'invention comporte notamment deux transistors PNP latéraux 23, 25 connectés à une source de courant constant 22 et à deux diodes 28, 29, qui sont respectivement attaqués par une tension de référence et par le signal d'entrée CK ; une paire de transistors NPN miroirs de courant 41, 30 ; des circuits de charge 40, 32 connectés aux collecteurs des transistors NPN ; et des circuits de couplage 39, 35 qui fournissent des signaux de sortie ECL complémentaires CLK, CLK. Application au traitement numérique de signaux audio à haute fidélité. (CF DESSIN DANS BOPI) The invention relates to circuits for converting TTL logic levels into ECL levels. A conversion circuit 10 according to the invention comprises in particular two lateral PNP transistors 23, 25 connected to a constant current source 22 and to two diodes 28, 29, which are respectively driven by a reference voltage and by the signal of CK entry; a pair of NPN current mirror transistors 41, 30; load circuits 40, 32 connected to the collectors of the NPN transistors; and coupling circuits 39, 35 which provide complementary ECL output signals CLK, CLK. Application to the digital processing of high fidelity audio signals. (CF DRAWING IN BOPI)

CONVERTER OF LOGICAL LEVELS

CIRCUIT ECL FOR PARALLEL SERIAL CONVERTER

CIRCUIT CONVERTISSEUR DE NIVEAUX LOGIQUES A TROIS ETATS

LE CIRCUIT CONVERTISSEUR DE NIVEAUX LOGIQUES SELON L'INVENTION COMPORTE UN PREMIER ETAT E BAS, E BAS PRODUISANT UN NIVEAU HAUT EN SORTIE TTL S, UN DEUXIEME ETAT E HAUT, E BAS PRODUISANT UN NIVEAU BAS EN SORTIE S ET UN TROISIEME ETAT E HAUT D'IMPEDANCE TRES ELEVEE, DANS LEQUEL LES DEUX TRANSISTORS DE SORTIE T ET T SONT BLOQUES. LE COURANT D'UNE SOURCE DE COURANT I EST AIGUILLE PAR DES TRANSISTORS T, T, T, T ET T. DANS LE DEUXIEME ET LE TROISIEME ETAT, UNE DIODE D PONTANT LES BASES DES TRANSISTORS T ET T - POINTS A ET B - EST CONDUCTRICE, ALORS QU'UNE DIODE D CONNECTEE ENTRE LA MASSE ET LE POINT A EST CONDUCTRICE DANS LE TROISIEME ETAT.

Operational amplifier, driving interface, measurement and control device, driving circuit and driver

An operational amplifier, a driving interface, a measurement and control device, a driving circuit and a driver are provided. The operational amplifier is used as at least one of an input interface and output interface, and when the operational amplifier corresponds to one transistor (Q), an external circuit of the transistor further includes: a first port (Vdj), connected with a base (B) of the transistor (Q) through a first resistor (Rb); a second port (I/Oe), connected with an emitter E of the transistor (Q); a third port (I/Oc), connected with a collector (C) of the transistor (Q); and a fourth port (GND), connected with the emitter (E) of the transistor (Q) through a second resistor and used as a public port for signal input and signal output.

TTL-ECL Input translation with AND/NAND function

A new and improved translation circuit that accepts TTL signals and converts them to ECL levels while performing an AND/NAND function is provided, comprising at least two emitter-coupled transistor pairs, each coupled to an input terminal for receiving corresponding TTL signals and coupled to one another for performing the AND operation. Each emitter-coupled pair is also coupled to a bias drive for providing reference voltages that designate which one of each of the transistor pairs conducts, depending upon the state of the TTL signal received.

Semiconductor integrated circuit device for converting PECL-signal into TTL-signal

A semiconductor integrated circuit device has a first ground to which a first circuit is connected and whose level is fluctuate due to noise and a second ground to which a second circuit, which provides an output to the first circuit, is connected and whose level is stable. The semiconductor integrated circuit device includes a fluctuation detecting unit for detecting a fluctuation in the level of the first ground according to the level of the second ground serving as a reference; and a level controlling unit for controlling the level of the output of the second circuit, to cancel the fluctuation detected by the fluctuation detecting unit. The semiconductor integrated circuit device detects a fluctuation in the level of the first ground, which is easily affected by noise, according to the level of the second ground, which is stable, and controls the level of the output of the second circuit, to cancel the detected fluctuation. Consequently, this semiconductor integrated circuit device reduces ...

TTL output translator driver with ECL tristate control

The present invention provides a circuit for driving a TTL bus from an ECL circuit. The circuit of the present invention speeds up the "tri-state" to "active" transition by eliminating the need to pass the tri-state signal through a translator and buffer. A tri-state control circuit (13) accepts true ECL input directly, thus eliminating the delay, power and density "cost" of the translator and buffer circuits. This circuit further improves the delay performance of tri-state/active transitions by restricting device saturation to low levels.

Interface circuit

A conversion circuit for converting a high-speed continuous serial flow of data pulses into a reconstructed analog signal

Inverter circuit arrangement

An inverter circuit arrangement that connects an IO-link master with a slave includes an AB class transistor circuit of which the currents are replicated by a current mirror to a terminal of the slave. A bias circuit provides bias voltages to the AB class transistors. A comparator forms a feedback between the master and slave terminals. The circuit provides for a bidirectional inversion to make a slave device IO-link compatible.

LOAD CURRENT COMPENSATION FOR ANALOG INPUT BUFFERS

Systems and methods for load current compensation for analog input buffers. In various embodiments, an input buffer may include a first transistor (Q) having a collector terminal coupled to a power supply node and a base terminal coupled to a first input node (v); a second transistor (Q) having a collector terminal coupled to an emitter terminal of the first transistor (Q); a third transistor (Q) having an emitter terminal coupled to an emitter terminal of the second transistor (Q) and to a ground node, a collector terminal coupled to a current source (I), and a base terminal coupled the collector terminal and to a base terminal of the second transistor (Q); and a capacitor (C) coupled to the base terminals of the second and third transistors (Qand Q) and to a second input node (v), wherein the first and second input nodes (vand v) are differential inputs. 1. An input buffer , comprising:{'sub': 1', 'inp, 'a first transistor (Q) having a collector terminal coupled to a power supply node and a base terminal coupled to a first input node (v);'}{'sub': 2', '1, 'a second transistor (Q) having a collector terminal coupled to an emitter terminal of the first transistor (Q);'}{'sub': 3', '2', 'bias', '2, 'a third transistor (Q) having an emitter terminal coupled to an emitter terminal of the second transistor (Q) and to a ground node, a collector terminal coupled to a current source (I), and a base terminal coupled the collector terminal and to a base terminal of the second transistor (Q); and'}{'sub': 1', '2', '3', 'inn', 'inp', 'inn, 'a capacitor (C) coupled to the base terminals of the second and third transistors (Qand Q) and to a second input node (v), wherein the first and second input nodes (vand v) are differential inputs.'}2. The input buffer of claim 1 , wherein an output node (v) between the emitter terminal of the first transistor (Q) and the collector terminal of the second transistor (Q) is coupled to an input of an analog-to-digital converter (ADC).3. The ...

Operational Amplifier, Driving Interface, Measurement and Control Device, Driving Circuit and Driver

An operational amplifier, a driving interface, a measurement and control device, a driving circuit and a driver are provided. The operational amplifier is used as at least one of an input interface and output interface, and when the operational amplifier corresponds to one transistor (Q), an external circuit of the transistor further includes: a first port (Vdj), connected with a base (B) of the transistor (Q) through a first resistor (Rb); a second port (I/Oe), connected with an emitter ε of the transistor (Q); a third port (I/Oc), connected with a collector (C) of the transistor (Q); and a fourth port (GND), connected with the emitter (E) of the transistor (Q) through a second resistor and used as a public port for signal input and signal output. 1. An operational amplifier , comprising a transistor , wherein the operational amplifier is used as at least one of an input interface and output interface , and when the operational amplifier corresponds to one transistor , an external circuit of the transistor further comprises:a first port, connected with a base of the transistor through a first resistor;a second port, connected with an emitter of the transistor;a third port, connected with a collector of the transistor; anda fourth port, connected with the emitter of the transistor through a second resistor and used as a public port for signal input and signal output.2. The operational amplifier as claimed in claim 1 , wherein further comprising:a first diode, connected in series with the first resistor,wherein an anode of the first diode is connected with the first resistor and a cathode of the first diode is connected with the base of the transistor, oran anode of the first diode is connected with the first port and the cathode of the first diode is connected with the first resistor.3. The operational amplifier as claimed in claim 1 , wherein further comprising:a second diode, of which an anode is connected with the emitter of the transistor and a cathode is ...

Level conversion circuit

내용 없음. No content.

インタ−フエイス回路

(57)【要約】本公報は電子出願前の出願データであるた め要約のデータは記録されません。

Capacitively cross-coupled DCS emitter-follower output stage

An output stage device for an enhanced differential current switch. The output stage receives a differential signal pair (COC,COT) from a prior logic stage and must shift the output signals (OUTC,OUTT) to the levels necessary for the next stage. The output stage has a differential pair of emitter followers that are capacitively cross coupled. Capacitors (Cc,Ct) couple the collector of a first transistor (T1 or T2) to the emitter of the second (T2 or T1). The capacitors (Cc,Ct) can be formed from forward biased diodes or transistors. The result is a more rapid falling output transition while reducing power requirements.

Logic signal discrimination circuit

Logic level conversion circuit

Potential level converter

How to use semiconductor integrated circuits

Translators and methods for converting differential signals to single-ended signals

High-speed signal translators are provided to convert differential input signals (e.g., ECL signals) to single-ended output signals (e.g., CMOS signals). An exemplary translator is formed with first and second current mirrors, first and second complimentary differential pairs of transistors, a complimentary transistor output stage and first and second current-diverting transistors. The complimentary output stage initially generates the single-ended output signal in response to currents received from the complimentary differential pairs. When the output signal has been established, the current-diverting transistors respond by carrying at least portions of the currents supplied by the complimentary differential pairs. The current-diverting transistors also drive the current mirrors to divert other portions of these currents away from the complimentary output stage. Stored charges in the output stage are accordingly reduced and its response time enhanced. Translator speed is further enhanced with elements associated with the current-diverting transistors that prevent saturation in the current mirrors and the complimentary output stage.

Low power output circuit

PURPOSE: A low power output circuit is provided to reduce current consumption and to optimize output characteristics by replacing a resistor in an emitter follower with a transistor. CONSTITUTION: A low power output circuit includes a differential amplifier(11) and an emitter follower(12). The differential amplifier(11) includes bias resistors and transistors having a bias current varied according to an input voltage. The emitter follower(12) is connected to an output terminal of the differential amplifier and includes a transistor for output bias. The differential amplifier(11) includes a first resistor(Q1) receiving the input voltage, a second transistor(Q2) receiving a reference voltage, first through third emitter resistors(Re1,Re2,Re3) connected between emitters of the transistors(Q1,Q2) and a ground potential, third transistor(Q3), a first collector resistor(Rc1) between the first transistor(Q1) and a source voltage, and a second collector resistor(Rc2) between the second transistor(Q2) and the source voltage. The emitter follow includes fourth and fifth transistors(Q4,Q5). The fourth transistor(Q4) includes a base connected to a collector of the first transistor(Q1) and a collector connected to the source voltage. The fifth transistor(Q5) includes a base connected between the first and second emitter resistors(Re1,Re2), a collector connected to an emitter of the fourth transistor(Q4), and an emitter connected to the ground potential.

CONVERTER CIRCUIT FROM BIPOLAR LOGIC TO HIGH SPEED CMOS LOGIC

Load current compensation for analog input buffers

In described examples of systems and methods for load current compensation for analog input buffers, an input buffer (300) may include: a first transistor (Q 1 ) having a collector terminal coupled to a power supply node and a base terminal coupled to a first input node (vinp); a second transistor (Q 2 ) having a collector terminal coupled to an emitter terminal of the first transistor (Q 1 ); a third transistor (Q 3 ) having an emitter terminal coupled to an emitter terminal of the second transistor (Q 2 ) and to a ground node, a collector terminal coupled to a current source (I bias ), and a base terminal coupled to the collector terminal and to a base terminal of the second transistor (Q 2 ); and a capacitor (C 1 ) coupled to the base terminals of the second and third transistors (Q 2 and Q 3 ) and to a second input node (v inn ), wherein the first and second input nodes (v inp and V inn ) are differential inputs.

Matching of TTL to MOS circuits - allows integration of both, adjusting current levels using current reflecting transistors

The matching or interfacing arrangement links TTL and MOS circuits the design allows the two types of circuit to be integrated and provides the required input and output level adjustment allowing the MOS circuit to be interfaced with further TTL. The interface is governed by an input differential amplifier having a constant current power source. This controls the logic state of a following switching circuit feeding the MOS section. The current levels in the two circuits are governed by current reflecting transistors the final one of which provides a reference current governed by a resistor in its collector to supply circuit.

Differential circuit

Dual supply ECL to TTL translator

An ECL to TTL translator (10) converts a signal from ECL logic levels to TTL compatible logic levels without introducing current spikes in the output signal during logic transitions. The ECL input signal (12, 14) is transformed into first and second differentially related currents which develop first and second voltages at two nodes (28, 36) for biasing first (30, 44, 46) and second (34, 48, 50) switching circuits which in turn generate first and second complementary control signals. The sum total of the differentially related currents are limited to a predetermined magnitude blocking simultaneously assertion of the control signals. An output stage (56, 58, 60, 62, 64, 66) includes upper (56, 58) and lower (60) transistors each responsive to the first and second control signal respectively for developing a TTL high and TTL low output signal. The first and second switching circuits inhibit simultaneous conduction of the upper and lower transistors of the output stage preventing undesirable current spikes in the output signal thereof.

Semiconductor integrated circuit having a C-MOS internal logic block and an output buffer for providing ECL level signals

A semiconductor integrated circuit is provided which combines an MOS internal logic circuit (C-MOS in the preferred embodiment) with input and output buffers which have pin-compatibility with ECL circuitry. An ECL-CMOS level-conversion input buffer circuit arranged for a C-MOS internal logic circuit has a pair of emitter-coupled transistors which are responsive to an input signal at an ECL level. Thus, the input buffer circuit operates at a high speed. A CMOS-ECL level-conversion output buffer circuit arranged for the C-MOS internal logic circuit has an amplifying transistor, which has its base responsive to the output signal of the C-MOS internal logic circuit, and an emitter-follower transistor which has its base responsive to the collector signal of said amplifying transistor for generating an output signal at an ECL level at its emitter. Thus, the output buffer circuit operates at a high speed. Utilizing such an arrangement, the circuit can obtain the benefits of lower power consumption for the C-MOS internal logic circuit together with high speed in the buffer stages and ECL compatibility.

Interface circuit

An interface circuit (100) includes a first (INN) and a second (INP) input terminal, a first output transistor (Q121), a second output transistor (Q122), a first output controller (107) for implementing control according to a voltage supplied to the first and the second input terminal so that a predetermined current appears at a control terminal of the first output transistor if the first output transistor is in saturated state and supplies a predetermined current to the control terminal of the first output transistor if the first output transistor is in shutoff state, and a second output controller (108) for implementing control according to a voltage supplied to the first and the second input terminal so that a predetermined current appears at a control terminal of the second output transistor if the second output transistor is in saturated state and supplies a predetermined current to the control terminal of the second output transistor if the second output transistor is in shutoff state.

Level shift circuit

Electronic structure for passing signals across voltage differences

An electronic structure for passing signals across voltage differences includes a signal bus segment that includes at least one circuit element. Circuitry connected to the signal bus segment is operatively connected to a voltage source. Signal bus segments and the associated circuitry can be stacked and connected to corresponding stacked voltage sources. This allows a signal to be passed to a particular circuit, regardless of the voltage difference between the source circuit and the desired circuit.

Level converting circuit

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Inverter circuit arrangement

An inverter circuit arrangement that connects an IO-link master with a slave comprises an AB class transistor circuit (Q nc2 , Q pc2 ) of which the currents are replicated by a current mirror (Q po1 , Q no1 , Q po2 , Q no2 ) to a terminal of the slave (OUT1). A bias circuit (R b1 , Q b1 , ..., Q nc1 , Q pc1 ) provides bias voltages to the AB class transistors (Q nc2 , Q pc2 ). A comparator (C) forms a feedback between the master and slave terminals (C/Q, OUT1). The circuit provides for a bidirectional inversion to make a slave device IO-link compatible.

Circuit system

一种电路系统，包括利用差分控制信号控制第一和第二存储单元的装置(102)。差分控制信号包括第一控制信号和与第一控制信号反向的第二控制信号。电路系统还包括一条差分控制信号线(120)，它包括提供第一控制信号的第一信号线(122)和提供第二控制信号的第二信号线(124)。第一电路单元(104)通过第一信号线(122)而第二电路单元(106)通过第二信号线(124)连接到控制装置(102)。

Logic signal discrimination circuitry

내용 없음. No content.

High-speed output buffer

A robust output buffer component capable of providing high quality output signals comprising a cascode module for receiving a differential signal from a differential pair module and transmitting that differential signal as two output waveforms. Using a bipolar implementation example, the emitter end of a common base cascode pair is coupled to the collector end of a common emitter differential pair with an optional resistive module inserted between the cascode pair and the differential pair. Engineering the cascode bias, the resistance at the collector nodes of the differential pair and/or the resistance at the base nodes of the differential pair effects: the degree of non-linearity of the base-collector capacitance as a function of the base-collector voltage, the voltage swing of the collector nodes, and the degree of symmetry of the input voltages. These three parameters may be used to optimize the symmetry of the output waveforms.

Ttl-ecl input translation with and/nand function

A new and improved translation circuit (10) that accepts TTL signals and converts them to ECL levels while performing an AND/NAND function is provided, comprising at least two emitter-coupled transistor pairs (Q1-Q2 and Q3-Q4), each coupled to an input terminal (12 and 14) for receiving corresponding TTL signals and coupled to one another for performing the AND operation. Each emitter-coupled pair (Q1-Q2 and Q3-Q4) is also coupled to a bias drive (30) for providing reference voltages that designate which one of each of the transistor pairs (Q1-Q2 and Q3-Q4) conducts, depending upon the state of the TTL signal received.

ECL to TTL translator circuit with improved slew rate

An ECL to TTL translator circuit incorporates an ECL input gate, a TTL output gate, and a voltage amplifier transistor element circuit coupled between the ECL input gate and TTL output gate for effecting the translation. The ECL gate has differential ECL inputs for receiving ECL input signals at least at one of the ECL inputs (V IN ) and differential first and second ECL output nodes (A, B). First and second emitter follower output circuits (Q7, Q3) are coupled to the respective first and second ECL output nodes (A, B). The TTL gate (12) has a TTL output (V OUT ) for delivering TTL output signals corresponding to ECL input signals. The TTL gate phase splitter transistor element (Q9) controls the TTL output (V OUT ). The collector node of a voltage amplifier transistor element (Q6) is coupled to a base node of the phase splitter transistor element (Q9) for controlling the conducting state of the phase splitter transistor element out of phase with the voltage amplifier transistor element. The first emitter follower output circuit (Q7, Q8, R4) is coupled to the base node (C) of voltage amplifier transistor element (Q6) and the second emitter follower output circuit (Q3, Q4, R3) is coupled to the collector node (D) of the voltage amplifier transistor element (Q6) for controlling the conducting state of (Q6) in accordance with ECL input signals and for effecting translation with improved output switching speed.

Input buffer of prescaler

본 발명에 따른 프리스케일러의 입력 버퍼는 로드 회로, 제 1 및 제 2 앰프들 및 출력 구동 회로를 포함한다. 상기 입력 버퍼는 로우 임피던스를 가지는 제 1 앰프와 하이 임피던스를 가지는 제 2 앰프 및 출력 구동 회로를 가짐으로써, 넓은 대역폭을 가지며, 상기 제 1 앰프에 구비되는 저항들의 저항값들을 이용하여 대역폭 내의 평탄도를 조절할 수 있다. 그리고, 주목할만한 것은 상기 로드 회로가 상기 제 1 앰프의 전류를 재사용함으로써, 종래의 기술에 따른 입력 버퍼보다 2 배의 전류 소모를 줄일 수 있다. The input scale of the prescaler according to the invention comprises a load circuit, first and second amplifiers and an output drive circuit. The input buffer has a wide bandwidth by having a first amplifier having a low impedance, a second amplifier having a high impedance, and an output driving circuit, and having a wide bandwidth, and flatness within the bandwidth by using resistance values of resistors included in the first amplifier. Can be adjusted. And notably, the load circuit reuses the current of the first amplifier, thereby reducing the current consumption of twice as much as the input buffer according to the prior art.

Level converting circuit

(57)【要約】本公報は電子出願前の出願データであるた め要約のデータは記録されません。

TTL-to-ECL input translator/driver circuit

The present invention provides a high speed low power electrical circuit for converting true TTL level signals to true ECL level signals. The circuit only has a single buffer delay with some small additional delay due to an input emitter follower stage. The circuit includes a clamped, switched emitter follower which acts as a level shifting comparator; a self-centering reference threshold translator; a clamped level shifted input translator; and, an ECL Buffer Driver. The circuit also includes a TTL reference and an ECL reference which are tied together. If the TTL reference level shifts slightly due to temperature changes, supply voltage shifts or other factors, the ECL voltage reference will automatically shift by an appropriate percentage to compensate for the original shift in the TTL reference.

Voltage level converter

The TTL to ECL level converter whose input comprises emitter coupled pair to improve the level converting speed receives the TTL level input data whose level is medium state at base of a transistor (Q1). When the input TTL level is high, the current flows from an active pull-up transistor of the TTL circuit through a resistor (R3), but flows to an active pull-down transistor of the TTL circuit through a transistor (Q3) and resistor (R4) when the level is low. The TTL level received to the transistor (Q1) is compared with a reference level applied to base of a transistor (Q2) and converted to inner voltage level to provide the ECL level signal through a level shifting circuit,

Interface circuit

Logic level converting circuit

(57)【要約】本公報は電子出願前の出願データであるた め要約のデータは記録されません。

Circuit arrangement for converting ECL-logic signals to TTL-logic signals

A circuit arrangement for level conversion of ECL-logic levels to TTL-logic levels, having an emitter-coupled current switch with an input addressable by ECL-logic levels, and a TTL-logic output stage, includes a voltage-controlled current source having an input addressable by an output of the current switch, and having an output connected to the TTL-logic output stage.

Low power output driver

An output driver. The novel output driver includes a first circuit for receiving an input signal and in accordance therewith generating an output signal at an output node, a second circuit for applying a variable current to the output node, and a third circuit for controlling the magnitude of the variable current in accordance with the input signal. In an illustrative embodiment, the third circuit is adapted to generate a controlling current in accordance with the input signal, and the second circuit includes a current mirror adapted to receive the controlling current and output a scaled version of the controlling current to the output node.

Level shift circuit

There is disclosed a level shift circuit which has a differential input, for receiving input signals, and a differential output, for supplying output signals derived from the input signals. The level shift circuit further includes a control level setting input, and a feedback circuit for setting a common mode level of the output signals to a level set on the control level setting input. This allows the output common mode to be set accurately, independently of the input common mode.

Apparatus and method for shifting a signal from a first reference level to a second reference level

A level-shifting apparatus 80 includes an input section 82, level shift sections 84 and output sections 86. Differential signaling input signals received from an upstream data source at input terminals 100, 102 of input section 82 are coupled with respective bases of common emitter NPN bipolar transistors Q1, Q2 and respectively presented at collector outputs 124, 126 to level shift sections 84. Each level shift section 84 includes a low speed network 130 and a high speed network 140 coupled substantially in parallel between a respective output 124, 126 and an output locus 88. Low speed network 130 operates as a level setting signal path to set the DC (direct current) level at output locus 88 to a desired level. Low speed network 130 employs an active amplifier component to set output DC resistance. In one embodiment, the active component is an NPN bipolar transistor Q4 configured as an emitter-follower, with its base connected to an output 124, 126 via a resistor RLS. High speed network 140 operates as a signal transition path to speed up provision of signal transitions (for example, information bearing signal transitions) to output locus 88. In one embodiment, a base 142 of an NPN bipolar transistor Q5 is driven without added series resistance to avoid delay and unwanted filtering. Output section 86 connects signals appearing at output locus 88 with downstream portions of a communication system.

Fan out buffer and method therefor

Line driver-switching stage

Operational amplifier, driving interface, measuring and controlling equipment, drive circuit and driver

本发明公开了一种运算放大器、驱动接口、测控设备、驱动电路和驱动器。其中，该运算放大器作为输入和/或输出接口，其中，运算放大器对应一个晶体管时，晶体管的外部电路还包括：晶体管；第一端口，通过第一电阻与晶体管的基极相连接；第二端口，与晶体管的发射极相连接；第三端口，与晶体管的集电极相连接；以及第四端口，通过第二电阻与晶体管的发射极相连接，作为信号输入与信号输出的公共端口。本发明提供的大电流驱动输出高电压恒流输入斩波器解决了相关技术中的接口电路或电平转换电路由于无法支持既可以作为高电压输入接口又可以作为大电流输出接口的转换导致降低应用电路性能的技术问题。

Output circuit

High-speed bipolar-to-CMOS logic converter circuit

A high-speed bipolar-to-CMOS logic converter circuit, including an input stage, including a differential amplifier meant to be connected to a bipolar-logic circuit portion and to be supplied by the supply voltage of the bipolar-logic portion, and an output stage, which is supplied by the voltage of a CMOS-logic circuit portion, a dynamic level shifting circuit interposed between the input stage and the output stage, the output stage being connected to the CMOS-logic circuit portion.

ECL to TTL voltage level translator

A voltage level translator circuit is provided that translates an input voltage referenced to an ECL supply voltage V CC to a voltage referenced to a TTL supply voltage V EE independent of power supply voltage variations. A first and a second embodiment have reference circuits coupled to receive a data input signal for providing a single signal referenced to a first supply voltage terminal to a current mirror. An output circuit is coupled to the current mirror for providing an output signal referenced to the second supply voltage terminal. A third embodiment has a reference circuit coupled to receive a data input signal for referencing a voltage on a first supply voltage terminal to a voltage on a second supply voltage terminal. A voltage setting circuit is coupled to the reference circuit for setting a voltage within the reference circuit. An output circuit is coupled to the voltage setting circuit for providing an output voltage referenced to a voltage on the second voltage terminal and independent of variations in supply voltages.

Ttl-ecl input translation with and/nand function.

Emitter-coupled logic (ECL) output buffer circuit

본 발명의 ECL 출력 버퍼 회로는 출력부가 와이어드·오어 접속할 수 있는 ECL 출력 버퍼의 수를 증가할수 있도록 한다. ECL 출력 버퍼 회로 본체 및 이 회로 본체의 출력단 이미터·폴로워와 이 이미터·폴로워의 바이폴라 트랜지스터의 베이스에 채널 도전로의 일단이 접속되고, 정전류원을 통하여 제 2 의 전원에 접속된 제 1 의 MOS 트랜지스터와, 상기 ECL 출력 버퍼 회로 본체의 출력단 이미터·폴로워의 출력을 컷오프 상태로 하고자할 경우에 상기 제 1 의 출력은 상기 제 1 의 MOS트랜지스터가 도통 상태그 되도록 변화하고, 상기 제 2의 출력으로 상기 이미터·폴로워의 출력이 저레벨이 되는 것보다도 더욱 저레벨의 출력이 상기 이미터·폴로워의 출력으로서 얻어지도록 하는 제어 회로를 구비하는 것을 특징으로 한다.

CIRCUIT ARRANGEMENT FOR LEVEL CONVERSION

Circuit arrangement for push-pull transmission of binary signals

Integrated circuit device accepting inputs and providing outputs at the levels of different logic families

An integrated circuit device containing internal logic and/or memory circuitry is provided with means to receive multiple inputs at the voltage levels of different logic families and with means to provide multiple outputs at the voltage levels of different logic families. On-chip input translators receive the inputs at the level of a given logic family and translate to the level required by the internal logic and/or memory circuitry. After performance of logic and/or memory functions, on-chip output translators translate the output of the internal logic and/or memory circuitry and provide external outputs at the voltage levels of different logic families. The internal logic and/or memory circuitry may be of a single logic family or may be composed of several logic families. On-chip translators may also be added between internal logic and/or memory circuitry of different families.

Buffer circuit, amplifier circuit, and test apparatus

There is provided a buffer circuit that outputs a signal according to an input signal. The buffer circuit includes a first receiving transistor that receives the input signal through its base terminal, a first clamp transistor having polarity same as that of the first receiving transistor, of which an emitter terminal and a collector terminal are connected to corresponding terminals of the first receiving transistor and which receives a first clamp voltage restricting a signal level output from the buffer circuit through its base terminal, and a first current defining section that is commonly provided for the first receiving transistor and the first clamp transistor and defines a total amount of emitter currents flowing into the first receiving transistor and the first clamp transistor. The buffer circuit outputs an output signal according to an emitter voltage of the first receiving transistor.

ECL/TTL level converter with TTL tristate output and ECL control input

Level converter for converting ecl-level signal voltage to ttl-level signal voltage

According to this invention, a level converter has a pair of differential transistors operated at a negative voltage in accordance with an ECL-level input signal, and first and second output nodes are arranged between a collector of one transistor of the pair of differential transistors and a positive power source voltage. A level-converting resistor for converting an ECL-level signal to a positive level signal is inserted between the first output node and the second output node so as to output the positive level signal in accordance with an ECL-level input signal to the first output node. The emitter-collector path of a bipolar transistor is inserted between the second output node and the positive power source voltage. A clamp potential for controlling saturation of transistors constituting a TTL circuit connected to an output of the transistor is generated by a constant potential applied to the base of the transistor.

Level conversion circuit

Converting circuit of signal level

(57)【要約】本公報は電子出願前の出願データであるた め要約のデータは記録されません。

Logic-level converted circuit

내용 없음. No content.

Level converter circuit

Herein disclosed is a circuit for converting the logic amplitude of an ECL by logically amplifying a TTL or CMOS so that no substantial dc current flows in the steady state. The level converting circuit comprises: a level-shift circuit for generating a first output with a small level-shift and a second output with a larger level-shift than said first output; a CMOS circuit including a PMOS transistor having its gate fed with said first output, and an nMOS transistor having its gate fed with said second output; and a current switch for giving output levels to turn on said PMOS transistor and off said nMOS transistor at its high level and to turn on said PMOS transistor and off said nMOS transistor at its low level.

Supply voltage compensation circuit for high speed LVDS predrive

A circuit that provides a stable predrive to a BiCMOS LVDS output which compensates for supply voltage variations while maintaining a suitably fast signal path. The supply voltage compensation circuit provides an offset to the predrive level shift such that when the supply voltage V cc rises, the predrive output voltage is lowered in response.

LEVEL SHIFT CIRCUIT FOR A SERIES-PARALLEL CONVERTER

ECL-TTL conversion output circuit

Transistor-transistor logic to emitter coupled logic translator

A transistor-transistor logic (TTL) to emitter coupled logic (ECL) translator includes a TTL input gate for receiving TTL voltage level logic input signals in the positive voltage range compatible with TTL circuits and an ECL output gate for delivering corresponding ECL voltage level logic output signals in the negative voltage range compatible with ECL circuits. A translating current source operatively coupled between the TTL input gate and ECL output gate translates signals down to the negative ECL voltage range for application to the input transistor of the ECL output gate. A bidirectional bridge clamp also operatively coupled between the TTL input gate and ECL output gate limits the swing of the translated signals in the negative voltage range applied at the input of the ECL output gate thereby reducing propagation delay across the translator and reducing power dissipation.

Semiconductor integrated circuit provided with emitter coupled logic input/output buffers

A semiconductor integrated circuit comprises an Emitter Coupled Logic (ECL) input buffer and an ECL output buffer which are driven by m (m is equal to 2 or more) power supplies, a test ECL input buffers and a test ECL output buffers which are driven by m power supplies, and four first to fourth drive voltage supply lines for delivering drive voltages to the four input and output buffers. This semiconductor integrated circuit is characterized in that one of the m number of third drive voltage supply lines and a corresponding one of the m number of first drive voltage supply lines are commonly connected, or the third drive voltage supply lines are provided independently of the first drive voltage supply lines, and that one of m number of fourth drive voltage supply lines and a corresponding one of the m number of second drive voltage supply lines are commonly connected, or the fourth drive voltage supply lines are provided independently of the second drive voltage supply lines, whereby when the semiconductor integrated circuit is in an ordinary use state after being assembled into the system, the same voltages are delivered to the m number of third drive voltage supply lines and the m number of fourth drive voltage voltages supply lines, respectively.

Level converting circuit

(57)【要約】本公報は電子出願前の出願データであるた め要約のデータは記録されません。

Level converting circuit

Method and apparatus for signal level conversion with clamped capacitive bootstrap

A method and apparatus for converting input signals at one predetermined logic level to output signals at corresponding different logic levels includes differential amplification of input signals with a first output of a differential amplifier connected for establishing a voltage level between voltage limits V cc and V ee at the output of an output driver in response to variations in amplifier output. A pull-down transistor has a collector connected to the output driver output, an emitter connected to the V ee voltage source, and a base capacitively coupled to the second amplifier output. In further aspects of the invention, a voltage clamp embracing a transistor with a base connected to receive a predetermined control voltage has an emitter connected to the pull-down transistor base and a collector connected to the V cc voltage source.

Systems and methods for level shifting using AC coupling

Systems and methods for conveying signals between integrated circuit (IC) components in domains having different supply voltages. AC coupling is used to increase the speed at which the common mode voltage of a signal is shifted from one level to another. One embodiment comprises a method for level shifting a binary signal in an IC. This method includes receiving an input binary signal and decoupling its AC component from its common mode component. A second common mode component is added to the AC component, providing a binary output signal. The common mode voltage of the input signal may be greater (or smaller) than that of the output signal. In one embodiment of the method, duty cycle compensation (DCC) is performed. The DCC drives the duty cycle toward a desired value.

Low voltage differential signaling (LVDS) driving circuit

An LVDS (Low Voltage Differential Signaling) driving circuit includes a first transistor, a second transistor, a third transistor, a fourth transistor, a first resistor, a second resistor, and a bias driver. The first transistor is coupled between a supply voltage and a first node. The second transistor is coupled between the supply voltage and a second node. The third transistor is coupled between the first node and a ground voltage. The fourth transistor is coupled between the second node and the ground voltage. The first resistor is coupled between the first node and a third node. The second resistor is coupled between the second node and the third node. The bias driver generates bias signals for controlling the first, second, third, and fourth transistors according to a data signal.

Bidirectional transmission circuit from true TTL to true ECL

Systems and Methods for Level Shifting using AC Coupling

Systems and methods for conveying signals between integrated circuit (IC) components in domains having different supply voltages. AC coupling is used to increase the speed at which the common mode voltage of a signal is shifted from one level to another. One embodiment comprises a method for level shifting a binary signal in an IC. This method includes receiving an input binary signal and decoupling its AC component from its common mode component. A second common mode component is added to the AC component, providing a binary output signal. The common mode voltage of the input signal may be greater (or smaller) than that of the output signal. In one embodiment of the method, duty cycle compensation (DCC) is performed. The DCC drives the duty cycle toward a desired value.

Inverter circuit

An inverter circuit operating at a high speed and with low power consumption is disclosed, which comprises a first bipolar transistor having a collector coupled to the output of the circuit, a second bipolar transistor having a collector coupled to the base of the first transistor and means responsive to at least one input signal to produce a first signal for driving the first transistor and a second signal complementary to the first signal for driving the second transistor substantially at the same time.

Inverter circuit arrangement

Current mode phase detection

The invention relates to phase detectors that integrate a portion of a transition between adjacent or consecutive bits of a serial bitstream in a relatively fixed window by switching currents as opposed to voltages. The phase detector can be used to synchronize a VCO clock in a PLL to a fast data bitstream used in an optical network, such as SONET. Advantageously, embodiments of a current mode phase detector switch currents, rather than voltages, to integrate the window of the serial bitstream. The current switching allows devices to operate at frequencies approaching the device's f T and can advantageously extend the phase detector's bandwidth and allow an associated transceiver to operate at higher data rates. By contrast, the conventional switching of voltage results in a delay induced by the charging of related capacitances, such as parasitic substrate capacitances, which in turn results in actual performance far below the f T of the devices.

High speed ecl/cml to ttl translator circuit

An ECL/CML to TTL translator circuit couples the output of an ECL/CML gate to the input of a TTL gate. The ECL/CML gate operates with reference to a first power rail higher reference voltage level with transistor elements operating in the non-saturation operating region. The TTL gate operates with reference to a second power rail lower reference voltage level with transistor elements operating in the saturation operating region. The translator circuit includes a reference voltage level shifting constant current non-­ switching current mirror circuit coupled to the output of the ECL/CML gate. The current mirror circuit shifts the reference voltage level of the ECL/CML gate output from the higher reference voltage level to the lower reference voltage level and delivers a reference voltage level shifted output signal. An operating region translating emitter follower output buffer circuit is coupled to receive the voltage level shifted output signal and drive the input of the TTL gate in the saturation region. The circuit functions of reference voltage level. shifting and of operating region translating are thereby separately performed by separate components. The TTL gate input is a phase splitter transistor element. A resistor pulldown discharges the phase splitter transistor element. Base drive to the phase splitter transistor element is limited by a base drive limiting anti-saturation clamp. More generally, an overdrive and anti-saturation clamp circuit provides high speed switching of the phase splitter or other TTL switching transistor element.

Differential linear to digital translator

An improved linear to digital translator having parallel current paths with unequal resistances. The resistances are sized according to a determined relationship between circuit parameters to improve crossover performance. In addition, non-saturating devices are used to reduce delay times.

TTL-to-CML translator circuit

A TTL-to-CML translator circuit includes a TTL input stage (20), a translation chain (22), a first CML differential pair (24), a level shifter (26), and a second CML differential pair (28). The first CML differential pair (24) is coupled between a TTL ground potential (GTTL) and a negative supply potential (VEE). The second CML differential pair (28) is connected between a CML ground potential (GCML) and the negative supply potential. The level shifter (26) serves to electrically isolate the TTL ground potential and the CML ground potential, thereby producing relatively noise free CML-compatible output signals.

High speed ECL/CML to TTL translator circuit

An ECL/CML to TTL translator circuit couples the output of an ECL/CML gate to the input of a TTL gate. The ECL/CML gate operates with reference to a first power rail higher reference voltage level with transistor elements operating in the non-saturation operating region. The TTL gate operates with reference to a second power rail lower reference voltage level with transistor elements operating in the saturation operating region. The translator circuit includes a reference voltage level shifting constant current non-­switching current mirror circuit coupled to the output of the ECL/CML gate. The current mirror circuit shifts the reference voltage level of the ECL/CML gate output from the higher reference voltage level to the lower reference voltage level and delivers a reference voltage level shifted output signal. An operating region translating emitter follower output buffer circuit is coupled to receive the voltage level shifted output signal and drive the input of the TTL gate in the saturation region. The circuit functions of reference voltage level. shifting and of operating region translating are thereby separately performed by separate components. The TTL gate input is a phase splitter transistor element. A resistor pulldown discharges the phase splitter transistor element. Base drive to the phase splitter transistor element is limited by a base drive limiting anti-saturation clamp. More generally, an overdrive and anti-saturation clamp circuit provides high speed switching of the phase splitter or other TTL switching transistor element.

Level shift circuit

There is disclosed a level shift circuit which has a differential input, for receiving input signals, and a differential output, for supplying output signals derived from the input signals. The level shift circuit further includes a control level setting input, and a feedback circuit for setting a common mode level of the output signals to a level set on the control level setting input. This allows the output common mode to be set accurately, independently of the input common mode.

LOGIC LEVEL CONVERTER CIRCUIT WITH THREE STATES

LE CIRCUIT CONVERTISSEUR DE NIVEAUX LOGIQUES SELON L'INVENTION COMPORTE UN PREMIER ETAT E BAS, E BAS PRODUISANT UN NIVEAU HAUT EN SORTIE TTL S, UN DEUXIEME ETAT E HAUT, E BAS PRODUISANT UN NIVEAU BAS EN SORTIE S ET UN TROISIEME ETAT E HAUT D'IMPEDANCE TRES ELEVEE, DANS LEQUEL LES DEUX TRANSISTORS DE SORTIE T ET T SONT BLOQUES. LE COURANT D'UNE SOURCE DE COURANT I EST AIGUILLE PAR DES TRANSISTORS T, T, T, T ET T. DANS LE DEUXIEME ET LE TROISIEME ETAT, UNE DIODE D PONTANT LES BASES DES TRANSISTORS T ET T - POINTS A ET B - EST CONDUCTRICE, ALORS QU'UNE DIODE D CONNECTEE ENTRE LA MASSE ET LE POINT A EST CONDUCTRICE DANS LE TROISIEME ETAT. THE LOGIC LEVEL CONVERTER CIRCUIT ACCORDING TO THE INVENTION INCLUDES A FIRST STATE E LOW, E LOW PRODUCING A HIGH LEVEL AT TTL S OUTPUT, A SECOND STATE E HIGH, E LOW PRODUCING A LOW LEVEL AT OUTPUT S AND A THIRD STATE HIGH D 'VERY HIGH IMPEDANCE, IN WHICH THE TWO T AND T OUTPUT TRANSISTORS ARE BLOCKED. THE CURRENT OF A CURRENT SOURCE I IS NEEDED BY TRANSISTORS T, T, T, T AND T. IN THE SECOND AND THIRD STATE, A DIODE D BRIDGING THE BASES OF THE T AND T TRANSISTORS - POINTS A AND B - IS CONDUCTIVE, WHILE A DIODE D CONNECTED BETWEEN EARTH AND POINT A IS CONDUCTIVE IN THE THIRD STATE.

Input circuit

본 발명은 입력 버퍼에 관한 것으로, 차동증폭부와 출력부, 지연부를 포함하여 이루어진다. 차동증폭부는 외부에서 입력되는 입력신호와 소자의 내부에서 발생되는 기준신호를 입력받아 입력신호와 기준신호의 전압차에 비례하는 출력신호 발생시킨다. 출력부는 차동증폭부의 출력신호의 레벨을 반전시켜 출력한다. 지연부는 출력부의 출력신호에 의해 턴 온되는 풀 업 수단과 풀 다운 수단을 갖고, 출력부의 출력신호의 레벨이 천이하면 이로부터 소정 시간이 경과한 뒤에 차동증폭부의 출력단을 풀 업 또는 풀 다운 시켜서 차동증폭부의 출력신호가 히스테리시스 특성을 갖도록 한다. The present invention relates to an input buffer, comprising a differential amplifier, an output, and a delay. The differential amplifier receives an input signal input from the outside and a reference signal generated inside the device to generate an output signal proportional to the voltage difference between the input signal and the reference signal. The output section inverts and outputs the level of the output signal of the differential amplifier section. The delay unit has a pull-up means and a pull-down means turned on by the output signal of the output part, and when the level of the output signal of the output part transitions, after a predetermined time has elapsed from this, the output stage of the differential amplifier part is pulled up or pulled down to differential The output signal of the amplifier section has hysteresis characteristics.

Level converter for converting ECL-level signal voltage to TTL-level signal voltage

Logic level translator

A logic level translator utilizes a TTL logic gate, a current switch, and a clamp circuit to convert CML level binary signals into TTL level binary signals. The translator provides isolation between the TTL ground and the CML ground in order to reduce noise in the CML portion of the circuit. The clamp circuit prevents a switching transistor in the current switch from reaching saturation, thereby increasing the speed of operation of the translator. A portion of the current switch provides a quick pulldown of a switching transistor in the TTL circuit to reduce noise in the TTL circuit.

[UNK]

Dispositivo a circuito integrato a semiconduttori.

Schnittstellenschaltung.

Schaltungsanordnung zur verstaerkung von elektrischen signalen.

Schaltungsanordnung zur pegelumsetzung.

Masken-programmierbares bussteuerungsgattenfeld

[UNK]

Traducteur de niveau logique