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Небесная энциклопедия

Космические корабли и станции, автоматические КА и методы их проектирования, бортовые комплексы управления, системы и средства жизнеобеспечения, особенности технологии производства ракетно-космических систем

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Мониторинг СМИ

Мониторинг СМИ и социальных сетей. Сканирование интернета, новостных сайтов, специализированных контентных площадок на базе мессенджеров. Гибкие настройки фильтров и первоначальных источников.

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Поддерживает ввод нескольких поисковых фраз (по одной на строку). При поиске обеспечивает поддержку морфологии русского и английского языка
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Применить Всего найдено 50. Отображено 50.
10-04-2003 дата публикации

COLUMN REDUNDANCY SYSTEM AND METHOD FOR EMBEDDED DRAM DEVICES WITH MULTIBANKING CAPABILITY

Номер: US20030067816A1
Автор: Darren Anand, John Barth

A column redundancy system is disclosed for a memory array having a page structure organized into columns and data lines. In an exemplary embodiment of the invention, the system includes a steering logic network for coupling a memory input/output (I/O) device to the memory array. A storage register is in communication with the steering logic network, the storage register for storing location information for defective data lines in the memory array. During a memory operation, the location information stored in the storage register is transmitted to the steering logic network, the storage register further having the location information loaded therein prior to the memory operation. Thereby, the steering logic network prevents any of the defective data lines from being coupled to the I/O device.

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01-03-2007 дата публикации

CIRCUITRY AND METHOD FOR PROGRAMMING AN ELECTRICALLY PROGRAMMABLE FUSE

Номер: US20070046361A1
Автор: Darren Anand, Larry Wissel

Circuitry that includes a voltage controller (224) for providing a variable gate signal (220) for controlling the gate of a programming transistor (212) used in conjunction with programming an electrically programmable fuse (“eFuse”) (204) of an integrated circuit (200). The voltage controller adjusts the gate signal depending upon whether the circuitry is in an eFuse programming mode or an eFuse resistance measuring mode. The voltage controller may optionally include a voltage tuner (252) for tuning the gate signal to account for operating variations in the programming transistor caused by manufacturing variations.

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18-06-2009 дата публикации

STRUCTURE FOR INDICATING STATUS OF AN ON-CHIP POWER SUPPLY SYSTEM

Номер: US20090153172A1

A design structure embodied in a machine readable medium used in a design process includes a system for indicating status of an on-chip power supply system with multiple power supplies, having a power system status register for receiving digital compliance signals, each compliance signal associated with one of the multiple power supplies, and having an associated compliance level, wherein each digital compliance signal indicates whether its associated power supply is operating at the associated compliance level, and wherein the power system status register generates a power supply status signal based on the digital compliance signals indicating status of the digital compliance signals; and an output for outputting the power supply status signal, wherein if a power supply is operating at its associated compliance level, the power supply status signal indicates that the power supply is passing, otherwise the power supply status signal indicates that the power supply is failing.

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13-01-2005 дата публикации

METHOD AND CIRCUIT FOR PRECISE TIMING OF SIGNALS IN AN EMBEDDED DRAM ARRAY

Номер: US20050007866A1

A method and circuit for timing the start of a precharge period in an eDRAM. The circuit including: a delayed lock loop circuit for receiving a clock signal and generating a control signal for adjusting an internal delay of the clock signal; and means for generating a delayed clock signal in response to the control signal. The means for generating the delayed clock signal is a multiple stage delay circuit, each stage of the multiple delay stage circuit connected in series and each stage individually responsive to the control signal.

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03-07-2003 дата публикации

Flexible multibanking interface for embedded memory applications

Номер: US20030123278A1
Автор: Darren Anand, John Barth

A growable multibank DRAM macro is achieved with a flexible multibank interface which can be grown without redesign and without change of appearance/behavior to the customer. The interface is preferably characterized by the presence of bank select inputs (pins) which permit selection of one or more banks of the macro. The banks preferably each have respective row decode circuitry and respective limited repair redundancy.

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08-04-2004 дата публикации

METHOD OF ELECTRICALLY BLOWING FUSES UNDER CONTROL OF AN ON-CHIP TESTER INTERFACE APPARATUS

Номер: US20040066695A1

A chip repair system designed for automated test equipment independent application on many unique very dense ASIC devices in a high turnover environment is disclosed. During test, the system will control on chip built-in self-test (BIST) engines collect and compress repair data, program fuses and finally decompress and reload the repair data for post fuse testing. In end use application this system decompresses and loads the repair data at power-up or at the request of the system.

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15-01-2009 дата публикации

DESIGN STRUCTURE FOR INCREASING FUSE PROGRAMMING YIELD

Номер: US20090016129A1
Принадлежит:

A design structure which enables e-fuse memory repair. The design structure uses a compressed bit string to generate another bit string based on a select value. The select value provides instructions to an encoding logic element, which generates a second bit string. For example, the select value may instruct the encoding logic to create a duplicate copy of each bit in the compressed bit string to generate a 2n-bit string. Once the fuses are programmed using the second bit string, the fuse values are read out as a third string, which is decoded by a decoding logic element according to the select value, thereby improving memory repair.

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29-08-2023 дата публикации

Voltage power switch

Номер: US0011742858B1
Принадлежит: Marvell Asia Pte, Ltd.

A voltage power switch includes circuitry configured to output a known voltage. The voltage power switch includes a lock circuit configured to output a known state and a voltage level shifter configured to receive an input, the input being based on the known state output by the lock circuit. The voltage power switch, using an output circuit, is configured to output a known voltage level based on an output of the voltage level shifter, wherein the known voltage is one of a high voltage V HI for a fuse programing period or a first non-zero intermediate voltage V MID1 for a non-fuse programming period.

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10-02-2005 дата публикации

SYSTEM AND METHOD FOR IMPLEMENTING SELF-TIMED DECODED DATA PATHS IN INTEGRATED CIRCUITS

Номер: US20050030065A1
Автор: Darren Anand, John Barth

A self-timed data transmission system includes a data bit group defined by at least two data bits to be transmitted from a corresponding plurality of transmitting storage elements. A corresponding plurality of data receiving storage elements receives the data transmitted from said transmitting storage elements. Encoding logic is used for encoding the transmitted data from the transmitting storage elements, wherein the encoded transmitted data is coupled to a plurality of data lines. The encoding logic is further configured so as to result in only one of the plurality of data lines being activated during a given data transmission cycle.

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27-09-2011 дата публикации

Structure for indicating status of an on-chip power supply system

Номер: US0008028195B2

A design structure embodied in a machine readable medium used in a design process includes a system for indicating status of an on-chip power supply system with multiple power supplies, having a power system status register for receiving digital compliance signals, each compliance signal associated with one of the multiple power supplies, and having an associated compliance level, wherein each digital compliance signal indicates whether its associated power supply is operating at the associated compliance level, and wherein the power system status register generates a power supply status signal based on the digital compliance signals indicating status of the digital compliance signals; and an output for outputting the power supply status signal, wherein if a power supply is operating at its associated compliance level, the power supply status signal indicates that the power supply is passing, otherwise the power supply status signal indicates that the power supply is failing.

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07-02-2008 дата публикации

DESIGN STRUCTURE FOR IMPROVING SENSING MARGIN OF ELECTRICALLY PROGRAMMABLE FUSES

Номер: US20080030260A1

A design structure embodied in a machine readable medium used in a design process includes an apparatus for sensing the state of a programmable resistive memory element device, the apparatus further including a latch device coupled to a fuse node and a reference node, the fuse node included within a fuse leg and the reference node configured within a reference resistance leg, the latch device configured to detect a differential signal developed between the reference node and the fuse node as the result of sense current passed through the fuse leg and the reference resistance leg; and the fuse and reference resistance legs further configured for first and second sensing modes, wherein the second sensing mode utilizes a different level of current than the first sensing mode.

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03-02-2005 дата публикации

DIAGNOSTIC METHOD AND APPARATUS FOR NON-DESTRUCTIVELY OBSERVING LATCH DATA

Номер: US20050025277A1

The invention provides a circuit that can observe data within shift registers without altering the data. The circuit includes selectors connected to the inputs and outputs of the shift registers. The selectors selectively connect the input with the output of a selected shift register to form a wiring loop for the selected shift register. A control device connected to the wiring loop uses the wiring loop to cause the data to be continually transferred from the output of the selected shift register to the input of the selected shift register and back through the selected shift register in a circular manner. The control device includes a counter used for determining the length of a selected shift register and a set of registers to store, for future use when rotating data in the shift registers, the length of each shift register. The control device also includes a data output accessible from outside the circuit. An observation wire is connected to the wiring loop, and the data passes from the ...

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31-01-2008 дата публикации

METHOD FOR IMPROVING SENSING MARGIN OF ELECTRICALLY PROGRAMMABLE FUSES

Номер: US20080025071A1

A method for determining the state of a programmable resistive memory element includes passing a first level of current through a fuse leg and a reference resistance leg of a test circuit including the programmable resistive memory element; detecting a differential signal developed between a reference node and a fuse node of the test circuit as a result of the first level of current; passing a second level of current through the fuse leg and the reference leg of a test circuit, the second level of current being higher than the first level of current so as to enable detection of trip resistance of the test circuit at a lower value than with respect to the first level of current; and detecting a differential signal developed between the reference node and the fuse node of the test circuit as a result of the second level of current.

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02-06-2005 дата публикации

AUTOMATIC BIT FAIL MAPPING FOR EMBEDDED MEMORIES WITH CLOCK MULTIPLIERS

Номер: US20050120270A1

A bit fail map circuit accurately generates a bit fail map of an embedded memory such as a DRAM by utilizing a high speed multiplied clock generated from a low-speed Automated Test Equipment (ATE) tester. The circuit communicates between the ATE tester, the embedded memory under test, Built-In Self-Test (BIST) and Built-In Redundancy Analysis (BIRA). An accurate bit fail map of an embedded DRAM memory is provided by pausing the BIST test circuitry at a point when a fail is encountered, namely a mismatch between BIST expected data and the actual data read from the array, and then shifting the bit fail data off the chip using the low-speed ATE tester clock. Thereafter, the high-speed test is resumed from point of fail by again running the BIST using the high-speed internal clock, to provide at-speed bit Fail Maps.

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19-05-2005 дата публикации

MODULAR DLL ARCHITECTURE FOR GENERATING MULTIPLE TIMINGS

Номер: US20050104639A1
Автор: Darren Anand, Kevin Gorman

A modular Digital Locked Loop (DLL) architecture capable of generating a plurality of multiple phase clock signals, having particular applicability to synchronization of embedded DRAM systems with on chip timing. The architecture comprises a single core frequency locking circuit that includes a delay element with control logic and locking circuitry capable of locking the DLL system clock frequency to an external reference clock, and a plurality of secondary phase locking circuits capable of synchronizing a plurality of internal clock signals to any phase of the external reference clock.

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31-03-2009 дата публикации

Embedded test circuit for testing integrated circuits at the die level

Номер: US0007512915B2

A design structure instantiated in a machine readable medium; the design structure includes all of the necessary information for designing a test circuit. The test circuit is used for performing device-specific testing and acquiring parametric data on integrated circuits, for example ASICs, such that each chip is tested individually without excessive test time requirements, additional silicon, or special test equipment. The design structure includes at least one test circuit and may be integrated into an IC design, along with all of the required manufacturing data for producing a final design structure. The final design structure may be in the form of a GDS storage medium or another form of medium suitable for sending the final data structure to, for example, a manufacturer, foundry, customer, or other design house.

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30-10-2008 дата публикации

Embedded Test Circuit For Testing Integrated Circuits At The Die Level

Номер: US20080270951A1
Принадлежит: International Business Machines Corp

A design structure instantiated in a machine readable medium; the design structure includes all of the necessary information for designing a test circuit. The test circuit is used for performing device-specific testing and acquiring parametric data on integrated circuits, for example ASICs, such that each chip is tested individually without excessive test time requirements, additional silicon, or special test equipment. The design structure includes at least one test circuit and may be integrated into an IC design, along with all of the required manufacturing data for producing a final design structure. The final design structure may be in the form of a GDS storage medium or another form of medium suitable for sending the final data structure to, for example, a manufacturer, foundry, customer, or other design house.

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20-01-2005 дата публикации

METHOD FOR REDUCED ELECTRICAL FUSING TIME

Номер: US20050013187A1

A method and electrical fuse circuit design for reducing the testing time for a semiconductor device manufactured with redundant eFuse circuitry. A two-to-one multiplexer (MUX) is provided at each eFuse circuit in addition to the fuse latch and pattern latch and other logic components the eFuse circuit. Information on which fuse is to be blown is stored in the fuse's pattern latch. The output generated by the pattern latch is ANDed with a program input to provide a select signal for the MUX. Based on the select signal, the MUX allows the shifted “1” to either go to the next latch in the shift chain or bypass the next latch or latches in the shift chain depending on whether the next fuse is to be blown. Accordingly, rather than serially shifting through each fuse latch within the device, the invention enables only those fuse latches associated with fuses that are to be blown to hold up the propagation of the shifted “1” to the next eFuse circuits.

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28-07-2005 дата публикации

FUSE LATCH WITH COMPENSATED PROGRAMMABLE RESISTIVE TRIP POINT

Номер: US20050162799A1
Автор: Darren Anand, John Fifield

A fuse latch circuit with a current reference generator is described where the resistive switch point of the latch is stabilized against effects of manufacturing processing, operating voltage and temperature. A digital control word is used to select the desired resistive trip point of the fuse latch and compensation within the reference generator maintains this resistive trip point with high accuracy. The variable resistive trip point is set to a first value at test and then to a second value in use condition to enhance operating margin, and soft error immunity.

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01-08-2002 дата публикации

Method and apparatus for initializing an integrated circuit using compressed data from a remote fusebox

Номер: US20020101777A1

A method and apparatus for initializing an integrated circuit using compressed data from a remote fusebox allows a reduction in the number of fuses required to repair or customize an integrated circuit and allows fuses to be grouped outside of the macros repaired by the fuses. The remote location of fuses allows flexibility in the placement of macros having redundant repair capability, as well as a preferable grouping of fuses for both programming convenience and circuit layout facilitation. The fuses are arranged in rows and columns and represent control words and run-length compressed data to provide a greater quantity of repair points per fuse. The data can be loaded serially into shift registers and shifted to the macro locations to control the selection of redundant circuits to repair integrated circuits having defects or to customize logic.

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26-10-2006 дата публикации

METHOD AND APPARATUS FOR INCREASING FUSE PROGRAMMING YIELD THROUGH PREFERRED USE OF DUPLICATE DATA

Номер: US20060239088A1

Integrated circuit memory is tested to discover defective memory elements. To replace the defective memory elements, spare memory elements are selected and a string is generated to indicate which ones of the spares replace which ones of the defective memory elements. The number of bits of the string depend upon how many of the memory elements are defective. Although a certain number of the memory elements are defective, which determines the number of the string bits, nevertheless, a number of fuses to program on the integrated circuit is determined responsive to how many fuses are available for programming relative to the number of the binary string bits. That is, if more fuses are available than a certain threshold number relative to the number of string bits (as is preferred), then more than the threshold number are programmed. If not, then only that certain threshold number of fuses are programmed.

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08-02-2007 дата публикации

Diagnostic Method and Apparatus For Non-Destructively Observing Latch Data

Номер: US20070033458A1
Принадлежит: Individual

The invention provides a circuit that can observe data within shift registers without altering the data. The circuit includes selectors connected to the inputs and outputs of the shift registers. The selectors selectively connect the input with the output of a selected shift register to form a wiring loop for the selected shift register. A control device connected to the wiring loop uses the wiring loop to cause the data to be continually transferred from the output of the selected shift register to the input of the selected shift register and back through the selected shift register in a circular manner. The control device includes a counter used for determining the length of a selected shift register and a set of registers to store, for future use when rotating data in the shift registers, the length of each shift register. The control device also includes a data output accessible from outside the circuit. An observation wire is connected to the wiring loop, and the data passes from the wiring loop to the control device through the observation wire. The control device outputs data appearing on the wiring loop as the data is circulated through the selected shift register to permit data within the selected shift register to be observed outside the circuit without altering the data within the selected shift register.

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03-03-2005 дата публикации

METHOD FOR SEPARATING SHIFT AND SCAN PATHS ON SCAN-ONLY, SINGLE PORT LSSD LATCHES

Номер: US20050050415A1

A method and circuit design for enabling both shift path and scan path functionality with a single port LSSD latch designed for scan path functionality only, without increasing the device's internal real estate and without substantial increase in overall device real estate. The circuit design eliminates the need for additional logic components to be built into the internal circuitry of the device and also eliminates the cost of providing dual port LSSD latches within the device. Implementation of the invention involves providing a unique configuration of low level logic components as input circuitry that is coupled to a pair of single port LSSD latches that operate as the input latches for the device. The low level logic components accomplishes the splitting of scan chain inputs and shift chain inputs to the input latches and thus enables the single ported LSSD latches to operate with similar functionality as dual ported LSSD latches.

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14-02-2013 дата публикации

FUSEBAY CONTROLLER STRUCTURE, SYSTEM, AND METHOD

Номер: US20130042166A1

Error correction is selectively applied to data, such as repair data to be stored in a fusebay for BIST/BISR on an ASIC or other semiconductor device. Duplicate bit correction and error correction code state machines may be included, and selectors, such as multiplexers, may be used to enable one or both types of correction. Each state machine may include an indicator, such as a “sticky bit,” that may be activated when its type of correction is encountered. The indicator(s) may be used to develop quality and yield control criteria during manufacturing test of parts including embodiments of the invention. 1. A fusebay controller structure comprising:a retrieval input configured to communicate with a storage data register;a retrieval output configured to communicate with a repair data register;a storage input configured to communicate with the repair data register;a storage output configured to communicate with the storage data register;a duplicate bit (DB) state machine having a retrieval mode in which the DB state machine is configured to reconstruct a bit of data from every pair of retrieved bits, and a storage mode in which the DB state machine is configured to generate a duplicate bit of data for each bit of received repair data;an error correction code (ECC) state machine having a retrieval mode in which the ECC state machine is configured to interpret ECC syndrome bits encountered in retrieved data, and a storage mode in which the ECC state machine is configured to generate ECC syndrome bits for received repair data;a first DB selector configured to bypass the DB state machine responsive to a first DB select state and to enable the DB state machine responsive to a second DB select state; anda first ECC selector configured to bypass the ECC state machine responsive to a first ECC select state and to enable the ECC state machine responsive to a second ECC select state.2. The fusebay controller structure of claim 1 , further comprising a compressor connected to the ...

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22-08-2013 дата публикации

REFERENCE GENERATOR WITH PROGRAMMABLE M AND B PARAMETERS AND METHODS OF USE

Номер: US20130215686A1

A reference generator with programmable m and b parameters and methods of use are provided. A circuit includes a first generator operable to generate a first voltage including a fraction of a supply voltage. The circuit further includes a second generator operable to generate a second voltage. The circuit further includes a mixer and buffer circuit operable to output a reference voltage including a sum of the first and second voltages. 1. A circuit comprising:a first generator operable to generate a first voltage comprising a fraction of a supply voltage;a second generator operable to generate a second voltage; anda mixer and buffer circuit operable to output a reference voltage comprising a sum of the first and second voltages.2. The circuit of claim 1 , wherein the second voltage is independent of the supply voltage.3. The circuit of claim 1 , wherein the mixer and buffer circuit is further operable to generate and output a high reference voltage comprising a sum of the reference voltage and an offset voltage.4. The circuit of claim 1 , wherein the first and second voltages are adjustable by respective digital control words.5. The circuit of claim 1 , wherein the first generator comprises an operational amplifier comprising a negative feedback claim 1 , and the operational amplifier is operable to buffer the first voltage.6. The circuit of claim 5 , wherein the first generator further comprises a selectable resistor circuit operable to input the first voltage into the negative feedback of the operational amplifier based on digital control words.7. The circuit of claim 5 , wherein the first generator further comprises a current supply circuit operable to increase linearity of a current based on the first voltage.8. The circuit of claim 1 , wherein the second generator comprises an operational amplifier comprising a negative feedback claim 1 , and the operational amplifier is operable to buffer the second voltage.9. The circuit of claim 8 , wherein the second ...

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28-11-2013 дата публикации

MULTI-BANK RANDOM ACCESS MEMORY STRUCTURE WITH GLOBAL AND LOCAL SIGNAL BUFFERING FOR IMPROVED PERFORMANCE

Номер: US20130315022A1

Disclosed are embodiments of a multi-bank random access memory (RAM) structure that provides signal buffering at both the global and local connector level for improved performance. Specifically, inverters are incorporated into the global connector(s), which traverse groups of memory banks and which transmit signals (e.g., address signals, control signals, and/or data signals) from a memory controller, and also into alternating groups of local connectors, which connect nodes on the global connector(s) to corresponding groups of memory banks, such that any of the signals that are received by the memory banks from the memory controller via the global and local connectors are buffered by an even number of inverters and are thereby true signals. Signal buffering at both the global and local connector level results in relatively fast slews, short propagation delays, and low peak power consumption with minimal, if any, increase in area consumption. 1. A memory structure comprising:groups of memory banks, each group of memory banks comprising at least one memory bank;a global connector traversing said groups of memory banks and comprising first inverters electrically connected in series; andgroups of local connectors electrically connecting nodes on said global connector to said groups of memory banks,each group of local connectors comprising at least one local connector,each portion of said global connector between adjacent nodes comprising a single first inverter, andin alternating groups of local connectors across said global connector, each local connector further comprising a second inverter such that any signals received by any memory bank via said global connector are buffered by an even number of inverters.2. The memory structure of claim 1 , said signals comprising any of address signals claim 1 , control signals and data signals.3. The memory structure of claim 1 , said second inverter being smaller than said first inverters.4. The memory structure of claim 1 , ...

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30-01-2020 дата публикации

Program and erase memory structures

Номер: US20200035295A1
Принадлежит: Globalfoundries Inc

The present disclosure generally relates to semiconductor structures and, more particularly, to program and erase memory structures and methods of manufacture. The semiconductor memory includes: a charge trap transistor; and a self-heating circuit which selectively applies voltages to terminals of the charge trap transistor to assist in erase operations of the charge trap transistor.

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11-04-2019 дата публикации

Margin test for multiple-time programmable memory (mtpm) with split wordlines

Номер: US20190108894A1
Принадлежит: Globalfoundries Inc

The present disclosure relates to a structure which includes a twin-cell memory which includes a first device and a second device and which is configured to store data which corresponds to a threshold voltage difference between the first device controlled by a first wordline and the second device controlled by a second wordline.

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07-06-2018 дата публикации

PARALLEL PROGRAMMING OF ONE TIME PROGRAMMABLE MEMORY ARRAY FOR REDUCED TEST TIME

Номер: US20180158532A1
Принадлежит:

The present disclosure relates to a method of a non-volatile one time programmable memory (OTPM) including parallel programming of all banks of the OTPM by programming two rows per bank at a time, verifying the programming by comparing a first row of the two rows per bank, and verifying the programming by comparing a second row of the two rows per bank. 1. A method of a non-volatile one time programmable memory (OTPM) , comprising:parallel programming of all banks of the OTPM by programming two rows per bank at a time;verifying the programming by comparing data in a first row of the two rows per bank;verifying the programming by comparing data in a second row of the two rows per bank; andtesting a plurality of wordline drivers of the OTPM using a set of test data lines without writing in a selected array of the banks.2. The method of claim 1 , wherein the parallel programming of all banks of the OTPM by programming two rows per bank at the time comprises writing a data input to the two rows per bank at the time in parallel.3. The method of claim 2 , wherein the verifying the programming by comparing data in the first row of the two rows per bank comprises comparing the written data input to a data output in the first row to determine whether there is a match between the written data input and the data output.4. The method of claim 3 , wherein in response to determining there is a match between the written data input and the data output in the first row claim 3 , masking future writes for the data input in the first row.5. The method of claim 3 , wherein in response to determining there is a mismatch between the written data input and the data output in the first row claim 3 , continuing to write the data input to the first row.6. The method of claim 2 , wherein the verifying the programming by comparing data in the second row of the two rows per bank comprises comparing the written data input to a data output in the second row to determine whether there is a match ...

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23-06-2016 дата публикации

Regulation for multi-phase voltage pump system

Номер: US20160181912A1
Принадлежит: Globalfoundries Inc

An approach of operating a voltage pump system for a semiconductor chip. The approach includes one or more voltage pumps receiving a pair of clock signal inputs. The approach includes activating a first group of voltage pumps with a high clock signal level and activating a second group of voltage pumps activate with a low clock signal level. Furthermore, the approach includes deriving the pair of clock signal inputs from an oscillator and a hold circuit and configuring a current clock signal output level to latch upon receipt of a hold signal.

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05-08-2021 дата публикации

Charge trap memory devices

Номер: US20210242230A1
Принадлежит: GlobalFoundries US Inc

The present disclosure generally relates to semiconductor structures and, more particularly, to charge trap memory devices and methods of manufacture and operation. The semiconductor memory includes: a charge trap transistor comprising a gate structure, a source region and a drain region; and a self-heating circuit which selectively applies an alternating bias direction between the source region and the drain region of the charge trap transistor to provide an erase operation or a programming operation of the charge trap transistor.

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16-08-2018 дата публикации

Circuit and method for detecting time dependent dielectric breakdown (tddb) shorts and signal-margin testing

Номер: US20180233216A1
Принадлежит: Globalfoundries Inc

The present disclosure relates to a structure which includes a twin-cell memory which is configured to program a plurality of write operations, a current sense amplifier which is connected to the twin-cell memory and is configured to sense a current differential and latch a differential voltage based on the current differential, and at least one current source which is connected to the current sense amplifier and is configured to add an offset current to the current sense amplifier to create the differential voltage.

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22-12-2016 дата публикации

LATCHING CURRENT SENSING AMPLIFIER FOR MEMORY ARRAY

Номер: US20160372164A1
Принадлежит:

A latching current sensing amplifier circuit for memory arrays and a current sensing technique using the latching current sensing amplifier circuit are provided. The current sense-amplifier circuit includes a first and second pair of series connected transistors configured with a common gate node for a sense operation and reconfigurable as a cross-coupled pair for a latching operation. 1. A current sense-amplifier circuit comprising a first and second pair of series connected transistors configured with a common gate node for a sense operation and reconfigurable as a cross-coupled pair for a latching operation.2. The current sense-amplifier circuit of claim 1 , wherein the series connected transistors are a self-biased circuit.3. The current sense-amplifier circuit of claim 1 , wherein the first pair of series connected transistors and the second pair of series connected transistors claim 1 , each includes the common-gate node claim 1 , an output-drain node claim 1 , an intermediate node and an input-source node.4. The current sense-amplifier circuit of claim 3 , wherein the output-drain node for each of the pair of series connected transistors is connected to a pair of first current sources claim 3 , respectively.5. The current sense-amplifier circuit of claim 3 , wherein the pair of intermediate nodes for each of the pair of series are connected to a pair of sense lines.6. The current sense-amplifier circuit of claim 3 , wherein the input-source node for each of the pair of series is connected to a power supply.7. The current sense-amplifier circuit of claim 3 , wherein the common-gate node for each pair of series connected transistors is coupled together to the output-drain node in a sense operation claim 3 , and separated and reconfigured in a cross-coupled arrangement in a latch mode.8. The current sense-amplifier circuit of claim 7 , wherein the common-gate node claim 7 , when enabled by a sense signal claim 7 , selectively shorts gates of the first pair of ...

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21-12-2017 дата публикации

LATCHING CURRENT SENSING AMPLIFIER FOR MEMORY ARRAY

Номер: US20170365302A1
Принадлежит:

A latching current sensing amplifier circuit for memory arrays and a current sensing technique using the latching current sensing amplifier circuit are provided. The current sense-amplifier circuit includes a first and second pair of series connected transistors configured with a common gate node for a sense operation and reconfigurable as a cross-coupled pair for a latching operation. 1. A circuit , comprising:a first pair of p-type transistors (PFETs) connected in series;a second pair of PFETs connected in series;a first PFET of the first pair of PFETs and a second PFET of the second pair of PFETs are cross coupled by a common node; anda second PFET of the first pair of PFETs and a first PFET of the second pair of PFETs are cross coupled by the common node.2. The circuit of claim 1 , wherein the first pair of PFETs and the second pair of PFETs form a self-biased circuit.3. The circuit of claim 1 , wherein the first pair of PFETs is connected between Vdd and a MID node and the second pair of PFETs is connected between Vdd and an OUT_ANALOG node.4. The circuit of claim 1 , wherein each of the first pair of PFETs and the second pair of PFETs further comprises an output drain node claim 1 , an intermediate node claim 1 , and an input source node.5. The circuit of claim 4 , wherein the input source node of the first pair of PFETs and the input source node of the second pair of PFETs are coupled to Vdd.6. The circuit of claim 1 , wherein a true bitline (BLT) and a complementary bitline (BLC) of a differential memory cell are coupled at an intermediate node between PFETs of the first pair of PFETs and the second pair of PFETs claim 1 , respectively.7. The circuit of claim 6 , wherein the first pair of series connected PFETs and the second pair of series connected PFETs are each coupled in series to stacked transistors which pull a differential current from the differential memory cell through the BLT and BLC to OUT_ANALOG.8. The circuit of claim 6 , wherein a current is ...

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03-10-2017 дата публикации

Latching current sensing amplifier for memory array

Номер: US9779783B2
Принадлежит: Globalfoundries Inc

A latching current sensing amplifier circuit for memory arrays and a current sensing technique using the latching current sensing amplifier circuit are provided. The current sense-amplifier circuit includes a first and second pair of series connected transistors configured with a common gate node for a sense operation and reconfigurable as a cross-coupled pair for a latching operation.

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08-07-2014 дата публикации

Reference generator with programmable M and B parameters and methods of use

Номер: US8773920B2
Принадлежит: International Business Machines Corp

A reference generator with programmable m and b parameters and methods of use are provided. A circuit includes a first generator operable to generate a first voltage including a fraction of a supply voltage. The circuit further includes a second generator operable to generate a second voltage. The circuit further includes a mixer and buffer circuit operable to output a reference voltage including a sum of the first and second voltages.

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30-01-2007 дата публикации

Electronic fuse blow mimic and methods for adjusting electronic fuse blow

Номер: US7170299B1
Принадлежит: International Business Machines Corp

A system, method and program product for adjusting an environmental variable of a fuse blow of an electronic fuse are disclosed. A mimic NFET is coupled to a fuse blow source voltage line, a fuse blow gate voltage line, and a chip ground in the same manner as the electronic fuse, except that the mimic NFET is not attached to a poly fuse link. The on current (ion) and off current (ioff) of the mimic NFET are measured to determine a blow current of the electronic fuse. The environmental variable is adjusted based on the determined blow current.

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16-04-2024 дата публикации

Structures and methods for deriving stable physical unclonable functions from semiconductor devices

Номер: US11962709B1
Принадлежит: Marvell Asia Pte Ltd

A semiconductor device includes circuitry configured to derive a physical unclonable function. The circuitry includes a plurality of bitcells, each bitcell being readable as one of a ‘0’ value and a ‘1’ value, and sense amplifier circuitry configurable to read values from the plurality of bitcells. The sense amplifier circuitry includes margin circuitry configurable (i) to selectably bias reading of the plurality of bitcells toward one of ‘0’ values and ‘1’ values, (ii) to identify addresses of bitcells having a stable ‘1’ value when the margin circuitry is configured to bias reading of the plurality of bitcells toward ‘0’ values, and (iii) to identify addresses of bitcells having a stable ‘0’ value when the margin circuitry is configured to bias reading of the plurality of bitcells toward ‘1’ values. Each bitcell in the plurality of bitcells may include a differential transistor pair.

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05-08-2021 дата публикации

Charge-trapping-speichervorrichtungen

Номер: DE102021102344A1
Принадлежит: GlobalFoundries US Inc

Die vorliegende Offenbarung betrifft im Allgemeinen Halbleiterstrukturen und insbesondere Charge-Trapping-Speichervorrichtungen und Herstellungsverfahren und einen Betrieb. Der Halbleiterspeicher umfasst: einen Charge-Trapping-Transistor (150) umfassend eine Gate-Struktur (125), einen Source-Bereich (120a) und einen Drain-Bereich (120b); und eine Selbsterwärmungsschaltung, die selektiv eine alternierende Vorspannungsrichtung zwischen dem Source-Bereich (120a) und dem Drain-Bereich (120b) des Charge-Trapping-Transistors (150) anlegt, um eine Löschoperation (145) oder eine Programmieroperation (145a) des Charge-Trapping-Transistors (150) bereitzustellen.

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10-12-2020 дата публикации

Auswahlschaltung

Номер: DE102020204548A1
Принадлежит: Globalfoundries Inc

Die vorliegende Erfindung betrifft eine Struktur, die eine Spannungsauswahlschaltung mit einer ersten Vorrichtung und einer zweiten Vorrichtung umfasst, wobei die Spannungsauswahlschaltung konfiguriert ist, um eine höhere Spannung aus einer ersten Versorgungsspannung und einer zweiten Versorgungsspannung durch die erste Vorrichtung und die zweite Vorrichtung auszugeben, und wobei eine Spannungsdifferenz zwischen der ersten Versorgungsspannung und der zweiten Versorgungsspannung kleiner ist als eine Schwellenspannung.

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19-12-2019 дата публикации

Physikalisch nicht klonbare Funktion in Verwendung eines Twin-Cell-Charge-Trapping-Transistor-Speichers

Номер: DE102019206854A1
Принадлежит: Globalfoundries Inc

Die vorliegende Erfindung bezieht sich auf eine Struktur, die ein Paar von nichtflüchtigen Speichervorrichtungen in einer Speicheranordnung umfasst, die zum Bestimmen eines anfänglichen Datenzustands erfasst und durch einen Schreibvorgang des anfänglichen Datenzustands auf das Paar von nichtflüchtigen Speichervorrichtungen verstärkt werden.

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03-01-2008 дата публикации

Structure for differential efuse sensing without reference fuses

Номер: US20080001251A1
Принадлежит: Individual

A design structure comprising a differential fuse sensing system, which includes a fuse leg configured for introducing a sense current through an electrically programmable fuse (eFUSE) to be sensed, and a differential sense amplifier having a first input node coupled to the fuse leg and a second node coupled to a reference voltage. The fuse leg further includes a current supply device controlled by a variable reference current generator configured to generate an output signal therefrom such that the voltage on the first input node of the sense amplifier is equal to the voltage on the second input node of the sense amplifier whenever the resistance value of the eFUSE is equal to the resistance value of a programmable variable resistance device included within the variable reference current generator.

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30-01-2020 дата публикации

Speicherprogrammier- und Speicherlöschstrukturen

Номер: DE102019209317A1
Принадлежит: Globalfoundries Inc

Die vorliegende Erfindung betrifft allgemein Halbleiterstrukturen und insbesondere das Programmieren und Löschen von Speicherstrukturen und Herstellungsverfahren. Der Halbleiterspeicher umfasst: einen Charge-Trapping-Transistor; und eine Selbsterwärmungsschaltung, die selektiv Spannungen an die Anschlüsse des Charge-Trapping-Transistors anlegt, um Löschvorgänge des Charge-Trapping-Transistors zu unterstützen.

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03-08-2023 дата публикации

Toleranztest für mehrfach programmierbare Speicher (MTPM) mit geteilten Wortleitungen

Номер: DE102018200972B4
Принадлежит: GlobalFoundries US Inc

Struktur umfassend einen Twin-Cell-Speicher mit mindestens einer ersten Speicherzelle (130), die eine erste Vorrichtung und eine zweite Vorrichtung umfasst, wobei der Twin-Cell-Speicher zur Speicherung von Daten ausgebildet ist, die einem Unterschied in den Schwellspannungen der ersten Vorrichtung, die durch eine erste Wortleitung gesteuert wird, und der zweiten Vorrichtung entsprechen, die durch eine zweite Wortleitung gesteuert wird, wobei die erste Wortleitung mit einem gegenüber der zweiten Wortleitung verschiedenen Spannungspotential gegenüber der zweiten Wortleitung während einer Signaltoleranztestoperation freigegeben wird, so dass beide Wortleitungen in der Signaltoleranztestoperation mit unterschiedlichem Spannungspotential freigegeben werden, wobei die erste Vorrichtung und die zweite Vorrichtung komplementäre Zellen der ersten Speicherzelle (130) des Twin-Cell-Speichers darstellen, und wobei die erste Wortleitung und die zweite Wortleitung komplementäre Wortleitungen (WL0_T, ..., WLn_T; WL0_C, ..., WLn_C) der ersten Speicherzelle (130) sind.

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11-04-2019 дата публикации

Toleranztest für mehrfach programmierbare Speicher (MTPM) mit geteilten Wortleitungen

Номер: DE102018200972A1
Принадлежит: Globalfoundries Inc

Die vorliegende Erfindung betrifft eine Struktur, die einen Twin-Cell-Speicher umfasst, der eine erste Vorrichtung und eine zweite Vorrichtung umfasst und der zur Speicherung von Daten ausgebildet ist, die einem Unterschied in der Schwellspannung der ersten Vorrichtung, die durch eine erste Wortleitung gesteuert wird, und der zweiten Vorrichtung entsprechen, die durch eine zweite Wortleitung gesteuert wird.

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18-11-2008 дата публикации

Diagnostic method and apparatus for non-destructively observing latch data

Номер: US7453973B2
Принадлежит: International Business Machines Corp

The invention provides a circuit that can observe data within shift registers without altering the data. The circuit includes selectors connected to the inputs and outputs of the shift registers. The selectors selectively connect the input with the output of a selected shift register to form a wiring loop for the selected shift register. A control device connected to the wiring loop uses the wiring loop to cause the data to be continually transferred from the output of the selected shift register to the input of the selected shift register and back through the selected shift register in a circular manner. The control device includes a counter used for determining the length of a selected shift register and a set of registers to store, for future use when rotating data in the shift registers, the length of each shift register. The control device also includes a data output accessible from outside the circuit. An observation wire is connected to the wiring loop, and the data passes from the wiring loop to the control device through the observation wire. The control device outputs data appearing on the wiring loop as the data is circulated through the selected shift register to permit data within the selected shift register to be observed outside the circuit without altering the data within the selected shift register.

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16-07-2009 дата публикации

Diagnostic method and apparatus for non-destructively observing latch data

Номер: US20090180584A1
Принадлежит: International Business Machines Corp

The invention provides a circuit that can observe data within shift registers without altering the data. The circuit includes selectors connected to the inputs and outputs of the shift registers. The selectors selectively connect the input with the output of a selected shift register to form a wiring loop for the selected shift register. A control device connected to the wiring loop uses the wiring loop to cause the data to be continually transferred from the output of the selected shift register to the input of the selected shift register and back through the selected shift register in a circular manner. The control device includes a counter used for determining the length of a selected shift register and a set of registers to store, for future use when rotating data in the shift registers, the length of each shift register. The control device also includes a data output accessible from outside the circuit. An observation wire is connected to the wiring loop, and the data passes from the wiring loop to the control device through the observation wire. The control device outputs data appearing on the wiring loop as the data is circulated through the selected shift register to permit data within the selected shift register to be observed outside the circuit without altering the data within the selected shift register.

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29-03-2011 дата публикации

Diagnostic method and apparatus for non-destructively observing latch data

Номер: US7916826B2
Принадлежит: International Business Machines Corp

The invention provides a circuit that can observe data within shift registers without altering the data. The circuit includes selectors connected to the inputs and outputs of the shift registers. The selectors selectively connect the input with the output of a selected shift register to form a wiring loop for the selected shift register. A control device connected to the wiring loop uses the wiring loop to cause the data to be continually transferred from the output of the selected shift register to the input of the selected shift register and back through the selected shift register in a circular manner. The control device includes a counter used for determining the length of a selected shift register and a set of registers to store, for future use when rotating data in the shift registers, the length of each shift register. The control device also includes a data output accessible from outside the circuit. An observation wire is connected to the wiring loop, and the data passes from the wiring loop to the control device through the observation wire. The control device outputs data appearing on the wiring loop as the data is circulated through the selected shift register to permit data within the selected shift register to be observed outside the circuit without altering the data within the selected shift register.

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24-04-2018 дата публикации

Circuit and method for detecting time dependent dielectric breakdown (TDDB) shorts and signal-margin testing

Номер: US09953727B1
Принадлежит: Globalfoundries Inc

The present disclosure relates to a structure which includes a twin-cell memory which is configured to program a plurality of write operations, a current sense amplifier which is connected to the twin-cell memory and is configured to sense a current differential and latch a differential voltage based on the current differential, and at least one current source which is connected to the current sense amplifier and is configured to add an offset current to the current sense amplifier to create the differential voltage.

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29-11-2016 дата публикации

Voltage-aware adaptive static random access memory (SRAM) write assist circuit

Номер: US09508420B1
Принадлежит: Globalfoundries Inc

Approaches for a write assist circuit are provided. The write assist circuit includes a plurality of binary weighted boost capacitors which each contain a first node coupled to a bitline and a second node connected to a corresponding boost enabling transistor, and a plurality of boost enabling transistors which each contain a gate connected to a boost control enable signal for controlling a corresponding binary weighted boost capacitor. The boost control enable signal of each of the plurality of boost enabling transistors is controlled by encoded values based on a power supply level.

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