DIGITAL SIGNAL-RATE CONVERTER AND SYSTEMS INCORPORATING SAME

A digital signal-rate converting system. The system includes a first mechanism for receiving a digital input signal characterized by a first rate. A second mechanism interleaves the digital input signal in accordance with a predetermined pattern to yield an adjusted-rate digital signal. The adjusted-rate digital signal is representative of the digital input signal, such as a bandpass signal. In a more specific embodiment, the digital signal-rate converting system is an input interface of a rate-converting Digital-to-Analog Converter (DAC). The rate-converting DAC includes a DAC module, such as multi-bit or a 1-bit DAC module, for receiving the adjusted-rate digital signal and providing an analog output signal with a desired bandwidth or center frequency in response thereto. In the specific embodiment, the adjusted-rate digital signal approximates the digital input signal and is characterized by a rate based on a desired center frequency of the analog output signal. In this embodiment, the ...

Configurable filter and receiver incorporating same

An efficient configurable signal filter. The filter includes a first mechanism for receiving a first signal of a first type and a second signal of a second type. A second mechanism selectively filters the first signal during a first mode of operation, and filters the second signal during a second mode of operation. A third mechanism generates control signals. A fourth mechanism automatically configures the second mechanism to operate in the first mode of operation or the second mode of operation based on the control signals. In a specific embodiment, the first type of signal is characterized by a first rate, and the second type of signal is characterized by a second rate. The first signal and the second signal are digital ADC outputs. The second mechanism includes plural filter blocks, each having one or more Multiply-Accumulate (MAC) pipes. Each of the one or more MAC pipes include one or more MAC blocks that are each associated with a coefficient memory data structure of a coefficient ...

GAS TURBINE ENGINE AIRFOIL TIP RECESSES

A gas turbine engine airfoil extending from an airfoil base to an airfoil tip at a free end of the airfoil and from a leading edge to a trailing edge of the airfoil has at least one recess extending into and circumferentially completely through the airfoil tip and located inwardly of the leading and trailing edges. The recess is located in an area of the airfoil tip subject to high tip vibratory stress and or rubs and may be a circular scallop having a scallop radius and a maximum depth of a few mills in a range of about 0.005-0.01 inches as measured from a nominal tip edge without the recess. The airfoil may be on a radial blade, a stator vane, or an impeller blade. An annular tip seal may surround a plurality of such airfoil tips with an airfoil tip clearance therebetween. 1. A gas turbine engine component comprising:an airfoil extending from an airfoil base to an airfoil tip at a free end of the airfoil,the airfoil extending downstream from a leading edge to a trailing edge of the airfoil,at least one recess extending into and circumferentially completely through the airfoil tip, andthe recess located inwardly of the leading and trailing edges of the airfoil.2. The component as claimed in wherein the recess is located in an area of the airfoil tip subject to high tip vibratory stress and or rubs.3. The component as claimed in wherein the recess is a circular scallop having a scallop radius.4. The component as claimed in wherein the recess has a maximum depth of a few mills in a range of about 0.005-0.01 inches as measured from a nominal tip edge without the recess.5. A gas turbine engine compressor blade comprising:an airfoil extending radially outwardly from an airfoil base located on a gas turbine engine rotor to an airfoil tip at a free end of the airfoil,the airfoil extending downstream from a leading edge to a trailing edge of the airfoil,at least one recess extending into and circumferentially completely through the airfoil tip, andthe recess located ...

FLEXIBLE CHIRP GENERATOR

A processing-efficient chirp generator that allows flexibility in controlling phase, frequency and slope, i.e., rate of change of frequency. In one embodiment, a fine phase propagation block generates phase values in increments of the fine time step, each phase value also offset from other phase values by multiples of a coarse time step. The phase samples are realigned in time after conversion to digital-to-analog converter (DAC) values. 1. A system for generating a sequence of sine wave output values separated by a fine time step , the system comprising:a fine time recursion block comprising a chain of fine phase propagation blocks, a slope input and a slope output;', 'a frequency input and a frequency output;', 'a phase input and a first phase output and a second phase output;', 'a first adder, a second adder, each comprising a first input, a second input and an output; and', 'a slope delay;', 'wherein:', through the slope delay to the slope output; and', 'to a first input of the first adder;, 'the slope input is connected, 'the frequency input is connected to the second input of the first adder;', 'the output of the first adder is connected to the frequency output and to the first input of the second adder;', 'the phase input is connected to the second input of the second adder;', 'the output of the second adder is connected to the first phase output and to the second phase output;, 'a plurality of the fine phase propagation blocks comprisingthe slope output, a frequency output, and the first phase output of each of the plurality of fine phase propagation blocks connected to the slope input, the frequency input, and the phase input, respectively, of a subsequent fine phase propagation block in the chain;a plurality of sine generators, each sine generator having an input and an output, the inputs of the plurality of sine generators connected to the second phase outputs of the plurality of fine phase propagation blocks; anda plurality of delay blocks; each of the ...

A radar with a synthetic aperture and monopulse with reverse monopulse combining weapon guidance

Predictive analog-to-digital converter with direct action.

L'invention concerne les convertisseurs analogique-numérique prédictifs. Un convertisseur analogique-numérique à prédiction linéaire fonctionne entièrement dans un mode d'action directe pour étendre sa dynamique, augmenter sa vitesse de fonctionnement, parvenir à un fonctionnement stable et éviter la nécessité de circuits échantillonneurs-bloqueurs. Un premier quantificateur (Qc) convertit un signal analogique d'entrée en un format numérique, tandis qu'un prédicteur de signal (32) prédit une valeur suivante du signal d'entrée. Après reconversion en format analogique, le signal prédit est comparé avec la valeur suivante réelle du signal d'entrée, pour produire un signal d'erreur qui est converti en un format numérique par un second quantificateur (Qf). Le signal prédit numérique est transmis dans un mode d'action directe et il est combiné avec le signal d'erreur numérique pour produire un signal de sortie numérique de haute précision. Application aux convertisseurs à très haute résolution. The invention relates to predictive analog-to-digital converters. A linear prediction analog-to-digital converter operates entirely in a forward-acting mode to extend its dynamics, increase its operating speed, achieve stable operation, and avoid the need for sample-and-hold circuits. A first quantizer (Qc) converts an input analog signal to a digital format, while a signal predictor (32) predicts a next value of the input signal. After converting back to analog format, the predicted signal is compared with the next actual value of the input signal, to produce an error signal which is converted to a digital format by a second quantizer (Qf). The digital predicted signal is transmitted in a feedforward mode and is combined with the digital error signal to produce a high precision digital output signal. Application to very high resolution converters.

Combined Sar Monopulse and Inverse Monopulse Weapon Guidance

A system (10) and method (20) that provides for all-weather precision guidance of conventional air-to-surface weapons. The system (10) and method employs a coherent monopulse radar (12) disposed on a launch platform (11) and a noncoherent passive (receive only) radar (14) disposed on the weapon (13). The synthetic aperture radar (12) generates a synthetic aperture radar monopulse map of an area around the target (15). The radar (12) is used designate the location of the target (15), and transmit a sequence of alternating sum and simultaneous azimuth and elevation difference patterns centered on the target (15). The weapon (13) includes a guidance system and seeker (14) that is responsive to guidance commands transmitted by the synthetic aperture radar (12). The guidance system and seeker (14) receives reflections of the alternating sum and combined azimuth and elevation difference pattern from the target (15), and the sum pulse is used by the weapon (13) to acquire and track the azimuth and elevation difference pattern null on the target (15) to fly an optimum trajectory to the target (15). One method for guiding a weapon (13) to a target comprises the following steps. A synthetic aperture radar (12) is used to generate (21) a SAR monopulse map of a target area and designate a target (15) therein. The weapon (13) is then launched (23) toward the target (15). The radar (12) is used to transmit (24) an interleaved sum and simultaneous azimuth and elevation difference pattern guidance pulse train at the target (15). The reflected interleaved sum and simultaneous azimuth and elevation difference pattern is received (25) from the target (15) at a seeker and guidance system (14) on the weapon (13). The sum pattern is used by the weapon (15) to lock (26) onto the converging null, and is used by the launch platform (11) to provide closed loop tracking of the target (15) during guidance illumination. After weapon null lock-on, steering commands are generated (27) to cause ...

Turbine stator vane frame

process for laser shock hammering front or rear edges of gas turbine engine blades.

Laser shock peening integrally bladed rotor blade edges

A method for laser shock peening rotor blade (108) leading and trailing edges (LE, TE) of gas turbine engine integrally bladed rotors and disks that are not blocked by other rows of blades is described. The method includes continuously firing a stationary laser beam (102), which repeatable pulses between relatively constant periods, along at least a portion of leading or trailing edges (LE, TE) of the blade (108), with the laser beam (102) aimed at an oblique angle (110) with respect to a surface of the edge such that laser pulses form overlapping elliptical shaped laser spots (60). In the exemplary embodiment of the invention, the elliptical shaped laser spots (60) have an overlap of about 50% and are on the order of 11.7 mm by 4 mm in diameter. Another method is for laser shock peening rotor blade leading and trailing edges (LE, TE) of gas turbine engine integrally bladed rotors and disks that are blocked by other rows of blades. The method includes continuously firing the stationary laser beam (102), which repeatable pulses between relatively constant periods, along at least a portion of leading or trailing edges (LE, TE) of the blade (108), with the laser beam (102) compoundly angled such that it is aimed at a first oblique angle (110) with respect to a surface of the edge and at a second oblique angle with respect to an axis about which the rotor is circumscribed. Laser pulses form the elliptical shaped laser spots (60) that are angled from the leading edge (LE) radially inwardly towards the axis. In the exemplary embodiment, the elliptical shaped laser spots (60) have an overlap of about 50%.

Optoelectronic phased array with digital transmit signal interface

A true time delay phased array is provided which includes a digital subarray interface in the transmit signal path. The digital transmit signal path interface includes a digital reference signal generation means and digital signal propagation means for supplying the digital reference signal to the subarray. Each subarray includes RF carrier signal generating means for generating an RF carrier signal phase coherent with the reference signal, a fiber optic true time delay circuit for applying an appropriate phase delay to the RF carrier and an appropriate true time delay to the modulation signal, and a waveform modulator for modulating the modulating signal onto the phase locked RF carrier signal to provide the transmit signal for the subarray. The present invention can be used in conjunction with existing digital interface technology for receive and control signal paths to provide an entirely digital subarray signal path interface.

turbine guide

Feed forward predictive analog-to-digital converter

Part span shrouded fan blisk

Including a disk, a plurality of circumferentially spaced apart airfoils extending radially outwardly from the disk, a plurality of shroud segments being disposed circumferentially between the plurality of airfoils and configured to attach to a corresponding airfoil of the plurality of airfoils and a plurality of wear surfaces, where at least one wear surface of the plurality of wear surfaces is configured and disposed to prevent excessive wear between the adjacent shroud segments. Each shroud segment of the plurality of shroud segments may be attached to a corresponding airfoil by weld connections to permit clearance during translation friction welding of the airfoil to the disk hub are located to avoid high stress areas.

Corner tang fan blade

A fan blade (12) includes perforated anchor tangs (32-38), one with inboard corners (46) and the remainder without. The corners are disposed in a complementary seat (44) in a rotor disk (14) for limiting blade pivoting during assembly.

Fan blade configuration

A fan blade (12) includes perforated anchor tangs (32-38), one with inboard corners (46) and the remainder without. The corners are disposed in a complementary seat (44) in a rotor disk (14) for limiting blade pivoting during assembly.

Flexible chirp generator

A processing-efficient chirp generator that allows flexibility in controlling phase, frequency and slope, i.e., rate of change of frequency. In one embodiment, a fine phase propagation block (305) generates phase values in increments of the fine time step (m), each phase value also offset from other phase values by multiples of a coarse time step (N). The phase samples are realigned in time after conversion to digital-to-analog converter (DAC) values.

Configurable filter and receiver incorporating same

An efficient configurable signal filter (52). The filter (52) includes a first mechanism for receiving a first signal of a first type and a second signal of a second type. A second mechanism (60,62) selectively filters the first signal during a first mode of operation and filters the second signal during a second mode of operation. A third mechanism (68) generates control signals. A fourth mechanism (64,68) automatically configures the second mechanism (60,62) to operate in the first mode of operation or the second mode of operation based on the control signals. In a specific embodiment, the first type of signal is characterized by a first rate, and the second type of signal is characterized by second rate. The first signal and the second signal are digital ADC outputs. The second mechanism (60,62) includes plural filter blocks (60,62), each having one or more Multiply-Accumulate (MAC) blocks. Each of the one or more MAC blocks include one or more MAC pipes that are each associated with a coefficient memory data structure of a coefficient memory (64). The third mechanism (68) or a user selects coefficients from each memory data structure to apply to each MAC block, thereby selectively affecting filter response. The control signals direct multiplexers or switches to configure the MAC pipes in a serial configuration or a parallel configuration corresponding to the first mode of operation or the second mode of operation, respectively.

Desfasador digital de precision.

UN CAMBIADOR DE FASE (50) EMPLEA CIRCUITERIA DIGITAL PARA CONSEGUIR CONTROL DE FASE ARBITRARIAMENTE DE SEÑALES DE REFERENCIA A FRECUENCIAS QUE EXTIENDE A LA REGION DE GIGAHERTZ. EL CAMBIADOR DE FASE (50) INCLUYE UNA CASCADA DE UNIDADES COMBINADORAS DE FASE IDENTICA QUE COMPRENDE UN DIVISOR DE FRECUENCIA DE MODO DUAL (52A) SEGUIDO POR UN DIVISOR ADICIONAL (58A), CUYA SALIDA ESTA CONVERTIDA POR UN MEZCLADOR DIGITAL (60A). EL EFECTO DE LA CASCADA ES PARA PROPORCIONAR LA RESOLUCION DEL CONTROL DE FASE PROGRESIVAMENTE SOBRE UN RANGO COMPLETO DE 360 GRADOS. EL CAMBIADOR DE FASE SUMINISTRADO POR CADA ESTADO SE DETERMINA POR EL CONTROL DE DIVISOR (112A), QUE REGULA EL NUMERO DE CICLOS DEL DIVISOR DE MODO DUAL (52A) QUE SE PRODUCE POR UNA ELECCION DE UNA DE LAS RELACIONES DE DIVISION. LA PRECISION DE FASE SE ESTABLECE POR EL NUMERO DE ESTADOS USADOS.

Configurable filter and receiver incorporating same

An efficient configurable signal filter (52). The filter (52) includes a first mechanism for receiving a first signal of a first type and a second signal of a second type. A second mechanism (60, 62) selectively filters the first signal during a first mode of operation and filters the second signal during a second mode of operation. A third mechanism (68) generates control signals. A fourth mechanism (64, 68) automatically configures the second mechanism (60, 62) to operate in the first mode of operation or the second mode of operation based on the control signals. In a specific embodiment, the first type of signal is characterized by a first rate, and the second type of signal is characterized by second rate. The first signal and second signal are digital ADC outputs. The second mechanism (60, 62) includes plural filter blocks (60, 62), each having one or more Multiply-Accumulate (MAC) blocks. Each of the one or more MAC blocks include one or more MAC pipes that are each associated with a coefficient memory data structure of a coefficient memory (64). The third mechanism (68) or a user selects coefficients from each memory data structure to apply to each MAC block, thereby selectively affecting filter response. The control signals direct multiplexers or switches to configure the MAC pipes in a serial configuration or a parallel configuration corresponding to the first mode of operation or the second mode of operation, respectively.

Configurable filter and receiver incorporating same

An efficient configurable signal filter (52). The filter (52) includes a first mechanism for receiving a first signal of a first type and a second signal of a second type. A second mechanism (60,62) selectively filters the first signal during a first mode of operation and filters the second signal during a second mode of operation. A third mechanism (68) generates control signals. A fourth mechanism (64,68) automatically configures the second mechanism (60,62) to operate in the first mode of operation or the second mode of operation based on the control signals. In a specific embodiment, the first type of signal is characterized by a first rate, and the second type of signal is characterized by second rate. The first signal and the second signal are digital ADC outputs. The second mechanism (60,62) includes plural filter blocks (60,62), each having one or more Multiply-Accumulate (MAC) blocks. Each of the one or more MAC blocks include one or more MAC pipes that are each associated with a coefficient memory data structure of a coefficient memory (64). The third mechanism (68) or a user selects coefficients from each memory data structure to apply to each MAC block, thereby selectively affecting filter response. The control signals direct multiplexers or switches to configure the MAC pipes in a serial configuration or a parallel configuration corresponding to the first mode of operation or the second mode of operation, respectively.

Configurable filter and receiver incorporating same

Konfigurerbart filter og mottaker som innarbeider det samme

Configurable filter and receiver incorporating same

An efficient configurable signal filter (52). The filter (52) includes a first mechanism for receiving a first signal of a first type and a second signal of a second type. A second mechanism (60,62) selectively filters the first signal during a first mode of operation and filters the second signal during a second mode of operation. A third mechanism (68) generates control signals. A fourth mechanism (64,68) automatically configures the second mechanism (60,62) to operate in the first mode of operation or the second mode of operation based on the control signals. In a specific embodiment, the first type of signal is characterized by a first rate, and the second type of signal is characterized by second rate. The first signal and the second signal are digital ADC outputs. The second mechanism (60,62) includes plural filter blocks (60,62), each having one or more Multiply-Accumulate (MAC) blocks. Each of the one or more MAC blocks include one or more MAC pipes that are each associated with a coefficient memory data structure of a coefficient memory (64). The third mechanism (68) or a user selects coefficients from each memory data structure to apply to each MAC block, thereby selectively affecting filter response. The control signals direct multiplexers or switches to configure the MAC pipes in a serial configuration or a parallel configuration corresponding to the first mode of operation or the second mode of operation, respectively.

Präzises digitales Phasenschieberelement

Flexibler programmierbarer sigma-delta Analogwandler

Präzises digitales Phasenschieberelement

Elemento desfasador digital de precision.

UN CIRCUITO DE DESFASE DIGITAL DE PRECISION (100;120) PARA CONSEGUIR UN DESFASE PRECISO DE UNA SEÑAL DE TREN DE PULSO DE ENTRADA. LA SALIDA ES UN TREN DE PULSOS A UNA FRECUENCIA IGUAL A LA FRECUENCIA DE SEÑAL DE ENTRADA DIVIDIDA POR N, Y QUE TIENE N ESTADOS DE FASE ESPACIADOS IGUALMENTE. EL ESTADO DE FASE RELATIVO DE LA SEÑAL DE SALIDA ES CONTROLADO FIABLEMENTE POR BORRADO SELECTIVO DE PULSOS DESDE EL TREN DE PULSOS DE LA SEÑAL DE ENTRADA. EL BORRADOR SELECTO PUEDE SER CONSEGUIDO DISPONIENDO SELECTIVAMENTE (102) EL TREN DE PULSO DE ENTRADA, O POR EL USO DE UN CIRCUITO DIVISOR DE FRECUENCIA DE MODULOS DUALES (122).

Digitaler Phasenschieber mit Frequenzteiler

Convertidor de señal analogica delta-sigma, flexible y programable.

Un convertidor de señal analógica delta-sigma programable (20), caracterizado por: un modulador delta-sigma de sobremuestreo (21) para muestrear y cuantificar a un bit una señal de entrada compuesta por una señal de banda limitada a una frecuencia portadora; un convertidor serie a paralelo (22) conectado al modulador delta-sigma; un filtro de diezmado digital (23) para filtrar digitalmente la señal de salida del modulador delta-sigma y producir una estimación de las componentes en fase y en cuadratura de la banda de base de la señal de entrada; filtros de imagen (27, 28) en fase y en cuadratura para procesar la señal de salida del filtro de diezmado para generar muestras en fase y en cuadratura que son la salida del convertidor de señal analógica; una pluralidad de convertidores digital a analógico (25) conectados al modulador delta-sigma (21); y un controlador (26) conectado a la pluralidad de convertidores digital a analógico para centrar los ceros de la conformación del ruido del modulador delta-sigma alrededor de la frecuencia portadora, y conectado al convertidor serie a paralelo para ajustar el espaciamiento entre los ceros para maximizar la relación señal/ruido de la salida digital del convertidor de señal analógica, y conectado al convertidor serie a paralelo para ajustar los tiempos de muestreo del mismo para muestrear la portadora en cuadratura y conectado al filtro de diezmado para programar los coeficientes del mismo para formar un filtro de paso de banda a la frecuencia de la portadora y conectado a los filtros de imagen en fase y en cuadratura para programar los coeficientes de los mismos para formar filtros de paso de banda a la frecuencia de la señal portadora diezmada.

Flexibler programmierbarer sigma-delta Analogwandler

Konfigurerbart filter og mottaker som innarbeider det samme

Et effektivt konfigurerbart signalfilter (52). Filteret (52) innbefatter en første mekanisme for å motta et første signal av en første type og et andre signal av en andre type. En andre mekanisme (60, 61) filtrerer selektivt det første signalet under den første driftsmodus og filtrerer det andre signalet under en andre driftsmodus. En tredje mekanisme (68) danner styringssignaler. En fjerde mekanisme (64, 68) konfigurerer automatisk den andre mekanismen til å arbeide i den første driftsmodusen eller den andre driftsmodusen basert på styringssignalene. I en spesifikk utførelsesform karakteriseres den første signaltypen av en første hastighet, og den andre signaltypen er karakterisert ved den andre hastighet. Det første signalet og det andre signalet er digitale ADC utmatinger. Den andre mekanismen (60, 62) innbefatter et flertall av filterblokker som hver har en eller flere multipliser-akkumuler (MAC)-blokker. Hver av de en eller flere MAC-blokkene innbefatter en eller flere MAC-paiper som hver er forbundet med en koeffisientminne datastruktur av et koeffisientminne (64). Den tredje mekanismen (68) eller en bruker velger koeffisienter fra hver minnedatastruktur for å anvendes på hver MAC-blokk, hvorved selektivt påvirker signalresponsen. Styringssignalene ordner multiplekserne eller svitsjene til å konfigurere MAC-paipene i en seriell konfigurasjon eller en parallell konfigurasjon motsvarende henholdsvis den første driftsmodusen eller den andre driftsmodusen.

Desfasador numerico con divisor de frecuencia.

UN DESFASADOR DIVISOR DE FRECUENCIA DIGITAL COMPRENDE UN DIVISOR CONTADOR DE MODULO DUAL (102) CONTROLADO POR UN CONTADOR DIGITAL PROGRAMABLE (112). UNA CUENTA INICIAL QUE CORRESPONDE A UN DESFASE DESEADO SE INTRODUCE DENTRO DEL CONTADOR PROGRAMABLE (112). EL DIVISOR CONTADOR DE MODULO DUAL (102) DIVIDE POR UNO DE LOS MODULOS MIENTRAS EL CONTADOR PROGRAMABLE CUENTE LA CUENTA INTRODUCIDA, DE DONDE SE SELECCIONA EL OTRO MODULO. UNA PLURALIDAD DE TALES DESFASADORES PUEDE SUMINISTRAR UN MONTAJE DE CIRCUITOS EN PARALELO DE UN NUMERO DE UNIDADES DE DESFASE BASICAS, CADA UNA DE LAS CUALES INCLUYE UN CONTADOR/DIVISOR DE MODULO DUAL Y CIRCUITERIA DE CONTROL DE FASE (170) PARA CONTROLAR EL MODULO CONTADOR. LAS SALIDAS DE VARIAS UNIDADES SON COMBINADAS EN PARALELO. CON LAS RELACIONES DIVISORAS DE TODOS LOS DIVISORES DE LAS UNIDADES QUE SE COMPONE DE RAICES DE PAREJAS DE NUMEROS RELATIVAMENTE PRIMOS, EL NUMERO TOTAL DE ESTADOS DE FASE ES IGUAL A LA MULTIPLICACION DE SUS RELACIONES DIVISORAS.

Dds spur mitigation in a high performance radar exciter

A technique is described for providing a pulsed radar exciter signal, in a radar exciter including a direct digital synthesizer (DDS) (60). The DDS is reset pulse-to-pulse to provide a pulsed DDS signal having pulse-to-pulse phase discontinuities due to the resetting of the DDS. The phase of the pulsed DDS signal can be shifted pulse-to-pulse by a phase shift that is held constant over a pulse to correct the pulse-to-pulse phasing of the DDS signal. A discrete phase modulator (70) can provide the phase shift. The phase of the pulsed DDS signal can be shifted pulse-to-pulse by an additional phase shift which is a linear phase sequence from pulse-to-pulse, or by an additional phase shift which is a quadratic phase sequence from pulse-to-pulse to produce a ranging wafeform.

Verringerung von dds störsignalen in einem hochleistungsradarerreger