Phase detection in an analog clock data recovery circuit with decision feedback equalization

An embodiment of the invention relates to a method of phase detection in a receiver circuit with decision feedback equalization. Partial-equalization and full-equalization edge signals are generated. The feedback from the first tap of the decision feedback equalizer is separated from the feedback of the remaining plurality of taps. The feedback from the plurality of taps (not including the first tap) is used to generate partial-equalization edge signals, while the feedback from all the taps is used to generate full-equalization edge signals. The partial-equalization and full-equalization edge signals are utilized by phase-detection circuitry to provide highly-accurate data sampling locations for improved performance.

Edge based partial response equalization

An integrated circuit (IC) memory device includes receiver circuitry to receive write data from a memory controller. The receiver circuitry includes equalization circuitry having at least one tap to equalize the write data. The equalization circuitry includes a tap weight adapter circuit to adaptively generate a tap weight for the tap from an edge analysis of previously received write data.

HYBRID CLOCK DATA RECOVERY CIRCUITRY FOR PULSE AMPLITUDE MODULATION SCHEMES

An integrated circuit for supporting a high-speed communications link. The integrated circuit may include equalization and hybrid phase detection circuitry configured to perform clock data recovery (CDR) for high-order pulse amplitude modulated (PAM) signals. The phase detector circuit includes partial oversampling sampling circuitry that generates edge samples an incoming PAM signal and Baud rate sampling circuitry that generates error and data samples on the PAM signals. Edge, data, and error samples may be passed to error minimization circuitry within an adaptation circuit that may dynamically compute contributions to a weighted phase error by oversampling and Baud rate components. The adaptation circuit may use the weighted phase error to adjust the phase of a recovered clock signal used to recover data transmitted through the high speed communications link. 1. An integrated circuit , comprising:a first sampling circuit that receives a data signal and obtains a corresponding edge sample;a second sampling circuit that receives the data signal and obtains a corresponding error sample; andadaptation logic circuitry that adjusts the first and second sampling circuits based on the edge sample and the error sample.2. The integrated circuit of claim 1 , wherein the first sampling circuit comprises an oversampling circuit.3. The integrated circuit of claim 1 , wherein the second sampling circuit comprises a baud rate sampling circuit claim 1 , and wherein the error sample is computed based on discrepancies between a data signal sampled by the second sampling circuit and an expected Baud rate locking condition.4. The integrated circuit of claim 1 , wherein the second sampling circuit further obtains a data sample that is fed to the adaptation logic circuitry.5. The integrated circuit of claim 1 , wherein the first and second sampling circuits receive a data signal that transitions from a first data value to a second data value claim 1 , and wherein the edge sample is ...

Methods and circuits for reducing clock jitter

A communication system includes a continuous-time linear equalizer in the clock forward path. The equalizer may be adjusted to minimize clock jitter, including jitter associated with the first few clock edges after the clock signal is enabled. Reducing early-edge jitter reduces the power and circuit complexity otherwise needed to turn the system on quickly.

METHODS AND CIRCUITS FOR ASYMMETRIC DISTRIBUTION OF CHANNEL EQUALIZATION BETWEEN DEVICES

A transceiver architecture supports high-speed communication over a signal lane that extends between a high-performance integrated circuit (IC) and one or more relatively low-performance ICs employing less sophisticated transmitters and receivers. The architecture compensates for performance asymmetry between ICs communicating over a bidirectional lane by instantiating relatively complex transmit and receive equalization circuitry on the higher-performance side of the lane. Both the transmit and receive equalization filter coefficients in the higher-performance IC may be adaptively updated based upon the signal response at the receiver of the higher-performance IC. 1. (canceled)2. An integrated circuit comprising:a transmit equalizer having a transmit-equalizer control port, the transmit equalizer to equalize a first signal resulting in a first equalized signal, using a first range of coefficients, applied to the transmit-equalizer control port;a receive port to receive a corrupted second signal that includes noise;a signal monitor to provide a measure of the noise of the second signal; andequalization control circuitry coupled between the signal monitor and the transmit-equalizer control port.3. The integrated circuit of claim 2 , further comprising a receive equalizer having a receive-equalizer control port claim 2 , the receive equalizer to increase a ratio of the second signal to the noise.4. The integrated circuit of claim 3 , wherein the equalization control circuitry is coupled to the receive-equalizer control port.5. The integrated circuit of claim 3 , wherein the signal monitor is coupled to the receive port via the receive equalizer.6. The integrated circuit of claim 2 , wherein the transmit equalizer includes a pre-cursor filter tap claim 2 , and wherein the equalization control circuitry controls the pre-cursor filter tap based upon the measure of the noise of the second signal.7. The integrated circuit of claim 2 , wherein the signal monitor measures a ...

Signaling with superimposed clock and data signals

A data transmission circuit includes a clock driver to obtain a clock signal having a first rate and to drive the clock signal onto one or more transmission lines. The data transmission circuit also includes a timing circuit to obtain the clock signal and to generate a symbol clock having a second rate. The first rate is a multiple of the second rate, wherein the multiple is greater than one. The data transmission circuit further includes a data driver synchronized to the symbol clock. The data driver obtains a data signal and drives the data signal onto the one or more transmission lines at the second rate. The data signal and the clock signal are driven onto the one or more transmission lines simultaneously.

EDGE BASED PARTIAL RESPONSE EQUALIZATION

A device implements data reception with edge-based partial response decision feedback equalization. In an example embodiment, the device implements a tap weight adapter circuit that sets the tap weights that are used for adjustment of a received data signal. The tap weight adapter circuit sets the tap weights based on previously determined data values and input from an edge analysis of the received data signal using a set of edge samplers. The edge analysis may include adjusting the sampled data signal by the tap weights determined by the tap weight adapter circuit. A clock generation circuit generates an edge clock signal to control the edge sampling performed by the set of edge samplers. The edge clock signal may be generated as a function of the signals of the edge samplers and prior data values determined by the equalizer. 1sampling a data signal having a voltage value at an expected edge time of the data signal:generating a first alpha value and a second alpha value in dependence upon the voltage value;adjusting the data signal by the first alpha value to derive a first adjusted signal;adjusting the data signal by the second alpha value to derive a second adjusted signal;sampling the first adjusted signal to output a first data value;sampling the second adjusted signal to output a second data value; andselecting between the first data value and the second data value as a function of a prior received data value to determine a received data value.. A method comprising: This application is a Continuation of U.S. application Ser. No. 12/513,898, filed Dec. 23, 2009, which is the national phase entry of International Application No. PCT/U.S.2007/023600, filed Nov. 9,2007, which claims benefit of priority to U.S. Provisional Application No. 60/859,820, filed Nov. 16, 2006; all of the priority claims are hereby incorporated by Reference in their entirety for all purposes.The performance of conventional digital systems is limited by the transmission interconnection ...

GRAPHITIC CARBON-DOPED AND MIXED CRYSTAL-TYPE TITANIUM DIOXIDE NANOTUBE COMPOSITE FOR ELECTROCATALYSIS, AND PREPARATION METHOD AND USE THEREOF

The present disclosure belongs to the technical field of electrocatalytic materials, and provides a graphitic carbon-doped and mixed crystal-type titanium dioxide nanotube composite for electrocatalysis, and a preparation method and use thereof. The composite for electrocatalysis includes a titanium substrate and a titanium dioxide nanomesh deposited on the titanium substrate, where the titanium dioxide nanomesh is woven from titanium dioxide nanowires; the titanium dioxide nanowires include anatase-type titanium dioxide nanowires and rutile-type titanium dioxide nanowires. The mixed crystal-type titanium dioxide phase improves a catalytic activity of the composite for electrocatalysis; meanwhile, the titanium dioxide nanowires are further loaded with graphitic carbon particles to improve an overall conductivity of the composite for electrocatalysis. Therefore, the composite for electrocatalysis has a high electron mobility to achieve an improved electrocatalytic activity, which can be applied to the degradation of organic pollutants by electrocatalysis.

Stochastic steady state circuit analyses

A method for simulating a system without a time invariant or periodically time-varying steady state is provided. The method limits the number of states included in a Markov chain model by discretizing the states based on Gaussian decomposition, utilizes a state exploration algorithm that discovers only recurrent states, and/or utilizes a state truncation algorithm that eliminates states with negligible stationary probabilities.

Method and apparatus for source-synchronous signaling

A low-power, high-performance source-synchronous chip interface which provides rapid turn-on and facilitates high signaling rates between a transmitter and a receiver located on different chips is described in various embodiments. Some embodiments of the chip interface include, among others: a segmented “fast turn-on” bias circuit to reduce power supply ringing during the rapid power-on process; current mode logic clock buffers in a clock path of the chip interface to further reduce the effect of power supply ringing; a multiplying injection-locked oscillator (MILO) clock generator to generate higher frequency clock signals from a reference clock; a digitally controlled delay line which can be inserted in the clock path to mitigate deterministic jitter caused by the MILO clock generator; and circuits for periodically re-evaluating whether it is safe to retime transmit data signals in the reference clock domain directly with the faster clock signals.

METHOD AND APPARATUS FOR SOURCE-SYNCHRONOUS SIGNALING

A low-power, high-performance source-synchronous chip interface which provides rapid turn-on and facilitates high signaling rates between a transmitter and a receiver located on different chips is described in various embodiments. Some embodiments of the chip interface include, among others: a segmented “fast turn-on” bias circuit to reduce power supply ringing during the rapid power-on process; current mode logic clock buffers in a clock path of the chip interface to further reduce the effect of power supply ringing; a multiplying injection-locked oscillator (MILO) clock generator to generate higher frequency clock signals from a reference clock; a digitally controlled delay line which can be inserted in the clock path to mitigate deterministic jitter caused by the MILO clock generator; and circuits for periodically re-evaluating whether it is safe to retime transmit data signals in the reference clock domain directly with the faster clock signals. 120- (canceled)21. An integrated circuit device , comprising:a set of serially coupled clock path stages; anda duty-cycle error correction circuit coupled to the set of clock path stages, wherein the duty-cycle error correction circuit is configured to measure a cumulative duty-cycle error associated with the clock path and correct the cumulative duty-cycle error along the clock path.22. The integrated circuit device of claim 21 , wherein the duty-cycle error correction circuit corrects the cumulative duty-cycle error at a single location.23. The integrated circuit device of claim 21 , wherein the duty-cycle error correction circuit measures the cumulative duty-cycle error at a location following the set of clock path stages in the clock path.24. The integrated circuit device of claim 21 , wherein each clock path stage of the set of clock path stages includes a delay element implemented using a digitally controlled delay line.25. The integrated circuit device of claim 21 , wherein the duty-cycle error correction circuit ...

Methods and circuits for asymmetric distribution of channel equalization between devices

A transceiver architecture supports high-speed communication over a signal lane that extends between a high-performance integrated circuit (IC) and one or more relatively low-performance ICs employing less sophisticated transmitters and receivers. The architecture compensates for performance asymmetry between ICs communicating over a bidirectional lane by instantiating relatively complex transmit and receive equalization circuitry on the higher-performance side of the lane. Both the transmit and receive equalization filter coefficients in the higher-performance IC may be adaptively updated based upon the signal response at the receiver of the higher-performance IC.

Methods and circuits for asymmetric distribution of channel equalization between devices

A transceiver architecture supports high-speed communication over a signal lane that extends between a high-performance integrated circuit (IC) and one or more relatively low-performance ICs employing less sophisticated transmitters and receivers. The architecture compensates for performance asymmetry between ICs communicating over a bidirectional lane by instantiating relatively complex transmit and receive equalization circuitry on the higher-performance side of the lane. Both the transmit and receive equalization filter coefficients in the higher-performance IC may be adaptively updated based upon the signal response at the receiver of the higher-performance IC.

Clock and Data Recovery Having Shared Clock Generator

This disclosure provides a clock recovery circuit for a multi-lane communication system. Local clocks are recovered from the input signals using respective local CDR circuits, and associated CDR error signals are aggregated or otherwise combined. A global recovered clock for shared use by the local CDR circuits is generated at a controllable oscillation frequency as a function of a combination of the error signals from the plurality of receivers. A voltage- or current-controlled delay line can also be used to phase adjust the global recovered clock to mitigate band-limited, lane-correlated, high frequency jitter. 117-. (canceled)18. A device comprising:a plurality of receivers responsive to a global recovered clock, the receivers including local phase detectors which provide local error signals indicating timing differences between respective input data signals and associated local sampling times; anda global clock generator coupled to the plurality of receivers, the global clock generator having a controllable oscillator to generate the global recovered clock at a frequency of oscillation in dependence on the local error signals.19. The device of claim 18 , wherein the controllable oscillator includes a voltage controlled oscillator to generate the global recovered clock claim 18 , the voltage controlled oscillator controlled by a voltage that is dependent on the local error signals.20. The device of claim 19 , wherein the global clock generator includes a circuit to generate a combined error signal in response to the local error signals by aggregating the local error signals to produce an output claim 19 , and a digital to analog converter to generate the voltage in a manner dependent on the output.21. The device of claim 20 , wherein the circuit to generate a combined error signal further includes a Delta-Sigma modulator.22. The device of claim 18 , further including a delay locked loop coupled to the controllable oscillator to receive a timing signal at the ...

Methods and Circuits for Asymmetric Distribution of Channel Equalization Between Devices

A transceiver architecture supports high-speed communication over a signal lane that extends between a high-performance integrated circuit (IC) and one or more relatively low-performance ICs employing less sophisticated transmitters and receivers. The architecture compensates for performance asymmetry between ICs communicating over a bidirectional lane by instantiating relatively complex transmit and receive equalization circuitry on the higher-performance side of the lane. Both the transmit and receive equalization filter coefficients in the higher-performance IC may be adaptively updated based upon the signal response at the receiver of the higher-performance IC.

Calibrating a retro-directive array for an asymmetric wireless link

The disclosed embodiments relate to a technique for calibrating a retro-directive array. During the calibration process, the system measures a gain g1 through a first pair of antennas in the retro-directive array. Next, the system measures a gain g2 through a second pair of antennas in the retro-directive array. The system then simultaneously measures a combined gain G1,2 through the first and second pairs of antennas in the retro-directive array. If G1,2 is less than g1+g2 by more than a threshold value, the system calibrates a phase relationship between the first and second pairs of antennas.

Receiver with Clock Recovery Circuit and Adaptive Sample and Equalizer Timing

A receiver is equipped with an adaptive phase-offset controller and associated timing-calibration circuitry that together shift the timing for a data sampler and a digital equalizer. The sample and equalizer timing is shifted to a position with less residual inter-symbol interference (ISI) energy relative to the current symbol. The shifted position may be calculated using a measure of signal quality, such as a receiver bit-error rate or a comparison of filter-tap values, to optimize the timing of data recovery. 1. (canceled)2. A receiver comprising:a data input port;an edge sampler coupled to the data input port;clock recovery circuitry having a clock-recovery input port, coupled to the data input port via the edge sampler, and a clock-recovery output port;a data sampler having a data-sampler input terminal, coupled to the data input port, and a data-sampler output terminal;an equalizer coupled to the data-sampler input terminal, the equalizer having an equalizer clock terminal; andan adaptive phase-offset controller coupled between the clock-recovery output port of the clock recovery circuitry and the equalizer clock terminal, the phase-offset controller having a phase-offset control port.3. The receiver of claim 2 , wherein the data input port is to receive a signal comprised of a series of data symbols and the data sampler is to sample the data symbols to produce a series of sampled data claim 2 , the receiver further comprising a signal quality measurement circuit claim 2 , coupled to the phase-offset control port claim 2 , to derive a quality measure for the sampled data.4. The receiver of claim 3 , further comprising equalization control circuitry coupled to the signal quality measurement circuit.5. The receiver of claim 2 , further comprising a second data sampler coupled between the data input port and the clock recovery circuitry.6. The receiver of claim 5 , wherein the edge sampler receives an edge clock signal having an edge-clock phase claim 5 , the ...

Method and apparatus for source-synchronous signaling

A low-power, high-performance source-synchronous chip interface which provides rapid turn-on and facilitates high signaling rates between a transmitter and a receiver located on different chips is described in various embodiments. Some embodiments of the chip interface include, among others: a segmented “fast turn-on” bias circuit to reduce power supply ringing during the rapid power-on process; current mode logic clock buffers in a clock path of the chip interface to further reduce the effect of power supply ringing; a multiplying injection-locked oscillator (MILO) clock generator to generate higher frequency clock signals from a reference clock; a digitally controlled delay line which can be inserted in the clock path to mitigate deterministic jitter caused by the MILO clock generator; and circuits for periodically re-evaluating whether it is safe to retime transmit data signals in the reference clock domain directly with the faster clock signals.

HIGH-ACCURACY DETECTION IN COLLABORATIVE TRACKING SYSTEMS

An electronic device for wirelessly tracking the position of a second electronic device is disclosed. The electronic device includes transceiver circuitry and processing circuitry. The transceiver circuitry includes a beacon generator to generate a beacon at a particular frequency and direction. An antenna array transmits the beacon, and receives at least one modulated reflected beacon from the second electronic device. The transceiver circuitry also includes a discriminator to discriminate between received modulated reflected beacons and received reflected interfering beacons. The processing circuitry couples to the transceiver circuitry and tracks the position of the second device based on the modulated reflected beacons. 1. An electronic device for wirelessly tracking the position of a second electronic device , the electronic device comprising: a beacon generator to generate a beacon at a particular frequency and direction,', 'an antenna array to transmit the beacon, and to receive at least one modulated reflected beacon from the second electronic device, and', 'a discriminator to discriminate between received modulated reflected beacons and received reflected interfering beacons; and, 'transceiver circuitry including'}processing circuitry coupled to the transceiver circuitry to determine the position of the second device based on the modulated reflected beacons.2. The electronic device according to wherein the transceiver circuitry further includes a modulator to modulate the beacon signal prior to transmission by the antenna array.3. The electronic device according to wherein the modulator comprises a linear frequency modulator (LFM).4. The electronic device according to wherein the modulator comprises a pulse modulator.5. The electronic device according to wherein the second electronic device comprises a wireless mobile gaming controller.6. The electronic device according to embodied as a game console unit.7. The electronic device according to wherein:the ...

PARTIAL RESPONSE DECISION-FEEDBACK EQUALIZATION WITH ADAPTATION BASED ON EDGE SAMPLES

A device (102) implements data reception with edge-based partial response decision feedback equalization. In an example embodiment, the device implements a tap weight adapter circuit (114) that sets the tap weights that are used for adjustment of a received data signal (104). The tap weight adapter circuit (119) sets the tap weights based on previously determined data values and input from an edge analysis of the received data signal using a set of edge samplers. The edge analysis (116) may include adjusting the sampled data signal by the tap weights determined by the tap weight adapter circuit. A clock generation circuit (220) generates an edge clock signal to control the edge sampling performed by the set of edge samplers. The edge clock signal may be generated as a function of the signals of the edge samplers and prior data values determined by the equalizer.

Clock and Data Recovery Having Shared Clock Generator

This disclosure provides a clock recovery circuit for a multi-lane communication system. Local clocks are recovered from the input signals using respective local CDR circuits, and associated CDR error signals are aggregated or otherwise combined. A global recovered clock for shared use by the local CDR circuits is generated at a controllable oscillation frequency as a function of a combination of the error signals from the plurality of receivers. A voltage- or current-controlled delay line can also be used to phase adjust the global recovered clock to mitigate band-limited, lane-correlated, high frequency jitter. 1. (canceled)2. An integrated circuit , comprising:receivers, each receiver to receive and sample a respective data signal carrying a respective embedded clock, the embedded clocks generated responsive to a common timing source; anda global clock generator to generate a global clock for distribution to each of the receivers; each one of the receivers has a respective clock recovery circuit to adjust a respective clock derived from the global clock to track the respective embedded clock in dependence on locally-generated error, and', 'the integrated circuit further comprises circuitry to control generation of the global clock dependent on an average of the locally-generated error from the respective clock recovery circuits., 'wherein'}3. The integrated circuit of claim 2 , wherein the integrated circuit further comprises circuitry to limit change in a generation control parameter for the global clock to when the average of the locally-generated error is greater than or equal to a clock cycle of the global clock.4. The integrated circuit of claim 2 , further comprising a phase adjustment circuit to receive the global clock and to adjust a phase of the global clock as a function of a sum of the locally-generated error from the respective clock recovery circuits claim 2 , wherein the circuitry to control generation of the global clock is characterized by an ...

Receiver with clock recovery circuit and adaptive sample and equalizer timing

A receiver is equipped with an adaptive phase-offset controller and associated timing-calibration circuitry that together shift the timing for a data sampler and a digital equalizer. The sample and equalizer timing is shifted to a position with less residual inter-symbol interference (ISI) energy relative to the current symbol. The shifted position may be calculated using a measure of signal quality, such as a receiver bit-error rate or a comparison of filter-tap values, to optimize the timing of data recovery.

METHODS AND CIRCUITS FOR ASYMMETRIC DISTRIBUTION OF CHANNEL EQUALIZATION BETWEEN DEVICES

A transceiver architecture supports high-speed communication over a signal lane that extends between a high-performance integrated circuit (IC) and one or more relatively low-performance ICs employing less sophisticated transmitters and receivers. The architecture compensates for performance asymmetry between ICs communicating over a bidirectional lane by instantiating relatively complex transmit and receive equalization circuitry on the higher-performance side of the lane. Both the transmit and receive equalization filter coefficients in the higher-performance IC may be adaptively updated based upon the signal response at the receiver of the higher-performance IC. 1. (canceled)2. A memory system comprising:a memory controller;a memory integrated-circuit; and a transmit equalizer having a transmit-data input node to receive a transmit signal and a transmit-equalizer control port to receive a transmit coefficient, the transmit equalizer to produce an equalized signal responsive to the transmit signal and the transmit coefficient;', 'a receive port coupled to the memory integrated-circuit to receive, from the memory integrated-circuit, a corrupted signal that includes inter-symbol interference;', 'a signal monitor coupled to the receive port to receive the corrupted signal and to provide a measure of the inter-symbol interference of the corrupted signal; and', 'equalization control circuitry coupled between the signal monitor and the transmit-equalizer control port, the equalization control circuitry to derive the transmit coefficient from the measure of the inter-symbol interference., 'a memory buffer communicatively disposed between the memory controller and the memory integrated-circuit, the memory buffer including3. The memory system of claim 2 , the memory buffer further comprising a receive equalizer having a receive-equalizer control port claim 2 , the receive equalizer to equalize the inter-symbol interference of the corrupted signal to produce a second ...

METHODS AND CIRCUITS FOR REDUCING CLOCK JITTER

A communication system includes a continuous-time linear equalizer in the clock forward path. The equalizer may be adjusted to minimize clock jitter, including jitter associated with the first few clock edges after the clock signal is enabled. Reducing early-edge jitter reduces the power and circuit complexity otherwise needed to turn the system on quickly. 1. An integrated circuit comprising:a data sampler having a data input node, a data output node, and a clock node;a data path extending to the data input node;a clock path extending from a clock source to the clock node and including a linear equalizer, the linear equalizer having an equalization control port; andequalization control circuitry coupled between the data output node and the equalization control port.2. The integrated circuit of claim 1 , wherein the equalizer is a linear equalizer.3. The integrated circuit of claim 2 , wherein the equalizer is a continuous-time equalizer.4. The integrated circuit of claim 2 , wherein the clock path further includes a clock buffer.5. The integrated circuit of claim 4 , wherein the clock buffer is a linear buffer.6. The integrated circuit of claim 5 , wherein the clock buffer is a CML buffer.7. The integrated circuit or claim 1 , wherein the equalization control port receives an offset signal that adjusts a voltage offset of the equalizer.8. The integrated circuit of claim 7 , wherein the control circuitry applies the offset signal for a first edge of a clock signal in the clock path to produce an equalized clock signal and removes the offset responsive to an edge of the equalized clock signal.9. The integrated circuit of claim 1 , wherein the linear equalizer is one of a plurality of linear equalizers selectively included in the clock path claim 1 , wherein a number of linear equalizers selectively included in the clock path defines delay through the clock path.10. The integrated circuit of claim 9 , further comprising a multiplexer in the clock path to select an ...

METHODS AND CIRCUITS FOR ASYMMETRIC DISTRIBUTION OF CHANNEL EQUALIZATION BETWEEN DEVICES

A transceiver architecture supports high-speed communication over a signal lane that extends between a high-performance integrated circuit (IC) and one or more relatively low-performance ICs employing less sophisticated transmitters and receivers. The architecture compensates for performance asymmetry between ICs communicating over a bidirectional lane by instantiating relatively complex transmit and receive equalization circuitry on the higher-performance side of the lane. Both the transmit and receive equalization filter coefficients in the higher-performance IC may be adaptively updated based upon the signal response at the receiver of the higher-performance IC.

Methods and circuits for asymmetric distribution of channel equalization between devices

A transceiver architecture supports high-speed communication over a signal lane that extends between a high-performance integrated circuit (IC) and one or more relatively low-performance ICs employing less sophisticated transmitters and receivers. The architecture compensates for performance asymmetry between ICs communicating over a bidirectional lane by instantiating relatively complex transmit and receive equalization circuitry on the higher-performance side of the lane. Both the transmit and receive equalization filter coefficients in the higher-performance IC may be adaptively updated based upon the signal response at the receiver of the higher-performance IC.

Receiver with Clock Recovery Circuit and Adaptive Sample and Equalizer Timing

A receiver is equipped with an adaptive phase-offset controller and associated timing-calibration circuitry that together shift the timing for a data sampler and a digital equalizer. The sample and equalizer timing is shifted to a position with less residual inter-symbol interference (ISI) energy relative to the current symbol. The shifted position may be calculated using a measure of signal quality, such as a receiver bit-error rate or a comparison of filter-tap values, to optimize the timing of data recovery.

Edge based partial response equalization

An intergrated circuit (IC) chip includes receiver circuitry to receive signals from a second IC chip. The receiver circuitry includes equalization circuitry having at least one tap to equalize the signals. The equalization circuitry includes a tap weight adapter circuit to generate at least one tap weight corresponding to the at least one tap based on edge information of previously received signals.

Stochastic Steady State Circuit Analyses

A method for simulating a system without a time invariant or periodically time-varying steady state is provided. The method limits the number of states included in a Markov chain model by discretizing the states based on Gaussian decomposition, utilizes a state exploration algorithm that discovers only recurrent states, and/or utilizes a state truncation algorithm that eliminates states with negligible stationary probabilities.

Edge based partial response equalization

A method is disclosed. The method includes sampling a data signal having a voltage value at an expected edge time of the data signal. A first alpha value is generated, and a second alpha value generated in dependence upon the voltage value. The data signal is adjusted by the first alpha value to derive a first adjusted signal. The data signal is adjusted by the second alpha value to derive a second adjusted signal. The first adjusted signal is sampled to output a first data value while the second adjusted signal is sampled to output a second data value. A selection is made between the first data value and the second data value as a function of a prior received data value to determine a received data value.

Methods and circuits for asymmetric distribution of channel equalization between devices

A transceiver architecture supports high-speed communication over a signal lane that extends between a high-performance integrated circuit (IC) and one or more relatively low-performance ICs employing less sophisticated transmitters and receivers. The architecture compensates for performance asymmetry between ICs communicating over a bidirectional lane by instantiating relatively complex transmit and receive equalization circuitry on the higher-performance side of the lane. Both the transmit and receive equalization filter coefficients in the higher-performance IC may be adaptively updated based upon the signal response at the receiver of the higher-performance IC.

Adjusting a continuous time linear equalization-based receiver

Devices and methods for adjusting operation of a receiver that includes a continuous time linear equalizer, a decision feedback equalizer, and a feed forward equalizer. Operation of the receiver may be controlled by determining whether the receiver is operating in operation region using frequency responses of the feed forward equalizer at a first frequency and a second frequency and using the frequency responses of the decision feedback equalizer at the first frequency and the second frequency. If the operation is outside the frequency, a parameter of the continuous time linear equalizer is adjusted based on the frequency responses of the feed forward equalizer and the decision feedback equalizer.

Receiver with clock recovery circuit and adaptive sample and equalizer timing

A receiver is equipped with an adaptive phase-offset controller and associated timing-calibration circuitry that together shift the timing for a data sampler and a digital equalizer. The sample and equalizer timing is shifted to a position with less residual inter-symbol interference (ISI) energy relative to the current symbol. The shifted position may be calculated using a measure of signal quality, such as a receiver bit-error rate or a comparison of filter-tap values, to optimize the timing of data recovery.

METHOD AND APPARATUS FOR SOURCE-SYNCHRONOUS SIGNALING

A low-power, high-performance source-synchronous chip interface which provides rapid turn-on and facilitates high signaling rates between a transmitter and a receiver located on different chips is described in various embodiments. Some embodiments of the chip interface include, among others: a segmented “fast turn-on” bias circuit to reduce power supply ringing during the rapid power-on process; current mode logic clock buffers in a clock path of the chip interface to further reduce the effect of power supply ringing; a multiplying injection-locked oscillator (MILO) clock generator to generate higher frequency clock signals from a reference clock; a digitally controlled delay line which can be inserted in the clock path to mitigate deterministic jitter caused by the MILO clock generator; and circuits for periodically re-evaluating whether it is safe to retime transmit data signals in the reference clock domain directly with the faster clock signals. 1. A method for operating an integrated circuit device , comprising:phase-aligning a data signal and a first timing signal to produce a first phase-aligned data signal;generating a second timing signal from the first timing signal using a frequency multiplying circuit, the second timing signal being mesochronous with respect to the first timing signal; andretiming the first phase-aligned data signal to produce a second phase-aligned data signal that is phase-aligned to a clock domain based on the second timing signal.2. The method of claim 1 , wherein retiming the first phase-aligned data signal comprises:determining whether a phase-relationship between the first-phase aligned data signal and the clock domain based on the second timing signal is within an unsafe range for retiming the first phase-aligned data signal based on the second timing signal;adjusting the first phase-aligned data signal to produce a phase-adjusted data signal, a phase-relationship between the phase-adjusted data signal and the second timing ...

Methods and circuits for reducing clock jitter

A communication system includes a continuous-time linear equalizer in the clock forward path. The equalizer may be adjusted to minimize clock jitter, including jitter associated with the first few clock edges after the clock signal is enabled. Reducing early-edge jitter reduces the power and circuit complexity otherwise needed to turn the system on quickly.

METHOD AND APPARATUS FOR SOURCE-SYNCHRONOUS SIGNALING

A low-power, high-performance source-synchronous chip interface which provides rapid turn-on and facilitates high signaling rates between a transmitter and a receiver located on different chips is described in various embodiments. Some embodiments of the chip interface include, among others: a segmented “fast turn-on” bias circuit to reduce power supply ringing during the rapid power-on process; current mode logic clock buffers in a clock path of the chip interface to further reduce the effect of power supply ringing; a multiplying injection-locked oscillator (MILO) clock generator to generate higher frequency clock signals from a reference clock; a digitally controlled delay line which can be inserted in the clock path to mitigate deterministic jitter caused by the MILO clock generator; and circuits for periodically re-evaluating whether it is safe to retime transmit data signals in the reference clock domain directly with the faster clock signals. 1. A method for synchronizing a current mode logic (CML) clock signal with a CMOS gate signal , the method comprising:receiving a CMOS gate signal and a CML clock signal, wherein the CMOS gate signal has an undetermined phase relationship with respect to the CML clock signal; andretiming the CMOS gate signal based on the CML clock signal so that a transition of the retimed CMOS gate signal is substantially phase-aligned with a midpoint between two adjacent transitions in the CML clock signal.2. The method of claim 1 , wherein the midpoint between two adjacent transitions of the CML clock signal corresponds to a logic low of the CML clock signal.3. The method of claim 1 , wherein retiming the CMOS gate signal based on the CML clock signal involves using a transition in the CML clock signal to trigger a gate in the retimed CMOS gate signal.4. The method of claim 1 , wherein prior to receiving the CMOS gate signal claim 1 , the method further comprises synthesizing the CMOS gate signal based on a duration control signal and ...

Signaling with superimposed differential-mode and common-mode signals

A data receiver circuit (206) includes first and second interfaces (221) coupled to first and second respective transmission lines (204). The first and second respective transmission lines comprise a pair of transmission lines external to the data receiver circuit. The first and second interfaces receive a transmission signal from the pair of transmission lines. A common mode extraction circuit (228) is coupled to the first and second interfaces to extract a common-mode clock signal from the received transmission signal. A differential mode circuit (238) is coupled to the first and second interfaces to extract a differential-mode data signal from the received transmission signal. The extracted data signal has a symbol rate corresponding to a frequency of the extracted clock signal (e.g., the symbol rate may be twice the frequency of the extracted clock signal). The differential mode circuit is synchronized to the extracted clock signal.

EDGE BASED PARTIAL RESPONSE EQUALIZATION

A method is disclosed. The method includes sampling a data signal having a voltage value at an expected edge time of the data signal. A first alpha value is generated, and a second alpha value generated in dependence upon the voltage value. The data signal is adjusted by the first alpha value to derive a first adjusted signal. The data signal is adjusted by the second alpha value to derive a second adjusted signal. The first adjusted signal is sampled to output a first data value while the second adjusted signal is sampled to output a second data value. A selection is made between the first data value and the second data value as a function of a prior received data value to determine a received data value.

Signaling with Superimposed Clock and Data Signals

A data transmission circuit includes a clock driver to obtain a clock signal having a first rate and to drive the clock signal onto one or more transmission lines. The data transmission circuit also includes a timing circuit to obtain the clock signal and to generate a symbol clock having a second rate. The first rate is a multiple of the second rate, wherein the multiple is greater than one. The data transmission circuit further includes a data driver synchronized to the symbol clock. The data driver obtains a data signal and drives the data signal onto the one or more transmission lines at the second rate. The data signal and the clock signal are driven onto the one or more transmission lines simultaneously.

METHODS AND CIRCUITS FOR ASYMMETRIC DISTRIBUTION OF CHANNEL EQUALIZATION BETWEEN DEVICES

A transceiver architecture supports high-speed communication over a signal lane that extends between a high-performance integrated circuit (IC) and one or more relatively low-performance ICs employing less sophisticated transmitters and receivers. The architecture compensates for performance asymmetry between ICs communicating over a bidirectional lane by instantiating relatively complex transmit and receive equalization circuitry on the higher-performance side of the lane. Both the transmit and receive equalization filter coefficients in the higher-performance IC may be adaptively updated based upon the signal response at the receiver of the higher-performance IC. 1. (canceled)2. An integrated circuit comprising:a transmit equalizer having a transmit-equalizer control port, the transmit equalizer to equalize a first signal resulting in a first equalized signal, using a first range of coefficients, applied to the transmit-equalizer control port;a receive port to receive a corrupted second signal that includes inter-symbol interference;a signal monitor to provide a measure of the inter-symbol interference of the second signal; andequalization control circuitry coupled between the signal monitor and the transmit-equalizer control port.3. The integrated circuit of claim 2 , further comprising a receive equalizer having a receive-equalizer control port claim 2 , the receive equalizer to equalize the inter-symbol interference of the second signal.4. The integrated circuit of claim 3 , wherein the equalization control circuitry is coupled to the receive-equalizer control port.5. The integrated circuit of claim 3 , wherein the signal monitor is coupled to the receive port via the receive equalizer.6. The integrated circuit of claim 2 , wherein the transmit equalizer includes a pre-cursor filter tap claim 2 , and wherein the equalization control circuitry controls the pre-cursor filter tap based upon the measure of inter-symbol interference of the second signal.7. A method ...

Methods and circuits for asymmetric distribution of channel equalization between devices

A transceiver architecture supports high-speed communication over a signal lane that extends between a high-performance integrated circuit (IC) and one or more relatively low-performance ICs employing less sophisticated transmitters and receivers. The architecture compensates for performance asymmetry between ICs communicating over a bidirectional lane by instantiating relatively complex transmit and receive equalization circuitry on the higher-performance side of the lane. Both the transmit and receive equalization filter coefficients in the higher-performance IC may be adaptively updated based upon the signal response at the receiver of the higher-performance IC.

Receiver with Clock Recovery Circuit and Adaptive Sample and Equalizer Timing

A receiver is equipped with an adaptive phase-offset controller and associated timing-calibration circuitry that together shift the timing for a data sampler and a digital equalizer. The sample and equalizer timing is shifted to a position with less residual inter-symbol interference (ISI) energy relative to the current symbol. The shifted position may be calculated using a measure of signal quality, such as a receiver bit-error rate or a comparison of filter-tap values, to optimize the timing of data recovery.

Receiver with clock recovery circuit and adaptive sample and equalizer timing

A receiver is equipped with an adaptive phase-offset controller and associated timing-calibration circuitry that together shift the timing for a data sampler and a digital equalizer. The sample and equalizer timing is shifted to a position with less residual inter-symbol interference (ISI) energy relative to the current symbol. The shifted position may be calculated using a measure of signal quality, such as a receiver bit-error rate or a comparison of filter-tap values, to optimize the timing of data recovery.

Methods and circuits for asymmetric distribution of channel equalization between devices

A transceiver architecture supports high-speed communication over a signal lane that extends between a high-performance integrated circuit (IC) and one or more relatively low-performance ICs employing less sophisticated transmitters and receivers. The architecture compensates for performance asymmetry between ICs communicating over a bidirectional lane by instantiating relatively complex transmit and receive equalization circuitry on the higher-performance side of the lane. Both the transmit and receive equalization filter coefficients in the higher-performance IC may be adaptively updated based upon the signal response at the receiver of the higher-performance IC.

Clock and data recovery having shared clock generator

This disclosure provides a clock recovery circuit for a multi-lane communication system. Local clocks are recovered from the input signals using respective local CDR circuits, and associated CDR error signals are aggregated or otherwise combined. A global recovered clock for shared use by the local CDR circuits is generated at a controllable oscillation frequency as a function of a combination of the error signals from the plurality of receivers. A voltage- or current-controlled delay line can also be used to phase adjust the global recovered clock to mitigate band-limited, lane-correlated, high frequency jitter.

Partial response decision-feedback equalization with adaptation based on edge samples

A device (102) implements data reception with edge-based partial response decision feedback equalization. In an example embodiment, the device implements a tap weight adapter circuit (114) that sets the tap weights that are used for adjustment of a received data signal (104). The tap weight adapter circuit (119) sets the tap weights based on previously determined data values and input from an edge analysis of the received data signal using a set of edge samplers. The edge analysis (116) may include adjusting the sampled data signal by the tap weights determined by the tap weight adapter circuit. A clock generation circuit (220) generates an edge clock signal to control the edge sampling performed by the set of edge samplers. The edge clock signal may be generated as a function of the signals of the edge samplers and prior data values determined by the equalizer.

Receiver with clock recovery circuit and adaptive sample and equalizer timing

A receiver is equipped with an adaptive phase-offset controller and associated timing-calibration circuitry that together shift the timing for a data sampler and a digital equalizer. The sample and equalizer timing is shifted to a position with less residual inter-symbol interference (ISI) energy relative to the current symbol. The shifted position may be calculated using a measure of signal quality, such as a receiver bit-error rate or a comparison of filter-tap values, to optimize the timing of data recovery.

FREQUENCY RESPONSIVE BUS CODING

A data system permits bus encoding based on frequency of the bus and the frequency of switching on the bus so as to avoid undesirable frequency conditions such as a resonant condition or interference with other electrical devices. Transmission frequencies along one or more busses are monitored and used to control the encoding process, for example, an encoding process based on data bus inversion (DBI). The use of both a measure of an absolute number of logic levels (“DBI_DC”) and a measure of a number of logic level transitions relative to a prior signal (“DBI_AC”) provides a measure of control that may be used to compensate for both main and predriver switching noise.

Edge based partial response equalization

An integrated circuit (IC) memory controller includes receiver circuitry to receive read data from a memory. The receiver circuitry includes equalization circuitry having at least one tap to apply data level equalization to the read data, and a tap weight adapter circuit. The tap weight adapter circuit adaptively generates a data level tap weight corresponding to the data level equalization from an edge analysis of previously received read data.

EDGE BASED PARTIAL RESPONSE EQUALIZATION

A method is disclosed. The method includes sampling a data signal having a voltage value at an expected edge time of the data signal. A first alpha value is generated, and a second alpha value generated in dependence upon the voltage value. The data signal is adjusted the first alpha value to derive a first adjusted signal. The data signal is adjusted by the second alpha value to derive a second adjusted signal. The first adjusted signal is sampled to output a first data value while the second adjusted signal is sampled to output a second data value. A selection is made between the first data value and the second data value as a function of a prior received data value to determine a received data value. 1. (canceled)2. An integrated circuit (IC) memory controller comprising:transmit circuitry to transmit write data to a memory; and equalization circuitry to apply a level of equalization to the read data, and', 'wherein the level of equalization is adaptively generated from an edge analysis of previously received read data., 'receiver circuitry to receive read data from the memory, the receiver circuitry including'}3. The IC memory controller according to claim 2 , wherein the edge analysis is based on a pattern of multiple edge-sampled read data signals.4. The IC memory controller according to claim 2 , wherein the equalizer comprises a decision-feedback equalizer (DFE).5. The IC memory controller according to claim 4 , wherein the equalizer comprises a partial response decision-feedback equalizer (PrDFE).6. The IC memory controller according to claim 5 , wherein the PrDFE includes parallel alternative decision paths claim 5 , and the data signal is received along each of the parallel alternative decision paths.7. The IC memory controller according to claim 6 , wherein the equalization circuitry is to adjust a voltage of the received data signal along each of the parallel alternative decision paths.8. The IC memory controller according to claim 2 , wherein the ...

Method and apparatus for source-synchronous signaling

A low-power, high-performance source-synchronous chip interface which provides rapid turn-on and facilitates high signaling rates between a transmitter and a receiver located on different chips is described in various embodiments. Some embodiments of the chip interface include, among others: a segmented fast turn-on bias circuit to reduce power supply ringing during the rapid power-on process; current mode logic clock buffers in a clock path of the chip interface to further reduce the effect of power supply ringing; a multiplying injection-locked oscillator (MILO) clock generator to generate higher frequency clock signals from a reference clock; a digitally controlled delay line which can be inserted in the clock path to mitigate deterministic jitter caused by the MILO clock generator; and circuits for periodically re-evaluating whether it is safe to retime transmit data signals in the reference clock domain directly with the faster clock signals.

ADJUSTING A CONTINUOUS TIME LINEAR EQUALIZATION-BASED RECEIVER

Devices and methods for adjusting operation of a receiver that includes a continuous time linear equalizer, a decision feedback equalizer, and a feed forward equalizer. Operation of the receiver may be controlled by determining whether the receiver is operating in operation region using frequency responses of the feed forward equalizer at a first frequency and a second frequency and using the frequency responses of the decision feedback equalizer at the first frequency and the second frequency. If the operation is outside the frequency, a parameter of the continuous time linear equalizer is adjusted based on the frequency responses of the feed forward equalizer and the decision feedback equalizer.

Calibration for Mismatch in Receiver Circuitry with Multiple Samplers

Receiver circuitries having multiple branches, such as unrolled feedback equalizers and fractional-rate receivers, may present differences between filtering elements of different branches with common filter inputs. Embodiments include devices capable of calibration that compensates such differences. The devices may be capable of introducing front-end offsets to emphasize the mismatches, and sweep filter input values to calculate the mismatches, and introducing offsets in the branches to compensate for the mismatches. Methods for use of the calibration devices are also described. 1. An electronic device comprising a receiver that comprises:front-end circuitry configured to amplify an input signal to provide an internal signal, wherein the front-end circuitry is configured to receive a front-end offset;a first branch comprising a first summer configured to receive the internal signal and a tap signal and to provide a first filtered signal, and a first sampler configured to receive the first filtered signal, wherein the first sampler comprises a first correction offset value;a second branch comprising a second summer configured to receive the internal signal and the tap signal and to provide a second filtered signal, and a second sampler configured to receive the second filtered signal, wherein the second sampler comprises a second correction offset value; and setting the front-end offset to a first value;', 'determining a first crossover tap value that changes a first output of the first sampler;', 'determining a second crossover tap value that changes a second output of the second sampler; and', 'adjusting the first correction offset value and the second correction offset value based, at least in part, on the first crossover tap value and the second crossover tap value., 'processing circuitry configured to perform a calibration process, wherein the calibration process comprises2. The electronic device of claim 1 , wherein the receiver comprises a decision feedback ...

Receiver with Clock Recovery Circuit and Adaptive Sample and Equalizer Timing

A receiver is equipped with an adaptive phase-offset controller and associated timing-calibration circuitry that together shift the timing for a data sampler and a digital equalizer. The sample and equalizer timing is shifted to a position with less residual inter-symbol interference (ISI) energy relative to the current symbol. The shifted position may be calculated using a measure of signal quality, such as a receiver bit-error rate or a comparison of filter-tap values, to optimize the timing of data recovery. 1. (canceled)2. A receiver comprising:a data input port to receive data symbols;an equalizer coupled to the data input port to receive and equalize the data symbols, the equalizer timed to an equalizer clock signal;a data sampler coupled to the equalizer to sample the equalized data symbols responsive to a data-clock signal and issue the sampled data symbols as data samples; anda phase offset controller to independently phase adjust the data-clock signal and the equalizer clock signal.3. The receiver of claim 2 , wherein the equalizer produces a feedback signal to subtract from the data symbols responsive to the data samples.4. The receiver of claim 3 , wherein the equalizer is a decision-feedback equalizer.5. The receiver of claim 2 , further comprising signal-quality measurement circuitry to issue a measure of signal quality to the phase offset controller claim 2 , the phase offset controller phase adjusting the data-clock signal relative to the equalizer clock signal responsive to the measure of signal quality.6. The receiver of claim 5 , further comprising equalization control circuitry coupled to the data sampler claim 5 , the equalizer claim 5 , and the signal-quality measurement circuitry claim 5 , the equalization control circuitry to control the equalizer and the signal-quality measurement circuitry responsive to the sampled data signals.7. The receiver of claim 6 , further comprising an edge sampler to sample edges of at least one of the data ...

Integrated circuit with continuously adaptive equalization circuitry

An integrated circuit for supporting a high-speed communications link is provided. The integrated circuit may include equalization circuitry having a continuous time linear equalizer (CTLE) circuit, a decision feedback equalizer (DFE) circuit, and associated adaptation logic for controlling the CTLE circuit and the DFE circuit. The adaptation logic may include an error minimization adaptation circuit operable to generate at least a first post-cursor value, a signal amplitude detection circuit operable to generate a main cursor value, and a CTLE adaptation circuit configured to compute a ratio between the first post-cursor value and the main cursor value. The CTLE adaptation circuit may compare the computed ratio to predetermined values to determine whether or not to adjust the peaking gain of the CTLE circuit to help minimize inter-symbol interference for signals traveling through the high-speed communications link.

Graphitic carbon-doped and mixed crystal-type titanium dioxide nanotube composite for electrocatalysis, and preparation method and use thereof

The present disclosure belongs to the technical field of electrocatalytic materials, and provides a graphitic carbon-doped and mixed crystal-type titanium dioxide nanotube composite for electrocatalysis, and a preparation method and use thereof. The composite for electrocatalysis includes a titanium substrate and a titanium dioxide nanomesh deposited on the titanium substrate, where the titanium dioxide nanomesh is woven from titanium dioxide nanowires; the titanium dioxide nanowires include anatase-type titanium dioxide nanowires and rutile-type titanium dioxide nanowires. The mixed crystal-type titanium dioxide phase improves a catalytic activity of the composite for electrocatalysis; meanwhile, the titanium dioxide nanowires are further loaded with graphitic carbon particles to improve an overall conductivity of the composite for electrocatalysis. Therefore, the composite for electrocatalysis has a high electron mobility to achieve an improved electrocatalytic activity, which can be applied to the degradation of organic pollutants by electrocatalysis.

Method and apparatus for source-synchronous signaling

A low-power, high-performance source-synchronous chip interface which provides rapid turn-on and facilitates high signaling rates between a transmitter and a receiver located on different chips is described in various embodiments. Some embodiments of the chip interface include, among others: a segmented “fast turn-on” bias circuit to reduce power supply ringing during the rapid power-on process; current mode logic clock buffers in a clock path of the chip interface to further reduce the effect of power supply ringing; a multiplying injection-locked oscillator (MILO) clock generator to generate higher frequency clock signals from a reference clock; a digitally controlled delay line which can be inserted in the clock path to mitigate deterministic jitter caused by the MILO clock generator; and circuits for periodically re-evaluating whether it is safe to retime transmit data signals in the reference clock domain directly with the faster clock signals.

Clock and Data Recovery Having Shared Clock Generator

This disclosure provides a clock recovery circuit for a multi-lane communication system. Local clocks are recovered from the input signals using respective local CDR circuits, and associated CDR error signals are aggregated or otherwise combined. A global recovered clock for shared use by the local CDR circuits is generated at a controllable oscillation frequency as a function of a combination of the error signals from the plurality of receivers. A voltage- or current-controlled delay line can also be used to phase adjust the global recovered clock to mitigate band-limited, lane-correlated, high frequency jitter.

Clock and data recovery having shared clock generator

This disclosure provides a clock recovery circuit for a multi-lane communication system. Local clocks are recovered from the input signals using respective local CDR circuits, and associated CDR error signals are aggregated or otherwise combined. A global recovered clock for shared use by the local CDR circuits is generated at a controllable oscillation frequency as a function of a combination of the error signals from the plurality of receivers. A voltage- or current-controlled delay line can also be used to phase adjust the global recovered clock to mitigate band-limited, lane-correlated, high frequency jitter.

Methods and circuits for asymmetric distribution of channel equalization between devices

A transceiver architecture supports high-speed communication over a signal lane that extends between a high-performance integrated circuit (IC) and one or more relatively low-performance ICs employing less sophisticated transmitters and receivers. The architecture compensates for performance asymmetry between ICs communicating over a bidirectional lane by instantiating relatively complex transmit and receive equalization circuitry on the higher-performance side of the lane. Both the transmit and receive equalization filter coefficients in the higher-performance IC may be adaptively updated based upon the signal response at the receiver of the higher-performance IC.

Receiver with Clock Recovery Circuit and Adaptive Sample and Equalizer Timing

A receiver is equipped with an adaptive phase-offset controller and associated timing-calibration circuitry that together shift the timing for a data sampler and a digital equalizer. The sample and equalizer timing is shifted to a position with less residual inter-symbol interference (ISI) energy relative to the current symbol. The shifted position may be calculated using a measure of signal quality, such as a receiver bit-error rate or a comparison of filter-tap values, to optimize the timing of data recovery.

Methods and circuits for asymmetric distribution of channel equalization between devices

A transceiver architecture supports high-speed communication over a signal lane that extends between a high-performance integrated circuit (IC) and one or more relatively low-performance ICs employing less sophisticated transmitters and receivers. The architecture compensates for performance asymmetry between ICs communicating over a bidirectional lane by instantiating relatively complex transmit and receive equalization circuitry on the higher-performance side of the lane. Both the transmit and receive equalization filter coefficients in the higher-performance IC may be adaptively updated based upon the signal response at the receiver of the higher-performance IC.

Signaling with Superimposed Differential-Mode and Common-Mode Signals

A data receiver circuit (206) includes first and second interfaces (221) coupled to first and second respective transmission lines (204). The first and second respective transmission lines comprise a pair of transmission lines external to the data receiver circuit. The first and second interfaces receive a transmission signal from the pair of transmission lines. A common mode extraction circuit (228) is coupled to the first and second interfaces to extract a common-mode clock signal from the received transmission signal. A differential mode circuit (238) is coupled to the first and second interfaces to extract a differential-mode data signal from the received transmission signal. The extracted data signal has a symbol rate corresponding to a frequency of the extracted clock signal (e.g.,the symbol rate may be twice the frequency of the extracted clock signal). The differential mode circuit is synchronized to the extracted clock signal.

Edge based partial response equalization

A device implements data reception with edge-based partial response decision feedback equalization. In an example embodiment, the device implements a tap weight adapter circuit that sets the tap weights that are used for adjustment of a received data signal. The tap weight adapter circuit sets the tap weights based on previously determined data values and input from an edge analysis of the received data signal using a set of edge samplers. The edge analysis may include adjusting the sampled data signal by the tap weights determined by the tap weight adapter circuit. A clock generation circuit generates an edge clock signal to control the edge sampling performed by the set of edge samplers. The edge clock signal may be generated as a function of the signals of the edge samplers and prior data values determined by the equalizer.

Clock and Data Recovery Having Shared Clock Generator

This disclosure provides a clock recovery circuit for a multi-lane communication system. Local clocks are recovered from the input signals using respective local CDR circuits, and associated CDR error signals are aggregated or otherwise combined. A global recovered clock for shared use by the local CDR circuits is generated at a controllable oscillation frequency as a function of a combination of the error signals from the plurality of receivers. A voltage- or current-controlled delay line can also be used to phase adjust the global recovered clock to mitigate band-limited, lane-correlated, high frequency jitter. 1. (canceled)2. An apparatus , comprising:receivers, each to receive a respective data signal arriving via a respective signaling lane, each data signal transmitted in response to a common clock source and carrying a respective embedded clock, wherein each of the receivers is to generate a respective local error signal representing timing error between the respective embedded clock and timing derived from a global clock;a controllable oscillator to generate an oscillation signal in response to a first control signal; anda delay locked loop to receive the oscillation signal and to generate an output, the global clock dependent on the output, the delay locked loop to impart delay in response to a second control signal;wherein the first control signal and the second control signal are each to be generated as a function of the local error signals generated by the receivers.3. The apparatus of claim 2 , wherein the second control signal is to be generated so as to cause the imparted delay to be responsive to phase differences represented by the local error signals at a first bandwidth claim 2 , and wherein the first control signal is to be generated so as to cause the oscillation signal to have a frequency responsive to phase differences represented by the local error signals that are not offset by variation in the imparted delay claim 2 , at a second loop ...

High-accuracy detection in collaborative tracking systems

An electronic device for wirelessly tracking the position of a second electronic device is disclosed. The electronic device includes transceiver circuitry and processing circuitry. The transceiver circuitry includes a beacon generator to generate a beacon at a particular frequency and direction. An antenna array transmits the beacon, and receives at least one modulated reflected beacon from the second electronic device. The transceiver circuitry also includes a discriminator to discriminate between received modulated reflected beacons and received reflected interfering beacons. The processing circuitry couples to the transceiver circuitry and tracks the position of the second device based on the modulated reflected beacons.

METHODS AND CIRCUITS FOR ASYMMETRIC DISTRIBUTION OF CHANNEL EQUALIZATION BETWEEN DEVICES

A transceiver architecture supports high-speed communication over a signal lane that extends between a high-performance integrated circuit (IC) and one or more relatively low-performance ICs employing less sophisticated transmitters and receivers. The architecture compensates for performance asymmetry between ICs communicating over a bidirectional lane by instantiating relatively complex transmit and receive equalization circuitry on the higher-performance side of the lane. Both the transmit and receive equalization filter coefficients in the higher-performance IC may be adaptively updated based upon the signal response at the receiver of the higher-performance IC. 1a transmitter to transmit information from the first integrated circuit to the second integrated circuit over a first conductive path, the transmitter including a transmit equalizer;a receiver to receive information from the second integrated circuit over one of the first conductive path, or a second conductive path; anda circuit to generate equalization settings for the transmit equalizer responsive to inter-symbol interference affecting the transmission of the information transmitted to the first integrated circuit from the second integrated circuit.. A first integrated circuit to communicate with a second integrated circuit over at least one conductive path, the first integrated circuit comprising: The present invention relates generally to the field of communications, and more particularly to high speed electronic signaling within and between integrated circuit devices.The performance of many digital systems is limited by the interconnection bandwidth within and between integrated circuit devices (ICs). High performance communication channels between ICs suffer from many effects that degrade signals. Primary among them are frequency dependent channel loss (dispersion) and reflections from impedance discontinuities, both of which lead to inter-symbol interference (ISI). Attempts to address these ...

Receiver with clock recovery circuit and adaptive sample and equalizer timing

A receiver is equipped with an adaptive phase-offset controller and associated timing-calibration circuitry that together shift the timing for a data sampler and a digital equalizer. The sample and equalizer timing is shifted to a position with less residual inter-symbol interference (ISI) energy relative to the current symbol. The shifted position may be calculated using a measure of signal quality, such as a receiver bit-error rate or a comparison of filter-tap values, to optimize the timing of data recovery.

METHODS AND CIRCUITS FOR ASYMMETRIC DISTRIBUTION OF CHANNEL EQUALIZATION BETWEEN DEVICES

A transceiver architecture supports high-speed communication over a signal lane that extends between a high-performance integrated circuit (IC) and one or more relatively low-performance ICs employing less sophisticated transmitters and receivers. The architecture compensates for performance asymmetry between ICs communicating over a bidirectional lane by instantiating relatively complex transmit and receive equalization circuitry on the higher-performance side of the lane. Both the transmit and receive equalization filter coefficients in the higher-performance IC may be adaptively updated based upon the signal response at the receiver of the higher-performance IC. 1a transmitter to transmit information from the first integrated circuit to the second integrated circuit over a first conductive path, the transmitter including a transmit equalizer;a receiver to receive information from the second integrated circuit over one of the first conductive path, or a second conductive path; anda circuit to generate equalization settings for the transmit equalizer responsive to inter-symbol interference affecting the transmission of the information transmitted to the first integrated circuit from the second integrated circuit.. A first integrated circuit to communicate with a second integrated circuit over at least one conductive path, the first integrated circuit comprising: The present invention relates generally to the field of communications, and more particularly to high speed electronic signaling within and between integrated circuit devices.The performance of many digital systems is limited by the interconnection bandwidth within and between integrated circuit devices (ICs). High performance communication channels between ICs suffer from many effects that degrade signals. Primary among them are frequency dependent channel loss (dispersion) and reflections from impedance discontinuities, both of which lead to inter-symbol interference (ISI). Attempts to address these ...

Clock and data recovery having shared clock generator

This disclosure provides a clock recovery circuit for a multi-lane communication system. Local clocks are recovered from the input signals using respective local CDR circuits, and associated CDR error signals are aggregated or otherwise combined. A global recovered clock for shared use by the local CDR circuits is generated at a controllable oscillation frequency as a function of a combination of the error signals from the plurality of receivers. A voltage- or current-controlled delay line can also be used to phase adjust the global recovered clock to mitigate band-limited, lane-correlated, high frequency jitter.

METHODS AND CIRCUITS FOR ASYMMETRIC DISTRIBUTION OF CHANNEL EQUALIZATION BETWEEN DEVICES

A transceiver architecture supports high-speed communication over a signal lane that extends between a high-performance integrated circuit (IC) and one or more relatively low-performance ICs employing less sophisticated transmitters and receivers. The architecture compensates for performance asymmetry between ICs communicating over a bidirectional lane by instantiating relatively complex transmit and receive equalization circuitry on the higher-performance side of the lane. Both the transmit and receive equalization filter coefficients in the higher-performance IC may be adaptively updated based upon the signal response at the receiver of the higher-performance IC. 1a transmitter to transmit information from the first integrated circuit to the second integrated circuit over a first conductive path, the transmitter including a transmit equalizer;a receiver to receive information from the second integrated circuit over one of the first conductive path, or a second conductive path; anda circuit to generate equalization settings for the transmit equalizer responsive to inter-symbol interference affecting the transmission of the information transmitted to the first integrated circuit from the second integrated circuit.. A first integrated circuit to communicate with a second integrated circuit over at least one conductive path, the first integrated circuit comprising: The present invention relates generally to the field of communications, and more particularly to high speed electronic signaling within and between integrated circuit devices.The performance of many digital systems is limited by the interconnection bandwidth within and between integrated circuit devices (ICs). High performance communication channels between ICs suffer from many effects that degrade signals. Primary among them are frequency dependent channel loss (dispersion) and reflections from impedance discontinuities, both of which lead to inter-symbol interference (ISI). Attempts to address these ...

Methods and circuits for asymmetric distribution of channel equalization between devices

A transceiver architecture supports high-speed communication over a signal lane that extends between a high-performance integrated circuit (IC) and one or more relatively low-performance ICs employing less sophisticated transmitters and receivers. The architecture compensates for performance asymmetry between ICs communicating over a bidirectional lane by instantiating relatively complex transmit and receive equalization circuitry on the higher-performance side of the lane. Both the transmit and receive equalization filter coefficients in the higher-performance IC may be adaptively updated based upon the signal response at the receiver of the higher-performance IC.

Frequency responsive bus coding

A data system permits bus encoding based on frequency of the bus and the frequency of switching on the bus so as to avoid undesirable frequency conditions such as a resonant condition or interference with other electrical devices. Transmission frequencies along one or more busses are monitored and used to control the encoding process, for example, an encoding process based on data bus inversion (DBI). The use of both a measure of an absolute number of logic levels ("DBI_DC") and a measure of a number of logic level transitions relative to a prior signal ("DBI_AC") provides a measure of control that may be used to compensate for both main and predriver switching noise.

Calibration for mismatch in receiver circuitry with multiple samplers

Receiver circuitries having multiple branches, such as unrolled feedback equalizers and fractional-rate receivers, may present differences between filtering elements of different branches with common filter inputs. Embodiments include devices capable of calibration that compensates such differences. The devices may be capable of introducing front-end offsets to emphasize the mismatches, and sweep filter input values to calculate the mismatches, and introducing offsets in the branches to compensate for the mismatches. Methods for use of the calibration devices are also described.

Method and apparatus for source-synchronous signaling

A low-power, high-performance source-synchronous chip interface which provides rapid turn-on and facilitates high signaling rates between a transmitter and a receiver located on different chips is described in various embodiments. Some embodiments of the chip interface include, among others: a segmented “fast turn-on” bias circuit to reduce power supply ringing during the rapid power-on process; current mode logic clock buffers in a clock path of the chip interface to further reduce the effect of power supply ringing; a multiplying injection-locked oscillator (MILO) clock generator to generate higher frequency clock signals from a reference clock; a digitally controlled delay line which can be inserted in the clock path to mitigate deterministic jitter caused by the MILO clock generator; and circuits for periodically re-evaluating whether it is safe to retime transmit data signals in the reference clock domain directly with the faster clock signals.

Methods and Circuits for Asymmetric Distribution of Channel Equalization Between Devices

A transceiver architecture supports high-speed communication over a signal lane that extends between a high-performance integrated circuit (IC) and one or more relatively low-performance ICs employing less sophisticated transmitters and receivers. The architecture compensates for performance asymmetry between ICs communicating over a bidirectional lane by instantiating relatively complex transmit and receive equalization circuitry on the higher-performance side of the lane. Both the transmit and receive equalization filter coefficients in the higher-performance IC may be adaptively updated based upon the signal response at the receiver of the higher-performance IC.

Receiver with Clock Recovery Circuit and Adaptive Sample and Equalizer Timing

A receiver is equipped with an adaptive phase-offset controller and associated timing-calibration circuitry that together shift the timing for a data sampler and a digital equalizer. The sample and equalizer timing is shifted to a position with less residual inter-symbol interference (ISI) energy relative to the current symbol. The shifted position may be calculated using a measure of signal quality, such as a receiver bit-error rate or a comparison of filter-tap values, to optimize the timing of data recovery. 1a data input port;an edge sampler coupled to the data input port;clock recovery circuitry having a clock-recovery input port, coupled to the data input port via the edge sampler, and a clock-recovery output port;a data sampler having a data-sampler input terminal, coupled to the data input port, and a data-sampler output terminal;an equalizer coupled to the data-sampler input terminal, the equalizer having an equalizer clock terminal; andan adaptive phase-offset controller coupled between the clock-recovery output port of the clock recovery circuitry and the equalizer clock terminal, the phase-offset controller having a phase-offset control port.. A receiver comprising: The subject matter disclosed herein relates generally to the field of communications, and more particularly to high speed electronic signaling within and between integrated circuit devices.Synchronous digital systems employ clock signals to coordinate the transmission and receipt of data. For example, a transmitter might synchronize transmitted data to a clock signal and then convey the synchronized data and clock signals to a receiver. The receiver might then recover the data using the clock signal. High-performance digital transmitters often communicate data unaccompanied by a clock signal with which to synchronize the receiver. Instead, the receiver phase-aligns a locally generated receive clock signal to the incoming data and uses the phase-adjusted “recovered” clock signal to sample the ...

EDGE BASED PARTIAL RESPONSE EQUALIZATION

A method is disclosed. The method includes sampling a data signal having a voltage value at an expected edge time of the data signal. A first alpha value is generated, and a second alpha value generated in dependence upon the voltage value. The data signal is adjusted by the first alpha value to derive a first adjusted signal. The data signal is adjusted by the second alpha value to derive a second adjusted signal. The first adjusted signal is sampled to output a first data value while the second adjusted signal is sampled to output a second data value. A selection is made between the first data value and the second data value as a function of a prior received data value to determine a received data value.

Edge based partial response equalization

A method is disclosed. The method includes sampling a data signal having a voltage value at an expected edge time of the data signal. A first alpha value is generated, and a second alpha value generated in dependence upon the voltage value. The data signal is adjusted by the first alpha value to derive a first adjusted signal. The data signal is adjusted by the second alpha value to derive a second adjusted signal. The first adjusted signal is sampled to output a first data value while the second adjusted signal is sampled to output a second data value. A selection is made between the first data value and the second data value as a function of a prior received data value to determine a received data value.

METHODS AND CIRCUITS FOR REDUCING CLOCK JITTER

A communication system includes a continuous-time linear equalizer in the clock forward path. The equalizer may be adjusted to minimize clock jitter, including jitter associated with the first few clock edges after the clock signal is enabled. Reducing early-edge jitter reduces the power and circuit complexity otherwise needed to turn the system on quickly. 1a data sampler having a data input node, a data output node, and a clock node;a data path extending to the data input node;a clock path extending from a clock source to the clock node and including a linear equalizer, the linear equalizer having an equalization control port; andequalization control circuitry coupled between the data output node and the equalization control port.. An integrated circuit comprising: Embodiments of the invention relate to the distribution of timing signals (e.g. clock and strobe signals) for synchronizing sequential logic within and between integrated circuits.High-speed digital communication typically requires transmitters and receivers to be synchronized. Such synchronization can be accomplished using a shared clock signal, or the receiver can derive a clock signal from received data. In either case, the clock signal oscillates between high and low states to create carefully timed signal edges that are used to coordinate the transmitter and receiver.It is not necessary to coordinate the transmitter and receiver when no information is being conveyed between them, and clock signals consume considerable power. Clock circuitry is therefore disabled, or placed in an “idle” state, when not in use. Clock signals require time to stabilize after transitioning from the idle state. Circuits that rely on clock signals in such systems are therefore designed to ignore early clock edges until the clock signal has had an opportunity to stabilize. In high-speed, low-power systems this wait time has an unacceptable impact on performance and system complexity.depicts a source-synchronous ...

RECEIVER WITH ENHANCED ISI MITIGATION

A receiver integrated circuit is disclosed that includes a filter and a linear equalization circuit. The filter has an input to receive a signal symbols a main tap and a pre-cursor tap to reduces a pre-cursor ISI acting on the data symbols. The linear equalization circuit couples to the output and cooperates with the filter to further reduce ISI. 1. A device having a signaling pad to receive an input signal , the device comprising:a transversal filter to receive the input signal from the signaling pad and generate an intermediate signal;a circuit to equalize and sample the intermediate signal, and to thereby generate a digital output.2. The device of where the transversal filter includes at least one pre-cursor tap.3. The device of where the transversal filter is formed by at least one electrostatic discharge (ESD) structure.4. The device of where the transversal filter includes at least one post-cursor tap.5. The device of where the circuit includes a sampler circuit and a linear equalizer claim 1 , the linear equalizer coupled to the transversal filter to receive the intermediate signal claim 1 , the sampler circuit coupled to the linear equalizer to receive an output of the linear equalizer and generate the digital output therefrom.6. The device of where the circuit includes a sampling phase offset circuit claim 5 , to shift a sampling phase used by the sampler circuit to sample at a data eye point less subject to precursor intersymbol interference (ISI).7. The device of where the circuit includes a sampling phase offset circuit claim 5 , to shift a sampling phase used by the sampler circuit away from a point of maximum voltage margin to sample at a data eye point less subject to precursor intersymbol interference (ISI).8. The device of further comprising a decision feedback equalizer (DFE) circuit to adjust at least one of sampling or the intermediate signal to compensate for a previously-resolved digital symbol.9. The device of where the circuit includes a ...

Edge based partial response equalization

A method is disclosed. The method includes sampling a data signal having a voltage value at an expected edge time of the data signal. A first alpha value is generated, and a second alpha value generated in dependence upon the voltage value. The data signal is adjusted by the first alpha value to derive a first adjusted signal. The data signal is adjusted by the second alpha value to derive a second adjusted signal. The first adjusted signal is sampled to output a first data value while the second adjusted signal is sampled to output a second data value. A selection is made between the first data value and the second data value as a function of a prior received data value to determine a received data value.

CALIBRATING A RETRO-DIRECTIVE ARRAY FOR AN ASYMMETRIC WIRELESS LINK

The disclosed embodiments relate to a technique for calibrating a retro-directive array. During the calibration process, the system measures a gain gthrough a first pair of antennas in the retro-directive array. Next, the system measures a gain gthrough a second pair of antennas in the retro-directive array. The system then simultaneously measures a combined gain Gthrough the first and second pairs of antennas in the retro-directive array. If Gis less than g+gby more than a threshold value, the system calibrates a phase relationship between the first and second pairs of antennas. 1. A method for calibrating a retro-directive array , comprising:{'sub': '1', 'measuring a gain gthrough a first pair of antennas in the retro-directive array;'}{'sub': '2', 'measuring a gain gthrough a second pair of antennas in the retro-directive array;'}{'sub': '1,2', 'simultaneously measuring a combined gain Gof the first and second pairs of antennas in the retro-directive array; and'}{'sub': 1,2', '1', '2, 'if Gis less than g+gby more than a threshold value, calibrating a phase relationship between the first and second pairs of antennas.'}2. The method of claim 1 , wherein measuring the gain gthrough the first pair of antennas comprises:activating the first pair of antennas while other antennas in the retro-directive array are inactive; and{'sub': '1', 'performing a loopback measurement through the first pair of antennas to determine g.'}3. The method of claim 1 , wherein measuring the gains g claim 1 , g claim 1 , and Gcomprises measuring the gains g claim 1 , g claim 1 , and Gat more than one frequency.4. The method of claim 1 , wherein the first pair of antennas includes a first antenna and a second antenna which are coupled together through a loopback mechanism.5. The method of claim 4 ,wherein the first antenna comprises a first set of antenna elements; andwherein the second antenna comprises a second set of antenna elements.6. The method of claim 1 , wherein calibrating the ...

METHOD AND APPARATUS FOR SOURCE-SYNCHRONOUS SIGNALING

A low-power, high-performance source-synchronous chip interface which provides rapid turn-on and facilitates high signaling rates between a transmitter and a receiver located on different chips is described in various embodiments. Some embodiments of the chip interface include, among others: a segmented “fast turn-on” bias circuit to reduce power supply ringing during the rapid power-on process; current mode logic clock buffers in a clock path of the chip interface to further reduce the effect of power supply ringing; a multiplying injection-locked oscillator (MILO) clock generator to generate higher frequency clock signals from a reference clock; a digitally controlled delay line which can be inserted in the clock path to mitigate deterministic jitter caused by the MILO clock generator; and circuits for periodically re-evaluating whether it is safe to retime transmit data signals in the reference clock domain directly with the faster clock signals. 1. (canceled)2. A method of operating an integrated circuit , comprising:receiving a first timing signal from another integrated circuit;based on the first timing signal, sampling a first data signal from the another integrated circuit;transmitting a second timing signal to the another integrated circuit, the second timing signal being derived from the first timing signal; and,transmitting, with timing based on the second timing signal, a second data signal to the another integrated circuit.3. The method of claim 2 , wherein the first timing signal was generated by a multiplying injection locked oscillator (MILO).4. The method of claim 2 , further comprising:receiving a wakeup signal from the another integrated circuit.5. The method of claim 2 , further comprising:delaying the first timing signal, as received, to generate the second timing signal.6. The method of claim 5 , wherein the first timing signal is delayed by a digitally controlled delay line.7. The method of claim 2 , wherein the first data signal and the ...

METHOD AND APPARATUS FOR SOURCE-SYNCHRONOUS SIGNALING

A low-power, high-performance source-synchronous chip interface which provides rapid turn-on and facilitates high signaling rates between a transmitter and a receiver located on different chips is described in various embodiments. Some embodiments of the chip interface include, among others: a segmented “fast turn-on” bias circuit to reduce power supply ringing during the rapid power-on process; current mode logic clock buffers in a clock path of the chip interface to further reduce the effect of power supply ringing; a multiplying injection-locked oscillator (MILO) clock generator to generate higher frequency clock signals from a reference clock; a digitally controlled delay line which can be inserted in the clock path to mitigate deterministic jitter caused by the MILO clock generator; and circuits for periodically re-evaluating whether it is safe to retime transmit data signals in the reference clock domain directly with the faster clock signals. 1. (canceled)2. An integrated circuit , comprising:circuitry to produce a first data signal that has a determinate phase-alignment to a first timing reference signal;a multiplying injection-locked oscillator to produce, based on the first timing reference signal, a second timing reference signal that has an indeterminate phase relationship to the first timing reference signal;circuitry to, based on a third timing reference signal, retime the first data signal to have a determinate phase relationship to the second timing reference signal, the third timing reference signal having a determinate phase relationship to the second timing reference signal.3. The integrated circuit of claim 2 , further comprising:circuitry to transition the multiplying injection-locked oscillator from a power-off state to a power-on state.4. The integrated circuit of claim 3 , wherein the first timing reference signal is switching at a first frequency and the third timing reference signal is switching at a second frequency that is an integer ...

Phase detection in an analog clock data recovery circuit with decision feedback equalization

An embodiment of the invention relates to a method of phase detection in a receiver circuit with decision feedback equalization. Partial-equalization and full-equalization edge signals are generated. The feedback from the first tap of the decision feedback equalizer is separated from the feedback of the remaining plurality of taps. The feedback from the plurality of taps (not including the first tap) is used to generate partial-equalization edge signals, while the feedback from all the taps is used to generate full-equalization edge signals. The partial-equalization and full-equalization edge signals are utilized by phase-detection circuitry to provide highly-accurate data sampling locations for improved performance.

Methods and circuits for reducing clock jitter

A communication system includes a continuous-time linear equalizer in the clock forward path. The equalizer may be adjusted to minimize clock jitter, including jitter associated with the first few clock edges after the clock signal is enabled. Reducing early-edge jitter reduces the power and circuit complexity otherwise needed to turn the system on quickly.

Signaling with superimposed differential-mode and common-mode signals

A data receiver circuit (206) includes first and second interfaces (221) coupled to first and second respective transmission lines (204). The first and second respective transmission lines comprise a pair of transmission lines external to the data receiver circuit. The first and second interfaces receive a transmission signal from the pair of transmission lines. A common mode extraction circuit (228) is coupled to the first and second interfaces to extract a common-mode clock signal from the received transmission signal. A differential mode circuit (238) is coupled to the first and second interfaces to extract a differential-mode data signal from the received transmission signal. The extracted data signal has a symbol rate corresponding to a frequency of the extracted clock signal (e.g.,- the symbol rate may be twice the frequency of the extracted clock signal). The differential mode circuit is synchronized to the extracted clock signal.

Receiver with clock recovery circuit and adaptive sample and equalizer timing

Nanoscale magnetite-modified activated carbon fiber (ACF) composite, and preparation method and use thereof

The present disclosure belongs to the technical field of catalytic materials for heterogeneous Electro-Fenton, and provides a nanoscale magnetite-modified activated carbon fiber (ACF) composite, and a preparation method and use thereof. The nanoscale magnetite-modified activated carbon fiber (ACF) composite comprises an ACF and iron(II,III) oxide particles loaded on a surface of the ACF. The preparation method of the nanoscale magnetite-modified ACF composite comprises the steps of: immersing the ACF in an inorganic acid for acid treatment to obtain a pretreated ACF; dissolving ferrous ions and ferric ions to obtain an iron ion solution; and soaking the pretreated ACF in the iron ion solution, and conducting precipitation and aging in sequence under alkaline conditions to obtain the nanoscale magnetite-modified ACF composite. In an aspect of the invention, the nanoscale magnetite-modified ACF composite is used in oxidative degradation of an organic pollutant by heterogeneous Electro-Fenton. Suitably, the nanoscale magnetite-modified ACF composite is used as a cathode and a conductive material as an anode, in an electrolyte containing the organic pollutant, wherein air may be blown in the electrolyte.

Methods and circuits for adaptive equalization and channel characterization using live data

A communication system supports high-speed communication over a signal lane that extends between respective transmitting and receiving integrated circuit (IC) devices. One or both of the IC devices includes an equalizer to offset channel characteristics that otherwise impair speed performance. A margining circuit on the receiving IC measures a timing margin of the received signal and adjusts the equalization settings for one or both transmitters to maximize the timing margin. Another embodiment compensates for performance asymmetry between ICs communicating over a bidirectional lane by instantiating relatively complex error analysis and adaptation circuitry on the higher-performance side of the lane. The error analysis and adaptation circuitry reduces the error margin of the transmitted signal to introduce bit errors at the receiver, analyzes the bit errors to measure ISI imposed by the channel, and adjusts voltage offsets of the continuous-time signal to compensate for the ISI. In some embodiments the receiver calculates the system response for diagnostics and for computing equalization settings.

Partial response decision-feedback equalization with adaptation based on edge samples

A device (102) implements data reception with edge-based partial response decision feedback equalization. The device implements a tap weight adapter circuit (114) that sets the tap weights that are used for adjustment of a received data -signal (104). The tap weight adapter circuit (114) sets the tap weights based. on previously determined data values and input from an edge analysis of the received data signal using a set of edge samplers. The edge analysis (116) may include adjusting the sampled data signal by the tap weights determined by the tap weight adapter circuit. A clock generation circuit (220) generates an edge clock signal to control the edge sampling performed by the set of edge samplers. The edge clock signal is generated as a function of the signals of the edge samplers and prior data values determined by the equalizer.

Nanoscale magnetite-modified activated carbon fiber (ACF) composite, and preparation method and use thereof

Clock and data recovery having shared clock generator

This disclosure provides a clock recovery circuit for a multi-lane communication system. Local clocks are recovered from the input signals using respective local CDR circuits, and associated CDR error signals are aggregated or otherwise combined. A global recovered clock for shared use by the local CDR circuits is generated at a controllable oscillation frequency as a function of a combination of the error signals from the plurality of receivers. A voltage- or current-controlled delay line can also be used to phase adjust the global recovered clock to mitigate band-limited, lane-correlated, high frequency jitter.