Method and system for exchanging setup configuration protocol information in beacon frames in a WLAN

Certain aspects of a method for enabling exchange of information in a secure communication system may comprise configuring at least one 802.11 client station via authentication enablement information comprising data that specifies a time period during which configuration is allowed. The data that specifies a time period during which configuration is allowed may comprise a configuration window open field, which indicates a period when a configuration setup window is open. At least one client station may be configured via the authentication enablement information comprising recently configured data, which indicates whether at least one configurator has configured at least one other client station within the time period during which the configuration is allowed.

Method and system for transporting configuration protocol messages across a distribution system (DS) in a wireless local area network (WLAN)

Aspects of a method and system for transporting configuration messages across a DS in a WLAN are presented. Aspects of a method for enabling communication of information in a secure communication system may comprise configuring a wireless client station located in a client network based on configuration information received from a configurator. The configurator is located in a configurator network that is located external to and communicatively coupled to the client network. Aspects of a system for enabling communication of information in a secure communication system may comprise a configurator located in a configurator network that is located external to and communicatively coupled to a client network. The configurator configures a wireless client station located in the client network based on configuration information transmitted by the configurator to the wireless client station.

Method and system for transporting configuration protocol messages across a distribution system (DS) in a wireless local area network (WLAN)

Aspects of a method and system for transporting configuration messages across a DS in a WLAN are presented. Aspects of a method for enabling communication of information in a secure communication system may comprise configuring a wireless client station located in a client network based on configuration information received from a configurator. The configurator is located in a configurator network that is located external to and communicatively coupled to the client network. Aspects of a system for enabling communication of information in a secure communication system may comprise a configurator located in a configurator network that is located external to and communicatively coupled to a client network. The configurator configures a wireless client station located in the client network based on configuration information transmitted by the configurator to the wireless client station.

Method and apparatus for performing large scale consensus based clustering

A method for designing a system on a target device includes identifying a candidate cluster for a node in the system based on a gain value that quantifies utility for the candidate cluster. The candidate cluster is designated as a final cluster for the node when the candidate cluster has a highest gain value among other candidate clusters for each node in the candidate cluster.

Method and System for Transporting Configuration Protocol Messages Across a Distribution System (DS) in a Wireless Local Area Network (WLAN)

Aspects of a method and system for transporting configuration messages across a DS in a WLAN are presented. Aspects of a method for enabling communication of information in a secure communication system may comprise configuring a wireless client station located in a client network based on configuration information received from a configurator. The configurator is located in a configurator network that is located external to and communicatively coupled to the client network. Aspects of a system for enabling communication of information in a secure communication system may comprise a configurator located in a configurator network that is located external to and communicatively coupled to a client network. The configurator configures a wireless client station located in the client network based on configuration information transmitted by the configurator to the wireless client station.

Method and system for improved authentication for communications network setup

Aspects of a system for enabling secure wireless communication of information between stations in a communication system may comprise a configurator, that exchanges configuration information with a client station, in an IEEE 802.11 communication system. The exchange of configuration information may be encrypted based on information transmitted between the configurator and the client station via a communication network, and information that remains locally on the configurator and locally on the client station. Aspects of a method for enabling secure wireless communication of information between stations in a communication system may comprise exchanging configuration information between a configurator and a client station, in an IEEE 802.11 communication system. The exchanged configuration information may be encrypted based on information transmitted between the configurator and the client station via a communication network, and information that remains locally on the configurator and locally ...

Supply Voltage Control Systems And Methods For Integrated Circuits

A circuit system includes a power control circuit that generates multiple voltage identifiers. Multiple voltage regulator circuits generate multiple supply voltages based on the voltage identifiers. The supply voltages are provided to multiple integrated circuit dies. The power control circuit varies the voltage identifiers based on changes in metrics associated with the integrated circuit dies to cause the voltage regulator circuits to vary the supply voltages. Integrated circuit dies receive supply voltages from voltage regulator circuits through power delivery networks. The integrated circuit dies provide voltage sense signals that indicates the supply voltages. The voltage regulator circuits adjust the supply voltages based on the voltage sense signals to compensate for voltage drops in the power delivery networks.

Circuit Systems And Methods For Reducing Power Supply Voltage Droop

A circuit system includes a first integrated circuit die having a first group of circuits configured to perform a first set of operations. The circuit system also includes a second integrated circuit die having a second group of circuits configured to start performing a second set of operations with a delay after the first group of circuits starts performing the first set of operations to reduce power supply voltage droop. The operations performed by the first and second groups of circuits can be interleaved with a fixed or a variable delay. Logic circuits can be partitioned into the first and the second groups of circuits based on predicted switching activity of the logic circuits. Decoupling capacitors in integrated circuit dies can be coupled together to reduce droop in a supply voltage during a high current event.

Construction of a technology library for use in an electronic design automation system that converts the technology library into non-linear, gain-based models for estimating circuit delay

A system and process for constructing a technology library that is suitable for use with an electronic design automation system that converts the target technology library into a scalable cell library having non-linear, gain-based delay models for estimating circuit delay. The scalable cell library can then be used by gain-based structuring and mapping processes. The library construction process places at least six discrete cells in each logic function of a basic cell set. The library construction process also places at least five discrete cells in each logic function of an extended cell set and rules out cell sizing using internal buffer circuits. Also, for each discrete cell in the complete cell set, the variance of the capacitances between different input pins of the cell is maintained to be within 10 percent. For corresponding timing arcs of discrete sizes for a particular logic function, the present invention keeps equal the ratio of the output load to input capacitance. Also, the ...

Techniques for signal skew compensation

An integrated circuit includes a signal network and a phase detector circuit. The signal network includes an adjustable delay circuit. The adjustable delay circuit is coupled at an intersection in the signal network between branches of the signal network. The signal network generates a first signal at a first leaf node of the signal network in response to a second signal. The signal network generates a third signal at a second leaf node of the signal network in response to the second signal. The phase detector circuit compares phases of the first and third signals to generate a phase detection signal. The adjustable delay circuit adjusts a delay provided to the first signal relative to the second signal to reduce a skew between the first and third signals based on the phase detection signal indicating that the first and third signals have the skew.

Dynamically Scalable Timing and Power Models for Programmable Logic Devices

Embodiments of the present disclosure are related to dynamically adjusting a timing and/or power model for a programmable logic device. In particular, the present disclosure is directed to adjusting a timing and/or power model of the programmable logic device that operates at a voltage level that is not other than a predefined voltage defined by a voltage library. A system of the present disclosure may interpolate between voltage levels defined by the voltage libraries to generate a new voltage library for the programmable logic device. A timing and/or power model may be generated for the programmable logic device based on the new voltage library and the programmable logic device may be analyzed using the timing and/or power model at the interpolated voltage. The timing and/or power model may be used to generate a bitstream that is used to program the integrated circuit.

Method and system for distribution of configuration information among access points in a wireless local area network (WLAN) across a distribution system (DS)

Aspects of a method and system for distribution of configuration information among access points (AP) in a WLAN across a distribution system (DS) are presented. An AP, performing in a role of an AP-configurator may configure another AP, performing in a role of AP-client. The AP-configurator may distribute configurator configuration information to the AP-client. A configured AP-client may adopt a role of AP-configurator to configure a subsequent AP-client. An AP-configurator, or configured AP-client may subsequently configure a client station. The AP-configurator or configured AP-client may distribute configuration information to the client station. The configuration information may be based on previously distributed configurator configuration information. The method may enable client stations to be configured based on common configuration information that may be derived from configurator configuration information that was distributed by an AP-configurator. The client stations configured ...

Method and system for exchanging setup configuration protocol information in beacon frames in a WLAN

Certain aspects of a method for enabling exchange of information in a secure communication system may comprise configuring at least one 802.11 client station via authentication enablement information comprising data that specifies a time period during which configuration is allowed. The data that specifies a time period during which configuration is allowed may comprise a configuration window open field, which indicates a period when a configuration setup window is open. At least one client station may be configured via the authentication enablement information comprising recently configured data, which indicates whether at least one configurator has configured at least one other client station within the time period during which the configuration is allowed.

Three dimensional circuit systems and methods having memory hierarchies

A three dimensional circuit system includes a first integrated circuit die having a core logic region that has first memory circuits and logic circuits. The three dimensional circuit system includes a second integrated circuit die that has second memory circuits. The first and second integrated circuit dies are coupled together in a vertically stacked configuration. The three dimensional circuit system includes third memory circuits coupled to the first integrated circuit die. The third memory circuits reside in a plane of the first integrated circuit die. The logic circuits are coupled to access the first, second, and third memory circuits and data can move between the first, second, and third memories. The third memory circuits have a larger memory capacity and a smaller memory access bandwidth than the second memory circuits. The second memory circuits have a larger memory capacity and a smaller memory access bandwidth than the first memory circuits.

Techniques For Signal Skew Compensation

An integrated circuit includes a signal network and a phase detector circuit. The signal network includes an adjustable delay circuit. The adjustable delay circuit is coupled at an intersection in the signal network between branches of the signal network. The signal network generates a first signal at a first leaf node of the signal network in response to a second signal. The signal network generates a third signal at a second leaf node of the signal network in response to the second signal. The phase detector circuit compares phases of the first and third signals to generate a phase detection signal. The adjustable delay circuit adjusts a delay provided to the first signal relative to the second signal to reduce a skew between the first and third signals based on the phase detection signal indicating that the first and third signals have the skew. 1. An integrated circuit comprising:a signal network comprising a first adjustable delay circuit, wherein the first adjustable delay circuit is coupled at a first intersection in the signal network between branches of the signal network, wherein the signal network generates a first signal at a first leaf node of the signal network in response to a second signal, and wherein the signal network generates a third signal at a second leaf node of the signal network in response to the second signal; anda first phase detector circuit that compares phases of the first and third signals to generate a first phase detection signal, wherein the first adjustable delay circuit adjusts a delay provided to the first signal relative to the second signal to reduce a skew between the first and third signals based on the first phase detection signal indicating that the first and third signals have the skew.2. The integrated circuit of claim 1 , wherein the signal network further comprises a second adjustable delay circuit that is coupled at a second intersection in the signal network between branches of the signal network claim 1 , wherein ...

COEXISTENCE MANAGEMENT FOR COOPERATIVE TRANSCEIVING IN A SHARED SPECTRUM

A wireless interface circuit transceives packetized data between a host module and a first external device using a frequency spectrum, wherein the packetized data is formatted in accordance with a first wireless communication protocol and wherein the packetized data includes a request from the first external device to use at least a potion of the frequency spectrum for communication via a second wireless communication protocol. A coexistence management module generates a wireless interface schedule that includes a least one contention free period reserved for communication via the second wireless communication protocol, and generates schedule data, based on the wireless interface schedule, for transmission to a plurality of external devices including the first external device.

Non-linear, gain-based modeling of circuit delay for an electronic design automation system

A non-linear, gain-based modeling of circuit delay within an electronic design automation system. The present invention provides a scalable cell model for use in early logic structuring and mapping for the design of integrated circuits. The scalable cell model includes a four dimensional delay model accepting input slew and gain and providing delay and output slew. By eliminating output loading as a requirement for delay computations, the scalable model of the present invention can effectively be used to provide accurate delay information for early logic synthesis processes, e.g., that precede technology dependent optimizations where the actual load of a cell is unknown. This scalable cell model considers: the impact of transition times on delay; complex gates having different input capacitances for different input pins; the impact of limited discrete cell sizes in the technology library; and design rules, e.g., maximum capacitance and maximum transition associated with gates. A technology ...

Method and system for improved communication network setup utilizing extended terminals

Aspects of a method and system for improved communication network setup utilizing extended terminals are presented. Aspects of the method may comprise configuring a wireless Ethernet terminal functioning as a client station by a configurator via a network. The configured wireless Ethernet terminal may wirelessly receives information from a wireless station, and communicate the wirelessly received information to at least one of a plurality of wired stations via at least one of a plurality of corresponding wired interfaces. Aspects of the system may comprise a collocated device functioning as a configurator that configures a wireless Ethernet terminal functioning as a client station via a network. The configured wireless Ethernet terminal may wirelessly receives information from a wireless station, and communicate the wirelessly received information to at least one of a plurality of wired stations via at least one of a plurality of corresponding wired interfaces.

METHOD AND SYSTEM FOR IMPROVED COMMUNICATION NETWORK SETUP UTILIZING EXTENDED TERMINALS

Aspects of a method and system for improved communication network setup utilizing extended terminals are presented. Aspects of the method may comprise configuring a wireless Ethernet terminal functioning as a client station by a configurator via a network. The configured wireless Ethernet terminal may wirelessly receives information from a wireless station, and communicate the wirelessly received information to at least one of a plurality of wired stations via at least one of a plurality of corresponding wired interfaces. Aspects of the system may comprise a collocated device functioning as a configurator that configures a wireless Ethernet terminal functioning as a client station via a network. The configured wireless Ethernet terminal may wirelessly receives information from a wireless station, and communicate the wirelessly received information to at least one of a plurality of wired stations via at least one of a plurality of corresponding wired interfaces. 1. A method for communicating information , the method comprising: receiving a wireless local area network (WLAN) frame including a physical layer header field specifying at least one WLAN address and a physical layer service data unit (PSDU) field;', 'using information included in the PSDU field to determine a media access control (MAC) address of a local area network (LAN) station connected to the WET via a wired interface;', 'transcoding the physical layer header of the received WLAN frame to generate a LAN physical layer header including the MAC address of the LAN station; and', 'communicating a LAN frame based on said LAN physical layer header., 'performing, by processing circuitry integrated within a wireless Ethernet terminal (WET)2. The method according to claim 1 , comprising appending the LAN physical header to the WLAN frame.3. The method according to claim 1 , comprising associating a port at said WET corresponding to said determined network layer destination address.4. The method according to ...

High temperature CO2 capture using engineered eggshells: a route to carbon management

Applying an acid treatment to eggshells provides a sorbent with unexpectedly high CO 2 capture capacity and ability to regenerate.

Separation of carbon dioxide (CO2) from gas mixtures by calcium based reaction separation (CaRS-CO2) process

A reaction-based process has been developed for the selective removal of carbon dioxide (CO2) from a multicomponent gas mixture to provide a gaseous stream depleted in CO2 compared to the inlet CO2 concentration in the stream. The proposed process effects the separation of CO2 from a mixture of gases (such as flue gas/fuel gas) by its reaction with metal oxides (such as calcium oxide). The Calcium based Reaction Separation for CO2 (CaRS—CO2) process consists of contacting a CO2 laden gas with calcium oxide (CaO) in a reactor such that CaO captures the CO2 by the formation of calcium carbonate (CaCO3). Once “spent”, CaCO3 is regenerated by its calcination leading to the formation of fresh CaO sorbent and the evolution of a concentrated stream of CO2. The “regenerated” CaO is then recycled for the further capture of more CO2. This carbonation-calcination cycle forms the basis of the CaRS—CO2 process. This process also identifies the application of a mesoporous CaCO3 structure, developed by ...

Construction of a technology library for use in an electronic design automation system that converts the technology library into non-linear, gain-based models for estimating circuit delay

A system and process for constructing a technology library that is suitable for use with an electronic design automation system that converts the target technology library into a scalable cell library having non-linear, gain-based delay models for estimating circuit delay. The scalable cell library can then be used by gain-based structuring and mapping processes. The library construction process places at least six discrete cells in each logic function of a basic cell set. The library construction process also places at least five discrete cells in each logic function of an extended cell set and rules out cell sizing using internal buffer circuits. Also, for each discrete cell in the complete cell set, the variance of the capacitances between different input pins of the cell is maintained to be within 10 percent. For corresponding timing arcs of discrete sizes for a particular logic function, the present invention keeps equal the ratio of the output load to input capacitance. Also, the present invention constructs a technology library that has geometrically distributed sizes of cells within each logic function. Lastly, for each discrete cell within a logic cluster, the output maximum capacitance constraint is kept linearly proportional to the average input capacitance of the discrete cell. These processes likely allow a technology library to be suitable for the generation of a scalable library which can be used for integrated circuit design and fabrications.

Method and apparatus for improving efficiency of constraint solving

Techniques are presented for identifying blockable subsets. Blockable subsets can increase the efficiency by which solutions to a constraint set representation (CSR) can be found. Nodes of a blockable subset can be marked as “blocked” and learning or implication procedures, used as part of a CSR solving process, can be designed to skip nodes marked as blocked. The identification of a particular blockable subset is typically associated with certain conditions being true. If and when the conditions no longer hold, the nodes of the blockable subset need to be unblocked. One type of blockable subset can be identified during the operation of an implication engine (IE) by a technique called justified node blocking (JNB). Another type of blockable subset can be identified by a technique called pivot node learning (PNL). PNL can be applied in-between application of an IE and application of case-based learning.

CLIENT CONFIGURATION DURING TIMING WINDOW

Certain aspects of a method for enabling exchange of information in a secure communication system may comprise configuring at least one 802.11 client station via authentication enablement information comprising data that specifies a time period during which configuration is allowed. The data that specifies a time period during which configuration is allowed may comprise a configuration window open field, which indicates a period when a configuration setup window is open. At least one client station may be configured via the authentication enablement information comprising recently configured data, which indicates whether at least one configurator has configured at least one other client station within the time period during which the configuration is allowed. 1. A method comprising:transmitting a first message including information indicating that no additional client devices can be configured during a current configurator timing window;receiving, at the configurator, a second message from a client device, the second message indicating that an unintended client may have utilized the configurator for configuration.2. The method according to claim 1 , wherein the first message comprises a RECENTLY CONFIGURED STATE indication.3. The method according to claim 1 , further comprising:disallowing configuration of more than one client device during the current configurator timing window.4. The method according to claim 1 , wherein the client device and the configuration device are wireless devices.5. The method according to claim 4 , wherein the configurator comprises a wireless access point.6. The method according to claim 1 , wherein the client device expects to be configured during the current configurator timing window based on a value of a CONFIGURATION PROTOCOL DATA field included in the first message.7. The method according to claim 6 , wherein the CONFIGURATION PROTOCOL DATA field comprises a CONFIGURATION PROTOCOL OPEN WINDOW bit.8. The method according to claim 1 ...

Method and system for improved communication network setup utilizing extended terminals

Aspects of a method and system for improved communication network setup utilizing extended terminals are presented. Aspects of the method may comprise configuring a wireless Ethernet terminal functioning as a client station by a configurator via a network. The configured wireless Ethernet terminal may wirelessly receives information from a wireless station, and communicate the wirelessly received information to at least one of a plurality of wired stations via at least one of a plurality of corresponding wired interfaces. Aspects of the system may comprise a collocated device functioning as a configurator that configures a wireless Ethernet terminal functioning as a client station via a network. The configured wireless Ethernet terminal may wirelessly receives information from a wireless station, and communicate the wirelessly received information to at least one of a plurality of wired stations via at least one of a plurality of corresponding wired interfaces.

CONFIGURATOR FORCED CLIENT NETWORK REJOINING

A collocated device functioning as a configurator can use short and long button activations to enter a configuration state, open a timing window, and force client devices currently joined to a network to rejoin the network. If the collocated device functioning as a configurator is unconfigured, a short (or long) button activation can initiate a configuration sequence. A short button activation on that same collocated device, once configured, can cause the device to open a configurator timing window, during which one or more devices can be provided the information necessary to securely communicate on a network. A long (or short) button activation can be used to force all currently connected client devices, or rejoin the network using a new Service Set Identifier (SSID) or passphrase. 1. A configurator station comprising:a configuration processor;persistent memory coupled to the configuration processor and configured to store configuration information pertaining to previously configured client stations;a button capable of being activated, wherein a time duration for which the button is activated corresponds to a first-duration button activation or a second-duration button activation;the configuration processor configured to open a configurator timing window in response to the first-duration button activation; andthe configuration processor configured to release, from the persistent memory, the configuration information pertaining to previously configured client stations in response to the second-duration button activation.2. The configurator station of claim 1 , wherein the configuration processor is further configured to generate either claim 1 , or both of claim 1 , a new Service Set Identifier (SSID) and a new passphrase in response to the second duration button activation.3. The configurator station of claim 1 , wherein:the first-duration button activation corresponds to one of a short button activation and a long button activation; andthe second-duration button ...

Method and apparatus for solving bit-slice operators

The following techniques for word-level networks are presented: constraints solving, case-based learning and bit-slice solving. Generation of a word-level network to model a constraints problem is presented. The networks utilized have assigned, to each node, a range of permissible values. Constraints are solved using an implication process that explores the deductive consequences of the assigned range values. The implication process may include the following techniques: forward or backward implication and case-based learning. Case-based learning includes recursive or global learning. As part of a constraint-solving process, a random variable is limited to a single value. The limitation may be performed by iterative relaxation. An implication process is then performed. If a conflict results, the value causing the conflict is removed from the random variable by range splitting, and backtracking is performed by assigning another value to the random variable. A procedure is provided for efficiently ...

Coexistence management for cooperative transceiving in a shared spectrum

A wireless interface circuit transceives packetized data between a host module and a first external device using a frequency spectrum, wherein the packetized data is formatted in accordance with a first wireless communication protocol and wherein the packetized data includes an indication that the first external device is configured to use at least a portion of the frequency spectrum for communication via a second wireless communication protocol. A coexistence management module generates a wireless interface schedule that includes a least one contention free period reserved for communication via the second wireless communication protocol, and generates schedule data, based on the wireless interface schedule, for transmission to a plurality of external devices including the first external device.

COEXISTENCE MANAGEMENT FOR COOPERATIVE TRANSCEIVING IN A SHARED SPECTRUM

A wireless interface circuit transceives packetized data between a host module and a first external device using a frequency spectrum, wherein the packetized data is formatted in accordance with a first wireless communication protocol and wherein the packetized data includes an indication that the first external device is configured to use at least a portion of the frequency spectrum for communication via a second wireless communication protocol. A coexistence management module generates a wireless interface schedule that includes a least one contention free period reserved for communication via the second wireless communication protocol, and generates schedule data, based on the wireless interface schedule, for transmission to a plurality of external devices including the first external device.

Evaluation of a technology library for use in an electronic design automation system that converts the technology library into non-linear, gain-based models for estimating circuit delay

An evaluation system for evaluating the suitability of a target technology library for use with an electronic design automation system that converts the target technology library into a scalable library having non-linear, gain-based delay models for estimating circuit delay. After a library analysis process executes, an internal scalable library is generated having a scalable cell model for each functional cell class of the target technology library. Internal characteristics of the scalable library are analyzed to determine whether or not the target technology library is suitable for generating a suitable scalable library. Suitable scalable libraries are used for gain-based structuring and mapping processes. The library evaluation processes uses several metrics to determine the suitability the target technology library. The first metric is the number of sizes metric and the second metric is the size consistency metric. The number of sizes metric is computed with respect to subsets (e.g.

Method and system for transporting configuration protocol messages across a distribution system (DS) in a wireless local area network (WLAN)

Aspects of a method and system for transporting configuration messages across a DS in a WLAN are presented. Aspects of a method for enabling communication of information in a secure communication system may comprise configuring a wireless client station located in a client network based on configuration information received from a configurator. The configurator is located in a configurator network that is located external to and communicatively coupled to the client network. Aspects of a system for enabling communication of information in a secure communication system may comprise a configurator located in a configurator network that is located external to and communicatively coupled to a client network. The configurator configures a wireless client station located in the client network based on configuration information transmitted by the configurator to the wireless client station.

Three Dimensional Programmable Logic Circuit Systems And Methods

A three dimensional circuit system includes first and second integrated circuit (IC) dies. The first IC die includes programmable logic circuits arranged in sectors and first programmable interconnection circuits having first router circuits. The second IC die includes non-programmable circuits arranged in regions and second programmable interconnection circuits having second router circuits. Each of the regions in the second IC die is vertically aligned with at least one of the sectors in the first IC die. Each of the second router circuits is coupled to one of the first router circuits through a vertical die-to-die connection. The first and second programmable interconnection circuits are programmable to route signals between the programmable logic circuits and the non-programmable circuits through the first and second router circuits. The circuit system may include additional IC dies. The first and second IC dies and any additional IC dies are coupled in a vertically stacked configuration. 1. A three dimensional circuit system comprising:a first integrated circuit die comprising programmable logic circuits that are arranged in sectors in the first integrated circuit die and first programmable interconnection circuits comprising first router circuits; anda second integrated circuit die comprising non-programmable circuits that are arranged in regions in the second integrated circuit die and second programmable interconnection circuits comprising second router circuits, wherein each of the regions is vertically aligned with at least one of the sectors, wherein each of the second router circuits is coupled to one of the first router circuits through a vertical die-to-die connection, wherein the first and second programmable interconnection circuits are programmable to route signals between the programmable logic circuits and the non-programmable circuits through the first and second router circuits, and wherein the first and second integrated circuit dies are ...

Method and system for improved communication network setup utilizing extended terminals

Aspects of a method and system for improved communication network setup utilizing extended terminals are presented. Aspects of the method may comprise configuring a wireless Ethernet terminal functioning as a client station by a configurator via a network. The configured wireless Ethernet terminal may wirelessly receives information from a wireless station, and communicate the wirelessly received information to at least one of a plurality of wired stations via at least one of a plurality of corresponding wired interfaces. Aspects of the system may comprise a collocated device functioning as a configurator that configures a wireless Ethernet terminal functioning as a client station via a network. The configured wireless Ethernet terminal may wirelessly receives information from a wireless station, and communicate the wirelessly received information to at least one of a plurality of wired stations via at least one of a plurality of corresponding wired interfaces.

Non-linear, gain-based modeling of circuit delay for an electronic design automation system

A non-linear, gain-based modeling of circuit delay within an electronic design automation system. The present invention provides a scalable cell model for use in early logic structuring and mapping for the design of integrated circuits. The scalable cell model includes a four dimensional delay model accepting input slew and gain and providing delay and output slew. By eliminating output loading as a requirement for delay computations, the scalable model of the present invention can effectively be used to provide accurate delay information for early logic synthesis processes, e.g., that precede technology dependent optimizations where the actual load of a cell is unknown. This scalable cell model considers: the impact of transition times on delay; complex gates having different input capacitances for different input pins; the impact of limited discrete cell sizes in the technology library; and design rules, e.g., maximum capacitance and maximum transition associated with gates. A technology ...

Techniques for signal skew compensation

An integrated circuit includes a signal network and a phase detector circuit. The signal network includes an adjustable delay circuit. The adjustable delay circuit is coupled at an intersection in the signal network between branches of the signal network. The signal network generates a first signal at a first leaf node of the signal network in response to a second signal. The signal network generates a third signal at a second leaf node of the signal network in response to the second signal. The phase detector circuit compares phases of the first and third signals to generate a phase detection signal. The adjustable delay circuit adjusts a delay provided to the first signal relative to the second signal to reduce a skew between the first and third signals based on the phase detection signal indicating that the first and third signals have the skew.

Method and system for improved communication network setup

Aspects of a method and system for improved communication network setup may comprise receiving authentication enablement information from a configurator station comprising indication of a current state of a configurator timing window. In response to input at a client station to communicate authentication response information to the configurator station, receiving at the client station, configuration information and/or status information resulting from input at the client station. Other aspects of the invention may comprise responding to input at a configurator station to transmit authentication enablement information comprising indication of a current state of a configurator timing window, receiving authentication response information from the client station based on the transmitted authentication enablement information, and transmitting to the client station configuration information and/or status information from the configurator station based on the received authentication response information ...

Method and System for Improved Communication Network Setup Utilizing Extended Terminals

Aspects of a method and system for improved communication network setup utilizing extended terminals are presented. Aspects of the method may comprise configuring a wireless Ethernet terminal functioning as a client station by a configurator via a network. The configured wireless Ethernet terminal may wirelessly receives information from a wireless station, and communicate the wirelessly received information to at least one of a plurality of wired stations via at least one of a plurality of corresponding wired interfaces. Aspects of the system may comprise a collocated device functioning as a configurator that configures a wireless Ethernet terminal functioning as a client station via a network. The configured wireless Ethernet terminal may wirelessly receives information from a wireless station, and communicate the wirelessly received information to at least one of a plurality of wired stations via at least one of a plurality of corresponding wired interfaces.

Method and apparatus for case-based learning

The following techniques for word-level networks are presented: constraints solving, case-based learning and bit-slice solving. Generation of a word-level network to model a constraints problem is presented. The networks utilized have assigned, to each node, a range of permissible values. Constraints are solved using an implication process that explores the deductive consequences of the assigned range values. The implication process may include the following techniques: forward or backward implication and case-based learning. Case-based learning includes recursive or global learning. As part of a constraint-solving process, a random variable is limited to a single value. The limitation may be performed by iterative relaxation. An implication process is then performed. If a conflict results, the value causing the conflict is removed from the random variable by range splitting, and backtracking is performed by assigning another value to the random variable. A procedure is provided for efficiently ...

Power-save for wireless networks

Embodiments of the present invention enable power-save methods for wireless networks. Embodiments of the present invention are compliant with the IEEE 802.11 protocol. Further, embodiments of the present invention are readily inter-operable with other third party implementations.

Method and system for improved authentication for communications network setup

Aspects of a system for enabling secure wireless communication of information between stations in a communication system may comprise a configurator, that exchanges configuration information with a client station, in an IEEE 802.11 communication system. The exchange of configuration information may be encrypted based on information transmitted between the configurator and the client station via a communication network, and information that remains locally on the configurator and locally on the client station. Aspects of a method for enabling secure wireless communication of information between stations in a communication system may comprise exchanging configuration information between a configurator and a client station, in an IEEE 802.11 communication system. The exchanged configuration information may be encrypted based on information transmitted between the configurator and the client station via a communication network, and information that remains locally on the configurator and locally ...

Method and system for exchanging setup configuration protocol information in beacon frames in a WLAN

Certain aspects of a method for enabling exchange of information in a secure communication system may comprise configuring at least one 802.11 client station via authentication enablement information comprising data that specifies a time period during which configuration is allowed. The data that specifies a time period during which configuration is allowed may comprise a configuration window open field, which indicates a period when a configuration setup window is open. At least one client station may be configured via the authentication enablement information comprising recently configured data, which indicates whether at least one configurator has configured at least one other client station within the time period during which the configuration is allowed.

Method and System for Exchanging Setup Configuration Protocol Information in Beacon Frames in a WLAN

Certain aspects of a method for enabling exchange of information in a secure communication system may comprise configuring at least one 802.11 client station via authentication enablement information comprising data that specifies a time period during which configuration is allowed. The data that specifies a time period during which configuration is allowed may comprise a configuration window open field, which indicates a period when a configuration setup window is open. At least one client station may be configured via the authentication enablement information comprising recently configured data, which indicates whether at least one configurator has configured at least one other client station within the time period during which the configuration is allowed.

Configurator forced client network rejoining

A collocated device functioning as a configurator can use short and long button activations to enter a configuration state, open a timing window, and force client devices currently joined to a network to rejoin the network. If the collocated device functioning as a configurator is unconfigured, a short (or long) button activation can initiate a configuration sequence. A short button activation on that same collocated device, once configured, can cause the device to open a configurator timing window, during which one or more devices can be provided the information necessary to securely communicate on a network. A long (or short) button activation can be used to force all currently connected client devices, or rejoin the network using a new Service Set Identifier (SSID) or passphrase.

Method and system for improved communication network setup

Aspects of a method and system for improved communication network setup may comprise receiving authentication enablement information from a configurator station comprising indication of a current state of a configurator timing window. In response to input at a client station to communicate authentication response information to the configurator station, receiving at the client station, configuration information and/or status information resulting from input at the client station. Other aspects of the invention may comprise responding to input at a configurator station to transmit authentication enablement information comprising indication of a current state of a configurator timing window, receiving authentication response information from the client station based on the transmitted authentication enablement information, and transmitting to the client station configuration information and/or status information from the configurator station based on the received authentication response information ...

Three dimensional programmable logic circuit systems and methods

A three dimensional circuit system includes first and second integrated circuit (IC) dies. The first IC die includes programmable logic circuits arranged in sectors and first programmable interconnection circuits having first router circuits. The second IC die includes non-programmable circuits arranged in regions and second programmable interconnection circuits having second router circuits. Each of the regions in the second IC die is vertically aligned with at least one of the sectors in the first IC die. Each of the second router circuits is coupled to one of the first router circuits through a vertical die-to-die connection. The first and second programmable interconnection circuits are programmable to route signals between the programmable logic circuits and the non-programmable circuits through the first and second router circuits. The circuit system may include additional IC dies. The first and second IC dies and any additional IC dies are coupled in a vertically stacked configuration ...

Method and system to transmit code to a system on a chip (SOC)

A method and system to transmit code to a System on Chip (SOC) from a host processor using a host-side driver is provided herein. The SOC and host processor are coupled by a bus. The host driver receives an overlay from an application layer and stores the overlay. The host driver receives an IOCTL to be transmitted to the SOC. The host driver determines whether an input/output control (IOCTL) value of the IOCTL to be transmitted to the SOC corresponds to an IOCTL value in one of the stored overlays. The host driver transmits an overlay to the SOC if the IOCTL value of the IOCTL to be transmitted is equal to at least one IOCTL value in the overlay. The host driver then transmits the IOCTL to the SOC.

Three Dimensional Circuit Systems And Methods Having Memory Hierarchies

A three dimensional circuit system includes a first integrated circuit die having a core logic region that has first memory circuits and logic circuits. The three dimensional circuit system includes a second integrated circuit die that has second memory circuits. The first and second integrated circuit dies are coupled together in a vertically stacked configuration. The three dimensional circuit system includes third memory circuits coupled to the first integrated circuit die. The third memory circuits reside in a plane of the first integrated circuit die. The logic circuits are coupled to access the first, second, and third memory circuits and data can move between the first, second, and third memories. The third memory circuits have a larger memory capacity and a smaller memory access bandwidth than the second memory circuits. The second memory circuits have a larger memory capacity and a smaller memory access bandwidth than the first memory circuits.

Method and apparatus for improving efficiency of constraint solving

Techniques are presented for identifying blockable subsets. Blockable subsets can increase the efficiency by which solutions to a constraint set representation (CSR) can be found. Nodes of a blockable subset can be marked as “blocked” and learning or implication procedures, used as part of a CSR solving process, can be designed to skip nodes marked as blocked. The identification of a particular blockable subset is typically associated with certain conditions being true. If and when the conditions no longer hold, the nodes of the blockable subset need to be unblocked. One type of blockable subset can be identified during the operation of an implication engine (IE) by a technique called justified node blocking (JNB). Another type of blockable subset can be identified by a technique called pivot node learning (PNL). PNL can be applied in-between application of an IE and application of case-based learning.

Method and system for distribution of configuration information among access points in a wireless local area network (WLAN) across a distribution system (DS)

Aspects of a method and system for distribution of configuration information among access points (AP) in a WLAN across a distribution system (DS) are presented. An AP, performing in a role of an AP-configurator may configure another AP, performing in a role of AP-client. The AP-configurator may distribute configurator configuration information to the AP-client. A configured AP-client may adopt a role of AP-configurator to configure a subsequent AP-client. An AP-configurator, or configured AP-client may subsequently configure a client station. The AP-configurator or configured AP-client may distribute configuration information to the client station. The configuration information may be based on previously distributed configurator configuration information. The method may enable client stations to be configured based on common configuration information that may be derived from configurator configuration information that was distributed by an AP-configurator. The client stations configured ...

Method and System for Improved Communication Network Setup

Aspects of a method and system for improved communication network setup may comprise receiving authentication enablement information from a configurator station comprising indication of a current state of a configurator timing window. In response to input at a client station to communicate authentication response information to the configurator station, receiving at the client station, configuration information and/or status information resulting from input at the client station. Other aspects of the invention may comprise responding to input at a configurator station to transmit authentication enablement information comprising indication of a current state of a configurator timing window, receiving authentication response information from the client station based on the transmitted authentication enablement information, and transmitting to the client station configuration information and/or status information from the configurator station based on the received authentication response information ...

Coexistence management for cooperative transceiving in a shared spectrum

A wireless interface circuit transceives packetized data between a host module and a first external device using a frequency spectrum, wherein the packetized data is formatted in accordance with a first wireless communication protocol and wherein the packetized data includes a request from the first external device to use at least a potion of the frequency spectrum for communication via a second wireless communication protocol. A coexistence management module generates a wireless interface schedule that includes a least one contention free period reserved for communication via the second wireless communication protocol, and generates schedule data, based on the wireless interface schedule, for transmission to a plurality of external devices including the first external device.

Method and system for improved communication network setup utilizing extended terminals

Aspects of a method and system for improved communication network setup utilizing extended terminals are presented. Aspects of the method may comprise configuring a wireless Ethernet terminal functioning as a client station by a configurator via a network. The configured wireless Ethernet terminal may wirelessly receives information from a wireless station, and communicate the wirelessly received information to at least one of a plurality of wired stations via at least one of a plurality of corresponding wired interfaces. Aspects of the system may comprise a collocated device functioning as a configurator that configures a wireless Ethernet terminal functioning as a client station via a network. The configured wireless Ethernet terminal may wirelessly receives information from a wireless station, and communicate the wirelessly received information to at least one of a plurality of wired stations via at least one of a plurality of corresponding wired interfaces.

Voltage Regulator Circuit Systems And Methods

A circuit system includes a first voltage regulator circuit that generates a first supply voltage for an integrated circuit die based on a first control signal. The first voltage regulator circuit generates a first feedback signal based on the first supply voltage. The circuit system also includes a second voltage regulator circuit that generates a second supply voltage for an integrated circuit die based on a second control signal. The second voltage regulator circuit generates a second feedback signal based on the second supply voltage. The circuit system also includes a third voltage regulator circuit that generates the first control signal based on the first feedback signal and the second control signal based on the second feedback signal. The circuit system may include fully integrated, on-board, and on-package voltage regulator circuits.

HYPER-CONCURRENT MULTI-SCENARIO OPTIMIZATION

Some embodiments of the present invention provide techniques and systems for performing aggressive and dynamic scenario reduction during different phases of optimization, e.g., during delay, area, leakage and DRC (design rule check) optimization. Specifically, essential scenarios at gates and timing end-points can be identified and then used during the dynamic scenario reduction process. In some embodiments, margin values associated with various constraints can be used to determine the set of essential scenarios to account for constrained objects that are near critical in addition to the constrained objects that are the worst violators. In some embodiments, at any point during the optimization process, only the set of essential scenarios are kept active, thereby substantially reducing runtime and memory requirements without compromising on the quality of results. 1. A method for optimizing a circuit design over a set of scenarios , the method comprising:determining one or more margin values for each gate in a set of gates in each scenario in the set of scenarios, wherein a margin value indicates an amount by which a parameter can be changed in a scenario without violating a design requirement or affecting a slack value at a timing end-point;using the margin values to determine a set of essential scenarios for each gate in the set of gates; andusing one or more computers to optimize the circuit design, wherein if a gate is modified during optimization, circuit information is updated in at least the set of essential scenarios associated with the gate.2. The method of claim 1 , wherein the margin values include a timing margin for an output pin of a gate in a scenario which indicates an amount of timing degradation at the output pin of the gate in the scenario which is unobservable at a timing end-point in a path-group.3. The method of claim 1 , wherein the margin values include a leakage margin for a gate in a scenario which indicates how much the gate's leakage power ...

Process for the conversion of mixed lower alkanes to aromatic hydrocarbons

A process for the conversion of mixed lower alkanes into aromatics which comprises first reacting a mixed lower alkane feed comprising at least propane and ethane in the presence of an aromatization catalyst under reaction conditions which maximize the conversion of propane into first stage aromatic reaction products, separating ethane from the first stage aromatic reaction products, reacting ethane in the presence of an aromatization catalyst under reaction conditions which maximize the conversion of ethane into second stage aromatic reaction products, and optionally separating ethane from the second stage aromatic reaction products.

PROCESS FOR THE CONVERSION OF LOWER ALKANES TO AROMATIC HYDROCARBONS

The present invention provides a process for producing aromatic hydrocarbons which comprises: (a) alternately contacting a lower alkane feed with an aromatization catalyst under aromatization reaction conditions in a reactor for a short period of time, preferably 30 minutes or less, to produce aromatic reaction products and then contacting the aromatization catalyst with a hydrogen-containing gas at elevated temperature for a short period of time, preferably 10 minutes or less, (b) repeating the cycle of step (a) at least one time, (c) regenerating the aromatization catalyst by contacting it with an oxygen-containing gas at elevated temperature and (d) repeating steps (a) through (c) at least one time. 1. A process for producing aromatic hydrocarbons which comprises:(a) alternately contacting a lower alkane feed with an aromatization catalyst under aromatization reaction conditions in a reactor for a period of time of 30 minutes or less, to produce aromatic reaction products and then contacting the aromatization catalyst with a hydrogen-containing gas at elevated temperature for a period of time of 30 minutes or less,(b) repeating the cycle of step (a) at least one time,(c) regenerating the aromatization catalyst by contacting it with an oxygen-containing gas at elevated temperature,(d) optionally subjecting the regenerated aromatization catalyst to a metal redispersal treatment,(e) optionally reducing the regenerated aromatization catalyst, preferably with hydrogen-containing gas,(f) optionally sulfiding the catalyst, and(g) repeating steps (a) through (f) at least one time.2. The process of wherein the process is carried out in at least three reactors arranged in parallel and at least one reactor is operated according to step (c) and at least two reactors are operated according to step (a) and in at least one of the at least two reactors operated according to step (a) the aromatization catalyst is contacted with the lower alkane feed and in at least one of the at ...

Process for the regeneration of hydrocarbon conversion catalysts

The present invention provides a process for hydrocarbon conversion, especially for producing aromatic hydrocarbons, which comprises: (a) alternately contacting a hydrocarbon feed, especially a lower alkane feed, with a hydrocarbon conversion catalyst, especially an aromatization catalyst, under hydrocarbon conversion, especially aromatization reaction conditions, in a reactor for a short period of time, preferably 30 minutes or less, to produce reaction products and then contacting the catalyst with hydrogen-containing gas at elevated temperature for a short period of time, preferably 10 minutes or less, (b) repeating the cycle of step (a) at least one time, (c) regenerating the catalyst by contacting it with an oxygen-containing gas at elevated temperature and (d) repeating steps (a) through (c) at least one time.

SEPARATION OF CARBON DIOXIDE (CO2) FROM GAS MIXTURES BY CALCIUM BASED REACTION SEPARATION (CaRS-CO2) PROCESS

A reaction-based process developed for the selective removal of CO2 from a multicomponent gas mixture to provide a gaseous stream depleted in CO2 compared to the inlet CO2 concentration. The proposed process effects the separation of CO2 from a mixture of gases by its reaction with metal oxides. The Calcium based Reaction Separation for CO2 (CaRS-CO2) process consists of contacting CO2 laden gas with CaO in a reactor such that CaO captures CO2 by the formation of CaCO3. CaCO3 is regenerated by calcination leading to the formation of fresh CaO sorbent and the evolution of a concentrated stream of CO2. The “regenerated” CaO is then recycled for the further capture of CO2. This carbonation-calcination cycle forms the basis of the CaRS-CO2 process. This process also may use a mesoporous CaCO3 structure that attains >90% conversion over multiple carbonation and calcination cycles. 1. A facility separating carbon dioxide and sulfur dioxide from a flow of gas comprising carbon dioxide and sulfur dioxide , comprising:a gas-solid contact reactor receiving said flow of gas;a sorbent within said gas-solid reactor, comprising a metal oxide, said sorbent reacting with said carbon dioxide and said sulfur dioxide so as to convert at least a portion of said sorbent to a metal carbonate and at least a portion of said sorbent to a metal sulfate; anda calcinator, said calcinator receiving said at least a portion of said metal carbonate, said calcinatory calcining said metal carbonate to form said metal oxide and carbon dioxide,wherein said sorbent is replenished in said gas-solid reactor with said metal oxide formed in said calcinatory.2. The facility of claim 1 , further comprising a cyclone claim 1 , said cyclone separating said metal carbonate from said flow of gas.3. The facility of claim 1 , wherein said gas-solid reactor is operated at between about 600° to about 650° Celsius to facilitate the reaction between said carbon dioxide and said sulfur dioxide with said sorbent.4. The ...

PROCESS FOR THE CONVERSION OF PROPANE AND BUTANE TO AROMATIC HYDROCARBONS

A process for the conversion of propane and/or butane into aromatics which comprises first reacting a propane and/or butane feed in the presence of an aromatization catalyst under reaction conditions which maximize the conversion of propane and/or butane into first stage aromatic reaction products, separating ethane produced in the first stage reaction from the first stage aromatic reaction products, reacting ethane in the presence of an aromatization catalyst under reaction conditions which maximize the conversion of ethane into second stage aromatic reaction products, and optionally separating ethane from the second stage aromatic reaction products. 1. A process for the conversion of butane and/or propane into aromatics which comprises first reacting a butane and/or propane feed in the presence of an aromatization catalyst under first stage reaction conditions which maximize the conversion of propane and/or butane into first stage aromatic reaction products , separating ethane produced in the first stage aromatic reaction from the first aromatic reaction products , reacting the ethane in presence of an aromatization catalyst under second stage reaction conditions which maximize the conversion of ethane into second stage aromatic reaction products , and optionally separating ethane from the second stage aromatic reaction products.2. The process of wherein the aromatization reaction is carried out at a temperature of from 400 to 700° C.3. The process of wherein the first stage reaction conditions comprise a temperature of from 400 to 650° C.4. The process of wherein the second stage reaction conditions comprise a temperature of from 450 to 680° C.5. The process of wherein the first stage reaction products are produced in at least two reactors aligned in parallel.6. The process of wherein the second stage reaction products are produced in at least two reactors aligned in parallel.7. The process of wherein fuel gas is also produced in either or both of the first and ...

SEQUENTIAL SIZING IN PHYSICAL SYNTHESIS

Techniques and systems for optimizing a circuit design are described. In some embodiments, a sequential cell is selected for optimization. Next, the system iterates through a set of candidate sequential cells that are functionally equivalent to the sequential cell that is being optimized. The system evaluates the global timing impact of each candidate sequential cell in a highly efficient manner. For each candidate sequential cell that is evaluated, a non-timing metric and a timing metric for a candidate sequential cell are compared with the corresponding non-timing metric and timing metric for the current best sequential cell. If a candidate sequential cell improves the timing metric, or maintains the timing metric and has better non-timing metric(s), then the candidate sequential cell is stored as the current best sequential cell. Once the process completes, the current best sequential cell is the optimized cell size for the sequential cell. 1. A method for optimizing a circuit design , the method comprising:determining a set of delays corresponding to a set of pins of a candidate sequential cell that is being considered as a replacement for a sequential cell in the circuit design, wherein each delay in the set of delays includes a transition-induced delay component that is computed using a transition-effect coefficient;computing a timing metric based on the set of delays, and a non-timing metric based on one or more non-timing parameters of the candidate cell; anddetermining that replacing the sequential cell with the candidate sequential cell improves the circuit design if the timing metric improves, or the non-timing metric improves without degrading the timing metric.2. The method of claim 1 , wherein the non-timing metric is based on at least one of: an area of the candidate cell and a leakage power of the candidate cell.3. The method of claim 1 , wherein said computing the timing metric includes:determining a set of adjusted delays based on the set of delays ...

PROGRESSIVE CIRCUIT EVALUATION FOR CIRCUIT OPTIMIZATION

Systems and techniques for optimizing a circuit design are described. Some embodiments reduce the number of gates in the library (e.g., by dynamically pruning the library) which are considered for optimization. Some embodiments create a linear delay model, and use the linear delay model instead of a non-linear delay model to substantially reduce the amount of computation required to check whether or not a particular replacement gate improves one or more metrics of the circuit design. Some embodiments determine an order for processing the gates in the library or for processing input pins of a gate to facilitate early rejection of a candidate gate in the library of gates. In some embodiments, the evaluation of the impact of a candidate gate transformation is done progressively and level-by-level only up to the point where the gate transformation degrades one or more metrics. 1. A method for optimizing a circuit design , the method comprising:evaluating, by computer, a first candidate gate from a library of gates as a replacement for a gate that is being optimized, wherein said evaluating involves computing one or more timing metrics based on the first candidate gate;responsive to rejecting the first candidate gate based on said evaluating, storing one or more parameter values of the first candidate gate;determining whether a second candidate gate from the library of gates degrades the one or more timing metrics by comparing one or more corresponding parameter values of the second candidate gate with the one or more stored parameter values; andrejecting the second candidate gate based on said determining.2. The method of claim 1 , wherein said determining does not involve computing the one or more timing metrics for the second candidate gate.3. The method of claim 1 , wherein the one or more parameter values includes an input capacitance of the first candidate gate claim 1 , and wherein said rejecting involves rejecting the second candidate gate if an input capacitance ...

DELTA-SLACK PROPAGATION FOR CIRCUIT OPTIMIZATION

Systems and techniques for optimizing a circuit design are described. When a selected gate is transformed during optimization, it causes a slack value at a pin of the transformed gate to change. The change in the slack value, called the delta-slack, is then propagated through a transitive fanin cone and a transitive fanout cone of the transformed gate to compute the new slack values at all the affected pins of the design. Some embodiments update slack values without propagating arrival and required times, and also without repeatedly evaluating timing arcs to compute gate delays. The updated slack values can be used to compute timing metrics. The timing metrics can be used to decide whether or not to commit the gate transformation to the circuit design. 1. A method for updating slack values in a circuit design , the method comprising:transforming a gate in a circuit design;determining a change in a slack value at a pin of the transformed gate; andupdating, by computer, the slack values in the circuit design by propagating the change in the slack value through a transitive fanin cone and a transitive fanout cone of the transformed gate.2. The method of claim 1 , wherein said propagating includes propagating a change in a slack value from a branch point to a set of points by applying the change in the slack value at the branch point to a slack value at each point in the set of points.3. The method of claim 1 , wherein said propagating includes propagating slack values from a set of points to a merge point by:selecting a dominant slack value from a set of slack values at the set of points;propagating the dominant slack value to the merge point; andcomputing a change in slack value at the merge point for further propagation.4. The method of claim 1 , wherein said propagating includes propagating slack values from a set of input points to a set of output points by:selecting a dominant slack value from a set of slack values at the set of input points;propagating the ...

MODELING TRANSITION EFFECTS FOR CIRCUIT OPTIMIZATION

Systems and techniques are described for determining a transition-effect model for a timing arc of a library cell. A transition-effect model can be determined for each library cell that is used during an optimization process. The transition-effect models enable an optimization system to estimate the impact of a change in the transition at an output of a driver gate on the delays of downstream gates without requiring to propagate the change in the transition to the downstream gates. Once determined, the transition-effect models can be used to compute one or more transition-induced penalties during circuit optimization. An optimization system can then use the one or more transition-induced penalties to determine whether or not to accept an optimizing transformation, or to discretize a solution obtained from a numerical solver. 1. A method for determining a transition-effect delay model for a timing arc of a library cell , the method comprising:receiving a discretized delay model for the timing arc of the library cell, wherein the discretized delay model is capable of being represented by a set of points in a multi-dimensional space, the multi-dimensional space including an output loading dimension, an input transition dimension, an output delay dimension, and an output transition dimension; anddetermining, by computer, a set of transition-effect coefficients for the timing arc of the library cell based on the discretized delay model, wherein each transition-effect coefficient represents a linear relationship between a change in output delay and a change in input transition for a corresponding output load value from a set of output load values.2. The method of claim 1 , wherein each transition-effect coefficient corresponds to a slope in a plot of output delay versus input transition.3. The method of claim 2 , wherein the slope is computed at a nominal input transition value or at a nominal output delay value.4. The method of claim 1 , wherein a transition-effect ...

EFFICIENT TIMING CALCULATIONS IN NUMERICAL SEQUENTIAL CELL SIZING AND INCREMENTAL SLACK MARGIN PROPAGATION

Techniques and systems are described for improving the efficiency of timing calculations in numerical sequential cell sizing and for improving the efficiency of incremental slack margin propagation. Some embodiments cache timing-related information associated with a source driver that drives an input of a sequential cell that is being sized, and/or timing-related information for each output of the sequential cell that is being sized. The cached timing-related information for the source driver can be reused when sizing a different sequential cell. The cached timing-related information for the outputs of the sequential cell can be reused when evaluating alternatives for replacing the sequential cell. Some embodiments incrementally propagate slack margins in a lazy fashion (i.e., only when it is necessary to do so for correctness or accuracy reasons) while sizing gates in the circuit design in a reverse-levelized processing order. 1. A method for optimizing a circuit design , the method comprising:while optimizing a first sequential cell, computing first timing-related information associated with a source driver that drives an input of the first sequential cell;storing the first timing-related information;reusing the first timing-related information while evaluating alternatives for the first sequential cell; andreusing the first timing-related information while optimizing a second sequential cell that has at least one input that is driven by the source driver.2. The method of claim 1 , wherein the first timing-related information includes one or more of:a minimum slack margin at an output of the source driver that drives the input of the first sequential cell;a worst case transition-effect coefficient at the output of the source driver that drives the input of the first sequential cell;an input of the source driver whose arrival time and transition time is propagated to the output of the source driver that drives the input of the first sequential cell;an arc from the ...

AUTOMATIC CONFIGURATION OF A WIRELESS DEVICE

A method of automatically configuring a wireless device includes receiving programming credentials from a server at a programming module and authenticating the wireless device based on the programming credentials. The method includes programming the wireless device with access credentials of an access point of a network to enable the wireless device to communicate, via the access point, with one or more devices outside of the network. 1. A method of automatically configuring a wireless device , the method comprising:receiving programming credentials from a server at a programming module;authenticating the wireless device based on the programming credentials; andprogramming the wireless device with access credentials of an access point of a network to enable the wireless device to communicate, via the access point, with devices outside of the network.2. The method of claim 1 , wherein authenticating the wireless device based on the programming credentials unlocks the wireless device to enable the programming of the wireless device with the access credentials.3. The method of claim 2 , wherein the programming module authenticates the wireless device by exchanging authentication messages with the wireless device via the access point.4. The method of claim 3 , wherein the programming credentials include a shared key.5. The method of claim 3 , wherein the programming credentials include a digital certificate.6. The method of claim 3 , wherein the programming credentials include a user-name and a password.7. The method of claim 3 , wherein the programming credentials include information stored within a subscriber identity module (SIM).8. The method of claim 3 , wherein the access credentials include a service set identifier (SSID) of the access point and a passphrase of the access point.9. The method of claim 8 , wherein the programming module is configured to receive the access credentials from the access point.10. The method of claim 8 , wherein the access credentials ...

Numerical delay model for a technology library cell and/or a technology library cell type

Methods and systems for determining a numerical delay model based on one or more discretized delay models are described. A discretized delay model is a delay model in which the delay behavior is represented using a set of discrete data points of delay behavior. A numerical delay model is a delay model that can be used by a numerical solver to optimize a cost function. In general, computing delay using a numerical delay model is significantly faster than computing delay using discretized delay models. This performance improvement is important when optimizing a design for various metrics like timing, area and leakage power, because repeated delay computations are required in circuit optimization approaches.

EXCLUDING LIBRARY CELLS FOR DELAY OPTIMIZATION IN NUMERICAL SYNTHESIS

Methods and systems for excluding library cells are described. Some embodiments receive a generic logical effort value and optionally a generic parasitic delay value for a timing arc of a library cell type. Next, library cells of the library cell type are excluded whose specific logical effort values for the timing arc are greater than the generic logical effort value by more than a first threshold and/or optionally whose specific parasitic delay values for the timing arc are greater than the generic parasitic delay value by more than a second threshold. A new generic logical effort value and optionally a new generic parasitic delay value can be determined based on at least some of the remaining library cells. The process of excluding library cells and determining new generic logical effort values and optionally new generic parasitic delay values can be performed iteratively. 1. A method for determining a subset of a set of library cells of a library cell type for a timing arc of the library cell type , the method comprising:receiving a first generic logical effort value for the timing arc of the library cell type; anddetermining, by using a computer, the subset of the set of library cells of the library cell type by excluding library cells in the set of library cells of the library cell type whose specific logical effort values for the timing arc are greater than the first generic logical effort value by more than a first threshold.2. The method of claim 1 , wherein the method further comprises iteratively performing said excluding by:determining a second generic logical effort value based on at least some library cells in the subset of the set of library cells of the library cell type; andexcluding library cells in the subset of the set of library cells of the library cell type whose specific logical effort values for the timing arc are greater than the second generic logical effort value by more than a second threshold.3. The method of claim 1 , wherein the ...

INCREMENTAL ELMORE DELAY CALCULATION

Systems and techniques for incrementally updating Elmore pin-to-pin delays are described. During operation, an embodiment receives a representation of a physical topology of a routed net that electrically connects a driver pin to a set of load pins. The embodiment then computes a set of incremental Elmore delay coefficients based on the representation. Next, using the Elmore delay coefficients, the embodiment computes a set of delays based on the representation, wherein each delay in the set of delays corresponds to a delay between the driver pin and a corresponding load pin in the set of load pins. As load pin capacitances change during circuit optimization, the set of incremental Elmore delay coefficients can then be used to update the delays between the driver pin and the load pins in a very computationally efficient manner. 1. A method for incrementally updating a set of Elmore pin-to-pin delays for a routed net that electrically connects a driver pin to a set of load pins , the method comprising:receiving a representation of a physical topology of the routed net that electrically connects the driver pin to the set of load pins;computing a set of incremental Elmore delay coefficients based on the representation, wherein the incremental Elmore delay coefficients do not need to be changed as long as the physical topology of the routed net does not change;receiving a change in a capacitance of a load pin in the set of load pins;computing, by using a computer, a set of incremental Elmore pin-to-pin delay adjustments based on the change in the capacitance and the set of incremental Elmore delay coefficients, wherein each incremental Elmore pin-to-pin delay adjustment is computed by multiplying a corresponding incremental Elmore delay coefficient with the change in the capacitance; andupdating the set of Elmore pin-to-pin delays by adding each incremental Elmore pin-to-pin delay adjustment in the set of incremental Elmore pin-to-pin delay adjustments to a ...

PROCESS FOR THE CONVERSION OF MIXED LOWER ALKANES TO AROMATIC HYDROCARBONS

A process comprising: contacting a lower alkane feed comprising propane and ethane with an aromatization catalyst in a first stage under first stage reaction conditions to produce a first stage product stream comprising ethane and aromatics; separating the aromatics from the first stage product stream to form an aromatics product stream and a second stage feed; and contacting the second stage feed with an aromatization catalyst in a second stage under second stage reaction conditions to produce a second stage product stream comprising ethane and aromatics wherein the amount ethane in the first stage product stream is equal to from 80 to 300% of the amount of ethane in the lower alkane feed and the amount of ethane in the second stage product stream is 500 equal to at most 80% of the amount of ethane in the second stage feed is described. 1. A process comprising:a. contacting a lower alkane feed comprising propane and ethane with an aromatization catalyst in a first stage under first stage reaction conditions to produce a first stage product stream comprising ethane and aromatics;b. separating the aromatics from the first stage product stream to form an aromatics product stream and a second stage feed; andc. contacting the second stage feed with an aromatization catalyst in a second stage under second stage reaction conditions to produce a second stage product stream comprising ethane and aromaticsd. wherein the amount of ethane in the first stage product stream is equal to from 80 to 300% of the amount of ethane in the lower alkane feed and the amount of ethane in the second stage product stream is equal to at most 80% of the amount of ethane in the second stage feed.2. The process as claimed in wherein the amount of ethane in the first stage product stream is equal to from 150 to 300% of the amount of ethane in the lower alkane feed.3. The process of wherein the amount of ethane in the first stage product stream is equal to from 200 to 300% of the amount of ethane ...

ESTIMATING OPTIMAL GATE SIZES BY USING NUMERICAL DELAY MODELS

Systems and techniques are described for estimating optimal gate sizes in a circuit design using numerical delay models of cells and cell types in a technology library. Gate sizes are optimized in the circuit design in a reverse-levelized processing order. Gates that are at the same level in the reverse-levelized processing order, and whose inputs are electrically connected to the same driver output are optimized together. A closed-form expression is used to determine the optimized size for each gate in a set of gates that are optimized together. Some embodiments perform multiple optimization iterations, wherein in each optimization iteration all of the gates in the circuit design are processed in the reverse-levelized processing order. The iterative optimization process terminates when one or more termination conditions are met. 1. A method for optimizing a circuit design , the method comprising:receiving the circuit design; and collecting circuit information, wherein the circuit information includes generic logical effort values of each gate in the set of gates, an input capacitance value and a specific logical effort value of a driver gate that drives one or more inputs of each gate in the set of gates, and a wire resistance value of a net that electrically connects an output of the driver gate with one or more inputs of each gate in the set of gates, and', 'determining gate sizes for the set of gates by substituting values from the collected circuit information into a set of closed-form expressions., 'optimizing gate sizes in the circuit design in a reverse-levelized processing order, wherein sizes of a set of gates at a given level in the circuit design are optimized by2. The method of claim 1 , wherein the collected circuit information includes a generic logical effort value for a virtual driver gate claim 1 , and a fixed load value as seen by the virtual driver gate.3. The method of claim 2 , wherein the fixed load value is equal to a sum of input ...

ACCURATE APPROXIMATION OF THE OBJECTIVE FUNCTION FOR SOLVING THE GATE-SIZING PROBLEM USING A NUMERICAL SOLVER

Systems and techniques are described for optimizing a circuit design by using a numerical solver. Some embodiments construct a set of lower bound expressions for a parameter that is used in an approximation of an objective function. Next, the embodiments evaluate the set of lower bound expressions to obtain a set of lower bound values. The embodiments then determine a maximum lower bound value from the set of lower bound values. Next, while solving a gate sizing problem using the numerical solver, the embodiments evaluate the approximate objective function and the partial derivatives of the approximate objective function by using the maximum lower bound value of the parameter. The maximum lower bound value of this parameter determines the accuracy of the approximation of the objective function. 1. A method for optimizing a circuit design , the method comprising:constructing a set of lower bound expressions for a parameter that is used in an approximation of a log-sum-exp approximation of a maximum function that is part of an objective function, wherein the set of lower bound expressions are constructed based on the objective function, partial derivatives of the objective function, the maximum value that can be represented by an underlying computing architecture and/or can be handled by a numerical solver, and the minimum value that can be represented in the underlying computing architecture and/or handled by the numerical solver;evaluating the set of lower bound expressions to obtain a set of lower bound values;determining a maximum lower bound value from the set of lower bound values; andwhile solving a gate sizing problem using the numerical solver, evaluating the objective function and the partial derivatives of the objective function by using the maximum lower bound value.2. The method of claim 1 , wherein the numerical solver is a conjugate-gradient based numerical solver claim 1 , and wherein the maximum lower bound value is computed for each net in the ...

DETERMINING OPTIMAL GATE SIZES BY USING A NUMERICAL SOLVER

Systems and techniques are described for optimizing a circuit design by using a numerical solver. The gates sizes are optimized by modeling a set of gate optimization problems and solving the set of gate optimization problems by using a numerical solver. Modeling each gate optimization problem can include selecting a portion of the circuit design that includes a driver gate that drives one or more inputs of each gate in a set of gates, and modeling a gate optimization problem for the portion of the circuit design based on circuit information for the portion of the circuit design. A differentiable objective function for delay can be created using numerical models for the delays in the circuit. In some embodiments, gradients of the differentiable objective function can be computed to enable the use of a conjugate-gradient-based numerical solver. 1. A method for optimizing a circuit design , the method comprising:receiving the circuit design;selecting a portion of the circuit design that includes a driver gate that drives one or more inputs of each gate in a set of gates;modeling a gate optimization problem for the portion of the circuit design based on circuit information that includes generic logical effort values of each gate in the set of gates, an input capacitance value and a specific logical effort value of the driver gate, and wire resistance and capacitance values of a net that electrically connects an output of the driver gate with one or more inputs of each gate in the set of gates, wherein said modeling includes constructing a differentiable objective function that minimizes the maximum delay from the driver gate to each gate in the set of gates;executing a conjugate-gradient based numerical solver to solve the set of gate optimization problems;incrementally computing a gradient of the differentiable objective function; andproviding the gradient to the conjugate-gradient based numerical solver.2. The method of claim 1 , further comprising:estimating gate ...

MODELING GATE SIZE RANGE IN A NUMERICAL GATE SIZING FRAMEWORK

Systems and techniques are described for optimizing a circuit design by using a numerical solver. The gates sizes are optimized by modeling a set of gate optimization problems and solving the set of gate optimization problems by using a numerical solver. The optimization can be performed iteratively, wherein in each iteration a gate optimization problem can be modeled for the portion of the circuit design based on circuit information for the portion of the circuit design. An objective function can be created, wherein the objective function includes at least one penalty function that imposes a lower and/or upper bound on at least one variable that is being optimized. In some embodiments, gradients of the objective function (which includes the penalty function) can be computed to enable the use of a conjugate-gradient-based numerical solver. 1. A method for modeling gate size range , the method comprising:selecting a gate in a circuit design that is to be optimized, wherein a range of a variable associated with the gate is desired to be bounded during optimization;determining a lower bound and/or an upper bound for the variable based on values of the variable associated with equivalent gates in a technology library that is to be used to optimize the gate;constructing, by computer, a penalty function based on the lower bound and/or the upper bound for the variable; andincorporating the penalty function into an objective function that is used during optimization.2. The method of claim 1 , wherein the penalty function has a first value when the variable is within a range defined by the lower and/or upper bounds claim 1 , wherein the penalty function has a value that is greater than the first value when the variable is outside the range defined by the lower and/or upper bounds claim 1 , and wherein the penalty function's value increases monotonically as a difference between the variable's value and the lower or upper bound increases.3. The method of claim 1 , further ...

OPTIMIZING A CIRCUIT DESIGN FOR DELAY USING LOAD-AND-SLEW-INDEPENDENT NUMERICAL DELAY MODELS

Systems and techniques are described for optimizing a circuit design. Specifically, gate sizes in the circuit design are optimized by iteratively performing a set of operations that include, but are not limited to: selecting a portion of the circuit design (e.g., according to a reverse-levelized processing order), selecting an input-to-output arc of a driver gate in the portion of the circuit design, selecting gates in the portion of the circuit design for optimization, modeling a gate optimization problem based on the selected input-to-output arc of the driver gate and the selected gates, solving the gate optimization problem to obtain a solution using one or more solvers, and discretizing the solution. Discretizing the solution involves identifying library cells that exactly or closely match the gate sizes specified in the solution. These library cells can then be used to model other gate optimization problems in the current or subsequent iterations. 1. A method for optimizing a circuit design , the method comprising:receiving the circuit design; and selecting a portion of the circuit design,', 'selecting an input-to-output arc of a driver gate in the portion of the circuit design,', 'selecting gates in the portion of the circuit design for optimization,', 'modeling a gate optimization problem based on the selected input-to-output arc of the driver gate and the selected gates, wherein said modeling uses a specific numerical delay model for the driver gate and generic numerical delay models for the selected gates, wherein the specific numerical delay model models the delay behavior of the selected input-to-output arc of the driver gate, and wherein, for each selected gate, the generic numerical delay model models an aggregated delay behavior of a library cell type associated with the selected gate,', 'solving the gate optimization problem to obtain a solution, and', 'discretizing the solution., 'optimizing, by computer, gate sizes in the circuit design, wherein ...

SYSTEMS, APPARATUS, AND METHODS FOR ADDRESS FORMAT DETECTION

Systems, methods, and devices for address format detection are described herein. In one aspect, a method of detecting whether an addressing format is supported by an access point on a wireless network is disclosed. The method includes transmitting a request to an access point using an addressing format including a source address field and a separate transmitter address field. In some aspects, the request may be an address resolution protocol (ARP) request or an Internet Control Message Protocol (ICMP) ping request. The request includes the source address field set to a first address and the transmitter address field set to a second address; monitoring transmissions of the access point to determine whether the access point transmits a response to the request that includes a destination address equal to the first address; and determining whether the access point supports the addressing format based on the monitoring. 1. A method of detecting whether an addressing format is supported by an access point on a wireless network , comprising:transmitting a request to an access point using an addressing format including a source address field and a separate transmitter address field, wherein the request includes the source address field set to a first address and the transmitter address field set to a second address;monitoring transmissions of the access point to determine whether the access point transmits a response to the request that includes a destination address equal to the first address; anddetermining whether the access point supports the addressing format based on the monitoring.2. The method of claim 1 , wherein the access point is determined to support the addressing format if the access point transmits a response to the request that includes a destination address equal to the first address.3. The method of claim 1 , wherein the access point is determined to not support the addressing format if the access point transmits a response to the request that includes a ...

INCREMENTAL SLACK MARGIN PROPAGATION

Techniques and systems are described for improving the efficiency of timing calculations in numerical sequential cell sizing and for improving the efficiency of incremental slack margin propagation. Some embodiments cache timing-related information associated with a source driver that drives an input of a sequential cell that is being sized, and/or timing-related information for each output of the sequential cell that is being sized. The cached timing-related information for the source driver can be reused when sizing a different sequential cell. The cached timing-related information for the outputs of the sequential cell can be reused when evaluating alternatives for replacing the sequential cell. Some embodiments incrementally propagate slack margins in a lazy fashion (i.e., only when it is necessary to do so for correctness or accuracy reasons) while sizing gates in the circuit design in a reverse-levelized processing order. 1. In an electronic design automation (EDA) tool in a computer , a method for incrementally propagating slack margins in a circuit design while optimizing the circuit design by processing gates in the circuit design in a reverse-levelized order , the method comprising:after the EDA tool in the computer replaces a first gate with an alternative gate, the EDA tool in the computer marking outputs of source drivers that drive inputs of the alternative gate as out-of-date;in response to the EDA tool in the computer determining that an output of a source driver is marked out-of-date, the EDA tool in the computer performing at least the following operations: (1) computing a new arrival time at the output of the source driver, (2) propagating the new arrival time to inputs of gates that are driven by the output of the source driver, and (3) removing an out-of-date mark from the output of the source driver;in response to the EDA tool in the computer determining that an input of a second gate is marked out-of-date or that a slack margin was not ...

Method and Apparatus for Reducing Constraints During Rewind Structural Verification of Retimed Circuits

A method for performing rewind functional verification includes identifying state variables that model the number of registers on each edge of a retiming graph for an original design and a retimed design. Random variables are identified that model retiming labels representing a number and direction of register movement relative to a node on a retiming graph for the retimed design. A retiming constraint is identified for each edge on the retiming graph for the design, wherein the retiming constraint reflects a relationship between the state variables and the random variables. A random variable that models a retiming label at a source of an edge is recursively substituted for a random variable that models a retiming label at a sink of the edge when a number of registers on the edge is unchanged after register retiming. 1. A method for performing rewind functional verification , comprising:identifying state variables that model a number of registers on each edge of a retiming graph for an original design and a retimed design;identifying random variables that model retiming labels representing a number and direction of register movement relative to a node on a retiming graph for the retimed design; andidentifying a retiming constraint for each edge on the retiming graph for the design, wherein the retiming constraint reflects a relationship between the state variables and the random variables; andsubstituting a random variable that models a retiming label at a source of an edge for a random variable that models a retiming label at a sink of the edge when a number of registers on the edge is unchanged after register retiming.2. The method of further comprising substituting the random variable that models the retiming label at the source of the edge for another random variable that models a retiming label at a node connected to the sink of the edge when a number of registers on an edge connecting the node to the sink is unchanged after the register retiming.3. The method ...

Method and Apparatus for Performing Rewind Structural Verification of Retimed Circuits Driven by a Plurality of Clocks

A method for designing a system on a target device includes performing register retiming on an original design for the system to generate a retimed design. The retimed design is verified to determine whether it is structurally correct by performing a plurality of iterations of register retiming on the retimed design, wherein each iteration accounts for the retiming of registers in the system driven by a different clock. 1. A method for designing a system on a target device , comprising:performing register retiming on an original design for the system to generate a retimed design; andverifying whether the retimed design is structurally correct by performing a plurality of iterations of register retiming on the retimed design, wherein each iteration accounts for the retiming of registers in the system driven by a different clock.2. The method of claim 1 , wherein performing register retiming on the retimed design comprises for each of the plurality of iterations claim 1 , defining a weight for each edge on a retiming graph for the original design and a retiming graph for the retimed design claim 1 , wherein the weight represents a number of registers on the edge driven by a clock associated with an iteration.3. The method of further comprising for each of the plurality of iterations claim 2 , identifying state variables that model the number of registers on the edge of the retiming graph for the original design and for the retimed design corresponding to registers driven by a current clock associated with a current iteration.4. The method of claim 3 , further comprising for each of the plurality of iterations claim 3 , identifying random variables that model retiming labels representing a number and direction of register movement relative to a node on a retiming graph for the retimed design.5. The method of claim 4 , further comprising for each of the plurality of iterations claim 4 , identifying a retiming constraint for each edge on the retiming graph for the design ...

Solving a gate-sizing optimization problem using a constraints solver

Systems and techniques are described for solving a gate-sizing optimization problem using a constraints solver. Some embodiments can create a constraints problem based on a gate-sizing optimization problem for a portion of a circuit design. Specifically, the constraints problem can comprise a set of upper bound constraints that impose an upper bound on one or more variables that are used in the objective function of the gate-sizing optimization problem. Next, the embodiments can solve the gate-sizing optimization problem by repeatedly solving the constraints problem using a constraints solver. Specifically, prior to each invocation of the constraints solver, the upper bound can be increased or decreased based at least on a result returned by a previous invocation of the constraints solver.

NUMERICAL AREA RECOVERY

Systems and techniques are described for performing area recovery on a circuit design. Some embodiments can select a gate for area recovery in accordance with a reverse-levelized processing order, wherein an output pin of a driver gate is electrically coupled to an input pin of the gate. Next, the embodiment can determine a maximum delay value from an input pin of the driver gate to an output pin of the gate that does not create new timing requirement violations or worsen existing timing requirement violations at any of the timing endpoints of the circuit design. The embodiment can then downsize the gate based on the maximum delay value, wherein said downsizing comprises inputting the maximum delay value in a closed-form expression. Timing margin computation can be used to ensure that timing violations are not worsened when the embodiment recovers area from non-timing-critical regions of the circuit design. 1. A method for performing area recovery on a circuit design , the method comprising:selecting a gate for area recovery, wherein an output of a driver gate is electrically coupled to an input of the gate;determining a maximum delay value from an input pin of the driver gate to an output pin of the gate that does not create new timing requirement violations or worsen existing timing requirement violations at any of the timing endpoints of the circuit design; anddownsizing, by using a computer, the gate based on the maximum delay value, wherein said downsizing comprises inputting the maximum delay value in a closed-form expression.2. The method of claim 1 , wherein said selecting the gate for area recovery involves selecting gates according to a reverse-levelized processing order.3. The method of claim 2 , wherein for a current processing level in the reverse-levelized processing order claim 2 , the method further comprises propagating timing margins backward to outputs of optimizable gates of the current processing level.4. The method of claim 3 , wherein within ...

Discretizing gate sizes during numerical synthesis

Systems and techniques are described for discretizing gate sizes during numerical synthesis. Some embodiments can receive an optimal input capacitance value for an input of an optimizable cell, wherein the input capacitance value is determined by a numerical solver that is optimizing the circuit design. Note that the circuit design may be optimized for different objective functions, e.g., best delay, minimal area under delay constraints, etc. Next, the embodiments can identify an initial library cell in a technology library whose input capacitance value is closest to the optimal input capacitance value. The embodiments can then use the initial library cell to attempt to identify a better (in terms of the objective function that is being optimized) library cell in the technology library. The delay computations used during this process are also minimized.

ROBUST NUMERICAL OPTIMIZATION FOR OPTIMIZING DELAY, AREA, AND LEAKAGE POWER

Systems and techniques are described for performing numerical delay, area, and leakage power optimization on a circuit design. During operation, an embodiment can iteratively perform at least the following set of operations in a loop, wherein in each iteration a current threshold voltage value is progressively decreased: (a) perform numerical delay optimization on the circuit design using a numerical delay model that is generated using gates in a technology library whose threshold voltages are equal to the current threshold voltage; (b) perform a total negative slack based buffering optimization on the circuit design; and (c) perform a worst negative slack touchup optimization on the circuit design that uses gates whose threshold voltages are greater than or equal to the current threshold voltage. Next, the embodiment can perform combined area and leakage power optimization on the circuit design. The embodiment can then perform multiple iterations of worst negative slack touchup optimization. 1. A method for performing delay , area , and leakage power optimization on a circuit design , the method comprising: performing numerical delay optimization on the circuit design using a numerical delay model that is generated using gates whose threshold voltages are equal to the current threshold voltage; and', 'performing a worst negative slack touchup optimization on the circuit design, wherein the worst negative slack touchup optimization uses gates whose threshold voltages are greater than or equal to the current threshold voltage., 'iteratively performing, by computer, at least the following set of operations in a loop, wherein in each iteration a current threshold voltage value is progressively decreased2. The method of claim 1 , wherein the set of operations in the loop further comprises performing a total negative slack based buffering optimization on the circuit design claim 1 , wherein the total negative slack based buffering optimization uses a numerical buffer ...

Solving an optimization problem using a constraints solver

Systems and techniques are described for solving an optimization problem using a constraints solver. A set of constraints that correspond to the optimization problem can be generated. Next, a set of upper bound constraints can be added to the set of constraints, wherein the set of upper bound constraints imposes an upper bound on one or more variables that are used in an objective function of the optimization problem. Next, the embodiments can iteratively perform the following set of operations on a computer: (a) solve the set of constraints using the constraints solver; (b) responsive to the constraints solver returning a solution, decrease the upper bound; and (c) responsive to the constraints solver indicating that no solutions exist or that the constraints solver timed out, increase the upper bound. The solution with the lowest upper bound value can be outputted as the optimal solution for the optimization problem.

Method and Apparatus for Verifying Structural Correctness in Retimed Circuits

A method for designing a system on a target device includes performing register retiming on an original design for the system to generate a retimed design. Whether the retimed design is structurally correct is verified by performing register retiming on the retimed design. 1. A non-transitory computer readable medium including a sequence of instructions stored thereon for causing a computer to execute a method for designing a system on a target device , comprising:performing register retiming on an original design for the system to generate a retimed design; anddetermining that the retimed design is structurally correct in response to determining that performing register retiming on the retimed design results in the original design.2. The non-transitory computer readable medium of claim 1 , wherein the performing register retiming on the retimed design comprises identifying how registers in the original design are repositioned to form the retimed design.3. The non-transitory computer readable medium of claim 1 , wherein the performing register retiming on the retimed design comprises identifying state variables that model registers on each edge of a retiming graph for the original design and for the retimed design.4. The non-transitory computer readable medium of claim 3 , wherein the performing register retiming on the retimed design comprises identifying random variables that model retiming labels representing a number and a direction of register movement relative to a node on a retiming graph for the retimed design.5. The non-transitory computer readable medium of claim 4 , wherein the performing register retiming on the retimed design comprises identifying a retiming constraint for each edge on the retiming graph for the retimed design claim 4 , wherein the retiming constraint reflects a relationship between the state variables and the random variables.6. The non-transitory computer readable medium of claim 5 , wherein the performing register retiming on the ...

CONFIGURABLE WICKLESS CAPILLARY-DRIVEN CONSTRAINED VAPOR BUBBLE (CVB) HEAT PIPE STRUCTURES

An integrated circuit package may include one or more integrated circuit dies and reconfigurable constrained vapor bubble (CVB) heat pipe structures formed on the integrated circuit dies. The reconfigurable CVB heat pipe structures may be adjusted using micro-electro-mechanical systems (MEMS) switches. By turning on a MEMS switch, the corresponding heat pipe structure will exhibit a first heat transfer efficiency. By turning off a MEMS switch, the corresponding heat pipe structure will exhibit a second heat transfer efficiency that is less than the first heat transfer efficiency. The reconfigurable CVB heat pipe structures may be statically programmed and/or dynamically adjusted as hot spot locations within the integrated circuit package migrate over time. 1. Circuitry , comprising:an integrated circuit die;an adjustable constrained vapor bubble (CVB) heat pipe structure coupled to the integrated circuit die; anda micro-electro-mechanical systems (MEMS) switch configured to adjust the adjustable CVB heat pipe structure.2. The circuitry of claim 1 , wherein the adjustable CVB heat pipe structure is wickless.3. The circuitry of claim 1 , wherein the MEMS switch comprises a piezoelectric switch.4. The circuitry of claim 1 , wherein the adjustable CVB heat pipe structure includes at least a first constrained vapor bubble at a first end and a second constrained vapor bubble at a second end claim 1 , and wherein the MEMS switch is configured to simultaneously adjust the size of the first and second constrained vapor bubbles.5. The circuitry of claim 1 , wherein the adjustable CVB heat pipe structure includes a first constrained vapor bubble at a first end and a second constrained vapor bubble at a second end claim 1 , and wherein the size of the first and second constrained vapor bubbles are independently adjustable.6. The circuitry of claim 1 , further comprising:control circuitry for selectively activating the MEMS switch, wherein the control circuitry comprises a ...

Methods for handling integrated circuit dies with defects

A method of handling integrated circuit dies with defects is provided. After forming a plurality of dies on one or more silicon wafers, test equipment may be used to identify defects on the dies and to create corresponding defect maps. The defect maps can be combined to form an aggregate defect map. Circuit design tools may create keep-out zones from the aggregate defect map and run learning experiments on each die, while respecting the keep-out zones, to compute design metrics. The circuit design tools may further create larger keep-out zones and run additional learning experiments on each die while respecting the larger keep-out zones to compute additional design metrics. The dies can be binned into different Stock Keeping Units (SKUs) based on one or more of the computed design metrics. Circuit design tools automatically respect the keep-out regions for these dies to program them correctly in the field.

Circuits And Methods For Accessing Signals In Integrated Circuits

An integrated circuit includes a monitored circuit and a signal analyzer circuit. The signal analyzer circuit includes a logic circuit that determines if a condition signal satisfies a condition to generate an output signal. A first-in-first-out (FIFO) buffer circuit stores opportunistic data indicated by a monitored signal received from the monitored circuit in response to the output signal indicating if the condition signal satisfies the condition. A communication channel transmits the opportunistic data stored in the FIFO buffer circuit outside the integrated circuit. 1. An integrated circuit comprising:a monitored circuit; anda signal analyzer circuit comprising a first logic circuit that determines if a first condition signal satisfies a first condition to generate a first output signal, a first-in-first-out (FIFO) buffer circuit that stores opportunistic data indicated by a monitored signal received from the monitored circuit in response to the first output signal indicating if the first condition signal satisfies the first condition, and a communication channel that transmits the opportunistic data stored in the FIFO buffer circuit to a storage location.2. The integrated circuit of claim 1 , wherein the signal analyzer circuit further comprises:a data logic circuit that stores a subset of the opportunistic data received from the FIFO buffer circuit based on the first output signal indicating that the first condition signal satisfies the first condition, wherein the data logic circuit provides the subset of the opportunistic data to the communication channel for transmission outside the integrated circuit.3. The integrated circuit of claim 1 , wherein the signal analyzer circuit further comprises:an additional monitored circuit;a circular buffer circuit that stores continuous data received from the additional monitored circuit based on the first output signal; anda data logic circuit that correlates timing of the opportunistic data received from the FIFO ...

MULTI-MODAL WIRELESS CONNECTION MANAGEMENT

A wireless device configured as a group owner determines whether all client devices paired with the group owner are currently associated with the group owner. If all paired client devices are currently associated with the group owner, the group owner enters a first mode in which the group owner is in an active mode (powered up to communicate) during a first portion of a beacon interval and is in a low power mode (in which no communication occurs) during a second portion of the beacon interval. If not all paired client devices are currently associated with the group owner, the group owner enters a second mode in which the group owner is in the active state during the first portion and at least part of the second portion of the beacon interval. The group owner and client devices are configured to operate as master and slave. 1. A method of operating a wireless device configured as a group owner of a peer-to-peer (P2P) group , the method comprising:in response to a determination that all of a number of client devices paired with the group owner are currently associated with the group owner, entering a first mode during which the group owner is in an active state during a first portion of a beacon interval and is in a low power mode during a second portion of the beacon interval; andin response to a determination that not all of the number of client devices paired with the group owner are currently associated with the group owner, entering a second mode during which the group owner is in the active state during the first portion and during at least part of the second portion of the beacon interval, wherein the group owner operates as a master device and the client devices operate as slave devices.2. The method of claim 1 , wherein group owner includes a transceiver claim 1 , and wherein:the transceiver is enabled during the active state; andthe transceiver is disabled during the low power mode.3. The method of claim 1 , further comprising:when operating in the first ...

SEPARATION OF CARBON DIOXIDE (CO2) FROM GAS MIXTURES BY CALCIUM BASED REACTION SEPARATION (CaRS-CO2) PROCESS

A reaction-based process developed for the selective removal of CO2 from a multicomponent gas mixture to provide a gaseous stream depleted in CO2 compared to the inlet CO2 concentration. The proposed process effects the separation of CO2 from a mixture of gases by its reaction with metal oxides. The Calcium based Reaction Separation for CO2 (CaRS—CO2) process consists of contacting CO2 laden gas with CaO in a reactor such that CaO captures CO2 by the formation of CaCO3. CaCO3 is regenerated by calcination leading to the formation of fresh CaO sorbent and the evolution of a concentrated stream of CO2. The “regenerated” CaO is then recycled for the further capture of CO2. This carbonation-calcination cycle forms the basis of the CaRS—CO2 process. This process also may use a mesoporous CaCO3 structure that attains >90% conversion over multiple carbonation and calcination cycles. 1. A method for separating carbon dioxide and sulfur dioxide from a flow of gas comprising carbon dioxide and sulfur dioxide , said method comprising the steps of:reacting said carbon dioxide and said sulfur dioxide with a metal oxide sorbent to convert at least a portion of said metal oxide sorbent to a metal carbonate and at least a portion of said sorbent to a metal sulfate;calcining at least a portion of said metal carbonate to form a reformed metal oxide sorbent and carbon dioxide; andreplenishing said metal oxide sorbent with said reformed metal oxide sorbent formed during calcination.2. The method of claim 1 , further comprising:separating said metal carbonate from said gas flow in a cyclone.3. The method of claim 1 , wherein said conversion of said metal oxide sorbent to metal carbonate and metal sulfate occurs at a temperature in the range of about 600° to about 650° Celsius.4. The method of claim 1 , further comprising:removing said carbon dioxide produced during calcination.5. The method of claim 1 , wherein said metal oxide sorbent has a mesoporous pore size distribution.6. The ...

POWER SAVE MECHANISM FOR LOW-POWER NETWORK DEVICES

A power save unit of a first network device determines a sleep duration associated with a sleep mode of a low-power network device based on an exchange of information between the first network device and the low-power network device of a communication network. The power save unit determines whether the low-power network device is in the sleep mode. In response to determining that the low-power network device is in the sleep mode, the power save unit redirects network packets destined to the low-power network device to the first network device. The first network device stores the redirected network packets and notifies the low-power network device that the first network device has stored the redirected network packets. 1. A method comprising:establishing, at a first network device, a communication link between the first network device and a low-power network device of a communication network;determining, at the first network device, a sleep duration associated with a sleep mode of the low-power network device based on an exchange of information between the first network device and the low-power network device;determining, at the first network device, whether the low-power network device is in the sleep mode;redirecting network packets from the communication network, destined to the low-power network device, to the first network device in response to determining that the low-power network device is in the sleep mode;storing the network packets from the communication network at the first network device; andnotifying the low-power network device that the first network device has stored the network packets.2. The method of claim 1 , wherein said establishing the communication link comprises exchanging association information and exchanging power save information between the first network device and the low-power network device.3. The method of claim 2 , wherein said exchanging association information comprises exchanging network addresses of the first network device and ...

SECURE PATCH UPDATES FOR PROGRAMMABLE MEMORIES

Methods, apparatus, and computer program products for securely writing patch code to a memory of a system-on-chip (SoC) are described. An example of a method for securely writing patch code to the memory of the SoC includes determining an authentication status of a patch code image, if the authentication status of the patch code image is authenticated, then writing the patch code from the patch code image into a one-time programmable (OTP) memory and generating a system reset signal, and if the authentication status of the patch code image is unauthenticated, then booting the SoC without writing the patch code from the patch code image into the OTP memory. 1. A method of securely writing patch code to a memory of a system-on-chip (SoC) comprising:determining an authentication status of a patch code image;if the authentication status of the patch code image is authenticated, then writing patch code from the patch code image into a one-time programmable (OTP) memory and generating a system reset signal; andif the authentication status of the patch code image is unauthenticated, then booting the SoC without writing the patch code from the patch code image into the OTP memory.2. The method of further comprising receiving the patch code image post-manufacturing via a signal received at the SoC.3. The method of further comprising claim 1 , in response to the system reset signal:executing primary boot loader (PBL) firmware stored in read-only memory; andreplacing at least a portion of the PBL firmware with the patch code written to the OTP memory.4. The method of further comprising determining the authentication status of the patch code image during execution of pre-boot loader code and based at least in part on a digital signature and a public key.5. The method of further comprising:in response to the writing the patch code into the OTP memory, writing a lock value to at least one of a fuse device or a one-time writable register (OWR); anddetermining an output of a write ...

METHODS AND APPARATUS FOR REDUCING RELIABILITY DEGRADATION ON AN INTEGRATED CIRCUIT

An integrated circuit with programmable logic circuitry is provided. The integrated circuit may include quiet regions, toggling regions, or unused regions. An integrated circuit may also include heavily-used metal routing paths, lightly-used metal routing paths, and unused metal routing paths. Circuit design tools may be used to generate multiple configuration images that replace the quiet regions with toggling or unused regions, that swap the heavily-used metal routing paths with lightly-used or unused metal routing paths, or that use random fitter seeds of improve the usage coverage to statistically reduce the always quiet regions on the integrated circuit. The multiple configuration images implement the same design and can be used to reconfigure the integrated circuit upon startup to reduce aging effects and improve circuit performance. 1. A method of using integrated circuit design tools to implement a given circuit design on an integrated circuit , the method comprising:with the integrated circuit design tools, generating a first configuration image to implement the given circuit design;with the integrated circuit design tools, generating a second configuration image that is different than the first configuration image, wherein the second configuration image also implements the given circuit design;configuring the integrated circuit using the first configuration image; andreconfiguring the integrated circuit using the second configuration image.2. The method of claim 1 , further comprising:generating a physical netlist for the given circuit design; andrunning functional simulation on the physical netlist to obtain signal activity profile data.3. The method of claim 2 , further comprising analyzing the signal activity profile data to identify a quiet region and a toggling region in the given circuit design.4. The method of claim 3 , further comprising analyzing the signal activity profile data to identify an unused region in the given circuit design.5. The ...

METHODS FOR REDUCING DELAY ON INTEGRATED CIRCUITS

Configuration data for an integrated circuit may be generated using logic design equipment to implement an circuit design on the integrated circuit. Implementing the circuit design may include placing functional blocks at optimal locations that increase the maximum operating frequency of the integrated circuit implementing the optimal circuit design. Logic design equipment may perform timing analysis on an initially placed circuit design that includes initially placed functional blocks. The timing analysis may identify one or more critical paths that may be shortened by moving the critical functional blocks within the circuit design to candidate placement locations. A levelized graph representing possible candidate locations and paths between the possible candidate locations may be traversed in a breadth-first search to generate a shortest updated critical path. The critical functional blocks may be moved to candidate locations corresponding to the updated critical path. The process of shortening critical paths may be iteratively performed. 1. A method of operating design tools running on logic design computing equipment to implement a circuit design , the method comprising:placing a plurality of functional blocks in the circuit design;identifying a critical path linking the plurality of functional blocks;identifying candidate placement locations for each of the plurality of functional blocks in the critical path;generating a levelized graph that represents possible paths linking the candidate placement locations for a first functional block in the plurality of functional blocks to the candidate placement locations for a second functional block in the plurality of functional blocks; andanalyzing the levelized graph to identify an updated critical path.2. The method of claim 1 , further comprising:updating the placement of the plurality of functional blocks according to the updated critical path.3. The method of claim 2 , further comprising:determining whether the ...

METHOD AND APPARATUS FOR PERFORMING REWIND STRUCTURAL VERIFICATION OF RETIMED CIRCUITS DRIVEN BY A PLURALITY OF CLOCKS

A method for designing a system on a target device includes performing register retiming on an original design for the system to generate a retimed design. The retimed design is verified to determine whether it is structurally correct by performing a plurality of iterations of register retiming on the retimed design, wherein each iteration accounts for the retiming of registers in the system driven by a different clock. 1. A method for designing a system on a target device , comprising:performing register retiming on an original design to generate a retimed design of the system;identifying compare points in the original design and the retimed design where signal values reflect initial states of one or more flip-flops;performing bounded sequential logic simulation within a time frame; anddetermining whether changed flip-flops in the retimed design have initial states that are correct by comparing signal values at the compare points from the bounded sequential logic simulation.2. The method of further comprising identifying the compare points from retiming labels that reflect a number and direction of register movement relative to a node in the retimed design.3. The method of claim 1 , wherein a number of time frames for performing bounded sequential logic simulation is determined from a maximum absolute value of retiming labels that reflect a number and direction of register movement relative to a node in the retimed design.4. The method of claim 1 , wherein a changed flip-flop is a flip-flop that has been re-positioned from the original design.5. The method of claim 1 , wherein an initial state is a state of a register at power-up.6. The method of claim 1 , wherein determining whether changed flip-flops in the retimed design have initial states that are correct is performed in response to determining that unchanged flip-flops in the retimed design have initial states that are correct.7. The method of further comprising generating an indication of the correctness of ...

FAST MEMORY FOR PROGRAMMABLE DEVICES

An integrated circuit device may include a programmable fabric die having programmable logic fabric and configuration memory that may configure the programmable logic fabric. The integrated circuit device may also include a base die that may provide fabric support circuitry, including memory and/or communication interfaces as well as compute elements that may also be application-specific. The memory in the base die may be directly accessed by the programmable fabric die using a low-latency, high capacity, and high bandwidth interface. 1. A programmable fabric device , comprising: a plurality of partial reconfiguration regions each corresponding to a design for the programmable fabric, wherein the partial reconfiguration regions of the plurality of partial reconfiguration regions are aligned to sectors of the programmable fabric;', 'a plurality of external sectors outside of the plurality of partial reconfiguration regions; and', 'fabric resources that couple the external sectors to adjacent sectors of the plurality of the partial reconfiguration regions; and, 'a fabric die having a programmable fabric comprisinga base die coupled to the external sectors and that provides interconnection between the external sectors.2. The programmable fabric device of claim 1 , wherein the external sectors enable communications between regions using external paths outside of the plurality of partial reconfiguration regions.3. The programmable fabric device of claim 2 , wherein communications between partial reconfiguration regions of the plurality of partial reconfiguration regions uses at least one of the plurality of external sectors.4. The programmable fabric device of claim 1 , wherein communications between partial reconfiguration regions of the plurality of partial reconfiguration regions uses a network on chip of the base die.5. The programmable fabric device of claim 1 , wherein background partial reconfiguration personas for the plurality of partial reconfiguration region ...

METHODS FOR VERIFYING RETIMED CIRCUITS WITH DELAYED INITIALIZATION

Circuit design computing equipment may perform register moves within a circuit design. When moving the registers, counter values may be maintained for non-justifiable elements. The counter values may be maintained and updated on a per element, per clock domain basis to account for register moves across the corresponding non-justifiable elements. The maximum counter value for each clock domain may be chosen as an adjustment value that is used to generate a sequence for resetting the modified circuit design after the register moves. The adjustment value may be bound by a user-specified maximum value. This retiming operation may also be verified by performing rewind verification. The rewind verification involves retiming the retimed circuit back to the original circuit, while respecting the counter values. If verification succeeds, the circuit design may be reset using a smaller adjustment value. If verification fails, a correct counter value may be suggested for each clock domain. 1. A method for implementing an integrated circuit using integrated circuit design tools running on computing equipment , comprising:retiming an original circuit design of the integrated circuit to produce a retimed circuit design for the integrated circuit;determining a count value c for a clock domain, wherein the original circuit design is properly reset using an initialization sequence, and wherein the retimed circuit is reset using a delayed initialization sequence that is delayed with respect to the initialization sequence by c clock cycles for the clock domain; andverifying that the original circuit design using the initialization sequence and the retimed circuit using the c-cycle delayed initialization sequence are sequentially equivalent.2. The method of claim 1 , wherein verifying that the original circuit design and the retimed circuit design are c-cycle sequentially equivalent comprises performing rewind structural verification.3. The method of claim 2 , wherein performing the ...

Numerical delay model for a technology library cell type

Methods and systems for determining a numerical delay model based on one or more discretized delay models are described. A discretized delay model is a delay model in which the delay behavior is represented using a set of discrete data points of delay behavior. A numerical delay model is a delay model that can be used by a numerical solver to optimize a cost function. In general, computing delay using a numerical delay model is significantly faster than computing delay using discretized delay models. This performance improvement is important when optimizing a design for various metrics like timing, area and leakage power, because repeated delay computations are required in circuit optimization approaches.

AUTOMATIC CONFIGURATION OF A WIRELESS DEVICE

A method of automatically configuring a wireless device includes performing service discovery by the wireless device to identify a programming module and sending to the programming module a probe request including a first device public key. The method includes receiving from the programming module a probe response including an indication of a match between the first device public key and a second device public key. 1. A method of automatically configuring a wireless device , the method comprising:performing service discovery by the wireless device to identify a programming module;sending to the programming module a probe request including a first device public key;receiving from the programming module a probe response including an indication of a match between the first device public key and a second device public key;receiving from the programming module one or more authentication messages including programming credentials;receiving from the programming module an authentication success message after authentication of the wireless device, wherein the wireless device is unlocked to enable programming of access credentials of an access point after receiving the authentication success message; andreceiving from the programming module a programming message after receiving the authentication success message, wherein the programming message includes the access credentials of the access point.2. The method of claim 1 , wherein the indication of the match between the first device public key and the second device public key includes an invitation from the programming module to the wireless device to initiate configuration of the wireless device by the programming module.3. The method of claim 1 , wherein the wireless device performs the service discovery based on a beacon claim 1 , a public action frame claim 1 , a probe request message claim 1 , or any combination thereof.4. The method of claim 1 , wherein the wireless device is authenticated by the programming module based ...

On-Die Aging Measurements for Dynamic Timing Modeling

A method includes mapping an AMC into the core fabric of an FPGA and operating the AMC for a select time period. During the select period of time, the AMC counts transition of a signal propagating through the AMC. Timing information based on the counted transitions is stored in a timing model in a memory. The timing information represents an aging characteristic of the core fabric at a time that the AMC is operated. An EDA toolchain uses the timing information in the timing model to generate a timing guard-band for the configurable IC die. The AMC is removed from the core fabric and another circuit device is mapped and fitted into the core fabric using the generated timing guard-band models. The circuit device is operated in the configurable IC die based on the timing guard-band models.

LOW LATENCY 802.11 MEDIA ACCESS

A method, an apparatus, and a computer program product for wireless communication are provided. The apparatus may comprise a transceiver configured to transmit uplink frames and receive downlink frames in a first transaction slot of a super-frame. The one or more of the uplink frames and the downlink frames are associated with over-allocated network allocation vectors that reserve a transmission time which exceeds a time required to transmit acknowledgements of the one or more downlink frames or receive acknowledgement of the one or more uplink frames, respectively. The apparatus may comprise a processing system configured to cause the transceiver to transmit a first uplink frame to the access point with a first over-allocated NAV, to establish a start-time for the super-frame and to extract data from two or more downlink frames in a burst received from the access point.

Techniques For Providing Optimizations Based On Categories Of Slack In Timing Paths

Systems and methods are provided for using an integrated circuit design tool to analyze timing requirements of a circuit design for an integrated circuit. A slack is calculated for a timing path in the circuit design that fails to satisfy a timing constraint. The slack is decomposed into multiple categories of delays in the timing path. The categories of delays for the slack may include intrinsic margin, clock skew, logic delay, and fabric interconnect delay. The logic delay may include local interconnect delay and logic circuit delay. The fabric interconnect delay may include delays in interconnect elements that are used to make connections between larger blocks of the logic circuits. Different optimization strategies are provided to solve the timing constraint failure for each of the different categories of slack breakdown. Slack profiles of the entire design in each of the four categories of slack are also provided. 1. A method of using an integrated circuit design tool to analyze timing requirements of a circuit design for an integrated circuit , the method comprising:calculating a slack for a timing path in the circuit design that fails to satisfy a timing constraint;decomposing the slack for the timing path into categories of delays in the timing path, wherein a first one of the categories of delays is intrinsic margin that comprises a first edge of a first clock signal, a second edge of a second clock signal, a delay of a first sequential circuit responsive to the first clock signal, and a delay of a second sequential circuit responsive to the second clock signal; andproviding a first set of optimizations for the intrinsic margin in response to a comparison between the intrinsic margin and a timing failure threshold indicating that the intrinsic margin is a factor in the failure to satisfy the timing constraint.2. The method of further comprising:providing profiles of the slack for an entirety of the circuit design in four of the categories of delays, wherein ...

METHODS AND APPARATUS FOR AUTOMATICALLY IMPLEMENTING A COMPENSATING RESET FOR RETIMED CIRCUITRY

A compensating initialization module may be automatically inserted into a design to compensate for register retiming which changes the designs behavior under reset. The device configuration circuitry may provide an adjustment sequence length as well as a start signal to the initialization module to properly reset the retimed user logic implemented on the integrated circuit after initial configuration and unfreezing of the integrated circuit. The auto initialization module may control the c-cycle initialization process and indicate to the user logic when c-cycle initialization has completed. The user logic may subsequently begin a user-specified reset sequence. When the user-specified reset sequence ends, the user logic implemented on the integrated circuit may begin normal operations. Additionally, a user reset request may also trigger the auto initialization module to begin a reset process. 1. An integrated circuit , comprising:logic circuitry that is reset using a reset sequence;configuration circuitry that programs the logic circuitry to implement a custom logic function and that provides a count value c; andan initialization module that is interposed between the logic circuitry and the configuration circuitry and that automatically delays the reset sequence by c clock cycles.2. The integrated circuit of claim 1 , wherein the initialization module receives a clock signal from the logic circuitry.3. The integrated circuit of claim 2 , wherein the initialization module receives a reset trigger signal from a selected one of the configuration circuitry and the logic circuitry.4. The integrated circuit of claim 3 , wherein the reset trigger signal comprises a start signal that is conveyed from the configuration circuitry to the initialization module.5. The integrated circuit of claim 3 , wherein the reset trigger signal comprises a request signal that is conveyed from the logic circuitry to the initialization module.6. The integrated circuit of claim 3 , wherein the ...

Methods and apparatus to insert buffers in a dataflow graph

Disclosed examples to insert buffers in dataflow graphs include: a backedge filter to remove a backedge between a first node and a second node of a dataflow graph, the first node representing a first operation of the dataflow graph, the second node representing a second operation of the dataflow graph; a latency calculator to determine a critical path latency of a critical path of the dataflow graph that includes the first node and the second node, the critical path having a longer latency to completion relative to a second path that terminates at the second node; a latency comparator to compare the critical path latency to a latency sum of a buffer latency and a second path latency, the second path latency corresponding to the second path; and a buffer allocator to insert one or more buffers in the second path based on the comparison performed by the latency comparator.

PROCESS FOR PREPARING A PARAFFIN PRODUCT

The Fischer-Tropsch process can be used for the conversion of hydrocarbonaceous feed stocks into normally liquid and/or solid hydrocarbons (i.e. measured at 0° C., 1 bar). The feed stock (e.g. natural gas, associated gas, coal-bed methane, residual oil fractions, biomass and/or coal) is converted in a first step into a mixture of hydrogen and carbon monoxide. This mixture is often referred to as synthesis gas or syngas. The present invention relates to process for preparing a paraffin product from a carbonaceous feedstock and a system for preparing a paraffin product from a carbonaceous feedstock. 1. A process for preparing a paraffin product from a carbonaceous feedstock comprising the following steps:i. Converting a carbonaceous feedstock such as a gas mixture comprising natural gas to obtain a mixture comprising hydrogen and carbon monoxide,ii. Performing a Fischer-Tropsch reaction using the mixture as obtained in step i. and recovering an off-gas from the Fischer-Tropsch reaction and a paraffin product,iii. Feeding said off-gas to a gas separation unit comprising at least one gas separating membrane;iv. Obtaining from said gas separation unit a permeate gas and a retentate gas;v. Adding at least a part of said retentate gas to the carbonaceous feedstock to be converted in step i.2. The process according to wherein the off-gas comprises water claim 1 , methane claim 1 , carbon dioxide claim 1 , hydrogen claim 1 , carbon monoxide claim 1 , C2-C5 hydrocarbons argon and nitrogen claim 1 , 10-50 vol % carbon dioxide claim 1 , 0.1-65 vol % carbon monoxide claim 1 , 1-80 vol % hydrogen claim 1 , up to 2 vol % C2-C5 hydrocarbons claim 1 , 1-55 vol % nitrogen and up to 3 vol % of argon claim 1 , based on the total volume of the off-gas.3. The process according to wherein the retentate gas comprises at least carbon monoxide claim 2 , methane and hydrocarbons.4. The process according to wherein the gas separation membrane is a carbon molecular sieve membrane.5. The process ...

PROCESS FOR PREPARING A PARAFFIN PRODUCT

The Fischer-Tropsch process can be used for the conversion of hydrocarbonaceous feed stocks into normally liquid and/or solid hydrocarbons (i.e. measured at 0° C., 1 bar). The feed stock (e.g. natural gas, associated gas, coal-bed methane, residual oil fractions, biomass and/or coal) is converted in a first step into a mixture of hydrogen and carbon monoxide. This mixture is often referred to as synthesis gas or syngas. The present invention relates to process for preparing a paraffin product from a carbonaceous feedstock and a system for preparing a paraffin product from a carbonaceous feedstock. 1. A system for preparing a paraffin product from a carbonaceous feedstock comprising the following:i. one or more reactors for converting the carbonaceous feedstock into a gas mixture comprising hydrogen and carbon monoxide;ii. one or more reactors for conducting a Fischer-Tropsch reaction, comprising a Fischer-Tropsch catalyst;iii. one or more gas separation units comprising a membrane for separating gas;wherein the gas separation unit is connected to the one or more reactors for converting carbonaceous feedstock such that a retentate gas obtained in the one or more gas separation units is provided to said one or more reactors for converting carbonaceous feedstock.2. The system according to claim 1 , further comprising one or more pretreatment units.3. The system according to claim 2 , wherein the pretreatment unit comprises an adsorption-based unit.4. The system according to claim 3 , wherein the adsorption-based unit is selected from a thermal swing adsorption unit claim 3 , a pressure swing adsorption unit and an adsorption unit comprising adsorption material which cannot be regenerated.5. The system according to claim 1 , comprising downstream of the Fischer-Tropsch reactor and upstream of the gas separation unit at least one CO shift reactor.6. The system according to claim 1 , wherein the gas separation membrane is a carbon molecular sieve membrane.7. The system ...

CONFIGURABLE LOW MEMORY MODES FOR REDUCED POWER CONSUMPTION

Certain aspects of the present disclosure provide apparatus and techniques for configuring memory in an effort to reduce power consumption. For example, certain aspects of the present disclosure may provide an apparatus having a processing system configured to determine an operating mode of an application executing on the processing system. The operating mode may be one of a plurality of operating modes of the application, and each operating mode of the plurality of operating modes may correspond to a different configuration of memory. In certain aspects, the configurations of memory may correspond to different portions of memory that are active or inactive. In certain aspects, the apparatus may also include a memory control module configured to configure the memory based on the determined operating mode of the application. 1. An apparatus , comprising:a processing system configured to determine an operating mode of an application executing on the processing system, the operating mode being one of a plurality of operating modes of the application, wherein each operating mode of the plurality of operating modes corresponds to a different configuration of memory, the configurations of memory corresponding to different portions of memory that are active or inactive; anda memory control module configured to configure the memory based on the determined operating mode of the application.2. The apparatus of claim 1 , wherein the application comprises a plurality of operations claim 1 , wherein in each of the operating modes claim 1 , different operations of the plurality of operations are placed in different states corresponding to one of the memory configurations.3. The apparatus of claim 1 , wherein the processing system is further configured to determine a service to be provided by the apparatus claim 1 , wherein the operating mode is determined based on the service.4. The apparatus of claim 1 , wherein the operating mode comprises a full operating mode (FOM) claim 1 , ...

METHODS FOR PERFORMING REGISTER RETIMING WITH HYBRID INITIAL STATES

An integrated circuit design may include registers and combinational logic. Integrated circuit design computing equipment may perform retiming for the circuit design, where registers are moved across one or more portions of the combinational logic. The registers may be retimed while considering hybrid initial states of the registers. At least some of the registers may have don't-care initial states. When performing backward retiming, initial states of the retimed registers may be computed that is consistent with the original initial state and functionality of the combinational logic while maximizing the number of don't-care initial states. When performing forward retiming across non-justifiable combinational elements, any don't-care initial states may be assumed to be equal to a deterministic binary value, and the initial states of the retimed registers may be computed that is consistent with the original initial states and functionality of the combinational logic. 1. A method of operating an integrated circuit design tool implemented on computing equipment , comprising:receiving a circuit design that includes a register coupled to a combinational element;determining an initial state for the register; andin response to determining that the initial state of the register is a don't-care initial state, performing retiming by moving the register across the combinational element, wherein the retiming is a forward retiming move;determining whether the combinational element is a non-justifiable circuit element;in response to determining that the combinational element is a non-justifiable circuit element, assuming that the don't-care initial state of the register before the forward retiming move is equal to a deterministic binary value; andcomputing an initial state for the retimed register.2. (canceled)3. The method of claim 1 , wherein the computed initial state is consistent with the initial state of the register and the functionality of the combinational element.4. The ...

Process for preparing a paraffin product

Process for the conversion of lower alkanes to aromatic hydrocarbons

A process is provided for producing aromatic hydrocarbons which comprises: (a) contacting a lower alkane feed with a solid particulate aromatic hydrocarbon conversion catalyst in a fixed bed reaction zone to produce aromatic hydrocarbons and other products, whereby the catalyst is at least partially deactivated by the formation of undesirable coke deposits,(b) periodically regenerating the catalyst under regeneration conditions, (c) separating aromatic hydrocarbons from the other products and unreacted lower alkanes, and (d) optionally recycling unreacted lower alkanes to the reaction zone wherein the fixed bed reaction zone additionally comprises a volume of a catalytically inactive solid.

Delegated network connection management and power management in a wireless device

A method and system for advanced media access control delegated from a host device, such as a WiFi device, to a smart wireless communications module. In an embodiment, the host signals to the wireless module a list of one or more preferred networks. The wireless module offloads from the host the processing required to scan for the preferred network(s), as well as possibly other management tasks. The wireless communications module may automatically reassign the network connection from an existing network to a preferred network, or may report to the host when a preferred network is discovered. In either case, the wireless communications module may monitor the wireless environment, and scan for preferred networks, in parallel with maintaining an existing connection. The method and system allows rapid adaptation to a changing network environment, and enables lower system power consumption by distributing management functions between the host and the lower-powered wireless communications module.

Separation of carbon dioxide (CO2) from gas mixtures

A reaction-based process has been developed for the selective removal of carbon dioxide from a multicomponent gas mixture. The proposed process effects the separation of CO 2 from a mixture of gases by its reaction with metal oxides. The Calcium based Reaction Separation for CO 2 process consists of contacting a CO 2 laden gas with calcium oxide in a reactor such that CaO captures the CO 2 by the formation of calcium carbonate. Once “spent”, CaCO 3 is regenerated by its calcination leading to the formation of fresh CaO sorbent. The “regenerated” CaO is then recycled for the further capture of more CO 2 . This process also identifies the application of a mesoporous CaCO 3 structure, that attains >90% conversion over multiple carbonation and calcination cycles. Lastly, thermal regeneration (calcination) under vacuum provided a better sorbent structure that maintained reproducible reactivity levels over multiple cycles.

High temperature CO2 capture using engineered eggshells: a route to carbon management

Applying an acid treatment to eggshells provides a sorbent with unexpectedly high CO 2 capture capacity and ability to regenerate.

Calcium cycling process for the production of high purity hydrogen

Un procedimiento para producir hidrógeno, que comprende las etapas de: gasificar un combustible en un gas de síntesis crudo que comprende CO, hidrógeno, vapor y azufre y contaminantes de haluros en forma de H2S, COS y HX, donde X es un haluro; inyectar dicho gas de síntesis crudo, CaO y vapor en un reactor de desplazamiento de gas de agua, WGSR, donde el vapor se inyecta en dicho WGSR en el intervalo del requerimiento estequiométrico a 3 veces el requerimiento estequiométrico, donde dicho gas de síntesis crudo se transforma en un gas desplazado sin un catalizador; permitiendo que dicho gas desplazado reaccione con dicho CaO en dicho WGSR a fin de eliminar el CO2, el azufre y los haluros en un producto que contiene calcio en fase sólida que comprende CaCO3, CaS y CaX2; separar el producto que contiene calcio en fase sólida de un producto de hidrógeno gaseoso enriquecido; y regenerar el CaO calcinando el producto que contiene calcio en fase sólida en un estado seleccionado de entre el grupo que consiste en: en presencia de vapor, en presencia de CO2, en presencia de gas de síntesis, en presencia de H2 y O2, bajo vacío parcial, y combinaciones de los mismos. A process for producing hydrogen, comprising the steps of: gasifying a fuel into a crude synthesis gas comprising CO, hydrogen, steam and sulfur and halide contaminants in the form of H2S, COS and HX, where X is a halide; inject said crude synthesis gas, CaO and steam into a water gas displacement reactor, WGSR, where the steam is injected into said WGSR in the range of the stoichiometric requirement to 3 times the stoichiometric requirement, where said crude synthesis gas is transforms into a displaced gas without a catalyst; allowing said displaced gas to react with said CaO in said WGSR in order to remove CO2, sulfur and halides in a solid phase calcium-containing product comprising CaCO3, CaS and CaX2; separating the solid phase calcium-containing product from an enriched hydrogen gas product; and regenerate ...

Process for the conversion of lower alkanes to aromatic hydrocarbons

The present invention provides a process for producing aromatic hydrocarbons which comprises: (a) alternately contacting a lower alkane feed with an aromatization catalyst under aromatization reaction conditions in a reactor for a short period of time, preferably 30 minutes or less, to produce aromatic reaction products and then contacting the aromatization catalyst with a hydrogen-containing gas at elevated temperature for a short period of time, preferably 10 minutes or less, (b) repeating the cycle of step (a) at least one time, (c) regenerating the aromatization catalyst by contacting it with an oxygen-containing gas at elevated temperature and (d) repeating steps (a) through (c) at least one time.

Method for identifying untestable faults in logic circuits

A method of identifying untestable faults in a logic circuit. A lead in the circuit is selected and the circuit is analyzed to determine which faults would be untestable if the selected circuit lead were unable to assume a logic 0 and which faults would be untestable if the selected circuit lead were unable to assume a logic 1. Faults that would be untestable in both (hypothetical) cases are identified as untestable faults. Faults which would be untestable if the selected lead were unable to assume a given value may be determined based on an implication procedure. The implication procedure comprises the forward propagation of uncontrollability indicators and the backward propagation of unobservability indicators. An uncontrollability indicator for the given value is assigned to the selected circuit lead and propagated forward through the circuit according to a set of well-defined propagation rules. In addition, unobservability indicators are generated in the circuit based on the propagation of uncontrollability indicators. These unobservabilityindicators are then propagated backward through the circuit. The (hypothetically) untestable faults are then determined based on the resultant indicators and their corresponding circuit leads. Untestable faults may be identified in a sequential circuit by generating an equivalent combinational iterative array circuit model for a fixed number of time frames. Faults that would be untestable in both (hypothetical) cases and which are located in the last (i.e., latest-in-time) time frame are identified as untestable faults.

A process for producing hydrogen

A process is described for producing hydrogen comprising: producing an aqueous feed stream comprising 5% to 15% wt. ethanol by a biomass fermentation process; separating at least a portion of the water from the feed stream so that the concentration of ethanol in the resulting reformer feed stream is in the range of from 15% to 35% wt.; and contacting the reformer feed stream with a catalyst in a reformer under reforming conditions to produce a reformer product stream comprising hydrogen wherein the pressure in the reformer is in a range of from 100 psi to 600 psi.

Systems, apparatus, and methods for address format detection

Systems, methods, and devices for address format detection are described herein. In one aspect, a method of detecting whether an addressing format is supported by an access point on a wireless network is disclosed. The method includes transmitting a request to an access point using an addressing format including a source address field and a separate transmitter address field. In some aspects, the request may be an address resolution protocol (ARP) request or an Internet Control Message Protocol (ICMP) ping request. The request includes the source address field set to a first address and the transmitter address field set to a second address; monitoring transmissions of the access point to determine whether the access point transmits a response to the request that includes a destination address equal to the first address; and determining whether the access point supports the addressing format based on the monitoring.

Process for the conversion of lower alkanes to aromatic hydrocarbons and ethylene

A process comprising: contacting a lower alkane feed with an aromatization catalyst in a first stage under first stage reaction conditions to produce a first stage product stream comprising ethane and aromatics; separating the aromatics from the first stage product stream to form an aromatics product stream and a non-aromatics product stream; introducing a first portion of the non-aromatics product stream into an alkane cracker; and contacting a second portion of the non-aromatics product stream with an aromatization catalyst in a second stage under second stage reaction conditions to produce a second stage product stream comprising aromatics is described herein.

SEPARATION OF CARBON DIOXIDE (CO2) FROM GAS MIXTURES BY CALCIUM BASED REACTION SEPARATION ( CaRS-CO2) PROCESS

A reaction-based process has been developed for the selective removal of carbon dioxide (CO2) from a multicomponent gas mixture to provide a gaseous stream depleted in CO2 compared to the inlet CO2 concentration in the stream. The proposed process effects the separation of CO2 from a mixture of gases (such as flue gas/fuel gas) by its reaction with metal oxides (such as calcium oxide). The Calcium based Reaction Separation for CO2 (CaRS-CO2) process consists of contacting a CO2 laden gas with calcium oxide (CaO) in a reactor such that CaO captures the CO2 by the formation of calcium carbonate (CaCOa). Once 'spent', CaCO3 is regenerated by its calcination leading to the formation of fresh CaO sorbent and the evolution of a concentrated stream of CO2. The 'regenerated' CaO is then recycled for the further capture of more CO2. This carbonation-calcination cycle forms the basis of the CaRS-CO2 process. This process also identifies the application of a mesoporous CaCO3 structure, developed by a process detailed elsewhere, that attains >90% conversion over multiple carbonation and calcination cycles. Lastly, thermal regeneration (calcination) under vacuum provided a better sorbent structure that maintained reproducible reactivity levels over multiple cycles.

Process for the conversion of mixed lower alkanes to aromatic hydrocarbons

A process for the conversion of mixed lower alkanes into aromatics which comprises first reacting a mixed lower alkane feed comprising at least propane and ethane in the presence of an aromatization catalyst under reaction conditions which maximize the conversion of propane into first stage aromatic reaction products, separating ethane from the first stage aromatic reaction products, reacting ethane in the presence of an aromatization catalyst under reaction conditions which maximize the conversion of ethane into second stage aromatic reaction products, and optionally separating ethane from the second stage aromatic reaction products.

A process for producing hydrogen

A process is described for producing hydrogen comprising: producing an aqueous feed stream comprising 5% to 15% wt. ethanol by a biomass fermentation process; separating at least a portion of the water from the feed stream so that the concentration of ethanol in the resulting reformer feed stream is in the range of from 15% to 35% wt.; and contacting the reformer feed stream with a catalyst in a reformer under reforming conditions to produce a reformer product stream comprising hydrogen wherein the pressure in the reformer is in a range of from 100 psi to 600 psi.

Method and apparatus for determining a robustness metric for a circuit design

Some embodiments provide techniques and systems for determining a change indicator for an endpoint, a pathgroup, a design, and/or a flow. The system can determine base critical path delays and base slacks for the endpoints in a base implementation of the circuit design. The system can then determine the new critical path delays and new slacks for the endpoints in a new implementation of the circuit design. Next, the system determines slack differences for the endpoints using the new slacks and the base slacks. Finally, for each endpoint, the system can determine an endpoint change indicator using the associated slack difference, the base critical path delay, and the new critical path delay. A pathgroup change indicator can be determined using endpoint change indicators. A design change indicator can be determined using pathgroup change indicators or scenario change indicators. A design flow change indicator can be determined using design change indicators.

Methods for bounding the number of delayed reset clock cycles for retimed circuits

Integrated circuit design computing equipment may perform register moves within a circuit design. When moving the registers, counter values may be maintained for non-justifiable elements. The counter values may be maintained and updated on a per element, per clock domain basis to account for register moves across the corresponding non-justifiable elements. The maximum counter value for each clock domain may be chosen as an adjustment value that is used to generate a sequence for resetting the circuit design. The adjustment value may be bound by a user-specified maximum value. The user-specified maximum value may constrain logic/physical synthesis transforms and local/global retiming operations. If the counter value for a non-justifiable element is equal to the user-specified maximum value, then all future forward retiming across that element is prevented. If the maximum counter value is less than the user-specified maximum value, the user may optionally shorten the reset sequence.

A process for producing hydrogen

Method and apparatus for improving efficiency of constraint solving

Techniques are presented for identifying blockable subsets. Blockable subsets can increase the efficiency by which solutions to a constraint set representation (CSR) can be found. Nodes of a blockable subset can be marked as “blocked” and learning or implication procedures, used as part of a CSR solving process, can be designed to skip nodes marked as blocked. The identification of a particular blockable subset is typically associated with certain conditions being true. If and when the conditions no longer hold, the nodes of the blockable subset need to be unblocked. One type of blockable subset can be identified during the operation of an implication engine (IE) by a technique called justified node blocking (JNB). Another type of blockable subset can be identified by a technique called pivot node learning (PNL). PNL can be applied in-between application of an IE and application of case-based learning.

Incremental slack margin propagation

Techniques and systems are described for improving the efficiency of timing calculations in numerical sequential cell sizing and for improving the efficiency of incremental slack margin propagation. Some embodiments cache timing-related information associated with a source driver that drives an input of a sequential cell that is being sized, and/or timing-related information for each output of the sequential cell that is being sized. The cached timing-related information for the source driver can be reused when sizing a different sequential cell. The cached timing-related information for the outputs of the sequential cell can be reused when evaluating alternatives for replacing the sequential cell. Some embodiments incrementally propagate slack margins in a lazy fashion (i.e., only when it is necessary to do so for correctness or accuracy reasons) while sizing gates in the circuit design in a reverse-levelized processing order.

Process for the conversion of propane and butane to aromatic hydrocarbons

A process for the conversion of propane and/or butane into aromatics which comprises first reacting a propane and/or butane feed in the presence of an aromatization catalyst under reaction conditions which maximize the conversion of propane and/or butane into first stage aromatic reaction products, separating ethane produced in the first stage reaction from the first stage aromatic reaction products, reacting ethane in the presence of an aromatization catalyst under reaction conditions which maximize the conversion of ethane into second stage aromatic reaction products, and optionally separating ethane from the second stage aromatic reaction products.

High purity, high pressure hydrogen production with in-situ co2 and sulfur capture in a single stage reactor

A process for producing hydrogen is provided. The process comprises the steps of reforming a gaseous hydrocarbon fuel in the presence of CaO and steam to remove CO2, sulfur and halide contaminants in the form of H2S, COS and HX, where X is a halide, in a solid-phase calcium-containing product comprising CaCO3, CaS and CaX2, thereby producing a mixture of CO and hydrogen; separating the solid-phase calcium-containing product from an enriched gaseous hydrogen product; and regenerating the CaO by calcining the solid-phase calcium-containing product at a condition that is: in the presence of steam, in the presence of CO2, in the presence of synthesis gas, in the presence of H2 and O2, under partial vacuum, or a combination thereof.

Process for the conversion of mixed lower alkanes to armoatic hydrocarbons

A process comprising: contacting a lower alkane feed comprising propane and ethane with an aromatization catalyst in a first stage under first stage reaction conditions to produce a first stage product stream comprising ethane and aromatics; separating the aromatics from the first stage product stream to form an aromatics product stream and a second stage feed; and contacting the second stage feed with an aromatization catalyst in a second stage under second stage reaction conditions to produce a second stage product stream comprising ethane and aromatics wherein the amount of ethane in the first stage product stream is equal to from 80 to 300% of the amount of ethane in the lower alkane feed and the amount of ethane in the second stage product stream is equal to at most 80% of the amount of ethane in the second stage feed is described.

A process for producing hydrogen

A process is described for producing hydrogen comprising: producing an aqueous feed stream comprising 5% to 15% wt. ethanol by a biomass fermentation process; separating at least a portion of the water from the feed stream so that the concentration of ethanol in the resulting reformer feed stream is in the range of from 15% to 35% wt.; and contacting the reformer feed stream with a catalyst in a reformer under steam reforming conditions to produce a reformer product stream comprising hydrogen wherein substantially no oxygen is added to the reformer.

Systems, apparatus, and methods for address format detection

Systems, methods, and devices for address format detection are described herein. In one aspect, a method of detecting whether an addressing format is supported by an access point on a wireless network is disclosed. The method includes transmitting a request to an access point using an addressing format including a source address field and a separate transmitter address field. In some aspects, the request may be an address resolution protocol (ARP) request or an Internet Control Message Protocol (ICMP) ping request. The request includes the source address field set to a first address and the transmitter address field set to a second address; monitoring transmissions of the access point to determine whether the access point transmits a response to the request that includes a destination address equal to the first address; and determining whether the access point supports the addressing format based on the monitoring.

Process for the conversion of mixed lower alkanes to armoatic hydrocarbons

A process comprising: contacting a lower alkane feed comprising propane and ethane with an aromatization catalyst in a first stage under first stage reaction conditions to produce a first stage product stream comprising ethane and aromatics; separating the aromatics from the first stage product stream to form an aromatics product stream and a second stage feed; and contacting the second stage feed with an aromatization catalyst in a second stage under second stage reaction conditions to produce a second stage product stream comprising ethane and aromatics wherein the amount of ethane in the first stage product stream is equal to from 80 to 300% of the amount of ethane in the lower alkane feed and the amount of ethane in the second stage product stream is equal to at most 80% of the amount of ethane in the second stage feed is described.

Methods for handling integrated circuit dies with defects

A method of handling integrated circuit dies with defects is provided. After forming a plurality of dies on one or more silicon wafers, test equipment may be used to identify defects on the dies and to create corresponding defect maps. The defect maps can be combined to form an aggregate defect map. Circuit design tools may create keep-out zones from the aggregate defect map and run learning experiments on each die, while respecting the keep-out zones, to compute design metrics. The circuit design tools may further create larger keep-out zones and run additional learning experiments on each die while respecting the larger keep-out zones to compute additional design metrics. The dies can be binned into different Stock Keeping Units (SKUs) based on one or more of the computed design metrics. Circuit design tools automatically respect the keep-out regions for these dies to program them correctly in the field.

Separation of carbon dioxide (co2) from gas mixtures by calcium based reaction separation (cars-co2) process

Carbon dioxide is selectively removed from a gas mixture to provide a gaseous stream depleted in CO sub 2 compared to the inlet stream The CO sub 2 is separated from a gas mixture (e g flue gas/fuel gas) by its reaction with metal oxides (such as calcium oxide) Calcium-based reaction separation for CO sub 2 (CaRS-CO sub 2) consists of contacting a CO sub 2 laden gas with calcium oxide (CaO) in a reactor such that CaO captures the CO sub 2 by the formation of calcium carbonate (CaCO sub 3) Once "spent", CaCO sub 3 is regenerated by its calcination leading to the formation of fresh CaO sorbent and the evolution of a concentrated stream of CO sub 2 The "regenerated" CaO is then recycled for the further capture of more CO sub 2 A mesoporous CaCO sub 3 structure that attains >90% conversion over multiple carbonation and calcination cycles is identified Thermal regeneration (calcination) under vacuum proves a sorbent structure that maintains reproducible reactivity levels over multiple cycles

Temperature Control Systems And Methods For Integrated Circuits

An integrated circuit system includes a temperature sensor circuit that generates an output indicative of a temperature in an integrated circuit. The integrated circuit system also includes a temperature management controller circuit that compares the temperature indicated by the output of the temperature sensor circuit to a temperature threshold. The integrated circuit system further includes temperature reduction circuitry and/or design compilation techniques and partial or full reconfiguration that controls the temperature in the integrated circuit system. The temperature management controller circuit causes the temperature reduction circuitry to reduce the temperature in response to the temperature indicated by the output of the temperature sensor circuit exceeding the temperature threshold. The temperature sensor circuit, the temperature management controller circuit, and the temperature reduction circuitry may be implemented by soft logic circuits, hard logic circuits, or any combination thereof.

Separation of carbon dioxide (co2) from gas mixtures by calcium based reaction separation (cars-co2) process

Carbon dioxide is selectively removed from a gas mixture to provide a gaseous stream depleted in CO sub 2 compared to the inlet stream The CO sub 2 is separated from a gas mixture (e g flue gas/fuel gas) by its reaction with metal oxides (such as calcium oxide) Calcium-based reaction separation for CO sub 2 (CaRS-CO sub 2) consists of contacting a CO sub 2 laden gas with calcium oxide (CaO) in a reactor such that CaO captures the CO sub 2 by the formation of calcium carbonate (CaCO sub 3) Once "spent", CaCO sub 3 is regenerated by its calcination leading to the formation of fresh CaO sorbent and the evolution of a concentrated stream of CO sub 2 The "regenerated" CaO is then recycled for the further capture of more CO sub 2 A mesoporous CaCO sub 3 structure that attains >90% conversion over multiple carbonation and calcination cycles is identified Thermal regeneration (calcination) under vacuum proves a sorbent structure that maintains reproducible reactivity levels over multiple cycles

On-Die Aging Measurements for Dynamic Timing Modeling

A method includes mapping an aging measurement circuit (AMC) into the core fabric of an FPGA and operating the AMC for a select time period. During the select period of time, the AMC counts transition of a signal propagating through the AMC. Timing information based on the counted transitions is stored in a timing model in a memory. The timing information represents an aging characteristic of the core fabric at a time that the AMC is operated. An EDA toolchain uses the timing information in the timing model to generate a timing guard-band for the configurable IC die. The AMC is removed from the core fabric and another circuit device is mapped and fitted into the core fabric using the generated timing guard-band models. The circuit device is operated in the configurable IC die based on the timing guard-band models.

Separation of carbon dioxide (co2) from gas mixtures by calcium based reaction separation (cars-co2) process

A reaction-based process has been developed for the selective removal of carbon dioxide (CO2) from a multicomponent gas mixture to provide a gaseous stream depleted in CO2 compared to the inlet CO2 concentration in the stream. The proposed process effects the separation of CO2 from a mixture of gases (such as flue gas/fuel gas) by its reaction with metal oxides (such as calcium oxide). The Calcium based Reaction Separation for CO2 (CaRS-CO2) process consists of contacting a CO2 laden gas with calcium oxide (CaO) in a reactor such that CaO captures the CO2 by the formation of calcium carbonate (CaCOa). Once "spent", CaCO3 is regenerated by its calcination leading to the formation of fresh CaO sorbent and the evolution of a concentrated stream of CO2. The "regenerated" CaO is then recycled for the further capture of more CO2. This carbonation-calcination cycle forms the basis of the CaRS-CO2 process. This process also identifies the application of a mesoporous CaCO3 structure, developed by a process detailed elsewhere, that attains >90% conversion over multiple carbonation and calcination cycles. Lastly, thermal regeneration (calcination) under vacuum provided a better sorbent structure that maintained reproducible reactivity levels over multiple cycles.

Three dimensional circuit systems and methods having memory hierarchies

A three dimensional circuit system includes a first integrated circuit die having a core logic region that has first memory circuits and logic circuits. The three dimensional circuit system includes a second integrated circuit die that has second memory circuits. The first and second integrated circuit dies are coupled together in a vertically stacked configuration. The three dimensional circuit system includes third memory circuits coupled to the first integrated circuit die. The third memory circuits reside in a plane of the first integrated circuit die. The logic circuits are coupled to access the first, second, and third memory circuits and data can move between the first, second, and third memories. The third memory circuits have a larger memory capacity and a smaller memory access bandwidth than the second memory circuits. The second memory circuits have a larger memory capacity and a smaller memory access bandwidth than the first memory circuits.

Methods and apparatus to insert buffers in a dataflow graph