Multi-output phase detector

Representative implementations of devices and techniques provide a multi-bit binary representation of a phase difference between two signals. The multi-bit binary representation may include information regarding a sign of the phase difference and a magnitude of the phase difference.

Delay stage, ring oscillator, PLL-circuit and method

The invention discloses a delay stage, a ring oscillator, a PLL-circuit and a method. The delay stage used for semiconductor pieces comprises at least one delay branch and at least one controllable switch device. The at least one controllable switch device connects at least one delay branch of predetermined number to a power supply voltage.

Oscillator circuit

The invention relates to an oscillator circuit, concretely, devices are provided comprising oscillator circuits coupled to a supply voltage via an adjustable resistance. Corresponding methods to control adjustable resistances are also provided.

CIRCUIT WITH NOISE SHAPER

In an embodiment, a circuit comprising an oscillator is provided. The oscillator is controlled based on a feedback value and an input reference value. The feedback value or the reference value or both are generated using noise shaping. 1. A circuit , comprising:an oscillator configured to generate an output signal having a frequency,a feedback value generator coupled to said oscillator configured to generate a feedback value depending on said output signal,a reference value generator comprising a noise shaper circuit configured to generate a noise shaped reference value depending on a predetermined value,a combiner configured to combine said noise shaped reference value and said feedback value and to output a combined signal, anda loop filter configured to generate a control signal to control said oscillator based on said combined signal,wherein said reference value generator is further configured to generate said noise shaped reference value independent of signal values in a path from said combiner to said oscillator via said loop filter and independent of signal values in a path from said oscillator to said combiner via said feedback value generator.2. The circuit of claim 1 ,wherein said predetermined value determines a relationship between a frequency of a reference clock and said frequency of said output signal.3. The circuit of claim 1 ,wherein said predetermined value comprises at least one first value and at least one second value,wherein said reference value comprises at least one first reference value and at least one second reference value,wherein said reference value generator is configured to generate said first reference value depending on said first value without using said noise shaper circuit and to generate said second reference value depending on said at least one second value using said noise shaper circuit.4. The circuit of claim 1 ,wherein said loop filter comprises a modulator configured to modulate said control signal based on said output ...

Polar Transmitter Suitable for Monolithic Integration in SoCs

The disclosed polar modulation transmitter circuit is configured to generate an output signal having a transmission frequency that minimizes crosstalk effects between different transmission bands (e.g., Bluetooth, GSM, UMTS, etc.). In particular, a polar modulation transceiver circuit, having an amplitude modulated (AM) signal and a phase modulated (PM) signal, comprises a digitally controlled oscillator (DCO) configured to generate a DCO signal having a DCO frequency. The DCO signal is provided to one or more frequency dividers that are configured to selectively divide the DCO signal to generate various lower frequency signals, used to select a sampling rate for a DAC operating on the AM signal and an RF carrier signal frequency, which result in an output signal having a frequency that does not interfere with other RF systems on the same IC (e.g., that falls outside of the downlink frequency of other RF systems). Other systems and methods are also disclosed. 1. A transmission circuit configured to transmit over a plurality of transmission signal bands , comprising:a digitally controlled oscillator (DCO) configured to generate a DCO signal having a DCO frequency;one or more frequency dividers configured to selectively generate one or more reduced frequency signals by selectively dividing the DCO signal;a clock selection circuit configured to receive one of the reduced frequency signals and based thereupon to generate a sampling frequency;a digital to analog converter (DAC) configured to sample a digital amplitude modulated signal at the sampling frequency to generate an analog amplitude modulated signal; anda mixer configured to combine the analog amplitude modulated signal and a phase modulated carrier signal to generate an output signal having a frequency that is outside of the downlink frequencies of other signals within the plurality of transmission signal bands.2. The circuit of claim 1 , wherein the one or more frequency dividers comprise a first frequency ...

DIGITAL PLL WITH AUTOMATIC CLOCK ALIGNMENT

One embodiment of the present invention relates to a digital phase locked loop (ADPLL) configured to generate a plurality of time-aligned output clock signals having different frequency values. The ADPLL comprises a digital controlled oscillator configured to generate a variable clock signal that is separated into two signal paths operating according to two separate clock domains. A first signal path is configured to generate a feedback signal that synchronizes the variable clock signal with a reference signal. A second signal path comprises a clock divider circuit configured to synchronously divide the variable clock signal to automatically generate a plurality of time-aligned output clock signals having different frequencies. A clock aligner monitors a phase difference between the variable clock signal and one of the plurality of time-aligned output clock signals and generates a control signal that causes a programmable delay line to automatically time-align the output clock signals with the variable clock signal. 1. A phase locked loop , comprising:a digitally controlled oscillator configured to generate a variable clock signal;a first signal path comprising a first clock signal operating within a first clock domain having a first frequency range, the first signal path comprising a time-to-digital converter configured to generate a PLL feedback signal that drives the variable clock signal to follow a reference signal;a second signal path having a second clock signal operating within a second clock domain having a second frequency range, the second signal path comprising a clock divider circuit configured to generate a plurality of automatically time-aligned output clock signals from the second clock signal, respectively having different frequencies; anda clock aligner configured to generate a control signal based upon a detected phase difference between the variable clock signal and one of the plurality of time-aligned output clock signals, and used to ...

Oscillator Circuit

Devices are provided comprising oscillator circuits coupled to a supply voltage via an adjustable resistance. Corresponding methods to control adjustable resistances are also provided.

Split Varactor Array with Improved Matching and Varactor Switching Scheme

One embodiment of the present invention relates to a digital controlled oscillator. The oscillator includes an oscillator circuit, a varactor array, and a control circuit. The oscillator circuit receives a control word and a signal and generates an oscillator clock signal from the signal at a frequency selected by the control word. The varactor array has a first array of varactor cells having incremental capacitance values and a second array of varactor cells having equal capacitance values. The split varactor array provides a capacitance value. A control circuit is coupled to the oscillator circuit and controls the split varactor array according to the control word. The control circuit sets varactor cells of the split varactor array on or off. 1. A digital controlled oscillator , comprising:an oscillator circuit configured to receive a control word and configured to generate an oscillator clock signal at a frequency selected by the control word;a varactor array having a first array of varactor cells having incremental capacitance values; anda control circuit coupled to the oscillator circuit configured to control the varactor array according to the control word.2. The oscillator of claim 1 , wherein the varactor array further comprises a second array of equal capacitance values.3. The oscillator of claim 1 , further comprising a coupling network to couple an output of the varactor array to an output of the oscillator circuit.4. The oscillator of claim 1 , wherein the control word is time varying digital information.5. The oscillator of claim 1 , wherein the oscillator clock signal is configured to have a specified step size.6. The oscillator of claim 5 , wherein a lowest bit of the control word corresponds to the specified step size.7. The oscillator of claim 1 , wherein the first array comprises a number of cells ranging from one to a selected number claim 1 , and wherein the size of each cell ranges from unity to unity multiplied by the selected number.8. The ...

MULTI-OUTPUT PHASE DETECTOR

Representative implementations of devices and techniques provide a multi-bit binary representation of a phase difference between two signals. The multi-bit binary representation may include information regarding a sign of the phase difference and a magnitude of the phase difference. 1. A device , comprising:a plurality of delay components coupled to a first input of the device; anda plurality of logic components coupled to the plurality of delay components and coupled to a second input of the device, the plurality of logic components having a plurality of outputs arranged to output a multi-bit binary representation of a phase difference between a signal at the first input of the device and another signal at the second input of the device.2. The device of claim 1 , wherein the delay components are arranged in series claim 1 , and delay values of each of the delay components are substantially equal.3. The device of claim 2 , wherein the binary representation of the phase difference is at least in part a result of summing the delay values of a quantity of the delay components claim 2 , the quantity of the delay components summed being proportional to a magnitude of the phase difference.4. The device of claim 3 , wherein the delay components comprise CMOS buffers with substantially equal capacitive loads.5. The device of claim 1 , wherein the delay components are arranged in parallel claim 1 , and delay values of each of the delay components are substantially different from each other.6. The device of claim 5 , wherein the binary representation of the phase difference is a result of a comparison of the phase difference to a delay value of one or more of the delay components.7. The device of claim 5 , wherein the delay components comprise CMOS buffers with different capacitive loads.8. The device of claim 1 , wherein one or more of the delay components have a delay value that is programmable and/or adjustable.9. The device of claim 1 , wherein each of the plurality of ...

POLAR TRANSMITTER SUITABLE FOR MONOLITHIC INTEGRATION IN SoCs

The disclosed polar modulation transmitter circuit is configured to generate an output signal having a transmission frequency that minimizes crosstalk effects between different transmission bands (e.g., Bluetooth, GSM, UMTS, etc.). In particular, a polar modulation transceiver circuit, having an amplitude modulated (AM) signal and a phase modulated (PM) signal, comprises a digitally controlled oscillator (DCO) configured to generate a DCO signal having a DCO frequency. The DCO signal is provided to one or more frequency dividers that are configured to selectively divide the DCO signal to generate various lower frequency signals, used to select a sampling rate for a DAC operating on the AM signal and an RF carrier signal frequency, which result in an output signal having a frequency that does not interfere with other RF systems on the same IC (e.g., that falls outside of the downlink frequency of other RF systems). Other systems and methods are also disclosed. 1. A transmission circuit configured to transmit over a plurality of transmission signal bands , comprising:a polar converter configured modulate an amplitude of an input signal to generate an amplitude modulated signal and to modulate a phase of the input signal to generate a phase modulated signal;a digitally controlled oscillator (DCO) configured to generate a DCO signal having a DCO frequency that depends upon the phase modulated signal;one or more frequency dividers configured to selectively generate one or more reduced frequency signals by selectively dividing the DCO signal, wherein one of the reduced frequency signals comprises a phase modulated carrier signal;a clock selection circuit configured to receive one of the reduced frequency signals and based thereupon to generate a sampling frequency;a digital to analog converter (DAC) configured to receive the sampling frequency from the clock selection circuit and to sample a digital amplitude modulated signal at the sampling frequency to generate an ...

MULTI-OUTPUT PHASE DETECTOR

Representative implementations of devices and techniques provide a multi-bit binary representation of a phase difference between two signals. The multi-bit binary representation may include information regarding a sign of the phase difference and a magnitude of the phase difference. 1. A system , comprising:a digitally-controlled oscillator (DCO), arranged to produce an output signal having a frequency proportional to a value of a digital control word;a feedback divider arranged to provide a modified clock signal based on the output signal;a multi-output phase detector arranged to sense a phase difference between a reference clock signal and the modified clock signal and to output a multi-bit representation of the phase difference; anda digital loop filter arranged to form the digital control word based on the multi-bit representation.2. The system of claim 1 , wherein the multi-output phase detector is arranged to detect whether and to what extent a phase of the reference clock signal leads or lags a phase of the modified clock signal.3. The system of claim 1 , wherein the multi-bit representation comprises a binary word of predetermined length and includes information about a polarity of the phase difference and a magnitude of the phase difference.4. A method claim 1 , comprising:receiving a clock signal;receiving a reference clock signal;sensing a phase difference between the reference clock signal and the clock signal;determining a sign and a magnitude of the phase difference;outputting a multi-bit binary representation of the phase difference.5. The method of claim 4 , further comprising determining whether and to what extent the reference clock signal leads or lags the clock signal.6. The method of claim 4 , further comprising comparing the phase difference to a delay value of one or more delay components claim 4 , the one or more delay components representing a predetermined phase-mismatch range.7. The method of claim 6 , further comprising outputting the ...

Analog-to-digital conversion

A circuit having an array of Analog-to-Digital Converters (ADCs); a sampling order selector configured to select a sampling order of the ADCs and output corresponding sampling order control words; sampling pulse generators coupled between the sampling order selector and the respective ADCs, and configured to output respective sampling pulses based on the respective sampling order control words, wherein the ADCs are configured to sample and convert analog data into digital data in response to the sampling pulses; and a single clock generator configured to distribute a delay-matched clock to each of the ADCs in parallel, to each of the sampling pulse generators in parallel, and to the sampling order selector.

Circuit with noise shaper

In an embodiment, a circuit comprising an oscillator is provided. The oscillator is controlled based on a feedback value and an input reference value. The feedback value or the reference value or both are generated using noise shaping.

Method and device for extracting a clock pulse frequency underlying a data flow

The invention relates to a device for extracting a clock pulse frequency underlying a data flow, said device comprising a unit (11) for controlling a controllable oscillator, a coarse-tuning unit (13), and a fine-tuning unit (14). The coarse-tuning unit (13) responds to a second data pattern present in the data flow and coarsely adjusts the oscillator (10) on the basis of the length of said data pattern. The fine tuning unit (14) responds to temporally successive first data patterns which are present in the data flow with higher precision, in order to finely tune the oscillator (10) on the basis of the period of time between the two first data patterns and on the basis of the number of clock pulse cycles of the controllable oscillator (10) which occur during said period of time. In this way, a timing recovery can be achieved in a rapid and easy-to-implement manner, without oscillator quartz or resonators, especially suitable for USB applications and especially for chip cards for USB applications.

Method and device for extracting a clock frequency on which a data stream is based

Eine Vorrichtung zum Extrahieren einer einem Datenstrom zugrundeliegenden Taktfrequenz umfaßt eine Einrichtung (11) zum Steuern eines steuerbaren Oszillators, eine Grobabstimmungseinrichtung (13) und eine Feinabstimmungseinrichtung (14), wobei die Grobabstimmungseinrichtung (13) auf ein in dem Datenstrom vorhandenes zweites Datenmuster anspricht und aufgrund deren Länge den Oszillator (10) grob einstellt. Die Feinabstimmungseinrichtung (14) spricht auf zeitlich aufeinanderfolgende erste Datenmuster an, die mit einer höheren Genauigkeit im Datenstrom vorhanden sind, um auf der Bais der zeitlichen Länge zwischen den beiden ersten Datenmustern und auf der Basis der Anzahl von Taktzyklen des steuerbaren Oszillators (10), die in dieser zeitlichen Länge auftreten, eine Feinabstimmung des Oszillators (10) durchzuführen. Damit kann schnell und implementierungsmäßig einfach eine Taktwiedergewinnung ohne Schwingquarze oder Resonatoren erreicht werden, die besonders für USB-Anwendungen und insbesondere für Chipkarten für USB-Anwendungen geeignet sind. A device for extracting a clock frequency on which a data stream is based comprises a device (11) for controlling a controllable oscillator, a coarse tuning device (13) and a fine tuning device (14), the coarse tuning device (13) responding to and based on a second data pattern present in the data stream whose length roughly adjusts the oscillator (10). The fine-tuning device (14) responds to temporally successive first data patterns which are present with a higher accuracy in the data stream, in order to base the time length between the two first data patterns and on the basis of the number of clock cycles of the controllable oscillator (10), that occur in this length of time to fine-tune the oscillator (10). In this way, clock recovery can be achieved quickly and in terms of implementation without oscillating crystals or resonators, which are particularly suitable for USB applications and in particular for chip cards for USB ...

Digitally controllable oscillator

A digitally controllable oscillator includes an oscillation generation means and an oscillator control, wherein the oscillator control comprises two digital/analog converters whose output signals are combined by a combiner in order to generate an analog input signal into the oscillation generation means. The second digital/analog converter is implemented in order to provide, in response to a digital increment in its digital input signal, a difference in the output signal of the second digital/analog converter which is smaller than a difference in the output signal of the first digital/analog converter when the first digital/analog converter is pulsed with the digital increment in its digital input signal.

Signed-RFDAC architectures enabling wideband and efficient 5G transmitters

A radio frequency digital-to-analog converter (RFDAC) circuit includes an RFDAC array circuit including an array of cells arranged into a plurality of segments. Each segment of the plurality of segments is configured to process input data signals. The RFDAC array circuit is configured to process an input data based on activating a set of segments of the plurality of segments, forming a set of active segments, and when the sign of the input data is changed, deactivate a partially active segment of the set of active segments and activate a sign change segment within the RFDAC array circuit. The sign change segment includes a segment within the plurality of segments of the RFDAC array circuit that is different from the set of active segments.

Variable capacitance unit

Implementations of differential variable capacitance systems are disclosed.

Digitally controllable oscillator

The invention relates to a digitally controllable oscillator comprising an oscillation generating device (10) and an oscillator control system (11). Said oscillator control system comprises two digital/analog converters (54, 55), the output signals (502, 504) thereof being combined by a combiner (52) in order to produce an analog input signal in the oscillation generating device (10). The second digital/analog converter is embodied in such a way as to supply a difference in the output signal (504) of the second digital/analog converter in response to a digital increment in the digital input signal (505) thereof, said difference being smaller than a difference in the output signal of the first digital/analog converter when the first digital/analog converter is supplied with the digital increment in the digital input signal (503) thereof. The control of the digitally controllable oscillator is flexible both in terms of the maximum control range and in terms of the smallest frequency increment that can be produced.

Analog-to-digital conversion

A circuit having an array of Analog-to-Digital Converters (ADCs); a sampling order selector configured to select a sampling order of the ADCs and output corresponding sampling order control words; sampling pulse generators coupled between the sampling order selector and the respective ADCs, and configured to output respective sampling pulses based on the respective sampling order control words, wherein the ADCs are configured to sample and convert analog data into digital data in response to the sampling pulses; and a single clock generator configured to distribute a delay-matched clock to each of the ADCs in parallel, to each of the sampling pulse generators in parallel, and to the sampling order selector.

Frequency synthesizer and method for generating an rf clock signal

A frequency synthesizer and a method for generating an RF clock signal. A system includes a plurality of transceivers. Each transceiver includes a digital-to-analog converter, an analog-to-digital converter, and a frequency synthesizer. A frequency synthesizer in each transceiver receives a first reference clock signal and a second, different, reference clock signal. The frequency synthesizer includes a digitally-controlled oscillator (DCO), a feedback loop circuitry, a phase alignment and clock generation circuitry. The DCO generates an RF clock signal that is synchronized with the first reference clock signal. The phase alignment and clock generation circuitry aligns the phase of the RF clock signal with a phase of the second reference clock signal. The second reference clock signal is a system-wide reference clock signal for the plurality of transceivers.

Analog-to-digital conversion

A circuit having an array of Analog-to-Digital Converters (ADCs); a sampling order selector configured to select a sampling order of the ADCs and output corresponding sampling order control words; sampling pulse generators coupled between the sampling order selector and the respective ADCs, and configured to output respective sampling pulses based on the respective sampling order control words, wherein the ADCs are configured to sample and convert analog data into digital data in response to the sampling pulses; and a single clock generator configured to distribute a delay-matched clock to each of the ADCs in parallel, to each of the sampling pulse generators in parallel, and to the sampling order selector.

Method and system for clock distribution for multi-device synchronization

A method and system for clock distribution for multi-device synchronization. The system may include a plurality of transceiver devices that are coupled in a daisy chain. A phase-locked loop, PLL, reference clock signal and an external system reference clock signal are supplied to a first transceiver device in the daisy chain. The first transceiver device sends a first system reference clock signal in a forward direction on the daisy chain based on the external system reference clock signal and a last transceiver device in the daisy chain sends a second system reference clock signal in a reverse direction on the daisy chain in response to reception of the first system reference clock signal. Each transceiver device measures transition times of the first and second system reference clock signals, computes an average transition time, and generates a radio frequency clock signal based on the average transition time.

System and method for testing a phase noise or jitter of a phase-locked loop

A system and method for testing or determining a phase noise and/or jitter of a phase locked loop (PLL). The system includes a first PLL configured to generate a first clock signal based on a reference clock signal, a first buffer for providing the reference clock signal to the first PLL, a mixer configured to mix the first clock signal with a second clock signal, an analog-to-digital converter (ADC) configured to convert an output of the mixer to digital data, and a processing circuit configured to process the digital data to determine a phase noise or jitter of the first PLL and generate an output indicative of the phase noise or jitter of the first PLL. The system may include a second PLL configured to generate the second clock signal based on the reference clock signal, and a second buffer for providing the reference clock signal to the second PLL.

Multi-device system and method for phase alignment of devices in the multi-device system

A multi-device system and a method for phase alignment of multiple devices in a multi-device system. The system includes a plurality of devices, a plurality of clock dividers, and a delay circuit. The plurality of devices are configured to operate based on a first clock signal. The clock dividers are configured to generate a second clock signal from the first clock signal and provide the second clock signal to the devices. The delay circuit is configured to incur a specific delay to the second clock signal provided to the devices such that a phase of the second clock signal provided to the devices is spread over time. Each of the clock dividers may be reset based on a reference clock signal provided to each clock divider, and the delay circuit may incur the specific delay on the reference clock signal provided to each clock divider.

Chip-to-chip interface of a multi-chip module (mcm)

Split varactor array with improved matching and varactor switching scheme

One embodiment of the present invention relates to a digital controlled oscillator. The oscillator includes an oscillator circuit, a varactor array, and a control circuit. The oscillator circuit receives a control word and a signal and generates an oscillator clock signal from the signal at a frequency selected by the control word. The varactor array has a first array of varactor cells having incremental capacitance values and a second array of varactor cells having equal capacitance values. The split varactor array provides a capacitance value. A control circuit is coupled to the oscillator circuit and controls the split varactor array according to the control word. The control circuit sets varactor cells of the split varactor array on or off.