Efficient implementation of arrays of structures on simt and simd architectures

One embodiment of the present invention sets forth a technique providing an optimized way to allocate and access memory across a plurality of thread/data lanes. Specifically, the device driver receives an instruction targeted to a memory set up as an array of structures of arrays. The device driver computes an address within the memory using information about the number of thread/data lanes and parameters from the instruction itself. The result is a memory allocation and access approach where the device driver properly computes the target address in the memory. Advantageously, processing efficiency is improved where memory in a parallel processing subsystem is internally stored and accessed as an array of structures of arrays, proportional to the SIMT/SIMD group width (the number of threads or lanes per execution group).

Programmable graphics processor for multithreaded execution of programs

A processing unit includes multiple execution pipelines, each of which is coupled to a first input section for receiving input data for pixel processing and a second input section for receiving input data for vertex processing and to a first output section for storing processed pixel data and a second output section for storing processed vertex data. The processed vertex data is rasterized and scan converted into pixel data that is used as the input data for pixel processing. The processed pixel data is output to a raster analyzer.

INDIRECT FUNCTION CALL INSTRUCTIONS IN A SYNCHRONOUS PARALLEL THREAD PROCESSOR

An indirect branch instruction takes an address register as an argument in order to provide indirect function call capability for single-instruction multiple-thread (SIMT) processor architectures. The indirect branch instruction is used to implement indirect function calls, virtual function calls, and switch statements to improve processing performance compared with using sequential chains of tests and branches. 1. A system for executing indirect function calls for synchronous parallel processing threads , the system comprising:an execution stack configured to store thread state information for a number of threads that are concurrently executed by the system; receive program instructions including control instructions;', 'execute the control instructions by pushing and popping the thread state information;', 'maintain an active mask that indicates active threads in a thread group that should be processed in parallel; and', 'serialize execution of a plurality of indirect function calls for each unique pointer within a set of pointers that corresponds to any of the active threads; and, 'a controller that is coupled to the execution stack and configured tomultiple processing engines that are configured to receive the program instructions and execute each program instruction in parallel for the threads in the thread group that should be processed in parallel according to the active mask.2. The system of claim 1 , wherein the controller is further configured to:receive a first control instruction that references the set of pointers to one or more functions in a program, each pointer in the set of pointers specifying an address of a corresponding function in the one or more functions;determine if two pointers in the set of pointers corresponding to active threads in the thread group are different, indicating that the active threads diverge during execution of the indirect function calls;push a first token onto the execution stack when the active threads diverge, the token ...

COOPERATIVE THREAD ARRAY REDUCTION AND SCAN OPERATIONS

One embodiment of the present invention sets forth a technique for performing aggregation operations across multiple threads that execute independently. Aggregation is specified as part of a barrier synchronization or barrier arrival instruction, where in addition to performing the barrier synchronization or arrival, the instruction aggregates (using reduction or scan operations) values supplied by each thread. When a thread executes the barrier aggregation instruction the thread contributes to a scan or reduction result, and waits to execute any more instructions until after all of the threads have executed the barrier aggregation instruction. A reduction result is communicated to each thread after all of the threads have executed the barrier aggregation instruction and a scan result is communicated to each thread as the barrier aggregation instruction is executed by the thread. 1. A method for performing a scan operation across multiple threads , the method comprising:receiving a barrier instruction that specifies the scan operation for execution by a first thread of the multiple threads;combining a value associated with the first thread with an scan result for the multiple threads;communicating the scan result to the first thread; andcausing another instruction to be executed without waiting until the barrier instruction is received by a second thread of the multiple threads.2. The method of claim 1 , further comprising the steps of:determining that the second thread is the last thread of the multiple threads to receive the barrier instruction; andinitializing the scan result.3. The method of claim 1 , wherein the communication of the scan result to the first thread occurs before the value associated with the first thread is combined with the scan result.4. The method of claim 1 , wherein the communication of the scan result to the first thread occurs after the value associated with the first thread is combined with the scan result.5. The method of claim 1 , ...

PROGRAMMABLE GRAPHICS PROCESSOR FOR MULTITHREADED EXECUTION OF PROGRAMS

A processing unit includes multiple execution pipelines, each of which is coupled to a first input section for receiving input data for pixel processing and a second input section for receiving input data for vertex processing and to a first output section for storing processed pixel data and a second output section for storing processed vertex data. The processed vertex data is rasterized and scan converted into pixel data that is used as the input data for pixel processing. The processed pixel data is output to a raster analyzer. 1. A system , comprising:a processor unit; and 'execution pipeline that is configured to execute a plurality of threads to process vertex data and to execute a plurality of threads to process fragment data.', 'a graphics processing unit that includes at least one'}2. The system of claim 1 , further comprising a memory that stores vertex program instructions that are executed by two or more threads in the at least one execution pipeline.3. The system of claim 2 , wherein the memory further stores fragment program instructions that are executed by two or more threads in the at least one execution pipeline.4. The system of claim 2 , wherein the graphics processing unit further includes a texture unit configured to read texture maps from the memory.5. The system of claim 1 , wherein claim 1 , during a first pass through the at least one execution pipeline claim 1 , a first plurality of threads is configured to perform vertex processing operations on vertex data.6. The system of claim 1 , wherein claim 1 , during a second pass through the at least one execution pipeline claim 1 , a second plurality of threads is configured to perform fragment processing operations on fragment data.7. The system of claim 1 , wherein the graphics processing unit further includes a raster unit configured to output fragment data and to perform scan conversion operations.8. The system of claim 1 , wherein the graphics processing unit further includes a raster ...

INSTRUCTIONS FOR MANAGING A PARALLEL CACHE HIERARCHY

A technique for managing a parallel cache hierarchy that includes receiving an instruction from a scheduler unit, where the instruction comprises a load instruction or a store instruction; determining that the instruction includes a cache operations modifier that identifies a policy for caching data associated with the instruction at one or more levels of the parallel cache hierarchy; and executing the instruction and caching the data associated with the instruction based on the cache operations modifier. 1. A method , comprising:receiving an instruction from a scheduler unit, wherein the instruction comprises a load instruction or a store instruction and is associated with an address that identifies a memory region;determining that the instruction includes a cache operations modifier that identifies a policy for caching data associated with the instruction at one or more levels of a parallel cache hierarchy; andexecuting the instruction and caching the data associated with the instruction in accordance with the policy identified by the cache operations modifier.2. The method of claim 1 , wherein the parallel cache hierarchy includes an L1 cache level and an L2 cache level3. The method of claim 2 , wherein each L1 cache included in the L1 cache level is associated with a different processing core included in a processor claim 2 , and the L2 cache level includes at least one L2 cache that each processing core is configured to access.4. A system claim 2 , comprising:a memory; and receives an instruction from a scheduler unit, wherein the instruction comprises a load instruction or a store instruction and is associated with an address that identifies a memory region,', 'determines that the instruction includes a cache operations modifier that identifies a policy for caching data associated with the instruction at one or more levels of a parallel cache hierarchy; and', 'executes the instruction and caching the data associated with the instruction in accordance with the ...

PROGRAMMABLE GRAPHICS PROCESSOR FOR MULTITHREADED EXECUTION OF PROGRAMS

A processing unit includes multiple execution pipelines, each of which is coupled to a first input section for receiving input data for pixel processing and a second input section for receiving input data for vertex processing and to a first output section for storing processed pixel data and a second output section for storing processed vertex data. The processed vertex data is rasterized and scan converted into pixel data that is used as the input data for pixel processing. The processed pixel data is output to a raster analyzer. 1. A system , comprising:a first processor; anda graphics processing unit that includes at least one execution pipeline, wherein the at least one execution pipeline executes a plurality of threads to process vertex data and executes a plurality of threads to process fragment data, and wherein the at least one execution pipeline is programmable to process vertex data as well as fragment data.2. The system of claim 1 , further comprising a memory that stores vertex program instructions that are executed by two or more threads in the at least one execution pipeline.3. The system of claim 2 , wherein the memory further stores fragment program instructions that are executed by two or more threads in the at least one execution pipeline.4. The system of claim 2 , wherein the graphics processing unit further includes a texture unit that reads texture maps from the memory.5. The system of claim 1 , wherein claim 1 , during a first pass through the at least one execution pipeline claim 1 , a first plurality of threads performs vertex processing operations on vertex data.6. The system of claim 5 , wherein claim 5 , during a subsequent pass through the at least one execution pipeline claim 5 , a second plurality of threads performs fragment processing operations on fragment data.7. The system of claim 1 , wherein the graphics processing unit further includes a rasterizer that outputs fragment data and performs scan conversion operations.8. The system ...

PROGRAMMABLE GRAPHICS PROCESSOR FOR MULTITHREADED EXECUTION OF PROGRAMS

A processing unit includes multiple execution pipelines, each of which is coupled to a first input section for receiving input data for pixel processing and a second input section for receiving input data for vertex processing and to a first output section for storing processed pixel data and a second output section for storing processed vertex data. The processed vertex data is rasterized and scan converted into pixel data that is used as the input data for pixel processing. The processed pixel data is output to a raster analyzer. 1. A system , comprising:a processor unit; and 'execution pipeline that is configured to execute a plurality of threads to process vertex data and to execute a plurality of threads to process fragment data.', 'a graphics processing unit that includes at least one'}2. The system of claim 1 , further comprising a memory that stores vertex program instructions that are executed by two or more threads in the at least one execution pipeline.3. The system of claim 2 , wherein the memory further stores fragment program instructions that are executed by two or more threads in the at least one execution pipeline.4. The system of claim 2 , wherein the graphics processing unit further includes a texture unit configured to read texture maps from the memory.5. The system of claim 1 , wherein claim 1 , during a first pass through the at least one execution pipeline claim 1 , a first plurality of threads is configured to perform vertex processing operations on vertex data.6. The system of claim 1 , wherein claim 1 , during a second pass through the at least one execution pipeline claim 1 , a second plurality of threads is configured to perform fragment processing operations on fragment data.7. The system of claim 1 , wherein the graphics processing unit further includes a raster unit configured to output fragment data and to perform scan conversion operations.8. The system of claim 1 , wherein the graphics processing unit further includes a raster ...

COOPERATIVE THREAD ARRAY REDUCTION AND SCAN OPERATIONS

One embodiment of the present invention sets forth a technique for performing aggregation operations across multiple threads that execute independently. Aggregation is specified as part of a barrier synchronization or barrier arrival instruction, where in addition to performing the barrier synchronization or arrival, the instruction aggregates (using reduction or scan operations) values supplied by each thread. When a thread executes the barrier aggregation instruction the thread contributes to a scan or reduction result, and waits to execute any more instructions until after all of the threads have executed the barrier aggregation instruction. A reduction result is communicated to each thread after all of the threads have executed the barrier aggregation instruction and a scan result is communicated to each thread as the barrier aggregation instruction is executed by the thread. 1. A subsystem for performing an aggregation operation across multiple threads , the subsystem comprising: receive a barrier aggregation instruction that specifies the aggregation operation for execution by a first thread of the multiple threads;', 'generate an aggregation result based on the aggregation operation;', 'communicate the aggregation result to each thread of the multiple threads; and', 'waiting until each of the multiple threads has received the barrier aggregation instruction before any additional instructions are executed., 'a barrier instruction execution unit that is configured to2. The subsystem of claim 1 , wherein the barrier aggregation instruction specifies a number of the multiple threads that are synchronized by the barrier aggregation instruction.3. The subsystem of claim 2 , wherein each of the threads has received the barrier aggregation instruction when a count equals the number of the multiple threads specified by the barrier aggregation instruction.4. The subsystem of claim 1 , wherein the first thread is included in a first thread group claim 1 , and the ...

Structured programming control flow in a SIMD architecture

One embodiment of a computing system configured to manage divergent threads in a SIMD thread group includes a stack configured to store state information for processing control instructions. A parallel processing unit is configured to perform the steps of determining if one or more threads diverge during execution of a conditional control instruction. A disable mask allows for the use of conditional return and break instructions in a multithreaded SIMD architecture. Additional control instructions are used to set up thread processing target addresses for synchronization, breaks, and returns.

Lock mechanism to enable atomic updates to shared memory

A system and method for locking and unlocking access to a shared memory for atomic operations provides immediate feedback indicating whether or not the lock was successful. Read data is returned to the requestor with the lock status. The lock status may be changed concurrently when locking during a read or unlocking during a write. Therefore, it is not necessary to check the lock status as a separate transaction prior to or during a read-modify-write operation. Additionally, a lock or unlock may be explicitly specified for each atomic memory operation. Therefore, lock operations are not performed for operations that do not modify the contents of a memory location.

Mousepad telephone

An improved mousepad (100) includes a telephone integrated therewith. A keypad (108) for the telephone is disposed beneath a mylar layer (130). The keypad (108) includes a plurality of capacitive switches (108a, 108b) disposed just beneath the mylar layer. In a mousepad mode, a mouse may be moved around the surface of the mylar in the standard fashion. In a telephone mode, the user may activate the keypad (108) by pressing the buttons which are viewable beneath the mylar.

Maximized memory throughput using cooperative thread arrays

In parallel processing devices, for streaming computations, processing of each data element of the stream may not be computationally intensive and thus processing may take relatively small amounts of time to compute as compared to memory accesses times required to read the stream and write the results. Therefore, memory throughput often limits the performance of the streaming computation. Generally stated, provided are methods for achieving improved, optimized, or ultimately, maximized memory throughput in such memory-throughput-limited streaming computations. Streaming computation performance is maximized by improving the aggregate memory throughput across the plurality of processing elements and threads. High aggregate memory throughput is achieved by balancing processing loads between threads and groups of threads and a hardware memory interface coupled to the parallel processing devices.

Generating event signals for performance register control using non-operative instructions

One embodiment of an instruction decoder includes an instruction parser configured to process a first non-operative instruction and to generate a first event signal corresponding to the first non-operative instruction, and a first event multiplexer configured to receive the first event signal from the instruction parser, to select the first event signal from one or more event signals and to transmit the first event signal to an event logic block. The instruction decoder may be implemented in a multithreaded processing unit, such as a shader unit, and the occurrences of the first event signal may be tracked when one or more threads are executed within the processing unit. The resulting event signal count may provide a designer with a better understanding of the behavior of a program, such as a shader program, executed within the processing unit, thereby facilitating overall processing unit and program design.

Unified addressing and instructions for accessing parallel memory spaces

One embodiment of the present invention sets forth a technique for unifying the addressing of multiple distinct parallel memory spaces into a single address space for a thread. A unified memory space address is converted into an address that accesses one of the parallel memory spaces for that thread. A single type of load or store instruction may be used that specifies the unified memory space address for a thread instead of using a different type of load or store instruction to access each of the distinct parallel memory spaces.

Indirect function call instructions in a synchronous parallel thread processor

Structured programming control flow using a disable mask in a SIMD architecture

One embodiment of a computing system configured to manage divergent threads in a SIMD thread group includes a stack configured to store state information for processing control instructions. A parallel processing unit is configured to perform the steps of determining if one or more threads diverge during execution of a conditional control instruction. Threads that exit a program are identified as idle by a disable mask. Other threads that are disabled may be enabled once the divergent threads reach an instruction that enables the disabled threads. Use of the disable mask allows for the use of conditional return and break instructions in a multithreaded SIMD architecture.

DESULFURATION OF HEAVY HYDROCARBON OILS

Register based queuing for texture requests

A graphics processing unit can queue a large number of texture requests to balance out the variability of texture requests without the need for a large texture request buffer. A dedicated texture request buffer queues the relatively small texture commands and parameters. Additionally, for each queued texture command, an associated set of texture arguments, which are typically much larger than the texture command, are stored in a general purpose register. The texture unit retrieves texture commands from the texture request buffer and then fetches the associated texture arguments from the appropriate general purpose register. The texture arguments may be stored in the general purpose register designated as the destination of the final texture value computed by the texture unit. Because the destination register must be allocated for the final texture value as texture commands are queued, storing the texture arguments in this register does not consume any additional registers.

Configurable cache for multiple clients

One embodiment of the present invention sets forth a technique for providing a L1 cache that is a central storage resource. The L1 cache services multiple clients with diverse latency and bandwidth requirements. The L1 cache may be reconfigured to create multiple storage spaces enabling the L1 cache may replace dedicated buffers, caches, and FIFOs in previous architectures. A “direct mapped” storage region that is configured within the L1 cache may replace dedicated buffers, FIFOs, and interface paths, allowing clients of the L1 cache to exchange attribute and primitive data. The direct mapped storage region may used as a global register file. A “local and global cache” storage region configured within the L1 cache may be used to support load/store memory requests to multiple spaces. These spaces include global, local, and call-return stack (CRS) memory.

Support for Non-Local Returns in Parallel Thread SIMD Engine

One embodiment of the present invention sets forth a method for executing a non-local return instruction in a parallel thread processor. The method comprises the steps of receiving, within the thread group, a first long jump instruction and, in response, popping a first token from the execution stack. The method also comprises determining whether the first token is a first long jump token that was pushed onto the execution stack when a first push instruction associated with the first long jump instruction was executed, and when the first token is the first long jump token, jumping to the second instruction based on the address specified by the first long jump token, or, when the first token is not the first long jump token, disabling the active thread until the first long jump token is popped from the execution stack.

Instructions for managing a parallel cache hierarchy

A method for managing a parallel cache hierarchy in a processing unit. The method includes receiving an instruction from a scheduler unit, where the instruction comprises a load instruction or a store instruction; determining that the instruction includes a cache operations modifier that identifies a policy for caching data associated with the instruction at one or more levels of the parallel cache hierarchy; and executing the instruction and caching the data associated with the instruction based on the cache operations modifier.

System and method for managing divergent threads in a SIMD architecture

One embodiment of a computing system configured to manage divergent threads in a thread group includes a stack configured to store at least one token and a multithreaded processing unit. The multithreaded processing unit is configured to perform the steps of fetching a program instruction, determining that the program instruction is not a branch instruction, determining whether the program instruction includes a pop-synchronization bit, and updating an active program counter, where the fashion in which the active program counter is updated relates to whether the program instruction includes a pop-synchronization bit.

Credit-Based Streaming Multiprocessor Warp Scheduling

One embodiment of the present invention sets forth a technique for ensuring cache access instructions are scheduled for execution in a multi-threaded system to improve cache locality and system performance. A credit-based technique may be used to control instruction by instruction scheduling for each warp in a group so that the group of warps is processed uniformly. A credit is computed for each warp and the credit contributes to a weight for each warp. The weight is used to select instructions for the warps that are issued for execution.

Hierarchical processor array

Apparatuses and methods are presented for a hierarchical processor. The processor comprises, at a first level of hierarchy, a plurality of similarly structured first level components, wherein each of the plurality of similarly structured first level components includes at least one combined function module capable of performing multiple classes of graphics operations, each of the multiple classes of graphics operations being associated with a different stage of graphics processing. The processor comprises, at a second level of hierarchy, a plurality of similarly structured second level components positioned within each one of the plurality of similarly structured first level components, wherein each of the plurality of similarly structured second level components is capable of carrying out different operations from the multiple classes of graphics operations, wherein each first level component is adapted to distribute work to the plurality of similarly structured second level components positioned within the first level component.

Instructions for managing a parallel cache hierarchy

A method for managing a parallel cache hierarchy in a processing unit. The method includes receiving an instruction from a scheduler unit, where the instruction comprises a load instruction or a store instruction; determining that the instruction includes a cache operations modifier that identifies a policy for caching data associated with the instruction at one or more levels of the parallel cache hierarchy; and executing the instruction and caching the data associated with the instruction based on the cache operations modifier.

Hydrocracking effluent cooling prior to hydrodesulfurization

A RESIDUE-CONTAINING PETROLEUM FRACTION, 50 PERCENT BOILING ABOVE 1,000*F., IS HYDROCRACKED AND THEN HYDRODESULFURIZED. DURING THE ONSTREAM PERIOD, THE CONVERSION LEVEL OF MATERIAL BOILING ABOVE 1,000*F. IS MAINTAINED SUBSTANTIALLY CONSTANT WHILE THE SULFUR CONTENT OF THE HYDROCRACKED EFFLUENT INCREASES. THE SULFUR CONTENT OF A PRODUCT FRACTTION IS MAINTAINED SUBSTANTIALLY CONSTANT BY GRADUALLY INCREASING THE HYDROSULFURIZATION TEMPERATURE. THE EFFLUENT FROM THE HYDROCRACKING REACTTION IS COOLED BY ADDING AN AROMATIC-RICH FRACTION AND THE COOLED MIXTURE IS PASSED TO THE DESULFURIZATION REACTION.

Unified addressing and instructions for accessing parallel memory spaces

One embodiment of the present invention sets forth a technique for unifying the addressing of multiple distinct parallel memory spaces into a single address space for a thread. A unified memory space address is converted into an address that accesses one of the parallel memory spaces for that thread. A single type of load or store instruction may be used that specifies the unified memory space address for a thread instead of using a different type of load or store instruction to access each of the distinct parallel memory spaces.

Vibrating element electrometer with output signal magnified over input signal by a function of the mechanical q of the vibrating element

PROCEDURE FOR HYDRO-DULVULATION OF HEAVY CARBONHYDRIDOLS

Systems and method for managing divergent threads in a SIMD architecture

One embodiment of a computing system configured to manage divergent threads in a thread group includes a stack configured to store at least one token and a multithreaded processing unit. The multithreaded processing unit is configured to perform the steps of fetching a program instruction, determining that the program instruction is a branch instruction, determining that the program instruction is not a return or break instruction, determining whether the program instruction includes a set-synchronization bit, and updating an active program counter, where the manner in which the active program counter is updated depends on a branch instruction type.

System and method for grouping execution threads

Design for a top

Garden tool

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Magnetic shielding and x-ray image intensifier tube using same

An x-ray image intensifier tube is evacuated by means of an appendage magnetically confined glow discharge getter-ion vacuum pump. A shell of soft iron is disposed surrounding the magnet of the appendage pump for shielding the image intensifier tube from the stray magnetic field of the appendage pump. A coating of magnetic material on the envelope of the intensifier tube, in the region facing the pump, provides additional magnetic shielding for shielding the interior of the tube from the stray magnetic field of the pump to further improve the resolution of the image intensifier tube.

Shared single-access memory with management of multiple parallel requests

A memory is used by concurrent threads in a multithreaded processor. Any addressable storage location is accessible by any of the concurrent threads, but only one location at a time is accessible. The memory is coupled to parallel processing engines that generate a group of parallel memory access requests, each specifying a target address that might be the same or different for different requests. Serialization logic selects one of the target addresses and determines which of the requests specify the selected target address. All such requests are allowed to proceed in parallel, while other requests are deferred. Deferred requests may be regenerated and processed through the serialization logic so that a group of requests can be satisfied by accessing each different target address in the group exactly once.

Fire-extinguisher.

Screen for potato diggers

Electric iron

[UNK]

Fremgangsmade til regenerering af afsvovlningskatalysatorer

Safety razor drier

System and method for processing thread groups in a SIMD architecture

Dealkylation

Ｓｉｍｄアーキテクチャ内でスレッドグループを処理するためのシステムおよび方法

【課題】そのハードウェアリソースを効率的に用いてより高いデータ処理スループットを達成するＳＭＩＤプロセッサを提供すること。 【解決手段】ＳＩＭＤプロセッサの有効幅は、データ処理側の速度の何分の１かの速度でＳＩＭＤ処理装置の命令処理側をクロッキングし、各々が複数のデータ経路を有する複数の実行パイプラインを提供することにより、拡張される。そのため、より高いデータ処理スループットが達成されると同時に、命令はフェッチされ、クロックごとに一度発行される。この構成はまた、１つの大きなスレッドグループがＳＩＭＤプロセッサを介してクラスタされ、一緒に実行されることも可能にし、その結果、グラフィックス処理に関して実行されるテクスチャメモリアクセスのようなあるタイプの動作に関してより大きなメモリ効率が達成されることが可能である。 【選択図】 図６

System and method for processing thread groups in a simd architecture

Automobile-radiator.

[UNK]

Processo de hidro-desulfurizacao de fracoes de petroleo

Fremgangsmåde til hydroafsvovlning af svære carbonhydridolier.

Dealkylation using nickel sulphide catalyst

Device for drying safety razors

Cache operations and policies for a multi-threaded client

A method for managing a parallel cache hierarchy in a processing unit. The method including receiving an instruction that includes a cache operations modifier that identifies a level of the parallel cache hierarchy in which to cache data associated with the instruction; and implementing a cache replacement policy based on the cache operations modifier.

Cooperative thread array reduction and scan operations

One embodiment of the present invention sets forth a technique for performing aggregation operations across multiple threads that execute independently. Aggregation is specified as part of a barrier synchronization or barrier arrival instruction, where in addition to performing the barrier synchronization or arrival, the instruction aggregates (using reduction or scan operations) values supplied by each thread. When a thread executes the barrier aggregation instruction the thread contributes to a scan or reduction result, and waits to execute any more instructions until after all of the threads have executed the barrier aggregation instruction. A reduction result is communicated to each thread after all of the threads have executed the barrier aggregation instruction and a scan result is communicated to each thread as the barrier aggregation instruction is executed by the thread.

Programmable graphics processor for multithreaded execution of programs

A processing unit includes multiple execution pipelines, each of which is coupled to a first input section for receiving input data for pixel processing and a second input section for receiving input data for vertex processing and to a first output section for storing processed pixel data and a second output section for storing processed vertex data. The processed vertex data is rasterized and scan converted into pixel data that is used as the input data for pixel processing. The processed pixel data is output to a raster analyzer.

Instructions for managing a parallel cache hierarchy

A method for managing a parallel cache hierarchy in a processing unit. The method includes receiving an instruction from a scheduler unit, where the instruction comprises a load instruction or a store instruction; determining that the instruction includes a cache operations modifier that identifies a policy for caching data associated with the instruction at one or more levels of the parallel cache hierarchy; and executing the instruction and caching the data associated with the instruction based on the cache operations modifier.

Indirect function call instructions in a synchronous parallel thread processor

An indirect branch instruction takes an address register as an argument in order to provide indirect function call capability for single-instruction multiple-thread (SIMT) processor architectures. The indirect branch instruction is used to implement indirect function calls, virtual function calls, and switch statements to improve processing performance compared with using sequential chains of tests and branches.