STRAP-BASED MULTIPLEXING SCHEME FOR MEMORY CONTROL MODULE

Embodiments include integrated circuits (ICs), system-on-chips (SoCs), and related methods for a strap-based multiplexing scheme for a memory control module. In one embodiment, a memory control module may include a first memory controller coupled to a first bus including a first conductor configured to carry a first signal, and a second memory controller coupled to a second bus including a second conductor configured to carry a second signal. The memory control module may further include a fuse configured to have a fuse setting, and a strap register configured to store a register value. The memory control module may further include a multiplexer configured to selectively pass the first signal or the second signal responsive to the fuse setting and the register value. Other embodiments may be described and claimed. 1. An integrated circuit on a semiconductor die comprising:a first memory controller coupled to a first bus including a first conductor configured to carry a first signal;a second memory controller coupled to a second bus including a second conductor configured to carry a second signal;a fuse configured to have a fuse setting;a strap register configured to store a register value; anda multiplexer coupled to the first conductor, the second conductor, the fuse, and the strap register, and configured to selectively pass either the first signal or the second signal responsive to the fuse setting and the register value.2. The integrated circuit of claim 1 , wherein the first conductor is configured to carry an error correction coding (ECC) signal for ECC of data signals associated with the first memory controller.3. The integrated circuit of claim 2 , wherein the second conductor is configured to carry data signals associated with the second memory controller.4. The integrated circuit of claim 1 , wherein the first conductor is configured to carry a first chip select signal associated with a first rank of the first memory controller claim 1 , and the second ...

Processing data packets within a data switch

Method and apparatus for reducing power consumption in multi-channel memory controller systems

Disclosed is a method, apparatus and computer program product for reducing memory power consumption in a server system. The server system includes a memory controller and a plurality of Dual Inline Memory Modules (DIMMs). The method for reducing the memory power consumption includes determining a status of a channel of a plurality of channels of the memory controller. The plurality of channels is associated with the plurality of DIMMs of the server system. The status of the channel represents a presence of at least one scheduled transaction in the channel. The method further includes monitoring the status of the channel by checking whether the status of the channel is in an idle mode for a period of at least equal to a first threshold time. Thereafter, the method includes driving the channel into a power down state based on the monitoring of the status of the channel.

Processing data packets within a data switch

A data switch such as an Ethernet switch compares the address contained in a received packet with addresses in MAC address table, to identify whether the table associates a port with the address. If such a match is found, the switch transmits the data packet through the port specified by the MAC address table. If not, the Ethernet switch processes the data packet according to whether the address is in a list of reserved addresses stored inside the switch.

A method for a first semiconductor device to determine if it is coupled to a second semiconductor device

A method for a first semiconductor device (1) coupled to a non-floating bus (3) to determine whether a second semiconductor device (2) is also coupled to the non-floating bus (3). The first semiconductor device (1) sends a control signal for the second semiconductor device (2) to the non-floating bus (3), and the first semiconductor device waits for a response signal from the non-floating bus (3). The first semiconductor device (1) determines that the second semiconductor device (2) is coupled to the non-floating bus (3) if a response signal is received, and determines that the second semiconductor device (2) is not connected to the non-floating bus (3) if a response signal is not received.

Verfahren, mit dem ein erster Halbleiterbaustein feststellt, ob er an einen zweiten Halbleiterbaustein gekoppelt ist

Verfahren, mit dem ein erster Halbleiterbaustein, der an einen nicht-floatenden Bus gekoppelt ist, feststellt, ob ein zweiter Halbleiterbaustein ebenfalls an den nicht-floatenden Bus gekoppelt ist, wobei das Verfahren umfasst, dass der erste Halbleiterbaustein ein Steuersignal für den zweiten Halbleiterbaustein an den nicht-floatenden Bus sendet und der erste Halbleiterbaustein auf ein Antwortsignal von dem nicht-floatenden Bus wartet, wobei der erste Halbleiterbaustein feststellt, dass der zweite Halbleiterbaustein an den nicht-floatenden Bus gekoppelt ist, wenn ein Antwortsignal empfangen wird, und feststellt, dass der zweite Halbleiterbaustein nicht an den nicht-floatenden Bus gekoppelt ist, wenn kein Antwortsignal empfangen wird.