DATA MEDIUM AND PROCEDURE FOR THE CONTACTLESS RECEIPT OF DATA AND ENERGY

The invention concerns a data medium according to the generic term of the requirement 1 with a coil for the contactless receipt of data and energy and for contactless sending of data as well as with a logical circuit for processing and memory of the received, demodulated and decoded data. Such a data medium is from FR-A-2 751,148 well-known.

Such data media become at present primarily as so-called contactless smart cards or, if them auß it the contactless interface still contacts exhibit, also as so-called combination maps or dual interface maps assigned. Their use is not limited however to the map form, since it was already suggested in wrist-watches and supporters, for example with ski elevators.

In the ISO standard of 14443 for the contactless interface such smart cards two different types of modulation for the data, which from one write/to read-in unit a map are sent, are specified at present, i.e. the pure blanking of the carrier, which is called also on-off-Keying and which work title ASK100% carries and a ASK modulation with a modulation factor from 5% to 15%, which carries the work title ASK10%. If in the following from ASK10% or from 10%-ASK-modulierten signals the speech is, a type of modulation is meant, as it is defined in ISO standard 14443.

With these types of modulation different bit codings are connected. Thus with the ASK100% a pulse position coding is used. The type of modulation and bit coding of the data, which from a smart card to one write/to read-in unit are sent, can be likewise different.

The ASK100% has the advantage to be easily demodulatable since only a blanking gap recognition circuit is necessary. However the clock is missing and in the frequency spectrum develops relatively strong sidebands with this type of modulation during the blanking gap.

The ASK10% made possible in contrast to this a constant clock supply and is with substantially lower level of the sidebands connected, is however difficult to demodulate, because on the one hand the distance between map and write/to read-in unit strongly vary can, which circuits on the map side a strongly varying power input have and which technical circuiting possibilities for the demodulator circuit are limited, since no sufficient constant and sufficiently high voltage supply is available.

It is task of the invention to indicate a data medium of the kind mentioned which the receipt of both types of modulation makes possible and clear data supplies with.

The task becomes gemä&szlig by a data medium; Requirement 1 and a procedure for the operation of such a data medium gemäß Requirement 5 solved. Favourable further educations of the invention are indicated in the Unteransprüchen.

Gemäß Requirement 1 two demodulators are intended, which can demodulate 100%-ASK and/or 10%-ASK-modulierte of signals in each case, whereby with the receipt of a 100%-ASK-modulierten of signal, with the receipt of the first blanking gap of the 10%-ASK-Demodulator, since he can receive 100%-ASK-modulierte of signals, however those is thus deactivated anschließ end to decoding completely wrong results supplies. By that erfindungsgemäß EN data medium is thus guaranteed, daß always a clear demodulation and decoding take place.

In further training of the invention after the receipt of the first data bit of a 10%-ASK-modulierten of signal of the 100%-ASK-Demodulator one deactivates. This Maß nahme provides for a clear condition of the circuit.

Alternatively indicating exit of the 100%-ASK-Demodulators can be connected after the receipt of a 10%-ASK-Datenbits with the RESET entrance of the logical circuit of the data medium, so da&szlig in favourable training of the invention article the receipt of a blanking gap; the entire data medium is put back, since the occurrence of a blanking gap with a 10%-ASK-modulierten points signal to an error or a manipulation.

In further training of the invention a status register controllable of the demodulators is intended to the announcement, which demodulator is active, which can be queried by the logical circuit for example over a common bus.

Since the power transmission differs with the receipt of a 10%-ASK-modulierten of signal substantially from with the receipt of the 100%-ASK-modulierten of signal, is intended in further training of the invention to head for a voltage supply mechanism dependent on the condition of the status register by the logical circuit so daß an optimal attitude is reached. Alternatively for this the control could take place also via the demodulators.

The invention is more near described in the following on the basis a remark example by figures. Show:

Figu

g 1 a circuit diagram for one erfindungsgemäß EN data medium,

Figure 2

a detailed circuit for a 100%-ASK-Demodulator,

Figure 3

Tension processes for the circuit gemäß Figure 2,

Figure 4

a detailed circuit for a 10%-ASK-Demodulator and

Figure 5

Tension processes for the circuit gemäß Figure 4.

In figure 1 a resonant circuit from a coil L and a condenser CS is connected with the entrance of a rectifier switch GR. The exit of the rectifier switch GR is connected with a filter capacitor CG, at whose clamps supply voltages are measurable VDD and VSS. Supply voltages VDD, VSS are supplied to a voltage supply mechanism sports association, which contains in particular rule members, in order to be able at the output to make as constant a voltage supply available for the circuits as possible downstream. The exit of the voltage supply mechanism sports association is gemä&szlig in the circuit; Figure 1 exemplary connected with a logical circuit LS. It understands itself however automatically, daß also all other circuit units with supply voltage are subjected.

The circuit diagram shows auß erdem a first demodulator DEM100 for the demodulation of 100%-ASK-modulierten signals. This is subjected with the high frequency signal, how it rests against the resonant circuit L, CS. The first demodulator DEM100 is connected with a first decoding circuit DEC100, which decodes the demodulated signal and which from it supplies derived data to the first entrance of a first OR gate OR1 and the clock pulse the first entrance of a second OR gate OR2 derived from it.

The first demodulator DEM100 points auß erdem a first exit up, which is connected with a first entrance R of a status register FF designed as flip-flop.

As signal the parallel and smoothed, however yet regular supply voltage VDD at its entrance, which can be demodulated, is supplied to a second demodulator DEM10 for the demodulation of 10%-ASK-modulierten signals. It understands itself thereby automatically, daß also the reference potential VSS just like at all other circuit parts at the second demodulator DEM10 fits. This is not explicitly represented in figure 1 for clarity reasons.

The second demodulator DEM10 is connected with a second decoding circuit DEC10, whose data output is connected with the second entrance of the first OR circuit OR1 and their clock exit with the second entrance of the second OR circuit OR2. An exit of the second demodulator DEM10 is connected with a second entrance S of the status register FF.

The first demodulator DEM100 exhibits a further exit, which is connected with a deactivation entrance of the second demodulator DEM10. In principle also its could be connected more connected with the status register FF first exit with the deactivation entrance of the second demodulator DEM10 instead of the further exit of the first demodulator DEM100.

In the same way the second demodulator DEM10 exhibits an exit, which is connected either, strichliert suggested, represented with a deactivation entrance of the first demodulator DEM100 or heads for, with pulled through lines, a Schaltmittel SM, which connects the first exit of the first demodulator DEM100 connected with the status register FF with a RESET entrance of the logical circuit LS.

The two OR gates OR1, OR2 are connected with a data pointer DR, into which the received data are written by means of the clock pulse derived from the received signal. The clock pulse is available naturally also for other circuit parts as for example the logical circuit LS. The status register FF, the data pointer DR and the logical circuit LS are for example, as in the figure 1 represented, connected by a bus with one another.

An exit of the logical circuit LS is connected, so da&szlig with an entrance of the voltage supply mechanism sports association; dependent on the condition of the status register FF and thus dependent on the received type of modulation the voltage supply mechanism sports association by the logical circuit LS to be optimally adjusted knows.

In the following the function of a 100%-ASK-Demodulators DEM100 is to be represented and described on the basis a remark example by means of the figures 2 and 3. Resembles circuit parts, as they are represented already in figure 1, is provided with same reference symbols.

The 100%-ASK-Demodulator DEM100 is essentially formed with three connected in series CMOS inverters I1, I2, I3, whereby the middle inverter I2 with differently conductive transistors T1, T2 is trained. Auß erdem the n-channel transistor T2 of the second inverter I2 a resistance R is upstream. Parallel to the series connection from the resistance R and the load distance of the n-channel transistor T2 a condenser C is arranged. The entrance of the first inverter I1 is subjected with at the resonant circuit L, CS lying close high frequency signal V, while the exit of the third inverter I3 forms the demodulated output signal V4.

In the top of the figure 3 the high frequency, 100%-ASK-modulierte signal V is represented, as it rests against the resonant circuit L, CS. In the represented example a blanking gap is shown. In the top of the figure 3 the process in principle of supply voltages VDD and VSS derived from this signal is likewise drawn in. Dependent on these supply voltages VDD, VSS results a trigger level S1 of the first inverter I1, which is strichliert represented. In the middle part of the figure 3 the process of the tension V3 at the condenser C is and, likewise strichliert, the process of the trigger level S2 of the second inverter I2 represented related to the reference potential VSS. From the relative process of the tension V3 regarding the trigger level S2 in the lower part of the figure 3 represented process of the output signal V4 of the third inverter I3 results.

As is to be taken 3 out of figure, can with a demodulator circuit DEM100 gemäß Figure 2 a blanking gap, as it is represented in the top of the figure 3, with a delay adjustable by the resistance R and the condenser C to be detected. For coding of one write/read-in unit the data medium to transferring data with a 100%-ASK-Modulation a pulse position coding one uses at present, with thus the information by the position the blanking gap within a time window which can be evaluated maß for the information is giving (see ISO/CInternational Electronical Commission 14443-2). For decoding for this the clock pulses derived from the high frequency oscillation can be counted and evaluated by the beginning of the time window up to the beginning of the blanking gap in the first decoding circuit DEC100.

A remark example of a 10%-ASK-Demodulator DEM10 is represented in figure 4. Same circuit parts, as they are represented already in figure 1, are provided with same reference symbols also here.

The 10%-ASK and/or second demodulator DEM10 is with the specialist admitted sum-and-difference amplifiers with Push Pull Ausgangstreiber downstream and this inverter downstream in an educated manner. The power source of the sum-and-difference amplifier as well as the Pull transistor of the output driver are subjected with a reference tension VREF, which is derived in not represented circuit parts from supply voltages VDD, VSS.

Against the first entrance of the sum-and-difference amplifier a signal V1 rests, which is derived over a resistance g 1 and a voltage divider RT1, RT2 from supply voltages VDD, VSS. Against the second entrance of the sum-and-difference amplifier a signal V2 rests, which is likewise derived from supply voltages VDD, VSS over the voltage divider RT1, RT2, however additionally over a Tiefpa&szlig formed with a resistance R2 and a condenser C2; one leads. Thereby the changes in the amplitude of supply voltage VDD, arising due to amplitude modulation, are set directly on the first entrance of the sum-and-difference amplifier and time-delayed to the second entrance of the sum-and-difference amplifier. In this way amplitude oscillations can be detected.

The individual tension processes are represented in figure 5, from which the function of the second demodulator DEM10 results self-describing. So is to be recognized, daß the modulation in the amplitude at the resonant circuit is illustrated of L, CS of lying close high frequency carrier signal into an appropriate amplitude oscillation of supply voltage VDD. This becomes over the voltage dividers RT1, RT2 and the resistance g 1 and/or the Tiefpaß R2, C2 to the entrances of the sum-and-difference amplifier of the second demodulator DEM10 put on. From it an output signal VOUT results, how it is represented in the lower part of the figure 5.

How is to be recognized 2 and 3 and/or 4 and 5 from a comparison of the figures, 100%-ASK-Demodulator DEM100 a 10%-ASK-Modulation can not be recognized of first, which will thus not address first demodulator DEM100 in this case. The second demodulator DEM10 will supply however output signals to the second decoder DEC10, which becomes according to decoded data in the data pointer DR writing. By a signal of the second demodulator DEM10 the status register FF is shifted into a condition, from which the logical circuit can recognize LS, which type of modulation it concerns. In favourable training of the invention the voltage supply mechanism sports association can be stopped to an optimal value by controlling of the logical circuit LS.

The second demodulator DEM10 can deactivate either the first demodulator DEM100 or an exit of this first demodulator DEM100, which indicates, daß a blanking gap was received, over a Schaltmittel SM to a RESET entrance of the logical circuit LS scolded. Thereby a possible error or a Mi&szlig can in favourable way; custom to be effectively prevented.

A deactivation of the first demodulator DEM100 and/or manipulation of the Schaltmittels SM may take place however only after is certain, daß it really around genuine ASK10%-Signal concerns and not a disturbance or the beginning of a ASK100%-Signals, thus at the earliest after the first data bit of a 10%-ASK-Modulation completely to receive became. Only then is guaranteed, daß the first demodulator DEM100 will not any longer respond, since it cannot concern a blanking gap. It can be even favourable to wait for the receipt of several bits e.g. a complete byte, in order to be able to then examine, e.g. by the starting and stop bits whether it concerns free of doubts a ASK10%-Modulation.

If however the first demodulator DEM100 detects first a blanking gap, muß the second demodulator DEM10 to be deactivated immediately, since this, as from a comparison of the figures 2, is to be recognized 3 and/or 4, 5, quite in the position is to demodulate a 100%-ASK-Modulation however due to the usually different bit coding wrong data would supply.

In order to ensure a functioning of the circuit, both demodulators and decoder must be in enterprise, in order to ensure a perfect functioning of the individual circuit parts after a power UP, after sufficient energy became to thus receive. The voltage supply mechanism sports association is initial thereby in favourable way in a condition, which permits a demodulation to a 10%-ASK-Modulation. In this condition a receipt of a 100%-ASK-Modulation is still possible, possibly however only with reduced range.