DEVICE OF CONVERSION OF NUMBERS.

The present invention provides computer systems and more particularly to devices for converting numbers between formats for use in a matrix arithmetic section of a graphics accelerator to extremely fast operation.

In the design of computer systems, is constantly searches to increase the speed of operation of such systems and to make them suited to processing of greater amounts of information. Both objectives result directly by performing a greater amount of work. The ability of computers to perform a greater amount of work is also increased by their capability to perform more different types of work. For example, using computers in many novel activities, in the arrival of display devices computer graphics, for displaying not only numbers and texts, but images representing the meanings of these numbers and for better understand the text. The ability to pivot, translate and adjust the scale of these images resulted in an extensive use of the computer in the field of engineering drawing and of the industrial design. A large number of persons in the industry are gradually computer convinced to a graphical representation is to be presented in most computer systems.

Unfortunately, the presentation of display of graphics by a computer system requires a substantial processing power of the system. For example, the presentation of a single image of graphics on the display device of the computer a satisfactory standard size requires storing information including about a thousand pixels in a horizontal direction and about a thousand pixels in a vertical direction. Therefore to storing information concerning about one million pixels to be displayed for each image. In a system that may be a certain number of different colors at display, each of these pixels may contain eight bits of digital information on the particular pixel. Therefore, is to be treated and storing about eight million bytes of information for each frame or picture to be presented on the output display.

It will be appreciated that, since the frames are updated thirty times per second in the output display to create a flickerless displacement, the total amount of information to be displayed in the output display device represents a very high number. By merely treating such an amount of information to provide a displaying graphics requires a significant time interval available for a central processing unit (CPU) and can substantially slow the operation of the faster of such processors. Therefore that the computer systems include keeping conventional graphic accelerators adapted to assist the central processing unit in its operations by supporting a portion of the data processing function concerning display graphics to the output display device of the computer. The unloading of the central processing unit of a certain part of the graphics processing functions to a graphics accelerator increases substantially the speed with which any particular computer system is adapted for processing graphical information.

Therefore, attempts have been made to design graphic accelerators to high-speed operation. One of the major functions, which can be produced with a graphics accelerator is the processing of the system matrix arithmetic required to move the images of graphics on the output display of a computer. Such matrix operations are required to manipulate both two-dimensional and three-dimensional graphics to rotate, translate, manipulate and adjust the scale otherwise the particular graphics to be displayed on the output display of the computer.

A graphics accelerator can be very useful to execute these steps since it releases the central processing unit of the need to recalculate in series different nodes of figures to be manipulated during each operation of the Figure to be displayed. A graphics accelerator can perform many operations required using hardware processing data and to greatly increase the operation of the computer system.

However there is still a major problem for obtaining extremely rapid operations. This problem is based on the fact that it is necessary to use a graphics accelerator for manipulating data in a plurality of formats of different numbers. For example, 1' information processed by the central processing unit normally occurs in a format of integers which is to appear under this format, when utilized by the output display device as a display device does not process fractions of pixels. On the other hand, many manipulations performed with very high numbers used for the scientific treatment require the use of a floating point format. Such numbers should be able to be represented in graphics associated with such scientific projects. It is evident that such floating point numbers are to be finally converted into the format of integer numbers for presentation on an output display of the computer.

Furthermore, the format described over IT FRACT is particularly useful for manipulating a particular type of display graphics in a method referred to as handling forms. The use of such a graphics system with a computer is described in British Patent US No. serial 07/252 589 having the title "method and device for manipulating images" names and deposited Rocchetti Donato 3 October 1988. Numbers FRACT The system uses a fully format different from that of the systems using the format integers and the format of the floating point numbers.

In computer systems of the prior art, is was call to the central processing unit (CPU)

to perform most conversions numbers. Therefore, although a floating point number can be processed using a floating-point coprocessor, it is to be finally converted for a processor of the system in a format of integers so that is may be used to display output on a particular graphical output display device of a computer. The number conversion between formats different numbers by a processor is processed in series and substantially delays the operation of the system. For example, to convert a floating point number to an integer number using the central processing unit, it is necessary to indicate to the central processing unit the format, with which 1' information is represented, and indicate to the central processing unit the format, wherein the output is desired, and then cause the central processing unit referring to an auxiliary process to convert the number, to obtain the output of the auxiliary processing and finally using an output in a system based on new numbers. It is evident to those skilled in the art that this significantly slows the operation of any computer system.

Therefore an object of the present invention is to accelerate the operation of a computer system by providing provisions for rapidly processing the number conversion between formats different number in a graphics accelerator used with such a computer system.

This and other objectives of the present invention are achieved using an accelerator

graphics system includes a matrix transformation including first and second circuits number conversion, a first of said circuits including means for converting the format of the numbers of integers, of floating point numbers and numbers FRACT in numbers expressed in the format numbers modulo 256 multi-port, while the second circuit includes means for converting numbers based ratio numbers modulo 256 multi-port in lesformats integers, of floating point numbers and numbers FRACT , using procedures matrix transformation.

Other features and advantages of the present invention shall become apparent from the description given below taken with reference to the accompanying drawings, on which the identical elements are designated by the same reference numbers and of which:

-figure 1 shows an illustration of three number formats which can be used by the graphics accelerator associated with the present invention;

-figure 2 represents the modulo 256 format to multiple access points used internally by the matrix transformation according to the present invention;

-figure 3 is a block diagram illustrating the circuit of the matrix transformation system according to the present invention;

-figure 4 is a block diagram illustrating the circuit for performing the input conversion process in the present invention; and

figure 5-is a block diagram showing the circuit for performing the process output conversion in the present invention.

One will keeps some portions of the detailed descriptions in the form of algorithms and symbolic representations of operations on data bits in a computer memory. S descriptions The as algorithms and representations are the means used by those skilled in the data processing technique to include in the most effective manner the nature of their work to other experts of the art.

An algorithm is here, and generally, designed as a autoconsistency sequence of steps leading to a desired result. The steps are those required by physical manipulations performed on physical quantities. Typically, but not necessarily, these quantities take the form of electrical or magnetic signals capable of being stored, transferred, combined, compared, and otherwise manipulated. It has been found sometimes suitable, principaiement due to common usage, to refer to these signals as bits, values, elements, symbols or characters, terms, numbers or the like. However, it is necessary to remember that all these terms and other similar terms may be associated with the appropriate physical quantities and are merely convenient title applied to these quantities.

Furthermore, the actions are often designated in the form of terms, such as additions or comparisons, which are usually associated with mental operations performed by a human operator. In most cases, any capability of a human operator is necessary or desirable in any one of the operations described herein, which is part of the present invention; the operations are machine operations. Useful machines for performing the operations according to the present invention include general-purpose computers or the like. In all cases, should be retained in memory, the distinction between the operations to a method for operating a computer and the method of calculation. The present invention relates to a device and of the method steps for operating a computer for processing electrical signals or other physical signals (i.e. mechanical, chemical) to produce other desired physical signals.

Referring maintaining in Figure 1, is represented is three number formats, that can be used in a computer system having a graphics accelerator arranged in accordance with the present invention. Format represented The first number is the integer format, which includes thirty-two bits of information in the type of two complementing. The decimal point (actually binary) is assumed to appear to the right of the rightmost bit. The format of integers of treating a number of -2³¹ 2 TO³¹ -1 in a format to thirty-two bits. Specialists art will include that the format of integers of treating only integers and to treat or moieties to decimal numbers.

The second format shown in Figure 1 is so-called FRACT the format. In this format, thirty-two bits of memory are provided in the two's complement format. The sixteen bits left most in the format FRACT represent binary integer numbers, while the right most sixteen bits represent the fractional portions of the numbers. Although the bits of the integer part represent positive powers of two beginning with 2° and increasing to the left from the binary point, the bits of the fractional portion are negative powers of two, starting with 2, the negative power increasing to right from the point. When using this format, can be easily represent the integer and a fractional portion. The format FRACT is particularly useful for treatment of graphical objects for their representations on an output display of a computer, as will be appreciated from the description provided in the application aforesaid copendante.

The third format number represented in Figure 1 is the floating point format single precision of the Institute of Electrical and Electronics Engineers (IEEE), whose thirty-two bit positions include a sign bit Completely left, eight bits which are used to represent an exponent and 23 bits, which are used to represent the mantissa, unsigned, of a floating point number. The figure IEEE, an additional bit, which represents a zero head and is assumed to be present-most left of the mantissa to twenty-three bits such that the mantissa reality includes twenty-four bits, when the representation is used. The floating point format IEEE single precision to represent numbers from about -2 ^^⁸ ^ 2 and 7.

Specialists art see that a process for treating numbers in the integer format cannot probably not processing numbers or in the format FRACT , in the IEEE single precision format. Similarly, a process for treating numbers in the format FRACT is probably incapable of processing numbers in the integer format and in the IEEE single precision format. Finally, a process for treating numbers in the IEEE single precision format is probably incapable of processing numbers in the integer format and in the format FRACT. Therefore use, generally, in computer systems of the prior art, the central processing unit or a floating-point coprocessor numbers for converting from one format to another before it is processed by the graphics accelerator associated with the system. However, as aforesaid, such manipulation substantially throttles the operation of the computer system for displaying output display graphics.

The invention obviates the need to use I ' central processing unit to perform conversions of numbers and thereby significantly accelerates the operation of the graphics accelerator. It executes these tasks by providing a new number format, in which each of the three number formats shown in Figure 1 is converted before it is handled by 1' graphics accelerator. This format of numbers is used internally by the system for converting the graphics accelerator to perform all operations matrix arithmetic. Numbers issued on the basis of the use of this novel format numbers are converted appropriately in each of the formats including the integer format, the format FRACT and floating-point format IEEE single precision to be then used by the system after the manipulations of the transformation system have been made. The system is also capable of receiving 1' information from the external circuit and output to the circuit in the internal format.

Figure 2 represents the new format number, which is referred to as number modulo 256 format to multiple access points (hereinafter referred to "modulo 256"), used in accordance with the present invention. This format comprises thirty-six individual bit positions including the four leftmost bits used to represent an exponent, the following eight bits used to represent an element of an integer type, and the twenty-four bit right most used to represent a fractional component as in the format fract numbers. This format number are used in a manner slightly different than any other number formats.

However it is easily adaptable for the conversion from each of the formats as will be described. Although only four bits are provided for the exponents, any increase of one unit of the exponent is considered a multiplication of the mantissa by 256 (an offset of eight bits). Furthermore, the number of available bits for the mantissa is significantly higher than in the case of the IEEE single precision format. Therefore the sufficient space to accommodate the majority of the encountered numbers is provided by the new format.

To read a number represented in the format modulo 256, the mantissa provided with a sign multiplied by 256 is raised to the power indicated by the four bits of the exponent least eight (the bit of rank high of the exponent). The high-order bit of the exponent is a for all positive exponents. The present in the high-order bit of the modulo 256 format allows the easy conversion to and from the IEEE format. The need of a position in the high bit require subtracting an eight decimal to obtain the correct value of 1' exponent.

One will consider a binary number present in the mantissa, the binary point being positioned as shown in Figure 2. If the four bits of the exponent are 1000, the binary point remains in its initial position as shown in Figure 2, eight bits being present to the right of the least significant bit of the exponent. If the bits of the exponent are 1001, indicating an exponent a, the binary point is effectively offset from eight bits to the right of the position shown in Figure 2. If the exponent is 1010, indicating an exponent equal to two, the binary point is offset effectively sixteen bits to the right of the position shown in Figure 2.

It is very easily from the different standard numbers modulo 256 format and vice versa. For example, the conversion from the integer format merely requires that the integer is placed with its least significant bit in 1¹ the space to the right of 1' space of the modulo 256 and mantissa that the exponent of the modulo 256 format is set to 1011 (which is an exponent corresponding to the decimal three. This value of the exponent causes an effective shift of the binary point separating the integer and the fractional portion from its normal position of thirty-four bit to the left of the right-most bit of the mantissa to the position right final mantissa, whereby the stored number is an integer. This number is then normalized so that the bits fit better in the space provided by the modulo 256 format, movement of the binary point as far as possible to the left in steps of eight bits, and by reducing an unit of the exponent for each step. Therefore, if the integer type generally required eight bits or less, it would be moved from thirty-four bits to the left so as to be located in the available space, and the exponent would be reduced and become three 1000, so that the binary point would be returned to its normal position in the format modulo 256. On the other hand, if the required nine bit integer, but less than seventeen bits in total, it would be moved on only sixteen bits to the left so as to fit in the space available, the exponents of two would be reduced and become 1001, so that the binary point would be located to eight bits to the right of its normal position in the modulo 256 format.

To perform the conversion from the format to the format numbers FRACT number modulo 256, it is sufficient that the number FRACT is placed in its normal position its least significant bit being located in the space of the right-most bit of the mantissa space of the modulo 256 and that the exponent modulo 256 is set to 1001 (incremented by one) since this causes the effective displacement of the point bit eight bits to the right as described in the discussion relative to Figure 2. Furthermore, the number FRA. CT is normalized in the same manner that the whole numbers by moving the entire part as far as possible to the left, in increments of eight bits, and by reducing a unit of the exponent for each such step. Therefore, if the integer portion type required in total eight bits or less, it would move eight bits to the left to insert them into the available space, and the exponent would be reduced by one to 1000 so that the binary point would be returned to its normal position in the format modulo 256. This is particularly advantageous in the format FRACT being given that ' obtains the maximum accuracy with the space available.

Finally, conversion expressed in the format of IEEE single precision format in the modulo 256 requires the mantissa is not provided with a sign is converted into a number type and that the number is shifted to adjust the different bits of base of the exponent. A different form of normalization is necessary for indicated numbers in floating-point format IEEE single-position. Such numbers include a mantissa and an exponent; however the exponent in the IEEE format is a power of two. Therefore there is a need to compensate for the difference of the value attributed to the exponent, in-point format into the format flottanteet modulo 256. Since each increment of the unit in the exponent of the floating point number is a magnification of a single power of two, while each increment of a unit in the exponent of the modulo 256 format represents 256 to additional power, there is a need to compensate for this difference by moving the point bit in the mantissa. For example, the number 0.1011110X2¹⁸ in floating-point format is represented by the number 10.11110X256² in the modulo 256 format. On the other hand, the number 0, 1011110Χ2⁸ in floating-point format can be represented by the number 101111.0X 256⁸ in the modulo 256 format. In each case, the conversion requires, when the exponent representing a power of two is changed into a power of 256, the binary point in the mantissa is moved. Therefore, it is often necessary to both modify the exponent to represent a correct power of 256 and shifting the binary point in the mantissa, of a selected number of individual bit positions, to normalize the numbers during the conversion from the floating point format in the IEEE single precision format modulo 256.

It will be appreciated that, although only four bits are provided for the exponents in the modulo 256 format, while eight bits are provided in the IEEE single precision format, eight additional bits are provided for the mantissa of the number in the modulo 256 format. Therefore, provides the number expressed almost the full range of numbers in the IEEE single precision format. More particularly, the numbers, which may be expressed in the modulo 256 format to represent the numbers of the IEEE single precision format, range from least 2⁶⁴ 2 TO⁶³ -l. Although this does not include an integer power of two at each end of the range and allows of expressing least that can express IEEE single precision format, it has been found to be entirely sufficient for expressing numbers used in display devices graphical output. Further a number can be maintained more accurately when undertaking in the modulo 256 format due to the greater number of bits available in the mantissa.

Figure 3 represents, in the form of a block diagram, the basic arrangement of the circuit according to the present invention.

As shown in Figure 3, input signals representing integers, numbers and FRACT numbers to floating point format, are received from a data bus in an input converting unit 12. In the system in which the present invention is used, the integers are sent to an address so that they can be detected by the input converting unit 12, wherein the unit they are present under this format. Similarly, numbers appearing respectively in the input format FRACT and in the format floating point input, are sent to addresses such that they are identified by the input converting unit 12 to occur in these formats, to be converted and normalized as described above for each of these formats.

The numbers in the input converting unit are converted in the format modulo 256 and are transferred to the motor or transformation system of the graphic accelerator 14. Figure 4 represents in the form of a block diagram the circuit of the input converting unit 12 for performing this input conversion. The circuit 12 shown in Figure 4 includes a data bus 21, in which input data is received in accordance with the integer format, the format FRACT or the IEEE format. The floating point data are transferred to a processing converter 200 numbers and complementary to two unsigned, and a computer 201 of the exponent floating point. The calculator 201 of the exponent floating point exponents calculates the change in accordance with the description previously given and controls a barrel shifter 202 for displacing the mantissa on a correct number of bits, according to increments of one bit, so that the numbers present in the two formats are equivalent. The floating point calculator delivers an exponent for use in the modulo 256 format while the barrel shifter 202 provides a mantissa provided with a sign. These bits are transmitted to a multiplexer 220 for use by the transformation system 14 shown in Figure 3.

Data integer FRACT and the data appearing on the data bus 21 are fed to a computer 210 integer exponent/numbers FRACT , which calculates the exponent appropriate for the number converted in accordance with the details previously described. The calculator 210 sends an exponent suitable format to the multiplexer 220 for the modulo 256 and controls a barrel shifter eight-bit 211 to send to the multiplexer 220 a mantissa offset from the appropriate number of bit positions. Depending on the format converted, the multiplexer 25 is activated to transfer the appropriate bits and exposure to the processing system 14.

The. transformation system 14 processes the matrix numbers according to formulas standard well known in the art and adapted however, the single format number according to the present invention and provides output signals to the unit for converting the output 16. The features of the circuit for performing the transformation of numbers are described in the specification as having patent copendante for "Device for handling of numbers in a computer", deposited on behalf of Priem and Malachowski , and having the same priority date of the present application. The conversion unit 16 converts from the format numbers modulo 256 at each integer formats, FRACT and number of floating-point numbers, for later use by the system. For example, the integer format is the format, in which numbers are to be used for storage in the frame buffer output. On the other hand, the format FRACT , floating-point format modulo 2546 and the internal format may be used by the computer system for other operations by the system, than the storage in the frame buffer.

Figure 5 represents a circuit used to perform the format conversion number modulo 256 at integer format, format FRACT and at floating point format. The conversion unit output 16 shown in Figure 5 receives data into the modulo 256 format. If the data are to be used in this format, they are transferred directly to a first multiplexer 303 and, therefrom, to a second multiplexer 320 for use by other parts of the system. The multiplexer 303 is necessary to divide the thirty-six bits of the modulo 256 format ten-eight bit positions, that can be used by the system.

If the desired output signal must be present in the IEEE format, the thirty-two bits of the mantissa provided with a sign are transferred to a request converter 300 complement numbers 2 and in numbers non-provided with a sign. The sign bit is transferred directly to the multiplexer 320, while the other bits are transferred to a barrel shifter 302, which can shift the mantissa the number modulo 256, a selected number of positions of individual bits. The number of bits of the mantissa is to be shifted, is controlled by a transformed exponent calculation circuit floating, which operates in accordance with the description previously indicated to normalize the exponents of the two formats and controlling shifting the mantissa using the barrel shifter 302. The exponent in the IEEE format is transferred from the computer to the multiplexer 320 301, while the mantissa, offset appropriately, is transferred from the shifter to the multiplexer 320 302.

If the data is to be converted is the format FRACT , either in the integer format, the exponent is transferred to a control device 310 integer exponent/number FRACT , which calculates the appropriate exponent in the desired format as described above, and controls the shifter 311 for by shifting the mantissa of the appropriate number of increments of eight bits so as to the proper location, the exponent is transferred by the control device 310 to the multiplexer 320, and the mantissa, offset appropriately, is transferred from the shifter 311 to the multiplexer 320.

While the present invention has been described in a preferred embodiment, those skilled in the art note that the can be ameliorated of many changes and modifications without departing from the frame 1¹ invention.