DISPLAY DEVICE

Hereinafter, based on a text content of the drawing of the present invention preferred embodiment in reference to. rapidly and to reduce a memory a.

If the second voice is inputted, the above-mentioned the present invention number and, number and constitution, and effect associated with drawing with an embodiment is simple for through examples will hereinafter. Each drawing an unambiguous for instructing a in part and preferably predominantly, of simple or been representation of a blown up. Each of the drawings components in by adding reference number, a structure similar to that of the drawing other although for elements even displayed on a has the same sign been shown to. to significantly different. In addition, the present invention describes the, associated with the function for configurations or publicly known a description is the present subject matter of invention a microscopic wall of the rectangular the when a mobile station is determined to a dispensed the description.

Figure 1 shows a multiplex device display according to an embodiment of the present invention also is of blocks.

Also with a 1, according to an embodiment of the present invention display device comprises a display panel (PNL), timing controller (TC), gate driver (GDV), and data driver includes (DDV).

Said display panel (PNL) substrate the number 1, number 2 substrate, and including a layer of liquid crystal disposed between the array substrate and the counter can be liquid crystal panel.

Said display panel (PNL) the number 1 direction (D1; for example the row direction)-extending gate lines (GL1 ∼GLm) said number 1 and number 2 direction transverse to a direction (D1) (D2; for example the column direction)-extending data lines (DL1 ∼DLn) includes. Said display panel (PNL) interposed between the lower substrate and the group may include (PG), said one or more said pixels 2 pixel group may include, for example, three or four pixels may include a. Said plurality of pixels group (PG) said number 2 direction (D1) and the number 1 direction (D2) .may be arranged in. One in the embodiment of the present invention (PG) in each pixel group the 3 pixels from bar, which may include, for example, (PX1) pixel number 1, number 2 and number 3 pixel pixel (PX2) may comprise an (PX3). Said number 1 to number 3 pixel (PX1, PX2, PX3) the number 1 direction (D1) can be sequentially arranged. Said number 1 to number 3 pixel (PX1, PX2, PX3) the same gate line (i.e., gate line (GL1) number 1) is connected to, different data line (i.e., number 1 to number 3 data line (DL1, DL2, DL3)) may be connected to respectively.

Said number 1 to number 3 pixel (PX1, PX2, PX3) the lead, green, and blue color filter may comprise an. On the other hand, the is one number, said number 1 to number 3 pixel (PX1, PX2, PX3) has white, yellow, cyan, magenta of a polyimide resin, such displays a color.

Said timing controller (TC) determinator an external graphic number (not shown) and number (RGB) video data from: this recorder receives the signals. A signal said number/output sequence signal vertical synchronous signal (Vsync), row distinguish signal horizontal synchronous signal (Hsync), data is areas of which data is output for display only according high (HIGH) level data enable signal (DES) and a main clock pulse signal (MCLK) may comprise an.

Said timing controller (TC) the Image data (RGB) for said data driver (DDV) and converted so as to to sidewalls of the storage space, converted Image data (DATA) a outputs the to said data driver (DDV). the number (TC) said timing controller based on thermoresistive signal the gate number and data number signal (GS1) generates a signal (DS1). Said timing controller (TC) the gate number signal (GS1) a gate driver (GDV) to output to said, said data number signal (DS1) a outputs the to said data driver (DDV). Said gate number signal (GS1) (GDV) the gate driver for driving a signals, said data number signal (DS1) (DDV) the data driver is signal for driving a.

the gate said gate driver (GDV) based on number signal (GS1) to generate a scaled signal and the gate, said gate signal said gate lines (GL1-gLm) outputs the to. Said gate number signal (GS1) the scanning starts indicating a scanning starts output cycles over a gate on voltage and gate off signal and number moves the at least one clock signal, and gate on voltage and gate off output enable defining a duration may include a signal or the like.

Said data driver the data number (DDV) based on signal (DS1) according to said Image data and generating a gradation voltage (DATA), said data voltage same data lines (DL1-dLn) outputs the to. Said a common data voltage having a positive value with respect to the voltage there positive data voltage and comprises a negative electrode-typed impurity may include a voltage-voice data. Said data number signal (DS1) Image data (DATA) is said data driver (DDV) as signal representing the start of a horizontal start signal (STH), said data lines (DL1-dLn) data voltage is applied, data, and load signals unit translates a first guest address, and common with respect to the voltage there the inverse polarity of data voltage may include a signal or the like.

Said timing controller (TC), said gate driver (GDV), and said data driver (DDV) each said at least one integrated circuit chip in the form of or to be mounted directly to a display panel (PNL), flexible printed circuit board (flexible printed circuit board) is mounted over the in the form of TCP (tape carrier package) is attached to and said display panel (PNL), separate printed circuit board (printed circuit board) can be mounted on. Alternatively, the, said gate driver (GDV) and said data driver (DDV) at least one of said gate lines (GL1-gLm), said data lines (DL1-dLn), and said transistor with said display panel (PNL) may be integrated. In addition, said timing controller (TC), said gate driver (GDV), and said data driver (DDV) a single chip can be integrated.

Also also shown in Figure 2 shows a 1 indicating a a display panel is plane.

Also refers to surface 2, in the embodiment according to one of the present invention shows an Image display device has a number of pixel group may include a (PG). In Figure 2 a plurality of pixel group one of the shown representatively. Said remaining pixel group in an illustrated structure and substantially is the same in structure as illustrated at since additional does not.

Said pixel group (PG) the number 1 direction (D1) sequentially arranged in between data lines 4 mutually adjacent bar a ball number between gate lines, 4 sequentially arranged in data line number 4 to number 1 m/i data lines (DL1, DL2, DL3, DL4) and referred to as the, each pixel a sidewall of the gate line is connected gate line referred to as the number 1 the invention relates to a (GL1).

Said pixel group (PG) the number 1 to number 3 pixels (PX1, PX2, PX3) includes. Said number 1 to number 3 pixels (PX1, PX2, PX3) the number 1 direction (D1) sequentially arranged in number 1 to number 3 pixel region (PA1, PA2, PA3) is ball number to. The number 1 and number 2 (PA1) said number 1 pixel region (DL1, DL2) between the data lines is ball number, said number 2 pixel region (PA2) the number 2 and number 3 data lines (DL2, DL3) are ball number between , the number 3 and number 4 (PA3) said number 3 pixel region (DL3, DL4) between the data line is ball number.

Pixel (PX1) said number 1 the number 1 transistor (TR1) is connected to, said number 1 transistor (TR1) (GL1) and the number 1 gate line is connected to data line (DL1) said number 1. Said number 2 pixel (PX2) the number 2 transistor (TR2) is connected to, said number 2 transistor (TR2) (GL1) and the number 1 gate line is connected to data line (DL2) said number 2. The number 3 transistor said number 3 pixel (PX3) (TR3) is connected to, the number 1 (TR3) said number 2 transistor gate line (GL1) and said number 3 is connected to data line (DL3).

Said number 1 pixel region (PA1), said number 2 pixel region (PA2), and said number 3 pixel region (PA3) the pixel region of at least two of said number 1 direction different (D1). width on a signal of the gate line. The transfer plate is combined with the vapor deposition transverse said each pixel from a data line are equipped other side can be defined by distance. In other words,, vapor deposition of said number 1 pixel (PX1) said number 1 direction along the data line (D1) from said number 1 (DL1) said number 2 data line (DL2) can be defined by distance. In the same manner (PX1) of said number 1 pixel width number 1 width (W1), said number 2 pixel (PX2) of width (W2) width number 2, number 3 width of said number 3 pixel (PX3) width (W3) is formed on the metal thin film, said number 1 to number 3 width (W1, W2, W3) each can take the different widths. In one in the embodiment of the present invention, two width are identical to each other and the other to the width of the may be greater or lesser. For example, as shown in also 2, said number 1 width (W1) and said number 2 width (W2) the substantially equal, said number 3 width (W3) the number 1 width (W1) or said number 2. can be larger than width (W2). In one in the embodiment of the present invention, the width (W3) said number 3 said number 1 width (W1) or width (W3) of said number 2 may bail 2.

Said number 1 pixel region (PA1), said number 2 pixel region (PA2), and said number 3 pixel region (D2) said number 2 (PA3) each other in each direction may have vertical width such as. Each pixel number 2 direction of said longitudinal vapor deposition (D2) a gate the transfer plate is combined with the other line distance line to a first end can be defined by. However, one in the embodiment of the present invention said number 1 to number 3 in different pixel region may have vertical width of.

In one in the embodiment of the present invention, said longitudinal width of each pixel area with their use in the vapor deposition can be setting up, in this case said number 1 pixel region (PA1), said number 2 pixel region (PA2), and surface of each other said number 3 pixel region (PA3) different or, two pixel region of a pixel within a scanning spot remaining the same as the area of the two area can be smaller or greater than each of pixel region..

In one in the embodiment of the present invention, pixel (PX1) said number 1 the number 1 color, for example red (R) indicating that the portable computing device is, the number 2 (PX2) said number 2 pixel color, for example green (G), white color filters, respectively, the number 3 color pixel (PX3) said number 3, for example blue (B) a new line. However, said number 1 to number 3 pixel (PX1, PX2, PX3) with a color are not limited to. Said number 1 to number 3 pixel (PX1, PX2, PX3) at least one of the pixels may have is larger than. Of the present invention in one example, said number 3 in Figure 1 converts the blue for displaying said number 1 and number 2 pixel (PX3) is pixel (PX1, PX2) is larger than was shown a structure having a SIGE buffer layer. However, said number 2 and number 3 pixel pixel (PX1) is said number 1 (PX2, PX3) or is larger than, said number 2 pixel (PX2) is pixel number 3 and number 1 (PX1, PX3) material may have a is larger than.

Hereinafter, also 2 3 also and a reference to the center of which lies on the pixel number 1 (PX1) includes such as TFTs are and the wiring to the display panel to the disclosed. Wherein, Figure 3 shows a I-I ' ray is according to cross-sectional drawing of Figure 2. Said number 1 to number 3 pixel pixel pixel said number 1, wherein the polishing system is substantially under the outside number portion and size is the same in structure and of substantially the same driving fashion since, to a, which does not require a described.

In the embodiment according to the display panel includes one of the present invention substrate number 1 (SUB1) substrate (SUB1) opposed to said number 1 and number 2 substrate (SUB2), and said number 1 substrate (SUB1) and formed between the number 2 substrate (SUB2) includes liquid crystal layer (LC).

Said number 1 substrate (SUB1) number on the number 1 base substrate a predetermined pitch between metal lines and outliers (BS2), is made from a high-density wiring said number 1 transistor (TR1), and said number 1 transistor (TR1) connected to the pixel electrodes contact the drain electrode includes (PE).

Number 1 base substrate (BS1) transparent and square shapes that approximately consisting of insulating material.

Number 1 the gate line (GL1), parasitic capacitance electrode (PCE), (DL1) data line number 1, includes storage line (STL).

Said number 1 gate line (GL1) (BS1) on the number 1 base substrate number 1 direction (D1) is formed bars are supported from the side rails.

Said parasitic capacitance electrode (PCE) (GL1) projecting from the number 1 gate line or said number 1 gate line (GL1) is formed on a portion of the is ball number.

the number 1 base substrate (STL) said storage line (BS1) on said number 1 away to said number 1 gate line (GL1) direction (D1) is formed bars are supported from the side rails. One in the embodiment of the present invention said number 1 (STL) is in said storage line (GL1) the direction which is parallel with the gate line extending only but is shown that, the shape of the storage line (STL) not limited to. the after alcoholic beverage it will do said storage line (PE) (STL) formed on the semiconductor substrate with the pixel electrode in order to achieve a high said number 2 along the adjacent data line direction (D2) is protruded with a predetermined protrusion extending from the may include further.

Said number 1 gate line (GL1) said number 1 base substrate (BS1) on the gate insulating film (GI) is ball number is. Said gate insulating layer of an insulating material (GI) that may be made from an bar, for example, silicon nitride or, may include a silicon oxide.

the number 1 gate line (DL1) said number 1 data line (GL1) and said gate insulating layer with respect to two non (GI) said number 1 number 2 direction transverse to a direction (D1) (D2) is ball number bars are supported from the side rails.

Said number 1 transistor (TR1) (GL1) and the number 1 gate line is connected to data line (DL1) said number 1. With a 1 also, in operation by all the pixels is made said data lines and said gate lines and, each including a plurality transistors ball number to a bar, each transistor a plurality of gate lines with a corresponding one of a plurality of data line is connected to a corresponding one of.

Also again with a 2 and 3, said number 1 transistor (TR1) has a gate electrode (GE), semiconductor pattern (SM), source electrode (SE), and a drain electrode includes (DE).

Said gate electrode (GE) (GL1) projecting from the number 1 gate line or said number 1 gate line (GL1) is formed on a portion of the is ball number.

Said gate electrode (GE) can be hollow metal elements in such a manner. Said gate electrode (GE) a nickel, chromium, molybdenum, aluminum, titanium, copper, tungsten, and can be alloy including. the said said gate electrode (GE) multilayer film or using a metal can be formed. For example, said said gate electrode (GE) molybdenum, aluminum, and molybdenum are sequentially triple film or, titanium and copper are subsequently charged layered double reflective KIPO &. Or titanium of copper with at reflective KIPO & a single alloy.

Said semiconductor pattern (SM) (GI) on the gate insulating layer is ball number. Said semiconductor layer (SM) (GI) the gate insulating layer of the gate with respect to two non (GE) on said gate electrode is ball number. A partial area of the semiconductor pattern (SM) (GE) and overlapped on said gate electrode. Said semiconductor pattern (SM) the amorphous silicon thin film or oxide semiconductor thin film is formed on can be.

Said source electrode (SE) in the data line (DL) is ball number branched. Said source electrode (SE) (SM) the second semiconductor pattern is formed on a partial area of said gate electrode (GE) overlap with the..

Said drain electrode (DE) the semiconductor pattern (SM) with respect to two non spaced apart from said source electrode (SE) is ball number. Said drain electrode (DE) (SM) the semiconductor pattern is formed on a partial area of said gate electrode (GE) is ball number and a reverse. In addition, said drain electrode (DE) one-way (for example number 1 direction (D1)) can be extending, the part thereof (GI) said gate insulating layer with respect to two non parasitic capacitance electrode (PCE) that overlaps with said.. Said drain electrode (DE), said parasitic capacitance electrode (PCE), and said gate insulating layer (GI) of the parasitic capacitor (Cgd) and form a.

Said source electrode (SE) and said drain electrode (DE) a nickel, chromium, molybdenum, aluminum, titanium, copper, tungsten, and can be alloy including. Said source electrode (SE) and said drain electrode (DE) the multilayer film or using a metal can be formed. For example, said source electrode (SE) and said drain electrode (DE) a titanium and copper are subsequently charged layered double reflective KIPO &. A single alloy of copper with at or titanium reflective KIPO &.

Said source electrode (SE) and spaced each other (DE) said drain electrode, said source electrode (SE) and between said drain electrode (DE) expose the upper surfaces of said semiconductor pattern is (SM). Said source electrode said drain electrode (SE) and said semiconductor pattern (DE) between the gate electrode (GE) (SM) for measuring a voltage is applied of said source electrode (SE) and said drain electrode (conductive channel) (DE) conduction channel between a channel portion (CHN) is.

Said source electrode (SE) and said drain electrode is on are overlapped (PSV) (DE) is ball number. Said protective film (PSV) for example, silicon nitride or, may include a silicon oxide.

Said protective film (PSV) the part of the upper surface of the drain electrode (DE) (CH) is a contact hole exposing the is ball number.

Said pixel electrode (PE) number on the protective film (PSV) are ball, said contact hole (CH) through (DE) is connected to said drain electrode.

Said pixel electrode (PE) when a planar for viewing on but substantially rectangular shaped, are not limited to said of the shape of each pixel (PXL) may be provided in a variety of shapes, . Slits or said pixel electrode (PE) or copper to block the electromagnetic wave may be ball number.

Said pixel electrode (PE) is made from a transparent conductive material. Said pixel electrode (PE) transparent conductive oxide (Transparent Conductive Oxide) may be formed as. Said transparent conductive oxide is ITO (indium tin oxide), IZO (indium zinc oxide), ITZO (indium tin zinc oxide) such as.

Said pixel electrode (PE) (GI) and the gate insulating layer with respect to two non said protective film (PSV) (STL) overlaps with said storage line (Cst) to form a storage capacitor.

Said number 2 substrate (SUB2) (SUB1) the number 1 substrate 1 comprises the rectangular plate like nut to oppose to the array substrate. The number 2 base substrate (SUB2) said number 2 substrate (BS2), color filter (CF), black matrix (BM), and a common electrode (CE) may include a.

Said color filter (CF) and black matrix (BM) the number 2 (BS2) is provided on base substrate. Said common electrode (CE) the color filters (CF) and black matrix (BM) is provided on.

Each color filters (CF) the lead, green, and blue can exhibit. While, the number is one, white, yellow, cyan, magenta of a polyimide resin, such displays a color.

Said black matrix (BM) (CF) the color filters are formed between, said between adjacent pixels a liquid crystal layer (LC) are shut off. In one in the embodiment of the present invention, said number 2 (CF) is said color filter substrate (SUB2) to show a outliers number but are not limited to, other in number on substrate (SUB1) said number 1 in the embodiment may be ball.

Said common electrode (CE) the color filters (CF) and black matrix (BM) is provided on. A low cost does not shown, said common electrode (CE) slits or may be ball number or copper to block the electromagnetic wave.

In the present in the embodiment, the device display said TN (vertical alignment) mode (twisted nematic) mode or VA. be able to operate with.

In one in the embodiment of the present invention, said pixel electrode (PE), said common electrode (CE), and the liquid crystal layer (LC) (PX1) and form a pixel number 1. Said number 1 pixel (PX1) the number 1 transistor (TR1) is driven by. I.e., gate line (GL1) through said number 1 number ball gate signal in response to said transistor (TR1) is turned on, said number 1 data line (DL1) data voltage a ball number through said turn - powered on transistor (TR1) (PE) in said pixel electrode through the is ball number. The, said applied data voltage said pixel electrode (PE) and the common of said common electrode (CE) is formed is between. Said according to the electric field the liquid crystal layer (LC) maximum are driven liquid crystal molecules of said liquid crystal layer (LC) according to the amount of light transmitting Image is a second window displays IDS.

Also door has 4b and 4a shown in 2 number 1 transistor (TR1) and a number 3 transistor (TR3) is indicative of the outlines each plane view.

According to one in the embodiment of the present invention connected to said number 1 pixel (PX1) size of the number 1 transistor (TR1) connected to said number 2 pixel (PX2) number 2 transistor (TR2) equal to the size of a container header and, said number 3 pixel (PX3) (TR3) connected to said number 3 transistor size of the transistor (TR1, TR2) said number 1 and number 2 on size and. hereinafter. Said number 1 transistor (TR1) and said number 2 transistor (TR2) identical shaped and of equal size on account of their is protruded from the guide, hereinafter, said number 2 transistor (TR2) and said number 1 transistor (TR1) under the outside the number said number 3 and a transistor (TR3) compares a a.

Also 2, also refers to surface 4a and 4b, in one in the embodiment of the present invention, said number 1 transistor (TR1) (CHN1) channel length of channel length of the number 3 transistor (TR3) (CHN2) can be smaller than the.. The number 1 and number 3 pixel region according to a ratio of area (PA1, PA3) is a section for are connected with the storage node, having the largest interior pixel region pixel number 3 (PX3) (TR3) connected to channel length of transistor number 3 (CHN3) is is formed have different.

In addition, drain electrode of said number 1 transistor (TR1) (DE) the area of the drain electrode of said number 3 transistor (TR3) smaller than than those of (DE). A portion of said drain electrode (DE) said gate insulating layer with respect to two non (GI) (PCE) said parasitic capacitance electrode that overlap that bar, said drain electrode (DE) according to the difference on the surface of the first said parasitic capacitance electrode (PCE) and said drain electrode (DE). difference in addition area elements with different inclination directions. I.e., to the drain electrode of a transistor (TR3) said number 3 (DE) and said parasitic capacitance electrode area elements with different inclination directions (PCE) (PCA3) drain electrode of the number 1 transistor (TR1) (PCE) (DE) and parasitic capacitance are electrode larger than area elements with different inclination directions (PCA1), pixel number 3 (PX3) result in parasitic capacitance (Cgd) is said number 1 pixel (PX1) in greater than parasitic capacitance (Cgd). Said number 1 and number 3 pixel (PX1, PX3) (Cgd) parasitic capacitance according to the difference in pixel number 3 and number 1 (PX1, PX3) in charge capacity of. unit as the operation of a current deviation voltage level.

Understructure is found in equations below, the storage capacitor (k) said quick back voltage (Cst) and liquid crystal capacitor (Clc) since inversely proportional to a magnitude of the, between pixels if the is the size of the pixel electrode, said quick back voltage between pixels (k) occurs a local. I.e., pixel electrode and storage line according to storage capacitor formed on the semiconductor substrate (Cst) difference and pixel transistor and the according to liquid crystal capacitor formed on the semiconductor substrate (Clc) between pixel by a difference in the detection voltage level. thereby cause variations.

1><expressions

Wherein Clc and capacity of the liquid crystal capacitor, which capacity of capacitor receives a storage Cst, Cgd has a gate source/drain conductive layer and in the ISDN switching, g has a gate a gate electrode is formed on gate on voltage and gate off and gate-off voltage difference value.

Understructure is found in 1 said expressions, said quick back voltage (Vkb) in each transistor a a pixel a coverage mask reflecting an is influenced to the, pixel electrode occurs variation of based on variations in size. For example, in the size of pixel region from relatively small number 1 number 2 pixel and minuter than one pixel, pixel regions are relatively large is less resistor is pixel number 3. The, each every pixel filling factor difference generating a, this lowers the Image quality.

In one in the embodiment of the present invention source/drain conductive layer in the ISDN switching (Cgd) by controlling the deviation of (k) of each pixel quick back voltage.. Specifically, said gate electrode and said parasitic capacitance between the source and drain electrodes (Cgd) said electrode and the parasitic capacitance of an area of overlap between drain electrode. For example, in the size of pixel region from relatively small number 1 in the case of pixel number 2 pixel and said formed on the semiconductor substrate so as to be less, relatively large in the size of pixel region from said pixel number 3 in the case of. and conditions the packet generator to large formed on the semiconductor substrate. Understructure is found in 1 said expressions, said quick back voltage a a pixel a coverage mask reflecting an (Vkb) in each transistor parasitic capacitance (Cgd) since-sensitive data, said pixels in each transistor with a different size by, said difference the size of the pixel electrode (k) due to quick back voltage can be for compensating deviation of. Quality of visual data according to an IEEE -.

According to one in the embodiment of the present invention, each pixel group the above-described structure limited not. Different size area according to, which coacts with a pixel having the first conductive layer to fill the different in using a deblocking filter imposes a significant deviation can be voltage level, the second different these configurations and for applying a transistor with is the decoration plate further comprises an.

Also in the embodiment according to Figure 5 shows a plane view of the present invention is shown in the pixel group one, Figure 6 shows a II-II ' ray according to cross section is of Figure 5. In the present in the embodiment, also in order to avoid duplication of described 2, also 3, 4a and 4b and also where otherwise a time as large as that of to illustrate the combine a rear cover.

Also refers to surface 5 and 6, the number 1 substrate (SUB1) said display device substrate (SUB1) opposed to said number 1 and number 2 substrate (SUB2), and said number 1 substrate (SUB1) and formed between the number 2 substrate (SUB2) includes liquid crystal layer (LC).

Said number 1 substrate (SUB1) number on the number 1 base substrate a predetermined pitch between metal lines and outliers (BS1), is made from a high-density wiring said number 1 transistor (TR1), said number 1 transistor (TR1) connected to the pixel electrodes contact the drain electrode (PE), and said pixel electrode (PE) insulating the common electrode is spaced apart and includes (CE).

Number 1 the gate line (GL1), parasitic capacitance electrode (PCE), and number 1 includes data line (DL1).

Said number 1 gate line (GL1) (BS1) on the number 1 base substrate number 1 direction (D1) is formed bars are supported from the side rails.

Said parasitic capacitance electrode (PCE) (GL1) projecting from the number 1 gate line or said number 1 gate line (GL1) is formed on a portion of the is ball number.

the number 1 gate line (DL1) said number 1 data line (GL1) and said gate insulating layer with respect to two non (GI) said number 1 number 2 direction transverse to a direction (D1) (D2) is ball number bars are supported from the side rails.

Said number 1 transistor (TR1) (GL1) and the number 1 gate line is connected to data line (DL1) said number 1. With a 1 also, in operation by all the pixels is made said data lines and said gate lines and, each including a plurality transistors ball number to a bar, each transistor a plurality of gate lines with a corresponding one of a plurality of data line is connected to a corresponding one of. Said number 1 transistor (TR1) has a gate electrode (GE), parasitic capacitance electrode (PCE), semiconductor pattern (SM), source electrode (SE), and a drain electrode includes (DE).

Said source electrode (SE) and said drain electrode, an interlayer film on the (DE) is ball number is (IL). Said interlayer film (IL) contains a fixing member to connect to the insulating material, for example, silicon nitride or, may include a silicon oxide.

Said interlayer film (IL) on are overlapped (PSV) is ball number is. Said protective film (PSV) for example, silicon nitride or, may include a silicon oxide.

Said interlayer film (IL) and said protective film (PSV) the part of the upper surface of the drain electrode (DE) (CH) is a contact hole exposing the is ball number.

Said pixel electrode (PE) number on the protective film (PSV) are ball, said contact hole (CH) through (DE) is connected to said drain electrode. Said a plurality branches of pixel electrode (PE) can take the. Said certain distance from one another the branches can be spaced, said common electrode (CE) can be, and an electric field with. The shape of the branches are not limited to, in a variety of shapes, may be ball number.

the said common electrode (CE) (PSV) said protective film, an interlayer film (IL) and may be ball number between the. Said common electrode (CE) to cover all the pixel areas along a first threading can be formed. The shape of the common electrode (CE) are not limited to, the pixel areas adjacent to each other are connected to one another in all of them the same common to which a voltage can be applied if may be ball number in different shapes in order. Wherein, said contact hole with ball number is (CH) to said common electrode (CE) reparing over-number is (OPN) has a opening, said common electrode (CE) and said pixel electrode (PE) the protective film (PSV) is insulating with respect to two non. Said common electrode (CE) and said pixel electrode (PE) and said protective film (PSV) storage capacitor of each pixel to form a (Cst).

Said number 2 substrate (SUB2) (SUB1) the number 1 substrate 1 comprises the rectangular plate like nut to oppose to the array substrate. The number 2 base substrate (SUB2) said number 2 substrate (BS2), (CF) color filter, and black matrix (BM) may comprise an.

In the present in the embodiment, said common electrode plate passing, has branches pixel electrode is said device said display the PLS (plane-to-line switching) mode. be able to operate with. However, said pixel electrode or common electrode, and it driving mode of the limited to not. For example, a plurality branches of said common electrode can be formed is. In this case, the branches said pixel electrode on a plane and said common electrode branches of IPS (in plane switching) are arranged distance from the stationary stages able to operate in KIPO &. In addition of the present invention general outline an ideal not against, the structure of said display device said PLS external grudge number mode IPS mode or which may have another mode is as well as.

Also 5 a again, in one in the embodiment of the present invention, also in the embodiment shown in 2, such as the of pixels, said number 1 transistor (TR1) to the drain electrode of a transistor (DE) (TR3) the area of the drain electrode of said number 3 (DE) than those of more larger. A portion of said drain electrode (DE) said gate insulating layer with respect to two non (GI) (PCE) said parasitic capacitance electrode that overlap that bar, said drain electrode (DE) according to the difference on the surface of the first said parasitic capacitance electrode (PCE). difference in addition area elements with different inclination directions. I.e., drain electrode of said number 3 transistor (TR3) (PCE) (DE) and parasitic capacitance are electrode area elements with different inclination directions drain electrode of said number 1 transistor (TR1) (PCE) (DE) and parasitic capacitance are electrode larger than area elements with different inclination directions, pixel number 3 (PX3) result in parasitic capacitance (Cgd) is pixel number 1 (PX1) in greater than parasitic capacitance (Cgd). In one in the embodiment of the present invention, said number 1 and number 3 pixel (PX1, PX3) (Cgd) parasitic capacitance according to the difference in pixel number 3 and number 1 (PX1, PX3) in charge capacity of. unit as the operation of a current deviation voltage level.

1 table a device display invention according to the existing device display in the embodiment according to one of the present invention and in, number 1 source and drain is connected to the each pixel number 3 examples of the compares voltage difference of data after an applies a gate signal constituted in the embodiment shown with codes is the simulation result. 5 door has said in the embodiment provides a construction disclosure to number 1 source and drain is connected to the data voltage pixel number 3 concerns a difference, compared to 5 also relate said disclosure structure and the parasitic capacitor is of a co-external grudge number, capacity parasitic capacitance pixel, in the case of no difference in pixel number 3 source and drain is connected to the number 1. which is indicative for a difference data voltage.

Pixel number 1 and positive examples compared said both said in the embodiment a channel length of 18 micrometers, a channel length of pixel number 3 for meshing into formed micrometers 32, the number 1 and number 3 pixel both satisfied by 99% filling factor has a value that is configured. Table a position at 1 indicative of the position is measurement of the data voltage as, predetermined size number after work grudge rectangular display panel, said display panel when two regions 9, indicative of the position center of each region of..

Table 1 with a, applies a gate signal constituted contemplated compared pixel number 3 source and drain is connected to the number 1 after difference data voltage 47. 9mV to 49. 7mV corresponding to but, applies a gate signal in the case of number 3 in the embodiment number 1 after 11 which includes a pattern such as the pixel data voltage difference. 7mV to 16. 0mV contrast e.g. the comparison of the showed very small value. The, number 1 number 3 source and drain is connected to the pixel in the ISDN switching different area which alter the number 1 and number 3 when kickback voltage deviation between pixels it was observed that be very small.

In group of pixels one said in the embodiment, number 1 pixel and having a same area pixel number 2, number 1 number 2 and number 3 pixel pixel of area greater than but in the embodiment it is shown a, limited to not. For example, display device has two or more of a pixel group may have.

Also in the embodiment in Figure 7 shows a one of the present invention, including group of two pixels. that is as planar as it is shown a device display.

Also with a 7, the device display in the embodiment according to one of the present invention pixel group number 2 and number 1 includes (PG1, PG2). Pixel group (PG1) said number 1 the number 1 to number 3 pixel (PX1, PX2, PX3) includes, said number 2 pixel group (PG2) the number 4 to number 6 pixel (PX4, PX5, PX6) includes. Said number 1 and number 2 pixel group (PG1, PG2) number 2 the number 1 direction (D1) and (D2) are arranged alternately in direction.

Said number 1 pixel group (PG1) in said number 1 to number 3 pixel (PX1, PX2, PX3) the number 1 direction (D1) is, said number 1 to number 3 pixel (PX1, PX2, PX3) at least one of the pixels may have is larger than. Of the present invention in one example, the number 1 (PX1) said number 1 pixel color, for example red (R) indicating that the portable computing device is, the number 2 (PX2) said number 2 pixel color, for example green (G), white color filters, respectively, the number 3 color pixel (PX3) said number 3, for example blue (B) a new line. Of the present invention in one example, said number 3 in Figure 13 converts the blue for displaying pixel (PX3) is said number 1 and number 2 pixel (PX1, PX2) is larger than but shown a structure having a SIGE buffer layer, the not one number.

Said number 2 pixel group (PG2) in said number 4 to number 6 pixel (PX4, PX5, PX6) the number 1 direction (D1) is, said number 4 to number 6 pixel (PX4, PX5, PX6) at least one of the pixels can take the is larger than. Of the present invention in one example, the number 4 (PX4) said number 4 pixel color, for example red (R) indicating that the portable computing device is, the number 5 (PX5) said number 5 pixel color, for example green (G), white color filters, respectively, the number 6 color pixel (PX6) said number 6, for example white (W) a new line. Of the present invention in one example, in Figure 13 has white (W) said number 6 for displaying pixel number 5 and said number 4 is pixel (PX6) (PX1, PX2) is larger than but shown a structure having a SIGE buffer layer, not limited to.

Said number 1 and number 2 pixel group (PG1, PG2) comprises a display a color each other can only be, substantially the same has a pixel structure. Thus, said number 1 and number 2 pixel group (PG1, PG2) a pixel structure to Figure 2 and described 4 since and overlaps a described, said number 1 and number 2 pixel group (PG1, PG2) the elucidation dispensed to a.

Or more but in the embodiment described by referring to, is a classic mirror server art corresponding a lead one skilled in the art of the present invention concept and region patent the following is claimed is within such a range that causes no away from the present invention various modified and change can be 2000 database for each consumer.