반도체 장치
The present invention refers to a semiconductor device are disclosed. For example, patent document 1 is provided with a plurality of avalanche photo diode preamplifiers mode each avalanche photo diode semiconductor substrate process output signals from a plurality of signal processing part is installed the mounting substrate semiconductor device is disclosed. Patent document 1 silicon nitride semiconductor device formed on the semiconductor substrate via a through hole (with a lead frame) side and a rear surface side of the electrical connection between the embodiment is coming in now. Semiconductor device such as described above (avalanche photo diode (APD) corresponding to) the photodetecting surface in a plurality of pixels in an area of amplifiers are enhanced with respect but preferably, each avalanche photo diode semiconductor substrate providing a through hole if through hole occupies reduce broadcast receiver of volume ratio. On the one hand, of disconnection of wiring in parallel to a through hole, a through hole of a semiconductor substrate through broadcast receiver ensure electrical connection. In particular, such as described above in avalanche photo diode-typed operating voltage applied to the semiconductor device, which can realize a semiconductor substrate between two of the through hole by the wiring ensured like disclosed. Thus, the present invention refers to a ratio of the volume occupied by the through hole in the semiconductor substrate while number billion, through a through hole of a semiconductor device to ensure the electrical connection number [...] intended. The semiconductor device of the present invention are selected from the number 1 and number 2 ([...]) opposite one surface having a surface, a through hole is formed from the surface number 1 and number 2 semiconductor substrate surface, surface number 1 are provided in front surface located above the wiring computers ball number 1 number 1 number 1, number 2 number 2 on the surface side of the surface of the through hole through an opening of the inner and number 2 through hole continuous insulating layer, are provided in the insulation layer in the insulating layer in at number 1 number 1 and number 2 is electrically connected to a wiring having a wiring surface side, vertical hole and the through hole, the through hole with respect to the plane of the tail cone of center line along a side regions noted in each of the cases, insulating layer corresponding to the edges of the opening number 1 number 2 points corresponding to edges of the opening the line segment connecting the number 1 and number 2 point a, number 2 number 2 with respect to the insulation layer in the opening corresponding to a point where the line segment connecting the number 2 and number 3 point, at which point a line segment connecting point number 3 number 1 number 3, line number 1 through hole with respect to the inner surface sides of the insulation layer correspond to the number 1 position, line number 1, number 2 segment, segment number 2 and number 3 surrounded by the insulation layer in the area and, line number 3 for the insulation layer is greater than the sum of number 3 area located opposite the inner surface of the through hole. The semiconductor device has a through ball center line along a side regions with respect to the plane of the tail cone noted in each of the cases, the aforementioned number 1 and number 2 area and greater than the sum of the aforementioned area number 3 area, so that there is in addition the aforementioned number 3 area insulating layer formed in the semiconductor substrate. The, number 2 cover the edges of the opening surface of the insulating layer is less average inclination angle (i.e., gently) Jim and simultaneously, the corresponding partial thickness of 2000 is reserved. The, vertical hole through hole when, number 2 disconnection of wiring, number 2 wiring and semiconductor substrate for suppressing leakage current in the vicinity of the opening are prevented from generating such further making it easier for the number 2. In addition, because a vertical hole through hole, the through hole number 1 number 2 from spreading toward the surface of the semiconductor substrate from the surface taper (taper) holes not to induce, in the ratio of the volume of the semiconductor substrate through the ball billion number with each other. This number 1 number 2 for wiring the wirings are connected from the surface is the same as the periphery of the device region need when a through hole of an opening part area number 1, number 2 from the surface toward the surface of the semiconductor substrate while a purge tapered hole number 1, number 1 number 2 from the surface of the semiconductor substrate toward the surface of the vertical hole is substantially purge but disclosed. Due to or more, the semiconductor device, the through hole in the semiconductor substrate while number ratio of volume occupied by billion, ensure electrical connection can be through a through hole of the semiconductor substrate. In addition, provide the means by which the inner surface of the vertical hole through hole (such as curved surface curved circumferential surface of an inner surface of the through hole if [...]) is with respect to the surface an angle number 1 (i.e., through ball center line along a transverse with respect to the plane of the centreline of the side regions each of the noted when, corresponding plane surface an angle between the inner surface of the through hole with the intersection number 1 average) is 80о -100о (More preferably 85о -95о ) In a through hole big. According to one aspect of the present invention in the insulation layer in the semiconductor device than that of the insulation layer at the point number 1 number 3 point are also the angle of tilt of the stacker. Thus, for example through the ball diameter and number 2 ([...]) cover the edges of the opening of the surface of insulating layer even when smaller angle (i.e., gentle angle) while maintaining the average angle of tilt, ensuring a sufficient width number 1 can be an insulating layer of an opening on the surface side of the semiconductor substrate. The, cover the edges of the opening to prevent disconnection of wiring insulating layer number 2 as well as in number 2, number 1 number 2 can prevent disconnection of wiring in an opening portion of the wiring. According to one aspect of the present invention semiconductor device provided on the inner surface of the insulation layer in the through hole in the inner surface of the through holes are even less than average inclination angle average inclination angle. Thus, for example insulating layer along an inner surface of the through hole formed in a uniform thickness compared with power consumption, number 2 opening side of the semiconductor substrate for formation of wiring number 2 can reliably embodiment hereinafter. In addition, average inclination angle of the inner surface of the through hole of the inner surface of the through holes (such as curved surface curved circumferential surface of an inner surface of the through hole if [...]) orthogonal to the surface of the semiconductor substrate and number 1, number 1 90 against an inner surface of the through holeо Angle of also be the case multiple myelomas are included. According to one aspect of the present invention in semiconductor device through ball center line along a transverse plane, each of both sides of the centreline when noted, with respect to the distance between the point corresponding to the edges of the opening number 1 number 1 number 4 are also condiments than the insulation layer opening. For example, the case of forming the insulating layer of the semiconductor substrate opening number 2 from the opening, and the opening of the insulating layer on the surface side of the semiconductor substrate spaced apart from the surface number 1 number 2 since, corresponding opening size, location deviation does easy one. The aforementioned number 1 number 4 larger than a distance between a point on the surface side insulating layer by the opening number 1, corresponding opening size, variations of position can drain regions. In addition, number 4 by taking point between a distance of number 1, number 2 and cover the thick insulating layer edges of the opening of the through hole, the through hole of cover the edges of the opening surface of the insulating layer in addition number 2 is provided to facilitate the design resulting in reduced average inclination angle. In addition, insulating layer number 1 opening width (rectangle) is spherical opening surface side when opening distance between the wearer and, when the opening diameter circular openings ([...]) is big. According to one aspect of the present invention semiconductor device in which a portion of the wiring pad for covering the opening number 1 number 1, number 1 edges of the opening and the distance between the edges of the opening exposed insulating layer number 1 edges of the opening and an intersection of condiments also with each other. As described above, the case of forming the insulating layer of the semiconductor substrate from the opening number 2 opening, corresponding opening size, but that is prone position, number 1 edges of the opening and insulating layer disposed between the edges of pad part number 1 is longer than a distance between edges of the opening edges of the opening by, corresponding opening size, variations of position can drain regions. In addition, point by point distance of number 4 take number 1, number 2 and cover the thick insulating layer edges of the opening of the through hole, the through hole of cover the edges of the opening surface of the insulating layer in addition number 2 is provided to facilitate the design resulting in reduced average inclination angle. According to one aspect of the present invention semiconductor device through hole in depth of opening size (aspect ratio) is divided by width number 2 are fig. 1 hereinafter. Thus, the insulation layer in the wiring can be reliably formed for the number 2 hereinafter. In addition, cover the edges of the opening of the surface of insulating layer number 2 less than the average angle of tilt (i.e., round through), the corresponding partial of number 2 disconnection of wiring can be more surely prevented. In addition, hereinafter for opening and reliably insulating layer can be formed. Depth of number 1 and number 2 stores opening distance between the through hole and opening means, opening width number 2 number 2 number 2 opening spherical distance between opening if the wearer, if big number 2 number 2 opening circular opening diameter. In the semiconductor device of the present invention even if one insulating layer resin are disclosed. Thus, that has an insulating layer is shaped as described above and hereinafter for can be surely prevented. According to one aspect of the present invention in semiconductor device, the insulation layer in the inner surface of the continuous surface configured as a through hole provided even when with each other. Thus, since the insulation layer in the relaxed stress concentration peak of number 2 disconnection of wiring can be more surely prevented. According to one aspect of the present invention semiconductor device provided in the insulation layer in the through hole and the inner surface of the insulation layer in the surface number 2 provided even when now configured as a continuous surface. The, since the thickness of the portion of insulating layer covering the edges of the opening is reserved number 2, number 2 number 2 semiconductor substrate leakage current in the vicinity of the wiring opening can be prevent. In addition, the surface of the insulating layer cover the edges of the opening so smooth number 2, number 2 number 2 in the vicinity of the opening to prevent the occurrence of disconnection of wiring can be. According to one aspect of the present invention provided with the surface of a semiconductor device comprises a plurality of number 3 wiring number 3, number 2 ([...]) surface opposing the surface number 3 arranged to the mounting substrate also having, preamplifiers semiconductor substrate is provided with a plurality of avalanche photo diode mode of operation, through hole, number 1 wiring, and number 2 wiring includes a plurality of avalanche photo diode corresponding to each of a plurality of avalanche photo diode provided with a corresponding number 1 to each of the corresponding number 2 wiring electrically connected to the wire, each of the plurality of bump electrodes corresponding number 2 through number 3 wiring electrically connected to the wiring in the ceramics disclosed. The photodetecting surface in such semiconductor device in which a plurality of pixels (corresponding to avalanche photo diode) but increase the area of amplifiers are preferably, each avalanche photo diode is installed through hole in the semiconductor substrate through hole number ratio of volume occupied by billion specifies a disclosed. Another, of disconnection of wiring of the semiconductor substrate through a through hole of the through hole to protect electrical connection ensure want disclosed. In particular, in such semiconductor device operating voltage applied to the avalanche photo diode-typed, ensured by the wiring insulation semiconductor substrate wherein a through hole like disclosed. According to the semiconductor device, as described above, a ratio of the volume of the semiconductor substrate through the ball while number billion, ensure electrical connection can be through a through hole of the semiconductor substrate, the through hole in the semiconductor substrate occupied by the number of volume ratio billion, to ensure electrical connection through a through hole of the semiconductor substrate, and a through hole between two semiconductor substrate so as to attain the ensured by the wiring can be realized. According to the present invention, ratio of volume occupied while number billion through hole in the semiconductor substrate, a through hole of a semiconductor substrate through a semiconductor device number [...] ensure electrical connection can be via the network. Figure 1 shows a device of the present invention of one embodiment type semiconductor sensors mounted thereon also are disclosed. Figure 2 shows a semiconductor device of cross-sectional drawing of Figure 1 are disclosed. Figure 3 shows a plane view of Figure 1 of semiconductor light detecting element of semiconductor device are disclosed. Figure 4 shows a bottom view of Figure 1 of semiconductor light detecting element of semiconductor device are disclosed. Figure 5 shows a plane view of Figure 1 of the mounting substrate of semiconductor device are disclosed. Figure 6 shows a circuit diagram of Figure 1 of semiconductor device are disclosed. Figure 7 shows a portion of the semiconductor device are disclosed cross-sectional drawing of Figure 1. Figure 8 shows a portion of a through hole of a semiconductor device are disclosed cross-sectional drawing of Figure 1 and its peripherals. Figure 9 shows a portion of a through hole of a semiconductor device are disclosed cross-sectional drawing of Figure 1 and its peripherals. Figure 10 shows a partial cross-sections of reference type semiconductor device also are disclosed. Figure 11 shows a portion of a through hole of a semiconductor device are disclosed cross-sectional drawing of Figure 10 and its peripherals. Semiconductor device of Figure 12 (a) and (b) of Figure 10 includes a number of the plurality of process tank cross-sectional drawing to explain the method are disclosed. Semiconductor device of Figure 13 (a) and (b) of Figure 10 includes a number of the plurality of process tank cross-sectional drawing to explain the method are disclosed. Semiconductor device of Figure 14 (a) and (b) of Figure 10 includes a number of the plurality of process tank cross-sectional drawing to explain the method are disclosed. Figure 15 shows a semiconductor device portion of variants of cross-sectional drawing of Figure 10 are disclosed. Figure 16 shows a semiconductor device portion of variants of cross-sectional drawing of Figure 10 are disclosed. Figure 17 shows a semiconductor device portion of variants of cross-sectional drawing of Figure 10 are disclosed. Hereinafter, with respect to the form of the present invention embodiment, with reference to the drawing detailed as follows. In addition, the same for each drawing a substantial portion or disconnecting the same heating code, redundant description supplied from a substrate. [Configuration of semiconductor device] As shown in the fig. 1, semiconductor device (1) includes a semiconductor light detecting element (110) on, mounting substrate (120) and, light transmitting substrate (130) etc. with. A mounting substrate (120) is semiconductor light detecting element (110) arranged opposite to the nanometer range. Light-transmitting substrate (130) is semiconductor light detecting element (110) arranged opposite to the nanometer range. Semiconductor light detecting element (110) includes a mounting substrate (120) light transmission substrate (130) disposed between in the nanometer range. Semiconductor light detecting element (110) designed to illuminated photodiode array PDA1 consists of. In the photodiode array PDA1 when viewed ([...]) (light-transmitting substrate (130) and semiconductor light detecting element (110) when viewed in the direction opposite each other) semiconductor substrate spherical shapes (2) valuable minerals. Also as shown in the variation 2, semiconductor substrate (2) opposing the inner peripheral surface (surface number 1) (2a) and the inner peripheral surface (surface number 2) (2b) valuable minerals. Semiconductor substrate (2) is made of a Si semiconductor substrate N type (number 1 conductivity type) are disclosed. PDA1 photodiode array semiconductor substrate (2) contains a plurality of avalanche photo diode (APD) formed. One avalanche photo diode (APD) photodiode array PDA1 etc. is one of the metal. Each avalanche photo diode (APD) coupled in series with the resistance R1 and the interval between the respective (quenching), etc. are connected in parallel to each other. Each avalanche photo diode (APD) applied reverse bias voltage from a power source is attached. Avalanche photo diode (APD) carry output current from SP are detected by the signal processing unit. Each avalanche photo diode (APD) P type (number 2 conductivity type) is number 1 of P type semiconductor region 1PA 1PB etc. of number 2 having on (number 2 conductivity type) semiconductor region. Number 1 1PA semiconductor region includes a substrate (2) primary surface (2a) side region of in the nanometer range. Number 1 and number 2 semiconductor region formed in the semiconductor region 1PA 1PB, etc. higher impurity concentration semiconductor region 1PA number 1. 1PB is number 2 semiconductor region when viewed polygons in (the embodiment in one form octagon) of shapes disclosed. Number 1 number 2 semiconductor region deeper than the depth of semiconductor region 1PA 1PB. Semiconductor substrate (2) is N type semiconductor region 1PC (number 1 conductivity type) has disclosed. 1PC semiconductor region includes a substrate (2) primary surface (2a) within one side, carry through holes (7) formed in a position corresponding to over. 1PC semiconductor region is N-type semiconductor substrate (2) and P type semiconductor region number 1 1PA PN junction formed between the through holes (7) servicing the exposed. Also 2, 3 also, and also 7 as shown in the variation, each avalanche photo diode (APD) is number 1 wiring (3) valuable minerals. Number 1 wiring (3) dielectric is (4) over the semiconductor substrate (2) primary surface (2a) formed on in the nanometer range. Number 1 wiring (3) dielectric is (4) through openings formed, semiconductor region 1PB number 2 is connected to disclosed. Number 1 wiring (3) when viewed in the through hole (7) disposed on the pad part (3a) has disclosed. Number 1 through number 1 number 2 semiconductor region comprises a semiconductor region 1PA 1PB wiring (3) electrically connected in the nanometer range. In addition, appearing in Figure 3 is also 2 oxide film (4) exposed in the nanometer range. Also 2, 4 also, and also 7 as shown in the variation, each avalanche photo diode (APD) is number 2 wiring (8) valuable minerals. Number 2 wiring (8) an insulating layer (10) through, the through hole (7) with the inner and semiconductor substrate (2) primary surface (2b) formed in the nanometer range. Number 2 wiring (8) number 2 semiconductor region on the semiconductor substrate when viewed with respect to the overlapping 1PB (2) primary surface (2b) disposed on the pad part (8a) has disclosed. Semiconductor substrate (2) primary surface (2b) of a semiconductor substrate (2) electrically connected to the electrode (not shown) formed in the nanometer range. In addition, in Figure 4 is also 2 on a resin protective layer (21) exposed in the nanometer range. Also as shown in the variation 2 and 7 also, through hole (7) is avalanche photo diode (APD) each formed in the semiconductor substrate. Each avalanche photo diode (APD) number 1 in wiring (3) and number 2 wiring (8) includes a through hole (7) electrically connected to each other through over. As shown in the 3 also, through holes (7) at the avalanche photo diode (APD) planar between are located in regions of the nanometer range. The embodiment includes a row number 1 (APD) in one form avalanche photo diode (nth M) number 1 and number 2 N M direction orthogonal direction to heat (nth N) 2 dimensional direction arranged in the form in the nanometer range. The through hole (7) in a region surrounded by the number 1 of 4 1PA semiconductor region disposed a. The through hole (7) is avalanche photo diode (APD) since installed near, row number 1 and number 2 N M direction 2 dimensional obtained be direction into heat. Number 1 wiring (3) and number 2 wiring (8) Al the energy to the combustion chamber. Semiconductor substrate (2) in addition to the Si case electrode materials include Al, Au, Cu, Ti, Ni, Pt, or laminate such as be used now. Number 1 wiring (3) and number 2 wiring (8) method for forming it, a spatter (spatter) can be manufacturing method. Semiconductor substrate (2) to the P-type impurity such as Si in case 3 B as elements are used, N-type impurities include N, P, such as As 5 element-used substrate. N P type semiconductor having a conductivity type each other even if the substituted element, can be equally enabling corresponding element. Method such as addition of impurities, diffusion method, ion implantation can be to one side. Oxide layer (4) is fitted in an opening, SiO2 The vibration-damping material be. SiO2 Consisting of oxide film (4) as the forming method, CVD (Chemical Vapor Deposition), exposing, such as spatter can be using. In addition, oxide film (4) in place, such as SiN provided other insulating material insulating layer may be disclosed. Also as shown in the variation 2, mounting substrate (120) opposing the inner peripheral surface (surface number 3) (120a) and the inner peripheral surface (120b) valuable minerals. A mounting substrate (120) at the planar spherical shapes disclosed. The inner peripheral surface (120a) semiconductor substrate (2) primary surface (2b) a space disclosed. A mounting substrate (120) comprises a main surface (120a) formed on a plurality of number 3 wiring (121) valuable minerals. Number 3 wiring (121) is number 2 wiring (8) pad part of (8a) is opposed to the inner peripheral surface (120a) disposed on the nanometer range. Semiconductor substrate (2) side (2c) and a mounting substrate (120) side (120c) over the same surface. I.e., when viewed in the semiconductor substrate (2) penetrating the mounting substrate (120) etc. penetrating coincide. Number 2 wiring (8) and number 3 wiring (121) bump electrodes is from the ice bank ([...]) electrode (9) electrically connected to each other through over. The, number 1 number 2 semiconductor region 1PB is wiring (3), number 2 wiring (8), and extraction electrode (9) number 3 through wiring (121) electrically connected in the nanometer range. Number 3 wiring (121) is number 1 wiring (3) and number 2 wiring (8) as well as, Al energy to the combustion chamber. In addition to electrode materials include Al, Au, Cu, Ti, Ni, Pt, or laminate such as be used now. The lead electrodes (9) in terms of solder or the like. The lead electrodes (9) through the UBM (Under Bump Metal), number 2 wiring (8) pad part of (8a) formed on in the nanometer range. The UBM electrodes (9) consisting of material with excellent electrical and physical connection. Method for forming electroless plating UBM can be provided to one side. The lead electrodes (9) method for forming solder balls mounted it the wirings, printing can be to one side. As shown in the variation also 5, mounting substrate (120) includes a plurality of panels and a plurality of signal processing unit SP resistance R1 has disclosed. A mounting substrate (120) ASIC (Application Specific Integrated Circuit) is adapted in such a way disclosed. In addition, 2 also appears in Figure 5 shows a passivation (passivation) film (122) exposed in the nanometer range. Each interval between the resistance R1 and the inner peripheral surface (120a) disposed on the nanometer range. One end of each centering resistance R1 corresponding number 3 wiring (121) and is connected to, the interval between the resistance R1 is connected to the common electrode at the other end of each CE 2000. The interval between the resistance R1 etc. manual matching circuit each. The interval between the resistance R1 are parallelly connected to common electrode over a plurality of CE. SP each signal processing section includes a main surface (120a) disposed on the nanometer range. SP each signal processing section to an input port of a corresponding number 3 wiring (121) connected to, and output to the corresponding signal line TL SP each signal processing section connected to the disclosed. SP each signal processing section is number 1 wiring (3), number 2 wiring (8), with the lead electrodes (9) and number 3 wiring (121) each avalanche photo diode (APD) through the output signal from the input thereto. Respective avalanche photo diode (APD) SP each signal processing section for processing the output signal from the other. Respective avalanche photo diode (APD) digital pulse signal output from the signal processing unit SP converting contains CMOS circuit. A mounting substrate (120) primary surface (120a) on, electrodes (9) with an opening formed in a position corresponding to passivation film (122) disposed in the nanometer range. Passivation film (122) SiN is like combustion chamber. Passivation film (122) forming method include CVD (Chemical Vapor Deposition) using such as can be. Also as shown in the variation 2, light transmitting substrate (130) and the inner peripheral surface opposing (130a) and the inner peripheral surface (130b) valuable minerals. Light-transmitting substrate (130) at the planar spherical shapes disclosed. Light-transmitting substrate (130) is consisting of an optically transmissive material such as glass. The inner peripheral surface (130b) semiconductor substrate (2) primary surface (2a) a space disclosed. Light-transmitting substrate (130) and semiconductor light detecting element (110) has an optical adhesive number by an adhesive layer (6) optical by and physically connected disclosed. In addition, light transmitting substrate (130) primary surface (130a) is an adhesive number by scintillator (scintillator) is when connected and physically optical flow tides. In this case, a scintillator scintillation light is from transmitting substrate (130) matched by the, semiconductor light detecting element (110) is obliquely incident on a substrate. Semiconductor substrate (2) side (2c) light transmission substrate (130) side (130c) over the same surface. I.e., when viewed in the semiconductor substrate (2) elastic sheet and a light-transmitting substrate (130) etc. penetrating coincide. Distilled semiconductor device (1) in N-type semiconductor substrate (semiconductor light detecting element (110)) (2) number 1 and P type semiconductor region between the 1PA PN junction is constructed, avalanche photo diode (APD) is formed in the nanometer range. Semiconductor substrate (2) comprises a main surface (2b) (not shown) are electrically connected to the second, number 1 through number 2 semiconductor region comprises a semiconductor region 1PA 1PB, number 1 wiring (3) electrically connected in the nanometer range. As shown in the 6 also, the avalanche photo diode (APD) the interval between the resistance R1 connected in series in the nanometer range. Each avalanche photo diode (APD) returning a photodiode array PDA1 preamplifiers mode. (APD) preamplifiers mode avalanche photo diode (APD) greater than break down voltage (reverse bias voltage) of a reverse direction voltage applies a avalanche photo diode anode/cathode. I.e., anode (-) is a potential V1, V2 (+) potential cathode is applies. The polarity of this potential to prevent the relative, one potential to ground potential also be disclosed. Number 1 and P type semiconductor region 1PA anode, cathode N-type semiconductor substrate (2) are disclosed. Avalanche photo diode (APD) is positioned to receive light (photon), photoelectric conversion is made within substrate, optoelectronic is generated. Number 1 of avalanche multiplying ([...]) method for a semiconductor region 1PA PN area close to a semiconductor substrate made in an amplified electronic group (2) are transmitted through the electrode formed toward the rear (with a lead frame). I.e., semiconductor light detecting element (110) (photodiode array PDA1) (avalanche photo diode (APD)) either is positioned to receive light (photon) pixel, doubling to, signal wiring number 3 (121) corresponding signal processing unit SP exiting the input thereto. [Peripheral portion of the through hole and] Also as shown in the variation 7, semiconductor substrate (2) comprises a main surface (2a) in the inner peripheral surface (2b) that extends into a through hole (7) formed in the nanometer range. Through holes (7) opening of number 1 (7a) includes a substrate (2) primary surface (2a) and can be located, through holes (7) opening of number 2 (7b) includes a substrate (2) primary surface (2b) of the cell disclosed. Number 1 opening (7a) is oxide (4) to an opening (4a) and can be continuously on, number 1 wiring (3) pad part of (3a) covered by the nanometer range. I.e., through holes (7) opening of number 1 (7a) number 1 on wiring (3) which is part of the pad part (3a) is being located. The through hole (7) vertical holes are disclosed. I.e., through hole (7) on the inner surface of (7c) (through hole (7) on the inner surface of (7c) and a cylindrical surface is curved such as curved surface of case [...]) primary surface (2a) to an angle (i.e., the through hole (7) centerline CL including with respect to the plane, centerline CL at both sides of each of the interest in case the plane and the through hole (7) on the inner surface of (7c) the intersection with the inner peripheral surface (2a) to an angle average) is 80о -100о (More preferably 85о -95о ) To be disclosed. The embodiment in one form through holes (7) comprises a main surface (2a, 2b) having orthogonal to centerline CL columnar in the nanometer range. In this case, the through hole (7) on the inner surface of (7c) to the main surface (2a, 2b) and orthogonal to a surface, the through hole (7) on the inner surface of (7c) primary surface (2a) to the blade 90о To in the nanometer range. The through hole (7) is of the size 1 hereinafter. A through hole size (7) depth of (number 1 opening (7a) number 2 on opening (7b) distance between) opening a number 2 (7b) width (number 2 opening (7b) a spherical case number 2 opening (7b) of concave distance between, number 2 opening (7b) number 2 is a circular opening (7b) diameter) divided by value. For example, the through hole (7) and the depth of 20 μm, number 2 opening (7b) the width of the 30 μm are disclosed. In this case, a size 0. 667 Is with each other. In addition, circular cylinder, having the shape of a square column shape or the like through hole (7) is, for example dry etching (dry etching) formed by. The through hole (7) on the inner surface of (7c) and semiconductor substrate (2) primary surface (2b) made of resin ([...]) insulating layer (10) is provided with a disclosed. Insulating layer (10) includes a through hole (7) opening of number 2 (7b) etc. in series through. Insulating layer (10) includes a through hole (7) inside the oxide (4) opening (4a) number 1 through wiring (3) pad part of (3a) which reaching, semiconductor substrate (2) primary surface (2a) side opening (10a) has disclosed. Insulating layer (10) surface (10b) (through hole (7) on the inner surface of (7c) and semiconductor substrate (2) primary surface (2b) opposite to the side surface) is number 2 wiring (8) provided in the nanometer range. Number 2 wiring (8) an insulating layer (10) opening (10a) number 1 in wiring (3) pad part of (3a) electrically connected in the nanometer range. Number 2 wiring (8) from the ice bank the bump electrodes electrode (9) disposed pad part (8a) and a number [...] resin protective layer (21) covered by the nanometer range. Above the insulating layer (10) for, also with reference to the 8 and 9 also extra each other. In addition, a light-transmitting substrate also in Figure 9 and 8 (5), adhesive layer (6), with the lead electrodes (9), and the resin protective layer (21) such as exposed in the nanometer range. Respective configuration of Figure 7 and 8 and also in Figure 9 is superposed on when reverse from 2000 counts the number represented. As shown in the variation also 8, insulating layer (10) surface (10b) includes a through hole (7) opening inside the number 1 (7a) reaching the number 1 region (11) and, through holes (7) opening inside the number 2 (7b) reaching the number 2 region (12) and, through hole (7) on the outside of the semiconductor substrate (2) primary surface (2b) opposite the number 3 area (13) comprises. Number 1 region (11) semiconductor substrate (2) primary surface (2a) in the inner peripheral surface (2b) area on taper spreading toward are disclosed. Number 1 region (11) having an average inclination angle α etc.. Number 1 region (11) implies an average inclination angle α through hole (7) with respect to the plane including the centerline of CL, centerline CL when one side of the area of interest, corresponding plane number 1 region (11) the intersection with the inner peripheral surface (2a) to average an angle are disclosed. A straight line if the intersection corresponding to the substantially straight inner peripheral surface (2a) become the number 1 region (11) is under or over average inclination angle α. The curve is formed by a tangent curve corresponding intersection if the inner peripheral surface (2a) is an angle between the calculated average number 1 region (11) is under or over average inclination angle α. Number 1 region (11) average inclination angle α is 0о Greater than 90 andо Less than. Number 2 region (12) semiconductor substrate (2) primary surface (2a) in the inner peripheral surface (2b) area on taper spreading toward are disclosed. Number 2 region (12) having an average inclination angle β etc.. Number 2 region (12) implies average inclination angle β through hole (7) with respect to the plane including the centerline of one side of centerline CL CL when the area of interest, corresponding plane number 2 region (12) the intersection with the inner peripheral surface (2a) to average an angle are disclosed. Corresponding intersection when the straight line, a straight line and the inner peripheral surface (2a) become the number 2 region (12) is under or over average inclination angle β. The curve is formed by a tangent curve corresponding intersection if the inner peripheral surface (2a) is an angle between the calculated average number 2 region (12) is under or over average inclination angle β. Number 2 region (12) average inclination angle β is 0о Greater than 90 andо Less than. Number 2 region (12) average inclination angle β is number 1 region (11) less than the average inclination angle α. I.e., number 2 region (12) is number 1 region (11) inclination operation in a region having a disclosed. In addition, number 2 region (12) average inclination angle β has a through hole (7) on the inner surface of (7c) γ average inclination angle (in which case, 90о ) Less than the. I.e., number 2 region (12) includes a through hole (7) on the inner surface of (7c) inclination operation in a region having a disclosed. The embodiment in one form number 1 region (11) average inclination angle α is number 2 region (12) than average inclination angle β through hole (7) on the inner surface of (7c) to average inclination angle γ Christ. Here through holes (7) on the inner surface of (7c) throughout the average inclination angle γ number 1 region (11) throughout the region number 2 average inclination angle α (12) average inclination angle β to the nanometer range. The through hole (7) on the inner surface of (7c) γ average inclination angle has a through hole (7) with respect to the plane including the centerline of CL, centerline CL when one side of the area of interest, inner surface of the corresponding plane (7c) the intersection and the inner peripheral surface (2a) to average an angle are disclosed. A straight line if the intersection corresponding to the substantially straight inner peripheral surface (2a) become the through hole (7) on the inner surface of (7c) γ average inclination angle is under or over. The curve is formed by a tangent curve corresponding intersection if the inner peripheral surface (2a) and the mean angle formed by the through hole (7) on the inner surface of (7c) γ average inclination angle is under or over. Insulating layer (10) surface (10b) the number 4 region (14) and number 5 region (15) results are. Number 1 region (11) includes a through hole (7) on the inner surface of (7c) is provided on the insulating layer (10) surface (10b) of number 4 area (14) than through holes (7) opening of number 1 (7a) side (through hole (7) in a direction parallel to the centerline of CL number 1 in opening (7a) side) is a region of the disclosed. Number 2 region (12) includes a through hole (7) on the inner surface of (7c) is provided on the insulating layer (10) surface (10b) of number 4 area (14) than through holes (7) opening of number 2 (7b) side (through holes (7) opening in a direction parallel to the centerline of CL number 2 (7b) side) and a region of the, number 4 region (14) and number 5 region (15) in an area between the are disclosed. Number 4 region (14) is number 1 region (11) and number 2 region (12) to continuously being curved disclosed. I.e., number 4 region (14) and the rounded curved, number 1 region (11) and number 2 region (12) and for connection or a metal silicide layer. Wherein, number 4 region (14) is present and is not home, number 1 region (11) semiconductor substrate (2) primary surface (2b) extend side, number 2 region (12) semiconductor substrate (2) primary surface (2a) extending side when, number 1 region (11) and number 2 region (12) intersection by (edge, a prescribed) formed therein. Number 4 region (14) formed when a corresponding intersection (edge, a prescribed) R chamfering ([...]) is equal to a curved. Number 4 region (14) includes a through hole (7) with respect to the plane including the centerline of CL, centerline CL when one side of the area of interest, corresponding plane surface (10b) intersection of number 1 region (11) parts and number 2 region (12) between parts through hole (7) on the inner surface of (7c) to cover the portions of the opposite side is formed on disclosed. Number 5 region (15) includes a through hole (7) opening of number 2 (7b) and along an edge of, number 2 region (12) and number 3 region (13) and connected to continuously being curved disclosed. I.e., number 5 region (15) and the rounded curved, number 2 region (12) and number 3 region (13) and for connection or a metal silicide layer. Wherein, number 5 region (15) is not there is thus set to the, number 2 region (12) semiconductor substrate (2) primary surface (2b) side faster and, number 3 region (13) the trough holes (7) extends toward the centerline of CL when, number 2 region (12) and number 3 region (13) intersection by (edge, such as a prescribed) formed therein. Number 5 region (15) formed when a corresponding intersection (edge, such as a prescribed) R chamfering applied is equal to a curved. Number 5 region (15) includes a through hole (7) with respect to the plane including the centerline of one side of centerline CL CL when area of interest, corresponding plane surface (10b) of intersection with number 2 region (12) and parts number 3 region (13) between the through hole parts (7) of number 2 opening (7b) in contrast to a side edge of the convex shape is formed on disclosed. The embodiment form at least number 4 region (14), number 2 region (12), and number 5 region (15) includes a through hole (7) on the inner surface of (7c) to cover the curved convex curved opposite side are disclosed. Number 3 region (13) semiconductor substrate (2) primary surface (2b) substantially parallel plane are disclosed. As described above, number 4 region (14) is number 1 region (11) and number 2 region (12) and connected to continuously being curved, number 5 region (15) is number 2 region (12) and number 3 region (13) is connected so that the curved continuously, insulating layer (10) surface (10b) consecutive surface (surfaces with intersection (edge, bending portion of) such as discontinuous portion is found without, each region (11, 12, 13, 14, 15) head is releasably connected to the surface) to be disclosed. The through hole (7) on the inner surface of (7c) is provided on the insulating layer (10) the average thickness of the semiconductor substrate (2) primary surface (2b) is provided on the insulating layer (10) is greater than an average thickness of. The through hole (7) on the inner surface of (7c) is provided on the insulating layer (10) the average thickness of the inner surface (7c) in a direction perpendicular to the insulating layer (10) is the thickness of the average. Semiconductor substrate (2) primary surface (2b) is provided on the insulating layer (10) the average thickness of the inner peripheral surface (2b) in a direction perpendicular to the insulating layer (10) is the thickness of the average. Semiconductor substrate (2) primary surface (2a, 2b) in a direction parallel to the insulating layer (10) of number 1 region (11) parts the average thickness of the insulating layer (10) of number 2 region (12) is greater than an average thickness of parts. Semiconductor substrate (2) primary surface (2a, 2b) in a direction parallel to the insulating layer (10) of number 1 region (11) the average thickness of the corresponding parts in the direction of the number 1 region (11) and the through hole (7) on the inner surface of (7c) of the distance between the average are disclosed. Semiconductor substrate (2) primary surface (2a, 2b) in a direction parallel to the insulating layer (10) of number 2 region (12) the average thickness of the corresponding parts in the direction of the number 2 region (12) and the through hole (7) on the inner surface of (7c) of the distance between the average are disclosed. Insulating layer (10) in number 1 region (11) includes a through hole (7) on the inner surface of (7c) is provided on the insulating layer (10) of semiconductor substrate (2) primary surface (2a) of the portion having a height H from the surface are disclosed. Height H includes a substrate (2) (i.e., the inner peripheral surface (2a) and the inner peripheral surface (2b) distance between) the thickness of the semiconductor substrate (2) primary surface (2b) is provided on the insulating layer (10) of the average thickness of the sum of the 2/3 hereinafter D are disclosed. Insulating layer (10) the insulating layer (10) opening (10a) of edges and a through hole (7) opening of number 2 (7b) through the edge of the interface as a S, S for the through hole (7) on the inner surface of (7c) side portions of P1, and surface S to through hole (7) on the inner surface of (7c) varies the opposite side portion P2, P1 P2 portion greater than the volume of the volume of the portion. In addition, insulating layer (10) in the through hole (7) with respect to the plane including the centerline of one side of the centerline CL CL area of interest, the area of triangle T1 T2 greater than the area of the triangle. The triangle T1 through hole (7) in a plane (i.e., the cross-section of Figure 8) CL centerline comprising through holes (7) opening of number 1 (7a) edge, through holes (7) opening of number 2 (7b) edge of, and insulting layer (10) opening (10a) is composed edge of the triangular are disclosed. Triangle T2 has a through hole (7) in (i.e., the cross-section of Figure 8) CL centerline planes including the insulating layer (10) opening (10a) edge, through holes (7) opening of number 2 (7b) edge of, and number 4 region (14) is composed a triangular cone frustum ([...]) are disclosed. Wherein, the through hole (7) with respect to the plane including the centerline of CL CL at both sides of the centerline each case noted described substrate. As shown in the variation also 9, insulating layer (10) opening (10a) of number 1 corresponding to edge point at which point X1, through holes (7) opening of number 2 (7b) corresponding to edge point in order to create a point of number 2 X2, through holes (7) opening of number 2 (7b) (i.e., the inner peripheral surface (2b) prolongation of the) on the insulating layer (10) surface (10b) number 3 point which is a point where X3, through holes (7) opening of number 1 (7a) corresponding point number 4 point X4 of less than 1000. Number 1 and number 2 point X2 X1 and a line segment connecting the point S1 in order to number 1, number 2 point on a line segment connecting the number 3 point X2 X3 S2 which is a number 2, number 3 and number 1 point X1 X3 line segment connecting point number 3 or equal to S3. At this time, line number 1 to S1 through hole (7) on the inner surface of (7c) is positioned on the insulating layer (10) number 1 of the area A1, line number 1 S1, S2 segment number 2, number 3 and S3 segment is surrounded by a insulating layer (10) of number 2 on area A2, number 3 for segment S3 through hole (7) on the inner surface of (7c) is positioned on the opposite side of the insulating layer (10) is greater than the sum of area A3 of number 3. In addition, number 1 point X1 in insulating layer (10) surface (10b) θ 1 the angle of tilt of the number 3 point X3 insulating layer (10) surface (10b) the angle of tilt of greater than θ 2. Number 1 point X1 in insulating layer (10) surface (10b) θ 1 RM the angle of tilt of the through hole (7) with respect to the plane including the centerline of one side of centerline CL CL when area of interest, and the insulator layer corresponding plane (10) surface (10b) to linear (tangential) and intersection point X1 with number 1 would be encountered in the inner peripheral surface (2a) is an angle are disclosed. The slope angle θ 1 0о Greater than 90 andо Less than. Number 3 point X3 insulating layer (10) surface (10b) θ 2 provide the means by which the angle of tilt of the through hole (7) with respect to the plane including the centerline of one side of centerline CL CL when area of interest, and the insulator layer corresponding plane (10) surface (10b) number 3 to linear (tangential) and X3 intersection point would be encountered in the inner peripheral surface (2a) is an angle are disclosed. The slope angle θ 2 0о Greater than 90 andо Less than. In addition, the through hole (7) on the inner surface of (7c) is provided on the insulating layer (10) surface (10b) average inclination angle θ has a through hole (7) on the inner surface of (7c) less than the average inclination angle γ. The through hole (7) on the inner surface of (7c) is provided on the insulating layer (10) surface (10b) average inclination angle θ has a through hole (7) with respect to the plane including the centerline of one side of centerline CL CL when area of interest, corresponding plane and the through hole (7) on the inner surface of (7c) is provided on the insulating layer (10) surface (10b) (i.e., number 1 opening (7a) on number 2 opening (7b) positioned between insulating layers (10) surface (10b)) the intersection of the inner peripheral surface (2a) to average an angle are disclosed. The average inclination angle θ is 0о Greater than 90о Less than. The through hole (7) on the inner surface of (7c) is the aforementioned efined γ average inclination angle. In addition, point X1 X4 number 1 and number 4 point D1 distance between insulating layer (10) opening (10a) is greater than the width of W. The insulating layer (10) opening (10a) the width of the opening (10a) when the spherical opening (10a) distance between of concave parts, opening (10a) is a circular opening (10a) big diameter. In addition, through holes (7) opening of number 1 (7a) edge of the insulating layer (10) opening (10a) D2 is an intersection of the through holes (7) opening of number 1 (7a) number 1 edge of wiring (3) pad part of (3a) intersection of greater than D3. [Action and effect] Semiconductor device (1) as shown in the variation in 9 also, through holes (7) with respect to the plane including the centerline of CL CL when noted each at both sides of the centerline, the aforementioned number 1 number 2 and number 3 area greater than the sum of the above-mentioned A1 A2 A3 on the area area, in addition the aforementioned number 3 A3 area so that there is insulating layer (10) is provided with a disclosed. The, insulating layer (10) of through holes (7) opening of number 2 (7b) cover the edge of the surface of the average inclination angle is less (i.e., gently) Jim and simultaneously, the corresponding partial thickness of 2000 is reserved. , the through hole (7) when the vertical hole, number 2 wiring (8) disconnection of, number 2 wiring (8) semiconductor substrate (2) leakage of current between said film is easily through holes (7) opening of number 2 (7b) such further used for generating the vicinity of the pipe joint. In addition, the through hole (7) because vertical hole through hole (7) the semiconductor substrate (2) primary surface (2a) from the inner peripheral surface (2b) from spreading toward the tapered hole not to induce, semiconductor substrate (2) in the through hole (7) occupies billion of volume ratio number with each other. This number 1 wiring (3) and number 2 wiring (8) for connecting the surface periphery of the device region need a through hole (7) opening of number 1 (7a) when the area of the same, tapered hole semiconductor substrate (2) primary surface (2a) from the inner peripheral surface (2b) while toward the purge, vertical hole is semiconductor substrate (2) primary surface (2a) from the inner peripheral surface (2b) substantially toward purge but disclosed. The mold, semiconductor device (1) the, semiconductor substrate (2) in the through hole (7) occupies billion while number of volume ratio, semiconductor substrate (2) of through holes (7) can be ensure through electrical connection. Semiconductor device (1) in number 1 point X1 in insulating layer (10) surface (10b) θ 1 X3 point number 3 in the angle of tilt of the insulating layer (10) surface (10b) the angle of tilt of greater than θ 2. The, for example through holes (7) even when the diameter of the insulating layer (10) of through holes (7) opening of number 2 (7b) cover the edge of the surface of (10b) while maintaining the average angle of tilt angle of less (i.e., gentle angle), semiconductor substrate (2) primary surface (2a) side insulating layer (10) opening (10a) edges can be sufficiently ensured. The, insulating layer (10) of through holes (7) opening of number 2 (7b) in number 2 cover the edge of the wiring (8) can be roller, insulating layer (10) opening (10a) number 1 wiring portion (3) of number 2 wiring (8) can be thin film with. Semiconductor device (1) in the through hole (7) on the inner surface of (7c) is provided on the insulating layer (10) surface (10b) is average inclination angle θ through hole (7) on the inner surface of (7c) less than the average inclination angle γ. The, for example insulating layer (10) through holes (7) on the inner surface of (7c) formed in a uniform thickness along not to induce, semiconductor substrate (2) opening of number 2 (7b) side wiring number 2 (8) for the formation of selected can surely embodiment hereinafter. Semiconductor device (1) in number 1 and number 4 point distance between point X1 X4 D1 of the insulating layer (10) opening (10a) is greater than the width of W. For example, semiconductor substrate (2) opening of number 2 (7b) side insulating layer (10) opening (10a) contact with, semiconductor substrate (2) primary surface (2b) from the insulating layer (10) primary surface (2a) side opening (10a) since away from the, a respective opening (10a) the size of the, location deviation does easy one. The aforementioned number 1 and number 4 point point X1 X4 D1 distance between the insulating layer (10) primary surface (2a) side opening (10a) is set larger than the width of W, a respective opening (10a) size, variations of position can drain regions. In addition, point X1 X4 number 1 and number 4 point greatly by taking the distance D1, insulating layer (10) of through holes (7) opening of number 2 (7b) and cover the thick edge of the, in addition insulating layer (10) of through holes (7) opening of number 2 (7b) patterned surface portion (10b) is provided to facilitate the design resulting in reduced average inclination angle. Semiconductor device (1) in the through hole (7) opening of number 1 (7a) edge of the insulating layer (10) opening (10a) D2 is an intersection of the through holes (7) opening of number 1 (7a) number 1 edge of wiring (3) pad part of (3a) intersection of greater than D3. As described above, semiconductor substrate (2) opening of number 2 (7b) side insulating layer (10) opening (10a) contact with, a respective opening (10a) of size, but that is prone position, number 1 opening (7a) edge of the insulating layer (10) opening (10a) opening an intersection of a number 1 D1 (7a) edge of the pad part (3a) is set larger than an intersection of D3, a respective opening (10a) size, variations of position can drain regions. In addition, point X1 X4 number 1 and number 4 point greatly by taking distance between D1, insulating layer (10) of through holes (7) opening of number 2 (7b) edge of the cover and thick in addition, insulating layer (10) of through holes (7) opening of number 2 (7b) patterned surface portion (10b) is provided to facilitate the design resulting in reduced average inclination angle. In addition, the distance between the number 1 and number 4 point X1 X4 point D1 of the insulating layer (10) opening (10a) and greater than the width of W, through holes (7) opening of number 1 (7a) edge of the insulating layer (10) opening (10a) D2 is an intersection of the through holes (7) opening of number 1 (7a) number 1 edge of wiring (3) pad part of (3a) intersection of D3 satisfy at least one of greater than, is satisfied and an intervening fourth worm portion can be achieved. Semiconductor device (1) in the through hole (7) opening depth of number 2 (7b) divided by the width of the size is 1 hereinafter are disclosed. The, insulating layer (10) surface (10b) to number 2 wiring (8) for a hereinafter can be reliably formed. In addition, insulating layer (10) number 2 during opening (7b) cover the edge of the surface of (10b) less than the average angle of tilt (i.e., round through), the corresponding partial in number 2 wiring (8) or breaks can be extended. The insulating layer (10) opening (10a) for a hereinafter can be reliably formed. Semiconductor device (1) the insulating layer (10) consisting of resin ([...]). The, is shaped as a described above the insulating layer (10) for a hereinafter can be reliably formed. Semiconductor device (1) in the through hole (7) on the inner surface of (7c) is provided on the insulating layer (10) surface (10b) over a continuous plane. The, insulating layer (10) surface (10b) since stress concentration peak of relaxed number 2 wiring (8) or breaks can be extended. Semiconductor device (1) in the through hole (7) on the inner surface of (7c) is provided on the insulating layer (10) surface (10b) and the inner peripheral surface (2b) is provided on the insulating layer (10) surface (10b) over a continuous plane. The, insulating layer (10) of through holes (7) opening of number 2 (7b) is reserved number 2 because the thickness of the patterned opening (7b) vicinity of number 2 wiring (8) semiconductor substrate (2) can prevent leakage of electric current in between. In addition, insulating layer (10) of through holes (7) opening of number 2 (7b) cover the edge of the surface of (10b) since a smooth, number 2 opening (7b) vicinity of number 2 wiring (8) can prevent disconnection of occurrence. Semiconductor device (1) silicon nitride and (2) a plurality of avalanche photo diode (APD) preamplifiers to mode of operation which has been described. Such semiconductor device (1) in a plurality of pixels (avalanche photo diode (APD) is equal to) the photodetecting surface in an area of the second electrode but amplifiers are preferably, avalanche photo diode (APD) each through hole (7) is providing a semiconductor substrate (2) in the through hole (7) ratio of volume occupied by number billion specifies a disclosed. Another, through hole (7) in disconnection of wiring and restored, semiconductor substrate (2) of through holes (7) electrical connection through ensure want disclosed. In particular, such semiconductor device (1) in avalanche photo diode (APD) operating voltage applying-typed, the through hole (7) in wiring and semiconductor substrate (2) which can realize a reliable isolation of desired disclosed. Semiconductor device (1) as if they were track positions, semiconductor substrate (2) in the through hole (7) occupies billion number ratio of volume in the semiconductor substrate (2) of through holes (7) can be surely through electrical connection since, semiconductor substrate (2) in the through hole (7) occupies number billion of volume ratio can be, semiconductor substrate (2) in the through hole (7) through the channel's electrical connection surely and the through hole (7) in wiring and semiconductor substrate (2) can be reliable conversion between two systems. [Modified examples] Or more, one embodiment of the present invention is described but form, the present invention refers to said embodiment form and not limited. For example, insulating layer (10) is formed by the insulating material other than resin may be disclosed. In addition, said embodiment in one form through holes (7) opening of number 1 (7a) is number 1 wiring (3) pad part of (3a) are covered with about, number 1 wiring (3) opening a portion of the number 1 (7a) located on number 1 and wiring (3) opening the number 1 (7a) covering the entire area of the need disclosed. The electrodes (9) semiconductor substrate (2) primary surface (2b) protruded through holes (7) arranged inside the ceramics disclosed. If so, the lead electrodes (9) includes a through hole (7) on the inner surface of (7c) is provided on the insulating layer (10) surface (10b) number 2 formed wiring (8) electrically connected with each other. Thus, in this case number 2 wiring (8) semiconductor substrate (2) primary surface (2b) is provided on the insulating layer (10) surface (10b) formed need disclosed. In addition, mounting substrate (120) (passive quenching) the passive matching circuit (the interval between the resistance) in place, the interval between the active (active quenching) circuit may be disclosed. If so, the matching circuit has a common electrode connected to the signal line on each active CE TL. Each active interval circuit CMOS circuitry, signal processing unit SP also functions as the substrate. Each avalanche photo diode (APD) active matching circuit output signal from digital pulse converted with, using MOS ON/OFF operation of embodiment and converted pulse, voltage steel number drop reset operation embodiment as follows. A mounting substrate (120) is active by the matching circuit, semiconductor light detecting element (110) is preamplifiers mode when operating voltage recovery time can be reduced. Number 1 and number 2 semiconductor region 1PB 1PA semiconductor region without limit the above shape each shape, other shapes (e.g., circular shape or the like) may have now. In addition, semiconductor substrate (2) formed avalanche photo diode (APD) number of (row number and be opened), not limited to the above such as arranged. In one form said embodiment semiconductor substrate (2) side (2c) and a mounting substrate (120) side (120c) but the same includes a cockpit, without limited to, for example when viewed in the plane, mounting substrate (120) penetrating the semiconductor substrate (2) located outside with respect to the elastic sheet may comprise other. In this case, mounting substrate (120) primary surface (120a) formed at the periphery of pad on the outside by a wire electrically connected to the signal processing information is outputted is external. [Reference type semiconductor device] 17 Also is consulted to type semiconductor device 10 also to reference (1) is described as follows. In addition, the aforementioned embodiment type semiconductor device (1) of through holes (7) and a portion of the periphery carry reference type semiconductor device (1) of through holes (7) and the peripheral portion as well as number can be high pressure liquid coolant. As shown in the 10 also, semiconductor device (1) are each opposing major sides (2a) and the inner peripheral surface (2b) having a substrate (2) etc. with. Semiconductor device (1) is, for example color sensor and optical device such as, for example silicon semiconductor substrate (2) primary surface (2a) the device is constituted disclosed. Semiconductor substrate (2) primary surface (2a) is, for example made of aluminum a number 1 wiring (3) oxide film (4) adhered to in the nanometer range. Oxide (4) wiring number 1 in (3) pad part of (3a) a narrow mouth with parts (4a) is formed in the nanometer range. Semiconductor substrate (2) primary surface (2a) is, for example made of a glass light-transmitting substrate (5) the adhesive layer (6) is installed through a in the nanometer range. Semiconductor substrate (2) is the inner peripheral surface (2a) from the inner peripheral surface (2b) that extends into a through hole (7) formed in the nanometer range. Through holes (7) opening of number 1 (7a) includes a substrate (2) primary surface (2a) and can be located, through holes (7) opening of number 2 (7b) includes a substrate (2) primary surface (2b) of the cell disclosed. Number 1 opening (7a) is oxide (4) opening (4a) on continuously and, number 1 wiring (3) pad part of (3a) covered by the nanometer range. The through hole (7) on the inner surface of (7c) to the main surface (2a) from the inner peripheral surface (2b) on spreading toward the taper are disclosed. For example, the through hole (7) is the inner peripheral surface (2a) from the inner peripheral surface (2b) to spreading toward an upper ([...]) in the form of in the nanometer range. In addition, the through hole (7) CL as viewed from a direction parallel to the centerline of the through holes (7) opening of number 1 (7a) edge of the oxide film (4) opening (4a) and the peripheral edge of the matching need not be, for example oxide (4) opening (4a) arranged at the through hole (7) of number 1 opening (7a) located on the rear side with respect to the edge of which may disclosed. The through hole (7) a size ratio of 0. 2 - 10 Are disclosed. A through hole size (7) depth of (number 1 opening (7a) number 2 on opening (7b) distance between) opening a number 2 (7b) width (number 2 opening (7b) a spherical case number 2 opening (7b) of concave distance between, number 2 opening (7b) number 2 is a circular opening (7b) diameter) divided by value. For example, the through hole (7) and the depth of 30 μm, number 2 opening (7b) the width of 130 μm are disclosed. In this case, a size 0. 23 Are disclosed. The through hole (7) on the inner surface of (7c) and semiconductor substrate (2) primary surface (2b) are provided with an isolating layer (10) is provided with a disclosed. Insulating layer (10) includes a through hole (7) opening of number 2 (7b) etc. in series through. Insulating layer (10) includes a through hole (7) in the interior of the, oxide (4) opening (4a) number 1 through wiring (3) pad part of (3a) which reaching, semiconductor substrate (2) primary surface (2a) side opening (10a) has disclosed. Insulating layer (10) surface (10b) (through hole (7) on the inner surface of (7c) and semiconductor substrate (2) primary surface (2b) opposite to the side surface) is, for example made of aluminum a number 2 wiring (8) provided in the nanometer range. Number 2 wiring (8) an insulating layer (10) opening (10a) number 1 in wiring (3) pad part of (3a) electrically connected in the nanometer range. Number 2 wiring (8) from the ice bank the bump electrodes electrode (9) disposed pad part (8a) and a number [...], the resin protective layer (21) covered by the nanometer range. In addition, the resin protective layer (21) in place, another insulating material (for example, oxide, nitride or the like) is provided on the protective layer may be disclosed. And the resin protective layer (21) the thickness of the insulating layer (10) may be made same as that of the degree, or insulating layer (10) smaller than the thickness of even with each other. In particular, the resin protective layer (21) the thickness of the insulating layer (10) if the thickness of the same extent, number 2 wiring (8) and number 3 wiring (22) acting on the stress can be reduced disclosed. Above the insulating layer (10) with reference to the extra 11 also with respect to each other. In addition, a light-transmitting substrate in Figure 11 (5), adhesive layer (6), with the lead electrodes (9), and the resin protective layer (21) exposed in the nanometer range. As shown in the variation also 11, insulating layer (10) surface (10b) includes a through hole (7) opening inside the number 1 (7a) reaching the number 1 region (11) and, through holes (7) opening inside the number 2 (7b) reaching the number 2 region (12) and, through hole (7) on the outside of the semiconductor substrate (2) primary surface (2b) opposite the number 3 area (13) comprises. Number 1 region (11) semiconductor substrate (2) primary surface (2a) from the inner peripheral surface (2b) area on taper spreading toward are disclosed. Number 1 region (11) having an average inclination angle α etc.. Number 1 region (11) implies an average inclination angle α through hole (7) with respect to the plane including the centerline of CL, centerline CL varies in case the plane area of one side of number 1 region (11) the intersection with the inner peripheral surface (2a) to average an angle are disclosed. A straight line if the intersection corresponding to the substantially straight inner peripheral surface (2a) become the number 1 region (11) is under or over average inclination angle α. When the corresponding intersection curve, the curve formed by a tangent of the inner peripheral surface (2a) is an angle between the calculated average number 1 region (11) is under or over average inclination angle α. Number 1 region (11) average inclination angle α is 0о Greater than 90 andо Less than. Number 2 region (12) semiconductor substrate (2) primary surface (2a) from the inner peripheral surface (2b) area on taper spreading toward are disclosed. Number 2 region (12) having an average inclination angle β etc.. Number 2 region (12) implies average inclination angle β through hole (7) with respect to the plane including the centerline of one side of centerline CL CL when the area of interest, corresponding plane number 2 region (12) the intersection and the inner peripheral surface (2a) and an angle between a pair of lengthwise are disclosed. Corresponding intersection when the straight line, a straight line and the inner peripheral surface (2a) become the number 2 region (12) is under or over average inclination angle β. When the corresponding intersection curve, the curve formed by a tangent of the inner peripheral surface (2a) is an angle between the calculated average number 2 region (12) is under or over average inclination angle β. Number 2 region (12) average inclination angle β is 0о Greater than 90о Less than. Number 2 region (12) average inclination angle β is number 1 region (11) less than the average inclination angle α. I.e., number 2 region (12) is number 1 region (11) have a zone that operation in inclination are disclosed. In addition, number 2 region (12) average inclination angle β has a through hole (7) inner surface (7c) less than the average inclination angle γ. I.e., number 2 region (12) includes a through hole (7) on the inner surface of (7c) region having operation in inclination are disclosed. The embodiment in one form number 1 region (11) average inclination angle α is number 2 region (12) than average inclination angle β through hole (7) on the inner surface of (7c) to average inclination angle γ Christ. Here number 1 region (11) throughout the average inclination angle α through hole (7) on the inner surface of (7c) throughout the average inclination angle γ number 2 region (12) average inclination angle β to the nanometer range. The through hole (7) on the inner surface of (7c) γ average inclination angle has a through hole (7) with respect to the plane including the centerline of one side of centerline CL CL when area of interest, inner surface of the corresponding plane (7c) the intersection with the inner peripheral surface (2a) to average an angle are disclosed. Corresponding intersection when the straight line, a straight line and the inner peripheral surface (2a) become the through hole (7) on the inner surface of (7c) γ average inclination angle is under or over. When the corresponding intersection curve, the curve formed by a tangent of the inner peripheral surface (2a) and the mean angle formed by the through hole (7) on the inner surface of (7c) γ average inclination angle is under or over. Insulating layer (10) surface (10b) includes a through hole (7) on the inner surface of (7c) ([...]) opposite to the convex side having an maximum number 4 region (14) and the through hole (7) opening of number 2 (7b) along an edge of number 5 region (15) results are. The through hole (7) on the inner surface of (7c) by which maximum curvature convex opposite side through hole (7) with respect to the plane including the centerline of one side of centerline CL CL when area of interest, corresponding plane surface (10b) intersection of through holes (7) on the inner surface of (7c) maximum curvature of the convex profile of the curved opposite side a part are disclosed. In addition, number 1 region (11) includes a through hole (7) on the inner surface of (7c) is provided on the insulating layer (10) surface (10b) of number 4 area (14) than through holes (7) opening of number 1 (7a) side region are disclosed. Number 2 region (12) includes a through hole (7) on the inner surface of (7c) is provided on the insulating layer (10) surface (10b) of number 4 area (14) than through holes (7) opening of number 2 (7b) side of (i.e., number 4 region (14) and number 5 region (15) in an area between the) are disclosed. Number 4 region (14) is number 1 region (11) and number 2 region (12) and connected to continuously being curved disclosed. I.e., number 4 region (14) and the rounded curved, number 1 region (11) and number 2 region (12) and for connection or a metal silicide layer. Wherein, number 4 region (14) is present and is not home, number 1 region (11) semiconductor substrate (2) primary surface (2b) side faster and, number 2 region (12) semiconductor substrate (2) primary surface (2a) when extending, number 1 region (11) and number 2 region (12) intersection by (edge, a prescribed) formed therein. Number 4 region (14) corresponding to the cotton it will take a curved intersection (edge, a prescribed) formed when R is equal to. Number 4 region (14) includes a through hole (7) with respect to the plane including the centerline of one side of centerline CL CL when area of interest, corresponding plane surface (10b) intersection of number 1 region (11) parts and number 2 region (12) between parts through hole (7) on the inner surface of (7c) opposite to the side to cover the convex curved portion are disclosed. Number 5 region (15) is number 2 region (12) and number 3 region (13) and connected to continuously being curved disclosed. I.e., number 5 region (15) and the rounded curved, number 2 region (12) and number 3 region (13) and for connection or a metal silicide layer. Wherein, number 5 region (15) and there is not home, number 2 region (12) semiconductor substrate (2) primary surface (2b) side faster and, number 3 region (13) the trough holes (7) extends toward the centerline of CL when, number 2 region (12) and number 3 region (13) intersection by (edge, such as a prescribed) formed therein. Number 5 region (15) corresponding to the cotton it will take a curved intersection (edge, such as a prescribed) formed when R is equal to. Number 5 region (15) includes a through hole (7) with respect to the plane including the centerline of one side of centerline CL CL when area of interest, corresponding plane surface (10b) intersection of number 2 region (12) and parts number 3 region (13) between the through hole parts (7) of number 2 opening (7b) in contrast to a side edge of the convex shape is formed on disclosed. The embodiment in one form number 1 region (11), number 4 region (14), and number 5 region (15) includes a through hole (7) on the inner surface of (7c) curved opposite side convex curved shape are disclosed. Number 2 region (12) includes a through hole (7) on the inner surface of (7c) side convex curved shape curved (i.e., through hole (7) on the inner surface of (7c) bent into a concave shape and curved opposite side herein) are disclosed. Number 3 region (13) semiconductor substrate (2) primary surface (2b) substantially parallel plane are disclosed. As described above, number 4 region (14) is number 1 region (11) and number 2 region (12) and connected to continuously being curved, number 5 region (15) is number 2 region (12) and number 3 region (13) is connected so that the curved continuously, insulating layer (10) surface (10b) consecutive surface (surfaces intersection (edge, bending portion of) such as discontinuous portion is found without, each region (11, 12, 13, 14, 15) head is releasably connected to the surface) to be disclosed. The through hole (7) on the inner surface of (7c) is provided on the insulating layer (10) the average thickness of the semiconductor substrate (2) primary surface (2b) is provided on the insulating layer (10) is greater than an average thickness of. The through hole (7) on the inner surface of (7c) is provided on the insulating layer (10) the average thickness of the inner surface (7c) in a direction perpendicular to the insulating layer (10) is the thickness of the average. Semiconductor substrate (2) primary surface (2b) is provided on the insulating layer (10) the average thickness of the inner peripheral surface (2b) in a direction perpendicular to the insulating layer (10) is the thickness of the average. Semiconductor substrate (2) primary surface (2a) and the inner peripheral surface (2b) in a direction parallel to the insulating layer (10) of number 1 region (11) parts the average thickness of the insulating layer (10) of number 2 region (12) is greater than an average thickness of parts. Semiconductor substrate (2) primary surface (2a) and the inner peripheral surface (2b) in a direction parallel to the insulating layer (10) of number 1 region (11) the average thickness of the parts corresponding direction number 1 region (11) and the through hole (7) on the inner surface of (7c) of the distance between the average are disclosed. Semiconductor substrate (2) primary surface (2a) and the inner peripheral surface (2b) in a direction parallel to the insulating layer (10) of number 2 region (12) in the direction corresponding to the average thickness of the parts number 2 region (12) and the through hole (7) on the inner surface of (7c) of the distance between the average are disclosed. Insulating layer (10) in number 1 region (11) includes a through hole (7) on the inner surface of (7c) is provided on the insulating layer (10) of semiconductor substrate (2) primary surface (2a) of the portion having a height H in surface are disclosed. Height H includes a substrate (2) (i.e., the inner peripheral surface (2a) and the inner peripheral surface (2b) distance between) the thickness of the semiconductor substrate (2) primary surface (2b) is provided on the insulating layer (10) sum of average thickness of 1/2 hereinafter D are disclosed. Insulating layer (10) the insulating layer (10) opening (10a) of edges and a through hole (7) opening of number 2 (7b) through the edge of the interface as a S, S with respect to the through hole (7) on the inner surface of (7c) side portions of P1, and surface S to through hole (7) on the inner surface of (7c) varies the opposite side portion P2, P1 P2 portion greater than the volume of the volume of the portion. In addition, insulating layer (10) in the through hole (7) with respect to the plane including the centerline of one side of the centerline CL CL area of interest, the area of triangle T1 T2 greater than the area of the triangle. The triangle T1 through hole (7) in a plane including the centerline of CL (i.e., in the cross section of Figure 11), through holes (7) opening of number 1 (7a) edge, through holes (7) opening of number 2 (7b) edge of, and insulting layer (10) opening (10a) is composed edge of the triangular are disclosed. Triangle T2 has a through hole (7) in a plane including the centerline of CL (i.e., in the cross section of Figure 11), insulating layer (10) opening (10a) edge, through holes (7) opening of number 2 (7b) edge of, and number 4 region (14) is composed Government of triangular are disclosed. As the device, semiconductor device (1) the insulating layer (10) surface (10b) of through holes (7) opening of number 1 (7a) reaching the region number 1 (11), and a through hole (7) opening of number 2 (7b) reaching the number 2 region (12) semiconductor substrate (2) primary surface (2a) from the inner peripheral surface (2b) area on taper spreading toward are disclosed. The number 2 region (12) average inclination angle through hole (7) on the inner surface of (7c) over less than average inclination angle. The, insulating layer (10) surface (10b) of semiconductor substrate (2) primary surface (2b) opposite the number 3 region (13) and the through hole (7) opening of number 2 (7b) reaching the number 2 region (12) become the semiconductor substrate (2) primary surface (2b) and the through hole (7) on the inner surface of (7c) greater than that formed by the (i.e., gently) with each other. The, number number even after discharge and a bath tank through holes (7) opening of number 2 (7b) portion of number 2 wiring (8) disconnection of pipe joint. In addition, for example insulating layer (10) through holes (7) on the inner surface of (7c) formed along a uniform thickness compared with the number 2 region (12) to cause the inclination of the, number 2 wiring (8) hereinafter for thermally processing silicon wafers can be reliably formed. In addition, the through hole (7) on the inner surface of (7c) without depending on the shape of the number 2 wiring (8) can be formed, for example through holes (7) on the inner surface of (7c) a pointed portion from remaining due to such portion even when the switching number 2 wiring (8) can be roller. The number 2 region (12) average inclination angle number 1 region (11) over less than average inclination angle. An editing unit surface, through holes (7) opening of number 1 (7a) reaching the number 1 region (11) average inclination angle number 2 region (12) average inclination angle is larger than 2000. The, for example through holes (7) in case the diameter of the semiconductor substrate (2) primary surface (2a) side insulating layer (10) opening (10a) whose scope of are sufficiently ensured. The, number number even after discharge and a bath tank insulating layer (10) opening (10a) number 1 wiring portion (3) and number 2 wiring (8) disconnection of pipe joint. In addition, insulating layer (10) surface (10b) number 4 in region (14) is number 1 region (11) and number 2 region (12) is curved and continuous-receiving, number 5 region (15) is number 2 region (12) and number 3 region (13) and connected to continuously being curved disclosed. To this end, insulating layer even after discharge and a number number bath bath (10) surface (10b) number 2 in the area of the former wiring (8) disconnection of pipe joint. In particular number bath after being insulating layer (10) surface (10b) since stress concentration peak of relaxed, number 2 wiring (8) effective head are disclosed. The mold, semiconductor device (1) according to the, semiconductor substrate (2) of through holes (7) can be ensure through electrical connection. Semiconductor device (1) the insulating layer (10) surface (10b) continuous surface (surfaces intersection (edge, bending portion of) such as discontinuous portion is found without, each region (11, 12, 13, 14, 15) head is releasably connected to the surface) to be disclosed. The, to mitigate stress concentration as the number 2 wiring (8) can be roller. Semiconductor device (1) in number 1 region (11) average angle number 2 region (12) than average inclination angle formed by a through hole (7) on the inner surface of (7c) average slope close to disclosed. The, number 1 wiring (3) pad part of (3a) having sufficient to expose the opening edges (10a) can be obtained, as a result number number tank insulating layer even after discharge and a tank (10) opening (10a) number 1 in wiring (3) and number 2 wiring (8) than the sealant can be surely prevented. Semiconductor device (1) in number 1 region (11) throughout the average inclination angle α through hole (7) on the inner surface of (7c) throughout the average inclination angle γ number 2 region (12) average inclination angle β to the nanometer range. The, number 2 wiring (8) can be roller simultaneously, number 1 wiring (3) pad part of (3a) having sufficient to expose the opening edges (10a) can be achieved at a. Semiconductor device (1) in the through hole (7) on the inner surface of (7c) is provided on the insulating layer (10) is the average thickness of the inner peripheral surface (2b) is provided on the insulating layer (10) has average thickness is larger than 2000. The, for example semiconductor substrate (2) even when the thickness ([...]) through hole (7) on the inner surface of (7c) is provided on the insulating layer (10) functions as a reinforcing layer (layer) since, through hole (7) can be ensuring a sufficient strength of the peripheral portion. In addition, number 1 region (11) average inclination angle and number 2 region (12) can be part includes average inclination angle surface (10b) continuous surface (surfaces intersection (edge, bending portion of) such as discontinuous portion is found without, each region (11, 12, 13, 14, 15) the head is releasably connected to the) consist of insulating layer (10) obtain the relationship. For example, insulating layer (10) through holes (7) on the inner surface of (7c) is formed in a uniform thickness along the surface (10b) the lead continuous insulating layer (10) to obtain impossible disclosed. Semiconductor device (1) silicon nitride (2) primary surface (2a) and the inner peripheral surface (2b) in a direction parallel to the insulating layer (10) of number 1 region (11) parts an average thickness of the insulating layer (10) of number 2 region (12) is greater than an average thickness of parts. The, number 2 wiring (8) disconnection of second wavelike wirings are arranged, in addition number 1 wiring (3) and number 2 wiring (8) having a shape such as a disconnection of the insulating layer (10) obtain the relationship. Semiconductor device (1) is, for example through holes (7) opening of number 2 (7b) (overhang) edge of the protrusions and the like using the former which brings, such as corresponding overhang the insulating layer (10) covered by a convex curved shape curved number 5 region (15) number 2 to wiring (8) provided to be coated. The, through holes (7) opening of number 2 (7b) portion of number 2 wiring (8) can be surely prevented from the sealant. Semiconductor device (1) in the through hole (7) on the inner surface of (7c) is provided on the insulating layer (10) of semiconductor substrate (2) the thickness of the inner peripheral surface (2b) is provided on the insulating layer (10) of the height of the surface of the portion having an average thickness of the sum of the H D 1/2 hereinafter number 1 region (11) is disclosed. The, insulating layer (10) surface (10b) in number 1 region (11) and number 2 region (12) connected to lead the number 1 region (11) and number 2 region (12) at boundaries of the number 2 wiring (8) can be surely prevented from the sealant. Semiconductor device (1) insulating layer (10) the insulating layer (10) opening (10a) of edges and a through hole (7) opening of number 2 (7b) through the edge of the interface as a S, S for the through hole (7) on the inner surface of (7c) side portions of P1, and surface S for through hole (7) on the inner surface of (7c) varies the opposite side portion P2, etc. is larger than the volume of the volume of the portion P1 P2 portion. In addition, the through hole (7) with respect to the plane including the centerline of one side of the centerline CL CL area of interest, etc. is larger than the area of triangle area of triangle T1 T2. By providing such, insulating layer (10) surface (10b) in number 1 region (11) and number 2 region (12) connected to lead the, number 1 region (11) and number 2 region (12) at boundaries of the number 2 wiring (8) can be surely prevented from the sealant. Semiconductor device (1) in the through hole (7) on the inner surface of (7c) is provided on the insulating layer (10) surface (10b) of through holes (7) on the inner surface of (7c) opposite to the convex side having an maximum number 4 region (14) number 1 than opening (7a) is a region of the side number 1 region (11) are divided, number 4 region (14) number 2 than opening (7b) is a region of the side number 2 region (12) is disclosed. The insulating layer (10) the shape of the semiconductor substrate (2) of through holes (7) in electrical connection through to guarantee that in particular efficient. Semiconductor device (1) in the through hole (7) on the inner surface of (7c) primary surface (2a) from the inner peripheral surface (2b) on spreading toward the taper are disclosed. Even when the semiconductor substrate (2) of through holes (7) can be ensure through electrical connection. Next, the aforementioned semiconductor device (1) for a number of tank 12 to 14 are described while referencing the method are also disclosed. First, semiconductor substrate (2) to prepare and, semiconductor substrate (2) primary surface (2a) constituting the device (i.e., the inner peripheral surface (2a) insulating layer (4), number 1 wiring (3) or the like provided other) (process number 1). And the semiconductor substrate (2) primary surface (2a) an adhesive layer (6) light through the transmitting substrate (5) disposed on the substrate. Still being formula, as shown in the variation of Figure 12 (a), anisotropic wet etching (wet etching) a semi-conductor substrate (2) to the through hole (7) is formed, as shown in the variation in addition of Figure 12 (b), oxide film (4) in number 1 wiring (3) pad part of (3a) corresponding to a stand-alone to a thermal oxidation number portion (4) opening (4a) and form. The, through holes (7) opening of number 1 (7a) number 1 to wiring (3) pad part of (3a) a reaction chamber (process number 2). Then, a viscosity of at least 10 cp has, in addition positive resin material prepared, resin material dip coating (dip coating) method (object resin paint immersion ([...]) and, by drawing up the object from object is coated with coating composition method) by the embodiment, as shown in the variation of Figure 13 (a), through hole (7) on the inner surface of (7c) and semiconductor substrate (2) primary surface (2b) an insulation layer (10) is provided on the other (process number 3). The, insulating layer (10) is number 2 region (12), number 3 region (13) and number 5 region (15) having a concave inner surface may follow ([...]) part (17) is formed. In addition, as resin material, for example phenol resin, polyimide resin, epoxy resin or the like can be using. Subsequently, as shown in the variation of Figure 13 (b), semiconductor substrate (2) primary surface (2b) is provided on the insulating layer (10) of a mask on a (30) placed. Mask (30) includes a number 1 wiring (3) pad part of (3a) in the position facing the light transmission part (31) having, a light transmission part (31) around the light shielding unit (32) has disclosed. Then, an insulating layer (10) in contact hole (16) to a portion corresponding to the mask (30) a light transmission part (31) through the irradiating, the corresponding partial exposure. In addition, insulating layer (10) in contact hole (16) by developing the parts, insulating layer (10) to contact hole (16) formed on the substrate. The, insulating layer (10) opening (10a) number 1 to wiring (3) pad part of (3a) a reaction chamber (process number 4). In addition, contact hole (16) at the time of forming, arcing (ashing) combination treatment may be disclosed. Of exposure mask (30) a light transmission part (31) on the insulating layer (10) in contact hole (16) between corresponding to the insulating layer (10) formed depressions (17) formed by a gap. The, light diffraction by insulating layer (10) applied to a substrate. To this end, at the time of developing semiconductor substrate (2) primary surface (2a) from the inner peripheral surface (2b) from spreading toward the taper on number 1 region (11), and number 2 region (12) having inner surface may follow the contact hole (16) formed therein. Then, as shown in the variation of Figure 14 (a), for example by using a spatter method embodiment aluminum, insulating layer (10) surface (10b) to number 2 wiring (8) provided with a insulating layer (10) opening (10a) number 1 in wiring (3) and number 2 wiring (8) electrically connected in (process number 5). At this time, contact hole (16) the semiconductor substrate (2) primary surface (2a) from the inner peripheral surface (2b) from spreading toward the taper on number 1 region (11) having inner surface may follow because, even inner surface corresponding reliably formed metal film, further insulating layer (10) opening (10a) number 1 in wiring (3) and number 2 wiring (8) clear-connected with each other. Subsequently, for example insulating layer (10) using the same resin material by dip coating method embodiment, as shown in the variation of Figure 14 (b), number 2 wiring (8) resin protective layer (21) fillter. Finally, the resin protective layer (21) is not covered with a number 2 wiring (8) pad part of (8a) to the lead electrodes (9) is arranged, the above-described semiconductor device (1) obtain. Said semiconductor device (1) the number of bath method, semiconductor substrate (2) of through holes (7) electrical connection is ensured through semiconductor device (1) can be efficiently number high pressure liquid coolant. Said semiconductor device (1) of the resin material in viscosity of at least 10 cp number bath method by dip coating method embodiment, through hole (7) on the inner surface of (7c) and semiconductor substrate (2) primary surface (2b) an insulation layer (10) is provided on the substrate. The, such as by shape above the insulating layer (10) for a reliably hereinafter can be achieved. In addition, dip coating method in which a low viscosity resin material (for example, a water-repellent coating resin used materials, for example with a viscosity resin material 1 cp hereinafter) is used to protect the glass of the pipe. But such embodiment using deep coating method in which a resin material even when the insulating layer (10) through holes (7) on the inner surface of (7c) with a thickness that is substantially uniform along the ring with. The, said semiconductor device (1) in number of bath method on the resin viscosity of at least 10 cp produced with the embodiment by dip coating method, such as by shape above the insulating layer (10) for a reliably hereinafter can be achieved. Said semiconductor device (1) in number of positive resin material using bath method, the through hole (7) on the inner surface of (7c) and semiconductor substrate (2) primary surface (2b) an insulation layer (10) is provided on the substrate. The insulating layer (10) in contact hole (16) by developing the exposed and parts, insulating layer (10) to contact hole (16) formed on the substrate. The, such as by shape above the insulating layer (10) and in addition can be achieved for a reliably hereinafter. In addition, exposure and development are provided with an isolating layer (10) formed depressions (17) by, insulating layer (10) in contact hole (16) are formed so that the thickness of the portion of corresponding to (i.e., contact hole (16) parts of the insulating layer (10) of semiconductor substrate (2) the thickness of the inner peripheral surface (2b) is provided on the insulating layer (10) having an average thickness of the sum of the height of H because of 1/2 hereinafter D portion) having a desired contact hole (16) for a reliably hereinafter can be achieved. Said semiconductor device (1) number of silicon nitride and oxide bath method (2) light-transmitting substrate (5) is provided in dip coating method embodiment as follows. To this end, a thinned semiconductor substrate (2) can be using. A thinned semiconductor substrate (2) in the through hole (7) to pass through the depth of, 10 cp as dip coating method using a resin material having high viscosities at least the insulating layer (10) alternated each component insulating layer (10) to contact hole (16) for a hereinafter can be reliably formed. In addition, as shown in the 15 also, semiconductor substrate (2) primary surface (2a) contains a light transmissive substrate (5) the adhesive layer (6) is installed through a sputtering process can be used now. In this case, the inner peripheral surface (2a) is number 1 wiring (3) so as to cover the oxide layer (18) is provided with a disclosed. The, semiconductor substrate (2) light-transmitting substrate (5) is unclamped or not provided insulating layer (10) in the inner peripheral surface (2a) with the periphery of the reinforcing layer from height H since functions as a through hole (7) in particular efficient in view of ensuring a sufficient strength of the peripheral portion. In addition, also as shown in the 16 and 17 also, the lead electrodes (9) semiconductor substrate (2) primary surface (2b) protruding from, the through hole (7) is positioned inside the ceramics disclosed. As shown in the 16 also even in this case, semiconductor substrate (2) primary surface (2a) light transmitting substrate (5) the adhesive layer (6) is installed through a may be made, or also 17 as shown in the, semiconductor substrate (2) primary surface (2a) light transmitting substrate (5) the adhesive layer (6) mounted through the need disclosed. (During industrial availability) According to the present invention, ratio of volume of the semiconductor substrate through the ball while number billion, electrical connection through a through hole of a semiconductor device ensure [...] narrower than the number. 1.. Semiconductor device, 2.. semiconductor substrate, 2a.. inner peripheral surface (surface number 1), 2b.. inner peripheral surface (surface number 2), 3.. number 1 wiring, 3a.. pad part, 7.. through hole, 7a.. number 1 opening, 7b.. number 2 opening, 7c.. inner surface, 8.. number 2 wiring, 9.. with the lead electrodes (bump electrodes), 10.. insulating layer, 10a.. opening, 10b.. surface, 120.. mounting substrate, 120a.. inner peripheral surface (surface number 3), 121.. number 3 wiring, APD.. avalanche photo diode. A through hole 7 is a vertical hole. When attention is paid to regions on both sides of a center line CL of the through hole 7 in a plane including the center line CL of the through hole, it is assumed that a segment that connects a first point X1 corresponding to the edge of an opening 10a of an insulating layer 10 and a second point X2 corresponding to the edge of a second opening 7b is a first segment S1, a segment that connects the second point X2 and a third point X3 corresponding to an intersection point between the second opening 7b and a surface 10b of the insulating layer 10 is a second segment S2, and a segment that connects the third point X3 and the first point X1 is a third segment S3. In this case, the first area A1 of the insulating layer 10 that is located on one side with respect to the first segment S1 is larger than the sum of the second area A2 of the insulating layer 10 that is surrounded by the first segment S1, the second segment S2, and the third segment S3 and the third area A3 of the insulating layer 10 that is located on the other side with respect to the third segment S3. Number 1 and number 2 surface of surface facing each other, said number 2 from the surface of a semiconductor substrate and said number 1 surface with through holes, said through holes are provided in said number 1 surface part of said number 1 number 1 number 1 wiring located openings on the front surface, said front surface of said through hole are provided in the inner and said number 2 surface through hole said number 2 number 2 through an opening continuous insulating layer, said surface of said insulating layer is arranged on the surface side of said number 1 and number 2 is electrically connected to a wiring having a wiring in at said number 1, vertical hole and said through hole, said through hole of said both sides of the centreline region with respect to the plane center line along a each of a noted when, said number 1 corresponding to edges of the opening with respect to said insulating layer, said number 2 the line segment connecting the number 1 and number 2 point a corresponding to the edges of the opening, said number 2 points, said point corresponding to said opening said number 2 insulating layer surface regions with a number 2 and number 3 the line segment connecting point, said number 3 points, said number 1 number 3 line connecting the point at which a line, said line segment is positioned on the inner surface of said through hole to said number 1 correspond to the number 1 said insulating layer, said number 1 segment, said number 2 segment, said segment and said number 3 is surrounded by a insulating layer area and number 2, said number 3 against said inner surface of said through hole is positioned on the opposite line number 3 area larger than the sum of said insulating layer semiconductor device. According to Claim 1, said number 1 that of said insulating layer in said surface at the point said insulating layer surface inclination greater than said semiconductor device said number 3. According to Claim 1 or Claim 2, said inner surface of said through hole provided through said inner surface of said surface of said insulating layer is less than said average angle ball average inclination angle formed by a semiconductor device. As described in claim either claim 1 to claim 3, said centerline of said each of said region including said through hole when said both sides of the centreline plane of interest, said number 1 points corresponding to the distance between the point number 4 said number 1 edges of the opening larger than said opening said insulating layer semiconductor device. As described in claim either claim 1 to claim 4, said number 1 wiring portion for covering the opening said number 1 and said pad, said number 1 edges of the opening and said insulating layer and said intersection of said said number 1 greater than the distance between the edges of the opening edges of the opening exposed semiconductor device. As described in claim either claim 1 to claim 5, said depth of said number 2 through hole opening size in semiconductor device divided by width ratio 1 hereinafter. As described in claim either claim 1 to claim 6, said insulating layer resin ([...]) consisting of semiconductor device. As described in claim either claim 1 to claim 7, said inner surface of said through hole of said insulating layer provided said continuous plane surface a semiconductor device. As described in claim either claim 1 to claim 8, said inner surface of said through hole of said insulating layer provided said surface said surface said number 2 provided a semiconductor device insulating layer said continuous surface is plane. As described in claim either claim 1 to claim 9, provided with a plurality of number 3 wiring the surface number 3, surface opposing said number 3 arranged to the mounting substrate also having said number 2 surface, said semiconductor substrate is provided with a plurality of avalanche photo diode preamplifiers mode of operation, said through hole, said number 1 wiring, and said number 2 to arranged inside said avalanche photo diode corresponding to each of a plurality of wiring, a plurality of said each avalanche photo diode, said number 1 corresponding to the wire and electrically connected to corresponding said number 2 wiring, a plurality of said number 3 the contact holes are connected, through bump electrodes electrically connected to the corresponding said number 2 wiring a semiconductor device.
