SEMICONDUCTOR DEVICE, VERTICAL FIN FIELD EFFECT TRANSISTOR, AND MANUFACTURING METHOD THEREOF

Advantages and features of the present invention, achieve the appended drawing method and an electronic component connected to the reference surface with specifically carry activitycopyright will in the embodiment. In the embodiment in the present invention refers to hereinafter however limited to various different rather than the disclosure are embodied in the form of percussion, in the embodiment of the present invention disclosure is completely only the are and can be utilized, the present invention is provided to a target area of the invention completely for alerting the person with skill in the art in categories to which ball number, defined by category of the present invention refers to claim only disclosed. Drawing layer in size and area as described above for intelligibility of the parsing exaggerated colors may be disclosed. Throughout the specification the same references refer to the same components.

One component (elements) other element "(connected to) connected" or "coupled (coupled to)" is referred to as the, another element when coupled or connected between another element comprising both interposed intermediate or foreseeable. While, one component other element "is directly connected (directly connected to)" or "directly coupled (directly coupled to)" is another element is not interposed intermediate referred by a goniophotometer.

Element (elements) or layer is another element or layer "on (on)" or "(on) on" another element or layer is referred as well as layered or other intermediate immediately above another element comprising both when interposed. While, element "(directly on) directly on" or "directly on" another element or layer is referred to intermediate is not interposed by a goniophotometer.

In the absence of other definitions, all terms used in the specification is provided to the present invention (including the techniques and the treatment) is in common sense can be understood to a person with skill in the art to can be used are disclosed. It is apparent that a term generally used in a pre-defined are not ideally or overly interpreted specially defined does not.

In hereinafter, in the embodiment of the present invention are also 1 and also with reference to the vertical fin field effect transistor according to some 1A is described substrate.

In the embodiment of the present invention are also includes vertical fin field effect transistor according to number 1 1 and also some 1A (100A) and number 2 vertical fin field effect transistor (100B) including a semiconductor device (100) of cross-sectional drawing are disclosed.

Number 1 vertical fin field effect transistor (100A) and number 2 vertical fin field effect transistor (100B) is, N type transistor or P type transistor be a. For example, number 1 vertical fin field effect transistor (100A) and number 2 vertical fin field effect transistor (100B) is, of the same type of semiconductor or, or be a different types of semiconductor.

Number 1 vertical fin field effect transistor (100A) is, number 2 vertical fin field effect transistor (100B) on can be substantially the same. The, descriptions and to receive, hereinafter number 1 in vertical fin field effect transistor (100A) are also described to, number 1 vertical fin field effect transistor (100A) vertical fin field effect transistor (100A) will referred to as. Number 1 vertical fin field effect transistor (100A) substrates for, number 2 vertical fin field effect transistor (100B) pivotably applied against said contact member. Number 2 vertical fin field effect transistor (100B) number 1 is vertical fin field effect transistor (100A) when other types of transistor, source/drain regions doped impurities can differ from each other disclosed.

Vertical fin field effect transistor (100A) is, pin structure (160), lower source/drain (120) and an upper source/drain (130) can be comprising.

A fin structure (160) at the bottom source/drain (120) disposed on the upper side of, upper source/drain (130) can be disposed beneath the surface of. For example, a fin structure (160) is, lower source/drain (120) extending perpendicularly from the upper surface of can be, lower source/drain (120) and the top source/drain (130) can be interposed between. In this case, a fin structure (160) has a height (H1), vertical fin field effect transistor (100A) can be equal to a gate length. A fin structure (160) has a height (H1), upper source/drain (130) and a lower source/drain (120) and a fin structure between (160) sidewall (160 a-S) can be measured along.

Lower source/drain (120) is, using ion implantation or diffusion process, substrate (110) can be formed by doping impurities in. Substrate (110) is, silicon and silicon and low friction (SiGe) hafnium alloy which includes either a can. Vertical fin field effect transistor (100A) is N type transistor if, impurity is phosphorus (phosphorus), such as antimony or arsenic (arsenic) (antimony), be a N type impurity. Vertical fin field effect transistor (100A) is P type transistor if, impurity is boron (boron), such as aluminum (aluminum) or gallium (gallium), P type impurity be a.

Vertical fin field effect transistor (100A) is, pin structure (160) can be in the channel. For example, vertical fin field effect transistor (100A) when are turned on, channel is pin structure (160) sidewall (160 a-S) can be formed along. At this time, transistor turn-on current, flows along channel can be.

Vertical fin field effect transistor (100A) is in addition, gate oxide layer (170), gate electrode number 1 (180), lower spacer (140) and an upper spacer (150) can be a.

Gate oxide layer (170) and gate electrode number 1 (180) is, upper spacer (150) and a lower spacer (140) can be interposed between. For example, gate oxide layer (170) and gate electrode number 1 (180) of the laminated structure is, upper spacer (150) and a lower spacer (140) can be interposed between.

Upper spacer (150) and lower spacer (140) is, pin structure (160) sidewall (160 a-S) can be formed on. Upper spacer (150) is, number 1 sidewall (150 a-S1) and sidewall number 2 (150 a-S2) can be comprising. Lower spacer (140) includes a sidewall number 1 (140 a-S1) and sidewall number 2 (140 a-S2) can be comprising. A fin structure (160) sidewall (160 a-S) is, upper side wall portion, and a central bottom and inner wall can be sidewall portion. A fin structure (160) sidewall (160 a-S) central sidewall portion, upper side wall portion can be located between the bottom and inner wall.

For example, upper spacer (150) number 1 of sidewall (150 a-S1) is, pin structure (160) can be upper sidewall of the transfer. In some in the embodiment, upper spacer (150) number 1 of sidewall (150 a-S1) is, pin structure (160) in contact with the upper surface of portion can be.

For example, lower spacer (140) number 1 of sidewall (140 a-S1) is, pin structure (160) can be disposed on the lower sidewall of the portion. In some in the embodiment, the lower spacer (140) number 1 of sidewall (140 a-S1) is, pin structure (160) in contact with the lower sidewall of the portion can be.

Lower spacer (140) is, two adjacent number 1 vertical fin field effect transistor (100A) and number 2 vertical fin field effect transistor (100B) can be shared by. In this case, lower spacer (140) is in addition, number 2 vertical fin field effect transistor (100B) pin structure (160') can be disposed on a side wall of. In some in the embodiment, sidewall number 2 (140 a-S2) is, number 2 vertical fin field effect transistor (100B) pin structure (160') can be in contact with the side wall.

Upper spacer (150) is, CVD (Chemical Vapor Deposition) process or PECVD deposited silicon nitride (silicon nitride) is deposited (Plasma Enhanced CVD) can be a. Upper spacer (150) and lower spacer (140) is, including integrated circuit comprising silicon nitride can be substantially the same.

In some in the embodiment, a fin structure (160) is, preliminary upper spacer layer, a sacrificial layer and a preliminary lower spacer layer sequentially stacked pre-laminate can be formed within a structure. The, vertical fin field effect transistor (100A) gate length, number can be determined by the thickness of the pre-laminate structure. Pre-laminated structure is, with reference to the entire 4 also carry.

Gate oxide layer (170) is, upper spacer (150) of the bottom of the spacer (140) can be formed on the upper side of. Gate oxide layer (170) is, in addition, upper spacer (150) and a lower spacer (140) exposed between a fin structure (160) can be formed on a central side wall portion. The, gate oxide layer (170) C may have the shape.

Gate oxide layer (170) is, HfO₂ Or HfSiO including a high-K dielectric material can be a (high-a k dielectric material). Gate oxide layer (170) is, CVD process, PECVD process, MOCVD (metallorganic CVD) process, or ALD (Atomic Layer Deposition) process including, can be formed using various deposition process.

Gate electrode number 1 (180) the gate oxide layer (170) can be disposed on. In this case, gate oxide layer (170) is, gate electrode number 1 (180) and pin structure (160) sidewall (160 a-S) can be interposed between. Gate oxide layer (170) is, upper spacer (150) on gate electrode number 1 (180) can be interposed between. In addition, gate oxide layer (170) is, lower spacer (140) number 1 on gate electrode (180) can be interposed between. In this case, gate electrode number 1 (180) is, gate oxide layer (170) to be formed on [khen foam (conformally), C shape may have.

The, gate oxide layer (170) and gate electrode number 1 (180) is a layered structure (SS), upper spacer (150) and a lower spacer (140) can be interposed between. In this case, gate oxide layer (170) and gate electrode number 1 (180) laminated structure (SS) of one side of the wall, and a fin structure (160) sidewall (160 a-S) can be in contact with. In addition, laminated structure (SS) of [...], upper spacer (150) sidewall of number 2 (150 a-S2) can be vertically aligned with the.

In some in the embodiment, gate electrode number 1 (180) is, as shown in also 1A, C shape forming gate oxide layer (170) can be complete filling. Other components are also shown in 1A, corresponding components of Figure 1 can be substantially the same. The, descriptions for clarity, the aforementioned capacity with redundant dispensed to each other.

Gate electrode number 1 (180) is a nitride including titanium nitride (TiN) can be. However, the present invention herein are number one are not disclosed. For example, gate electrode number 1 (180) is, such as TiN/TaN/TiAlC, at least two different materials can be formed.

Vertical fin field effect transistor (100A) is, two adjacent pin structure (160) that is located between the gate electrode number 2 (190) can be comprising. Vertical fin field effect transistor (100A) when viewed in the upper, gate electrode number 2 (190) includes a pin structure (160) can be surrounds. Gate electrode number 2 (190) upper surface of the, gate oxide layer (170) and the top spacer (150) are coplanar with the interface between can be located. However, the present invention herein are number one are not disclosed. For example, gate electrode number 2 (190) upper surface of the, gate oxide layer (170) and the top spacer (150) positioned interface between greater or lesser than disapproval.

Gate electrode number 2 (190) and gate electrode number 1 (180) is, can be electrically connected to each other. For example, gate electrode number 2 (190) is, gate electrode number 1 (180) can be in contact with. The, vertical fin field effect transistor (100A) gate length, gate electrode number 2 (190) of the upper surface of without correlated with the, gate electrode number 1 (180) and capacitively (capacitively) connected fin structure (160) can be determined by the height of (H1).

Gate electrode number 2 (190) is, two adjacent number 1 vertical fin field effect transistor (100A) number 2 on vertical fin field effect transistor (100B) can be shared by.

Gate electrode number 2 (190) is, upper spacer (150) and a lower spacer (140) between gate electrode number 1 (180) can be defined by filling a gap (gap). For example, number 1 C-shaped gate electrode (180) into, gate electrode number 2 (190) portion of (190 a-P) can be inserted. The, gate oxide layer (170) and gate electrode number 1 (180) is a layered structure (SS) in addition, gate electrode number 2 (190) portion of (190 a-P) can be comprising.

Gate electrode number 2 (190) portion of (190 a-P), gate electrode number 1 (180) and gate oxide (170) is a layered structure (SS), upper spacer (150) and a lower spacer (140) can be interposed between. For example, the laminated structure (SS), upper spacer (150) and a lower spacer (140) can be filling a space between. In this case, gate electrode number 2 (190) portion of (190 a-P) is, C-shaped gate electrode number 1 (180) can be projects into.

In the embodiment of in also 1A, gate electrode number 2 (190) is, gate electrode number 1 (180) projects into may not disclosed. The, gate electrode number 2 (190) of the side walls, upper spacer (150) sidewall of number 2 (150 a-S2) can be vertically aligned with the. The laminated structure (SS '), gate oxide layer (170) and gate electrode number 1 (180) can be comprising. Laminated structure (SS ') includes a top spacer (150) and a lower spacer (140) can be interposed between.

The reference also 1 again, lower spacer (140) includes a gate electrode number 2 (190) and a lower source/drain (120) interposed between, gate electrode number 2 (190) and a lower source/drain (120) and prevents electrical shorting between can.

Upper spacer (150) includes a gate electrode number 2 (190) and the top source/drain (130) interposed between, gate electrode number 2 (190) and the top source/drain (130) prevents electrical shorting between can.

Semiconductor device (100) is in addition, insulating layer (300), a metallic capping layer (210), and can be contact electrode. Contact electrode is, gate contact electrode (220A) and an upper source/drain electrode (220B) can be comprising.

Gate contact electrode (220A) is, number 2 gate electrode (190) electrically connected to the, insulating layer (300) can be through. Resistance contact layer is number 1, number 2 gate electrode (190) and the gate contact electrode (220A) spacer between to reduce, gate electrode number 2 (190) and the gate contact electrode (220A) can be interposed between. In this case, gate contact electrode (220A) is, resistance contact layer can be in contact with the number 1.

Upper source/drain electrode (220B) is, upper source/drain (130) electrically connected to the, insulating layer (300) and a metallic capping layer (210) can be through. Resistance contact layer is number 2, upper source/drain (130) and the top source/drain electrode (220B) can be interposed between.

In the embodiment of the present invention are hereinafter also with reference to 2 to 16 also in vertical fin field effect transistor according to some is described substrate. Descriptions for clarity and the described prior redundant dispensed to each other.

In the embodiment of the present invention Figure 2 shows a vertical fin field effect transistor according to some number of order of method are also tank are disclosed. Figure 16 shows a vertical fin field effect transistor according to number of bath method also 3 to order to explain a cross-sectional drawing of Figure 2 also are disclosed.

Figure 3 shows a also, in the embodiment of the present invention are some according to of Figure 2 step (100) after the lower source/drain (120) and upon 2000.

Step (100) in, substrate (110) lower source/drain in (120) for forming, such as self-aligned ion implantation or diffusion process can be performed. When N type transistor is formed, phosphorus (phosphorus), such as antimony or arsenic (arsenic) (antimony), N type impurity substrate (110) may be doped into 2000. When P type transistor is formed, boron (boron), such as aluminum (aluminum) or gallium (gallium), P type impurity substrate (110) may be doped into 2000.

Substrate (110) is, hafnium silicon or low (SiGe) can be alloy.

In the embodiment of the present invention are also some according to of Figure 2 Figure 4 shows a step (110, 120, 130) after structure etched when performed. The reference also 4, is pre-laminated structure (PSS), pre-lower spacer layer (140P), sacrificial layer (SL), and preliminary upper spacer layer (150P) can be comprising. In pre-laminated structure (PSS), pre-lower spacer layer (140P), sacrificial layer (SL) and preliminary upper spacer layer (150P) is, substrate (110) from a given order can be stacked together disclosed. For example, the pre-laminate structure (PSS), substrate (110) can be formed on.

Pre-lower spacer layer (140P) is, comprising silicon nitride (silicon nitride) can be. The sacrificial layer (SL), comprising silicon (silicon) oxide or a silicon (silicon oxide) can be. Preliminary upper spacer layer (150P) is, can be a silicon nitride.

In some in the embodiment, pre-lower spacer layer (140P) and preliminary upper spacer layer (150P) is, including silicon nitride, can be formed to substantially the same. The thickness of the sacrificial layer (SL) (T_SL ) Is, of Figure 1 target gate length can be determined according to vertical fin field effect transistor.

In the embodiment of the present invention are also some according to of Figure 2 Figure 5 shows a step (140) after the, pre-laminated structure (PSS) number 1 (TR1) when formed in a trench etched.

Step (140) in, photolithography process, pre-laminated structure (PSS) number 1 (TR1) in trench for defining can be performed. For example, the patterned photoresist layer, preliminary upper spacer layer of Figure 4 (150P) can be formed on. The patterned photoresist layer, trench number 1 (TR1) (PSS) can be pre-laminated structure is formed to expose a region of.

After formation of the patterned photoresist layer, directional etching process step (140) can be performed. The, in pre-laminated structure (PSS), number 1 (TR1) trench can be formed. At this time, the patterned photoresist layer, can be used as directional etching plasma.

Trench (TR1) is number 1, through pre-laminated structure (PSS), lower source/drain (120) can be exposed. Trench (TR1) is number 1, pre-lower spacer layer (140P) from lower spacer (140) can be defining. Number 1 in addition includes a trench (TR1), (PSL) from sacrificial layer (SL) can be defining patterned sacrificial layer. Number 1 in addition includes a trench (TR1), can be also define preliminary upper spacer (P150). Preliminary upper spacer (150) is, upper spacer of Figure 1 (150) be further be patterned form. Upper spacer (150) the formation of, 10 also applies with reference to carry.

The directional etching process, it buys the fire anger carbon (CF₄ ) Using etching gas including fluorine (fluorine) such as a RIE process can be. For example, gas containing fluorine, silicon, silicon oxide or silicon nitride capping be.

In the embodiment of the present invention are also some according to of Figure 2 Figure 6 shows a step (150) formed after the liner (200) when a is etched.

Step (150) in, pre-liner, (conformally) [khen foam on part of Figure 5 structure can be formed. For example, pre-liner, but formed in the trench (TR1) number 1, number 1 (TR1) trench completely oscillation thereof can. In addition pre-liner, preliminary upper spacer (150) on the upper side of can be hydroxyl.

After preliminary liner, directional etching process including the RIE process, liner (200) in order to produce, can be performed on the pre-liner. Preliminary upper spacer (150) and a lower source/drain (120) is then formed on the part of the liner, an exposure region of the number of special directional 1308. The, number 1 (TR1) to eliminate voids formed in the sidewall portion of the trench liner, directional etching process is performed after remain disclosed. The remaining portion is pre-liner, liner (200) can be referred to. For example, liner (200) is, number 1 (TR1) can be formed on sidewalls of the trench.

Pre-liner, CVD process, can be formed using a PECVD process or ALD process. Liner (200) is, can be a silicon nitride. For example, liner (200) is, upper spacer (150) and lower spacer (140) can be substantially on the same material.

Liner (200) is, [...] of Figure 2 step (160) for seed layer (seed layer) and patterned sacrificial layer of epitaxial growth process to prevent short (PSL), (PSL) patterned sacrificial layer covering disclosed.

Figure 7 shows a also, in the embodiment of the present invention are some according to of Figure 2 step (160) formed after the fin structure (160) when a is etched.

Step (160) in, pin structure (160) is, lower source/drain (120) by seed layer, can be epitaxial so formed. Liner (200) is, epitaxial growth furnace structure patterned sacrificial layer (PSL) and pin (160) can be prevented from being short circuited. In some in the embodiment, a fin structure (160) is, lower source/drain (120) can be from epitaxial growth furnace. However, the present invention herein are number one are not disclosed. For example, liner (200) can be applied to the number of special, and a fin structure (160) includes a patterned sacrificial layer from epitaxial growth furnace (PSL) may be disclosed.

In the embodiment of the present invention are also some according to of Figure 2 Figure 8 shows a step (170) after the upper source/drain (130) etched upon.

Step (170) in, upper source/drain (130) is, pin structure (160) can be from epitaxial so formed. Upper source/drain (130) in of epitaxial growth process, N type or P type impurities may be doped disclosed. In the case of type transistor N, N type impurities, upper source/drain (130) doping 1308. of epitaxial growth process. In the case of P type transistor, P type impurities, upper source/drain (130) doping 1308. of epitaxial growth process.

A fin structure (160) and an upper source/drain formation of (130) the formation of, or is carried out in situ (in non-situ), can be carried out continuously. For example, a fin structure (160) and an upper source/drain (130) is, using epitaxial growth process can be formed in a continuous manner. A fin structure (160) and an upper source/drain (130) is, low friction can be silicon or hafnium alloy.

In the embodiment of the present invention are also some according to of Figure 2 Figure 9 shows a step (180) formed after the capping layer (210) etched upon.

Two adjacent to deposit capping layers (210, 210') is, reference number 2 (TR2) [...] 10 also can be formed in the trench region. In the capping layer (210) is, pin structure (160) is formed on, upper source/drain (130) covering disclosed. Other deposit capping layers (210 ') is, other pin structure (160') can be formed on.

Step (180) in, pre-cap layer is used, PECVD process or CVD using the process, can be formed on the structure of Figure 8. Pre-cap layer is used, a titanium nitride (TiN) can be. Pre-capping layer followed by, e.g., a thermal treatment process is performed, an upper source/drain pre-capping layer (130) can be reacts with silicon.

For example, a metallic capping layer of the pre-amorphous (silicidation reaction), upper source/drain (130) can be generated for. In the capping layer formed on the upper portion of the preform, not be silicidation reaction to occur. The etching plasma, formed on the upper portion of the preform number 1308. maxillo-capping layer. The particles remain, silicidation reaction pre cap layer is used, the capping layer (210) can be referred.

Figure 10 shows a also, in the embodiment of the present invention are some according to of Figure 2 step (190) formed when a number 2 (TR2) after the trench is etched.

Step (190) in, directional etching process including the RIE process, can be performed on the structure of Figure 9. In the capping layer (210, 210 ') is, used as the, two adjacent to deposit capping layers (210, 210') number 2 (TR2) between the trench can be formed. Step (190) in, directional etching process, the lower spacer (140) are exposed through the trench can be performed until the number 2 (TR2). Trench (TR2) is number 2, preliminary upper spacer of Figure 9 (150) through the, upper spacer (150) can be defining.

In some in the embodiment, upper spacer (150) is, trench (TR1) number 1 and number 2 can be formed by trench (TR2). Trench number 2 (TR2) is in addition, patterned sacrificial layer patterning (PSL), number 2 (TR2) (PSL) capable of patterned sacrificial layer exposed through the trench.

Figure 11 shows a also, in the embodiment of the present invention are some according to of Figure 2 step (200) after the recessed trench formed in a decodes (RTR).

Step (200) in, the patterned sacrificial layer (PSL), etched in etching or dry etching process including using, trench (TR2) number 2 through number 1308. wetting ability. Liner (200) also in addition, step (200) in the wetting ability of etched in a number can be disclosed. For example, the trench of Figure 10 number 2 (TR2), laterally (laterally) to be elongated along the disclosed. The, pin structure (160) of the side walls, can be exposed by the recessed trench (RTR). In this case, upper spacer (150) and the fin structure (160) interposed between liner (200) is, number 1 residual liner (200') thereof can remain. In addition, lower spacer (140) and the fin structure (160) interposed between liner (200) is, number 2 residual liner (200") thereof can remain.

In some in the embodiment, liner (200), lower spacer (140) and an upper spacer (150) is, including silicon nitride, can be substantially the same material.

In this case, number 1 residual liner (200') and an upper spacer (150) is, as shown in also 11A, unitary component including can be viewed on the same material. In addition, in this case, number 1 residual liner (200') is, as shown in also 11A, upper spacer (150) is shown portion of disapproval. Residual liner number 2 (200") and lower spacer (140) likewise, as shown in also 11A including unitary component can be viewed on the same material. In this case, number 2 residual liner (200") is, as shown in also 11A, lower spacer (140) is shown portion of disapproval.

In hereinafter, descriptions for facilitating the, liner (200), lower spacer (140) and an upper spacer (150) is, including silicon nitride, has been formed to assume substantially the same to each other. The, step (200) the subsequent steps, a 11A also through a browser substrate.

However, the present invention herein are number one are not disclosed. For example, liner (200) is, upper spacer (150) and lower spacer (140) to a substance which may be formed into different materials disapproval. In this case, step (200) the subsequent steps, can be performed on the structure of Figure 11.

Figure 12 shows a also, in the embodiment of the present invention are some according to of Figure 2 step (210) formed after the preliminary gate electrode number 1 (180P) and the pre gate oxide layer (170P) etched upon.

Pre-gate oxide layer (170P) is, CVD process, using PECVD process or MOCVD process including deposition process, recessed trench (RTR) can be so formed that in [khen foam.

Pre-gate oxide layer (170P) is, recessed trench (RTR) may have a predetermined thickness such a degree that it does not fill completely. For example, preliminary gate oxide (170P) is, pin structure (160) side wall, upper spacer (150) of the bottom of the spacer (140) can be formed on the upper side of. Pre-gate oxide layer (170P) is, in addition, upper spacer (150) sidewall of number 2 (150 a-S2) can be formed on. Upper spacer (150) is in addition, a fin structure (160) in contact with the sidewall of sidewall number 1 (150 a-S1) can be comprising.

Pre-gate oxide layer (170P) is, hafnium oxide (HfO₂ ) Or hafnium silicon oxide (HfSiO) including a high-K dielectric material can be.

Number 1 preliminary gate electrode (180P) is, recessed trench (RTR) [khen foam in so formed or, may not be completely filling recessed trench (RTR). For example, number 1 preliminary gate electrode (180P) is, recessed trench (RTR) complete filling of gap (RTR-a G) can be disclosed. The recessed trench (RTR) gap (RTR-a G), upper spacer (150) and a lower spacer (140) can be interposed between.

However, the present invention herein are number one are not disclosed. For example, number 1 preliminary gate electrode (180P) is, as shown in also 12A, recessed trench (RTR) can be complete filling of gap (RTR-a G). But, even in this case, number 1 preliminary gate electrode (180P) (RTR) a recessed trench completely oscillation thereof can. Or, for example, number 1 preliminary gate electrode (180P) is, fully fill the recessed trench (RTR) may be filled.

Number 1 preliminary gate electrode (180P) is, can be formed using a CVD process. Number 1 preliminary gate electrode (180P) is, including a titanium nitride (TiN) can be formed through the second. However, the present invention herein are number one are not disclosed. For example, number 1 preliminary gate electrode (180P) is, titanium nitride/titanium aluminum carbide (TiAlC)/tantalum nitride (TaN) (TiN) such as, two or more different materials can be layer.

Figure 13 shows a also, in the embodiment of the present invention are some according to of Figure 2 step (220) (TR3) formed in a trench etched after the number 3. Of Figure 2 step (220) is, can be performed on the structure of Figure 12.

Step (220) in, directional etching process including the RIE process, can be performed on the structure of Figure 12. The, number 3 (TR3) trench can be formed. Step (220) of directional etching plasma, preliminary gate oxide (170P) and number 1 preliminary gate electrode (180P) each, gate oxide layer (170) and gate electrode number 1 (180) is patterned 1308.

For example, step (220) of directional etching process, number 3 (TR3) trench through lower spacer (140) can be performed until the upper surface of exposed. In this case, the capping layer (210, 210') is, preliminary gate oxide (170P) and number 1 preliminary gate electrode (180P) each gate oxide layer (170) and gate electrode number 1 (180) and apparatus for patterning can be used as is. Gate oxide layer (170) and gate electrode number 1 (180) may have the C shape. The, C shape forming gate oxide layer (170) and gate electrode number 1 (180) is, number 3 (TR3) trench gap (TR3 provided G) can be partially wraps around.

Upper spacer (150) is in addition, step (220) can be used as directional etching plasma.

The number 3 (TR3) trench gap (TR3 provided G), upper spacer (150) and lower spacer (140) can be overlapping.

Number 1 preliminary gate electrode (180P) is, ammonium hydroxide (NH₄ OH)/hydrogen peroxide (H₂ O₂ ) To be etched. However, the present invention herein are number one are not disclosed. For example, titanium nitride (TiN) including a capping layer (210, 210') number 1 for preliminary gate electrode (180P) of etchant having etch selectivity can be used.

Pre-gate oxide layer (170P) is, carbon tetrachloride (CCl₄ ) Such as, a etchant gas including chlorine (chlorine) to be etched. However, the present invention herein are number one are not disclosed. For example, the capping layer (210, 210') pre-gate oxide layer (170P) can be used an etchant gas is having etch selectivity of the concave disclosed.

The reference again also 12A, of Figure 2 step (220) is, 12A structure also can be performed. In this case, is also 13A, step (220) formed after the trench (TR3) number 3 is shown as follows. Unlike trench of Figure 13 number 3 (TR3) on, number 3 (TR3) is also 13A of trench, trench of Figure 13 number 3 (TR3) gap (TR3 provided G) thereof can not.

In the embodiment of the present invention are also some according to of Figure 2 Figure 14 shows a step (230) formed after the preliminary gate electrode layer number 2 (190P) etched upon.

Number 2 preliminary gate electrode layer (190P) is, number 3 (TR3) trench in, number 3 (TR3) [khen foam can be so formed to fill a trench. Number 2 preliminary gate electrode layer (190P) is in addition, capping layer (210) can be hydroxyl.

CVD process or MOCVD process, preliminary gate electrode layer number 2 (190P) for forming can be performed. Number 2 preliminary gate electrode layer (190P) is, can be conductive material including tungsten or copper.

Figure 15 shows a also, in the embodiment of the present invention are some according to of Figure 2 step (240) can be carried out is formed gate electrode number 2 (190) etched upon.

Of Figure 14 number 2 preliminary gate electrode layer (190P) is, number 2 gate electrode (190) for forming, using an etch-back process to be elongated along the disclosed. Gate electrode number 1 (180) is number 2 gate electrode (190) and electrically connected with, vertical fin field effect transistor (100A) gate length, gate electrode number 1 (180) (capacitively coupled) capacitively coupled with a fin structure (160) determined by the height of since, step (240) etch back process, may have a process margin.

In dependence on the variables of a half of the circular, gate electrode number 2 (190) upper surface of the, gate oxide layer (170) and the top spacer (150) are coplanar with the interface between the lower surface of or, or located higher than the interface, can be lower than an interface. For facilitating the description, in Figure 15, gate electrode number 2 (190) upper surface of the, gate oxide layer (170) and the top spacer (150) are coplanar with the interface between the lower surface of the event that was shown.

In the embodiment of the present invention are also some according to of Figure 2 Figure 16 shows a step (250) formed after the contact electrode (220A, 220B) etched upon.

Step (250) in, insulating layer (300) is, can be formed on the structure of Figure 15. For example, insulating layer (300) is, in the capping layer (210) and number 2 gate electrode (190) can be formed on. Contact electrode (220A, 220B) is, insulating layer (300) can be through. For example, gate contact electrode (220A) is, number 2 gate electrode (190) electrically connected with, insulating layer (300) can be through. In addition, upper source/drain electrode (220B) is, upper source/drain (130) electrically connected with, insulating layer (300) and a metallic capping layer (210) can be through. Gate contact electrode (220A) is, in the capping layer (210, 210') using, gate electrode number 2 (190) can be self-aligned.

Resistance contact layer, gate contact electrode (220A) and number 2 gate electrode (190) and an upper source/drain region between electrode (220B) can be interposed between the upper source/drain.

Lower source/drain electrode is, lower source/drain (120) electrically connected with, insulating layer (300) and a lower spacer (140) can be through. Resistance contact layer is, lower source/drain (120) and a lower source/drain electrode can be interposed between.

Viewed in the upper, lower spacer (140) includes a pin structure (160) can be surrounds. The, lower source/drain electrode is, lower source/drain (120) electrically connected with, the lower spacer (140) can be through.

In some in the embodiment, pre-lower spacer layer, preliminary upper spacer layer pre-laminated structure is uneven, and a fin structure (160) is formed can be formed. The, vertical fin field effect transistor target gate length, thickness can be determined by a sacrifice layer.

Of Figure 13 can be applied to a structure of Figure 2 step (230) step (250) is, also 1A semiconductor device (100') to form, 13A structure also can be applied against. Descriptions for clarity, step (230) to step (250) description is given of a dispensed to each other.

In hereinafter, in the embodiment of the present invention are semiconductor device including a semiconductor module according to some reference also 17 is described substrate.

In the embodiment of the present invention also Figure 17 shows a semiconductor device including a semiconductor module shown side according to some number produced therewith are disclosed.

The reference also 17, semiconductor module (500) in the embodiment according to the semiconductor device of the present invention are some (530) can be a. Semiconductor device (530)-sound module substrate (510) to be mounted on be. Semiconductor module (500) semiconductor module substrate (510) which is mounted on microprocessor (520) can be further comprises. Input/output terminal (540) is, semiconductor module substrate (510) can be disposed at least on one side. Semiconductor module (500) comprising a memory card or SSD (solid state drive) can be.

In hereinafter, in the embodiment of the present invention are electronic system including a semiconductor device according to 18 also some reference is described substrate.

In the embodiment of the present invention are electronic system including a semiconductor device according to some Figure 18 shows a block also are disclosed.

The reference also 18, in the embodiment of the present invention is prepared by the semiconductor device according to some number, electronic system (600) can be applied. Electronic system (600) is, body (610), a microprocessor unit (620), power supply device (630), by functional units (640) and display controller unit (650) can be comprising.

Body (610) is, like motherboard or system board including PCB can be. A microprocessor unit (620), power supply device (630), by functional units (640) and display controller unit (650) is, body (610) can be mounted on or disposed. Display unit (660) body (610) or disposed on the upper side of, body (610) can be disposed on the outer peripheral surface. For example, display unit (660) is, body (610) disposed on the surface of, display controller unit (650) for selecting can be processed by.

Power supply device (630) is also a constant voltage power supply from the power supply, a microprocessor unit (620), by functional units (640), display controller unit (650) supplies an electric power to produce various voltage levels such as can be. A microprocessor unit (620) is, by functional units (640) the display unit (660) for the number a, power supply device (630) from voltage be subjected to ball number.

By functional units (640) is, electronic system (600) can be a variety of performing a plurality of functions. For example, electronic system (600) such as mobile electronic number the center of the cellular phone, by functional units (640) is dialing system, display unit (660) video on either, or external device (670) with via speaker outputting voice for performing wireless communication function such as, various components can be. In addition, electronic device (600) including the camera when, by functional units (640) includes Image processor functions disapproval.

While, if electronic device (600) is in order to increase the capacity memory card and identification, by functional units (640) the memory card controller functions as a disapproval. By functional units (640) is, wired or wireless communication unit (680) through, external device (670) disapproval to exchange a signal on. Further, electronic system (600) for expanding this capability if a USB (Universal Serial Bus), by functional units (640) can be carry out tasks of the interface controller. By functional units (640) in the embodiment of the present invention is a semiconductor device according to some number produced therewith can be.

In hereinafter, in the embodiment of the present invention also refers to a semiconductor device including electronic system according to some number 19 is described S. produced therewith.

In the embodiment of the present invention also Figure 19 shows a semiconductor device including a block number according to some electronic system is produced therewith.

The reference also 19, electronic system (700) can be mobile device or computer. For example, electronic system (700) bus (720) the data communication is made between memory system (712), microprocessor (714), RAM (716), and user interface (718) can be a. Microprocessor (714) is program may be, electronic system (700) [...] be a number. RAM (716) has a microprocessor (714) can be used as selective memory. For example, microprocessor (714) or RAM (716) is, in the embodiment of the present invention can be prepared by the semiconductor device according to some number comprising.

Microprocessor (714), RAM (716) and/or other components may then, can be disposed in a single package. User interface (718) is an electronic system (700) or an equivalent data, electronic system (700) can be used for both output data from. Memory system (712) has a microprocessor (714) selective code, microprocessor (714) data processed by, or can be storing data that are received from the outside. Memory system (712) includes the controller and a memory can be.

Or more of the present invention in the embodiment described with reference to the attached drawing but, rather than limited to the present invention refers to said in the embodiment are different in various forms can be tank number, in the present invention is technical idea of the present invention is provided to essential features or person with skill in the art without changing other specific embodiment can form can be understand are disclosed. In the embodiment described above the exemplary non-limiting all sides are understood to which must substrate.