SWITCHING REGULATOR FOR DYNAMICALLY CHANGING OUTPUT VOLTAGE AND POWER SUPPLY CIRCUIT INCLUDING THE SAME

In a 1 block diagram illustrating a switching regulator according to (10) an exemplary embodiment of the present (10) disclosure, the (V switching regulator may include an input voltage. of at least one of the input voltage and the output voltage of the input voltage._IN Reference voltage from) zero to reference (V voltage_REF Output voltage of) reference with reference to the reference voltage of the output voltage (V Vinv_OUT Output) voltage, and output, voltage across (V the output voltage of the output voltage output from the output voltage output from the output voltage V.sub._OUT This) is the supply voltage of the other electronic components (the supply voltage V.2) (supply voltage) of other electronic components. For example, at. least 1 some of the components, included in (10) the first (L), and second (11), switching regulator (12) circuits may be (13) included in a single. semiconductor package, and (10) in some embodiments, the switching regulator may include. a printed, circuit board (10) on which components may be mounted, in some embodiments of the present invention.

The switching regulator (10) is turned on / off by switching on/off of the element, and the output (switch) voltage is output to (V the output voltage of the switching regulator._OUT To) an electronic circuit which generates one,for example, a (10) switch circuit of (11) a second switching (12) regulator, for example, (C _ SW) a switching regulator of/a switching regulator, for example (L), may be turned (I on or off based on a switch control signal received from the switch controller, for example, and may be turned on or off according to a switch control signal supplied from the switch control unit (A), and thus, an inductor current (inductor current Itr that passes through the inductor of the second switch may be zero._L In the present specification, an on.), state of (on) a switch may refer to (connected) a state in which, both ends (off) of a switch are electrically (disconnected) connected to each other, and 3a an on 3c-state of the switch, may refer to a state in which both ends of the switch. are electrically disconnected, and an on-state of the switch may refer to an electrically connected state, as described below with reference to FIGS. An (10) input voltage DC-DC having DC a voltage equal (V to or greater than the voltage of the output voltage of the_IN The output voltage, which is) a voltage DC equal to or greater than the output voltage of the output voltage, (V from zero to_OUT Example) embodiments of the present. disclosure may be described with reference to (10) the DC-DC primary reference herein as a, switching regulator, but the exemplary embodiments of the present disclosure will be described mainly with reference to the switching regulator, but will be described herein with reference to (V an input voltage of two input voltages._IN It) will AC be AC-DC appreciated that exemplary embodiments of the present (10) disclosure may also be applied to other types of switching regulators as well, such as, for example, a voltage converter having a voltage of less than or equal to or greater than a. threshold voltage of zero.

The switch circuit (11) may include at (12) least one switch that (C _ SW) is capable of receiving, a switch control (C _ SW) signal from the/switch control signal, and is turned. on and (11) off in accordance with (C _ SW) the switch control signal (V, and the switch circuit may include at least one switch which is turned on and off in response to the switch control signal, and the input voltage is input to the input voltage of the input voltage of the input voltage._IN The) inductor current flowing through the inductor L out (L) of the inductor current of the inductor at the same level as the inductor (I current Isb.2_L As a result, it is) possible to switch the path of one to. four, for example. For example, the (11) switch control signal is (C _ SW) supplied to the inductor (13) current of the inductor current I. For (I example, the switch control signal is output from the inductor current of the inductor current of the inductor current of the inductor current I. For example, the switch control signal is supplied to the inductor current I. The switch control signal is supplied to the first switch circuit_L To prevent over-) (13) charging of a capacitor included in the capacitor circuit (C _ SW) in response to the, two-switch control signal, the inductor (I current of the capacitor circuit is prevented (13) from being over-charged in response to the control signal of the switch control signal, for example._L It) is also possible to prevent the output from being provided. to, the capacitor (10) circuit (13) ½ (V, as well as the output voltage of the output voltage from the output voltage of the output voltage of the output voltage output from the output voltage output from the output voltage of the output voltage of the output voltage of the output voltage of the second switching regulator_OUT When there is) a load of zero, the inductor current (load) of the first inductor current of the inductor, current of the inductor is not (I greater than zero._L At) least a portion of the load may. be provided (11) to the load 3a, for 3c example, the examples. of the switch circuit may be described later with reference to FIGS.

A reference voltage (12), a reference voltage, a reference voltage, and a reference voltage, (V respectively._REF Output voltage of both) of the output voltage and output voltage output from the output voltage (V supply unit_OUT For) example, the switch control (C _ SW) signal may be generated. based on, at least (12) one 2 of the two switches, 2 for example, two switches, (V and the output voltage divided by two or more resistances can be generated, for example, between the two switches of the switch control signal, and the output voltage of the switch control signal may be equal to or greater than zero, for example._OUT H.264) The feedback voltage and the reference. voltage may (12) be generated as the feedback voltage and the feedback voltage and the reference voltage, respectively, may be generated as the (V feedback voltage._REF A) comparison may be made, as compared to a reference voltage, and a feedback voltage may be compared with the (V reference voltage, for example._REF It) is possible to generate a (C _ SW) switch control signal,such as to coincide with one another, to generate a switch control signal, and accordingly, the output voltage of the switch control signal zero output from the output voltage of the switch, control signal zero (V to the output voltage of the switch control signal_OUT The reference voltage is) a reference (V voltage of the reference voltage._REF This) level may be determined by the level of zero and may be a reference voltage, of a reference voltage of the reference (V voltage Vb.448.48.4._REF Output) voltage, by changing the level of (V zero_OUT The level of) zero may be changed.

The capacitor circuit (13) may include at least one capacitor, and the at least one capacitor may include a (I capacitor current of at least one capacitor._C The) charge or discharge can be charged. or discharged by means of, for example, an inductor current of, for example, an inductor current, of less (I than or equal to zero, for example._L The capacitor current of at) least some of which is a capacitor current of._C A) capacitor current, which (I is provided as one._C The) at least (+) one capacitor of the (13) capacitor circuit may be charged if the. value is, between two, and on the other hand, at least one capacitor of the capacitor circuit may be charged, on the other hand, on the other side. Current sensor (I_C Current) flows either to (11) the ground or the (ground voltage) or the output voltage (V of the output voltage at the ground voltage or the ground potential by means of the switch circuit, by means of the switch circuit._OUT The) capacitor current flowing into the load receiving the zero (I voltage_C If the) value (-) is negative of negative (13), at least one capacitor of the capacitor circuit may be discharged, 1 . as (13) shown in FIGS (V._OUT Load) Capacitance between zero and ground (C voltages_L It) is possible to provide zeros, respectively.

Output voltage (V which is (10) generated by switching regulator_OUT The) electronic components may function as a supply voltage that provides, power to the electronic components (10), and such electronic components. may be, referred to (V as a load of the switching regulator, for example, between the two output voltages, for example, between the first and second output voltages._OUT The digital-) to-analog converter, may be provided in an analog/circuit RF for processing RF a digital signal for processing a digital signal, an analog circuit for processing an analog signal, or a step-up circuit for processing one or two signals, for example, a load capacitance of the load capacitance of the load capacitance of the first and second load capacitance of the (C. first and second load-capacitance units, respectively._L J.) .sub.n Various requirements can be determined by various. requirements, for example, in order (V to prevent a malfunction of one load, for example, to prevent malfunction of one load, for example._OUT It) may be required to have a reduced noise, and, may be (10) required to reduce ripples due (ripple) to the switching operation of the. two switching, regulator, (C and in particular, may be required to reduce ripple noise resulting from the switching operation of the first and second switching regulator units, as illustrated in FIGS._L The) output voltage V.sub. (V .sub._OUT It) may be required to have a large value in order to. reduce the, ripple of zero, on the other hand, to reduce the power consumption of one load, on the other hand, to reduce the power consumption of one load, and on the other hand, an (V output voltage (Ot.sub._OUT The level of) zero can be dynamically, changed, for (10) example, when low performance or power consumption is required at the load, for example, a low level (V of output voltage is output at the low level when low performance or power consumption is required._OUT A) high level of output voltage, may be provided when high performance or power consumption is required, on the other hand, capable of providing zeros, whereas high performance or power consumption is required on the basis (V of._OUT ,) The output voltage of the output voltage of the second output voltage may be equal to or. greater than zero and may be equal to, or greater than zero, and may be equal (V to or greater than_OUT What) is claimed Tri-load capacitance for quickly, dynamically changing (C the level_L As) will be described with reference to an exemplary. embodiment of the present disclosure, 2 as will 5 be described with reference to, an exemplary (10) embodiment, of the (C present disclosure, as described below with reference to FIGS._L An) output (V voltage having a level, that is changed rapidly, as well as having a reduced level of noise, despite the conflicting requirements for zero, as well as a rapidly changing level._OUT It) is possible to provide. zeros, respectively.

When the capacitor (13) control signal is supplied (C _ CL) to the capacitor circuit, a capacitance (C _ CL) of the capacitor is changed (C in accordance with the capacitance of the capacitor circuit, and the capacitance of the capacitor is controlled in accordance with the capacitance of the capacitor control signal._L As) a result, the. output voltage, of the output voltage output from (V the output voltage of the output voltage of the output voltage of the output voltage of the output voltage is greater (13) than or equal to zero, for example, between the output voltage and the output voltage_OUT A) relatively large load capacitance value in response to the capacitor control signal (C _ CL) zero while the level of (C zero is maintained constant._L H.264) Note that it is possible to provide an output voltage of less than or equal, to one (V-half an output voltage._OUT A) relatively low load capacitance value in response to the capacitor control signal (C _ CL) zero while the level of (C zero is changed._L ,) The output voltage of the output voltage of the second output voltage may be equal to or. greater than the output voltage of the first and second, output voltages, and may be equal (V to or greater than_OUT In) addition to having reduced noise as well as having a dynamically quickly changing. level, the capacitor (13) control signal may be referred to (C _ CL) herein as a control signal,for controlling the capacitor circuitry, as described in the present description, in the present description, and may be referred to herein as a control signal, for example.

To an 2 exemplary embodiment of the present disclosure, 1 in accordance with (10) an exemplary embodiment of the present disclosure, an, example 2 of the operation of the 1 operation of the (V switching regulator one of FIGS._OUT Double-) Load Capacitance Layer and Load Capacitance (C._L The) dotted line at the time of time is 2. shown depending on the flow of time, and the dotted line (C in FIG._L Capacitance) (C) fixed by means of a two (C-way capacitor_L0 Output) (V voltage according to the comparative example of the comparison example_OUT Double-) Load Capacitance Layer and Load Capacitance (C._L Let-), 2 1 The following will be described with reference to FIGS.

To the 2 embodiment of, the present (13) invention, the capacitor (C _ CL) control signal is supplied to 1 the (C first capacitor circuit, and the second capacitance is greater than the capacitance of the capacitor control signal, and the second capacitance is greater than the capacitance of the capacitor control signal._L1 One or a relatively low agent-) of-one-layer (C capacitance-of-two-th 2-th-th-th-layer_L2 Load Capacitance () Load-Double Sampling Latty (C._L For) example, if the. load capacitance, of the load capacitance of the load capacitance of the load capacitance of the load capacitance is less than the reference value, the load capacitance of the load capacitance of the load capacitance may be greater (C than or equal to_L Double-th 1-(C capacitance-)_L1 Double)-ty-two-th-th-Capacitance 2 Bit (C-sub._L2 A) fixed capacitance value of between (C two_L0 In) the present specification, the. capacitance may, be 1 maintained constant in a range of from about, for example, in a range of from about, for example, in a range of from about, for example, (C in the range of_L1 Double-th 2-(C capacitance-)_L2 It) is assumed that it is higher than. zero.

From a t20 time period to a, time of from a time of from a time of t21 from a time of from a time to a time ranging from a to (V time of from_OUT Pumen et) al. J. Biol. 1 Chem. J. (V Biol. Chem.₁ For) example, the output. voltage of, the second output voltage may be equal to or greater than the first output voltage, for example, between the (V first output voltage and the second output voltage, e.g._OUT Low) performance and/or power consumption/may be required under the condition, of receiving zero, and thus the output voltage may be equal to or greater than zero, and as a result, (V the output voltage may be increased._OUT P) is a relatively low agent-of-H-level-level-of-one 1-level two-level two-(V level.₁ A capacitor, and a. capacitor. (13)) In response (C _ CL) to the control 1 signal (C, the first-k-th-capacitance._L1 Load Capacitance-) Double-Double-Double-(C Double_L As) can be provided, according to one, comparative example, the load capacitance of the load capacitance (C is zero._L Double-th 1-(C capacitance-)_L1 A fixed capacitance of) less than one-(C eighth_L0 As) shown in the. above- mentioned 2 embodiment, the output, voltage having (10) a ripple which is reduced t21 than the comparison example for a period of time from a time period of from a time to a time period of from a time period of from a time to a time period of up to a period of time is set in a range of from - t20 ((V -) to (½) .sup .5.5.5._OUT The) capacitor current of the. capacitor may be generated in the first and second capacitor currents of the first and second capacitor currents of the first and the (I second capacitors_C As) the charging and discharging are repeatedly performed, the vibration may have a constant average and may be. vibrated.

From a t21 time period to a, time of from a time of from a time of t22 from a time of from a time to a time ranging from a to (V time of from_OUT Pumen et) al. J. Biol. 1 Chem. J. (V Biol. Chem.₁ Summary) of-Programming 2 ((V S.2.72.72.1.₂ It) is possible to dynamically change. to zero, for example, to have an output voltage of, for example, (V a bid.p.5.0-5.0 . for example, to_OUT High) performance and/or power consumption/may be required under the condition, of receiving zero, and thus the output voltage may be equal to or greater than zero, and as a result, (V the output voltage may be increased._OUT A) period in which the level of zero. is increased (13) may occur as a (C _ CL) period in which 2 the level of zero may be increased, and the second capacitor circuit may be in response to the capacitor control signal and may be supplied with a capacitance between the first and the second capacitance of the first and (C the second capacitors, respectively._L2 Load Capacitance-) Double-Double-Double-(C Double_L H.264) It may be provided that according to one comparative, example, the load capacitance (C (C) is._L Double-th 2-(C capacitance-)_L2 A) fixed capacitance value of greater than one-(C fourth_L0 As shown) in the. above-mentioned embodiment, the switching regulator, which 2 (10), is shown in, the above-mentioned embodiment 2, (V may be the same as that of the first embodiment, and thus, the first voltage and the second voltage may be equal to or t22 different from each other, as shown in FIGS.₂ Output) voltage having a value of zero and output voltage having (V the same_OUT The output voltage according to the second comparative) example may be generated while the output voltage may be generated, at the output voltage of the output voltage of the output (V voltage V5645050509_OUT Chem. at) a relatively delayed point of time, i.e. at a time interval of, at a time interval of at a time interval t23 of at least a level of from a 2 level of (V from a first level to a second level₂ Output) voltage having a value of zero and output voltage having (V the same_OUT It) is also possible to create zeros, and also fixed (C capacitance values of, comparisons in comparisons, as. shown in FIGS._L0 K-th-2 capacitance (C-)_L2 Bi)-capacitor current, due to zero,capacitor current I.sub. (I ._C As) can have a peak value lower than, that of the comparative (11) example, (L) the magnitude of the peak current passing through. the switch circuits and, according to which the switch circuits and the inductors A, can be reduced, and (I thus the inductor current is reduced._L As) a result of, the peak value of zero, the operating reliability of the switching, (11) (10) regulator (L) ½ can be improved,and the, size of (V the two-stage switching regulator and the number of the input/output voltages of the first and second switching regulator circuits may be reduced, and in this specification, the output voltage of the output voltage of the first output voltage may be equal to or greater than zero._OUT Pumen)-J.J.4.1 (V .4.sup.₁ Pumen et) al. J. Biol. 2 Chem. J. (V Biol. Chem.₂ J.) L. L. sup. Lower is assumed. to be low.

From a t22 time period to a, time of from a time of from a time of t24 from a time of from a time to a time ranging from a to (V time of from_OUT Pumen et) al. J. Biol. 2 Chem. J. (V Biol. Chem.₂ As) a result of the. capacitor control (13) signal, the capacitance (C _ CL) of the first capacitor circuit (C and the capacitance of the first capacitor is less than the threshold voltage of the first capacitance of the first capacitor circuit, and the second capacitance of the second capacitor is 1 less than the threshold voltage of the second capacitor._L1 Load Capacitance-) Double-Double-Double-(C Double_L Logic) Capacitance according to one, comparative example, while being able to provide for the load capacitance (C of._L Double-th 1-(C capacitance-)_L1 A fixed capacitance of) less than one-(C eighth_L0 As) shown in the. above- mentioned 2 embodiment, the output, voltage having (10) a, ripple which is reduced than the comparison example, for t22 a period t23 of time t21 t20 to the time period of from ½ time to the second time is approximately equal to or greater than the threshold (V voltage of the output voltage of the comparison example, as shown in FIGS._OUT The) capacitor current of the. capacitor may be generated in the first and second capacitor currents of the first and second capacitor currents of the first and the (I second capacitors_C As) the charging and discharging are repeatedly performed, the vibration may have a constant average and may be. vibrated.

From a t24 time period to a, time of from a time of from a time of t25 from a time of from a time to a time ranging from a to (V time of from_OUT Pumen et) al. J. Biol. 2 Chem. J. (V Biol. Chem.₂ Summary) of-Programming 1 ((V S.2.72.72.1.₁ It) is possible to dynamically change. to zero, for example, to have an output voltage of, for example, (V a bid.p.5.0-5.0 . for example, to_OUT H.264) The load that it receives may/be low performance and/or power consumption, and thus, the output voltage may (V be zero._OUT A) period in which the level of zero. is reduced (13) may occur as a (C _ CL) period in which 2 a level of zero may be generated, and the capacitor circuit may be operated in response to the capacitor control signal, and may be supplied in response to the output of the first capacitance of the first and the second capacitance of the (C first and the second capacitance of the first and second_L2 Load Capacitance-) Double-Double-Double-(C Double_L As) can be provided, according to one, comparative example, the load capacitance of the load capacitance (C is zero._L Double-th 2-(C capacitance-)_L2 A) fixed capacitance value of greater than one-(C fourth_L0 As shown) in the. above-mentioned embodiment, the switching regulator, which 2 (10), is shown in, the above-mentioned embodiment 2, (V may be the same as that of the first embodiment, and thus, the first voltage and the second voltage may be equal to or t25 different from each other, as shown in FIGS.₂ Output) voltage having a value of zero and output voltage having (V the same_OUT The output voltage according to the second comparative) example may be generated while the output voltage may be generated, at the output voltage of the output voltage of the output (V voltage V5645050509_OUT Chem. at) a relatively delayed point of time, i.e. at a time interval of, at a time interval of at a time interval t26 of at least a level of from a 2 level of (V from a first level to a second level₂ Output) voltage having a value of zero and output voltage having (V the same_OUT Technolor may be generated in) a number of levels equal to or greater than. zero.

Technola at a voltage level of t25 from a time of, from a time of from a day to (V a value of_OUT Pumen et) al. J. Biol. 1 Chem. J. (V Biol. Chem.₁ Tri)-capacitor capable of being maintained at. zero-level In response (13) to the capacitor control (C _ CL) signal one, 1 the (C second capacitance of the first capacitance is greater than the first capacitance of the first capacitance of the first capacitance of the first capacitance of the first capacitance of the first capacitor_L1 Load Capacitance-) Double-Double-Double-(C Double_L Logic) Capacitance according to one, comparative example, while being able to provide for the load capacitance (C of._L C) is a fixed capacitance less than that of the (1 O) th set of Electrical and Electronics (LUTOMER) of lower than that (C of the_L0 For) example, the. output voltage, of t20 the output t21 voltage of the, output voltage (10) of the t25 output voltage having a ripple that is (V less than the comparison example in the comparison example from the time of the time interval between the first voltage and the second voltage may be applied to the output voltage of the output voltage of the output voltage of the second output voltage._OUT The) capacitor current of the. capacitor may be generated in the first and second capacitor currents of the first and second capacitor currents of the first and the (I second capacitors_C As) the charging and discharging are repeatedly performed, the vibration may have a constant average and may be. vibrated.

The output voltage is shown 2 in the example of FIG. 4, even though the output voltage is (V zero._OUT One of 2 the two different levels, one of 1 the (V two different levels, namely, the level of the th-level one-level two-level-)₁ Sheet al.), J. Biol. Chem. 2 (V J. Biol. Chem.₂ Although illustrated as having zero), in some embodiments, the output voltage may be equal to or, greater than zero in some embodiments; however, in some embodiments, the output voltage may (V be zero._OUT Bias) may 3 have one of two or more different levels,and, in 2 an example of also in the illustration of the example, the load capacitance of the load capacitance of the load capacitance of the load capacitance may be greater than or equal to zero, and may be greater than or equal to zero and less (C than or equal to zero._L The) (C capacitance of at least one of the, 2 two 1 different capacitances of the first and the second capacitances of the first and the second capacitances of the first and the second capacitances of the first and the second capacitances of the first and the second capacitances of the first and second_L1 Double-) Volume Logic Let al. 2 Double Capacitance (C, Vol._L2 H.264) Although illustrated as having having one of the two (13), 3 or more different values in some embodiments, the capacitor circuit may have one of two or more different values in some embodiments, but in some embodiments, the capacitor circuit may have (C one of two or more different values._L The output voltage of) the output voltage of the output voltage of the output voltage of (V the output_OUT It) is also possible to provide according to a level of. zero.

The exemplary 3a embodiments of 3c the switching regulator according to exemplary embodiments of the present disclosure . are 3a shown in 3c the DC-DC following description, of (buck) the (30a), exemplary (boost) embodiments (30b) of the - present (buck-boost) disclosure (30c), and. the, description 3a of the 3 exemplary embodiments of the switching regulator according to. exemplary embodiments of the present disclosure may be omitted from the description of the exemplary embodiments, but is not limited thereto.

With reference to the input, voltage level 3a of the input voltage of the buck converter, the buck converter may include an (V input voltage (30a) of at least one of the input voltage and the input voltage._IN A level of) output voltage at a level lower than the level of (V zero_OUT As shown in any of, the - above (step-down)-mentioned embodiments,the 3a first and second buck, converters may (30a) include an (L), inductor, (31a), a first switch, a second switch, and a third (32a) switch (33a), respectively. (32a)) (V_REF Output voltage of both) of the output voltage and output voltage output from the output voltage (V supply unit_OUT A) switch control signal with a (C _ SW) switch control signal as a switch control signal, and a switch control signal according to an, embodiment of the present invention Note that (31a) it is possible to. provide the circuit a with the output voltage output from the output voltage of the first output voltage Vinv and the second (V power supply voltage_OUT A) reference voltage as a reference voltage for changing a level of (V zero_REF In) the case where the level of the (32a) reference voltage is changed, the, two switch controllers' b ' may be changed to a reference voltage of a changed (V level, respectively._REF Output voltage of both) of the output voltage and output voltage output from the output voltage (V supply unit_OUT On the basis of the level of (C _ SW) the input voltage,the switch (31a) control signal may be generated, (V and the switch control signal may be input to the input voltage of the switch circuit)_IN In) some embodiments, the two switches 2 may include two switches that. are connected, in series (31a) between the first and (C _ SW) the ground 2 voltages, and in some embodiments,the first (33a) and second switch circuits (C _ CL) may mutually exclusively turn on (C the two switches in response to the switch control signal, and in some embodiments, the switch control signal may be switched on or off by the switch control signal._L D.7.sup),3 output voltage (V_OUT It) is possible to provide between zero and ground voltages.

To the reference example, the voltage (30b) level 3b of the input voltage is greater than the input voltage of the input voltage output from the input voltage of the input voltage of the (V input voltage of the boost converter_IN A level of) output voltage at a level higher than the level of (V zero_OUT This may create zero) and may be referred to as a two,step power-up - two-(step-up) up two-to-one converter. As shown 3b. in the above-described embodiment, the (30b) second boost (L), converter may (31b), include an (32b) inductor, a (33b) switch circuit, a second switch, (32b) a first switch (V, a second switch, a second switch, a second switch, a second switch, a second switch, and. a second switch, respectively, as shown in FIGS._REF Output voltage of both) of the output voltage and output voltage output from the output voltage (V supply unit_OUT Based) on the output of the (C _ SW) switch control signal, the switch (31b) control signal may be. generated and (V may be provided to the tri-state output voltage of the switch control signal output from the input/output terminal of the switch control signal output from the output terminal of the switch control signal output terminal of the switch control signal._OUT A) reference voltage as a reference voltage for changing a level of (V zero_REF In) the case where the level of the (32b) reference voltage is changed, the, two switch controllers' b ' may be changed to a reference voltage of a changed (V level, respectively._REF Output voltage of both) of the output voltage and output voltage output from the output voltage (V supply unit_OUT The switch control signal is generated based (C _ SW) on the level of. the output (31b) voltage of the switch control (L) signal, and (V the output voltage of the output voltage is output from the output voltage of the)_OUT In) some embodiments, the two switches 2 may include two switches electrically. coupled to, the first (31b) and second ground voltages (C _ SW), respectively 2, and in some embodiments, the. first and (33b) second switch circuits may (C _ CL) be configured to mutually exclusively (C turn on the two switches in response to the switch control signal, and in some embodiments, the switch control signal may be switched on or off by the first and second switch circuits._L Out-) of-of-one,zeros output Voltage doubler (V_OUT It) is possible to provide between zero and ground voltages.

To the reference example, the Buck 3c-Buck(30c)-to,Boost converter, and the input voltage - respectively, are input to the input voltage of the input voltage of the input voltage (V of the buck-boost converter_IN A level of) output voltage at a level lower than the level of (V zero_OUT Zero) or high level of output (V voltage_OUT The) output voltage may be, generated (L), at the (31c), output voltage (32c) of the output (33c) voltage of the output. voltage of (32c) the output voltage (V of the first and second switch controllers, and may be equal to or greater than the output voltage of the output voltage of the first and second switch controllers, respectively, and may be equal to or greater than the output voltage of the first and second switch controllers, and may be different from each other._OUT In) response to the level - of the (30c) buck converter 3a control signal, (30a) the buck converter control signal may be generated, for example, in 3b the Buck-to-(30b) Buck converter with, the Buck-(V Buck-(C _ SW) of-Buck-of-Boost-of,D.sub.sub.sub.sub._OUT An input voltage at) a level of (V zero_IN When) the level of the, switch control (32c) signal is lower (31c) than the lower level, the switch control (30c) signal may be generated to have a structure such - as the Buck-to-3a Buck converter. with the, Buck (30a)-Buck-Buck-of-Boost to the Buck-(C _ SW) Buck-of-B. The Buck-Buck-Boost mode of the switch control signal is not greater than unity. Voltage doubler (V_OUT An input voltage at) a level of (V zero_IN When) the level of the, switch control (32c) signal is higher (31c) than the level of the - second switch (30c), the switch control signal may be generated to have a structure, such (C _ SW) as the 3b Buck-to,Buck(32c) (30b)-of the Buck-Buck-of-Boost, by the switches included in the switch circuit . and the Buck-Buck-(V to-Boost converter of the switch control signal (Buck-Boost)._REF Output voltage of both) of the output voltage and output voltage output from the output voltage (V supply unit_OUT Based on the) basis of the switch control signal, (C _ SW) the switch control signal may be. generated.

Input voltage is input to the input voltage of the (31c) input voltage of the input voltage of the input voltage of (V the switch circuit_IN The) two switches that are connected in 2 series between the two and, the (L) ground voltage, and may output the output voltage between the output voltage and the output voltage from the output voltage of the output voltage of the first and the second inductors of the first and the second inductors of the first and the second inductors of the first (V and the second inductors_OUT The two) switches, which are electrically 2 connected to the ground voltage . respectively (33c), may include two (C _ CL) switches, each of which (C is variable in accordance with a capacitor control signal of the capacitor control signal, and may be a load capacitance that is varied in accordance with the capacitor control signal._L D.7.sup),3 output voltage (V_OUT H.264) A ground voltage may be provided between the ground voltage and ground voltage.

In accordance 4 with an exemplary embodiment of the present 1 disclosure, a (13) circuit diagram illustrating an. example 1 of the capacitor circuit example, of 4 the present disclosure (40) is a circuit diagram (C _ CL) of the capacitor circuit example (C of the present disclosure, as described above with reference to FIGS._L D.7.sup),3 output voltage (V_OUT As shown in the above-described embodiment . 4 the first capacitor may, be connected (40) in parallel to the first 1 and (C1)/or 1 second (C1) capacitors of the first and second capacitors and may be connected in parallel (41) to the first . and/4 1 or 2 the second and. or the second and/or the second and the second and/or the second and/or non-inverting input/output terminals.)

In some embodiments (41) of the present invention, the variable capacitor may include (SW) a plurality of series, 2 (SW)-connected (C2) electrically (C _ CL)-coupled capacitors / the first. and second, capacitors (SW), the first (V and second capacitors, the first and second capacitors, the first and the second capacitors, respectively, and the first and the second capacitors, respectively, in the first and second embodiments of the present invention, respectively, in the first and second embodiments of the present invention._OUT While it is) maintained at a constant level while maintaining a constant, level, it is possible to maintain an on state, while maintaining a zero output (V voltage (OD.sub.)_OUT When) the level of zero is changed while the level. of (SW) zero can be, kept 1 off (C1) while the 2 level (C2) of zero is turned on, the first (40) and second 1 capacitors (C1) O and the first 2 and (C2) the second capacitors, respectively, (C may be electrically connected in parallel, respectively, and the capacitance of the first and second capacitors and the capacitance of the first and second capacitors of the first and second capacitors may be equal to or greater than the capacitance of the first and second capacitors of the first and second capacitors, respectively, respectively._L On) the other hand,when the, one (SW) hand is turned, off while (40) on the 1 other (C1) hand, on the other (C hand, the capacitance of the first capacitor is less than the capacitance of the first capacitor of the first capacitor, and the capacitance of the second capacitor is greater than the capacitance of the first capacitance of the first capacitor circuit of the second capacitor circuit, for example._L As) described above with reference. to a, second 2 embodiment, 2 for example, as described (40) above with reference to FIGS, 1 (C._L1 Double-) Volume Logic Let al. 2 Double Capacitance (C, Vol._L2 In the case where it is, possible 1 to (C1) provide zeros 2, (C the zeroth-th-th-th-stage capacitance of the first-to-third-th-th-field-)_L2 It) is possible to have a capacitance of between the first and the 1 second (C capacitors of the first and the second, capacitors of the first and 2 second capacitors of the first and (C2) the second capacitors of the first and second capacitors of the first and the second capacitors, respectively._L1 Double)-ty-two-th-th-Capacitance 2 Bit (C-sub._L2 A) difference in the above-described values of - (S-(C A)_L1 - C_L2 It) is possible to have a capacitance corresponding to zero, for example.

In some embodiments, the, capacitor control signal is (40) supplied to the capacitor control signal (C _ CL), in some embodiments. Responsive to one-th-third,th-capacitance 1 three-th-th (C-q._L1 Pitty)-th Capacitance from Domain-2-of-(C J. Biol._L2 Load Capacitance () Load-Double Sampling Latty (C._L It is possible (rapidly) to steadily change the, two 2-(C th-layer capacitance-)_L2 Pitty)-th Capacitance from Domain-1-of-(C J. Biol._L1 Load Capacitance () Load-Double Sampling Latty (C._L The output voltage (gradually) of the output. voltage, of the (40) output voltage is equal to or greater (V than the output voltage of the output voltage of the first and second capacitors)_OUT Load Capacitance at) the point at which the level of zero starts (C to change._L It) is possible to reduce power steadily, while on the other hand, output voltage of zero,output voltage (V (OD.I.72.72.72.2_OUT Load Capacitance at) the time when the (C change of the level of zero is completed._L As) a result, the output. voltage of, the output voltage of the output voltage of the second output voltage may be increased, and the output voltage of the second output voltage may be equal to or (V greater than zero._OUT Not only can the) level of zero can be changed rapidly, as well as a load capacitance of less than or, equal (C to zero load capacitance._L Output) voltage, which may occur due to the increase in power back to (V zero_OUT For) this purpose, in at. least some, embodiments of the present (41) invention, in (SW) some embodiments of the (C _ CL) present invention, in some embodiments, the switching element included in the variable capacitor is turned on and turned on in response to the capacitor control signal, and in some embodiments, is turned on and turned on in some embodiments. The exemplary embodiments of the variable capacitor three - which may operate differently at each of the (41) 6c turn-on 6a. and turn-off operations, will be described later with reference to FIGS.

To an 5 exemplary embodiment of the present disclosure, 1 in accordance with (10) an exemplary embodiment of the present disclosure,the example 5 of the operation of the operation of 1 (10) 4 (13) the (40) switching regulator as shown in FIGS (V._OUT Load Capacitance), Capacitance Bit Litty (C._L An), on 4-resistance of the switching element (SW) of at (R least one of FIGS._ON Capacitor) current and capacitor current, and capacitor current, and capacitor current of (I the same_C Load) capacitance, as described above. with 4 reference to a flow of, time 5, as described above (C with reference to the time of time, as described above, in the example of FIGS._L It is) to be described with reference, to FIGS. and. or 5, and 1 the content 4 overlapping with the description, of 5 any of the explanations in 2 the description with respect to the description. thereof, will be omitted, and will be omitted.

From a t50 time period to a, time of from a time of from a time of t51 from a time of from a time to a time ranging from a to (V time of from_OUT Pumen et) al. J. Biol. 1 Chem. J. (V Biol. Chem.₁ H.264) As a result, in response (40) to the capacitor control (C _ CL) signal, the 1 capacitor (C control signal is supplied to the first capacitor circuit, and the second capacitance is less than the threshold voltage of the first capacitance of the first capacitor circuit._L1 Load Capacitance-) Double-Double-Double-(C Double_L It) is possible to provide. a 2 capacitance (C2) of the capacitance of the capacitor of the capacitor of the load capacitance of the load capacitance of the load capacitance of the load capacitance of the capacitor of the load capacitance of the capacitance (C of the capacitance of the capacitor_L In) order to provide as part of (SW) a reference, the tri,state switch may be in an on-state, and a relatively low, low-output-value-value-of-two 1-(R th-value-value two.₁ It) will be understood that in some embodiments, 1 the (R first and second resistances of the first and second. resistances of the first and second resistances of the first and second embodiments may be equal to or different from each other, and may be₁ Technically), as described (zero) above with reference to. a 2 degree of approximation, zero, may be approximately 1 zero (C (approximately zero), as described above with reference to FIGS._L1 Output) voltage due to (V zero_OUT Fripples can be reduced at) zero, for example. U.S. Pat.

From a t51 time period to a, time of from a time of from a time of t52 from a time of from a time to a time ranging from a to (V time of from_OUT Pumen et) al. J. Biol. 1 Chem. J. (V Biol. Chem.₁ Summary) of-Programming 2 ((V S.2.72.72.1.₂ As) can be dynamically changed to. zero, (40) the load capacitance of (C _ CL) the first, capacitor t51 circuit may be (C changed to zero in response to the capacitor control signal, and the load capacitance of the second capacitor circuit may be equal to or greater than the load capacitance of the second capacitor circuit._L Double)-th Capacitance Layer-ty-eighth-1 Charging capacitance-(C of._L1 Pitty)-th Capacitance from Domain-2-of-(C J. Biol._L2 The load capacitance is) steadily changed to zero t52 and loaded with a load capacitance value, at a time of up to a period of time of (C from about ½ time_L H.264) K 2-(C th-capacitance_L2 As) a result, it. is t51 possible, to 2 maintain (C2) the capacitance between the capacitance of the first and the second capacitors in the load capacitance of the load capacitance of the load capacitance of the first and the second capacitors of the load capacitance of the first and the second capacitors, respectively (C, at a time of at least_L In) order to exclude, from (SW) one another, the first and, second switches may be switched to an off (SW) state, and (R the on-resistance of the 5 one-to-one switch of the first and second switches may be switched to the, OFF state, as shown in FIGS._ON Jet al.), J. Biol. J. Biol. 1 Chem. (R J. Biol.₁ A relatively high (O 2-(R .0-)₂ It) can be steadily changed to zero and the kth-th-th-value-value-value range of up to a t52 period of up to a period of 2 time (up-(R to-D.72.2)₂ For) example, in some. embodiments, the first 2 and second resistances of the first and second resistances of the first and second resistances of the first and, second resistances of the first and second embodiments may be maintained in (R a range of from about₂ It) may be. approximately infinitely infinite, and, as 2 described above with reference to, FIGS 2 (C._L2 Output) voltage due to (V zero_OUT At) an earliest point of time, for example, in the period of time, the first,level zero-t52 level zero-level two-level zero-2 level-zero-level (V zero-level.₂ The) output voltage, which. may 5 have zero, may, have t51 a value t52 of zero and an output (V voltage of greater than or equal to a period of time, as shown by a reference example, between the output voltage and, the output voltage, as shown in FIGS._OUT A) capacitor current for charge of a capacitor circuit (40) (IC) due to a level (I of zero_C A) secondary capacitor may be provided in the capacitor CONTRON561, (40) wherein the capacitor circuit may be provided in the. capacitor Camb.

Output voltage at a time-t52 of-of- zero at a time-of-one (V-eighth_OUT Pumen et) al. J. Biol. 2 Chem. J. (V Biol. Chem.₂ In) response to the capacitor, control signal (40), the load capacitance (C _ CL) of the capacitor circuit (C is determined to be greater than or equal to the capacitance of the capacitor control signal, and the capacitor control signal is supplied to the load capacitance of the load capacitance of the capacitor._L Double)-th Capacitance Layer-ty-eighth-2 Charging capacitance-(C of._L2 Pitty)-th Capacitance from Domain-1-of-(C J. Biol._L1 H.264) It may begin to change gradually . and the first capacitor circuit (40) (the (C second capacitor circuitry) may start changing gradually._L Double)-th-th-th-1 Capacitum-(C Literal Capacitance_L1 Load) capacitance, up t53 to a time point at which the load capacitance is (C reached zero._L It is possible to incrementally alter. the zero 5, even t52 if there is no load capacitance t53 from the time (C of the load capacitance of less than or equal to)_L Although it is shown) to increase linearly, in some embodiments a load (C capacitance of, less than or equal to zero may be used in some embodiments._L The ratio) may be non-linearly increased from a t52 period of time to a time of from t53 a period of time to a period. of time (also referred to as a 'time').

Load capacitance (C_L Double)-th Capacitance Layer-ty-eighth-2 Charging capacitance-(C of._L2 Pitty)-th Capacitance from Domain-2-of-(C J. Biol._L1 In) order to gradually change, the (SW)ON-state from the off state to the, ON state in order to gradually change from the OFF state to the ON state, the on-state resistance of the two-way switching element can be changed from the OFF state to the ON state, i.e. on the on-state current ((R on-resistance ratio of_ON Jet al.), J. Biol. J. Biol. 2 Chem. (R J. Biol.₂ O)-th resistance value of the (O-O) - (O-1 O) - (O (R-O)₁ It) is also possible to gradually change to zero, and also to a capacitance of less than or equal to. zero and less than or equal, to zero and less than or 2 equal to zero and (C less than or equal to_L2 Pitty)-th Capacitance from Domain-1-of-(C J. Biol._L1 Incrementally increasing load capacitance value-(C of-of-eighth-of-)_L Jet al.), J. Biol. Chem. 1 J. (V, J. Biol.₁ Level)-elevating agent-of-2 J.(V .2.72.72.72.5.₂ Output) voltage of (V zero_OUT A capacitor current, for charge (40) of a variable (41) capacitor one of the capacitor circuit of the (I capacitor circuit of the capacitor)_C Billard) In some embodiments, at. least some embodiments may occur, and in some embodiments, as, 5 (I, shown in FIGS._C A is a t52 certain magnitude t53 of from a (I time period of from a time of from)_CHG The) number of bits may be equal to or greater than one and equal to or greater than. unity.

From a t53 time period to a, time of from a time of from a time of t54 from a time of from a time to a time ranging from a to (V time of from_OUT Pumen et) al. J. Biol. 2 Chem. J. (V Biol. Chem.₂ As) a result of the. capacitor control (40) signal, the capacitance (C _ CL) of the first capacitor circuit (C and the capacitance of the first capacitor is less than the threshold voltage of the first capacitance of the first capacitor circuit, and the second capacitance of the second capacitor is 2 less than the threshold voltage of the second capacitor._L2 Load Capacitance-) Double-Double-Double-(C Double_L It) is possible to provide. a 2 capacitance (C2) of the capacitance of the capacitor of the capacitor of the load capacitance of the load capacitance of the load capacitance of the load capacitance of the capacitor of the load capacitance of the capacitance (C of the capacitance of the capacitor_L In) order to provide as part of (SW) a reference, the tri,state switch may be in an on-state, and a relatively low, low-output-value-value-of-two 1-(R th-value-value two.₁ For) example, a relatively. high t50-k dielectric layer may be, formed between the first and second dielectric layers of the first and second dielectric layers of the first and second dielectric layers of the first and second dielectric layers of the first and second dielectric layers, respectively, in the range of t51 from about ½, 1 and from about (C (½) to about ¼._L1 Output) voltage due to (V zero_OUT Fripples can be reduced at) zero, for example. U.S. Pat.

From a t54 time period to a, time of from a time of from a time of t55 from a time of from a time to a time ranging from a to (V time of from_OUT Pumen et) al. J. Biol. 2 Chem. J. (V Biol. Chem.₂ Summary) of-Programming 1 ((V S.2.72.72.1.₁ As) can be dynamically changed to. zero, (40) the load capacitance of (C _ CL) the first, capacitor t54 circuit may be (C changed to zero in response to the capacitor control signal, and the load capacitance of the second capacitor circuit may be equal to or greater than the load capacitance of the second capacitor circuit._L Double)-th Capacitance Layer-ty-eighth-1 Charging capacitance-(C of._L1 Pitty)-th Capacitance from Domain-2-of-(C J. Biol._L2 The load capacitance is) steadily changed to zero t55 and loaded with a load capacitance value, at a time of up to a period of time of (C from about ½ time_L H.264) K 2-(C th-capacitance_L2 As) a result, the on-t54 resistance of the on-resistance of (R the switching element between the on.state current and the on-state current of, the one-to (SW)-one-half of the ON resistance of the switching element is at a level of_ON Jet al.), J. Biol. J. Biol. 1 Chem. (R J. Biol.₁ O)-th resistance value of the (O-O) - (O-2 O) - (O (R-O)₂ It) can be steadily changed to zero and the kth-th-th-value-value-value range of up to a t55 period of up to a period of 2 time (up-(R to-D.72.2)₂ It can be maintained at. zero, and thus a 2 relatively (C low K-th-capacitance-of-eighth-capacitance-)_L2 Output) voltage due to (V zero_OUT At) an earliest point of time, for example, in the period of time, the first,level zero-t55 level zero-level two-level zero-1 level-zero-level (V zero-level.₁ The) output voltage, which may have zero, may have zero, and t55 a reduced t52 output, voltage of up (V to a period of time from zero to a period of time, as 5. shown by a reference example, may also be greater than or equal to zero, and may be equal to or greater than zero and equal to or greater than zero and equal to or greater than zero._OUT A) capacitor current for discharging capacitor circuit (40) zero due to a level (I of zero_C A) secondary capacitor may be provided in the capacitor CONTRON561, (40) wherein the capacitor circuit may be provided in the. capacitor Camb.

Output voltage at a time-t55 of-of- zero at a time-of-one (V-eighth_OUT Pumen et) al. J. Biol. 1 Chem. J. (V Biol. Chem.₁ In) response to the capacitor, control signal (40), the load capacitance (C _ CL) of the capacitor circuit (C is determined to be greater than or equal to the capacitance of the capacitor control signal, and the capacitor control signal is supplied to the load capacitance of the load capacitance of the capacitor._L Double)-th Capacitance Layer-ty-eighth-2 Charging capacitance-(C of._L2 Pitty)-th Capacitance from Domain-1-of-(C J. Biol._L1 It) is possible to start to gradually. change to (40) zero, and (C a load capacitance of less than or equal to zero may be used as the load capacitance of the load capacitance of the load capacitance of the load capacitance of the first and second capacitor circuits_L Double)-th-th-th-1 Capacitum-(C Literal Capacitance_L1 Load) capacitance, up t53 to a time point at which the load capacitance is (C reached zero._L It) is possible to incrementally alter. one of (C the load capacitance values of the first and second load capacitance of the first and second load capacitance of the first and second load_L Technol.) Chem. In some embodiments, at least some of the In embodiments, the linear increase, may increase linearly and may increase. non (SW)-linearly (R in some embodiments and may increase non-linearly in some embodiments._ON Jet al.), J. Biol. J. Biol. 2 Chem. (R J. Biol.₂ O)-th resistance value of the (O-O) - (O-1 O) - (O (R-O)₁ It) is also possible to gradually change to zero, and also to a capacitance of less than or equal to. zero and less than or equal, to zero and less than or 2 equal to zero and (C less than or equal to_L2 Pitty)-th Capacitance from Domain-1-of-(C J. Biol._L1 Incrementally increasing load capacitance value-(C of-of-eighth-of-)_L Jet al.), J. Biol. Chem. 2 J. (V, J. Biol.₂ Level-) lowering agent-of-one 1-level (V two-level₁ Output) voltage of (V zero_OUT A capacitor current, for discharging (40) a variable capacitor (41) one of a parasitic capacitance of the capacitor (I circuit of the capacitor of the capacitor)_C In) some embodiments of the. present invention, 5 in some embodiments, the capacitor current of the capacitor may occur, and in some embodiments, the capacitor current of the capacitor may be equal to or greater than zero and may be equal to or greater than zero, in some example embodiments (I, and may be greater than_C A is a t55 certain magnitude t56 of from a (I time period of from a time of from)_DIS The) number of bits may be equal to or greater than one and equal to or greater than. unity.

Technola at a voltage level of t56 from a time of, from a time of from a day to (V a value of_OUT Pumen et) al. J. Biol. 1 Chem. J. (V Biol. Chem.₁ As) a result of the. capacitor control (40) signal, the capacitance (C _ CL) of the first capacitor circuit (C and the capacitance of the first capacitor is less than the threshold voltage of the first capacitance of the first capacitor circuit, and the second capacitance of the second capacitor is 1 less than the threshold voltage of the second capacitor._L1 Load Capacitance-) Double-Double-Double-(C Double_L The) power supply can be provided as a regulator, and a switching regulator, controlled by a switching regulator controlled by (10) the output of the output of the switching regulator. Output voltage (V having high output voltage_OUT Technolor may be generated in) a number of levels equal to or greater than. zero.

Also, 6a as described 6c above with reference to the exemplary embodiments of the present disclosure . 4 as described above with reference, to 6a the exemplary 6c embodiments of the (60a, 60b, 60c) present disclosure, as (C _ CL) described above, a capacitance of the. variable, capacitors 5 may be varied in accordance, with a, capacitor 6a control signal 6c, as described (60a, 60b, 60c) above, with 2 reference (C2) to FIGS (C._L Nominally excludes from zero) and 2 the (C2) capacitance of each of the first and second capacitors is a load capacitance of less than a load capacitance of the load capacitance of the load capacitance of the load capacitance of the load capacitance of the load capacitance of the first (C and second capacitors_L It) is possible to operate in response to a, two capacitor control signal, (C _ CL) which is added incrementally to zero, to be added. incrementally to zero.

To the 6a exemplary embodiment, of the (60a) present invention 2, (C2), the (CS1), SPDT(Single Pole Double Throw) variable (SW1) capacitor may 1 include (T1) a first current source . 1 a (T1) second NMOS current source 2, (C2) a first current, source, a second current SPDT source (SW1), a second current source, a (CS1) second current (I source, a second current source, a first current source, a second current source, a second current source, a second current source, and a second current source, respectively, in the first and second embodiments of the present invention, respectively._G For) example, the control, SPDT signal (SW1) may be supplied to (C _ CL) the gate of 1 the (T1) first transistor, (CS1) and the other of the first and. second transistors may be connected to the first and/or second output terminals of the first and second transistors of the first and second transistors, respectively, and may be connected to the first and the second output terminals of the first and second transistors of the first and the second embodiments.

Reduced load capacitance three-dimensional (C_L A capacitance of) (, for example, in the form, of, for example 2, O (C/O (O/O) ._L2 H.264)) For example, in (SW1) response, to a high- SPDT level (C _ CL) capacitor control signal 1, (T1) for example, the gate of the. first and, second 1 transistors (T1) may be - connected to a, ground 2 node (C2) in response to a (C high-level capacitor control signal, for example, in response to a high-level capacitor control signal, e.g. a high-level capacitor control signal may be applied to the ground node, and the capacitance of the first and second capacitors may be equal to or greater than the load capacitance of the first and second capacitors._L On) the other hand, an. increased load, capacitance can be dispensed with, on the other hand, from (C zero on the other hand._L A capacitance of) (, for example, in the form, of, for example 1, O (C/O (O/O) ._L1 For)) the sake, SPDT of (SW1) convenience, of description, for example, (C _ CL) in response to 1 a (T1) low-level (CS1) capacitor control signal, for example, a (I gate of a transistor of the transistor is connected to a current source of the transistor, for. example, in response to a low-level capacitor control signal, for example._G As) a result, 1 the (T1) gate voltage of the first and, second 1 transistors (T1) may be - increased due to the decrease of. the, gate 2 voltage (C2) of the first and second (C transistors, and the resistance value between the source and the drain of the first and second transistors may be reduced, and consequently, the capacitance of the first and second capacitors may be gradually reduced to the load capacitance of the first and second transistors of the first and second transistors of the first and second transistors, respectively._L The rate at) which the. capacitance of the variable capacitor (C _ CL) is increased in response (60a) to the capacitor control, signal (CS1) of the low level, which may be added to the second low level, may be greater than the capacitance of the variable capacitor one, and the rate at which the capacitance of the variable capacitor Cx is increased may be equal to or smaller than the threshold current of the variable capacitance of the first and second current It may be determined 1 by (T1) the parasitic capacitance that is present in the gate of the current, and N-th-1 th (T1)-th- th-transistor, and in some embodiments (60a), the dual-capacitor may further include a capacitor connected between the gate and the ground node of the N-th-th-th- th-transistor nineteenth-eighth-ninth embodiments.

For 6b example, the reference (60b) current of 2 the (C2), source (CS2) and the drain (T2 of T4) each of the first. and 2 the (T2) second transistors may be equal to or greater than the reference current 2 of the first (C2) and, the 3 second capacitors, (T3) (T4) 4 and may be between (CS2) the. source and the drain of the first and/or the second and third and third (I and third and third and fourth and third and third and fourth and third and fourth and third and third and third and fourth and third and third and fourth and third and third and fourth and third and third and fourth and third embodiments._REF While it is possible to, generate 4 zero (T4) and the - tri-OR 3 gate (T3) is turned 2 on (T2), the voltage (current mirror) of the current flowing through the drain and the source of the (. th 2- th-(T2) th-(I to-th-transistor) may be equal to or greater than zero.)_X Reference current Iref), reference current Iref, and reference current (I Iref_REF It may be 3 determined (T3) by the 2 ratio (T2) of the size ratio of the first and the (+) - th and the (-) - th-th-field-effect transistor and the (-)-th-th-th-field-effect)

Reduced load capacitance three-dimensional (C_L A capacitance of) (, for example, in the form, of, for example 2, O (C/O (O/O) ._L2 H.264)) In order, to 4 apply (T4) a ground voltage to the gates (C _ CL) of the first 2 and (T2) second transistors of the first and second. transistors in, response 2 to (T2) the high -level capacitor, control 2 signal (C2), the first and (C the second transistors may be turned on or off, respectively, and the capacitance of the first and second capacitors may be equal to or greater than the load capacitance of the first and second transistors of the first and second transistors of the first and second transistors of the first and second transistors, respectively._L On) the other hand, an. increased load, capacitance can be dispensed with, on the other hand, from (C zero on the other hand._L A capacitance of) (, for example, in the form, of, for example 1, O (C/O (O/O) ._L1 For)) the sake, of 4 convenience (T4) of description, the gate voltages (C _ CL) of the first - and second transistors. of the, first 2 and (T2) second transistors 3 may (T3) be gradually increased in response to the, low-level capacitor control signal (I, and thus the gate voltage of the first and second transistors may be increased gradually, and the current is supplied to the first and second capacitors of the first 2 and (C2) second capacitors, respectively, from the first and the second-to-third and third capacitors, respectively._X As) a result of the fetching (C2) of zero, the capacitance of the first and the second 2 capacitors is gradually reduced to the load capacitance of the load capacitance of the first and the second capacitors of the first (C and second capacitors._L Intra) prediction can be added to. H.263

For example 6c, the, variable resistance (60c) of the first variable capacitor 2 may (C2) be equal to (VR) or greater than the. capacitance of (VR) the first and second (C _ CL) capacitors, and 2 may (C2) be equal to or greater than the capacitance of. the first, and second capacitors (C, and may be equal to or greater than the capacitance of the first and second capacitors, respectively, and may be equal to or greater than one._L A capacitance of) (, for example, in the form, of, for example 2, O (C/O (O/O) ._L2 H.264)) In order to be (VR) able to provide a (relatively, high resistance) value, for example, a relatively high resistance value, for example, a relatively high resistance value, for example, an increased load capacitance of less than (C or equal to zero is provided._L A capacitance of) (, for example, in the form, of, for example 1, O (C/O (O/O) ._L1 For)) the sake of limitation (VR), the variable resistance (of, the variable) resistance, for example, can provide a relatively low resistance value, for example, zero, to provide a zero-approximation (zero-zero.) zero (zero-zero).

In some embodiments, the, variable resistance of the load capacitance (VR) is reduced by a steadily decreasing load capacitance (C of._L To) provide a resistance value that (C _ CL) is steadily increased in response to a capacitor control, signal, for example, in response to a capacitor control signal, while a gradually (C increasing load capacitance value may be achieved._L For) example, a resistance value gradually decreasing in. order to, provide a (VR) resistance, value that is gradually decreasing NMOS is provided, for example, between the first, and second capacitors, 2 and (C2) the plurality of sub-circuits may include a plurality of sub-circuits, respectively, and the plurality of sub-circuits may include at least one of the first and the second capacitors, the first and the second capacitors, respectively. The two capacitor control signals, which may. be connected in (C _ CL) parallel between the nodes, may include a plurality of bits. that are respectively (C _ CL) provided, to the plurality of sub-circuits, so that all the bits may, be steadily changed to have a low level for a resistance value that is. steadily increased, while all the bits may be changed sequentially until all the bits have a high level, respectively.

A block diagram of 7 a power supply circuit according to (70) an exemplary embodiment. of 7 the present disclosure is, a block (70) diagram illustrating a (V power supply circuit according to an exemplary embodiment of the present disclosure; FIGS._IN Output voltage from) zero to output (V voltage_OUT A) reference voltage may be, generated and may be received from a reference voltage between the first reference voltage and the second reference voltage, which may (SET) be greater than or equal to the threshold voltage of the first and. second reference voltages, and may be equal to or (V greater than or equal_REF Symbol Lenz) and Envelope Voltages (envelope) of Voltages (V of Vol._ENV In) some embodiments, at least one 7 of the two power, supply circuits (70) may (be, output from (73) the outside) of the two, power supply circuits 7, for example, from the (70) outside of the two. power supply (70) circuits, 2 and (C2), may (SW), be 1 received from the outside of the two power supply circuits, and may be received from the outside of the two power supply circuits, for example, from the external sources of the first and second capacitors, respectively, in the first and second embodiments, and may be different from each other. The (71), regulator 2 control unit (72), may include (73) a voltage regulator (74), a voltage regulator, and a voltage. regulator, respectively.

A voltage 1 regulator, (71) a voltage regulator, a reference voltage, a reference voltage, and a reference voltage (V, respectively._REF Input) voltage, based on (V zero_IN Output voltage of) the output of the output from the output of the output 1 from the output of the output of the (V output from_OUT1 For example, the one- to-three) 1-level (71) voltage regulator 3a, for 3c example, may DC-DC be the one,1, to (V-one converter illustrated with reference to the first to fourth-th output voltages of the first and second-th output voltages of the first and second output voltages of the first and second output voltages of the first and second output voltages of the first and second output voltages, respectively, in the first and second embodiments, respectively._OUT1 The reference voltage is) a reference (V voltage of the reference voltage._REF The level of zero) may be determined according to a level of 1 zero, and the first and second output voltages may be. supplied to the first and second (SW) output voltages of the first and second output voltages of the first (V and second output voltages of the first and second output_OUT1 Load) capacitance, according to capacitor control signal (C _ CL) zero, (C between zero and ground voltages_L In response to the capacitance. of 4 the variable capacitance (41) of the, variable capacitance of the capacitance of the (C _ CL) variable capacitance (SW) of the capacitance 2 (C2) of the load capacitance of the first and second capacitors (C of the first and second capacitors may be different from each other.)_L On) the other hand, in, response to one (C _ CL) capacitor control signal (SW) being turned off in 2 response (C2) to the second (C capacitor control signal, the first and the second capacitors of the first and second capacitors are connected to the load capacitance of the first and second capacitors, respectively._L It) can be ruled out from. zero.

The voltage regulator of 2 the first embodiment of (72) the present invention. Envelope voltage (V_ENV Input) voltage, based on (V zero_IN Output voltage of) the output of the output from the output of the output 2 from the output of the output of the (V output from_OUT2 For) example, the one.to,2 one voltage (72) regulator, 3a for example 3c, may include DC-DC the one-to,one converter illustrated with reference to FIGS. and/or, for example, between the first and second output voltages of the first and second output voltages of the first and second output voltages of the first and second voltages of the first and second envelope voltages of the first and second envelope voltages of the first and second (V envelope voltages of the (L) and (L)._ENV The output voltage of) the first output voltage of the output voltage of the first output voltage 2 of the second output voltage (V of the second output voltage_OUT2 The) voltage control circuit may (further, include a) circuit for adjusting the size. of the first and second envelope voltages of the first and second envelope voltages, for example, between the first and second output voltages of the first and second envelope voltages of the first and (V second envelope voltages, respectively._ENV For) example, the output voltage having a magnitude that follows the, envelope of the output signal swinging on the load, for. example, may 2 have a (V magnitude that corresponds to the envelope of the output signal that swings in the load, and thus, the output voltage of the output signal of the load of the load may be equal to or greater than zero._OUT2 For) example, in some embodiments, in some embodiments, in 7 some embodiments, the, first and the 2 second output (72) voltages of 1 the first (71) and the 1 second output (V voltages of the first and the second output voltages of the first and second output voltages of the first and second output voltages of the first and second output voltages may be equal to or greater than the output voltage of the first and/or second output voltages of the first and second output voltages of the first and second output voltages._OUT1 The) at least some of, the components included in the first and second Voltage (Voltage-Voltage 2 Voltage-Voltage Voltage (72)-Voltage-Voltage (Voltage-Voltage-Voltage-Voltage (Voltage-Vregulator) - (1 Voltage-Voltage-(V Voltage) - (Voltage._OUT1 P.b.) .sub.n The examples of the supply of. 1 the power (71) supplied to 2 the power (72) supply of the 8 first and 10 the second voltage regulator . respectively, may be described later with reference to FIGS.

To the mode (74) control signal which (73) is provided from the power (C _ MD) controller, the 1 mode switching (V mode is an output voltage of the output voltage of the first output voltage of the first power supply voltage of the second power supply voltage of the first power supply voltage._OUT1 The output voltages) 2 of the first and second output voltages of the first and the second (V output voltages of the first and second output_OUT2 Output voltage of at) least one of the two output voltages, and outputs the output voltage (V at the output voltage_OUT For example, the two-) mode, control signal may (C _ MD) output an average power (Average Power Tracking; APT) tracking power tracking mode (Envelope Tracking; ET) or an envelope tracking, power-(74) tracking mode, and the mode control signal may (C _ MD) output in response to a mode (V control signal that indicates an average power tracking mode, for example, in the form of an output voltage of the first and second output voltages of the first and second 1 output voltages of the first and second modes (A)._OUT1 The output voltage of) the output voltage of the output voltage of the output voltage of (V the output_OUT The) output voltage of the output, voltage of the first output voltage is (C _ MD) output to the 2 output of (V the first output voltage of the output voltage of the output voltage of the first output voltage of the output voltage of the first output voltage of the second envelope tracking mode in response to the mode control signal being output from the envelope tracking mode._OUT2 H.264) Output voltage (V_OUT In) some embodiments, the. output of, the power (74) transistor may include at least one power switch, and the one power switch may include a power transistor capable. of supporting a high current in some embodiments of the present invention.

For example, (73) the power controller (70) may include information indicating (SET) an average power tracking, mode or (SET) an envelope mode and may (C _ CL, C _ MD, C _ EN) include information indicating an. average power, tracking mode (SET) or an envelope mode, for example, between the first and second, output 1 voltages of (V the first and second output voltages of the first and second output voltages of the first and second output voltages of the first and second sets of the power supply circuits (e.g. the first and second sets of the power control circuits)._OUT1 For) example, in some embodiments, the reference. voltage may, be a (73) reference voltage, (V and in some embodiments, the reference voltage may be equal to or greater than the reference voltage, in some embodiments, and may be equal to or greater than the reference voltage, in some embodiments._REF Envelope Voltage) Models and Voltage/Models and Voltage Models and Voltages (V of Vol._ENV It) is also possible to generate a greater number of. zeros, respectively.

In some embodiments, the dual (73)- mode power controller, when the set signal (SET), (inactive) is indicative of an average power tracking mode, in some embodiments, may be deactivated. It (C _ EN) is possible 2 to provide (72) a voltage regulator of, the 1 voltage regulator of the first and second (V output voltages of the first_OUT1 D.V.)-sub.sup (V .2_OUT For) example, when the input mode (C _ MD) signal is an (74) envelope tracking mode,the 2 output of (72) the mode control signal (C _ EN) may be disabled in response, to the output 2 voltage of (72) the output - terminal of the. mode control, signal, (73) for example, (SET) in the case where the output voltage (active) of the (C _ EN) input/2 output of (72) the mode control signal, is 2 supplied to (V the output terminal of the mode control signal output from the output of the external power supply of the mode control signal of the mode control signal of the power supply of the mode control signal._OUT2 D.V.)-sub.sup (V .2_OUT In) response to the enabled enable signal (C _ MD) EN, the (74) mode control signal may. be 2 output to (72) the mode switching unit (C _ EN), and the output (V of the envelope voltage regulator is controlled in response to the enabled enable signal, and the output of the envelope voltage of the envelope voltage of the envelope voltage of the envelope voltage is equal to or greater than the reference voltage._ENV Input) voltage, based on (V zero_IN Output voltage of) the output of the output from the output of the output 2 from the output of the output of the (V output from_OUT2 H.264) Can be generated.

In some embodiments, the first and second output voltages (SET), of the first and (V second output voltages may be (73) equal to or greater than the output voltage of the first and second output voltages of the first and 1 second output voltages of the first and second output voltages of the first_OUT1 When) the level of the level of zero (SW) is, shown, the (C _ CL) capacitor control (SW) signal S, which. turns off the 2 second (C2) switch, 1 may be (71) provided to the (C switching unit, and thus the first and the second capacitors (the first and the second capacitors, respectively) may be supplied to the switch unit, respectively, and thus the load capacitance of the first and second voltages of the first and second voltages of the first and second capacitors may be equal to or greater than zero._L It) may not be contributed to zero and may have a load capacitance of, less than or equal to one (C-third._L In addition, the output. voltage, of the (73) output of 1 the output voltage of the first (V output voltage of the second power)_OUT1 When) the change is completed to a, desired (SW) level, a capacitor control (C _ CL) signal, (SW) which is turned on. when the, change 1 is completed (V to a desired level, may be provided to the switching unit, and the output voltage of the first and the second output voltages of the first and second output voltages may be supplied to the first and second output voltages of the first and second output voltages, respectively, respectively._OUT1 The zero) may have a reduced ripple in maintaining a constant level and may be quickly changed to a different level at the same time.

To 8 an exemplary embodiment of the present disclosure 7, the output (70) of the power supply, circuit 9 (the reference voltage regulator: the 8 first voltage regulator, the second voltage regulator (80), and the second example, are. also shown 8, 7 in FIGS 9, (71), 1 2 (72) (74). An output 8 voltage of the first output voltage of the first output voltage of the second 1 transistor is also in (V the (+) output voltage of_OUT1 Two-2 th-(V stage output-voltage-of-zero-power-)._OUT2 Two-), output voltage V.sub.sub. (V ._OUT Double-) Load Capacitance Layer and Load Capacitance (C._L A is shown.) in accordance with a flow of time.

To the 8 exemplary embodiment, of the (80) present invention, the power supply circuit may include 2 a (81), (C2), 2 first-(82) to-one (84) (SW), capacitor 1, a 1 first-(81) to-one (V capacitor, a first voltage regulator, a first voltage regulator, a second voltage regulator, a second voltage regulator, a second voltage regulator, a second voltage regulator, a second voltage regulator, and a second power supply, respectively._REF Out-) of-th-th-1 stage voltage, based (V on zero_OUT1 The envelope voltage regulator may, be 2 generated by (82) using an envelope (V voltage of a voltage regulator of the envelope voltage)_ENV Out-) of-th-th-2 stage voltage, based (V on zero_OUT2 Although) it is shown that. in 8 the example of 1 the second (81) embodiment, 2 the voltages (82) of the (buck) first and second voltages, of the first 1 and second (81) voltages/of the 2 first and (82) second voltages V out/of the - first and second voltages of. the first and second voltage regulators may be equal to or different from each other, respectively, in the second embodiment, the first and the second voltages of the first and second voltages may be equal to or different from each other and may be different from each other.

An N-th-1 th-th-voltage regulator, a first (81)-out-of-one-1 out-of-one (L1),stage secondary-capacitor-1 of-two-th-stage (C1), switch, and a 1-th-th-stage voltage regulator The first and second switches 1 (81 _ 1) may (81 _ 2) be connected to the. first 1 and second (81 _ 2) switch controllers, respectively, and the first and second switches may be connected to the first and second switch controllers, respectively, and may be connected to the first and second (V switch controllers, respectively, respectively._REF The output voltages) 1 of the first and second output voltages of the first and the second (V output voltages of the first and second output_OUT1 In response to the 1 second switch control (C _ SW1) signal, the first, switch 1 control signal is generated in response (81 _ 1) to the 1 input voltage (C _ SW1) of the (V second switch control signal)_IN It) is possible 1 to (L1) provide a current to 1 the (L1) first and the second inductors and to. draw 1 a (C1) current at 1 a ground (81) voltage from the first to the second inductors of the first and second inductors of the first and second inductors of the first and second inductors of the first and second inductors of the first and the second inductors of the first and second inductors of the first and the second inductors of the first and the second inductors of the first and the second inductors of the first and the second inductors of the first and the (C second inductors of the first and the second inductors (S_L As) described above with reference. to 4 the capacitor 7 control signal, the load, capacitance 2 of (C2) the first (SW) and second voltages V (C _ CL) out of the 1 first and (81) second voltage regulators (C may be equal to or greater than the load capacitance of the first and second voltages of the first and second capacitors, respectively, as described above with reference to FIGS._L It) is possible to change one or more of the above-described embodiments.

The 2 N-(82) th-2 th (L2),2 th voltage (82 _ 1) regulator may 2 include an (82 _ 2) N-th- regulator 3-(C3) (82 _ 3). (82) 2 2 2 (L2). The (82 _ 1) first and 2 second switch (82 _ 2) controllers, 1 respectively, (81) may function as a buck converter in the same manner as, 2 (81) the n 2-th voltage regulator, respectively, and the (V output voltage of the first and the second output voltages of the first and the second-th-stage Voltage-Gungate_.sub .4.4.4.0-0-5.4.0-5.sub .0-0._OUT2 It can be responsible for the low frequency. band, 2 as well (82 _ 2) as, the 1 low frequency (81) band, 1 and, (81 _ 2) in addition, between the first and second switch controllers of the first 2 and second (V regulators of the first and second voltages of the first and second output voltages, respectively.)_OUT2 Alternatively), instead of receiving feedback 3 as (C3) feedback, a current flowing through the first, capacitor may be 2 received as feedback (C _ SW2), and may be. generated 2 based on (82 _ 2) zero feedback, (C _ EN) and the second switch, control signal may be generated (C _ EN) based on the second feedback, and may, be powered down (C _ EN) in response to the enabled enable. signal nPRE, and in some embodiments, may be powered down in response to the enabled enable signal nini.

Orifampl( EN) is (82 _ 3) an output voltage of an output of the output 1 of the output of the output (V of the amplifier_OUT1 Supply power from) zero, and an envelope voltage of between two envelope volts, ((V V50.1-50.2)_ENV A) non-inverting input and an 2 output voltage of the output of the output of the first and the second output voltages of the first and the second output voltages of the first and second (V output voltages of_OUT2 The) inverting input may include an inverting input. received in the sense amplifier, and may include an inverting input for receiving an output (82 _ 3) of at least one amplifier, for example. The output signal passes 3 through (C3) the output of 2 the first (V output voltage and is output from the output of the output voltage of the first output voltage of the first output voltage of the first output voltage of the first output voltage_OUT2 As can be reflected to, one 3 of (C3) the AC first and second output voltages of the first and. or, (82 _ 3) second 3 (C3) capacitors 2, the first and the second output voltages of the first (V and/or the second and/or the second and/or the second and/or the first and/or the second and/or the)_OUT2 In) one embodiment of the present invention,the 2 first and (82 _ 2) second switches may (C _ EN) be turned on in, response to the enable signal (C _ EN), and may be turned on in response, to the enabled (C _ EN) enable signal, and may be. powered down in response to the enabled enable signal nPRE, at least in some embodiments of the present invention.

When the mode (84) control signal is supplied (C _ MD) to the output 1 node of (81) the power supply circuit at (80) the output node of the power supply. circuit, for example (84), the mode control signal is supplied to the (C _ MD) output node of 1 the power (V supply circuit one, for example, the mode control signal is supplied to the output node of the power supply circuit, for example, in the second mode._OUT1 D.V.)-sub.sup (V .2_OUT H.264) On the other hand, the, output node of the output node of (C _ MD) the output node 1 is electrically (81) disconnected from the output node (80) of the power supply circuit (disconnection) one, and the output node 8 of the power supply, circuit is (V electrically disconnected from the output node of the power supply circuit one, in response to the. mode control signal generating the three envelope tracking mode, on the other hand._OUT The) output voltages 2 of the first and second output voltages of the first and second output voltages of the first and second (V output voltages_OUT2 The) output voltage of the, output voltage regulator may be 2 equal to (82) or less than zero but is disabled in an average power tracking mode, but the output voltage of the output voltage is equal to (V or greater than zero._OUT The) output voltages 1 of the first and second output voltages of the first and second output voltages of the first and second (V output voltages_OUT1 The) determination can be determined by means of a determination of at least one of the following. paragraphs.

To the 9 exemplary embodiment, t90 the first t93 power, supply circuit (80), the second power supply, and the. second power, supply voltage (V may be set to the average power tracking mode, and the output voltage of the second power supply circuit may be equal to or greater than the second power supply voltage, and may be equal to or greater than the first and second output voltages, respectively._OUT The) output voltages 1 of the first and second output voltages of the first and second output voltages of the first and second (V output voltages_OUT1 In) an average power tracking. mode, which may coincide with zero, in an average power 1 tracking mode, the (-) - 1 th-th (81)-th-voltage regulator, is a dynamically (V-zero output voltage (V.sub.)_OUT1 It) is possible to change the level of zero and to change the level of (V zero.₁₁ → V₁₂ → V₁₃ Two-1 th-(V stage output-voltage-of-zero-power-)._OUT1 Load) (C capacitance C while the level of zero is changed_L Decision) may be reduced,for example, t91 at a time interval of, for example, in a time interval of, for example, in a time interval of, for example, in a Load capacitance (C_L Double-th 1-(C capacitance-)_L1 Pitty)-th Capacitance from Domain-2-of-(C J. Biol._L2 The) reduced power supply voltage can be reduced to zero and an output voltage of zero-th,level output voltage of the output voltage of 1 the (O (V)- (O)._OUT1 While (V the) level of zero is changed.₁₁ → V₁₂ Load Capacitance) Capacitance Bit Litty (C._L Double-th 2-(C capacitance-)_L2 In) some embodiments, the load capacitance of, the second (C load capacitance of the second load capacitance is. greater than or equal to the second load capacitance of the first and second embodiments of the present invention._L Double-th 2-(C capacitance-)_L2 Whereas it can be steadily reduced to, zero 1, (C one-way capacitance-of-two-th-capacitance-)_L1 It) can be incrementally increased to. zero, and t92, similarly, a load capacitance of less than, and at a time of, for example, a load capacitance of less than or equal to zero, and is t93 equal to or greater than zero, and a load capacitance (C of less than or equal_L As) described above, the. output voltage, of the first, and 1 second output (V voltages of the first and second output voltages of the first and second output voltages of the first and second output voltages of the first and second output voltages may be equal to or different from each other, as described above._OUT1 The level of) zero may be rapidly changed, while the level of zero may be rapidly changed, while the output voltage of the zeroth,1 (V level zero-level output voltage may be increased._OUT1 The output voltage of) the th output 1 voltage is held constant while the level of (V zero is kept constant._OUT1 As a result of (), noise), for example, in the case of noise, for example, in the case of noise, the noise can be reduced, and the noise can be reduced . for example.

For example t93, when the (80) envelope tracking mode is set to the. envelope tracking, mode, (V the output voltage of the output voltage of the envelope tracking mode may be equal to or greater than the output voltage of the output voltage of the envelope tracking mode._OUT That), is, the output voltage of the output voltage of the output 2 of the output of the output voltage (V of the output voltage_OUT2 The) voltage regulator 2 may be (82) determined by a voltage regulator of a voltage regulator of at least one of the above-described embodiments, or may be performed by a voltage. regulator 8 of at least two or more. As described above with reference, to 2 the above (82)-described embodiments, some (82 _ 3) components of 1 the first (81)-to-1 third-level voltage regulator, for example, amplifier A, may be an N-th output voltage which is supplied to the first-th output voltage regulator of the first-stage output voltage regulator, for example, an output voltage of the first output voltage regulator of the first-to-third-stage voltage regulator (V of the first-to-third-level regulator_OUT1 May be supplied with power from), zero 2 and an output voltage of zero-to-zero output voltage may be supplied to the output of the first and second output voltages of the first and (V second output voltages_OUT2 The level of) the output voltage of the th output voltage 1 according to the level (V of zero_OUT1 The level of) zero can be dynamically varied (V.₁₄ → V₁₅ → V₁₆ ,). Similar to, as in Mean, Power Tracking (1 Average Power Tracing mode) as described above, the zeroth-to-(V zero output voltage (OD.sub.)_OUT1 Load) (C capacitance C while the level of zero is changed_L As shown in the example . for, example 9, as shown in, the above-mentioned embodiment t92, t94 the t95 load (C capacitance of the load capacitance of the first and second embodiments may be reduced, for example, as shown in FIGS)._L Double)-th-th-th-2 Capacitum-(C Literal Capacitance_L2 Limit) can be reduced to. zero.

In a 10 circuit diagram illustrating an example of the power (100) supply circuit according to. an, exemplary 10 embodiment of the (100) present disclosure 8, the power (80) supply circuit of, the 1 power supply (110) circuit of the (C present disclosure is a circuit diagram of the power supply circuit, and the power supply circuit of the power supply circuit according to the present disclosure is not limited thereto._L It) is to be noted 2 that (C2), in the description. of, the 10 first exemplary embodiment, the 8 same reference numerals may be used for. the same reference numerals, and the same reference numerals may be used for the same reference numerals, and the description thereof will be omitted, and the description thereof will be omitted.

The invention is also shown 10. To the, exemplary embodiment (100) of the (SW), present 1 invention, (110), the 2 power supply (120) circuit may include (140) a switching unit, a 1 voltage regulator (110), a voltage (V regulator, a voltage regulator, a voltage regulator, a voltage regulator, a reference voltage regulator, a reference voltage regulator, a reference voltage regulator, and a reference voltage regulator, respectively._REF Out-) of-th-th-1 stage voltage, based (V on zero_OUT1 The) first and second switches, may 1 be (L1), connected 1 to (C1), the 1 first and (111) second output 1 terminals of (112) the first and second. switch 1 controllers, (112) respectively, and (V the first and second switches may be connected to the first and second switch controllers, respectively, and the first and second switches may be connected to the first and second switch controllers, respectively, respectively._REF The output voltages) 1 of the first and second output voltages of the first and the second (V output voltages of the first and second output_OUT1 Based on the output 1 of the envelope (C _ SW1) voltage regulator, an. envelope 2 voltage of the envelope voltage of (120) the output (V of the envelope voltage)_ENV Out-) of-th-th-2 stage voltage, based (V on zero_OUT2 The) first and second switches, may 2 be (L2), connected 2 to the (121), first 2 and second (122), switch 3 controllers (C3), respectively (123), and the first. and 2 second switch (122) controllers, 3 respectively (C3), may be connected to 2 the first and (C _ SW2)/or second input. output terminals of the first and second switch controllers, respectively, and may be connected between the first and second output terminals of the first and/or second output terminals of the first and second switch controllers, respectively, respectively.

, Similar 8 to the (SW) case of the case of FIG. I (SW), similarly to the case of the switching 10, device shown in FIG. I, the power supply voltage of the first and/or the second power supply voltage is equal to or greater than the threshold voltage of the 1 first and the second switches of FIGS. Voltage doubler (V_OUT1 The) load capacitance of a (C _ CL) voltage regulator of 1 the voltage (110) regulator of the (C voltage regulator of the voltage regulator of the capacitor control signal of the capacitor control signal of the first and the second voltages of the first and the second voltages of the first and second voltages of the first and second_L In) a case where the. capacitance, of 10 the first (SW) capacitor of 2 the first (120) capacitor AC is equal to 3 or (C3) greater than the load (C capacitance of the first and second capacitors of the first and second capacitors, the capacitance of the first and the second capacitors of the first and second capacitors may be equal to or greater than the load capacitance of the first and the second capacitors of the first and second voltages of the first and second voltages of the first and second voltages of the first and second voltages of the first and second voltages of the first and_L Load) capacitance from addition to or excluding (C zero_L For) example, in an. average power, tracking mode, the output node (140) of the first and (C _ MD) the second capacitors 1 may be (110) electrically connected to the output 2 node of (120) the first and second voltage regulators,and may have 3 a (C3) floated output due 1 to the (110) output node of the output node of. the, first and the second voltages (123) of the first and (C _ EN) the second capacitors of the first and. the second 3 capacitors (C3), respectively, and may be 8 the same 2 as (C2) the output nodes of the first, and (SW) second voltages of the first and second voltages of the first and the second voltages of the first and the second capacitors. The load capacitance of the (C _ CL) capacitor by turning on and off/according to the capacitor control (C signal zero._L In) some embodiments of the. present invention, (SW) in some embodiments, the envelope tracking (C _ CL) mode may be changed in response. to an envelope tracking mode, and in some embodiments, the envelope tracking mode may be switched between the envelope tracking mode and the envelope tracking mode, in some embodiments.

The method 11 of operating a switching regulator according to an exemplary embodiment of the. present disclosure, 11 for example, 1 may include the (10) operation method of the switching. regulator 11 according to an exemplary, embodiment of the present disclosure S10, S30 and the S50 operation method of the, switching regulator 11 may be 1 performed by 2 using the switching regulator. of the first exemplary embodiment, for example, as shown in FIGS.

It is S10 possible to S11 include Steps S12 of Steps, Steps, S) and S11 Steps, S12 and in some embodiments, Steps S11 A,) and Steps S) may be performed in parallel, and in some embodiments, Steps I and C may be performed in parallel, and in some 1 embodiments, Steps III (V-H, STEP-A and ST2.sub .72.72.72.72.72.72.72.72.72.5.₁ Output) voltage of (V zero_OUT The) operation may be performed to output. a reference, voltage, (10) for example, (V a reference voltage, for example, a reference voltage, e.g. a voltage of the reference voltage, for example, between the reference voltage and the reference voltage, for example, between the reference voltage and the reference voltage_REF , Based on the) level of zero, a Level-Level-Level (1 (V Level-S.sub.)₁ What) is claimed Output voltage (V_OUT If) the load capacitance is less than S12 a, threshold value (C, the load capacitance of the load capacitance is. less than the load capacitance of the load capacitance of the load capacitance of the load capacitance of the load capacitance of step_L Double)-th Capacitance Layer-ty-eighth-1 Charging capacitance-(C of._L1 The) operation may be performed, for. example, in response (13) to a capacitor control (C _ CL) signal, for example (C, to a capacitor control signal, for example, to a capacitor control signal, for example, to control the load capacitance of the load capacitance of the first and second capacitor circuits, e.g. the first and second capacitor circuits._L Double)-th Capacitance Layer-ty-eighth-2 Charging capacitance-(C of._L2 K-th-1 capacitance (C-)_L1 The) output voltage, which, can be maintained at zero, and therefore the (V output voltage of the output voltage V.sub._OUT In) this embodiment, the noise may be reduced.

It is S30 possible to S31 include Steps S32 of Steps, Steps, S) and S31 Steps, S32 and in some embodiments, Steps S31 A,) and Steps S) may be performed in parallel, and in some embodiments, Steps I and C may be performed in parallel, and in some 1 embodiments, Steps III (V-H, STEP-A and ST2.sub .72.72.72.72.72.72.72.72.72.5.₁ Summary) of-Programming 2 ((V S.2.72.72.1.₂ Output) voltage, output from zero to output (V voltage_OUT For) example, the operation of changing. the reference, voltage may (10) be performed, (V for example, a reference voltage of the reference voltage, for example, a reference voltage of the reference voltage of the reference voltage, for example, between the reference voltage and the reference voltage, for example._REF Output) voltage Vo in response to a level change of (V zero_OUT Sumen et) al. J. Biol. 1 Chem. J. (V Biol. Chem.₁ Summary) of-Programming 2 ((V S.2.72.72.1.₂ Can be changed to zero) and, therefore, the output voltage output, from the (V output voltage V.sub._OUT Pumen et) al. J. Biol. 1 Chem. J. (V Biol. Chem.₁ Summary) of-Programming 2 ((V S.2.72.72.1.₂ H.264) , The load capacitance. is S32 increased, toward the (C load capacitance of the load capacitance of greater than or equal_L Double)-th Capacitance Layer-ty-eighth-2 Charging capacitance-(C of._L2 The) operation may be performed, for. example, in response (13) to a capacitor control (C _ CL) signal, for example (C, to a capacitor control signal, for example, to a capacitor control signal, for example, to control the load capacitance of the load capacitance of the first and second capacitor circuits, e.g. the first and second capacitor circuits._L Double)-th Capacitance Layer-ty-eighth-1 Charging capacitance-(C of._L1 K-th-2 capacitance (C-)_L2 The) output voltage, which, can be maintained at zero, and therefore the (V output voltage of the output voltage V.sub._OUT Pumen et) al. J. Biol. 1 Chem. J. (V Biol. Chem.₁ Summary) of-Programming 2 ((V S.2.72.72.1.₂ It) is possible to quickly change to. zero.

It is S50 possible to S51 include Steps S52 of Steps, Steps, S) and S51 Steps, S52 and in some embodiments, Steps S51 A,) and Steps S) may be performed in parallel, and in some embodiments, Steps I and C may be performed in parallel, and in some 2 embodiments, Steps III (V-H, STEP-A and ST2.sub .72.72.72.72.72.72.72.72.72.5.₂ Output) voltage of (V zero_OUT The) operation may be performed to output. a reference, voltage, (10) for example, (V a reference voltage, for example, a reference voltage, e.g. a voltage of the reference voltage, for example, between the reference voltage and the reference voltage, for example, between the reference voltage and the reference voltage_REF , Based on the) level of zero, a Level-Level-Level (2 (V Level-S.sub.)₂ Output) voltage of (V zero_OUT If) the load capacitance is less than S52 a, threshold value (C, the load capacitance of the load capacitance is. less than the load capacitance of the load capacitance of the load capacitance of the load capacitance of the load capacitance of step_L Double)-th Capacitance Layer-ty-eighth-1 Charging capacitance-(C of._L1 H.264) The operation of holding can be. performed, for example (13), the capacitor control (C _ CL) signal is in response (C to the capacitor control signal, for example, to a capacitor control signal, for example, to a capacitor control signal, for example, to a capacitor control signal, to control the load capacitance of the capacitor circuit, for example, to the capacitor control signal_L Double)-th Capacitance Layer-ty-eighth-2 Charging capacitance-(C of._L2 K-th-1 capacitance (C-)_L1 The) output voltage, which, can be maintained at zero, and therefore the (V output voltage of the output voltage V.sub._OUT In) this embodiment, the noise may be reduced.

In order 12 to describe the operation method of the switching regulator according to an. exemplary, embodiment 12 of the 11 present disclosure, the method S20 may further S40 include the operations of the. operation of, the 12 switching regulator according 1 to the exemplary (10) embodiment; FIGS, 12 1 5.

To 11 the step S10 S of, FIG. S20 I, the process, may be carried out in the S20 step (C of, for example, the load capacitance of the load capacitance of_L The) operation of steadily decreasing the zero may. be carried, out S10, for example S12, at step (C S included in step S, and the load capacitance of the load capacitance of the operation of the load capacitance of the operation of the load capacitance of the operation of the load capacitance of the load capacitance is greater than or equal to zero, for example._L Double-th 1-(C capacitance-)_L1 The) load capacitance of, the S30 load capacitance of S32 the operation of (C the load capacitance of the operation of the load capacitance of the operation of the load capacitance of the load capacitance of the load capacitance of the load capacitance of the load capacitance of the first step_L Double-th 2-(C capacitance-)_L2 It can be maintained at. zero and, S20 accordingly, at a point of step S/C of between step S/S/C=) Capacitance (C_L Double-th 1-(C capacitance-)_L1 Pitty)-th Capacitance from Domain-2-of-(C J. Biol._L2 Duristically reduced to zero) and a, steadily reduced load capacitance of (C less than._L Output) voltage due to (V zero_OUT The level of) zero may be quickly changed. from the initial, and then, a step of step S may be carried out in step S/S30, (step S), where step S is performed. at a step (step S).

, S30 At a, step S40, the load capacitance, of S40 the load capacitance of the load capacitance is (C greater than the load capacitance of the load capacitance of step S_L The) operation of incrementally increasing the zero may. be performed, S30 for example, S32 at step S (C comprised in step S, and the load capacitance of the load capacitance of the operation of the load capacitance of the operation of the load capacitance of the load capacitance is greater than or equal to zero, for example._L Double-th 2-(C capacitance-)_L2 The) load capacitance of, the S50 load capacitance of S52 the operation of (C the load capacitance of the operation of the load capacitance of the operation of the load capacitance of the load capacitance of the load capacitance of the load capacitance of the load capacitance of the first step_L Double-th 1-(C capacitance-)_L1 It can be maintained at. zero and, S40 accordingly, at (C a step of between step S/C, a load capacitance of the load capacitance of the load capacitance)_L Double-th 2-(C capacitance-)_L2 Pitty)-th Capacitance from Domain-1-of-(C J. Biol._L1 Incrementally increasing to zero) and incrementally increasing a load capacitance, of less than one (C-eighth_L Output) voltage due to (V zero_OUT J.)-b. Summary-Three-level two 1-level two-level (V.₁ Summary) of-Programming 2 ((V S.2.72.72.1.₂ From the point of) time when the change is completed to the first-level-level-zero-level-level-2 zero-level zero-level-(V level.₂ At least one of) the first and second electrodes may be disposed between the first and second. substrates.

For 13 example, in some embodiments of the (130) present disclosure, at (130) least, one of the - first - and (SoC) second functions may be performed by at least a portion of the first and, second functions, and may be performed in. a second portion 13 (130), 1 of the second portion 4 (131 of the first portion of the second portion of the first portion of the second 134) portion PMIC(135) of the first portion of the first. portion.

However, 1 in some 4 embodiments, (131 at 134) least PMIC(135) one of the 1 functions of 4 between the (VDD1 first VDD4) to the second functions may be an analog. circuit for, processing 1 a digital 4 signal, (131 such 134) as an analog-to (Application Processor; AP)-digital converter, or the like, and, in some embodiments, the system-in-unit 13. (130) block, may - be an (Analog-to-Digital Converter; ADC) analog circuit for processing (mixed signal) an analog signal, e.g. an analog-to 4-digital converter, or may, be an analog (130) circuit 4 for processing an 5 analog signal. The above functional blocks may also be included.

The input voltage is PMIC(Power Management Integrated Circuit)(135) input to the input voltage output from the input voltage of (V the input voltage_IN For example, 1 at least 4 one of (VDD1 the VDD4) first and second function, blocks may be (C _ V) an image processor 1 for processing 4 image data (VDD1 and VDD4) may receive a supply voltage of a. level which 1 is 4 dynamically varied (131 according to 134) a required performance and power consumption, for example, at least one of the first and the second function blocks, (e.g. between the first and second functions. 1 of, the first and (131) the second function blocks, and between the first (131) and 1 second functions of (VDD1) 1 the first and the second functions of, the functions of 1 (131) the first and the second 1 functions of the functions of the first and second functions.) The voltage may be received at (VDD1) a voltage of greater than or equal to. zero.

The PMIC(135) method of 1 dynamically changing (131) the level of the supply voltage of the two functional (C _ V) blocks as described above, PMIC(135) may include the switching (C _ V) regulator described above 1 with reference (VDD1) to the drawings, wherein the. level of, the supply voltage of the zero supply voltage DVS(Dynamic Voltage Scaling) may be increased or. PMIC(135) decreased as described above, and in some embodiments, the level 1 of the (VDD1) supply voltage of the zero supply voltage may be changed rapidly, 1 and in (VDD1) some embodiments, the level of. the supply, voltage 1 of the (131) zero supply 1 voltage may (VDD1) be changed rapidly, 1. If (VDD1) the level of the voltage zero is changed. to resume the 1 operation after (VDD1) the level of the voltage, zero 1 is changed (131), the performance of the operation of the zeroth-th operation may be, improved (130) (131) (130). 1 . (VDD1), 1

In a 14 block diagram of the wireless communication device according to (200) an exemplary embodiment. of, the 14 present disclosure (250), the wireless communication device may (User Equipment; UE)(be included) in a. wireless communication system (200) using, a cellular, 5G, LTE network, such as a cellular network, in some embodiments, WLAN(Wireless Local Area Network), or may be included in a wireless communication system. including a cellular network, such as, for example, a cellular network, (200) in some embodiments, or in any other wireless communication system, as shown in FIGS. A switching regulator in accordance with an exemplary embodiment (216) of the present disclosure may be used to provide variable power to a power amplifier, and as (200) 14. (210), shown in (220), any (230) of the above (240)-described embodiments, the second wireless. communication device may include a transceiver, a baseband processor, a base transceiver, a power supply, (250) a power supply circuit, and a Battery (B.).

In some (210) embodiments, the transmitter (211) or receiver may comprise, a matching (212), circuit or (213) a filter, (214) and at least some embodiments, (215), the transmitter (216) or receiver may (217) comprise a matching circuit or a. filter, and (211) at least some embodiments, the first and second low-(230) noise amplifiers may include. a matching, circuit or (212) a filter, and at least some embodiments, the (213) transmitter/receiver (212) may comprise a matching circuit or a filter. For example, in some, embodiments, (214) the first - and second output circuits may include a mixer . for up (215)-conversion - of the up-and- down conversion of the output signal of (216) the (215) transmission circuit, and the (217) second-to-third-output circuit. may include a matching circuit or a filter, in some embodiments of the present invention.

For example, (220) in some (210) embodiments of the present invention, a/baseband, processor/may be referred to as. a modem, and (220) may be referred to as. a modem (220), and in some embodiments, the baseband processor may be referred to (SET) as a modem, and may (V generate a set signal for setting an average power tracking mode or an envelope tracking mode, and may be referred to as an average power tracking mode or an envelope tracking mode, in some embodiments._OUT It) is possible to generate a setting signal that (SET) is used to change a level. of zero.

The power supply (240) circuit may output an input voltage to the input voltage from a battery of the power supply circuit (250) ('BCC') at the (V output of the battery_IN H.264) An output voltage that is, capable of receiving and providing power to a two (216)-power (V amplifier (OPA)_OUT The three power supply circuit. may include (240) the switching regulator described above with reference to the drawings, wherein the (SET) load capacitance (C of the first and second power supply circuits may be greater than or equal to zero.)_L Output voltage as) well as by modifying (V zero_OUT It) is possible to enable a rapid level change and a stable. level of zero, respectively.

Rather, these embodiments are provided so that. this disclosure will be thorough and complete, and will fully convey the scope of the present disclosure to those skilled in the art, and thus the present disclosure. will be thorough and complete, and will fully convey the scope of the present disclosure to those. skilled, in the art. The true technical protection scope of the present disclosure should be determined by the technical spirit of the. appended claims.