Apparatus and method for determining effect of on-chip noise on signal propagation

Method and apparatus for automatically testing the design of a simulated integrated circuit

AUTOMATIC SELF TEST OF AN INTEGRATED CIRCUIT VIA AC I/O LOOPBACK

A multi-bit test value is loaded into a built-in latch of the IC component, and a pad of the component is selected for testing. A number of different sequences of test values are automatically generated, based on the stored test value, without scanning-in additional multi-bit values into the latch. A signal that is based on the different sequences of test values is driven into the selected pad and looped back. A difference between the test values and the looped back version of the test values is determined, while automatically adjusting driver and/or receiver characteristics to determine a margin of operation of on-chip I/O buffering for the selected pad.

TEST CIRCUIT AND TEST METHOD

A test circuit includes flip-flops operating in synchronization with a clock signal, a timing adjustment circuit to generate a first set signal that provides a command that sets output signals from the flip-flops at a predetermined logic, and a second set signal that provides a command that detects a fault in the output signals from the flip-flops, and to set timing for cancellation of the command of the second set signal, the timing being delayed by n cycles of the clock signal from timing for cancellation of the command of the first set signal, and a fault detection circuit to output a fault detection signal during a period of time from the cancellation of the command of the first set signal to the cancellation of the command of the second set signal, if there is an output signal having a different logic in the output signals from the flip-flops.

Device for determining the length of a shift register

A diagnostic arrangement is disclosed for determining the length of arbitrary shift registers not exceeding a maximum length. Knowledge of this length is an essential prerequisite for data manipulations by means of shift registers. Concerned are the reading of shift registers and the display of the contents stored in them, as well as the writing of arbitrarily selectable patterns into said shift registers. The arrangement proper includes circuitry connected to the shift register or test object for generating a test shift pattern of the length Lmax+K, with K>/=2, which pattern is made up of a defined bit configuration, for example, only binary ones, with a defined transition at the end facing the test object and which is shifted through the test object. Also provided is storage means of length Lmax+K, which is connected to the output of the test object and which, as the test shift pattern is shifted, accommodates the information of the length Lx of the test object and the part Lmax+K-Lx ...

Linear feedback shift register for circuit design technology validation

An apparatus and process employing an integrated circuit device technology within a linear feedback shift register using a cyclic redundancy check code scheme for validating the device technology under realistic very large scale integrated circuit operating conditions. By deploying two feedback shift registers in a full-duplex mode, the device technology can be subjected to arbitrarily-long, pseudo-random test signal sequences. Also, by checking the registers with variable-phase pulses, representative device delay time information can be obtained.

Apparatus and method for determining effect of on-chip noise on signal propagation

PROCEDURE AND EQUIPMENT FOR THE BINARY COUNTER EXAMINATION.

MECHANISM FOR THE STATEMENT OF THE LAENGE OF ARBITRARY SHIFT REGISTERS.

DISPOSICAO PARA A DETERMINACAO DO COMPRIMENTO DE REGISTRADORES DE DESLOCAMENTO ARBITRARIOS

Methods and Apparatus for Characterizing Electronic Fuses Used to Personalize an Integrated Circuit

An integrated circuit device having at least one fuse capable of being blown in order to provide measurements of fuse current-voltage characteristics is provided. The integrated circuit device also provides at least one pulse generation circuit associated with the fuse and capable of generating a pulse to blow the fuse through one or more DC input signals.

Circuit and testing circuit thereof

A circuit, including a TAP circuit, a routing circuit, a first test path and a second test path, is provided. A first input terminal and a first output terminal of the routing circuit are respectively coupled to a scan output terminal and a first scan input terminal of the TAP circuit. A first terminal of the first test path is coupled to a second input terminal of the routing circuit. A second terminal of the first test path is coupled to a second output terminal of the routing circuit. A first terminal of the second test path is coupled to a third input terminal of the routing circuit. A second terminal of the second test path is coupled to a third output terminal of the routing circuit. The routing circuit couples the scan output terminal of the TAP circuit to the first scan input terminal of the TAP circuit or the first terminal of the first test path or the first terminal of the second test path.

LINEAR RUECKGEKOPPELTES SHIFT REGISTER TO GUELTIGKEITSBESTAETIGUNG WITH THE CIRCUIT DRAFT TECHNOLOGY.

Einrichtung zur Feststellung der Laenge beliebiger Schieberegister

Apparatus and method for determining effect of on-clip noise on signal propagation

PSEUDORANDOM BINARY SEQUENCE ERROR COUNTERS

... 1431218 Counting apparatus MARCONI CO Ltd 14 March 1974 [15 June 1973] 28506/73 Heading G4D [Also in Division H4] In an arrangement where a test sequence, e.g. pseudo-random is transmitted and compared with an identical generated sequence at a remote end, to ensure correspondence of receiver generator, a known generator 101-151 is modified so that exclusive OR 151 output passes through a correcting and error counting circuit instead of directly as in prior art in order that the sequence leaving 151 should be the same as that fed into 101. Output of 151 is fed together with incoming signals to a second exclusive OR 16, which will only issue a 1 when inputs differ. This is gated by a clock into counter 19, also applied to exclusive OR 17; the second input to 17 will thus be inverted and act as corrector for input signals. In this arrangement shift register 101-141 must be initially correct. In a modification (Fig. 3, ...

PROCEDURE AND EQUIPMENT FOR THE AUTOMATIC TEST OF A SIMULATED INTEGRATED CIRCUIT

Global transition scan based AC method

The present invention, enables complementing the state of either the master (L1) or slave latch (L2) in the shift register latches (SRLs) without changing the state of the other. When this is done after properly loading the LSSD scan chain using a normal scan chain sequence, the next system clock sequence can be used to launch a desired transition from each SRL in the scan chain. The actual mechanism for complementing the state of latches in LSSD scan chains can vary depending on which one of the L1 or L2 latch is being complemented; details of the actual scan chain and Shift Register Latch (SRL) design; and the semiconductor chip circuit technology. The complementing function can be provided as an integral part of the SRL design with minimal impact to system path and performance. An alternate complementing method would be to use a self complementing latch function. In this design, the latch to be complemented does not require an additional input containing the complement value, but rather ...

LINEARES RUECKGEKOPPELTES SCHIEBEREGISTER ZUR GUELTIGKEITSBESTAETIGUNG BEI DER SCHALTUNGSENTWURFTECHNOLOGIE.

Method and apparatus for automatically testing the design of a simulated integrated circuit

Apparatus and method for determining effect of on-chip noise on signal propagation

Generating a test sequence of code based on a directed sequence of code and randomly selected instructions

ARRANGEMENT FOR DETERMINING THE LENGTH OF ARBITRARY SHIFT REGISTERS

METHOD AND ARRANGEMENT OF TESTING SEQUENTIAL CIRCUITS REPRESENTED BY MONOLITHICALLY INTEGRATED SEMICONDUCTOR CIRCUITS

Apparatus and method for determining effect of on-chip noise on signal propagation

An integrated circuit testing apparatus having at least two of a first test circuit producing a signal for determining at least one of an operating reference signal and a substrate coupling effect on a plurality of components within the integrated circuit; a second test circuit producing a signal for determining at least one of a cross-talk effect on the plurality of components and the accuracy of an interconnect capacitance extraction value; a third test circuit producing a signal for determining at least one of an effect of system noise on the operational speed of the plurality of components and a maximum degradation expected for a logic path between the plurality of components; and a fourth test circuit producing a signal for determining an effect of power supply noise on a signal propagation delay within the plurality of components.

PSEUDORANDOM BINARY SEQUENCE ERROR COUNTERS

Determining the effects of noise or crosstalk in an integrated circuit

An integrated circuit is provided with a core logic area 12 containing components such as transistors, logic gates, processors, memory caches etc. In order to test the effects of noise or crosstalk on these components a plurality of test circuits 22 - 28 are provided. Each test circuit may be a ring oscillator operable to produce a test signal of known frequency. Circuit 22 produces a reference signal for use in testing. Circuit 24 measures the delay introduced by crosstalk, and has the conductive traces between its elements formed into loops that extend close to components of the core logic of the integrated circuit. Circuit 26 has its elements randomly positioned throughout the core logic area and measures system noise. Circuits 22 to 26 may have their own power supply, separate from the power supply to the core logic. Circuit 28 mimics a logic path of the integrated circuit and shares a power supply with the core logic to measure power supply noise. Measurements may be made with the ...

PSEUDORANDOM BINARY SEQUENCE ERROR COUNTERS

DATA PROCESSING SYSTEM, CAPABLE OF STORING CONTROL DATA IN A CONTROL MEMORY WITH INCREASING SPEED

LSI Circuitry conforming to level sensitive scan design (LSSD) rules and method of testing same

An LSI integrated semiconductor circuit system comprised of a plurality of interconnected minimum replaceable units. The system and each minimum replaceable unit fully conforms to the Level Sensitive Scan Design (LSSD) Rules. [Level Sensitive Scan Design Rules are fully disclosed and defined in each of the following U.S. Pat. Nos. 3,783,254, 3,761,695, 3,784,907 and in the publication "A Logic Design Structure For LSI Testability" by E. B. Eichelberger and T. W. Williams, 14th Design Automation Conference Proceedings, IEEE Computer Society, June 20-22, 1977, pages 462-467, New Orleans, La Each of the minimum replaceable units includes a shift register segment having more than two shift register stages. Each register stage of each shift register segment of each minimum replaceable unit includes a master flip-flop (latch) and a slave flip-flop (latch). Connection means is provided for connecting the shift register segments of said minimum replaceable units into a single shift register. Additional ...

Linear feedback shift register for circuit design technology validation

An apparatus and process employing an integrated circuit device technology within a linear feedback shift register using a cyclic redundancy check code scheme for validating the device technology under realistic very large scale integrated circuit operating conditions. By deploying two feedback shift registers in a full-duplex mode, the device technology can be subjected to arbitrarily-long, pseudo-random test signal sequences. Also, by checking the registers with variable-phase pulses, representative device delay time information can be obtained.

METHOD AND APPARATUS FOR AUTOMATICALLY TESTING THE DESIGN OF A SIMULATED INTEGRATED CIRCUIT

A method and apparatus for automatically testing the design of a simulate integrated circuit containing a network of flip-flops. The network is put into a reset state and each flip-flop is tested to determine if it has expected input and output states. If the flip-flop is likely to transition, it is listed as a potential fault.

Determining the effects of noise or crosstalk in an integrated circuit

An integrated circuit is provided with a core logic area 12 containing components such as transistors, logic gates, processors, memory caches etc. In order to test the effects of noise or crosstalk on these components a plurality of test circuits 22 - 28 are provided. Each test circuit may be a ring oscillator operable to produce a test signal of known frequency. Circuit 22 produces a reference signal for use in testing. Circuit 24 measures the delay introduced by crosstalk, and has the conductive traces between its elements formed into loops that extend close to components of the core logic of the integrated circuit. Circuit 26 has its elements randomly positioned throughout the core logic area and measures system noise. Circuits 22 to 26 may have their own power supply, separate from the power supply to the core logic. Circuit 28 mimics a logic path of the integrated circuit and shares a power supply with the core logic to measure power supply noise. Measurements may be made with the ...

Apparatus and method for determining effect of on-chip noise on signal propagation

METHOD AND ARRANGEMENT OF TESTING SEQUENTIAL CIRCUITS REPRESENTED BY MONOLITHICALLY INTEGRATED SEMICONDUCTOR CIRCUITS

An LSI monolithically integrated semiconductor circuit consisting of sequential circuits and combinational circuits contains a considerable number of storage elements designed as latches which for error detection are assembled into a shift register. If a sequential circuit thus built of several minimum replaceable units is error checked according to the invention no major additional process steps in the form of further terminals and connecting pins to a module representing the minimum replaceable unit will be required. As disclosed by the invention, by minor modification of the respective input circuits in the minimum replaceable units, the first two shift register stages of a respective minimum replaceable unit are first brought into their respective complementary states. Then the shift register contents are read out in a conventional manner, with the bit positions represented respectively by the first two shift registers in all minimum replaceable units being examined at the shift output ...

Code-based directed sequence and random selection instruction generation code test sequence

Arrangement for determining the length of arbitrary shift registers

A diagnostic arrangement is disclosed for determining the length of arbitrary shift registers not exceeding a maximum length. Knowledge of this length is an essential prerequisite for data manipulations by means of shift registers. Concerned are the reading of shift registers and the display of the contents stored in them, as well as the writing of arbitrarily selectable patterns into said shift registers. The arrangement proper includes circuitry connected to the shift register or test object for generating a test shift pattern of the length Lmax+K, with K>/=2, which pattern is made up of a defined bit configuration, for example, only binary ones, with a defined transition at the end facing the test object and which is shifted through the test object. Also provided is storage means of length Lmax+K, which is connected to the output of the test object and which, as the test shift pattern is shifted, accommodates the information of the length Lx of the test object and the part Lmax+K-Lx ...

Pseudo-random binary sequence error counters

The invention relates to a pseudo-random binary sequence error counter. The error counter includes a multi-stage shift register and a logic gating circuit for comparing the signals at the outputs of predetermined stages of the shift register. The output of the first logic gating means, which during normal operation corresponds to the correct binary sequence, is compared in a second logic gating means with the incoming sequence and errors in the incoming sequence are detected and counted. Errors in the incoming signal are corrected in a further logic gating means whose output is fed into a serial input terminal of the shift register.

Device for determining the length of a shift register

A diagnostic arrangement is disclosed for determining the length of arbitrary shift registers not exceeding a maximum length. Knowledge of this length is an essential prerequisite for data manipulations by means of shift registers. Concerned are the reading of shift registers and the display of the contents stored in them, as well as the writing of arbitrarily selectable patterns into said shift registers. The arrangement proper includes circuitry connected to the shift register or test object for generating a test shift pattern of the length Lmax+K, with K>/=2, which pattern is made up of a defined bit configuration, for example, only binary ones, with a defined transition at the end facing the test object and which is shifted through the test object. Also provided is storage means of length Lmax+K, which is connected to the output of the test object and which, as the test shift pattern is shifted, accommodates the information of the length Lx of the test object and the part Lmax+K-Lx ...

EINRICHTUNG ZUR FESTSTELLUNG DER L ENGE BELIEBIGER SCHIEBEREGISTER

ARRANGEMENT FOR DETERMINING THE LENGTH OF ARBITRARY SHIFT REGISTERS

ARRANGEMENT FOR DETERMINING THE LENGTH OF ARBITRARY SHIFT REGISTERS

An arrangement for determining the length Lx of arbitrary shift registers, which registers may be in the form of test objects, not exceeding a predetermined maximum length Lmax, wherein the arrangement is connected to an input of the test object for generating a test shift pattern of length Lmax + K, with K?2 which consists of a defined bit configuration. that is only binary ones, with a defined data transition at its end facing the test object and which is shifted through the test object, a storage of the length Lmax + K which is connected to an output of the test object and which, a the shift pattern is shifted, accommodates the information of the length Lx of the test object and the part Lmax + K - Lx of the test shift pattern and a display field, whose individual fields are permanently associated with one storage cell, each of the storages indicating the content of the cell, so that the data transition, and thus the end and the length Lx, of the test object can be determined.

Data processing system, capable of storing control data in a control memory with enhanced speed

Système de traitement des données, capable de mémoriser des données de commande dans une mémoire de commande avec une vitesse accrue

... a) Système de traitement des données, capable de mémoriser des données de commande dans une mémoire de commande avec une vitesse accrue. b) Un processeur comporte une mémoire de commande 17 et reçoit des données de commande et un signal d'horloge dans un premier mode et des données de test et le signal d'horloge dans un second mode; un circuit de commande 31 commande l'envoi du signal d'horloge à un registre de chargement 16 et à un groupe de registres 14 en premier et second modes respectivement. Le registre de chargement est le premier chemin balayé; en réponse au signal d'horloge, il mémorise les données de commande dans la mémoire de commande. Dans le premier mode, le registre de chargement peut donner les données de commande sous forme de données de commande sorties par décalage. Le groupe de registres fonctionne comme second chemin balayé et reçoit les données de test pour les envoyer sous forme de données de test sorties par décalage. c) L'invention propose un système de traitement ...

Apparatus and method for hardware-assisted diagnosis of broken logic-test shift-registers

The present invention provides a systematic means of switching contiguous segments of each production-test shift-register into several diagnostic scan-configurations. If the functional scan-verification tests fail for the production-test scan-configuration, then these same verification tests can be repeated for the alternative, diagnostic scan configurations. Using the principle of superposition, the passing and failing LSSD flush/scan tests for these diagnostic configurations will allow the failing location to be localized to a single segment of the original failing shift-register.

Apparatus and method for determining effect of on-chip noise on signal propagation

Apparatus and method for determining effect of on-clip noise on signal propagation

METHOD AND APPARATUS FOR AUTOMATICALLY TESTING THE DESIGN OF A SIMULATED INTEGRATED CIRCUIT

A method and apparatus for automatically testing the design of a simulate integrated circuit containing a network of flip-flops. The network is put into a reset state and each flip-flop is tested to determine if it has expected input and output states. If the flip-flop is likely to transition, it is listed as a potential fault.

Monolithically integrated testable registers that cannot be directly addressed

A circuit is provided for testing a plurality of non-readable latch registers. Each of a plurality of first logic gates have an input coupled to one of a plurality of input pins, and an output coupled to an input of each of the latch registers. An address circuit is coupled to the latch registers for selectively addressing one of the latch registers. A plurality of second logic gates each have an input coupled to one output of each of the latch registers and an output coupled to one of the input pins. An enabling circuit is coupled to each of the second logic gates for enabling the logic gates.

SCAN COMPRESSION THROUGH PIN DATA ENCODING

A method for testing a chip comprising receiving N scan-in chains of test data; using the N scan-in chains of test data to perform tests on the chip; receiving a merged expected test-result and masking-instruction signal on X pins of the chip from the off-chip test equipment, X being less than 2*N; decoding the merged expected test-result and masking-instruction signal to extract N decoded output signals, each of the N decoded output signals corresponding to a respective chain of test results.

Torschaltung zur Pruefung von Ringschaltungen

Determining the effects of noise or crosstalk in an integrated circuit

An integrated circuit is provided with a core logic area 12 containing components such as transistors, logic gates, processors, memory caches etc. In order to test the effects of noise or crosstalk on these components a plurality of test circuits 22 - 28 are provided. Each test circuit may be a ring oscillator operable to produce a test signal of known frequency. Circuit 22 produces a reference signal for use in testing. Circuit 24 measures the delay introduced by crosstalk, and has the conductive traces between its elements formed into loops that extend close to components of the core logic of the integrated circuit. Circuit 26 has its elements randomly positioned throughout the core logic area and measures system noise. Circuits 22 to 26 may have their own power supply, separate from the power supply to the core logic. Circuit 28 mimics a logic path of the integrated circuit and shares a power supply with the core logic to measure power supply noise. Measurements may be made with the ...

Apparatus and method for determining effect of on-chip noise on signal propagation

Generating a test sequence of code based on a directed sequence of code and randomly selected instructions

Verfahren und Gerät zur Binärzählerprüfung.

Determining the effects of noise or crosstalk in an integrated circuit

An integrated circuit is provided with a core logic area 12 containing components such as transistors, logic gates, processors, memory caches etc. In order to test the effects of noise or crosstalk on these components a plurality of test circuits 22 - 28 are provided. Each test circuit may be a ring oscillator operable to produce a test signal of known frequency. Circuit 22 produces a reference signal for use in testing. Circuit 24 measures the delay introduced by crosstalk, and has the conductive traces between its elements formed into loops that extend close to components of the core logic of the integrated circuit. Circuit 26 has its elements randomly positioned throughout the core logic area and measures system noise. Circuits 22 to 26 may have their own power supply, separate from the power supply to the core logic. Circuit 28 mimics a logic path of the integrated circuit and shares a power supply with the core logic to measure power supply noise. Measurements may be made with the ...

Generating a test sequence of code based on a directed sequence of code and randomly selected instructions

A method of generating a test sequence code 500 to be run on a target processing system for use in testing the target processing system wherein: the test sequence of code is based on one or more directed sequences of code 504; the one or more directed sequences of code are predetermined sequences of one or more directed instructions for testing predetermined parts of the target processing system; the method comprises for at least one of the one or more directed sequences of code, inserting randomly selected instructions at one or more insertion points in the directed sequence of code 506. A second independent claim to a computer program which when executed causes a computer to generate a test sequence of code to be run on a target processing system which implements said method. The method may further comprise selecting resources including at least one of a set of registers and/or a set of memory locations, to be used by the randomly selected instructions that are different to the resources ...

ARRANGEMENT FOR DETERMINING THE LENGTH OF ARBITRARY SHIFT REGISTERS

METHOD AND APPARATUS FOR AUTOMATICALLY TESTING THE DESIGN OF A SIMULATED INTEGRATED CIRCUIT

VERFAHREN UND GERÄT ZUM AUTOMATISCHEN TEST EINES SIMULIERTEN INTEGRIERTEN SCHALTKREISES

PSEUDO-RANDOM BINARY SEQUENCE ERROR COUNTERS

Apparatus and method for determining effect of on-chip noise on signal propagation

The invention relates to an integrated circuit testing apparatus having a first test circuit producing a signal for determining at least one of an operating reference signal and a substrate coupling effect on a plurality of components within the integrated circuit; a second test circuit producing a signal for determining at least one of a cross-talk effect on the plurality of components and the accuracy of an interconnect capacitance extraction value; a third test circuit producing a signal for determining at least one of an effect of system noise on the operational speed of the plurality of components and a maximum degradation expected for a logic path between the plurality of components; and a fourth test circuit producing a signal for determining an effect of power supply noise on a signal propagation delay within the plurality of components. Methods of operating such a testing apparatus are also disclosed.

M-BIT BINARY COUNTER AND ITS OPERATION METHOD

PURPOSE: To quickly and completely inspect an M-bit binary counter including carry propagation also by decoupling respective stages of the M-bit binary counter including plural stages, and after independently checking respective stages, recoupling respective stages together and checking carry propagation among stages. CONSTITUTION: During the test operation of the multistage M-bit binary counter including S counting stages each of which includes an N-bit counter, respective stages are decoupled to execute individual operation, a count value is loaded to the N-bit counter included in each stage and the N-bit counter of each stage is clocked 2N times to independently check the function of the N-bit counter. Then respective stages are together coupled and functioned as a multistage M-bit counter, one clock pulse is supplied to the M-bit counter to check carry propagation among respective stages. When each N-bit counter is a type for generating an output only when the counter is completely ...

Register with a context switch device and method of context switching

CIRCUIT AND TESTING CIRCUIT THEREOF

A circuit, including a TAP circuit, a routing circuit, a first test path and a second test path, is provided. A first input terminal and a first output terminal of the routing circuit are respectively coupled to a scan output terminal and a first scan input terminal of the TAP circuit. A first terminal of the first test path is coupled to a second input terminal of the routing circuit. A second terminal of the first test path is coupled to a second output terminal of the routing circuit. A first terminal of the second test path is coupled to a third input terminal of the routing circuit. A second terminal of the second test path is coupled to a third output terminal of the routing circuit. The routing circuit couples the scan output terminal of the TAP circuit to the first scan input terminal of the TAP circuit or the first terminal of the first test path or the first terminal of the second test path. 1. A circuit , comprising:a test access port circuit, comprising a first scan input terminal and a scan output terminal;a routing circuit, comprising a first input terminal, a first output terminal, a second input terminal, a second output terminal, a third input terminal and a third output terminal, wherein said first input terminal and said first output terminal of said routing circuit are respectively coupled to said scan output terminal and said first scan input terminal of said test access port circuit;a first test path, comprising a first terminal and a second terminal, wherein said first terminal of said first test path is coupled to said second input terminal of said routing circuit, said second terminal of said first test path is coupled to said second output terminal of said routing circuit; anda second test path, comprising a first terminal and a second terminal, wherein said first terminal of said second test path is coupled to said third input terminal of said routing circuit, and said second terminal of said second test path is coupled to said third ...

Apparatus and method for hardware-assisted diagnosis of broken logic-test shift-registers

The present invention provides a systematic means of switching contiguous segments of each production-test shift-register into several diagnostic scan-configurations. If the functional scan-verification tests fail for the production-test scan-configuration, then these same verification tests can be repeated for the alternative, diagnostic scan configurations. Using the principle of superposition, the passing and failing LSSD flush/scan tests for these diagnostic configurations will allow the failing location to be localized to a single segment of the original failing shift-register.

Apparatus and method for determining effect of on-chip noise on signal propagation

The invention relates to a combination for determining the effects of signal noise and cross-talk on on-chip propagation, comprising an integrated circuit, and a testing system having a signal generator, a plurality of ring oscillators responsive to the signal generator and a signal analyzer responsive to the plurality of ring oscillators for dynamically measuring the effects of noise and cross-talk on the integrated circuit. The plurality of ring oscillators includes a first ring oscillator constructed to mimic a data path within the integrated circuit, a second ring oscillator constructed with traces routed within the core logic area, a third ring oscillator randomly placed within the core logic area, and a fourth ring oscillator constructed to mimic a data path within the integrated circuit, the fourth ring oscillator sharing a power source with at least one component of the plurality of components within the core logic area.

Methods and Apparatus for Characterizing Electronic Fuses Used to Personalize an Integrated Circuit

An integrated circuit device having at least one fuse capable of being blown in order to provide measurements of fuse current-voltage characteristics is provided. The integrated circuit device also provides at least one pulse generation circuit associated with the fuse and capable of generating a pulse to blow the fuse through one or more DC input signals.

Pseudo random pattern generation circuit

In a pseudo random pattern generation circuit having a normal input operation mode, a boundary scanning operation mode and an inherent pseudo random pattern generation mode, output stage selectors are provided to supply input data as output data without modification in the normal input operation mode. In addition, flipflops are provided to hold the data in the boundary scanning operation mode, so that the data held in the flipflops are not supplied as output signals. Thus, in the normal input operation mode, the data processing speed is increased, and in the boundary scanning operation mode, the data just before the boundary scanning operation mode is maintained without being outputted to an internal circuit of the LSI chip.

Test circuit, selector, and semiconductor integrated circuit

A test circuit according to the present invention performs a test of a first tri-state device and a second tri-state device having their outputs connected to the same node, and includes: a test output terminal; and a test unit operable to output a first logical value or a second logical value to the test output terminal according to whether the voltage of the node is higher or lower than a threshold value, and the test unit converts the intermediate potential occurring at the node into the first logical value and outputs the first logical value to the test output terminal when the first tri-state device outputs a high level signal to the node and the second tri-state device outputs a low level signal to the node.

Method of determining systematic defect in first circuit under test

Methods for determining a systematic defect in a circuit under test are provided. Elements of the circuit under test converted into scan cells. A first scan chain that includes a first plurality of scan cells is formed. Each scan cell of the first plurality of scan cells of the first scan chain are of a first cell type. The first scan chain contains a first scan input and a first scan output. A first test pattern is applied at the scan input and a first test output is collected for the applied first test pattern at the first scan output. The collected first test output is compared with a first expected test output. The first cell type is marked to be a suspect for a systematic defect when the first test output is different from the first expected test output.

Methods and apparatus for characterizing electronic fuses used to personalize an integrated circuit

An integrated circuit device having at least one fuse capable of being blown in order to provide measurements of fuse current-voltage characteristics is provided. The integrated circuit device also provides at least one pulse generation circuit associated with the fuse and capable of generating a pulse to blow the fuse through one or more DC input signals.

REGISTER WITH A CONTEXT SWITCH DEVICE AND METHOD OF CONTEXT SWITCHING

A method of changing execution contexts is provided that includes receiving a context selection input. In a first clock phase, the method includes shifting data from a first latch element of a normal execution context to a second latch element of the normal execution context and shifting shadow data from a third latch element of a shadow execution context to a fourth latch element of the shadow execution context. In a second clock phase, the method includes shifting the shadow data of the fourth latch element of the shadow execution context into the first latch element of the normal execution context and shifting the data of the second latch element of the normal execution context into the third latch element of the shadow execution context. In a particular embodiment, the method may include receiving a test mode selection and shifting test data, such as scan test or automatic test pattern generated data, to a test output. © KIPO & WIPO 2009 ...

PSEUDOZUFALLS-BINAERFOLGE-FEHLERZAEHLER

ERROR DETECTION CIRCUIT, ELECTRONIC CONTROL SYSTEM FOR VEHICLE INCLUDING SAME, AND OPERATING METHOD THEREOF

An objective of the present invention is to provide an error detection circuit, an electronic control system for a vehicle including the same, and an operating method thereof which improve reliability of a fault signal generated when a vehicle operates. According to the present invention, the electronic control system for a vehicle comprises an error detection circuit having a diagnosis register to store error data corresponding to an error detected when a vehicle target device operates, and generating first and second output pulses corresponding to the detected error; and an electronic control unit connected to the error detection circuit. The electronic control unit performs a read operation for the error data from the diagnosis register, receives the first and second output pulses when the read operation fails, uses the received first and second output pulses to distinguish the detected error, and controls the vehicle target device in accordance with the detected error. COPYRIGHT KIPO ...

Method and apparatus for testing a binary counter

Verfahren und Gerät zur Binärzählerprüfung.

CONTROL STORAGE LOADING MEMORY FOR DATA PROCESSOR

PURPOSE: To load the control storage at a high speed and at the same time to decrease the packing pins by writing repetitively the contents of a control storage loading register and storing the control information in a control storage. CONSTITUTION: A word of a microprogram to be stored is received as a shift-in data 300, and a scan path clock 500 exclusive for loading control storage is continuously received until one word of the microprogram is applied to a control storage loading register 4. Then the contents of the register 4 are written into a control storage 1 via a control storage writing path 700. Hereafter the words of the microprogram are applied one by one into the register 4 and the contents of this register 4 are repetitively written into the storage 1. Thus all microprograms are stored in the storage 1. As a result, the storage 1 is loaded at a high speed and at the same time the number of packing pins can be decreased for a data processor. COPYRIGHT: (C)1990,JPO&Japio ...

VERFAHREN UND GERÄT ZUM AUTOMATISCHEN TEST EINES SIMULIERTEN INTEGRIERTEN SCHALTKREISES

Multiplexer select line exclusivity check method and apparatus

Disclosed herein is a system and method for determining whether multiplexers select lines within a circuit are exclusive of one another. The disclosed invention may be performed in an automated manner on one or more multiplexers within subunit, across subunits, within units, across units, or within entire modules. The method and system employs the application of logical circuit analysis in combination with predefined gate logic to ascertain select line exclusivity in an automated and flexible fashion.

Apparatus and method for determining effect of on-chip noise on signal propagation

The invention relates to a method for dynamically testing the effects of signal noise and cross-talk on an integrated circuit having a core logic area. The method comprises measuring an inactive operating frequency for each of the plurality of test circuits, measuring an active operating frequency for each of a plurality of test circuits, and analyzing the plurality of inactive operating frequencies and the plurality of active operating frequencies to determine the effects of signal noise and cross-talk on the integrated circuit.

Apparatus and method for determining effect of on-chip noise on signal propagation

The invention relates to an integrated circuit testing apparatus having a first test circuit producing a signal for determining at least one of an operating reference signal and a substrate coupling effect on a plurality of components within the integrated circuit; a second test circuit producing a signal for determining at least one of a cross-talk effect on the plurality of components and the accuracy of an interconnect capacitance extraction value; a third test circuit producing a signal for determining at least one of an effect of system noise on the operational speed of the plurality of components and a maximum degradation expected for a logic path between the plurality of components; and a fourth test circuit producing a signal for determining an effect of power supply noise on a signal propagation delay within the plurality of components. Methods of operating such a testing apparatus are also disclosed.

Method and apparatus for automatically testing the design of a simulated integrated circuit

A method and apparatus for automatically testing the design of a simulated integrated circuit containing a network of flip-flops. The network is put into a reset state and each flip-flop is tested to determine if it has expected input and output states. If the flip-flop is likely to transition, it is listed as a potential fault.

Data recorder

An apparatus that allows for access to any and all registers of a central processing unit in a line replaceable unit (LRU) without a need to open the housing of the LRU is provided. The apparatus may receive write or read packets from an external device and relay the same to an LRU. The apparatus may receive state information from one or more registers of the LRU in response. The apparatus may transmit or transfer the state information to an external device. The apparatus may be used to update firmware in the LRU, for diagnostics or testing.

Scannable last-in-first-out register stack

A scannable LIFO register stack in which registers are arranged in a stack with each register having a number of bit locations. Each register is in communication with an adjacent register located above and below it. In particular, each bit location in a register within the stack located between the top and the bottom register is in communication with a corresponding bit location in an adjacent register located above the register and a corresponding bit location in an adjacent register located below the register. Except for the last bit, each bit location in the top register has a connection to an offset bit location in the bottom register. Shifting a bit of data from a bit location in the top register to the offset bit location in the bottom register results in the bit being shifted to the right by one bit location according to the present invention. The last bit location in the top register has an output that is used as a scan output. The first bit location in the bottom register has an ...

Linear feedback shift register for circuit design technology validation

Scan chain technology and method for using scan chain structure

Scan chain techniques and method of using scan chain structure

Testing systems and method of testing an integrated circuit are provided. A testing system comprises an input terminal, multiple circuit elements, each having a register, and an output terminal forming a scan chain through which an input signal is propagated. The testing system further comprises a debugger that includes a mapping module that stores information mapping register values to their respective functional meanings. The input signal is applied to extract all values of all of the registers whether or not accessible by a processor.

Test circuit, selector, and semiconductor integrated circuit

REGISTER WITH A CONTEXT SWITCH DEVICE AND METHOD OF CONTEXT SWITCHING

A method of changing execution contexts is provided that includes receiving a context selection input. In a first clock phase, the method includes shifting data from a first latch element of a normal execution context to a second latch element of the normal execution context and shifting shadow data from a third latch element of a shadow execution context to a fourth latch element of the shadow execution context. In a second clock phase, the method includes shifting the shadow data of the fourth latch element of the shadow execution context into the first latch element of the normal execution context and shifting the data of the second latch element of the normal execution context into the third latch element of the shadow execution context. In a particular embodiment, the method may include receiving a test mode selection and shifting test data, such as scan test or automatic test pattern generated data, to a test output.

Method of determining the number of individual integrated circuit computer chips or the like in a boundary scan test chain and the length of the chain

A method in which the boundary-scan circuitry of a boundary-scan chain is placed in a first condition in which each bit of a series of bits will traverse a path through an equipment identification register if one exists or will require one clock to traverse each device in the boundary-scan chain in which no complete identification register exists. A first recognizable series of bits is sent through the chain and the beginning of the series of bits is detected at the output of the chain while a count is kept at the output to determine the number of individual boundary-scan circuits in the chain. The count is incremented by one for each identification register traversed or for each circuit which has no such complete register. The boundary-scan chain is then placed in a second condition in which each bit of a series of bits will traverse the instruction registers of the individual boundary-scan circuits in the boundary-scan chain, and a second recognizable series of bits is sent through the ...

Method for allocating addresses and corresponding units

A method includes providing a first and second electronic unit unit, generating a wirelessly transmitted signal for detecting or generating one signal or several signals for detection on a chain of electronic elements, for the first unit, detecting a transmission time of the wirelessly transmitted signal for detection or detecting a first transmission time on a first of the chain, for the second unit, detecting a second value or the transmission time of the wirelessly transmitted signal for detection or detecting a second value or a second transmission time on a second position of the chain that is different from the first position, converting the first value or the transmission time detected for the first unit to a first address for the first unit, and converting the second value or the transmission time detected within or for the second unit to a second address for the second unit.

Method and device for testing sequential circuits realized by monolithic integrated semiconductor circuits

An LSI integrated semiconductor circuit system comprised of a plurality of interconnected minimum replaceable units. The system and each minimum replaceable unit fully conforms to the Level Sensitive Scan Design (LSSD) Rules. [Level Sensitive Scan Design Rules are fully disclosed and defined in each of the following U.S. Pat. Nos. 3,783,254, 3,761,695, 3,784,907 and in the publication "A Logic Design Structure For LSI Testability" by E. B. Eichelberger and T. W. Williams, 14th Design Automation Conference Proceedings, IEEE Computer Society, June 20-22, 1977, pages 462-467, New Orleans, La.]. Each of the minimum replaceable units includes a shift register segment having more than two shift register stages. Each register stage of each shift register segment of each minimum replaceable unit includes a master flip-flop (latch) and a slave flip-flop (latch). Connection means is provided for connecting the shift register segments of said minimum replaceable units into a single shift register.

Адаптер тестирования канала оперативной памяти третьего поколения

Полезная модель относится к области испытательной техники и может быть использована для проведения испытаний на работоспособность каналов синхронной динамической памяти с произвольным доступом и удвоенной скоростью передачи данных третьего поколения в материнских платах компьютерной техники.Техническим результатом является расширение функциональных возможностей за счет обеспечения тестирования DIMM разъемов памяти третьего поколения.Адаптер тестирования канала оперативной памяти третьего поколения содержит семь штыревых соединителей, один двусторонний DIMM соединитель, девять перемычек и программируемую логическую интегральную схему, содержащую внутренний JTAG интерфейс.1 ил. РОССИЙСКАЯ ФЕДЕРАЦИЯ (19) RU (11) (13) 189 608 U1 (51) МПК G11C 29/56 (2006.01) G01R 31/317 (2006.01) ФЕДЕРАЛЬНАЯ СЛУЖБА ПО ИНТЕЛЛЕКТУАЛЬНОЙ СОБСТВЕННОСТИ (12) ОПИСАНИЕ ПОЛЕЗНОЙ МОДЕЛИ К ПАТЕНТУ (52) СПК G11C 29/56 (2019.02); G01R 31/318533 (2019.02) (21)(22) Заявка: 2019110382, 09.04.2019 (24) Дата начала отсчета срока действия патента: Дата регистрации: 29.05.2019 (73) Патентообладатель(и): Акционерное общество "МЦСТ" (RU) (45) Опубликовано: 29.05.2019 Бюл. № 16 (56) Список документов, цитированных в отчете о поиске: US 7730369 B2, 01.06.2010. EP (54) Адаптер тестирования канала оперативной памяти третьего поколения (57) Реферат: Полезная модель относится к области счет обеспечения тестирования DIMM разъемов испытательной техники и может быть памяти третьего поколения. использована для проведения испытаний на Адаптер тестирования канала оперативной работоспособность каналов синхронной памяти третьего поколения содержит семь динамической памяти с произвольным доступом штыревых соединителей, один двусторонний и удвоенной скоростью передачи данных третьего DIMM соединитель, девять перемычек и поколения в материнских платах компьютерной программируемую логическую интегральную техники. схему, содержащую внутренний JTAG интерфейс.1 Техническим результатом является ил. расширение функциональных ...

Method and apparatus for device access port selection

The disclosure describes a novel method and apparatuses for allowing a controller to select and access different types of access ports in a device. The selecting and accessing of the access ports is achieved using only the dedicated TDI, TMS, TCK, and TDO signal terminals of the device. The selecting and accessing of device access ports can be achieved when a single device is connected to the controller, when multiple devices are placed in a daisy-chain arrangement and connected to the controller, or when multiple devices are placed in a addressable parallel arrangement and connected to the controller. Additional embodiments are also provided and described in the disclosure.

Dual mode test access port method and apparatus

Connection circuitry couples scan test port (STP) circuitry to test access port (TAP) circuitry. The connection circuitry has inputs connected to scan circuitry control output leads from the TAP circuitry, a select input lead, and a clock input lead. The connection circuitry has outputs connected to a scan enable (SE) input lead, a capture select (CS) input lead, and the scan clock (CK) input lead of the STP circuitry. The connection circuitry includes a multiplexer having a control input connected with a clock select lead from the TAP circuitry, an input connected with a functional clock lead, an input connected with the clock input lead, an input connected with a Clock-DR lead from the TAP circuitry, an OFF lead, and an output connected with the scan clock input lead.

Integrated circuit having a scan chain and testing method for a chip

An IC having a scan chain and a testing method for a chip, comprising a first interface group, a second interface group and a scan data selector. The first interface group and the second interface group each comprise at least two input/output (I/O) interfaces which can be packaged as external pins of the IC. The I/O interfaces of the first interface group are connected to input terminals of the scan data selector in one-to-one correspondence, and an output terminal of the scan data selector is connected to a scan data input terminal of the scan chain. A scan data output terminal of the scan chain is connected to the I/O interfaces of the second interface group.

Serial i/o using jtag tck and tms signals

The present disclosure describes a novel method and apparatus of using the JTAG TAP's TMS and TCK terminals as a general purpose serial Input/Output (I/O) bus. According to the present disclosure, the TAP's TMS terminal is used as a clock signal and the TCK terminal is used as a bidirectional data signal to allow serial communication to occur between; (1) an IC and an external controller, (2) between a first and second IC, or (3) between a first and second core circuit within an IC.

Ieee 1149.1 and p1500 test interfaces combined circuits and processes

In a first embodiment a TAP of IEEE standard 1149.1 is allowed to commandeer control from a WSP of IEEE standard P1500 such that the P1500 architecture, normally controlled by the WSP, is rendered controllable by the TAP. In a second embodiment (1) the TAP and WSP based architectures are merged together such that the sharing of the previously described architectural elements are possible, and (2) the TAP and WSP test interfaces are merged into a single optimized test interface that is operable to perform all operations of each separate test interface. One approach provides for the TAP to maintain access and control of the TAP instruction register, but provides for a selected data register to be accessed and controlled by either the TAP+ATC or by the discrete CaptureDR, UpdateDR, TransferDR, ShiftDR, and ClockDR WSP data register control signals.

Two-Dimensional Scan Architecture

Aspects of the invention relate to techniques of using two-dimensional scan architecture for testing and diagnosis. A two-dimensional scan cell network may be constructed by coupling input for each scan cell to outputs for two or more other scan cells and/or primary inputs through a multiplexer. To test and diagnose the two-dimensional scan cell network, the two-dimensional scan cell network may be loaded with chain patterns and unloaded with corresponding chain test data along two or more sets of scan paths. Based on the chain test data, one or more defective scan cells or defective scan cell candidates may be determined.

Method and Apparatus for Fault Injection

The present invention provides various circuits for injecting faults into a larger circuit, sometimes called circuit under test, or CUT. One type of fault injection circuit is a clock controlled fault injection circuit. This type of circuit uses internal scan chains as a way by which a fault injection operation is performed while a system clock is in the off state. Another type of fault injection circuit is a concurrent fault injection circuit. This type of fault injection circuit uses dedicated fault injection scan chains in parallel with or without internal scan chains. Yet another type of fault injection circuit is a hybrid fault injection circuit that uses both clock controlled and concurrent fault injection circuits. Other embodiments are disclosed and still other embodiments would be obvious to those of ordinary skill in the art upon understanding the full scope of the present disclosure.

Semiconductor device

A semiconductor device, comprising: a user circuit having a plurality of flip-flops; and a connection path which, while in test mode, connects the plurality of flip-flops and forms a scan chain, wherein the connection path has a logic operation circuit which performs a logic operation on a non-inverted output value of any flip-flop among the plurality of flip-flops and outputs the result, or, an inverted value connection path which outputs to a following-stage flip-flop an inverted output value of any flip-flop among the plurality of flip-flops.

Selectively accessing test access ports in a multiple test access port environment

A TAP linking module ( 21, 51 ) permits plural TAPs (TAPs 1 - 4 ) to be controlled and accessed from a test bus ( 13 ) via a single TAP interface ( 20 ).

Scan Chain Fault Diagnosis

Embodiments related to identifying a reference scan cell locationally related to a fault condition exhibited by a scan chain in which the reference scan cell is included are provided. In one example, a method for identifying a reference scan cell is provided, the method comprising, in a capture mode, outputting combinational logic values to scan cells in the scan chain so that scan cell values for the scan cells are based on respective combinational logic values, the combinational logic values electrically connected with the scan chain. The example method further comprises, in a shift mode, sequentially determining the scan cell value for each scan cell, and identifying as the reference scan cell a scan cell last determined to be at an expected logical state for that scan cell.

Self-reparable semiconductor and method thereof

A semiconductor device includes a plurality of processors and a spare processor configured to perform respective processing functions. A plurality of first switches is located at respective inputs of the plurality of processors. Each of the plurality of first switches is configured to selectively provide an input signal to a respective one of the plurality of processors and the spare processor. A first multiplexer is located at an input of the spare processor. The first multiplexer is configured to receive the input signals from each of the plurality of first switches and route, to the spare processor, a selected one of the input signals corresponding to a failed one of the plurality of processors. The spare processor is further configured to perform a processing function associated with the failed one of the plurality of processors in response to receiving the selected one of the input signals.

Boundary scan path method and system with functional and non-functional scan cell memories

An integrated circuit or circuit board includes functional circuitry and a scan path. The scan path includes a test data input lead, a test data output lead, a multiplexer, and scan cells. A dedicated scan cell has a functional data output separate from a test data output. Shared scan cells each have a combined output for functional data and test data. The shared scan cells are coupled in series. The test data input of the first shared scan cell is connected to the test data output of the dedicated scan cell. The combined output of one shared scan cell is coupled to the test data input lead of another shared scan cell. The multiplexer has an input coupled to the test data output, an input connected to the combined output lead of the last shared scan cell in the series, and an output connected in the scan path.

Boundary scan chain for stacked memory

A boundary scan chain for stacked memory. An embodiment of a memory device includes a system element and a memory stack including one or more memory die layers, each memory die layer including input-output (I/O) cells and a boundary scan chain for the I/O cells. A boundary scan chain of a memory die layer includes a scan chain portion for each of the I/O cells, the scan chain portion for an I/O cell including a first scan logic multiplexer a scan logic latch, an input of the scan logic latch being coupled with an output of the first scan logic multiplexer, and a decoder to provide command signals to the boundary scan chain.

Selectively accessing test access ports in a multiple test access port environment

A TAP linking module ( 21, 51 ) permits plural TAPs (TAPs 1 - 4 ) to be controlled and accessed from a test bus ( 13 ) via a single TAP interface ( 20 ).

Position independent testing of circuits

Scan distributor, collector, and controller circuitry connect to the functional inputs and outputs of core circuitry on integrated circuits to provide testing through those functional inputs and outputs. Multiplexer and demultiplexer circuits select between the scan circuitry and the functional inputs and outputs. The core circuitry can also be provided with built-in scan distributor, collector, and controller circuitry to avoid having to add it external of the core circuitry. With appropriately placed built-in scan distributor and collector circuits, connecting together the functional inputs and outputs of the core circuitry also connects together the scan distributor and collector circuitry in each core. This can provide a hierarchy of scan circuitry and reduce the need for separate test interconnects and multiplexers.

Scan response reuse method and apparatus

The disclosure describes a novel method and apparatus for allowing response data output from the scan outputs of a circuit under test to be formatted and applied as stimulus data input to the scan inputs of the circuit under test. Also the disclosure described a novel method and apparatus for allowing the response data output from the scan outputs of a circuit under test to be formatted and used as expected data to compare against the response data output from the circuit under test. Additional embodiments are also provided and described in the disclosure.

Scan topology discovery in target systems

Topology discovery of a target system having a plurality of components coupled with a scan topology may be performed by driving a low logic value on the data input signal and a data output signal of the scan topology. An input data value and an output data value for each of the plurality of components is sampled and recorded. A low logic value is then scanned through the scan path and recorded at each component. The scan topology may be determined based on the recorded data values and the recorded scan values.

Adapting scan-bist architectures for low power operation

A Scan-BIST architecture is adapted into a low power Scan-BIST architecture. A generator 102, compactor 106, and controller 110 remain the same as in the known art. The changes between the known art Scan-BIST architecture and the low power Scan-BIST architecture involve modification of the known scan path into scan path 502, to insert scan paths A 506, B 508 and C 510, and the insertion of an adaptor circuit 504 in the control path 114 between controller 110 and scan path 502.

System and method for sharing a communications link between multiple communications protocols

A system and method for sharing a communications link between multiple protocols is described. A system includes a communications interface configured to exchange information with other systems using at least one of a plurality of protocols; a protocol select register that stores a value that selects a protocol from among the plurality of protocols to become an active protocol; and a state machine accessible to the communications interface, the state machine used to control the exchange of information through the communications interface according to the active protocol. The active protocol is used by the communications interface to exchange information while the remaining protocols of the plurality of protocols remain inactive. The state machine sequences through a series of states that cause the communications interface to operate according to the active protocol, and that are designated as inert sequences under the remaining protocols.

SCAN TESTING USING SCAN FRAMES WITH EMBEDDED COMMANDS

Testing of integrated circuits is achieved by a test architecture utilizing a scan frame input shift register, a scan frame output shift register, a test controller, and a test interface comprising a scan input, a scan clock, a test enable, and a scan output. Scan frames input to the scan frame input shift register contain a test stimulus data section and a test command section. Scan frames output from the scan frame output shift register contain a test response data section and, optionally, a section for outputting other data. The command section of the input scan frame controls the test architecture to execute a desired test operation. 1. Controller circuitry comprising:A. state machine circuitry having a command input, a frame marker input, a scan clock input, a test enable input, a clock 2 enable output, a parallel scan enable output, and a serial scan enable output;B. first gate circuitry having a first input connected to clock 2 enable output, a second input connected to the scan clock input, and a clock 2 output; andC. second gate circuitry having a first input connected to the scan clock input, a second input connected to the test enable input, and a clock 1 output.2. The controller circuitry of including a command lead connected to the command input and a command output of a flip-flop.3. The controller circuitry of including a frame marker lead connected to the frame marker input and a frame marker output of a flip-flop.4. The controller circuitry of in which the controller circuitry is included in an integrated circuit and a scan clock lead extends from the scan clock input onto the integrated circuit.5. The controller circuitry of in which the controller circuitry is included in an integrated circuit and a test enable lead extends from the test enable input onto the integrated circuit.6. The controller of including scan circuitry and a clock 1 lead connected from the clock 1 output to the scan circuitry.7. The controller of including scan circuitry and a ...

Path-based crosstalk fault test scanning in built-in self-testing

A path-based crosstalk fault model is used in conjunction with a built-in self-test (BIST) and software capability for automatic test pattern generation. The solution allows for test patterns to be generated that maximize switching activity as well as inductive and capacitive crosstalk. The path based fault model targets the accumulative effect of crosstalk along a particular net (“victim” path), as compared with the discrete nets used in conventional fault models. The BIST solution allows for full controllability of the target paths and any associated aggressors. The BIST combined with automatic test pattern generation software enables defect detection and silicon validation of delay defects on long parallel nets.

Adapting scan architectures for low power operation

Scan architectures are commonly used to test digital circuitry in integrated circuits. The present disclosure describes a method of adapting conventional scan architectures into a low power scan architecture. The low power scan architecture maintains the test time of conventional scan architectures, while requiring significantly less operational power than conventional scan architectures. The low power scan architecture is advantageous to IC/die manufacturers since it allows a larger number of circuits (such as DSP or CPU core circuits) embedded in an IC/die to be tested in parallel without consuming too much power within the IC/die. Since the low power scan architecture reduces test power consumption, it is possible to simultaneously test more die on a wafer than previously possible using conventional scan architectures. This allows wafer test times to be reduced which reduces the manufacturing cost of each die on the wafer.

BLOCKING THE EFFECTS OF SCAN CHAIN TESTING UPON A CHANGE IN SCAN CHAIN TOPOLOGY

A system comprises a plurality of components, scan chain selection logic coupled to the components, and override selection logic coupled to the scan chain selection logic. The scan chain selection logic selects various of the components to be members of a scan chain under the direction of a host computer. The override selection logic detects a change in the scan chain and, as a result, blocks the entire scan chain from progressing. 1. A system on a chip comprising:A. a communications link including a serial test data in lead and a serial test data out lead;B. a port coupled to the communications link including the serial test data in lead and the serial test data out lead, and having a chip serial test data in lead, a chip serial test data out lead, a first select output lead, and a second select output lead;C. a first component separate from the port, the first component including a first embedded TAP controller, the first component having a test data input coupled to the chip serial test data in lead, a first component serial test data output lead, and a first override output lead;D. first multiplexer circuitry having a first input coupled to the chip serial test data in lead, a second input coupled to the first component serial test data output, an output, and a control input;E. first gating circuitry having a first input connected to the first select output lead, a second input connected to the first override output lead, and an output connected to the control input of the multiplexer circuitry;C. a second component separate from the port and first component, the second component including a second embedded TAP controller, the second component having a test data input coupled to the output of the first multiplexer circuitry, a second component serial test data output lead, and a second override output lead;D. second multiplexer circuitry having a first input coupled to output of the first multiplexer circuitry, a second input coupled to the second component ...

Scan topology discovery in target systems

Topology discovery of a target system having a plurality of components coupled with a scan topology may be performed by driving a low logic value on the data input signal and a data output signal of the scan topology. An input data value and an output data value for each of the plurality of components is sampled and recorded. A low logic value is then scanned through the scan path and recorded at each component. The scan topology may be determined based on the recorded data values and the recorded scan values.

Mixed-Signal Integrated Circuit

A mixed-signal integrated circuit includes an analog circuit comprising at least one digital block embedded in the analog circuit, the at least one digital block comprising a plurality of functional bits and a plurality of configuration bits, the plurality of functional bits providing for a functionality of the analog circuit according to a designed functionality and the plurality of configuration bits being usable for configuring a plurality of operational modes of the analog circuit; and a digital circuit comprising a scan chain configured to scan at least part of the functional bits of the digital block embedded in the analog circuit with respect to the designed functionality, wherein the scan chain is further configured to set at least part of the configuration bits of the digital block embedded in the analog circuit according to a selected operational mode of the plurality of operational modes of the analog circuit.

SEMICONDUCTOR DEVICE, ELECTRONIC DEVICE, AND SELF-DIAGNOSIS METHOD FOR SEMICONDUCTOR DEVICE

A semiconductor device addresses to a problem in which a current consumption variation rate increases during BIST execution causing resonance noise generation in a power supply line. The semiconductor device includes a self-diagnosis control circuit, a scan target circuit including a combinational circuit and a scan flip-flop, and an electrically rewritable non-volatile memory. A scan chain is configured by coupling a plurality of the scan flip-flops. In accordance with parameters stored in the non-volatile memory, the self-diagnosis control circuit can change a length of at least one of a scan-in period, a scan-out period and a capture period, and can also change a scan start timing. 111-. (canceled)12. An electronic device , comprising:a first semiconductor device;a second semiconductor device;a power supply circuit; anda passive element,wherein the first and second semiconductor devices each include a self-diagnosis control circuit, a scan target circuit, and an electrically rewritable non-volatile memory, the scan target circuit including a plurality of scan flip-flops and a selector for switching between outputs of the scan flip-flops,wherein, in each of the first and second semiconductor devices, the scan flip-flops are coupled to configure a scan chain, andwherein the self-diagnosis control circuit controls the selector in accordance with data stored in the non-volatile memory such that the first and second semiconductor devices have a same scan chain configuration and such that the first and second semiconductor devices start scanning at different times.13. The electronic device according to claim 12 , a supply voltage monitoring A/D conversion circuit; and', 'a communication circuit,, 'wherein each of the first and second semiconductor devices includeswherein the supply voltage monitoring A/D conversion circuit monitors the supply voltage during a scan test,wherein the second semiconductor device transfers supply voltage variation data to the first ...

COMMON TEST BOARD, IP EVALUATION BOARD, AND SEMICONDUCTOR DEVICE TEST METHOD

According to one embodiment, there is provided a common test board including a socket board, an IP evaluation board, and a common board. To the socket board, a semiconductor device is to be connected. On the IP evaluation board, the socket board is able to be attached. On the common board, the IP evaluation board is able to be attached. 1. A common test board comprising:a socket board to which a semiconductor device is to be connected;an IP evaluation board on which the socket board is able to be attached; anda common board on which the IP evaluation board is able to be attached.2. The common test board according to claim 1 , wherein the socket board is able to be attached on the common board without the IP evaluation board therebetween.3. The common test board according to claim 1 , whereinthe socket board includes:a socket to which the semiconductor device is connected; anda first interface electrically connected to the socket and including a first connector.4. The common test board according to claim 3 , whereinthe common board includes:a common interface on which different IP evaluation board used to evaluate different IP function block is able to be attached; anda common test circuit electrically connected to the common interface, and able to generate any of signals of a quality determination test, an IP evaluation test, and an actual apparatus test, the quality determination test being a test to determine quality of the semiconductor device, the IP evaluation test being a test to evaluate a IP function block implemented on the semiconductor device, the actual apparatus test being a test to check whether the semiconductor device can exert required performance in an actual apparatus.5. The common test board according to claim 4 , wherein the common interface is an interface on which the socket board with different specification is able to be attached.6. The common test board according to claim 4 , whereinthe IP evaluation board includes:an evaluation signal ...

REGISTER ARRAY HAVING GROUPS OF LATCHES WITH SINGLE TEST LATCH TESTABLE IN SINGLE PASS

A register array includes a plurality of groups of latches. Each of the groups of latches includes a first latch, a second latch, and a test latch connected to the first latch and the second latch. During functional operation the first latch and the second latch process data, in response to the same read/write clock signal supplied simultaneously to the first read/write clock input and the second read/write clock input. During test operation a skewed test clock signal of an original test clock signal is supplied at different timings to the first latch, the second latch, and the test latch, and a single scan signal is input to the first latch. The single scan signal cascades from the first latch through the test latch to the second latch, and is output by the second latch, within a single cycle of the original test clock signal. 1. A register array comprising: a first latch;', 'a second latch; and', 'a test latch connected to the first latch and the second latch,, 'a plurality of groups of latches, each of the groups of latches comprisesduring functional operation the first latch and the second latch process data, in response to the same read/write clock signal, and a skewed test clock signal of an original test clock signal is supplied at different timings to the first latch, the second latch, and the test latch;', 'a single scan signal is input to the first latch; and', 'the first latch and the second latch are connected to the test latch to cause the single scan signal to cascade from the first latch through the test latch to the second latch, and be output by the second latch, to use a single test clock and the single scan signal to test both the first latch and the second latch within a single cycle of the original test clock signal., 'during test operation2. The register array according to claim 1 , the first latch and the second latch are physically symmetrical.3. The register array according to claim 1 , the first latch and the second latch each comprise a ...

THREE-DIMENSIONAL PROCESSING SYSTEM HAVING AT LEAST ONE LAYER WITH CIRCUITRY DEDICATED TO SCAN TESTING AND SYSTEM STATE CHECKPOINTING OF OTHER SYSTEM LAYERS

Three-dimensional processing systems are provided having one or more layers with circuitry that is dedicated to scanning and testing of other system layers, and which enables dynamic checkpointing, fast context switching and fast recovery of system state. For example, a semiconductor device includes a first chip and a second chip, which are physically conjoined to form a stacked structure. The first chip includes functional circuitry. The functional circuitry includes a plurality of scan cells such as scanable flip-flop and latches. The second chip includes scan testing circuitry, and a scan testing I/O (input/output) interface. The scan cells of the first chip are connected to the scan testing I/O interface of the second chip. The scan testing circuitry on the second chip operates to dynamically configure electrical connections between the scan cells on the first chip to form scan chains or scan rings for testing portions of the functional circuitry on the first chip. 1. A semiconductor device , comprising:a first chip and a second chip, which are physically conjoined to form a stacked structure;the first chip comprising functional circuitry, the functional circuitry including a plurality of scan cells comprising scanable flip-flop and latches;the second chip comprising scan testing circuitry, and a scan testing I/O (input/output) interface, wherein the scan cells of the first chip are connected to the scan testing I/O interface, and wherein the scan testing circuitry on the second chip operates to dynamically configure electrical connections between the scan cells on the first chip to form scan chains or scan rings for testing portions of the functional circuitry.2. The semiconductor device of claim 1 , wherein the first chip is a processor chip.3. The semiconductor device of claim 1 , wherein the first chip is a memory chip.4. The semiconductor device of claim 1 , wherein the scan testing circuitry on the second chip comprises:demultiplexer circuits;multiplexer ...

COMPRESSED SCAN CHAIN DIAGNOSIS BY INTERNAL CHAIN OBSERVATION, PROCESSES, CIRCUITS, DEVICES AND SYSTEMS

Electronic scan circuitry includes a decompressor (), a plurality of scan chains () fed by the decompressor (), a scan circuit () coupled to the plurality of scan chains () to scan them in and out, a masking circuit () fed by the scan chains (), and a scannable masking qualification circuit () coupled to the masking circuit (), the masking qualification circuit () scannable by scan-in of bits by the decompressor () along with scan-in of the scan chains (), and the scannable masking qualification circuit () operable to hold such scanned-in bits upon scan-out of the scan chains through the masking circuit (). Other scan circuitry, processes, circuits, devices and systems are also disclosed. 1. Electronic scan circuitry comprising:a decompressor;a plurality of scan chains fed by the decompressor;a scan circuit coupled to the plurality of scan chains to scan them in and out;a masking circuit fed by the scan chains;a scannable masking qualification circuit coupled to the masking circuit, the masking qualification circuit scannable by scan-in of bits by the decompressor along with scan-in of the scan chains, and the scannable masking qualification circuit operable to hold such scanned-in bits upon scan-out of the scan chains through the masking circuit; andbit-field decoders wherein the scannable masking qualification circuit has a shift register fed by the decompressor and including sets of shift register cells, each set operable to couple a bit-field to a corresponding one of the bit-field decoders, each one such decoder having a decode output coupled to the masking circuit to independently select at least one scan chain for qualification in a distinct respective group among the scan chains for each one such decoder corresponding to each such set of shift register cells in the shift register.2. The electronic scan circuitry of in which each set of shift register cells is operable to couple a bit-field to a corresponding one of the bit-field decoders equal to a binary ...

Adapting scan architectures for low power operation

Scan architectures are commonly used to test digital circuitry in integrated circuits. The present disclosure describes a method of adapting conventional scan architectures into a low power scan architecture. The low power scan architecture maintains the test time of conventional scan architectures, while requiring significantly less operational power than conventional scan architectures. The low power scan architecture is advantageous to IC/die manufacturers since it allows a larger number of circuits (such as DSP or CPU core circuits) embedded in an IC/die to be tested in parallel without consuming too much power within the IC/die. Since the low power scan architecture reduces test power consumption, it is possible to simultaneously test more die on a wafer than previously possible using conventional scan architectures. This allows wafer test times to be reduced which reduces the manufacturing cost of each die on the wafer.

OPTIMIZATION OF A STORAGE SYSTEM CONTAINING ECC AND SCRAMBLE ENGINES

A method for selecting the scrambling and descrambling data transmitted in a storage system containing ECC and scramble engines with a seed table is disclosed and the steps comprises: encoding a data sent from a HOST interface by an ECC encoding engine and transmitting the data to a LFSR scramble engine; scrambling the data by the LFSR scramble engine and transmitting to a storage device; creating a seed value and transmitting the seed value to a seed table by the LFSR scramble engine; receiving the seed value from the seed table and the scrambled data from the storage device by a LFSR descramble engine, and descrambling the scrambled data based on the seed value and transmitting to an ECC decoding engine; and decoding the descrambled data received from the LFSR descramble engine and then acquiring the original data sent from the HOST interface. 1. A method for selecting the scrambling and descrambling data transmitted in a storage system containing ECC and scramble engines with a seed table , the steps comprising:{'b': '1', 'step S: encoding a data sent from a HOST interface by an ECC encoding engine and transmitting the data to a LFSR scramble engine;'}{'b': '2', 'step S: scrambling the data by the LFSR scramble engine and transmitting to a storage device;'}{'b': '3', 'step S: creating a seed value and transmitting the seed value to a seed table by the LFSR scramble engine;'}{'b': '4', 'step S: receiving the seed value from the seed table and the scrambled data from the storage device by a LFSR descramble engine, and descrambling the scrambled data based on the seed value and transmitting to an ECC decoding engine; and'}{'b': '5', 'step S: decoding the descrambled data received from the LFSR descramble engine and then acquiring the original data sent from the HOST interface.'}2. The method as claimed in claim 1 , wherein the ECC decoding engine decodes the data every X2 bytes claim 1 , saving the seed value of every beginning of X2 bytes or times of X2 bytes get ...

SCAN TESTING SYSTEM, METHOD AND APPARATUS

Test circuits located on semiconductor die enable a tester to test a plurality of die/ICs in parallel by inputting both stimulus and response patterns to the plurality of die/ICs. The response patterns from the tester are input to the test circuits along with the output response of the die/IC to be compared. Also disclosed is the use of a response signal encoding scheme whereby the tester transmits response test commands to the test circuits, using a single signal per test circuit, to perform: (1) a compare die/IC output against an expected logic high, (2) a compare die/IC output against an expected logic low, and (3) a mask compare operation. The use of the signal encoding scheme allows functional testing of die and ICs since all response test commands (i.e. 1-3 above) required at each die/IC output can be transmitted to each die/IC output using only a single tester signal connection per die/IC output. In addition to functional testing, scan testing of die and ICs is also possible. 1. An integrated circuit comprising:A. input pads and output pads;B. core circuitry having inputs coupled to the input pads and outputs coupled to the output pads, the core circuitry including a first core output coupled to a first output pad, and the core circuitry including a second core output coupled to a second output pad;C. first comparator circuitry having an input coupled to the first core output, an expected data input coupled to the first output pad, a mask data input coupled to a third output pad, a compare strobe input coupled to a compare strobe lead, a scan data input, a scan data output, and a scan control input coupled to a scan control lead; andD. second comparator circuitry having an input coupled to the second core output, an expected data input coupled to the second output pad, a mask data input coupled to a fourth output pad, a compare strobe input coupled to the compare strobe lead, a scan data input coupled to the scan data output of the first comparator circuitry, ...

FLEXIBLE ISOMETRIC DECOMPRESSOR ARCHITECTURE FOR TEST COMPRESSION

A system for testing a circuit comprises scan chains, a controller, and hold-toggle circuitry. The hold-toggle circuitry is configured to allow, according to a control signal generated by the controller, some scan chains in the scan chains to operate in a full-toggle mode and some other scan chains in the scan chains to operate in a hold-toggle mode when a test pattern is being shifted into the scan chains. The control signal also contains information of a hold-toggle pattern for the scan chains operating in the hold-toggle mode. The hold-toggle pattern repeats multiple times when the test pattern is being shifted into the scan chains. 1. A system for testing a circuit , comprising:scan chains comprising scan cells, the scan chains configured, in a test mode, to shift in test patterns, apply the test patterns to the circuit, capture test responses of the circuit, and shift out the test responses;a controller comprising first storage circuitry, second storage circuitry, and a control signal generator, the first storage circuitry comprising circuitry configured to store operational mode information, the second storage circuitry comprising circuitry configured to store information of a hold-toggle pattern, and the control signal generator configured to generate a control signal based on the operational mode information and the hold-toggle pattern, wherein the operational mode information determines whether a scan chain operates in a full-toggle mode or in a hold-toggle mode during a shift period, the hold-toggle pattern determines in which shift clock cycles in a segment of consecutive shift clock cycles scan chains operating in the hold-toggle mode receive bits based on corresponding bits of a test pattern during the shift period, and the hold-toggle pattern repeats multiple times during the shift period, the shift period being a period when the test pattern is being shifted into the scan chains; andhold-toggle circuitry coupled to the controller and configured to ...

POWER SUPPLY MONITOR FOR DETECTING FAULTS DURING SCAN TESTING

Some embodiments of a power supply monitor include a measurement circuit to measure a voltage provided to the power supply monitor, a comparator to compare the voltage to a predetermined voltage threshold, and an interface to provide, during a scan test of a processing device including the power supply monitor, a fault signal in response to the voltage being below the voltage threshold. Some embodiments of a method include providing a first test pattern to one or more power supply monitors associated with one or more circuit blocks in the processing device and capturing a first result generated by the power supply monitor(s) based on the first test pattern. The first result indicates whether a voltage provided to the circuit block(s) is below a voltage threshold. 1. A power supply monitor , comprising:a measurement circuit to measure a voltage provided to the power supply monitor;a comparator to compare the voltage to a predetermined voltage threshold; andan interface to provide, during a scan test of a processing device including the power supply monitor, a fault signal in response to the voltage being below the voltage threshold.2. The power supply monitor of claim 1 , wherein the predetermined voltage threshold corresponds to a reduced speed of at least one circuit block that produces a fault in response to a test pattern provided to said at least one circuit block.3. The power supply monitor of claim 1 , comprising a test interface for receiving a test pattern and providing test results in response to the test pattern claim 1 , wherein the test pattern is used to configure the power supply monitor to measure the voltage after receiving a capture clock pulse generated by a test circuit.4. The power supply monitor of claim 1 , wherein the measurement circuit comprises a ring oscillator and at least one counter to count a number of stage transitions or ring oscillator revolutions during a measurement period claim 1 , the number of stage transitions or ring ...

METHOD AND APPARATUS FOR PROVIDING CLOCK SIGNALS FOR A SCAN CHAIN

An integrated circuit device includes a plurality of flip flops configured into a scan chain. The plurality of flip flops includes at least flip flop of a first type and at least one flip flop of a second type. A method includes generating a first scan clock signal for loading scan data into at least one flip flop of a first type, generating a second scan clock signal and a third scan clock signal for loading the scan data into at least one flip flop of a second type, and loading a test pattern into a scan chain defined by the at least flip flop of the first type and the at least one flip flop of the second type responsive to the first, second, and third scan clock signals. 1. An integrated circuit device , comprising:a plurality of flip flops configured into a scan chain, wherein the plurality of flip flops includes at least flip flop of a first type and at least one flip flop of a second type.2. The device of claim 1 , wherein the first type comprises a multiplexer data flip flop and the second type comprises a level-sensitive scan design flip-flop.3. The device of claim 2 , further comprising:logic to provide a first scan clock signal to the multiplexer data flip flop for loading scan data and second and third scan clock signals to the level-sensitive scan design flip-flop for loading the scan data, wherein the second and third scan clock signals are non-overlapping.4. The device of claim 3 , wherein the logic is to generate the second scan clock signal from a first external scan clock signal and generate the first and third scan clock signals from a second external scan clock signal claim 3 , wherein the first and second external clock signals are received by the integrated circuit device.5. The device of claim 4 , further comprising:at least one clock distribution tree to distribute a common clock signal and the first external scan clock signal; anda multiplexer coupled to the clock distribution tree and to select one of a functional clock signal for operating ...

Wafer scale testing using a 2 signal jtag interface

Testing of die on wafer is achieved by; (1) providing a tester with the capability of externally communicating JTAG test signals using simultaneously bidirectional transceiver circuitry, (2) providing die on wafer with the capability of externally communicating JTAG test signals using simultaneously bidirectional transceiver circuity, and (3) providing a connectivity mechanism between the bidirectional transceiver circuitry's of the tester and a selected group or all of the die on wafer for communication of the JTAG signals.

DEBUG SUPPORT DEVICE, DEBUG SUPPORT METHOD, AND COMPUTER READABLE STORAGE MEDIUM

A debug support device includes: a root device extraction unit that extracts, from a sequence program that includes a circuit block including a plurality of devices, a result device on the basis of an association between a factor device that contributes to determination of a value of another device and the result device having the value determined by the factor device; a related device retrieval unit that retrieves, as a related device, each and every one of the factor device(s) that determines the value of the result device; and a display control unit that outputs group information to a display device. The group information is information on a group, associating the result device, the value of the result device, the related device, and a value of the related device. 1. A debug support device comprising:a processor; anda memory to store a program which, when executed by the processor, performs processes of:extracting, from a sequence program that includes a circuit block each including a plurality of devices, a result device on the basis of an association between a factor device that contributes to determination of a value of another device and the result device a value of which is determined by the factor device;retrieving, as a related device, each and every one of the factor device(s) that determines a value of the result device; andoutputting group information to a display device, the group information being information on a group and associating the result device, a value of the result device, the related device, and a value of the related device, whereinthe processor extracts, from among a plurality of the result devices, a root device that does not behave as a factor device for each and every one of the plurality of the result devices in the sequence program,the processor retrieves, as the related device, the each and every one of the plurality of the factor devices that determines a value of the root device, andthe root device, a value of the root device, ...

Bidirectional scan cells for single-path reversible scan chains

A circuit comprises a plurality of scan chains. The plurality of scan chains comprises bidirectional scan cells. Each of the bidirectional scan cells comprises two serial input-output ports serving as either a serial data input port or a serial data output port based on a control signal. Each of the plurality of scan chains is configured to perform a shift operation in either a first direction or a second direction based on the control signal. The first direction is opposite to the second direction.

GATING TAP REGISTER CONTROL BUS AND AUXILIARY/WRAPPER TEST BUS

In a first embodiment a TAP of IEEE standard 1149.1 is allowed to commandeer control from a WSP of IEEE standard P1500 such that the P1500 architecture, normally controlled by the WSP, is rendered controllable by the TAP. In a second embodiment (1) the TAP and WSP based architectures are merged together such that the sharing of the previously described architectural elements are possible, and (2) the TAP and WSP test interfaces are merged into a single optimized test interface that is operable to perform all operations of each separate test interface. 1. An integrated circuit comprising:(a) a TDI lead, a TDO lead, a TMS lead, and a TCK lead;(b) a test access port controller having inputs connected to the TMS and TCK leads and having a CaptureDR output, a ShiftDR output, and an UpdateDR output;(c) instruction register circuitry having a Mode-2 output and an ATC enable output, the instruction register circuitry including a first gate with a gated CaptureDR input and a Capture-2 output, a second gate having a ShiftDR input coupled to the ShiftDR output and a Shift-2 output, and a third gate with a gated UpdateDR input and an Update-2 output;(d) data register circuitry having a TDI input connected to the TDI lead, a TDO output selectively coupled to the TDO lead, a Mode-2 input coupled to the Mode-2 output, a Clock-2 input coupled to the TCK lead, a Shift-2 input coupled to the Shift-2 output, and an Update-2 input coupled to the Update-2 output; and(e) ATC gating circuitry having an ATC enable input connected to the ATC enable output, a CaptureDR input coupled to the CaptureDR output, a Capture input, and a gated CaptureDR output coupled to the gated CaptureDR input.2. The integrated circuit of in which the Capture input is part of an auxiliary test control bus of leads that includes a Clock lead claim 1 , a Shift lead claim 1 , an Update lead claim 1 , a Transfer lead claim 1 , a Reset lead claim 1 , a Select lead claim 1 , a WSI lead claim 1 , and a WSO lead.3. The ...

CIRCUIT AND METHOD FOR DIAGNOSING SCAN CHAIN FAILURES

A circuit includes a plurality of scan chains arranged in a ring network topology. Each scan chain includes a plurality of scan blocks, each of the plurality of scan blocks including a storage element and a switching device. Each switching device includes a first input configured to receive an output of a storage element in a different scan chain from the scan chain in which the switching device is disposed, and a second input configured to receive one of a function logic signal or a test scan signal. The switching device configured to selectively couple the first input or the second input to an input of the storage element. 1. A circuit , comprising:a plurality of scan chains arranged in a ring network topology, each scan chain including a plurality of scan blocks, each of the plurality of scan blocks including a storage element and a switching device,wherein the storage element comprises a first input for receiving a functional logic signal and a second input for receiving a test scan signal, andwherein the switching device includes a first input configured to receive an output of a storage element in a different scan chain from the scan chain in which the switching device is disposed, a second input configured to receive the test scan signal, and an output coupled to the second input of the storage element.2. The circuit of claim 1 , wherein the storage element is selected from a group consisting of a D flip-flop claim 1 , a JK flip-flop claim 1 , an SR flip-flop and a T3. The circuit of claim 1 , wherein the switching device comprises a multiplexer.4. The circuit of claim 3 , wherein the multiplexer is configured to switch its output in response to a debug signal.5. The circuit of claim 1 , wherein the storage element is configured to switch between receiving the functional logic signal provided to its first input or the output of the switching device provided to its second input in response to a scan enable signal provided to the storage element.6. The circuit ...

SECURING REMOTE ETHERNET ACCESS TO A PROCESSOR AND A REGISTER VIA AN INTERNAL ACCESS PORT OF A NETWORK DEVICE

A network device is provided and operative to secure remote access to an internal component including a processor and/or a register. The network device includes an Ethernet interface, an access port, and a controller. The Ethernet interface receives, from a host device, frames transmitted over an Ethernet network. The access port is physically connected to the internal component and physically inaccessible to the host device. The controller is physically connected to the access port. The controller: accesses the internal component via the access port; based on the frames, determines whether the host device is authorized; if the host device is not authorized, prevent the host device from accessing the processor or the register; and if the host device is authorized, permit the host device, via the Ethernet interface and the access port, to control operation of the processor or change the contents of the register. 1. A network device operative to secure remote access to an internal component of the network device , wherein the internal component includes at least one of a processor or a register , the network device comprising:an Ethernet interface configured to receive one or more Ethernet frames transmitted over an Ethernet network, wherein the one or more Ethernet frames are received from a host device to gain access to the internal component and modify at least one of operation of the processor or contents of the register;a first access port physically connected to the internal component and physically inaccessible to the host device; and if the host device is not authorized, prevent the host device from accessing the at least one of the processor or the register, and', 'if the host device is authorized, permit the host device, via the Ethernet interface and the first access port, to perform at least one of a control operation of the processor or change the contents of the register., 'a controller physically connected to the first access port, the controller being ...

Scan topology discovery in target systems

Topology discovery of a target system having a plurality of components coupled with a scan topology may be performed by driving a low logic value on the data input signal and a data output signal of the scan topology. An input data value and an output data value for each of the plurality of components is sampled and recorded. A low logic value is then scanned through the scan path and recorded at each component. The scan topology may be determined based on the recorded data values and the recorded scan values.

DIRECT SCAN ACCESS JTAG

The present disclosure describes novel methods and apparatuses for directly accessing JTAG Tap domains that exist in a scan path of many serially connected JTAG Tap domains. Direct scan access to a selected Tap domain by a JTAG controller is achieved using auxiliary digital or analog terminals associated with the Tap domain and connected to the JTAG controller. During direct scan access, the auxiliary digital or analog terminals serve as serial data input and serial data output paths between the selected Tap domain and the JTAG controller. 1. An integrated circuit comprising:(a) core circuitry;(b) tap domain circuitry coupled to the core circuitry, the tap domain circuitry including a test data input, a test data output, a test clock input, a test mode select input, and control outputs;(c) auxiliary circuitry separate from the tap domain circuitry, the tap domain circuitry having auxiliary inputs, auxiliary outputs, a control input coupled to the control outputs, and output buffer control outputs; and(d) output buffers, each output buffer having an input coupled to an auxiliary output, a control input coupled to an output buffer control output, and an output.2. The integrated circuit of in which the tap domain circuitry includes:controller circuitry having a clock input coupled to the test clock input, a mode select input coupled to the test mode select input, and control outputs;instruction register circuitry having a data input coupled to the test data input, an instruction data output, an instruction control output, and a control input coupled to the control outputs;data register circuitry having a data input coupled to the test data input, a data register data output, an instruction control input coupled to the instruction control output, and a control input coupled to the control outputs;multiplexer circuitry having an instruction data input coupled to the instruction data output, a data register data input coupled to the data register data output, a control ...

Boundary scan chain for stacked memory

A boundary scan chain for stacked memory. An embodiment of a memory device includes a system element and a memory stack including one or more memory die layers, each memory die layer including input-output (I/O) cells and a boundary scan chain for the I/O cells. A boundary scan chain of a memory die layer includes a scan chain portion for each of the I/O cells, the scan chain portion for an I/O cell including a first scan logic multiplexer a scan logic latch, an input of the scan logic latch being coupled with an output of the first scan logic multiplexer, and a decoder to provide command signals to the boundary scan chain.

Blocking the effects of scan chain testing upon a change in scan chain topology

A system comprises a plurality of components, scan chain selection logic coupled to the components, and override selection logic coupled to the scan chain selection logic. The scan chain selection logic selects various of the components to be members of a scan chain under the direction of a host computer. The override selection logic detects a change in the scan chain and, as a result, blocks the entire scan chain from progressing.

Full Pad Coverage Boundary Scan

An integrated circuit, comprising functional circuitry and testing circuitry. A first set of pads is operable in a first state for communicating testing signals to the testing circuitry and operable in a second state for communicating input/output signals to the functional circuitry. A second set of pads, differing from the first set of pads, is operable in the second state for communicating testing signals to the testing circuitry for testing signals associated in the second state with the first set of pads. 112-. (canceled)13. A method of testing circuit operability , comprising:in a first state, applying a first set of test signals to a first set of pads of an integrated circuit comprising functional circuitry and testing circuitry and for communicating the first set of signals to the testing circuitry; andin a second state, applying a second set of test signals to a second set of pads of an integrated circuit, differing from the first set of pads, and communicating the second set of signals to the testing circuitry for testing signals associated with the first set of pads.14. The method of wherein the testing circuitry comprises a configurable scan chain comprising a plurality of scan cells claim 13 , wherein each cell in the plurality of scan cells is associated with a respective pad in one of the first set of pads and the second set of pads.15. The method of and further comprising:configuring the configurable scan chain in the first state so that a first set of pads communicate testing signals that bypass respective scan cells in the configurable scan chain; andconfiguring the configurable scan chain in the second state so that the second set of pads communicate testing signals that bypass respective scan cells in the configurable scan chain and are for testing boundary cells connected in the second state to respective pads in the first set of pads.16. The method circuit of wherein each scan cell in the plurality of scan cells comprises:a serial register for ...

Apparatus, method, and system for testing ic chip

An apparatus for performing scan test of IC chip includes a shift-frequency searching unit that searches usable shift frequency for a target scan section among at least one scan section each including whole or part of at least one scan pattern inputted to a scan path. When searching usable shift frequency for the target scan section, the shift-frequency searching unit scales shift frequency of the target scan section differently from that of at least one scan section among scan sections shifted before or after the target scan section or sets shift frequency of the target scan section differently from that of the at least one scan section among the scan sections shifted before or after the target scan section, and searches shift frequency with which result of the scan test indicates pass or shift frequency with which result of the scan test indicates fail.

METHOD FOR ALLOCATING ADDRESSES AND CORRESPONDING UNITS

A method includes providing a first and second electronic unit unit, generating a wirelessly transmitted signal for detecting or generating one signal or several signals for detection on a chain of electronic elements, for the first unit, detecting a transmission time of the wirelessly transmitted signal for detection or detecting a first transmission time on a first of the chain, for the second unit, detecting a second value or the transmission time of the wirelessly transmitted signal for detection or detecting a second value or a second transmission time on a second position of the chain that is different from the first position, converting the first value or the transmission time detected for the first unit to a first address for the first unit, and converting the second value or the transmission time detected for the second unit to a second address for the second unit.

SUSPECT RESOLUTION FOR SCAN CHAIN DEFECT DIAGNOSIS

This application discloses a computing system implementing an automatic test pattern generation tool to perform scan chain diagnosis-driven compaction setting. The computing system can perform fault simulation on scan chains in a circuit design describing an integrated circuit, which loads test patterns to the simulated scan chains and unloads test responses from the simulated scan chains. The computing system can determine locations of sensitive bits and locations of unknown bits in each of the scan chains based on the test responses from the simulated scan chains, and generate a configuration for a compactor in the integrated circuit based, at least in part, on the locations of the sensitive bits and the locations of the unknown bits in each of the scan chains, wherein the compactor is configured to compact test responses from the scan chains in the integrated circuit based on the configuration.

SCAN CLOCK GENERATOR AND RELATED METHOD THEREOF

An exemplary scan clock generator for providing a plurality of on-chip scan clocks to a plurality of cells under test includes: a receiving circuit, arranged for receiving an off-chip scan clock; and a clock processing circuit, coupled to the receiving circuit and arranged for generating the on-chip scan clocks according to the received off-chip scan clock; wherein clock edges of the on-chip scan clocks are staggered from each other, and the scan clock generator and the cells under test are set in a same chip. 1. A scan clock generator for providing a plurality of on-chip scan clocks to a plurality of cells under test , comprising:a receiving circuit, for receiving an off-chip scan clock; anda clock processing circuit, coupled to the receiving circuit and arranged for generating the on-chip scan clocks according to the received off-chip scan clock;wherein clock edges of the on-chip scan clocks are staggered from each other, and the scan clock generator and the cells under test are set in a same chip.2. The scan clock generator of claim 1 , wherein the clock processing circuit comprises:a plurality of delay circuits, arranged for delaying the received off-chip scan clock respectively to generate the plurality of on-chip scan clocks.3. The scan clock generator of claim 2 , wherein the clock processing circuit comprises:a controller, coupled to the plurality of delay circuits and arranged for adjusting a delay time of each delay circuit.4. The scan clock generator of claim 1 , wherein the clock processing circuit comprises:a delay circuit, arranged for delaying the received off-chip scan clock to generate the plurality of on-chip scan clocks respectively, wherein the delay circuit comprises a plurality of serially connected delay elements.5. The scan clock generator of claim 4 , wherein the clock processing circuit further comprises:a controller, coupled to the plurality of delay elements and arranged for adjusting a delay time of each delay element.6. The scan clock ...

Boundary scan path method and system with functional and non-functional scan cell memories

An integrated circuit or circuit board includes functional circuitry and a scan path. The scan path includes a test data input lead, a test data output lead, a multiplexer, and scan cells. A dedicated scan cell has a functional data output separate from a test data output. Shared scan cells each have a combined output for functional data and test data. The shared scan cells are coupled in series. The test data input of the first shared scan cell is connected to the test data output of the dedicated scan cell. The combined output of one shared scan cell is coupled to the test data input lead of another shared scan cell. The multiplexer has an input coupled to the test data output, an input connected to the combined output lead of the last shared scan cell in the series, and an output connected in the scan path.

SCAN TESTING SYSTEM, METHOD AND APPARATUS

Test circuits located on semiconductor die enable a tester to test a plurality of die/ICs in parallel by inputting both stimulus and response patterns to the plurality of die/ICs. The response patterns from the tester are input to the test circuits along with the output response of the die/IC to be compared. Also disclosed is the use of a response signal encoding scheme whereby the tester transmits response test commands to the test circuits, using a single signal per test circuit, to perform: (1) a compare die/IC output against an expected logic high, (2) a compare die/IC output against an expected logic low, and (3) a mask compare operation. The use of the signal encoding scheme allows functional testing of die and ICs since all response test commands (i.e. 1-3 above) required at each die/IC output can be transmitted to each die/IC output using only a single tester signal connection per die/IC output. In addition to functional testing, scan testing of die and ICs is also possible. 1. An integrated circuit die comprising:(a) die input and output pads including a first die input pad and a second die input pad; i. a first core input coupled to the first die input pad, a first core output, a second core input coupled to the second die input pad, and a second core output;', 'ii. a first scan path having a first scan path input coupled to the first core input and a first scan path output coupled to the first core output;', 'iii. a second scan path having a second scan path input coupled to the second core input and a second scan path output coupled to the second core output', 'iv. a first test circuit having a first core input coupled to the first core output, a first expected data input coupled to a third die pad, a first mask data input coupled to a fourth die pad, a first scan path input, and a first scan path output;', 'v. a second test circuit having a second core input coupled to the second core output, a second expected data input coupled to a fifth die pad, a ...

DUAL MODE TEST ACCESS PORT METHOD AND APPARATUS

Connection circuitry couples scan test port (STP) circuitry to test access port (TAP) circuitry. The connection circuitry has inputs connected to scan circuitry control output leads from the TAP circuitry, a select input lead, and a clock input lead. The connection circuitry has outputs connected to a scan enable (SE) input lead, a capture select (CS) input lead, and the scan clock (CK) input lead of the STP circuitry. The connection circuitry includes a multiplexer having a control input connected with a clock select lead from the TAP circuitry, an input connected with a functional clock lead, an input connected with the clock input lead, an input connected with a Clock-DR lead from the TAP circuitry, an OFF lead, and an output connected with the scan clock input lead. 1. An integrated circuit comprising:A. a test data in lead, a test data out lead, a test clock lead, and a test mode select lead;B. logic circuitry;C. first scan circuitry coupled to the logic circuitry and having a first serial data output;D. second scan circuitry coupled to the logic circuitry and having a second serial data output;E. controller circuitry having inputs coupled to the test clock lead and to the test mode select lead, and having state outputs indicating states that include a register clock state, a register capture state, and a register update state;F. register circuitry having an input coupled to a state output and having a control output; andG. connection circuitry having a control input connected to the control output of the register circuitry and being coupled to the first serial data output and to the second serial data output, the connection circuitry selectively coupling one of the first serial data output and the second serial data output to the test data out lead.2. The integrated circuit of in which the first register is an instruction register having a serial data input coupled to the test data in lead claim 1 , and control inputs connected to the state outputs.3. The ...

CARRIER-BASED TEST SYSTEM

An example test system includes a test carrier to receive a device to test. The test carrier includes test components to perform at least a structural test on the device. The example test system also includes a slot to receive the test carrier. The slot includes an interface to which the test carrier connects to enable the test carrier to communicate with a system that is part of the test system or external to the test system. 1. A test system comprising:a test carrier to receive a device to test, the test carrier comprising test components to perform at least a structural test on the device; anda slot to receive the test carrier, the slot comprising an interface to which the test carrier connects to enable the test carrier to communicate with a system that is part of the test system or external to the test system.2. The test system of claim 1 , wherein the structural test is for performing component-level testing on the device.3. The test system of claim 1 , wherein the structural test comprises a parametric test.4. The test system of claim 1 , wherein the structural test comprises a scan test.5. The test system of claim 1 , wherein the test components is configured to perform a functional test on the device.6. The test system of claim 5 , wherein the functional test is for performing system-level testing on the device.7. The test system of claim 5 , wherein the functional test comprises providing an input to the device claim 5 , obtaining an output based on the input claim 5 , and determining whether the device has passed the functional test based on the output.8. The test system of claim 1 , further comprising:a printed circuit board (PCB) comprising the test components to perform at least a structural test on the device.9. The test system of claim 1 , further comprising:robotics to move the test carrier into, and out of, the slot.10. The test system of claim 1 , wherein the test carrier is a first test carrier claim 1 , the device is a first device claim 1 , and ...

SEMICONDUCTOR DEVICE

According to one embodiment, a semiconductor device includes: a first scan chain and a second scan chain each including a plurality of cascaded flip-flops; a plurality of power supply lines that supply a power supply voltage to the first and second scan chains, extend in a first direction, and are arranged in a second direction intersecting with the first direction; and a clock control circuit that supplies a first clock to the first scan chain and a second clock to the second scan chain, the second clock having timing different to that of the first clock. The plurality of flip-flops are arranged along the second direction. 1. A semiconductor device comprising:a first scan chain and a second scan chain each including a plurality of cascaded flip-flops;a plurality of power supply lines that supply a power supply voltage to the first and second scan chains, extend in a first direction, and are arranged in a second direction intersecting with the first direction; anda clock control circuit that supplies a first clock to the first scan chain and a second clock to the second scan chain, the second clock having timing different to that of the first clock, whereinthe plurality of flip-flops are arranged along the second direction.2. The semiconductor device according to claim 1 , whereinthe plurality of flip-flops are arranged in such a manner that a maximum of two flip-flops are coupled to one power supply line.3. The semiconductor device according to claim 1 , further comprising:a first interconnect coupled to the plurality of power supply lines in common and extending in the second direction.4. The semiconductor device according to claim 1 , further comprising:a plurality of ground lines that supply a ground voltage to the first and second scan chains, extend in the first direction, and are arranged in the second direction.5. The semiconductor device according to claim 4 , further comprising:a second interconnect coupled to the plurality of ground lines in common and ...

SCAN TESTABLE THROUGH SILICON VIAs

The disclosure describes a novel method and apparatus for testing different types of TSVs in a single die or different types of TSV connections in a stack of die. The testing is facilitated by test circuitry associated with each type of TSV. The test circuitry includes a scan cell adapted for testing TSVs. 1. An integrated circuit comprising:(a) a die having a top surface and a bottom surface;(b) a top contact point on the top surface and a bottom contact point on the bottom surface;(c) a through silicon via in the die having a top end coupled to the top contact point and a bottom end coupled to the bottom contact point;(d) a three state buffer having an input coupled to one of the top contact point and the bottom contact point, an output coupled to one end of the through silicon via, and a control input; and(e) a scan cell having a reference voltage input, a serial data input, a control input, a stimulus output coupled to the output of the three state buffer and the one end of the through silicon via, a response input coupled to the other end of the through silicon via, and a serial data output.2. The integrated circuit of in which the top end of the though silicon via is coupled to the top contact point and the response input claim 1 , the three state buffer input is coupled to the bottom contact point claim 1 , and the three state buffer output is coupled to the bottom end of the through silicon via.3. The integrated circuit of in which the bottom end of the though silicon via is coupled to the bottom contact point and the response input claim 1 , the three state buffer input is coupled to the top contact point claim 1 , and the three state buffer output is coupled to the top end of the through silicon via.4. The integrated circuit of including a switch and a load resistor coupled in series between the response input and ground claim 1 , and the switch includes a load input.5. The integrated circuit of in which the scan cell includes a multiplexer and a flip-flop ...

Processor tap support for remote services

An apparatus can include a circuit board; a processor chip mounted to the circuit board that includes a Test Access Port (TAP); a controller mounted to the circuit board that includes a port operatively coupled to the Test Access Port (TAP) of the processor chip; and a network interface operatively coupled to the controller. Various other apparatuses, systems, methods, etc., are also disclosed.

JTAG BUS COMMUNICATION METHOD AND APPARATUS

The present disclosure describes using the JTAG Tap's TMS and/or TCK terminals as general purpose serial Input/Output (I/O) Manchester coded communication terminals. The Tap's TMS and/or TCK terminal can be used as a serial I/O communication channel between; (1) an IC and an external controller, (2) between a first and second IC, or (3) between a first and second core circuit within an IC. The use of the TMS and/or TCK terminal as serial I/O channels, as described, does not effect the standardized operation of the JTAG Tap, since the TMS and/or TCK I/O operations occur while the Tap is placed in a non-active steady state. 1A. a test data in lead, a test data out lead, a test clock lead, and a test mode select lead;B. test access port circuitry coupled to the test data in lead, the test data out lead, the test clock lead, and the test mode select lead, the test access port circuitry including a data register coupled to the test data in lead and the test data out lead and having parallel connections with other circuitry; andC. TMS communication circuitry having a bi-directional data connection with the test mode select lead and connections with data source circuitry and data destination circuitry that are separate from the other circuitry.. An integrated circuit comprising: This application is a divisional of application Ser. No. 14/102,624, filed Dec. 11, 2013, currently pending;Which was a divisional of application Ser. No. 13/757,361, filed Feb. 1, 2013, now U.S. Pat. No. 8,635,504, issued Jan. 21, 2014;Which was a divisional of application Ser. No. 13/468,173, filed May 10, 2012, now U.S. Pat. No. 8,392,773, issued Mar. 5, 2013;Which was a divisional of application Ser. No. 12/966,136, filed Dec. 13, 2010, now U.S. Pat. No. 8,230,280, issued Jul. 24, 2012;Which was a divisional of application Ser. No. 12/782,129, filed May 18, 2010, now U.S. Pat. No. 7,873,889, issued Jan. 18, 2011;Which was a divisional of application Ser. No. 12/351,510, filed Jan. 9, 2009 now U ...

MEMORY LOOPBACK SYSTEMS AND METHODS

One embodiment of the present disclosure describes a memory system that may include one or more memory devices that may store data. The memory devices may receive command signals to access the stored data as a loopback signal. The memory devices may operate in a normal operational mode, a loopback operational mode, a retrieval operational mode, a non-inverting pass-through operational sub-mode, and an inverting pass-through operational sub-mode. The operational modes facilitate the transmission of the loopback signal for the purpose of monitoring of memory device operations. A selective inversion technique, which uses the operational modes, may protect the loopback signal integrity during transmission. 1. A memory module comprising:a first loopback pin communicatively coupled to a first loopback chain; and a first memory device comprising first storage circuitry; and', 'a second memory device comprising second storage circuitry and coupled in the first loopback chain downstream relative to the first memory device;', the first memory device is configured to generate a first loopback signal based at least in part on the first data; and', 'the second memory device is configured to generate a second loopback signal by inverting the first loopback signal to facilitate monitoring operation of the first memory device when a first output loopback signal generated based at least in part on the second loopback signal is output via the first loopback pin., 'wherein, when first data communicated with the first storage circuitry is targeted by loopback parameters], 'a first plurality of memory devices coupled in series to form the first loopback chain, wherein the first plurality of memory devices comprises2. The memory module of claim 1 , comprising:a data pin communicatively coupled to the first memory device, wherein the data pin is configured to output a data signal indicative of the first data communicated with the first storage circuitry when the first memory device ...

JTAG BUS COMMUNICATION METHOD AND APPARATUS

The present disclosure describes using the JTAG Tap's TMS and/or TCK terminals as general purpose serial Input/Output (I/O) Manchester coded communication terminals. The Tap's TMS and/or TCK terminal can be used as a serial I/O communication channel between; (1) an IC and an external controller, (2) between a first and second IC, or (3) between a first and second core circuit within an IC. The use of the TMS and/or TCK terminal as serial I/O channels, as described, does not effect the standardized operation of the JTAG Tap, since the TMS and/or TCK I/O operations occur while the Tap is placed in a non-active steady state. 1. Communication circuitry comprising:(a) a test data in input, a bi-directional test mode select terminal, a test clock input, and a test data out output;(b) test access port circuitry including test controller circuitry coupled to the test mode select terminal and the test clock input;(c) serial communication circuitry separate from the test access port circuitry, the serial communication circuitry having a register that is serially accessible through the bi-directional test mode select terminal; and(d) gating circuitry operable to enable an access to the serially accessible register selectively in accordance with a sequence of signals input to the bi-directional test mode select terminal.2. The communication circuitry of in which the test access port circuitry includes:an instruction register having an input coupled to the test data in input, control inputs coupled to state outputs of the test controller circuitry, parallel outputs, and a data output;a data register having an input coupled to the test data in input, control inputs coupled to the state outputs, parallel outputs and parallel inputs, and a data output; andmultiplexer circuitry having data inputs coupled to the data outputs of the instruction register and the data register, having a control input coupled to the state outputs, and a data output coupled to the test data out output.3. ...

GATING TAP REGISTER CONTROL BUS AND AUXILIARY/WRAPPER TEST BUS

In a first embodiment a TAP of IEEE standard 1149.1 is allowed to commandeer control from a WSP of IEEE standard P1500 such that the P1500 architecture, normally controlled by the WSP, is rendered controllable by the TAP. In a second embodiment (1) the TAP and WSP based architectures are merged together such that the sharing of the previously described architectural elements are possible, and (2) the TAP and WSP test interfaces are merged into a single optimized test interface that is operable to perform all operations of each separate test interface. 1. An integrated circuit comprising: a serial shift register having an input and an output;', 'a test access port state machine having outputs indicating 16 states;', 'first externally accessible pins coupled to the serial shift register and the state machine, the first externally accessible pins including:, '(a) first test circuitry including(1) a Test Data Input pin;(2) a Test Data Output pin;(3) a Test Mode Select input pin;(4) a Test Clock input pin; and(5) a Test Reset input pin; and,(b) second test circuitry separate from the first test circuitry, the second test circuitry including a second externally accessible pin, the second externally accessible pin being coupled to the first test circuitry and providing additional control of the first test circuitry.2. The integrated circuit of in which the shift register input is coupled to the Test Data Input pin claim 1 , the shift register output is coupled to the Test Data Output pin claim 1 , and the shift register includes a CaptureDR control input coupled to the second externally accessible pin.3. The integrated circuit of in which the shift register input is coupled to the Test Data Input pin claim 1 , the shift register output is coupled to the Test Data Output pin claim 1 , and the shift register includes an ShiftDR input coupled to the second externally accessible pin.4. The integrated circuit of in which the shift register input is coupled to the Test Data ...

COMBINATORIAL SERIAL AND PARALLEL TEST ACCESS PORT SELECTION IN A JTAG INTERFACE

A circuit is for coupling test access port (TAP) signals to a Joint Test Action Group (JTAG) interface in an integrated circuit package. An nTRST pin receives a test reset signal, a TMS pin receives a test mode select signal, a testing test access port (TAP) has a test reset signal input and a test mode select signal input, and a debuging test access port (TAP) has a test reset signal input coupled to the nTRST pin and a test mode select signal input coupled to the TMS pin. An inverter has an input coupled to the nTRST pin and an output coupled to the test reset signal input of the testing TAP, and an AND gate has a first input coupled to the output of the inverter, a second input coupled to the TMS pin, and an output coupled to the test mode select input of the testing TAP. 1. A circuit for coupling test access port (TAP) signals to a Joint Test Action Group (JTAG) interface in an integrated circuit package , the circuit comprising:an nTRST pin configured to receive a test reset signal;a TMS pin configured to receive a test mode select signal;a testing test access port (TAP) having a test reset signal input and a test mode select signal input;a debuging test access port (TAP) having a test reset signal input coupled to the nTRST pin and a test mode select signal input coupled to the TMS pin;an inverter having an input coupled to the nTRST pin and an output coupled to the test reset signal input of the testing TAP; andan AND gate having a first input coupled to the output of the inverter, a second input coupled to the TMS pin, and an output coupled to the test mode select input of the testing TAP.2. The circuit of claim 1 , wherein the testing TAP is selected and the debugging TAP is placed in a reset mode claim 1 , when the test reset signal is asserted and the testing TAP operations are controlled from the test mode select signal.3. The circuit of claim 1 , wherein the debugging TAP is selected and the testing TAP is placed in a reset mode claim 1 , when the test ...

INTEGRATED ELECTRONIC DEVICE HAVING A TEST ARCHITECTURE, AND TEST METHOD THEREOF

An electronic device having a functional portion and a test portion. The test portion includes a boundary scan register formed by a plurality of test cells arranged in the body according to a register sequence, where first test cells are configured to form a serial-to-parallel converter and second test cells are configured to form a parallel-to-serial converter. The test cells are each coupled to a respective data access pin of the device and to a respective input/output point of the functional part and have a first test input and a test output. The boundary scan register defines two test half-paths formed, respectively, by the first test cells and by the second test cells. The first test cells are directly coupled according to a first sub-sequence, and the second test cells are directly coupled according to a second sub-sequence. 1. An electronic device integrated in a semiconductor-based body , the semiconductor-based body having a plurality of data access pins , the electronic device comprising:a functional portion; anda test portion;wherein the functional portion has a plurality of input/output points,wherein the test portion has a boundary scan register, the boundary scan register formed by a plurality of test cells arranged in the semiconductor-based body,wherein the plurality of test cells includes first test cells and second test cells,wherein the first test cells form a serial-to-parallel converter and the second test cells form a parallel-to-serial converter,wherein each of said first and second test cells is coupled to a respective data access pin and to a respective input/output point,wherein each of said first and second test cells has a first test input and a test output,wherein the boundary scan register defines a first test partial-path and a second test partial-path, the first test partial-path including the first test cells and the second test partial-path including the second test cells, andwherein the first test cells are directly coupled in ...

SERIAL COMMUNICATION CONTROL

An apparatus for performing serial data communication with a target device , such as an integrated circuit, utilizes serial transfer circuitry to perform a serial transfer of data to a communication register in the target device and serial retrieval circuitry to retrieve an acknowledge signal indicating whether or not the target device is ready to perform further processing following such a transfer. Delay control circuitry serves to apply a predetermined delay period following the transfer of the serial data via the serial transfer circuitry before initiating the retrieval of the acknowledge signal. This predetermined delay period is controlled in dependence upon the ready status indicated by the acknowledge signals retrieved such that the proportion of acknowledge signals retrieved which indicate an unready status meets a predetermined condition, such as being less than a non-zero predetermined value. The serial communication may take place via JTAG serial scan chains and require moving the controlling state machine between a shift state and a capture state. 1. Apparatus for performing serial communication with a target device , said apparatus comprising:serial transfer circuitry to transfer serial data with said target device; said target device is ready to perform processing; and', 'said target device is unready to perform said processing; and, 'serial retrieval circuitry to retrieve an acknowledge signal from said target device, said serial retrieval circuitry initiating retrieval of said acknowledge signal after a predetermined delay period following said transfer of said serial data, said acknowledge signal indicating a ready status of said target device as one ofdelay control circuitry to control said predetermined delay period applied in dependence upon said ready status of one or more retrieved acknowledge signals.2. Apparatus as claimed in claim 1 , wherein when said acknowledge signal indicates said target device is unready to perform said further ...

Combinatorial serial and parallel test access port selection in a jtag interface

A circuit includes a test data input (TDI) pin receiving a test data input signal, a test data out (TDO) pin outputting a test data output signal, and debugging test access port (TAP) having a test data input coupled to the TDI pin and a bypass register having an input coupled to the test data input of the debugging TAP. A multiplexer has inputs coupled to the TDI pin and the debugging TAP. A testing TAP has a test data input coupled to the output of the multiplexer, and a data register having an input coupled to the test data input of the testing TAP. The multiplexer switches so the test data input signal is selectively coupled to the input of the data register of the testing TAP so the output of the debugging TAP is selectively coupled to the input of the data register of the testing TAP.

PROGRAMMABLE SCAN COMPRESSION

An implementation of a system disclosed herein includes a decompressor logic with the capability to vary a level of decompression of a scanning input signal based on value of compression program bits and a compressor logic to generate a scanning output signal, the compressor logic including a plurality of XOR logics, wherein the output of the plurality of XOR logics is selected based on the compression program bits. 1. An apparatus , comprising:a decompressor logic with the capability to decompress a scanning input signal to generate a decompressed signal; anda plurality of multiplexers to multiplex the decompressed signal based on values of compression program bits onto a plurality of scan chains such that length of the plurality of scan chains traversed by the decompressed signal is determined by the values of the compression program bits.2. The apparatus of claim 1 , further comprising a compressor logic configured to receive output from the plurality of scan chains and to generate a scanning output signal claim 1 , the compressor logic including a plurality of XOR logics claim 1 , wherein the output of the plurality of XOR logics is selected based on the values of the compression program bits.3. The apparatus of claim 2 , wherein the plurality of multiplexers controlling the input to the plurality of scan chains claim 2 , wherein one of the compression program bits is input as a control bit for the one or more of the plurality of multiplexers.4. The apparatus of claim 3 , wherein the compressor logic further comprising one or more AND gates and an input to the one or more AND gates is an output signal from the XOR logics.5. The apparatus of claim 4 , wherein another input to the one or more AND gates is the one of the compression program bits.6. The apparatus of claim 1 , wherein compression program bits include two-bits that allows the level of compression of the scanning input signal at three different levels.7. The apparatus of claim 1 , wherein scan ...

Boundary Scan Test System And Method Thereof

A boundary scan test system and a method thereof are disclosed. In the boundary scan test system, two ends of a first loopback line of each CPU test card are connected to another CPU test card and a boundary scan unit of a DIMM test card, respectively, and two ends of a second loopback line of each CPU test card are connected to boundary scan units of the different DIMM test cards, respectively, so as to generate boundary scan nets. A test control host executes a diagnosis program to select and trigger one of the boundary scan units of each boundary scan net, to output an excitation signal, and make the other boundary scan units receive corresponding response signals, and compare the response signals and corresponding expectation signals in each boundary scan net, so as to output a diagnosis result of each boundary scan net.

Automated test equipment for testing one or more devices under test, method for automated testing of one or more devices under test, and computer program for handling command errors

An automated test equipment for testing one or more devices under test, comprises at least one port processing unit, comprising a high-speed-input-output interface, HSIO, for connecting with at least one of the devices under test, a memory for storing data received by the port processing unit from one or more connected devices under test, and a streaming error detection block, configured to detect a command error in the received data, wherein the port processing unit is configured to, in response to detection of the command error, limit the storing in the memory of data following, in the received data, after the command which is detected to be erroneous. A method and computer program for automated testing of one or more devices under test are also described.

Circuit and Method for Monolithic Stacked Integrated Circuit Testing

A monolithic stacked integrated circuit (IC) is provided with a known-good-layer (KGL) test circuit and a scan segment in one of its layers. The test circuit includes a plurality of inputs, outputs, and multiplexers coupled to the scan segment and to a second layer of the IC. The test circuit further includes a plurality of control elements such that scan testing of the IC may be conducted on a layer-by-layer basis. 1. A monolithic stacked integrated circuit (IC) comprising a known-good-layer (KGL) test circuit and a scan segment in a first layer of the IC , the KGL test circuit comprising:a first test input, coupled to an input of the scan segment, to receive a first scan shift data;a first multiplexer, the first multiplexer having two data inputs, a selection input, and a data output wherein one data input of the first multiplexer is coupled to the first test input and another data input of the first multiplexer is coupled to an output of the scan segment;a first test output, coupled to the data output of the first multiplexer, to send a second scan shift data to a second layer;a second test input, to receive a third scan shift data from the second layer;a second multiplexer, the second multiplexer having two data inputs, a selection input, and a data output wherein one data input of the second multiplexer is coupled to the second test input and another data input of the second multiplexer is coupled to the data output of the first multiplexer;a second test output, coupled to the data output of the second multiplexer, to send a fourth scan shift data;a first control element, coupled to the selection input of the first multiplexer; anda second control element, coupled to the selection input of the second multiplexer.2. The IC of claim 1 , wherein:the first control element is: an input to the first layer or a programmable register in the first layer; andthe second control element is: another input to the first layer or another programmable register in the first ...

CHIP TESTING WITH EXCLUSIVE OR

A system and method of testing a chip is disclosed. The method may include scanning input data into a first scan channel serially connected to a second scan channel. The scan channels may comprise a plurality of scannable latches, configured to scan input data to apply to logic circuits on the chip and to receive outputs from the logic circuits. The method may include outputting a data from the first scan channel to a first rotator. The method may include creating adjustment data using the data from the first scan channel by the rotator and transmitting of the adjustment data to a second XOR on the second scan channel. The method may exclusive or the adjustment data from the first rotator with an output of the first XOR of the second scan channel, wherein the first XOR hashes output data from the scannable latches of the second scan channel. 1. A test structure for testing a chip comprising:a first scan channel and a second scan channel serially connected to the first scan channel;a first rotator to receive a data from the serially connected first scan channel and use the data to create an adjustment data for transmittal to the second scan channel;the second scan channel comprising:a plurality of scannable latches, configured to input an input data to logic circuits on a chip and to receive output data from logic circuits on the chip;a first exclusive or (XOR) to hash output data from the scannable latches;a second XOR to exclusive or the adjustment data from the first rotator with an output of the first exclusive or.2. The system of claim 1 , wherein the first XOR is one of a series of XORs.3. The system of claim 1 , wherein the second XOR is one of a series of XORs.4. The system of claim 1 , wherein the adjustment data modifies the pin the output of the second scan channel is transmitted through.5. The system of claim 1 , further comprising:An output from the second XOR to transmit to a second rotator. This application is a continuation of co-pending U.S. patent ...

TESTING APPARATUS AND TESTING METHOD OF ELECTRONIC DEVICE

A testing apparatus and a testing method of an electronic device are provided. The testing apparatus includes at least two device transfer plates and a testing circuit. The device transfer plates are electrically and respectively connected to corresponding electronic devices and at least two sockets corresponding to the electronic devices. The testing circuit is electrically connected to the device transfer plates respectively through at least two sets of serial signal wire pairs. According to types of the electronic devices, the testing circuit provides a serial signal to one of the device transfer plates through the corresponding serial signal wire pair and receives a response from another one of the device transfer plates through the corresponding serial signal wire pair, so as to test whether an open circuit is occurred to a bus between the electronic devices respectively corresponding to the device transfer plates. 1. A testing apparatus configured to test a bus between at least two electronic devices on a circuit board , the circuit board comprising at least two sockets , the electronic devices being configured to electrically connect the corresponding sockets on the circuit board , respectively , the testing apparatus comprising:at least two device transfer plates electrically connected to the electronic devices corresponding to the device transfer plates and electrically connected to the sockets corresponding to the electronic devices; anda testing circuit electrically connected to the device transfer plates respectively through at least two sets of serial signal wire pairs, wherein the testing circuit, according to types of the electronic devices, provides a serial signal to one of the device transfer plates through the corresponding serial signal wire pair and receives a response from another one of the device transfer plates through the corresponding serial signal wire pair, so as to test whether an open circuit is occurred to the bus between the ...

WAFER SCALE TESTING USING A 2 SIGNAL JTAG INTERFACE

Testing of die on wafer is achieved by; (1) providing a tester with the capability of externally communicating JTAG test signals using simultaneously bidirectional transceiver circuitry, (2) providing die on wafer with the capability of externally communicating JTAG test signals using simultaneously bidirectional transceiver circuitry, and (3) providing a connectivity mechanism between the bidirectional transceiver circuitry's of the tester and a selected group or all of the die on wafer for communication of the JTAG signals. 1. An integrated circuit , comprising:(a) a test clock input pin;(b) a bidirectional test data input/output pin;(c) channel circuitry coupled to the test clock input pin and the bidirectional test data input/output pin and capable to receive a test input pattern that includes a sequence of TDI and TMS values and to output a test output pattern that includes a sequence of TDO values through the bidirectional test data input/output pin, the channel circuitry including:serial-in-parallel-out circuitry capable to shift in the test input pattern serially through the bidirectional test data input/output pin in synchronism with a clock signal received at the test clock input pin, having parallel outputs;register circuitry coupled to the parallel outputs and capable to store a TDI value and a TMS value of the test input pattern, the register circuitry having;TCK output lead;TDI output lead to drive the TDI value in synchronism with a TCK signal output at TCK output lead;TMS output lead to drive the TMS value in synchronism with a TCK signal output at TCK output lead; andTDO input lead,(d) at least one TAP domain coupled to the TDI output lead, TMS output lead, TCK output lead and TDO input lead.2. The integrated circuit of claim 1 , in which the test input pattern includes a first predetermined pattern to reset the at least one TAP domain and the first predetermined pattern has a plurality of TMS values of logic one.3. The integrated circuit of claim 2 ...

SEQUENTIAL CIRCUIT, SCAN CHAIN CIRCUIT INCLUDING THE SAME AND INTEGRATED CIRCUIT INCLUDING THE SAME

A sequential circuit includes a data input terminal, a data path, and a redundant feedback loop. The data input terminal receives input data. The data path is connected to the data input terminal and transmits the input data to a data output terminal based on a first clock signal and a second clock signal. The redundant feedback loop is connected to the first data path and stores first data based on at least one of the first or second clock signals when the first data is equal to second data. The first data corresponds to the input data. The second clock signal is a delayed signal of the first clock signal. The second data is delayed data of the first data. 1. A sequential circuit , comprising:a data input terminal to receive input data;a first data path, connected to the data input terminal, to transmit the input data to a data output terminal based on a first clock signal and a second clock signal; anda redundant feedback loop, connected to the first data path, to store first data based on at least one of the first or second clock signals when the first data is equal to second data, wherein the first data corresponds to the input data, wherein the second clock signal is a delayed signal of the first clock signal, and wherein the second data is delayed data of the first data.2. The sequential circuit as claimed in claim 1 , wherein:the redundant feedback loop includes a first latch connected to a first data node from which the first data is to be provided and a second data node from which the second data is to be provided,the first latch to store the first data based on the second clock signal when the first data is the same as the second data, andthe first data node is on the first data path.3. The sequential circuit as claimed in claim 2 , wherein the first latch includes:a first logic gate including a first input terminal connected to the first data node, a second input terminal connected to the second data node, and an output terminal connected to a first node; ...

INTEGRATED CIRCUIT WITH SECURE SCAN ENABLE

An integrated circuit senses attempts to access security-related data stored in registers connectable into a scan chain when the attempt includes locally and selectively asserting a scan-enable signal at a corresponding branch of the scan-enable tree when the integrated circuit is in a secure functional mode. When such an attempt is detected, the integrated circuit (i) generates a security warning that causes a reset of the security-related data and/or (ii) engages a bypass switch to disconnect the scan chain from the respective output terminal to preclude the security-related data from being shifted out of the IC via the scan chain. 1. An integrated circuit , comprising:a plurality of registers configured to be connected in two or more scan chains for scan-testing the integrated circuit in response to a scan-enable signal being asserted; anda security-warning generator, connected to the two or more scan chains, that asserts a security-warning signal in response to the scan-enable signal being asserted at a first subset of the two or more scan chains,wherein the integrated circuit is configurable to prevent data from being read from at least some of the registers in response to the security-warning signal being asserted by the security-warning generator.2. The integrated circuit of claim 1 , wherein the at least some of said registers are configurable to receive security-related data.3. The integrated circuit of claim 1 , wherein the integrated circuit is automatically configurable to reset the data in the at least some of the registers in response to the security-warning signal being asserted by the security-warning generator.4. The integrated circuit of claim 1 , further comprising a bypass switch connected between an input terminal and an output terminal of a scan chain having at least one of the at least some of the registers claim 1 , wherein the bypass switch is automatically configurable to connect the input terminal and the output terminal to one another to ...

DIRECT SCAN ACCESS JTAG

The present disclosure describes novel methods and apparatuses for directly accessing JTAG Tap domains that exist in a scan path of many serially connected JTAG Tap domains. Direct scan access to a selected Tap domain by a JTAG controller is achieved using auxiliary digital or analog terminals associated with the Tap domain and connected to the JTAG controller. During direct scan access, the auxiliary digital or analog terminals serve as serial data input and serial data output paths between the selected Tap domain and the JTAG controller.

Parallel scan distributors and collectors and process of testing integrated circuits

An integrated circuit ( 70 ) having parallel scan paths ( 824-842, 924-942 ) includes a pair or pairs of scan distributor ( 800,900 ) and scan collector ( 844,944 ) circuits. The scan paths apply stimulus test data to functional circuits ( 702 ) on the integrated circuit and receive response test data from the functional circuits. A scan distributor circuit ( 800 ) receives serial test data from a peripheral bond pad ( 802 ) and distributes it to each parallel scan path. A scan collector circuit ( 844 ) collects test data from the parallel scan paths and applies it to a peripheral bond pad ( 866 ). This enables more parallel scan paths of shorter length to connect to the functional circuits. The scan distributor and collector circuits can be respectively connected in series to provide parallel connections to more parallel scan paths. Additionally multiplexer circuits ( 886,890 ) can selectively connect pairs of scan distributor and collector circuits together. The scan distributor and collector circuits can be formed in core circuits ( 704 ). The core circuits then can be connected to other core circuits and functional circuits with simple connections to the parallel scan circuits through the scan distributor and collector circuits.

Buffer testing for reconfigurable instruction cell arrays

A reconfigurable instruction cell array (RICA) is provided that includes a plurality of master switch boxes that are configured to read and write from a plurality of buffers through a cross-bar switch. A master built-in-self-test (MBIST) engine is configured to drive a test word into the write path of at least one master switch box and to control the cross-bar switch so that the driven test word is broadcast to all the buffers for storage. The MBIST engine is also configured to retrieve the stored test words from the buffers through a read bus within the cross-bar switch.

COMMANDED JTAG TEST ACCESS PORT OPERATIONS

The disclosure describes a novel method and apparatus for improving the operation of a TAP architecture in a device through the use of Command signal inputs to the TAP architecture. In response to a Command signal input, the TAP architecture can perform streamlined and uninterrupted Update, Capture and Shift operation cycles to a target circuit in the device or streamlined and uninterrupted capture and shift operation cycles to a target circuit in the device. The Command signals can be input to the TAP architecture via the devices dedicated TMS or TDI inputs or via a separate CMD input to the device. 1. An integrated circuit comprising:a test data in (TDI) input, a test data out (TDO) output, a test clock in (TCK) input, a test mode select (TMS) input, and a command input; a data register capture input; and', 'a data register shift input;, 'a data register coupled to the TDI input, the TCK input, and the TDO output, the data register including a router enable input;', 'a router capture input;', 'a router shift input;', 'a router capture output coupled to the data register capture input; and', 'a router shift output coupled to the data register shift input;, 'a router coupled to the command input, the router including a state machine shift output coupled to the router shift input; and', 'a state machine capture output coupled to the router capture input; and, 'a state machine coupled to the TMS input and the TCK input, the state machine including 'an enable output coupled to the router enable input.', 'an instruction register including2. The integrated circuit of claim 1 , wherein:the TDI input is a serial input; andthe TDO output is a serial output.3. The integrated circuit of claim 1 , wherein: a first multiplexer including a first multiplexer first input coupled to the command input, a first multiplexer second input coupled to the router capture input, and a first multiplexer output;', 'a second multiplexer including a second multiplexer first inverted input ...

Voltage level monitoring of an integrated circuit for production test and debug

A scan chain collects scan chain data from testing of a functional circuit and outputs a scan chain signal containing the scan chain data. A voltage monitor circuit operates to compare a supply voltage against a threshold and assert a reset signal when the supply voltage crosses the threshold. The reset signal resets a flip flop circuit whose output signal controls operation of a logic circuit that blocks passage of the scan chain signal to an integrated circuit probe pad and instead applies a constant logic signal to the probe pad indicating a voltage monitoring error.

REGULATOR CONTROL DURING SCAN SHIFT AND CAPTURE CYCLES

During scan testing a voltage regulator is programmed to supply a first voltage to logic under test during a shift portion of the scan test, a second voltage during a first portion of a capture portion of the scan test and at least a third voltage during a second portion of the capture portion of the scan test. The availability of a programmable voltage regulator during shift and capture portions of scan testing allows a less stressful voltage to be used during a shift portion of the scan test to reduce shift failures and allows various voltages to be used during capture portions of the scan testing as a surrogate for testing at different temperatures and to provide more flexibility in testing margins. 1. An integrated circuit comprising:a first voltage regulator;a plurality of storage elements configurable into one or more scan chains;a first control circuit configured to supply the first voltage regulator a first value of a regulator control signal to cause the first voltage regulator to supply as a supply voltage a first voltage to the plurality of storage elements during a shift portion of a scan test; andwherein the first control circuit is configured to supply the first voltage regulator a second value of the regulator control signal to cause the first voltage regulator to supply as the supply voltage to the plurality of storage elements a second voltage during a first portion of a capture portion of the scan test and the first control circuit is configured to supply the first voltage regulator a third value of the regulator control signal to cause the first voltage regulator to supply as the supply voltage a third voltage during a second portion of the capture portion of the scan test.2. The integrated circuit as recited in claim 1 , wherein the first voltage is a higher voltage than the second voltage and the third voltage.3. The integrated circuit as recited in claim 1 , further comprising a first clock signal supplied to at least a first portion of the ...

POWER-AWARE SCAN PARTITIONING

Methods of a scan partitioning a circuit are disclosed. One method includes calculating a power score for circuit cells within a circuit design based on physical cell parameters of the circuit cells. For each of the circuit cells, the circuit cell is assigned to a scan group according to the power score for the circuit cell and a total power score for each scan group. A plurality of scan chains is formed. Each of the scan chains is formed from the circuit cells in a corresponding scan group based at least in part on placement data within the circuit design for each of the circuit cells. Interconnect power consumption can be assessed to determine routing among circuit cells in the scan chains. 1. A method of scan partitioning a circuit , the method comprising:calculating a power score for each of a plurality of circuit cells within a circuit design based on one or more physical cell parameters of the plurality of circuit cells used in the circuit design;for each of the plurality of circuit cells, assigning the circuit cell to a scan group from among a plurality of scan groups according to the power score for the circuit cell and a total power score for each scan group; andforming a plurality of scan chains, wherein each of the plurality of scan chains is formed from the circuit cells in a corresponding scan group of the plurality of scan groups based at least in part on placement data within the circuit design for each of the circuit cells included in the corresponding scan group.2. The method of claim 1 , further comprising ordering a plurality of circuit blocks included in a scan chain based at least in part on minimization of an interconnect power score defined by power consumption of interconnects between consecutive flops in the scan chain.3. The method of claim 1 , further comprising:determining whether a power score for the circuit design including the plurality of scan chains, and,based on a determination that the power score is above a threshold, ordering a ...

Semiconductor test system and method

A test controller applies test stimulus signals to the input pads of plural die on a wafer in parallel. The test controller also applies encoded test response signals to the output pads of the plural die in parallel. The encoded test response signals are decoded on the die and compared to core test response signals produced from applying the test stimulus signals to core circuits on the die. The comparison produces pass/fail signals that are loaded in to scan cells of an IEEE 1149.1 scan path. The pass/fail signals then may be scanned out of the die to determine the results of the test.

System, Apparatus And Method For Probeless Field Scan Of A Processor

In one embodiment, a processor includes a scan system controller to control test operations on the processor in response to test commands from an external test entity, and at least one core to execute instructions. The processor may further include a field scan controller to control a field test mode of the processor to perform a self-test of the at least one core during field operation, where the field scan controller is to obtain a test pattern from an external memory and cause the scan system controller to test circuitry of the first subsystem using the test pattern. Other embodiments are described and claimed. 1. A processor comprising:a scan system controller to control test operations on the processor in response to test commands from an external test entity; and a first subsystem having one or more pipelines to execute the instructions; and', 'a second subsystem having a cache memory and a field scan controller to control a field test mode of the processor to perform a self-test of the at least one core during field operation, wherein the field scan controller is to obtain a test pattern from an external memory and cause the scan system controller to test circuitry of the first subsystem using the test pattern., 'at least one core to execute instructions, the at least one core including2. The processor of claim 1 , wherein the field scan controller is to control a core autonomous scan-at-field test mode of the processor.3. The processor of claim 2 , wherein the at least one core further includes a power management agent claim 2 , the power management agent to cause the at least one core to enter into a scan power mode in response to an indication of the scan-at-field test mode from the field scan controller.4. The processor of claim 3 , wherein the power management agent is to cause the at least one core to exit the scan power mode at a conclusion of the scan-at-field test mode and enter into a normal power mode claim 3 , the normal power mode at a lower ...

On-Chip Test Pattern Generation

A chip is provided that includes an integrated circuit including a plurality of logic elements, wherein the plurality of logic elements is configured to form, in a test mode, a plurality of scan chains. The chip further includes an on-chip signal generator connected with the integrated circuit and configured to provide, in the test mode, a test pattern signal to the plurality of scan chains. 1. A chip , comprising:an integrated circuit comprising a plurality of logic elements, wherein the plurality of logic elements is configured to form, in a test mode, a plurality of scan chains, andan on-chip signal generator connected with the integrated circuit and configured to provide, in the test mode, a test pattern signal to the plurality of scan chains.2. The chip of claim 1 ,wherein the on-chip signal generator comprises a linear feedback shift register.3. The chip of claim 1 ,wherein the on-chip signal generator comprises less than 100,000 transistors, preferably less than 1,000 transistors, more preferably less than 500 transistors.4. The chip of claim 1 ,wherein the on-chip signal generator is configured to provide the test pattern signal having a codeword length N,wherein plurality of logic elements is configured to form M scan chains,wherein N is smaller than M, andwherein the chip further comprises a decompressor configured to translate the test pattern signal having the codeword length of N into a decompressed test pattern signal having a codeword length of M.5. The chip of claim 1 ,wherein the on-chip signal generator is configured to provide the test pattern signal having a codeword length of N,wherein the plurality of logic elements is configured to form M scan chains, andwherein N equals M.6. The chip of claim 1 , further comprising:an external clock pin connected with the signal generator and selectively connected with the integrated circuit,wherein the on-chip signal generator is configured to provide different states of the test pattern signal depending on ...

SCAN TESTABLE THROUGH SILICON VIAs

The disclosure describes a novel method and apparatus for testing different types of TSVs in a single die or different types of TSV connections in a stack of die. The testing is facilitated by test circuitry associated with each type of TSV. The test circuitry includes a scan cell adapted for testing TSVs. 1. An integrated circuit comprising:(a) a die having a top surface and a bottom surface;(b) a top contact point on the top surface and a bottom contact point on the bottom surface;(c) a through silicon via in the die having a top end coupled to the top contact point and a bottom end coupled to the bottom contact point;(d) a first switch having a first lead connected to the top contact point, a second lead connected to the top end of the through silicon via, a response lead, and a control input; and(e) a scan cell having a reference voltage input, a serial data input, a control input, a stimulus output coupled to between bottom top contact point and the bottom end of the through silicon via, a response input connected to the response lead, and a serial data output.2. The integrated circuit of in which the bottom end of the though silicon via is connected to the bottom contact point and the stimulus input.3. The integrated circuit of including a switch and a load resistor coupled in series between the response input and ground claim 1 , and the switch includes a load input.4. The integrated circuit of in which the scan cell includes a multiplexer and a flip-flop connected in series between the serial data input and the serial data output. This application is a Divisional of prior application Ser. No. 15/182,817, filed Jun. 15, 2016, currently pending;Which was a divisional of prior application Ser. No. 13/712,459, filed Dec. 12, 2012; now abandoned;And claims priority from Provisional Application No. 61/577,401, filed Dec. 19, 2011.This disclosure is related to pending TI patent TI-71609 which is incorporated herein by reference.This disclosure relates generally to ...

Test access port architecture to facilitate multiple testing modes

A system comprises a testing mode register, a set of pins, and a test access port controller. The test access port controller initiates a first testing mode by configuring the set of pins according to a first pin protocol. The test access port controller configures a first pin to receive first test pattern data based on a first convention and configures a second pin to output first test result data based on the first test pattern data. Based on detecting a register command stored in the testing mode register, the test access port controller initiates a second testing mode by configuring the set of pins according to a second pin protocol. The test access port controller configures the first pin to receive a second test pattern data generated based on a second convention and configures the second pin to output a second test result data based on the second test pattern data.

SYSTEMS AND METHODS FOR BYPASS TESTING

Technology for bypass testing of an integrated circuit using a testing device. The testing device comprising a port configured to connect to an integrated circuit before the integrated circuit is packaged into an end product. The testing device further comprising a controller with architecture configured to bypass a training process designed to be initiated when the integrated circuit is first connected to the port and the port is powered on, confirm a connection between the integrated circuit and the testing device, send a test pattern to the integrated circuit to execute; and receive results from the integrated circuit executing the test pattern. 1. A testing device for testing an integrated circuit , comprising:a port configured to connect to an integrated circuit before the integrated circuit is packaged into an end product; anda controller with architecture configured to:bypass a training process designed to be initiated when the integrated circuit is first connected to the port and the port is powered on;confirm a connection between the integrated circuit and the testing device;send a test pattern to the integrated circuit to execute; andreceive results from the integrated circuit executing the test pattern.2. The testing device as recited in claim 1 , wherein the test pattern comprises a plurality of test patterns.3. The testing device as recited in claim 2 , wherein at least one of the plurality of test patterns is configured to test the training process.4. The testing device as recited in claim 1 , wherein the testing device comprises a plurality of ports for testing a plurality of integrated circuits.5. The testing device as recited in claim 1 , wherein the test pattern is generated by a test access mechanism (TAM) DFx.6. The testing device as recited in claim 1 , wherein the controller is further configured to bypass a plurality of training processes.7. The testing device as recited in claim 1 , wherein the controller is configured to optionally bypass or ...

SEMICONDUCTOR DEVICE, TEST STRUCTURE OF THE SEMICONDUCTOR DEVICE, AND METHOD OF TESTING THE SEMICONDUCTOR DEVICE

A semiconductor device, a test structure of the semiconductor device, and a method of testing the semiconductor device are provided. The test structure including a first pad and a second pad being separated from each other, and a first test element and a second test element connected between the first pad and the second pad, a first value of a characteristic parameter of the first test element being different from a second value of the characteristic parameter of the second test element, may be provided. 1. A test structure of a semiconductor device , the test structure comprising:a first pad and a second pad separate from each other; anda first test element and a second test element connected between the first pad and the second pad, a first value of a characteristic parameter of the first test element being different from a second value of the characteristic parameter of the second test element.2. The test structure of claim 1 , wherein the characteristic parameter includes one of shapes and dispositions of the first test element and the second test element.3. The test structure of claim 1 , wherein the first test element and the second test element form one test element group.4. The test structure of claim 1 , wherein the characteristic parameter includes at least one of a width claim 1 , a space claim 1 , a length claim 1 , a thing to thing (T2T) distance claim 1 , a stagger claim 1 , a line color claim 1 , a via size claim 1 , a via to line end distance claim 1 , a via misalignment claim 1 , a via pitch claim 1 , and a via color.5. The test structure of claim 1 , wherein the first test element is connected to a connection pattern by a first via claim 1 , and the second test element is connected to the connection pattern by a second via different from the first via.6. The test structure of claim 1 , wherein the first value and the second value are randomized values.7. The test structure of claim 1 , wherein the first and second pads and the first and second test ...

SCAN RESPONSE REUSE METHOD AND APPARATUS

The disclosure describes a novel method and apparatus for allowing response data output from the scan outputs of a circuit under test to be formatted and applied as stimulus data input to the scan inputs of the circuit under test. Also the disclosure described a novel method and apparatus for allowing the response data output from the scan outputs of a circuit under test to be formatted and used as expected data to compare against the response data output from the circuit under test. Additional embodiments are also provided and described in the disclosure. 1. An integrated circuit comprising:(a) embedded circuitry including combinational logic and scan paths, the scan paths inputting and applying test stimulus patterns to the combinational logic and capturing and outputting test response patterns from the combinational logic, each scan path having a scan input, and a scan output; i. a first multiplexer circuit having data inputs coupled to the scan outputs, a data output coupled to a first scan input, and m first control inputs; and', 'ii. a second multiplexer circuit having data inputs coupled to the scan outputs, a data output coupled to a second scan input separate from the first scan input, and m second control inputs separate from the m first control inputs; and, '(b) formatter circuitry including(c) interface circuitry having one control bus of m inputs, a write strobe input, an address input; a scan clock input, m first control outputs coupled to the m first control inputs, and m second control outputs coupled to the m second control inputs;(d) in which m is an integer greater than 1.2. The integrated circuit of in which the formatter circuitry is separate from the embedded circuitry.3. The integrated circuit of in which each scan path has a scan enable input and a scan clock input.4. The integrated circuit of including a tester having a write strobe output coupled to the write strobe input claim 1 , an address output coupled to the address input claim 1 , a ...

SERIAL I/O USING JTAG TCK AND TMS SIGNALS

The present disclosure describes a novel method and apparatus of using the JTAG TAP's TMS and TCK terminals as a general purpose serial Input/Output (I/O) bus. According to the present disclosure, the TAP's TMS terminal is used as a clock signal and the TCK terminal is used as a bidirectional data signal to allow serial communication to occur between; (1) an IC and an external controller, (2) between a first and second IC, or (3) between a first and second core circuit within an IC. 1. An integrated circuit comprising:A. functional circuitry;B test data leads including a test data in lead and a test data out lead;C. control leads including a test clock lead, and a test mode select lead; i. first data path circuitry conveying test data to and from the functional circuitry over the test data leads;', 'ii. second data path circuitry conveying test data to and from the functional circuitry over only the control leads; and', 'iii. gating circuitry coupled to the first data path circuitry and the second data path circuitry and selecting the second data path circuitry to convey test data to and from the functional circuitry., 'D. test circuitry coupled to the functional circuitry and coupled to the test data leads and the control leads, the test circuitry including2. The integrated circuit of in which:A. the first data path circuitry includes test access port circuitry having a test data in input coupled to the test data in lead, a test data out output coupled to the test data out lead, a test clock input coupled to the test clock lead, and a test mode select input coupled to the test mode select lead, the test access port having first data connections with the functional circuitry; andB. the second data path circuitry includes a serial communication circuit having data and clock connections with the test clock lead and the test mode select lead, the serial communication circuit having second data connections with the functional circuitry separate from the first data ...

DIAGNOSTIC ENHANCEMENT FOR MULTIPLE INSTANCES OF IDENTICAL STRUCTURES

A method includes executing a test against a first structure and a second structure of a built-in self-test circuit. Each of the first and second structures include a plurality of latches arranged as a plurality of stump chains. The method also includes unloading a first result of the test from the plurality of stump chains of the first structure and a second result of the test from the plurality of stump chains of the second structure. The method further includes determining that the plurality of stump chains of the first structure includes a faulty latch based on the first result not matching the second result. 1. A method comprising:executing a test against a first structure and a second structure of a built-in self-test circuit, each of the first and second structures comprising a plurality of latches arranged as a plurality of stump chains;unloading a first result of the test from the plurality of stump chains of the first structure and a second result of the test from the plurality of stump chains of the second structure; anddetermining that the plurality of stump chains of the first structure includes a faulty latch based on the first result not matching the second result.2. The method of claim 1 , further comprising toggling multiple input signature registers (MISRs) of the first and second structures to operate as shift registers.3. The method of claim 1 , wherein unloading the first and second results comprises:unloading a first stump chain of the first structure and a first stump chain of the second structure;unloading a second stump chain of the first structure and a second stump chain of the second structure after unloading the first stump chain of the first structure and the first stump chain of the second structure.4. The method of claim 1 , wherein unloading the first and second results comprises:unloading, from each stump chain of the plurality of stump chains of the first and second structures, a first latch; andunloading, from each stump chain of ...

TEST DECOMPRESSOR AND TEST METHOD THEREOF

A test decompressor and a test method thereof for converting original input data of one single test input into test vectors for testing a circuit under test (CUT) containing scan chains are revealed. The test decompressor includes a test data spreader, a test configuration switch, and a test controller. The test data spreader converts the original input data into a plurality of test data. The test configuration switch receives the original input data and the plurality of test data and transfers these data to scan chains of the CUT. The test controller receives the original input data and outputs a select signal to the test configuration switch for switching current test configuration to another test configuration. The scan chains in the CUT are divided into several scan groups and the scan chains in each scan group share the same test data. Thus the test data volume can be significantly reduced. 2. The device as claimed in claim 1 , wherein the series of flip-flops includes a number of L flip-flops; the test configuration switch receives the original input data claim 1 , an output of the inverter and a number of 2*L output of the series of flip-flops so that the maximum is a number of 2+2*L inputs.3. The device as claimed in claim 1 , wherein the multiplexers are simplified into an integrated switch logic by logic minimization.4. The device as claimed in claim 1 , wherein the CUT contains a plurality of scan chains that are divided into a plurality of scan groups; the scan chains in the same scan group share and receive the same test vector.5. The device as claimed in claim 1 , wherein the test controller receives a test enable signal that triggers the test controller to start test procedure.6. The device as claimed in claim 1 , wherein the test controller receives a control data that controls switching of the test configuration switch.7. A test method of a test decompressor having a test data spreader claim 1 , a test configuration switch and a test controller ...

DRIVING PERVASIVE COMMANDS USING BREAKPOINTS IN A HARDWARE-ACCELERATED SIMULATION ENVIRONMENT

An aspect includes driving a plurality of commands to an interface unit of a circuit design in a hardware-accelerated simulator to dynamically initialize the circuit design to run one or more test cases based on an initialization sequence with breakpoint support. A state of the circuit design is examined through the interface unit based on triggering of a breakpoint on the hardware-accelerated simulator. A next action to perform in the initialization sequence is determined based on the state of the circuit design as determined through the interface unit. Execution of one or more scripts select the initialization sequence from a plurality of test cases, set the breakpoint, modify a state of the circuit design as the next action to perform, and capture a plurality of test results based on execution of the initialization sequence through the interface unit. 1. A method comprising:driving a plurality of commands to an interface unit of a circuit design in a hardware-accelerated simulator to dynamically initialize the circuit design to run one or more test cases based on an initialization sequence with breakpoint support;examining a state of the circuit design through the interface unit based on triggering of a breakpoint on the hardware-accelerated simulator; anddetermining a next action to perform in the initialization sequence based on the state of the circuit design as determined through the interface unit, wherein a circuit design verification system executes one or more scripts to select the initialization sequence from a plurality of test cases, set the breakpoint, modify a state of the circuit design as the next action to perform, and capture a plurality of test results based on execution of the initialization sequence through the interface unit.2. The method of claim 1 , wherein the interface unit is an alter display unit operable to inspect and modify a plurality of states of a plurality of processing system elements in the circuit design.3. The method of claim ...

METHOD FOR IDENTIFYING A FAULT AT A DEVICE OUTPUT AND SYSTEM THEREFOR

A device comprising includes an output terminal and a first current path from the output terminal to a first reference voltage. The first current path includes a series connection of current electrodes of a first transistor and a second transistor. The first transistor receives at a control electrode a signal to set a desired level of current to be conducted by the first current path. The second transistor generates at a control electrode a feedback signal indicative of an actual current conducted by the first transistor. 1. A device comprising:an output terminal; and a first transistor to receive at a control electrode of the first transistor a signal to set a desired level of current to be conducted by the first current path; and', 'a second transistor to generate at a control electrode of the second transistor a feedback signal indicative of an actual current conducted by the first transistor., 'a first current path from the output terminal to a first reference voltage, the first current path including a series connection of current electrodes of2. The device of claim 1 , further comprising a third transistor that together with the first transistor provides a first current mirror.3. The device of claim 2 , further comprising:a first reference current source to provide a first reference current; anda second current mirror to generate a second reference current based on the first reference current, the second current mirror coupled to a first current electrode and to a control electrode of the third transistor.4. The device of claim 1 , further comprising a third transistor that together with the second transistor provides a second current mirror.5. The device of claim 1 , further comprising a current comparator to compare the actual current conducted by the first transistor claim 1 , as indicated by the feedback signal claim 1 , to a first threshold current and to a second threshold current.6. The device of claim 5 , further comprising control logic coupled to the ...

WAFER SCALE TESTING USING A 2 SIGNAL JTAG INTERFACE

Testing of die on wafer is achieved by; (1) providing a tester with the capability of externally communicating JTAG test signals using simultaneously bidirectional transceiver circuitry, (2) providing die on wafer with the capability of externally communicating JTAG test signals using simultaneously bidirectional transceiver circuitry, and (3) providing a connectivity mechanism between the bidirectional transceiver circuitry's of the tester and a selected group or all of the die on wafer for communication of the JTAG signals. 1. An integrated circuit wafer , comprising: i. combinational logic core circuitry;', 'ii. a test access port (TAP) domain coupled to the combinational logic core circuitry, the test access port domain having a test data input (TDI) input lead, a test mode select (TMS) input lead, a test clock (TCK) input lead, and a test data output (TDO) output lead;', 'iii. scan path circuitry coupled to the combinational logic core circuitry and the test access port domain; and', a. a simultaneous bidirectional transceiver (SBT) connected to the DIO bidirectional lead and having an input connected to the TDO input lead, and a serial output lead; and', 'b. serial input parallel output (SIPO) circuitry having an input connected to the serial output lead of the simultaneous bidirectional transceiver, a clock input connected with the clock input lead, a TDI output connected to the TDI output lead, and a TMS output connected to the TMS output lead; and, 'iv. die channel circuitry having a Data I/O (DIO) bidirectional lead, a clock input (CLK) lead, a TDI output lead coupled to the TDI input lead, a TMS output lead coupled to the TMS input lead, a TCK output lead coupled to the TCK input lead, and a TDO input lead coupled to the TDO output lead, the die channel circuitry including], 'A. a number N of dies formed on the wafer, where N is greater than 2, each die includingB. the number N of wafer clock leads formed on the wafer with one wafer clock lead being ...

JTAG BUS COMMUNICATION METHOD AND APPARATUS

The present disclosure describes using the JTAG Tap's TMS and/or TCK terminals as general purpose serial Input/Output (I/O) Manchester coded communication terminals. The Tap's TMS and/or TCK terminal can be used as a serial I/O communication channel between; (1) an IC and an external controller, (2) between a first and second IC, or (3) between a first and second core circuit within an IC. The use of the TMS and/or TCK terminal as serial I/O channels, as described, does not effect the standardized operation of the JTAG Tap, since the TMS and/or TCK I/O operations occur while the Tap is placed in a non-active steady state. 1. An electrical device comprising:(a) a TDI terminal, a TCK terminal, a TMS terminal, and TDO terminal; and(b) control circuitry coupled to the terminals and adapting the terminals to operate in one of three separate modes of serial data communication, the three separate modes of serial communication including;(i) a first serial data communication mode in which serial data is received on the TDI terminal that is coupled to an input of a shift register, and data is transmitted on the TDO terminal that is coupled to an output of the shift register;(ii) a second serial data communication mode in which serial data is received on the TMS terminal, is coupled to a serial input of a parallel output register, and is coupled to a parallel input of a parallel data destination; and(iii) a third serial data communication mode in which parallel data from a parallel data source is coupled to a parallel input register, and serial data from a serial output of the parallel input register is coupled to and transmitted on the TMS terminal.2. The electrical device of in which the device is an integrated circuit on a substrate.3. The electrical device of in which the device is an embedded core circuit within an integrated circuit.4. A process of operating an electrical device comprising:(a) communicating serial data in a first mode by receiving serial data on a TDI ...

METHOD TO SORT PARTIALLY GOOD CORES FOR SPECIFIC OPERATING SYSTEM USAGE

A method for testing a multi-core integrated circuit device including a plurality of processing cores includes testing a first processing core on the integrated circuit device utilizing one or more tests. If a first feature on the first processing core fails a first test, the method includes performing a second test on the first processing core that tests the first processing core without the first feature. The method includes determining, based on the second test, if the first processing core is operable without the first feature. If the first processing core is operable without the first feature, the method includes storing information about the first processing core's capabilities in vital product data. 1. A method of testing a multi-core integrated circuit device including a plurality of processing cores , the method comprising:testing a first processing core on the integrated circuit device utilizing one or more tests;if a first feature on the first processing core fails a first test, performing a second test on the first processing core that tests the first processing core without the first feature;determining, based on the second test, if the first processing core is operable without the first feature; andif the first processing core is operable without the first feature, storing information about the first processing core's capabilities in vital product data.2. The method of claim 1 , further comprising:reading the information about the first processing core's capabilities stored in vital product data; andexecuting an application with the first processing core that utilizes the first processing core's capabilities.3. The method of claim 1 , wherein the first feature on the first processing core is a portion of a cache memory.4. The method of claim 1 , wherein the first feature on the first processing core is a floating point unit.5. The method of claim 1 , wherein the first feature on the first processing core is a vector unit.6. The method of claim 1 , ...