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Небесная энциклопедия

Космические корабли и станции, автоматические КА и методы их проектирования, бортовые комплексы управления, системы и средства жизнеобеспечения, особенности технологии производства ракетно-космических систем

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Мониторинг СМИ

Мониторинг СМИ и социальных сетей. Сканирование интернета, новостных сайтов, специализированных контентных площадок на базе мессенджеров. Гибкие настройки фильтров и первоначальных источников.

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24-02-2021 дата публикации

Блок преобразования интервалов времени

Номер: RU0000202557U1
Автор: Сергей Иванович Берестов
Принадлежит: Федеральное государственное унитарное предприятие «Всероссийский научно-исследовательский институт автоматики им.Н.Л.Духова» (ФГУП «ВНИИА»)

Полезная модель относится к измерительной технике и может быть использована в многоканальных устройствах измерения интервалов времени.Техническим результатом полезной модели является повышение быстродействия без увеличения частоты генератора импульсов.Блок преобразования интервалов времени, содержащий генератор импульсов, 4 запоминающих устройства, шину «Считывание», шину «Пуск», входную и выходную инф. шины, отличающийся тем, что дополнительно содержит ПЛИС, в которой спроектированы умножитель частоты, 1-й, 2-й, 3-й регистры сдвига, двоичный счетчик, мультиплексор, 4 ключа, 4 регистра, 1-й, 2-й, 3-й триггеры, 1-й, 2-й элемент И, 4 D- и 4 S-триггера, 4 счетчика адреса записи, 4 шинных мультиплексора, 4 счетчика адреса считывания; при этом выходная инф. шина соединена с выходом мультиплексора, 4 входа мультиплексора соединены с выходами 4-х ключей, вход/выход 4-х ключей соединен с входом/выходом данных 4-х запоминающих устройств, 2 входа управления мультиплексора соединены с 2-я разрядами двоичного счетчика, тактовый вход двоичного счетчика соединен с шиной «Считывание» и с тактовым входом 1-го регистра сдвига, 4 выхода которого соединены с 1-ми входами управления 4-х ключей и с тактовыми входами 4-х счетчиков адреса считывания, входная инф. шина соединена с входом 4-х регистров, выход которых соединен с входом 4-х ключей, генератор импульсов соединен с входом умножителя частоты, выход которого соединен с тактовыми входами триггеров, регистров сдвига, регистров, D-триггеров, счетчиков адреса записи и S-триггеров; шина «Пуск» соединена с входом 1-го триггера, выход которого соединен с входом 2-го триггера и с 1-м входом 1-го элемента И, 2-й вход которого соединен с инверсным выходом 2-го триггера, выход 1-го элемента И соединен с входом загрузки 2-го регистра сдвига, 4 выхода которого соединены с входами разрешения записи 4-х регистров, 1-й выход 2-го регистра сдвига соединен с входом 3-го триггера, выход которого соединен с 1-м входом 2-го элемента И, выход которого ...

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Номер записи: 1
02-02-2012 дата публикации

Time-to-digital converter and operating method

Номер: US20120026028A1
Автор: Tae Wook Kim, Yeomyung KIM
Принадлежит: Industry Academic Cooperation Foundation of Yonsei University

Provided are a TDC having a pipeline or cyclic structure and an operating method thereof. The TDC includes a first stage block and a second stage block. The first stage block detects a first bit of a digital code for a time difference between first and second input signals. The second stage block detects a second bit of the digital code for a time difference between first and second output signals of the first stage block. The first stage block amplifies a time difference between first and second delay signals for the first and second input signals to generate the first and second output signals, and transfers the first and second output signals to the second stage block.

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Номер записи: 2
11-10-2012 дата публикации

Medical tracking cap

Номер: US20120257478A1
Автор: Richard Marcellino
Принадлежит: Individual

The invention provides a container having a cap or lid including a tracking device for recording date, time, and elapsed time information, the container having opposite closed and open ends, and a cap able to be fixedly engaged with the open end of the container, the cap including a sensor for sensing closure of the container with the cap, and which initiates a digital display showing the time and day or opening and closing the container, and which tracks and displays the elapsed time since the container was last opened.

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Номер записи: 3
06-06-2013 дата публикации

TIMER DEVICE AND ELECTRONIC APPARATUS

Номер: US20130142299A1
Автор: SHIROTORI Toru, Takemura Makoto
Принадлежит: SEIKO EPSON CORPORATION

A timer device includes a RES input terminal, an OUT output terminal, a delay circuit that delays a signal input to the RES input terminal, and a pre-settable down counter that counts a given set value, and outputs a measurement completion signal via an output terminal when the counting of the set value is completed. When a predetermined signal is input to an input terminal after an output of the measurement completion signal, the pre-settable down counter completes the output of the measurement completion signal based on a delay signal obtained by the delaying the predetermined signal using the delay circuit. 1. A timer device comprising:a first external terminal;a second external terminal;a delay circuit that delays a signal input to the first external terminal; anda counting circuit that counts a given set value, and when counting of the set value is completed, outputs a measurement completion signal via the second external terminal,wherein, when a predetermined signal is input to the first external terminal after an output of the measurement completion signal, the counting circuit completes the output of the measurement completion signal based on a signal obtained by delaying the predetermined signal by the delay circuit.2. The timer device according to claim 1 , wherein the counting circuit newly counts the set value every time counting of the set value is completed.3. The timer device according to claim 2 , further comprising:an input time determination circuit that determines the time length relationship between an input time of the predetermined signal and a given determination time based on a signal obtained by delaying the predetermined signal by the delay circuit and input to the first external terminal,wherein the counting circuit selects whether or not a count value is to be initialized according to the determination result of the input time determination circuit.4. The timer device according to claim 3 , further comprising:third to n-th (n≧3) external ...

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Номер записи: 4
13-06-2013 дата публикации

User Interface Features for a Watch

Номер: US20130148477A1
Автор: Burton Maximillian P., Ishihara James Alec, Prstojevich Michael
Принадлежит: Nike, Inc.

A watch provides a chronographic function while the watch is in a “sport” mode. If a user activates a button relating to the chronographic function, such as a “start/lap” button, then the light for the watch will automatically activate. The light may remain active for a significantly long time, such as a period of six seconds or more. Alternately or additionally, if a user activates a button while the watch is in a “performance” or “sport” mode, then the light will automatically activate regardless of the button being activated. Still further, the chronographic function of the watch may be configured to not measure a lap time that is lower than a preset threshold value, such as, for example, three seconds. 1. A computer-implemented method comprising:in a device having a performance mode configured for monitoring athletic performance data and a second mode, and being configured to illuminate a display in both the performance mode and the second mode,detecting selection of the performance mode;processing input instructing the timing device to record information relating to an athletic activity while operating in the performance mode; andilluminating the display of the timing device to present the recorded information in response to the input without receiving separate input to cause the illumination.2. The method of claim 1 , wherein the illuminating of the display is for a preset amount of time.3. The method of claim 2 , wherein the preset amount of time is for six or more seconds.4. The method of claim 1 , further comprising processing second input to cause the device to operate in the second mode.5. The method of claim 4 , further comprising causing illumination of the display in the second mode claim 4 , wherein the timing device causes illumination of the display for a longer period of time in the performance mode than in the second mode.6. The method of claim 1 , wherein the recorded information corresponds to monitoring completion of a lap.7. The method of ...

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Номер записи: 5
11-07-2013 дата публикации

DISTANCE MEASURING DEVICE AND RECEIVING DEVICES THEREOF

Номер: US20130176158A1
Автор: KANG Man Keun, KIM Tae Wook
Принадлежит: Industry-Academic Cooperation Foundation, Yonsei University

Provided are a distance measuring device using an impulse signal and a receiving device thereof. The distance measuring device includes: a transmitting device transmitting an impulse signal; and a receiving device receiving the impulse signal and measuring a time interval (hereinafter, referred to as a delay time) between a transmitting timing and a receiving timing of the impulse signal, wherein the receiving device measures the delay time through a Time to Digital Converter (TDC) technique. According to the present invention, the distance measuring device measures the distance accurately and speedly. 1. A distance measuring device comprising:a transmitting device transmitting an impulse signal; anda receiving device receiving the impulse signal and measuring a delay time between a transmitting timing and a receiving timing of the impulse signal,wherein the receiving device measures the delay time through a Time to Digital Converter (TDC) technique.2. The distance measuring device of claim 1 , wherein the receiving device measures the delay time by delaying a first signal synchronized at the transmitting timing of the impulse signal and a second signal synchronized at the receiving timing of the impulse signal claim 1 , with respectively different time intervals.3. The distance measuring device of claim 2 , wherein the first signal is delayed by a first time interval and the second signal is delayed by a second time interval shorter than the first time interval.4. The distance measuring device of claim 3 , wherein the first and second time intervals are longer than the delay time.5. The distance measuring device of claim 1 , wherein the transmitting device comprises:a transmit clock signal generator generating a transmit clock signal;an impulse generator converting the transmit clock signal into a digital impulse signal; anda signal distortion filter converting the digital impulse signal into the impulse signal.6. The distance measuring device of claim 5 , wherein ...

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Номер записи: 6
15-08-2013 дата публикации

METHOD AND APPARATUS FOR CLOCKLESS CONVERSION OF TIME INTERVAL TO DIGITAL WORD

Номер: US20130207826A1
Автор: KOSCIELNIK Dariusz, MISKOWICZ Marek
Принадлежит:

Method and apparatus for detecting the beginning and end of a time interval using the control module and in mapping this time interval to a portion of electric charge proportional to this time interval and accumulated in the sampling capacitor and then realizing the process of charge redistribution in the array of redistribution by changing states of signals from relevant control outputs and in assignment of relevant values to bits in the digital word by means of the control module. After detection of the beginning of the next time interval, the charge is aaccumulated in the additional sampling capacitor and then the process of charge redistribution is realized and relevant values are assigned to bits of the digital word. When the beginning of the subsequent time interval is detected, the next cycle begins and electric charge is accumulated in the sampling capacitor again. 1. Method for clockless conversion of time interval to digital word consisting in a detection of the beginning and of the end of the time interval by the use of the control module and in mapping this time interval to a portion of electric charge proportional to this time interval and delivered by the use of the current source while the portion of electric charge is accumulated in the sampling capacitor , or in the sampling capacitor and in the capacitor having the highest capacitance value in an array of redistribution , which is connected to the sampling capacitor in parallel , and then consisting in the realization of the process of accumulated electric charge redistribution in the array of redistribution in a known way by means of the control module by changes of states of signals from relevant control outputs , while the array of redistribution comprises an array of on-off switches , of change-over switches and of capacitors such that a capacitance value of each capacitor of a given index is twice as high as a capacitance value of a capacitor of the previous index , and also consisting in the ...

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Номер записи: 7
22-08-2013 дата публикации

Multi-bit delta-sigma time digitizer circuit and calibration method thereof

Номер: US20130214945A1
Автор: Haruo Kobayashi, Masamichi Ishii, Satoshi Uemori
Принадлежит: Semiconductor Technology Academic Research Center

According to one embodiment, a multi-bit delta-sigma time digitizer circuit includes a delay array including delay selection circuits respectively including a delay element and a multiplexer, a phase comparator calculating a time difference, an integrator integrating the time difference output, a flash A/D converter executing digital conversion, a ring oscillation circuit including the delay array, a counter measuring a number of clock signal pulses, a memory storing a delay value of the delay element, and a processor correcting an output result of the A/D converter based on the delay value when the rising timing interval is measured.

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Номер записи: 8
22-08-2013 дата публикации

Low-power high-resolution time-to-digital converter

Номер: US20130214959A1
Автор: Ja Yol Lee
Принадлежит: Electronics and Telecommunications Research Institute ETRI

Disclosed is a low-power and high-resolution time-to-digital converter including: a coarse delay cell configured to delay a reference clock by a coarse delay time and output the reference clock; a rising-edge retimer configured to output a rising-edge retimed clock synchronized with the rising-edge of a DCO clock in response to the reference clock; a falling-edge retimer configured to output a falling-edge retimed clock synchronized with the falling-edge of the DCO clock; a firs sampler configured to latches output of the coarse delay cell in response to the rising-edge retimed clock and the falling-edge retimed clock; and a pseudo-thermometer code edge detector configured to detect a rising-edge fractional phase error between the reference clock and the rising-edge retimed clock as a coarse phase error from a signal output by the first sampler, and detect a falling-edge fractional phase error between the reference clock and the falling-edge retimed clock.

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Номер записи: 9
29-08-2013 дата публикации

METHOD AND APPARATUS FOR CONVERSION OF TIME INTERVAL TO DIGITAL WORD

Номер: US20130222170A1
Автор: KOSCIELNIK Dariusz, MISKOWICZ Marek
Принадлежит:

The solution according to the invention consisting in conversion of a time interval to a digital word of a number of bits equal to n by the use of the array (A) of binary-scaled capacitors (C., . . . , C) is characterized in that the time interval whose both start and end are detected by the control module (CM) is first mapped to a portion of electric charge delivered by the current source (I) and successively accumulated in the capacitors ((C, . . . , C)) in the order of decreasing capacitances starting from the capacitor (C) having the highest capacitance value in the array, and when the control module (CM) detects the end of the time interval, the charge accumulated in the capacitor (C) charged recently is successively transferred by the use of the current source (I) to the capacitors of lower capacitance values. The process of charge transfer is controlled by the control module (CM) on the basis of the output signals of the comparators (K) and (K) without the use of a clock while the value one is assigned to these bits (b, . . . , b) in the digital output word that correspond to the capacitors (C, . . . , C) on which the reference voltage (U) of a desired value has been obtained, and the value zero is assigned to the other bits. 1222111221212. Method for conversion of time interval to digital word characterized in that the time interval , whose both start and end are detected by the use of the control module (CM) , is mapped to a portion of electric charge proportional to the time interval , while the portion of electric charge is delivered during the time interval by the use of current source (I) and is accumulated in an array (A) of capacitors (C , C , . . . , C , C) whereas a capacitance value of a capacitor of a given index is twice as high as a capacitance value of the capacitor of the previous index and charge accumulation is started from the capacitor (C) having the highest capacitance value in the array (A) of capacitors and is realized from the start of ...

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Номер записи: 10
29-08-2013 дата публикации

Method and System for Compensating a Delay Mismatch Between a First Measurement Channel and a Second Measurement Channel

Номер: US20130223497A1
Автор: Jens Barrenscheen
Принадлежит: INFINEON TECHNOLOGIES AG

A method and a system for compensating a delay mismatch between a first measurement channel and a second measurement channel is disclosed. A method for compensating a delay mismatch between a first measurement channel and a second measurement channel includes providing a reference point for starting the first and second measurement channel, and starting the first measurement channel after expiration of a first delay period which begins at the reference point. The method further includes starting the second measurement channel after expiry of a second delay period which begins at the reference point, wherein a difference between a length of the first delay period and a length of the second delay period is substantially equal to the delay mismatch between the first measurement channel and the second measurement channel.

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Номер записи: 11
19-09-2013 дата публикации

Input capture peripheral with gating logic

Номер: US20130241626A1
Автор: James E. Bartling, Stephen Bowling
Принадлежит: Microchip Technology Inc

A microcontroller has an input capture peripheral, wherein the input capture peripheral is configured to store timer values of an associated timer in a memory and wherein the input capture peripheral has a gating input which controls whether an input capture function is activated.

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Номер записи: 12
07-11-2013 дата публикации

Multi-Lane Stop Watch

Номер: US20130294206A1
Автор: Yingjie Lin
Принадлежит: Individual

An electronic multi-lane stop watch is disclosed. Said multi-lane stop watch can record multi-athletes' split times and final times simultaneously. Said multi-lane stop watch can also automatically save collected data to files and export/import information and data to/from external devices such as computers or printers.

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Номер записи: 13
28-11-2013 дата публикации

PHYSICAL QUANTITY MEASURING APPARATUS AND PHYSICAL QUANTITY MEASURING METHOD

Номер: US20130315366A1
Автор: NOUNO Tomohito, OOSHIMA Akihiro
Принадлежит:

A physical quantity measuring method includes: (a) generating a synchronized input signal from an input signal, wherein the synchronized input signal is synchronized with a reference clock; (b) measuring a total number (N) that is the sum of pulses of the reference clock included in each of n units of the synchronized input signal; (c) generating 2n deviation signals based on a delay of the synchronized input signal with respect to the input signal; (d) generating a deviation integration signal by subtracting the total values of n rear-half deviation signals from the total values of n front-half deviation signals; (e) converting the deviation integration signal into a number of pulses of the reference clock; and (f) calculating the average number (Nr) of pulses of the reference clock included in one unit of the input signal, based on the total number (N), the number (dN), and the number n. 1100. A physical quantity measuring apparatus () comprising:{'b': '110', 'a synchronization unit () configured to generate a synchronized input signal from an input signal having a continuous pulse train, wherein the synchronized input signal is synchronized with a reference clock;'}{'b': '120', 'sub': 'sum', 'a counter () configured to measure a total number (N) that is the sum of pulses of the reference clock included in each of n units of the synchronized input signal, wherein each unit of the synchronized input signal has n cycles of the synchronized input signal, and n is a positive integer of 1 or more;'}{'b': '141', 'a deviation signal generator () configured to generate 2n deviation signals based on a delay of the synchronized input signal with respect to the input signal;'}{'b': '142', 'a deviation integrating unit () configured to generate a deviation integration signal by subtracting the total values of n rear-half deviation signals from the total values of n front-half deviation signals in the 2n deviation signals;'}{'b': '143', 'sub': 'sum', 'a compensation counter () ...

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Номер записи: 14
26-12-2013 дата публикации

PHYSICAL QUANTITY MEASURING APPARATUS AND PHYSICAL QUANTITY MEASURING METHOD

Номер: US20130346022A1
Автор: Sasaki Shinichi
Принадлежит:

A physical quantity measuring apparatus includes: a signal input module receiving an input signal having consecutive pulses; a low resolution clock signal generator generating a low resolution clock signal; a high resolution clock signal generator generating a high resolution clock signal; a gate time generator outputting gate time signals at a predetermined interval; a low resolution clock signal synchronizer generating a low resolution clock synchronization signal; a low resolution counter counting the number of rising edges of the low resolution clock signal; a high resolution clock signal generation controller outputting the high resolution clock signal as a gated clock signal; a high resolution clock signal synchronizer generating a high resolution clock synchronization signal; and a high resolution counter counting the number of rising edges of the gated clock signal. 1. A physical quantity measuring apparatus comprising:a signal input module configured to receive an input signal having consecutive pulses;a low resolution clock signal generator configured to generate a low resolution clock signal;a high resolution clock signal generator configured to generate a high resolution clock signal, wherein a clock speed of the high resolution clock signal is higher than that of the low resolution clock signal;a gate time generator configured to output gate time signals at a predetermined interval, wherein the gate time signals comprises a first gate time signal and a second gate time signal next to the first gate time signal;a low resolution clock signal synchronizer configured to generate a low resolution clock synchronization signal from the input signal by synchronizing the input signal with the low resolution clock signal;a low resolution counter configured to count the number of rising edges of the low resolution clock signal, wherein the low resolution counter starts counting the number of the rising edges of the low resolution clock signal when detecting a ...

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Номер записи: 15
27-02-2014 дата публикации

ZERO DEAD TIME, HIGH EVENT RATE, MULTI-STOP TIME-TO-DIGITAL CONVERTER

Номер: US20140054455A1
Автор: DUMONTHIER JEFFREY J., SUAREZ GEORGE
Принадлежит:

Time-to-digital converters adapted to analog and digital inputs and methods of use are described. A time-to-digital converter has an event frame latches and logic module with memory cells, an analog front-end module connected to the memory cells, and a bin increment generator module connected to the memory cells. The bin increment generator is configured to issue bin increments separated by a time increment, and the analog front end is configured to issue a start event followed by a plurality of stop events. Upon receipt of a first time increment following a start event, the event frame latches and logic module updates a first memory cell with a first bit-type; upon receipt of a second time increment following an intervening stop event, the event frame latches and logic module updates a second memory cell with a second bit-type different from the first bit-type. 1. A time-to-digital converter , comprising:an event frame latches and logic module having a plurality of memory cells;an analog front-end module connected to the event frame module; anda bin increment generator module connected to the event frame latches and logic module,wherein the bin increment generator module is configured to issue a sequence of bin increments to the event frame latches and logic module and wherein a successive bin increment follows a predecessor bin increment by a time interval,wherein the analog front-end module is configured to issue an event start indication to the event frame latches and logic module,wherein the analog front-end module is configured to issue at least one event stop indication to the event frame latches and logic module,wherein the event frame latches and logic module is configured to update at least one memory cell when the analog front-end module issues a bin increment, andwherein the memory cell update comprises a first bit-type following the issue of the start event indication, and wherein the memory cell update comprises a second bit-type following the issue of ...

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Номер записи: 16
27-02-2014 дата публикации

INFORMATION PROCESSING DEVICE, INFORMATION PROCESSING METHOD, AND PROGRAM

Номер: US20140058703A1
Автор: KIMISHIMA Masato, Matsunaga Hideyuki, ONOE Naoyuki, SATO Tatsuhito
Принадлежит: SONY CORPORATION

The present technique relates particularly to an information processing device, an information processing method, and a program which can improve sleep efficiency. The information processing device according to one aspect of the present technique has: an acquisition unit which acquires information which indicates an action schedule of a user; and a first determination unit which determines whether the user needs to wake up or sleep, and determines the degree of necessity of waking up when determining that the user needs to wake up and the degree of necessity of sleeping when determining the user needs to sleep, according to the action schedule of the user. The present technique is applicable to a mobile device such as a mobile telephone, a PDA and a digital camera. 1. An information processing device comprising:an acquisition unit which acquires information which indicates an action schedule of a user; anda first determination unit which performs at least one of determination as to at least one of whether or not the user needs to wake up and whether or not the user needs to sleep, and determination as to a degree of necessity of waking up when the user needs to wake up and a degree of necessity of sleeping when the user needs to sleep, according to the action schedule of the user.2. The information processing device according to claim 1 , wherein the first determination unit calculates a first score which indicates the degree of necessity of waking up or the degree of necessity of sleeping when determining the degree of necessity of waking up or the degree of necessity of sleeping.3. The information processing device according to claim 2 , further comprising a second determination unit which calculates a second score which indicates a degree of sleepiness of the user based on data detected by a sensor.4. The information processing device according to claim 3 , further comprising:a selection unit which selects content to play back based on the first score and the ...

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Номер записи: 17
06-03-2014 дата публикации

SYSTEMS AND METHODS FOR MONITORING MACHINING OF A WORKPIECE

Номер: US20140067321A1
Автор: Zinngrebe Michael Detlef
Принадлежит: SCHMITT INDUSTRIES, INC.

A monitoring system may be used to monitor machining of a workpiece. In some embodiments, the monitoring system may use an acoustic emission sensor to measure acoustic emissions from the machining and generate an acoustic emission signal. The acoustic emission signal may be compared to a master signal using several techniques, such as a Multi-Zone Strategy method. The Multi-Zone Strategy method may comprise generating a plurality of zones of the measured signal and generating a plurality of zones of a master signal to create a plurality of measured and master signal levels and thresholds. A measured signal level for each zone may be compared to a master signal level for each zone to determine whether the measured signal level differs from the master signal level by no more a predetermined percentage, which acts as a threshold for triggering notification of out of tolerance zones. 1. A system for monitoring machining of a workpiece , the system comprising:a sensor configured to generate a measured signal, wherein the measured signal is correlated to variations in the machining of the workpiece; and calculate a plurality of measured signal levels for a plurality of corresponding contiguous time zones from the measured signal; and', 'indicate whether each measured signal level at each corresponding time zone is within one or more predetermined thresholds., 'a monitoring system configured to2. The system of claim 1 , wherein the monitoring system is further configured to:receive a master signal;generate a plurality of master signal levels corresponding to the plurality of contiguous time zones; andsave the plurality of master signal levels, wherein the one or more predetermined thresholds for each contiguous time zone are calculated from the plurality of master signal levels.3. The system of claim 2 , wherein the master signal is received from the sensor during a trial/learning process.4. The system of claim 2 , wherein the monitoring system is configured to save ...

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Номер записи: 18
20-03-2014 дата публикации

PRACTICE TIME CALCULATING APPARATUS, A PRACTICE TIME CALCULATING METHOD, AND A COMPUTER READABLE RECORDING MEDIUM

Номер: US20140076123A1
Автор: Tanaka Takahiro
Принадлежит: CASIO COMPUTER CO., LTD.

An apparatus is provided, for calculating a practice time. The apparatus is used by a user to calculate such practice time that he/she requires to improve his/her playing technique to reach a predetermined progressing level at the playing technique. In the apparatus, a progressing-level evaluating unit evaluates a progressing level of a playing technique of the user who operates a playable unit. A history of the evaluated progressing level is recorded in a progressing-level recording unit. An operation-number counting unit counts the number of operations executed on the playable unit by the user every unit time. A history of the counted number of operations is recorded in an operation-number recording unit. A practice-time calculating unit calculates the practice time based on the history of the progressing level recorded in the progressing-level recording unit and the history of the number of operations recorded in the operation-number recording unit. 1. A practice-time calculating apparatus comprising:a progressing-level evaluating unit which evaluates a progressing level of a playing technique of a user who operates a playable unit;a progressing-level history recording unit which records a history of the progressing level evaluated by the progressing-level evaluating unit;an operation-number counting unit which counts the number of operations executed on the playable unit by the user in a unit time;an operation-number history recording unit which records a history of the number of operations counted by the operation-number counting unit; anda practice-time calculating unit which calculates a practice time, which is required to the user to improve the playing technique to reach a predetermined progressing level at the playing technique, based on the history of the progressing level recorded in the progressing-level history recording unit and the history of the number of operations recorded in the operation-number history recording unit.2. The practice-time ...

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Номер записи: 19
20-03-2014 дата публикации

Phase frequency detector

Номер: US20140077841A1
Автор: Fulvio Spagna, Shenggao Li, Wenyan Jia
Принадлежит: Intel Corp

Described is an apparatus comprising: a first phase frequency detector (PFD) to determine a coarse phase difference between a first clock signal and a second clock signal, the first PFD to generate a first output indicating the coarse phase difference; and a second PFD, coupled to the first PFD, to determine a fine phase difference between the first clock signal and the second clock signal, the second PFD to generate a second output indicating the fine phase difference.

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Номер записи: 20
01-01-2015 дата публикации

Powerless time reference

Номер: US20150003213A1
Автор: Thomas Suwald
Принадлежит: NXP BV

According to an embodiment, a time reference device ( 100 ) is provided, which comprises a corrodible element ( 140 ), wherein a corrosion of the corrodible element ( 140 ) advances with advancing time, and a sensor ( 102 ) configured for providing a sensor signal, the sensor signal depending on a physical property of the corrodible element ( 140 ). The physical property of the corrodible element ( 140 ) changes with a corrosion of the corrodible element ( 140 ) and the physical property of the corrodible element ( 140 ) is at least one of an electrical property, a magnetic property, and an optical property. A barrier ( 150 ) may be provided for defining a permeability for a corrosive substance ( 160 ) to the corrodible element ( 140 ).

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Номер записи: 21
02-01-2020 дата публикации

DTC BASED CARRIER SHIFT - ONLINE CALIBRATION

Номер: US20200004207A1
Автор: BANIN Elan, Ben Ami Eran, Degani Ofir
Принадлежит:

A digital to time converter (DTC) system is disclosed. The DTC system comprises a DTC circuit configured to generate a DTC output clock signal at a DTC output frequency, based on a DTC code. In some embodiments, the DTC system further comprises a calibration circuit comprising a period error determination circuit configured to determine a plurality of period errors respectively associated with a plurality consecutive edges of the DTC output clock signal. In some embodiments, each period error of the plurality of period errors comprises a difference in a measured time period between two consecutive edges of the DTC output clock signal from a predefined time period. In some embodiments, the calibration circuit further comprises an integral non-linearity (INL) correction circuit configured to determine a correction to be applied to the DTC code based on a subset of the determined period errors. 1. A digital to time converter (DTC) system , comprising:a DTC circuit configured to generate a DTC output clock signal at a DTC output frequency, based on a DTC code; and a period error determination circuit configured to determine a period error associated with successive edges of the DTC output clock signal; and', 'a correction circuit configured to determine a correction to be applied to the DTC code based on the determined period error., 'a calibration circuit comprising2. The DTC system of claim 1 , wherein the period error determination circuit is configured to determine a plurality of period errors associated with a plurality of successive edges of the DTC output clock signal.3. The DTC system of claim 2 , wherein the correction circuit is configured to determine the correction based on the plurality of period errors claim 2 , or a subset of the plurality of period errors.4. The DTC system of claim 1 , wherein the determined period error comprises a time period between a current edge of the DTC output signal and a delayed version of a pervious edge of the DTC output ...

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Номер записи: 22
13-01-2022 дата публикации

ENDOSCOPE INSERTION AND REMOVAL DETECTION SYSTEM

Номер: US20220011724A1
Автор: Batikian John, Higgins Larry, Kennedy Bruce L., Speier Craig J., Yao Wei
Принадлежит: Arthrex, Inc.

A system for determining elapsed time for a surgical procedure conducted using an endoscope is disclosed. The system may be configured to determine elapsed time for management overseeing operating rooms to determine performance metrics of the operating room such as, but not limited to, operating room consistency and frequency of unusual procedure times to assess operating room efficiency. The system may include determining insertion of an endoscope into a patient and determining removal of the endoscope from a patient. The system may then generate an elapsed surgery time based upon the insertion time of the endoscope into the patient and the removal time of the endoscope from the patient. 1. A system for determining elapsed time for a surgical procedure conducted using an endoscope , comprising:a memory that stores instructions; and determining an insertion time of an endoscope inserted into a patient via monitoring camera parameters of a camera that is positioned within the endoscope to identify the insertion time of the endoscope into the patient;', 'determining a removal time of the endoscope from a patient via monitoring camera parameters to identify the removal time of the endoscope from the patient; and', 'generating an elapsed surgery time based upon the insertion time of the endoscope into the patient and the removal time of the endoscope from the patient., 'a processor that executes the instructions to perform operations, the operations comprising2. The system of claim 1 , wherein the operation of monitoring camera parameters to identify the insertion time of the endoscope into the patient comprises monitoring a rate of change of a camera exposure index to identify a point in time in which the endoscope is inserted into the patient.3. The system of claim 2 , wherein the operation of monitoring a rate of change of a camera exposure index comprises monitoring a rate of change of a camera exposure index formed from a combination of exposure time and signal ...

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Номер записи: 23
13-01-2022 дата публикации

INTEGRATED CIRCUIT, ELECTRONIC DEVICE INCLUDING THE SAME, AND OPERATING METHOD THEREOF

Номер: US20220014208A1
Автор: CHOI Jaehyouk, HWANG Chanwoong, LEE Yongsun, PARK Hangi, SEONG Taeho
Принадлежит: KOREA ADVANCED INSTITUTE OF SCIENCE AND TECHNOLOGY

Disclosed is an integrated circuit, which includes a DTC block including DTCs, receiving a first reference signal and a first division signal, and outputting a second reference signal and a second division signal based on the first reference signal, the first division signal, and control codes, a TDC comparing phases of the second reference signal and the second division signal and outputting a comparison signal, a digital loop filter filtering the comparison signal, an oscillator generating an output signal based on the filtered comparison signal, a delta-sigma modulator outputting a first signal and a quantized noise signal based on first and second division ratio signals, a divider dividing a frequency of the output signal based on the first signal and outputting the first division signal, and a probability modulator generating the control codes based on the quantized noise signal. Probability density functions of the control codes are time-invariant. 1. An integrated circuit comprising:a digital-to-time converter (DTC) block including a plurality of DTCs, which receives a first reference signal and a first division signal and outputs a second reference signal and a second division signal based on the first reference signal, the first division signal, and a plurality of control codes;a time-to-digital converter (TDC) which compares a phase of the second reference signal and a phase of the second division signal and outputs a comparison signal;a digital loop filter which filters the comparison signal;an oscillator which generates an output signal based on the filtered comparison signal;a delta-sigma modulator which outputs a first signal and a quantized noise signal based on a first division ratio signal and a second division ratio signal;a divider which divides a frequency of the output signal based on the first signal and outputs the first division signal; anda probability modulator which generates the plurality of control codes based on the quantized noise ...

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Номер записи: 24
07-01-2021 дата публикации

MODULATORS

Номер: US20210006257A1
Автор: Lesso John Paul
Принадлежит: Cirrus Logic International Semiconductor Ltd.

This application relates to time-encoding modulators (TEMs). A TEM receives an input signal (S) and outputs a time-encoded output signal (S). A filter arrangement receives the input signal and also a feedback signal (S) from the TEM output, and generates a filtered signal (S) based, at least in part, on the feedback signal. A comparator receives the filtered signal and outputs a time-encoded signal (S) based at least in part on the filtered signal. The time encoding modulator is operable in a first mode with the filter arrangement configured as an active filter and in a second mode with the filter arrangement configured as a passive filter. The filter arrangement may include an op-amp, capacitance and switch network. In the first mode the op-amp is enabled, and coupled with the capacitance to provide the active filter. In the second mode the op-amp is disabled and the capacitance coupled to a signal path for the feedback signal to provide a passive filter. 146.-. (canceled)47. A photodiode module comprising:a photodiode;a time-encoding modulator (TEM) configured to receive an input signal from the photodiode;a bias node for receiving a bias voltage for operating the photodiode in a photoconductive mode;a reference node for receiving a reference voltage for operating the photodiode in a photovoltaic mode; a first state in which the photodiode is connected to the bias node to operate in the photoconductive mode; and', 'a second state in which the photodiode is connected to the reference node to operate in the photovoltaic node., 'at least one switch operable in at least48. A photodiode module according to claim 47 , wherein in the first state the photodiode is disconnected from the reference node.49. A photodiode module according to claim 47 , wherein in the second state the photodiode is disconnected from the bias node.50. A photodiode module according to claim 47 , wherein the photodiode comprises a first terminal and the at least one switch comprises a first switch ...

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Номер записи: 25
03-01-2019 дата публикации

Resonator Device, Electronic Apparatus, And Vehicle

Номер: US20190006989A1
Автор: Akio Tsutsumi, Fumikazu Komatsu, Takashi Kurashina
Принадлежит: Seiko Epson Corp

A resonator device includes first and second resonators and an integrated circuit device. The integrated circuit device includes a first oscillation circuit configured to oscillate the first resonator, a second oscillation circuit configured to oscillate the second resonator, and a processing circuit configured to perform processing by using frequency difference information or frequency comparison information between a first clock signal generated by oscillating the first resonator and a second clock signal generated by oscillating the second resonator. The first resonator is supported on the integrated circuit device by a first support portion. The second resonator is supported on the integrated circuit device by a second support portion.

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Номер записи: 26
03-01-2019 дата публикации

APPARATUS AND METHODS FOR SYSTEM CLOCK COMPENSATION

Номер: US20190007052A1
Автор: Nelson Reuben P.
Принадлежит:

Apparatus and methods for clock synchronization and frequency translation are provided herein. Clock synchronization and frequency translation integrated circuits (ICs) generate one or more output clock signals having a controlled timing relationship with respect to one or more reference signals. The teachings herein provide a number of improvements to clock synchronization and frequency translation ICs, including, but not limited to, reduction of system clock error, reduced variation in clock propagation delay, lower latency monitoring of reference signals, precision timing distribution and recovery, extrapolation of timing events for enhanced phase-locked loop (PLL) update rate, fast PLL locking, improved reference signal phase shift detection, enhanced phase offset detection between reference signals, and/or alignment to phase information lost in decimation. 1. An integrated circuit (IC) with system clock compensation , the IC comprising:a system clock generation circuit configured to generate a system clock signal based on a system reference signal;one or more circuit blocks having timing controlled by the system clock signal; anda system clock compensation circuit configured to generate one or more compensation signals operable to compensate the one or more circuit blocks for an error of the system clock signal.2. The IC of claim 1 , wherein the system clock compensation circuit comprises an error model configured to generate an estimate of the error of the system clock signal based on one or more operating conditions.3. The IC of claim 2 , wherein the error model is configured to receive a temperature signal indicating a temperature condition.4. The IC of claim 2 , wherein the error model is configured to receive a supply voltage signal indicating a supply voltage condition.5. The IC of claim 2 , wherein the IC is configured to receive one or more coefficients of the error model over an interface.6. The IC of claim 2 , wherein the system clock compensation ...

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Номер записи: 27
03-01-2019 дата публикации

APPARATUS AND METHODS FOR COMPENSATION OF SIGNAL PATH DELAY VARIATION

Номер: US20190007055A1
Автор: Nelson Reuben P.
Принадлежит:

Apparatus and methods for clock synchronization and frequency translation are provided herein. Clock synchronization and frequency translation integrated circuits (ICs) generate one or more output clock signals having a controlled timing relationship with respect to one or more reference signals. The teachings herein provide a number of improvements to clock synchronization and frequency translation ICs, including, but not limited to, reduction of system clock error, reduced variation in clock propagation delay, lower latency monitoring of reference signals, precision timing distribution and recovery, extrapolation of timing events for enhanced phase-locked loop (PLL) update rate, fast PLL locking, improved reference signal phase shift detection, enhanced phase offset detection between reference signals, and/or alignment to phase information lost in decimation. 1. An electronic system with compensation for signal path delay variation , the electronic system comprising: a timing circuit configured to generate an output signal based on timing of an input reference signal;', 'an output pin configured to receive the output signal from the timing circuit and', 'a delay compensation circuit configured to provide one or more compensation signals to the timing circuit; and, 'an integrated circuit (IC) comprisinga signal path configured to route the output signal from the output pin to a destination node,wherein the one or more compensation signals are operable to digitally compensate the timing circuit for a variation in delay of the signal path.2. The electronic system of claim 1 , wherein the delay compensation circuit comprises a delay model configured to generate an estimate of the variation in delay based on one or more operating conditions.3. The electronic system of claim 2 , wherein the delay model is configured to receive a temperature signal indicating a temperature condition.4. The electronic system of claim 2 , wherein the IC further comprises an interface ...

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Номер записи: 28
02-01-2020 дата публикации

Multi-level signal clock and data recovery

Номер: US20200007133A1
Автор: Atul Gupta, Bengt Littmann, George L. Barrier, IV
Принадлежит: MACOM Technology Solutions Holdings Inc

A system for retiming a multi-level signal that forms an eye diagram when plotted, such as a PAM4 signal that includes an equalizer configured to create an equalized signal and a first amplifier configured to amplify the equalized signal, responsive to a first amplifier control signal, to create a first amplified signal, and a second amplifier configured to amplify the equalized signal, responsive to a second amplifier control signal, to create a second amplified signal. An eye monitor processes the equalized signal, the first amplified signal, and the second amplified signal to create a first retiming clock phase signal and a second retiming clock phase signal, which control sampling times for flip-flops. One or more delays and one or more emphasis modules are configured to delay and introduce emphasis into an output from the flip-flops, the resulting signals are combined in a summing junction to create the retimed signal.

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Номер записи: 29
02-01-2020 дата публикации

TIME-TO-VOLTAGE CONVERTER USING CORRELATED DOUBLE SAMPLING

Номер: US20200007136A1
Автор: Caffee Aaron J., Drost Brian G., Kratyuk Volodymyr, Sonntag Jeffrey L.
Принадлежит:

A time-to-voltage converter is configured to generate an output voltage signal and a correlated reference voltage signal. The time-to-voltage converter includes a current source configured to generate a bias current through a current source output node. The time-to-voltage converter includes a first switched-capacitor circuit coupled to the current source output node and configured to generate the output voltage signal based on an input time signal and the bias current during a first interval. The time-to-voltage converter includes a second switched-capacitor circuit coupled to the current source output node and configured to generate the correlated reference voltage signal based on a reference time signal and the bias current during a second interval. The first interval and the second interval are non-overlapping intervals. 1. An apparatus comprising:a time-to-voltage converter configured to generate an output voltage signal and a correlated reference voltage signal, a current source configured to generate a bias current through a current source output node;', 'a first switched-capacitor circuit coupled to the current source output node and configured to generate the output voltage signal based on an input time signal and the bias current during a first interval; and', 'a second switched-capacitor circuit coupled to the current source output node and configured to generate the correlated reference voltage signal based on a reference time signal and the bias current during a second interval, the first interval and the second interval being non-overlapping intervals., 'wherein the time-to-voltage converter comprises2. The apparatus claim 1 , as recited in claim 1 , wherein the second switched-capacitor circuit comprises:a reference capacitor configured to sample a current source output node to develop a reference voltage during the second interval; anda hold capacitor selectively coupled in parallel with the reference capacitor and configured to hold the reference ...

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Номер записи: 30
20-01-2022 дата публикации

TIME-TO-DIGITAL CONVERTERS WITH LOW AREA AND LOW POWER CONSUMPTION

Номер: US20220019177A1
Автор: BHAUMIK Wreeju, SURYANARAYANA Batna
Принадлежит: Analog Devices International Unlimited Company

TDCs for converting time periods to digital values are disclosed. An example TDC includes a ring oscillator and a residue generation circuit. Each stage of the residue generation circuit is configured to operate on outputs from two different stages of the ring oscillator. The TDC further includes a counter for counting the number of times that an output of one of the stages of the ring oscillator switches between being at a first signal level and being at a second signal level during a time period that is being converted to a digital value. The TDC also includes a combiner for generating the digital value by combining a value indicative of the number of times counted by the counter and an output of the residue generation circuit. Such a TDC may have relatively low area and low power consumption compared to the conventional TDC designs, while yielding sufficiently linear behavior. 1. A device , comprising:a ring oscillator; anda residue generation circuit; an input of a first stage of the residue generation circuit is coupled to an output of a first stage of the ring oscillator and an output of a last stage of the ring oscillator,', 'an input of a second stage of the residue generation circuit is coupled to the output of the first stage of the ring oscillator and an output of a second stage of the ring oscillator, and', 'an input of a last stage of the residue generation circuit is coupled to an output of a one before last stage of the ring oscillator and the output of the last stage of the ring oscillator., 'wherein at least one of2. The device according to claim 1 , wherein:the ring oscillator includes a plurality of stages, the plurality of stages including the first stage of the ring oscillator, the second stage of the ring oscillator, the one before last stage of the ring oscillator, and the last stage of the ring oscillator, andthe device further includes a counter, coupled to an output of one of the plurality of stages of the ring oscillator, the counter to ...

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Номер записи: 31
27-01-2022 дата публикации

TIME DOMAIN RATIOMETRIC READOUT INTERFACES FOR ANALOG MIXED-SIGNAL IN MEMORY COMPUTE CROSSBAR NETWORKS

Номер: US20220027130A1
Автор: KASHMIRI Sayyed Mahdi, MESSNER Jonas, PAPAGEORGIOU Efthymios, WOJCIECHOWSKI Kenneth
Принадлежит:

A circuit configured to compute matrix multiply-and-add calculations that includes a digital-to-time converter configured to receive a digital input and output a signal proportional to the digital input and modulated in time-domain associated with a reference time, a memory including a crossbar network, wherein the memory is configured to receive the time modulated signal from the digital-to-time converter and output a weighted signal scaled in response to network weights of the crossbar network and the time modulated input signal, and an output interface in communication with the crossbar network and configured to receive its weighted output signal and output a digital value proportional to at least the reference time using a time-to-digital converter. 1. A circuit configured to compute matrix multiply-and-add calculations , comprising:a digital-to-time converter configured to receive a digital input and output a signal proportional to the digital input and modulated in time-domain associated with a reference time;a memory including a crossbar network, wherein the memory is configured to receive the time modulated signal from the digital-to-time converter and output a weighted signal scaled in response to network weights of the crossbar network and the time modulated signal; andan output interface in communication with the crossbar network and configured to receive its weighted output signal and output a digital value proportional to at least the reference time using a time-to-digital converter.2. The circuit of claim 1 , wherein the circuit includes a reference clock associated with the digital-to-time converter and the time-to-digital converter.3. The circuit of claim 1 , wherein the network weights include one or more electrical elements configured to scale the signal proportional to the digital input and modulated in time domain.4. The circuit of claim 1 , wherein the circuit includes an integrator for accumulation of the weighted signal scaled in response to ...

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Номер записи: 32
14-01-2021 дата публикации

Medical Device Usage Monitoring System and Method

Номер: US20210011543A1
Автор: Robertson Delaney Lee, Robertson Hadley Allen
Принадлежит:

A method, computer program product, and computer system for determining that a user wears a wearable device during one or more time periods. A total amount of time that the user is wearing the wearable device during the one or more time periods may be tracked. The total amount of time that the user wears the wearable device during the one or more time periods may be transmitted to a computing device for display on a user interface. 1. A computer-implemented method comprising:determining that a user wears a wearable device during one or more time periods;tracking a total amount of time that the user is wearing the wearable device during the one or more time periods, wherein the total amount of time that the user is wearing the wearable device is tracked using one or more timestamps stored in memory of the wearable device; andtransmitting to a computing device the total amount of time that the user wears the wearable device during the one or more time periods for display on a user interface.2. The computer-implemented method of wherein the total amount of time that the user wears the wearable device during the one or more time periods is transmitted manually.3. The computer-implemented method of wherein the total amount of time that the user wears the wearable device during the one or more time periods is transmitted automatically.4. The computer-implemented method of wherein a sensor connected to the wearable device determines that the user wears the wearable device during one or more time periods.5. The computer-implemented method of wherein the sensor includes at least one of a capacitive sensor claim 4 , a proximity sensor claim 4 , a pressure sensor claim 4 , a temperature sensor claim 4 , and a motion sensor.6. The computer-implemented method of wherein the wearable device is a back brace.7. The computer-implemented method of wherein the wearable device includes at least one of a knee brace claim 1 , an ankle brace claim 1 , a sling claim 1 , a removable cast ...

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Номер записи: 33
14-01-2021 дата публикации

Medical Device Usage Monitoring System and Method

Номер: US20210011544A1
Автор: Robertson Delaney Lee, Robertson Hadley Allen
Принадлежит:

A method, computer program product, and computer system for receiving, by a computing device, a total amount of time that a user wears a wearable device during one or more time periods. The total amount of time that the user wears the wearable device during the one or more time periods may be compared to a threshold amount of time for the one or more time periods. A remaining amount of time for the user to wear the wearable device during the one or more time periods may be displayed on a user interface based upon, at least in part, comparing the total amount of time that the user wears the wearable device during the one or more time periods to the threshold amount of time. 1. A computer-implemented method comprising:receiving, by a computing device, a total amount of time that a user wears a wearable device during one or more time periods;comparing the total amount of time that the user wears the wearable device during the one or more time periods to a threshold amount of time for the one or more time periods; anddisplaying on a user interface a remaining amount of time for the user to wear the wearable device during the one or more time periods based upon, at least in part, comparing the total amount of time that the user wears the wearable device during the one or more time periods to the threshold amount of time, wherein displaying on the user interface the remaining amount of time for the user to wear the wearable device during the one or more time periods includes displaying a surplus amount of time above the threshold amount of time that the user wears the wearable device during the one or more time periods, and wherein displaying on the user interface the remaining amount of time for the user to wear the wearable device during the one or more time periods further includes applying the surplus amount of time above the threshold amount of time to the remaining amount of time for the user to wear the wearable device during the one or more time periods.2. The ...

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Номер записи: 34
03-02-2022 дата публикации

SYSTEMS AND METHODS FOR DETERMINING TRUE COINCIDENCE EVENTS

Номер: US20220031272A1
Автор: LI JUN, LIU Shitao, YANG Longzi, Zheng Wei
Принадлежит: SHANGHAI UNITED IMAGING HEALTHCARE CO., LTD.

The present disclosure relates to systems and methods for determining true coincidence events. The systems and methods may determine original coincidence events based on time of occurrence of a plurality of single events. The systems and methods may also determine random coincidence events by processing the plurality of single events based on cycle offsets of detector units that detect the plurality of single events. A difference of any two cycle offsets may be greater than a predetermined coincidence window width. The systems and methods may then determine the true coincidence events based on the original coincidence events and the random coincidence events. 1. A device for determining coincidence events in a PET system , comprising:one or more detector rings; and a first coincidence event includes two first single events that are corresponding to each other, and', 'a second coincidence event includes a first single event and a second single event, the first single event being a single event from a detector ring corresponding to the coincidence module and the second single event being a single event from a detector ring not corresponding to the coincidence module., 'the coincidence events determined by a coincidence module include first coincidence events and second coincidence events, wherein, 'one or more coincidence modules, each corresponding to each of the one or more detector rings, respectively, the one or more coincidence modules being configured to determine coincidence events based on single events detected by the one or more detector rings, wherein2. The device of claim 1 , wherein the coincidence module includes a first coincidence unit and a second coincidence unit claim 1 , wherein:the first coincidence unit is configured to obtain multiple first single events and determine multiple first coincidence events based on the multiple first single events; andthe second coincidence unit is configured to obtain multiple first single events and multiple second ...

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Номер записи: 35
14-01-2021 дата публикации

Determining relevant information based on user interactions

Номер: US20210011963A1
Автор: Antoine J. Atallah, Eric Lance Wilson, Giovanni M. Agnoli, Joshua C. Weinberg, Joshua R. FORD, Roozbeh Mahdavian
Принадлежит: Apple Inc

A system for determining relevant information based on user interactions may include a processor configured to receive data and associated relevance information from a data source and a set of signals describing a current environment of a user or historical user behavior information in which the data source being local to a computing device. The processor may be further configured to provide, using a machine learning model, a relevance score for each of multiple data items based at least in part on the received relevance information and the set of signals. The processor may be further configured to sort the data items based on a ranking of each relevance score for each data item. The processor may be further configured to provide, as output, the multiple data items based at least in part on the ranking.

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Номер записи: 36
15-01-2015 дата публикации

INTEGRAL A/D CONVERTER AND CMOS IMAGE SENSOR

Номер: US20150014517A1
Автор: Ikebe Masayuki
Принадлежит: NATIONAL UNIVERSITY CORPORATION HOKKAIDO UNIVERSITY

The integral type Analog/Digital (AD) converter includes: a comparator configured to compare a reference voltage of a ramp waveform with an input voltage and output a comparison signal; a DLL circuit configured to generate a plurality of clock signals; a delay adjustment circuit configured to delay the comparison signal; a counter configured to count a time from starting of changing of the ramp waveform to the inversion of the outputting from the delay adjustment circuit and output the counted result as a high-order bit; and a TDC configured to latch and decode the plurality of clock signals when the output of the delay adjustment circuit is inverted and output the latched and decoded result as a low-order bit, wherein the TDC starts an operation thereof by the inversion of the comparison signal, and stops the operation thereof by the inversion of the output signal of the delay adjustment circuit. 1. An integral type Analog/Digital (AD) converter comprising:a comparator configured to compare a reference voltage of a ramp waveform linearly changed according to a passing of time with an input voltage and output a comparison signal for the reference voltage and the input voltage;a multi-phase clock generation circuit configured to generate a plurality of clock signals including a main clock signal and clock signals having phases different from that of the main clock signal;a delay adjustment circuit configured to delay the comparison signal output from the comparator by a time period longer than one period of the main clock signal, and output the delayed comparison signal;a counter configured to count a time from starting of changing of the ramp waveform to the inversion of the outputting from the delay adjustment circuit, based on the signals output from the delay adjustment circuit and the main clock signal, and output the counted result as a high order bit; anda time to digital converter configured to latch the plurality of clock signals generated by the multi-phase ...

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Номер записи: 37
14-01-2021 дата публикации

Sessions and Groups

Номер: US20210012099A1
Автор: Campbell Jenny, Orenstein Michael L., Self Christina S., Walker Elizabeth, White Kristen L.
Принадлежит:

Athletic activity may be tracked while providing encouragement to perform athletic activity. For example, energy expenditure values and energy expenditure intensity values may be calculated and associated with a duration and type of activity performed by an individual. These values and other movement data may be displayed on an interface in a manner to motivate the individual and maintain the individual's interest. The interface may track one or more discrete “sessions”. The sessions may be associated with energy expenditure values during a duration that is within a second duration, such as a day, that is also tracked with respect to variables, such as energy expenditure. Other individuals (e.g., friends) may also be displayed on an interface through which a user's progress is tracked. This may allow the user to also view the other individuals' progress toward completing an activity goal and/or challenge. 1. A computer-implemented method comprising:receiving movement data from a sensor of a first device worn by a first user and from a plurality of sensors worn by a plurality of users,initiating an athletic activity measurement session during a predetermined first time period;calculating energy expenditure values for the first user and the plurality of users for the predetermined first time period, based on the received movement data;receiving locational data for the first user from a location-determining sensor of the first device, and for the plurality of users during a second time period within the first time period;determining an activity type of the first user and an at least one of the plurality of users, based on the received movement data and locational data, wherein the first user and the at least one of the plurality of users are within a predetermined distance of one another;determining, based on the received locational data that the first user and the at least one of the plurality of users have remained stationary during the second time period and pausing ...

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Номер записи: 38
10-01-2019 дата публикации

Analog-digital converter

Номер: US20190013820A1
Автор: Kenichi Ohhata
Принадлежит: Kagoshima University NUC

AD conversion is performed by using a combination of a parallel AD converter that includes a plurality of comparators to compare an input potential of an analog input signal sampled by a track and hold circuit and reference potentials different from one another and determines a value of a predetermined number of bits on the higher-order side of a digital signal and a single-slope AD converter that reduces the input potential of the analog input signal sampled by the track and hold circuit at a constant speed, converts a time taken until the reduced input potential becomes equal to a reference potential corresponding to the value determined by the parallel AD converter to a digital value, and determines a remaining value on the lower-order side of the digital signal, and thereby the number of bits of the single-slope AD converter can be reduced and high-speed AD conversion is enabled with a small area and low power consumption.

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Номер записи: 39
09-01-2020 дата публикации

SYSTEM FOR PHASE CALIBRATION OF PHASE LOCKED LOOP

Номер: US20200014331A1
Автор: Ek Staffan, Påhlsson Tony, Sjöland Henrik
Принадлежит:

A system for phase control of a Phased Locked Loop, PLL, is disclosed. The system includes the PLL. The PLL includes an oscillator configured to generate an output signal; a frequency divider configured to generate a feedback signal by dividing the output signal from the oscillator; a first phase detector arrangement configured to output a first control signal to control the oscillator in response to a detection of a phase deviation between a reference signal and the feedback signal. A second phase detector is configured to receive the feedback signal from the frequency divider and the reference signal, and generate an output signal. A phase calibration circuit is configured to receive the output signal from the second phase detector and generate a second control signal to adjust a phase of the output signal of the oscillator. 1. A system for phase control of a Phased Locked Loop , PLL , the system comprising the PLL , an oscillator configured to generate an output signal;', 'a frequency divider configured to generate a feedback signal by dividing the output signal from the oscillator; and', 'a first phase detector arrangement configured to output a first control signal to control the oscillator in response to a detection of a phase deviation between a reference signal and the feedback signal; and, 'the PLL including a second phase detector configured to receive the feedback signal from the frequency divider and the reference signal, and generate an output signal; and', 'a phase calibration circuit configured to receive the output signal from the second phase detector and generate a second control signal to adjust a phase of the output signal of the oscillator., 'the system further comprises2. The system according to claim 1 , wherein the second phase detector is a binary phase detector.3. The system according to claim 1 , wherein the phase calibration circuit comprises:a summing component configured to sum the output signal from the second phase detector; anda ...

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Номер записи: 40
18-01-2018 дата публикации

HETEROGENEOUS SAMPLING DELAY LINE-BASED TIME TO DIGITAL CONVERTER

Номер: US20180017944A1
Автор: Lee Jae Sung, WON Jun Yeon
Принадлежит:

A delay line-based time to digital converter includes: a coarse counter for counting a pulse of a timing clock and measuring a time when an edge of an input signal is detected; a fine time interpolator including a plurality of first delay elements and a plurality of second delay elements, a delay line with the input signal as an input, and a flip-flop unit with outputs of the first delay element or outputs of the second delay elements as inputs and the timing clock as an operation frequency; and a timestamp generator for receiving a digital value on a time measured by the coarse counter and the fine time interpolator, and generating a timestamp on the input signal by using the received digital value. 1. A delay line-based time-to-digital converter comprising:a coarse counter for counting a pulse of a timing clock and measuring a time when an edge of an input signal is detected;a fine time interpolator including a plurality of first delay elements and a plurality of second delay elements, a delay line with the input signal as an input, and a flip-flop unit with outputs of the first delay element or outputs of the second delay elements as inputs and the timing clock as an operation frequency; anda timestamp generator for receiving a digital value on a time measured by the coarse counter and the fine time interpolator, and generating a timestamp on the input signal by using the received digital value.2. The delay line-based time-to-digital converter of claim 1 , whereinthe fine time interpolator further includesa multiplexer unit having outputs of the first delay element and outputs of the second delay elements as inputs, and outputting one of the input signals, andthe output of the multiplexer unit is an input to the flip-flop unit.3. The delay line-based time-to-digital converter of claim 1 , further comprisinga fine time information generator for calculating a digital value of a fine code for measuring a fine time by adding numbers of a value that is passed through ...

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Номер записи: 41
16-01-2020 дата публикации

Time-To-Digital Converter Circuit and Method for Single-Photon Avalanche Diode Based Depth Sensing

Номер: US20200018642A1
Автор: Chao Calvin Yi-Ping, CHOU Kuo-Yu, Lee Chih-Lin, Yeh Shang-Fu, Yin Chin
Принадлежит:

A self-calibration time-to-digital converter (TDC) integrated circuit for single-photon avalanche diode (SPAD) based depth sensing is disclosed. The circuit includes a SPAD matrix with a plurality of SPAD pixels arranged in m rows and n columns, the SPAD pixels in each column of SPAD pixels are connected by a column bus; a global DLL unit with n buffers and n clock signals; and an image signal processing unit for receiving image signals from the column TDC array. The circuit can also include a row control unit configured to enable one SPAD pixel in each row for a transmitting signal; a circular n-way multiplexer for circularly multiplexing n clock signals in the global DLL unit; a column TDC array with n TDCs, each TDC further comprises a counter and a latch, the latch of each TDC is connected to the circular n-way multiplexer for circular multiplexing. 1. A self-calibration time-to-digital converter (TDC) integrated circuit for single-photon avalanche diode (SPAD) based depth sensing , the circuit comprising:a SPAD matrix with a plurality of SPAD pixels arranged in m rows and n columns, wherein the SPAD pixels in each column of SPAD pixels are connected by a column bus;a global delay-locked loop (DLL) unit with n buffers and n clock signals; andan image signal processing unit for receiving image signals from the column TDC array.2. The circuit of claim 1 , wherein the circuit further comprises:a row control unit configured to enable one SPAD pixel in each row for a transmitting signal.3. The circuit of claim 2 , wherein the circuit further comprises:a circular n-way multiplexer for circularly multiplexing n clock signals in the global DLL unit.4. The circuit of claim 3 , wherein the circuit further comprises:a column TDC array with n TDCs, wherein each TDC further comprises a counter and a latch, wherein the latch of each TDC is connected to the circular n-way multiplexer for circular multiplexing.5. The circuit of claim 4 , wherein the SPAD matrix is implemented ...

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Номер записи: 42
17-04-2014 дата публикации

TIME DIFFERENCE ADJUSTMENT CIRCUIT AND TIME-TO-DIGITAL CONVERTER INCLUDING THE SAME

Номер: US20140104090A1
Автор: Dosho Shiro
Принадлежит: Panasonic Corporation

A time difference adjustment circuit includes two flip-flop circuits, a delay circuit, and a reset circuit. The delay circuit includes first and second transistors of a first polarity and third and fourth transistors of a second polarity, wherein drains of the first and third transistors are coupled to each other, drains of the second and fourth transistors are coupled to each other, the drains of the first and third transistors and a gate of the fourth transistor are coupled to each other, an input signal is coupled to a gate of the first transistor, an output signal is supplied from the drains of the second and fourth transistors, and first and second reset signals are respectively coupled to gates of the second and third transistors. 1. A time difference adjustment circuit for adjusting a time difference between edges of two input signals , comprising:first and second flip-flop circuits each configured to receive a corresponding one of the two input signals as a clock input;a delay circuit configured to delay an output signal of the first flip-flop circuit to obtain a delayed signal, and output the delayed signal; anda reset circuit configured to detect an edge of an output signal of the delay circuit and an edge of an output signal of the second flip-flop circuit to output first and second reset signals having complementary logical values, whereinthe first and second flip-flop circuits are reset by the first or second reset signal,the delay circuit includes a plurality of cascade-connected minimum-delay units each including first and second transistors of a first polarity and third and fourth transistors of a second polarity,a drain of the first transistor is coupled to a drain of the third transistor,a drain of the second transistor is coupled to a drain of the fourth transistor,the drains of the first and third transistors are coupled to a gate of the fourth transistor,an input signal to each of the minimum-delay units is coupled to a gate of the first ...

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Номер записи: 43
21-01-2021 дата публикации

OSCILLATION CIRCUIT AND INTERFACE CIRCUIT

Номер: US20210021267A1
Автор: YABE Hiroo
Принадлежит: Kioxia Corporation

An oscillation circuit has a voltage generator configured to generate a linearly changing voltage, a voltage level of which linearly changes as time passes, a first comparator configured to compare the linearly changing voltage with a first reference voltage, a second comparator configured to compare the linearly changing voltage with a second reference voltage having a higher voltage level than the first reference voltage, a time-to-digital converter configured to output a bit sequence signal in accordance with a time difference between a time when the first comparator detects that the linearly changing voltage matches the first reference voltage and a time when the second comparator detects that the linearly changing voltage matches the second reference voltage, and an oscillator configured to generate an oscillation signal that oscillates at a frequency according to the bit sequence signal. 1. An oscillation circuit comprising:a voltage generator configured to generate a linearly changing voltage, a voltage level of which linearly changes as time passes;a first comparator configured to compare the linearly changing voltage with a first reference voltage;a second comparator configured to compare the linearly changing voltage with a second reference voltage having a higher voltage level than the first reference voltage;a time-to-digital converter configured to output a bit sequence signal in accordance with a time difference between a time when the first comparator detects that the linearly changing voltage matches the first reference voltage and a time when the second comparator detects that the linearly changing voltage matches the second reference voltage; andan oscillator configured to generate an oscillation signal that oscillates at a frequency according to the bit sequence signal.2. The oscillation circuit according to claim 1 , further comprising a third comparator configured to compare the linearly changing voltage with a third reference voltage having a ...

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Номер записи: 44
10-02-2022 дата публикации

MULTI-FACTOR VERIFICATION TIMING AND DISPLAYING SYSTEM

Номер: US20220043401A1
Автор: Walklin Daniel
Принадлежит:

The invention is a device that attaches to musical equipment/instruments or fitness equipment, that can automatically track and display the duration of time a user has used the equipment using novel multi-factor verification from multiple sensors. The device includes a piezo vibration sensor, an accelerometer/gyroscope, a light sensor and IR sensor, a microprocessor, a battery for power, non-volatile memory, a mounting system, an inbuilt display, an antenna with means of wireless communication, and at least one button. The device functions via a multi-level verification process to ensure correct usage has been detected. The sensors to detect use are a piezo vibration sensor, accelerometer/gyroscope and a light sensor. In addition, the device also allows a user to select and create configurations to detect use of a variety of different objects. This could involve changing different sensor priorities, changing sensors sensitivity or disabling sensors. 1. A multi-factor verification timing and displaying system for musical or fitness equipment comprising:A device attached to the equipment arranged to automatically track and display timing data comprising;a microcontroller with non-volatile memory;a display;at least one button;a vibration sensor in communication with said microcontroller;a accelerometer and gyroscope in communication with said microcontroller;a light sensor arranged to sense visible and non-visible spectrum light in communication with said microcontroller;an antenna in communication with said microcontroller;a power source; andan adjustable mount;wherein the microcontroller is designed to detect data on the usage time of the equipment the device is attached to and store such data to non-volatile memory, and display on the display;wherein the accelerometer and gyroscope is configured to detect motion of the device;wherein the light sensor is configured to detect if the equipment is being stored ;wherein the light sensor is configured to detect the ...

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Номер записи: 45
10-02-2022 дата публикации

Power Down Detection for Non-Destructive Isolation Signal Generation

Номер: US20220043469A1
Автор: Bhatia Ajay, Venugopal Vivekanandan
Принадлежит:

A power detection circuit for detecting powering down of a voltage domain in an integrated circuit is disclosed. The power detection circuit is placed in or near the voltage domain in the integrated circuit to provide power detection on the integrated circuit. The power detection circuit detects powering down of the voltage domain to provide an isolation enable signal to another voltage domain that interfaces with the powering down voltage domain. The isolation enable signal may be used by an isolation cell coupled to the non-powering down voltage domain to prevent corrupted logic being received from the powering down voltage domain. 1. A device , comprising:a first time-to-digital converter circuit coupled to a first power supply, wherein the first time-to-digital converter circuit includes a series of first buffers coupled to a plurality of first flops; anda second time-to-digital converter circuit coupled to a second power supply, wherein the second time-to-digital converter circuit includes a series of second buffers coupled to a plurality of second flops;wherein the first time-to-digital converter circuit and the second time-to-digital converter circuit are configured to receive an input data signal; andwherein the device is configured to provide an isolation signal to at least one circuit block coupled to the second power supply when a value for a difference between a number of the first flops that receive the input data signal over a predetermined time period and a number of the second flops that receive the input data signal over the predetermined time period is below a threshold value for the difference.2. The device of claim 1 , wherein the first time-to-digital converter circuit and the second time-to-digital converter circuit operate at a lower frequency than the at least one circuit block.3. The device of claim 1 , wherein the second power supply is a substantially constant voltage power supply.4. The device of claim 1 , further comprising a level ...

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Номер записи: 46
28-01-2016 дата публикации

FREQUENCY SYNTHESIZER WITH INJECTION PULLING/PUSHING SUPPRESSION/MITIGATION AND RELATED FREQUENCY SYNTHESIZING METHOD THEREOF

Номер: US20160028411A1
Автор: Chen Chii-Horng, Kuo Chun-Ming, Liu Ai-Hsuan, Shen Shih-Chi
Принадлежит:

A frequency synthesizer includes a phase-locked loop (PLL) and a loop bandwidth controller. The PLL generates an output clock according to a reference clock. The loop bandwidth controller checks at least one indicator indicative of injection pulling/pushing of the PLL to configure a loop bandwidth of the PLL. In one exemplary design, the loop bandwidth controller sets the loop bandwidth of the PLL by controlling a configuration of a loop filter included in the PLL. For example, the PLL is an all-digital phase-locked loop (ADPLL), and the loop filter is a digital loop filter of the ADPLL. 1. A frequency synthesizer , comprising:a phase-locked loop (PLL), configured to generate an output clock according to a reference clock; anda loop bandwidth controller, configured to check at least one indicator indicative of injection pulling/pushing of the PLL to configure a loop bandwidth of the PLL.2. The frequency synthesizer of claim 1 , wherein the PLL includes a loop filter claim 1 , and the loop bandwidth controller configures the loop bandwidth of the PLL by controlling a configuration of the loop filter.3. The frequency synthesizer of claim 2 , wherein the configuration of the loop filter comprises at least one of a filter coefficient setting claim 2 , a filter type claim 2 , a filter order claim 2 , and a filter gain.4. The frequency synthesizer of claim 2 , wherein the PLL is an all-digital phase-locked loop (ADPLL) claim 2 , and the loop filter is a digital loop filter of the ADPLL.5. The frequency synthesizer of claim 1 , wherein the PLL is an all-digital phase-locked loop (ADPLL) claim 1 , the ADPLL comprises a time-to-digital converter (TDC) configured to generate a digital code of a time difference between the reference clock and a feedback clock derived from the output clock claim 1 , and the loop bandwidth controller obtains the at least one indicator based on at least an output of the TDC.6. The frequency synthesizer of claim 1 , wherein the PLL is an all- ...

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Номер записи: 47
25-01-2018 дата публикации

VERTICAL GATE GUARD RING FOR SINGLE PHOTON AVALANCHE DIODE PITCH MINIMIZATION

Номер: US20180026147A1
Автор: Mao Duli, ZHANG Bowei
Принадлежит:

A photon detection device includes a single photon avalanche diode (SPAD) including a multiplication junction defined at an interface between n doped and p doped layers of the SPAD in a first region of a semiconductor layer. A vertical gate structure surrounds the SPAD in the semiconductor layer to isolate the SPAD in the first region from a second region of the semiconductor layer on an opposite side of the vertical gate structure. The SPAD laterally extends within the first region of semiconductor layer to the vertical gate structure. An inversion layer is generated in the SPAD around a perimeter of the SPAD proximate to the vertical gate structure in response to a gate bias voltage coupled to the vertical gate structure. The inversion layer isolates the SPAD from the second region of the semiconductor layer on the opposite side of the vertical gate structure. 1. A photon detection device , comprising:a single photon avalanche diode (SPAD) disposed in a first region of a first semiconductor layer, wherein the SPAD includes a multiplication junction defined at an interface between an n doped layer and a p doped layer of the SPAD in the first region of the first semiconductor layer;a vertical gate structure disposed in the first semiconductor layer proximate to the SPAD, wherein the vertical gate structure surrounds the SPAD to isolate the SPAD in the first region of the first semiconductor layer from a second region of the first semiconductor layer on an opposite side of the vertical gate structure, wherein SPAD laterally extends within the first region of first semiconductor layer to the vertical gate structure; anda depletion layer generated around a perimeter of the SPAD proximate to the vertical gate structure in response to a gate bias voltage coupled to the vertical gate structure, wherein the depletion layer isolates the SPAD from the second region of the first semiconductor layer on the opposite side of the vertical gate structure.2. The photon detection ...

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Номер записи: 48
28-01-2021 дата публикации

Mixed-Domain Circuit with Differential Domain-Converters

Номер: US20210026309A1
Автор: Elkholy Ahmed
Принадлежит:

A mixed-domain circuit has a differential pair of Digital-to-Time Converters (DTCs), one receiving a reference clock and the other receiving a feedback clock. A Time-to-Digital Converter (TDC) compares outputs from the differential pair of DTCs and generates a digital error value that controls a digital loop filter that controls a Digitally-Controlled Oscillator (DCO) that generates an output clock. A Multi-Modulus Divider (MMD) generates the feedback clock. An accumulated modulation from a delta-sigma modulator is compared to the digital error value by a Least-Mean Square (LMS) correlator to adjust supply voltage or current sources in the pair of DTCs to compensate for errors. A capacitor in each DTC has a charging time adjusted by the accumulated modulation. The DTC can be reduced to a Time-to-Voltage Converter (TVC) and the analog voltages on the capacitors input to an Analog-to-Digital Converter (ADC) to generate the digital error value. 1. A mixed-domain circuit comprising:a first converter having a first input in a first domain, for generating a first output in a second domain;a second converter having a second input in the first domain, for generating a second output in the second domain;wherein the first domain is selected from the group consisting of a time domain, and a digital domain;wherein the second domain is selected from the group consisting of a time domain, a digital domain, and a voltage domain;wherein the first converter is matched to the second converter, wherein a signal injected to both the first input and to the second input adjusts the first output and adjusts the second output by a substantially same amount when a same adjustment signal is applied to both the first converter and to the second converter;wherein the second domain and the first domain are different domains;a differential converter that receives the first output from the first converter, and that receives the second output from the second converter, for generating an error ...

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Номер записи: 49
23-01-2020 дата публикации

METHOD OF AUTHENTICATING USER OF ELECTRONIC DEVICE, AND ELECTRONIC DEVICE FOR PERFORMING THE SAME

Номер: US20200029216A1
Автор: Choi Young-Joon, KIM Hyun-Jin, Kwak Ji-Yeon, SEO Joon-Kyu, Yoon Yeo-Jun
Принадлежит:

An electronic device is provided. The electronic device includes one or more processors that, while the electronic device is in a locked state, control to detect whether the electronic device is lifted, in response to detecting that the electronic device is lifted, control to activate the display, obtain an image from a camera, detect a face included in the image, and perform authentication of a user based on the face being detected in the image. Based on a result of the authentication, the one or more processors switch a state of the electronic device from the locked state to an unlocked state and display an indicator for indicating that the electronic device is in the unlocked state. 1. An electronic device comprising:a display;a camera;one or more processors; and [ control to detect that the electronic device is lifted,', control to activate the display to display a locking screen on the display;', 'control to obtain an image from the camera;', 'control to detect a face included in the obtained image; and', 'control to perform an authentication of a user based on the face being detected in the obtained image, and, 'in response to detecting that the electronic device is lifted while the electronic device is in the locked state and the display is inactivated], 'while the electronic device is in a locked state, 'based on a result of the authentication being successful, control to switch a state of the electronic device from the locked state to an unlocked state., 'a memory storing one or more programs including instructions which, when executed by the one or more processors, cause the one or more processors to2. The electronic device of claim 1 , wherein the instructions claim 1 , when executed by the one or more processors claim 1 , further cause the one or more processors to claim 1 , based on the result of the authentication being successful claim 1 , control the display to display an unlock screen.3. The electronic device of claim 1 , wherein the instructions ...

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Номер записи: 50
31-01-2019 дата публикации

INTEGRATED CIRCUIT DEVICE, PHYSICAL QUANTITY MEASURING DEVICE, ELECTRONIC APPARATUS, AND VEHICLE

Номер: US20190033793A1
Автор: KOMATSU Fumikazu, TSUTSUMI Akio
Принадлежит:

An integrated circuit device includes: an AFE circuit (analog front-end circuit) that receives a first signal and a second signal, carries out waveform shaping of the first signal and waveform shaping of the second signal, outputs the first signal whose waveform is shaped to a first signal line, and outputs the second signal whose waveform is shaped to a second signal line; and a time-to-digital converter that receives the first signal from the AFE circuit via the first signal line, receives the second signal from the AFE circuit via the second signal line, and converts a time difference between transition timings of the first signal and the second signal into a digital value. At least one of the first signal line and the second signal line has redundant wiring for isometric wiring. 1. An integrated circuit device comprising:an analog front-end circuit that receives a first signal and a second signal, carries out waveform shaping of the first signal and waveform shaping of the second signal, outputs the first signal whose waveform is shaped to a first signal line, and outputs the second signal whose waveform is shaped to a second signal line; anda time-to-digital converter that receives the first signal from the analog front-end circuit via the first signal line, receives the second signal from the analog front-end circuit via the second signal line, and converts a time difference between transition timings of the first signal and the second signal into a digital value,wherein at least one of the first signal line and the second signal line has redundant wiring for isometric wiring.2. The integrated circuit device according to claim 1 , whereinboth of the first signal line and the second signal line have the redundant wiring, andone signal line of the first signal line and the second signal line has a longer redundant wiring length than the other signal line.3. An integrated circuit device comprising:an analog front-end circuit that receives a first signal and a ...

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Номер записи: 51
30-01-2020 дата публикации

TIME-RESOLVING IMAGE SENSOR FOR RANGE MEASUREMENT AND 2D GREYSCALE IMAGING

Номер: US20200033456A1
Автор: Ovsiannikov Ilia, SHI Lilong, WANG Yibing Michelle
Принадлежит:

An image sensor includes a time-resolving sensor and a processor. The time-resolving sensor outputs a first signal and a second signal pair in response detecting one or more photons that have been reflected from an object. A first ratio of a magnitude of the first signal to a sum of the magnitude of the first signal and a magnitude of the second signal is proportional to a time of flight of the one or more detected photons. A second ratio of the magnitude of the second signal to the sum of the magnitude of the first signal and the magnitude of the second signal is proportional to the time of flight of the one or more detected photons. The processor determines a surface reflectance of the object where the light pulse has been reflected based on the first signal and the second signal pair and may generate a grayscale image. 1. An image sensor , comprising:a time-resolving sensor comprising at least one pixel, the time-resolving sensor outputting a first signal and a second signal pair in response to detecting by the at least one pixel one or more photons that have been reflected from an object corresponding to a light pulse projected toward the object, a first ratio of a magnitude of the first signal of the pair to a sum of the magnitude of the first signal and a magnitude of the second signal of the pair being proportional to a time of flight of the one or more detected photons, and a second ratio of the magnitude of the second signal of the pair to the sum of the magnitude of the first signal and the magnitude of the second signal of the pair being proportional to the time of flight of the one or more detected photons; anda processor that determines a surface reflectance of the object where the light pulse has been reflected based on the first signal and the second signal pair.2. The image sensor of claim 1 , wherein the processor further determines a distance to the object based on the first signal and second signal pair.3. The image sensor of claim 1 , wherein the ...

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Номер записи: 52
30-01-2020 дата публикации

Monitoring system for monitoring usage of uniquely identifiable machine components

Номер: US20200033812A1
Автор: Vincent Neyens
Принадлежит: Caterpillar Inc

System and methods for monitoring machine components are disclosed. A method may include detecting, by an electronic chip having a globally unique identifier and being integrated within the component of the machine, installation of the component in the machine. The method may include determining, by a monitoring module operatively connected to the electronic chip via a communication bus, a date or time of the installation based on receiving information regarding the installation from the electronic chip. The method may include monitoring, by the monitoring module, the component to determine an amount of time that the component has been operating. The method may include transmitting, by a transmitter module operatively connected to the monitoring module, information that identities the globally unique identifier, the date or time of the installation of the component in the machine, and the amount of time that the component has been operating.

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Номер записи: 53
05-02-2015 дата публикации

Integrated Digitizer System with Streaming Interface

Номер: US20150039272A1
Автор: Castro Scorsi Rafael, Patel Kunal H., Rubio Hector
Принадлежит: National Instruments Corporation

A digitizer system (DS) may include one or more input channels to receive sample data, and an acquisition state machine (ASM) to organize the sample data into one or more acquisition records according to events of interest, and generate framing information corresponding to the one or more acquisition records. The events of interest may be identified by a trigger circuit in the DS, and relayed to the ASM for organizing the sample data. The DS may further include a data interface capable of receiving the one or more acquisition records and the framing information, encoding the one or more acquisition records and the framing information into encoded data, and transmitting the encoded data to an expansion module. The expansion module may receive the encoded data, decode the encoded data, and recover the sample data from the decoded data according to the framing information and the one or more acquisition records. 1. A digitizer system comprising:one or more input channels configured to receive sample data; obtain the sample data from the one or more input channels, and generate one or more acquisition records from the sample data according to events of interest; and', 'generate framing information corresponding to the one or more acquisition records; and, 'an acquisition state machine (ASM) configured to perform data acquisition tasks, wherein in performing the data acquisition tasks, the ASM is configured to receive the one or more acquisition records and the framing information;', 'encode the one or more acquisition records and the framing information into encoded data;', 'transmit the encoded data, wherein the sample data is recoverable from the encoded data by a second data interface according to the framing information and the one or more acquisition records., 'a first data interface configured to2. The digitizer system of claim 1 , further comprising a trigger circuit configured to identify the events of interest claim 1 , and provide an indication of the events ...

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Номер записи: 54
12-02-2015 дата публикации

TIME TO DIGITAL CONVERTER AND APPLICATIONS THEREOF

Номер: US20150041625A1
Автор: Dutton Neale, Gnecchi Salvatore, Henderson Robert K.
Принадлежит: STMicroelectronics (Research & Development) Limited

A time to digital converter includes a sample module operable to sample an input signal at multiple different instances of time. A transition detection module, formed of comparison elements, processes the sampled input signal at successive time instances so as to detect transitions in the input signal in terms of time. An output module generates detected transitions in the input signal on multiple parallel outputs. 1. A time to digital converter , comprising:a sampling module configured to sample an input signal at multiple different instances of time;a transition detection module comprising a plurality of comparison elements, each comparison element configured to process the sampled input signal at successive time instances so as to detect transitions in the input signal in terms of time; andan output module comprising multiple parallel outputs operable to output in parallel said detected transitions in the input signal.2. The time to digital converter as claimed in claim 1 , wherein each of said comparison elements comprises a two-input logic gate claim 1 , each of its inputs being connected to a respective one of adjacent outputs of said sample module.3. The time to digital converter as claimed in claim 2 , wherein each two-input logic gate comprises one of a two-input exclusive-OR gate or a two-input exclusive-NOR gate.4. The time to digital converter as claimed in claim 1 , further comprising a toggle module operable to toggle the input signal between two states on each occasion that a timing event is detected.5. The time to digital converter as claimed in claim 4 , wherein said toggle module comprises a T-type flip-flop.6. The time to digital converter as claimed in claim 1 , wherein said sample module comprises a plurality of sample elements claim 1 , each sample element being operable to sample the input signal at a different time instance.7. The time to digital converter as claimed in claim 6 , wherein each of said sample elements comprises one of a flip- ...

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Номер записи: 55
11-02-2016 дата публикации

TIME MEASURING CIRCUIT

Номер: US20160041529A1
Автор: Taguchi Nobuyuki, WATANABE Takamoto, Yamauchi Shigenori
Принадлежит:

A first encoding part encodes a reference timing determined by a reference clock by using a delay line. A second encoding part encodes a measurement start timing and a measurement end timing of a measurement period determined by a measurement signal to be measured by also using the delay line. A count part counts the reference clocks included in the measurement period. A fraction calculation part calculates a start fraction number indicating a time difference from the measurement start timing and an immediately-following reference timing and an end fraction number indicating a time difference from the measurement end timing to an immediately-following reference timing, based on the encoding result. The fraction calculation part then calculates a fraction data indicating a difference between the measurement period and a product of the period of the reference timing and the count value of the count part. 1. A time measuring circuit comprising:a delay line having plural delay elements connected in series for delaying a pulse signal;a first encoding part for performing an encoding operation, at every reference timing determined by a reference clock, in accordance with a number of stages of the delay elements, which the pulse signal passes through during a period from a preset start timing to the reference timing;a second encoding part for performing an encoding operation with respect to a measurement start timing and a measurement end timing of a measurement period determined by a measurement signal inputted asynchronously from a reference signal, at every reference timing determined by the reference clock, in accordance with the number of stages of the delay elements, which the pulse signal passes through during the period from the preset start timing to the measurement start timing and from the preset start timing to the measurement end timing;a count part for counting a number of periods of the reference clock included in the measurement period; anda fraction ...

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Номер записи: 56
09-02-2017 дата публикации

TIME-TO-DIGITAL CONVERTER, FREQUENCY TRACKING APPARATUS AND METHOD

Номер: US20170038738A1
Автор: SONG Dongli, Zhou Shenghua
Принадлежит: Huawei Technologies Co., Ltd.

Embodiments of the present invention provide a time-to-digital converter, where the time-to-digital converter includes a delay unit, a first sampling unit, and a second sampling unit. The delay unit is connected to the first sampling unit and is configured to receive a first clock signal and delay the first clock signal; the first sampling unit is configured to perform sampling on the first clock signal and generate a first phase signal, so that a first phase-locked module adjusts a frequency of the first clock signal; the delay unit is further connected to the second sampling unit and is configured to receive a frequency-adjusted first clock signal and delay the frequency-adjusted first clock signal; and the second sampling unit is configured to perform sampling on the frequency-adjusted first clock signal and generate a second phase signal. 1. A time-to-digital converter , comprising a delay unit , a first sampling unit , and a second sampling unit , whereinthe delay unit is connected to the first sampling unit and is configured to: receive a first clock signal output by a first phase-locked module; and after delaying the first clock signal, output the first clock signal to the first sampling unit;the first sampling unit is configured to: perform, by using a reference clock signal, sampling on the first clock signal output by the delay unit; generate a first phase signal; and send the first phase signal to the first phase-locked module, so that the first phase-locked module adjusts a frequency of the first clock signal according to the first phase signal, and outputs a frequency-adjusted first clock signal to the delay unit;the delay unit is further connected to the second sampling unit and is configured to: receive the frequency-adjusted first clock signal output by the first phase-locked module; and after delaying the frequency-adjusted first clock signal, output the frequency-adjusted first clock signal to the second sampling unit; andthe second sampling unit ...

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Номер записи: 57
09-02-2017 дата публикации

Timing System

Номер: US20170039780A1
Автор: PAES Wolfgang Alexander
Принадлежит:

The invention relates to a timing system for measuring a runner's () running time between two presence points () of the runner's running path, comprising a measurement beam receiver (MSE ()) and a measurement beam emitter (MSG ()). The measurement beam () from these intersects said running path. When reception of the measurement beam is interrupted, presence signals are generated for the runner that are evaluated in the timer () in order to acquire and output the running time. In a running path with a turn-around between a start/finish line (SZL ()) and a turn-around point (), or a running path that is undulating to zig-zagged, the measurement beam receiver MSG (beam source mirror ) is situated at the ends of said running path. Presence signals are generated at the turn-around point () and/or at least one of the turning points () of said running path. In addition, the pairing of an additional measurement beam receiver [start/finish MSE ()] and beam source (), with a measurement beam perpendicularly intersecting the running path, can be arranged on the start/finish line () and is preferably integrated into a shared timer unit (). 114-. (canceled)15. A timing system for measuring the running time of a runner between two presence points of his running path , the system comprising:a measurement beam receiver (MSE) which works together with a measurement beam emitter (MSG), wherein the measurement beam thereof crosses the running path at the presence points, in such a manner that the interruption of the receipt of the measurement beam generates a runner presence signal, having a timer which is electrically connected to the measurement beam receiver (MSE) in such a manner that the timer can be controlled by the presence signals to detect and output the running time between the presence signals, wherein if the running path between a start/finish line (SZL) and a turnaround point is folded or wavy, up to and including a zigzag shape, the measurement beam receiver ( ...

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Номер записи: 58
09-02-2017 дата публикации

TIME-MEASURING SYSTEM

Номер: US20170039781A1
Автор: PAES Wolfgang Alexander
Принадлежит:

The invention relates to a time-measuring system for measuring the running time of a runner () comprising, for sensing the presence of the runner on a presence line () crossing the running track, a signaling device (), which has a light-beam source () and a light-beam receiver (), ahead of the running track () and, in the light beam oriented parallel to the running track, a reflector (). The reflector comprises a deflecting mirror () and an end mirror (). Both are positioned on the presence line () on different sides of the running track () in the horizontal plane of the light beam of the light-beam source () (light-beam plane) and are oriented in the manner of a prism in two vertical planes in such a way that the light beam crosses the running track () between the two mirrors at a substantially right angle and is reflected to the light-beam receiver (). 17.-. (canceled)8. A timing system for detecting the presence of a runner at a presence line which intersects the running path , said timing system comprising: a light beam source , the constant or constantly pulsing light beam of which intersects the running path at the presence line , a reflector , which is arranged at the side of the running courses in the measurement beam and reflects the light beam as a measurement beam , a measurement beam receiver which is arranged in the direction of the reflected measurement beam and which generates a presence signal of the runner when the receipt of the measurement beam is interrupted , a timer to which the presence signal is transmitted from the measurement beam receiver as a switching signal , wherein a pairing of a light beam source and a light beam receiver is arranged , together , before the head of the running path in such a manner that the light beam is oriented parallel to the running path , and wherein the reflector comprises a deflecting mirror and an end mirror which are placed at the presence line on different sides of the running path in the horizontal plane ...

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Номер записи: 59
08-02-2018 дата публикации

Local Oscillator Phase Synchronization for Beamforming and MIMO

Номер: US20180041290A1
Автор: Jyri Sintonen, Samu Laaja
Принадлежит: Telefonaktiebolaget LM Ericsson AB

An initial phase of each output signal generated by a plurality of radio frequency (RF) front-end circuits is determined by mixing an input signal with a mixing signal in a mixer of the corresponding RF front-end circuit. To that end, a time difference for each of the plurality of RF front-end circuits is determined by measuring a time difference between a reference signal (common to all of the RF front-end circuits) and the mixing signal of each RF front-end circuit. The initial phase for each output signal is then determined based on the measured time difference for the corresponding RF front-end circuit. Determining the initial phase in this manner accounts for any uncertainty of the phase when the RF front-end circuits are activated, enabling the phase of the corresponding antenna element to be accurately controlled.

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Номер записи: 60
16-02-2017 дата публикации

METHOD AND APPARATUS FOR TRACKING A BIOLOGICAL CONDITION

Номер: US20170043087A1
Автор: Lane John A.
Принадлежит:

Aspects of the subject disclosure may include, for example, a system or biological sensor configured to initiate a timed procedure upon detecting a biological condition. Other embodiments are disclosed. 1. A machine-readable storage medium , comprising executable instructions that , when executed by a processor , facilitate performance of operations , comprising:receiving data from a biological sensor;detecting a biological condition according to the data or input data provided by a computing device; andinitiating a timer having a period determined according to the biological condition.2. The machine-readable storage medium of claim 1 , wherein the operations further comprise presenting at a display of the biological sensor a value associated with the timer.3. The machine-readable storage medium of claim 2 , wherein the operations further comprise presenting at the display of the biological sensor an indicator associated with the biological condition.4. The machine-readable storage medium of claim 3 , wherein the indicator identifies a procedure for treating the biological condition.5. The machine-readable storage medium of claim 1 , wherein the operations further comprise presenting at a display of a device other than the biological sensor a value associated with the timer.6. The machine-readable storage medium of claim 1 , wherein the operations further comprise:receiving information indicating a treatment has been initiated in response to the biological condition; andinitiating a second timer having a period determined according to the treatment.7. The machine-readable storage medium of claim 1 , wherein the operations further comprise sending a notification message to a device upon expiration of the timer.8. The machine-readable storage medium of claim 1 , wherein the processor is an integral component of the biological sensor.9. The machine-readable storage medium of claim 1 , wherein the processor comprises a system that is communicatively coupled to the ...

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Номер записи: 61
07-02-2019 дата публикации

COMPUTE IN MEMORY CIRCUITS WITH TIME-TO-DIGITAL COMPUTATION

Номер: US20190042160A1
Автор: CHEN Gregory K., KNAG Phil, Krishnamurthy Ram, KUMAR Raghavan, Manipatruni Sasikanth, MATHURIYA Amrita, Sharma Abhishek, SUMBUL Huseyin Ekin, Young Ian A.
Принадлежит:

A memory circuit has compute-in-memory (CIM) circuitry that performs computations based on time-to-digital conversion (TDC). The memory circuit includes an array of memory cells addressable with column address and row address. The memory circuit includes CIM sense circuitry to sense a voltage for multiple memory cells triggered together. The CIM sense circuitry including a TDC circuit to convert a time for discharge of the multiple memory cells to a digital value. A processing circuit determines a value of the multiple memory cells based on the digital value. 1. A memory circuit , comprising:an array of memory cells addressable with column address and row address;compute in memory (CIM) sense circuitry to sense a voltage for multiple memory cells triggered together, the CIM sense circuitry including a time to digital converter (TDC) circuit to convert a time for discharge of the multiple memory cells to a digital value; anda processing circuit to determine a value of the multiple memory cells based on the digital value.2. The memory circuit of claim 1 , wherein the array of memory cells includes 6-transistor (6T) static random access memory (SRAM) memory cells claim 1 , 8-transistor (8T) SRAM memory cells claim 1 , or 10-transistor (10T) SRAM memory cells.3. The memory circuit of claim 1 , wherein the array of memory cells includes resistive-based random access memory (RAM) memory cells.4. The memory circuit of claim 1 , wherein the column address is to activate a wordline claim 1 , and wherein the row address is to charge a bitline.5. The memory circuit of claim 4 , wherein the bitline comprises a differential bitline claim 4 , wherein the TDC is to convert the time for discharge from a differential signal from the differential bitline.6. The memory circuit of claim 1 , wherein the TDC circuit comprises a series of delay cells claim 1 , with a number of delays in the series to correspond to a number of bits of resolution of the digital value.7. The memory circuit ...

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Номер записи: 62
01-05-2014 дата публикации

Electronic device, display control method and program

Номер: US20140121567A1
Автор: Akira Takakura, Kazuhiro Koyama, Keisuke Tsubata, Takanori Hasegawa
Принадлежит: Seiko Instruments Inc

A display control unit performs switching between internal measurement information (for example, a lap time and others) and living-body information (for example, the number of heartbeats) indicated by a living-body signal for display on a display unit, based on whether or not a receiving unit acquires the living-body signal (for example, a heartbeat signal). Accordingly, a user can switch between displaying living-body information indicated by a living-body signal on a running watch (a display unit) and not displaying the living-body information indicated by the living-body signal on the running watch, depending on whether or not a chest strap is worn. Accordingly, the user does not need to perform a user operation for switching between the display of the internal measurement information and the display of the living-body information indicated by the living-body signal. Therefore, a user's laborious job of performing a display switching operation can be reduced.

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Номер записи: 63
06-02-2020 дата публикации

METHOD FOR FORMING A DIGITAL VALUE FROM A CLOCK SIGNAL AND FROM A DATA SIGNAL

Номер: US20200041961A1
Автор: Widzgowski Bernd
Принадлежит:

A method forms a digital value from a clock signal and a digital data signal. The method includes sampling the clock signal in order to obtain a clock signal digital value sequence and sampling the digital data signal in order to obtain a data signal digital value sequence. Sampling points are ascertained from the clock signal digital value sequence, at which data signal digital values are extracted from the data signal digital value sequence. The digital value is formed from the data signal digital values. 1. A method for forming a digital value from a clock signal and a digital data signal , the method comprising:sampling the clock signal in order to obtain a clock signal digital value sequence,sampling the digital data signal in order to obtain a data signal digital value sequence,ascertaining sampling points from the clock signal digital value sequence, at which data signal digital values are extracted from the data signal digital value sequence, andforming the digital value from the data signal digital values.2. The method as claimed in claim 1 , wherein the sampling points are determined from value changes in the clock signal digital value sequence.3. The method as claimed in claim 1 , wherein the clock signal digital value sequence is a binary value sequence.4. The method as claimed in claim 1 , wherein the clock signal is oversampled.5. The method as claimed in claim 1 , wherein the digital data signal is oversampled claim 1 , or is sampled only at the sampling points claim 1 , in order to obtain the data signal digital value sequence.6. The method as claimed in claim 1 , wherein the data signal digital value sequence is a binary value sequence.7. The method as claimed in claim 6 , wherein the digital value is formed from the data signal digital values claim 6 , in that the data signal digital values form the bits of the digital value.8. The method as claimed in claim 1 , further comprising sampling a frame signal in order to obtain a frame signal digital ...

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Номер записи: 64
01-05-2014 дата публикации

METHOD AND APPARATUS FOR CALCULATING TRANSMISSION DELAY ACROSS A NETWORK

Номер: US20140122019A1
Автор: Turner Richard
Принадлежит: Cambridge Silicon Radio Limited

A method of calculating a transmission delay value for data transmitted from a first device to a second device across a communications link. The method involves calculating a plurality of measured values representing the transmission delay measured by the second device over time; detecting a minimum boundary of the measured values; and deriving the transmission delay value from the minimum boundary. The transmission delay value may be used to synchronize the clock signal of the second device to the clock signal of the first device. 1. A method of calculating a transmission delay value for data transmitted from a first device to a second device across a communications link , the method comprising:calculating a plurality of measured values representing the transmission delay measured by said second device over time;detecting a boundary of said measured values, wherein said boundary comprises at least one boundary value; andderiving said transmission delay value from said at least one boundary value.2. A method as claimed in claim 1 , wherein said first and second devices are co-operable with a respective clock signal claim 1 , and wherein said method further includes using said transmission delay value to synchronize the clock signal of said second device to the clock signal of said first device.3. A method as claimed in claim 1 , further comprising detecting an envelope representing said boundary.4. A method as claimed in claim 1 , wherein detecting said boundary involves determining a plurality of boundary values; fitting a model to said boundary values; and deriving said transmission delay value from said model.5. A method as claimed in claim 4 , wherein fitting said model involves fitting a curve claim 4 , preferably a rectilinear line claim 4 , to said boundary values.6. A method as claimed in claim 4 , wherein said model is a linear model.7. A method as claimed in claim 5 , wherein said first and second devices are co-operable with a respective clock signal ...

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Номер записи: 65
18-02-2016 дата публикации

IN-VITRO DIAGNOSTIC APPARATUS AND IN-VITRO DIAGNOSTIC METHOD PERFORMED BY IN-VITRO DIAGNOSTIC APPARATUS

Номер: US20160048108A1
Автор: JANG Eun-jeong, KIM Chung-ung, SHIN Im-ho
Принадлежит: SAMSUNG ELECTRONICS CO., LTD.

An in-vitro diagnostic apparatus includes a loading unit which receives a test medium including a test object; a first clock including first time information that is set as a standard clock time and used to determine whether an expiration date of the test medium has passed; a second clock including second time information that can be set as an arbitrary time; a sensor which acquires the expiration date of the test medium; a controller which determines whether the expiration date of the test medium has passed, based on the first time information; and an analyzer which analyzes the test object based on the second time information when it is determined that the expiration date of the test medium has not yet passed. 1. An in-vitro diagnostic apparatus comprising:a loading unit configured to receive a test medium including a test object;a first clock including first time information that is set as a standard clock time and used to determine whether an expiration date of the test medium has passed;a second clock including second time information that is set as an arbitrary time;a sensor configured to acquire the expiration date of the test medium;a controller configured to determine whether the expiration date of the test medium has passed, based on the first time information; andan analyzer configured to analyze the test object based on the second time information in response to determining that the expiration date of the test medium has not passed according to the first time information.2. The in-vitro diagnostic apparatus of claim 1 , further comprising:an output unit configured to output an informing signal indicating that the expiration date of the test medium has passed, in response to determining that the expiration date of the test medium has passed according to the first time information.3. The in-vitro diagnostic apparatus of claim 2 , wherein the informing signal comprises a user interface (UI) screen image claim 2 , andthe output unit comprises a display ...

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Номер записи: 66
07-02-2019 дата публикации

CLOCK SYNCHRONIZER TO SYNCHRONIZE A DEVICE CLOCK WITH A CLOCK OF A REMOTE DEVICE

Номер: US20190044774A1
Автор: CROLS Jan, Felicijan Tomaz, Jongsma Jakob, NASSAR Hamzeh, Pieber Michael
Принадлежит:

A device ()) with an antenna that receives a target carrier signal () from a remote target () and transmits a device carrier signal () modulated with data to communicate data between the device () and the target (), which device () comprises: clock extraction means () to extract a target clock () from the target carrier signal (); driver means () to generate the device carrier signal () from a device clock (); synchronization means () to synchronize the frequency and phase of the device clock () with the target clock (), wherein that the synchronization means () comprise: time measurement means () to measure the phase difference between the target clock () and the device clock () or an internal device clock () related to the device clock () and to provide a phase information (φ); measurement control means () to initiate a first time measurement that results in a first phase information (φ) and to initiate a second time measurement a fixed time period (ΔT) after the first time measurement that results in a second phase information (φ); frequency correction means () to correct the frequency of the device clock () and/or the internal device clock () to the frequency of the target clock () based on an evaluation of the first phase information (φ) and second phase information (φ) by evaluation means (); which measurement control means () are built to initiate a third time measurement after the frequency correction of the device clock () and/or the internal device clock () that results in a third phase information (φ) evaluated by the evaluation means () and corrected by phase correction means () which correct the phase of the device clock () to the phase of the target clock (). 1. Device with an antenna that receives a target carrier signal from a remote target and transmits a device carrier signal modulated with data to communicate data between the device and the target , which device comprises:clock extraction means to extract a target clock from the target carrier ...

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Номер записи: 67
18-02-2021 дата публикации

MULTIPLE INPUT ANALOG-TO-DIGITAL CONVERTER DEVICE AND CORRESPONDING METHOD

Номер: US20210050859A1
Автор: LA ROSA MANUELA, Sicurella Giovanni
Принадлежит: STMICROELECTRONICS S.R.L.

A multiple-input analog-to-digital converter device includes analog-to-digital converter circuits arranged between input nodes and output nodes. The analog-to-digital converter circuits operate over respective conversion times to provide simultaneous conversion of the analog input signals into respective conversion time signals. A time-to-digital converter circuit includes timer circuitry common to the plurality of analog-to-digital converter circuits. The timer circuitry cooperates with the analog-to-digital converter circuits to convert the conversion time signals into digital output signals at the output nodes. 1. A device , comprising:a plurality of input nodes configured to receive respective analog input signals;a plurality of output nodes configured to provide respective digital output signals;a plurality of analog-to-digital converter circuits arranged between the input nodes of said plurality of input nodes and the output nodes of said plurality of output nodes, wherein the analog-to-digital converter circuits of said plurality of analog-to-digital converter circuits are configured to operate over respective conversion times to provide simultaneous conversion of said analog input signals into respective conversion time signals; anda time-to-digital converter circuit comprising timer circuitry common to the analog-to-digital converter circuits of said plurality of analog-to-digital converter circuits, said timer circuitry configured to cooperate with the analog-to-digital converter circuits of said plurality of analog-to-digital converter circuits to convert said respective conversion time signals into said respective digital output signals.2. The device of claim 1 , wherein the analog-to-digital converter circuits of said plurality of analog-to-digital converter circuits comprise:converter stages configured to convert said analog input signals into respective conversion time signals, wherein said conversion time signals are a function of values of said ...

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Номер записи: 68
18-02-2021 дата публикации

SYSTEMS AND METHODS FOR PERFORMING ANALOG-TO-DIGITAL CONVERSION ACROSS MULTIPLE, SPATIALLY SEPARATED STAGES

Номер: US20210050861A1
Автор: OUZOUNOV SOTIR FILIPOV, Totev Emil Dimitrov
Принадлежит:

The invention provides a signal processing system, for transferring analog signals from a probe to a remote processing unit. The system comprises a first ASIC at a probe, which is adapted to receive an analog probe signal. The first ASIC comprises an asynchronous sigma-delta modulator, wherein the asynchronous sigma-delta modulator is adapted to: receive the analog probe signal; and output a binary bit-stream. The system further comprises a second ASIC at the remote processing unit, adapted to receive the binary bit-stream. The asynchronous may further include a time gain function circuit, the first ASIC may further comprise a multiplexer, the second ASIC may further comprise a time-to-digital converter. The time to digital converter may be a pipelined time-to-digital converter. 1. A system for performing analog-to-digital conversion , the system comprising: receive an analog signal; and', 'output a binary bit-stream comprising asynchronous time-domain pulses;, 'a probe having a first ASIC, wherein the first ASIC is adapted to receive the binary bit-stream; and', 'generate a digital output from the binary bit-stream based on time-to-digital conversion; and, 'a processing unit having a second ASIC, wherein the second ASIC comprises a time-to-digital converter adapted toa data channel adapted to propagate the binary bit-stream from the first ASIC to the second ASIC, wherein the first and second ASICs are spatially separated.2. A system as claimed in claim 1 , wherein claim 1 , and wherein: [ receive the binary bit-stream; and', a coarse digital output; and', 'a coarse residue time; and, 'output], 'a coarse time-to-digital converter, wherein the coarse time-to-digital converter is adapted to, [ 'receive an incoming residue time from the previous fine, or coarse, time-to-digital converter in the series;', 'one or more fine time-to-digital converters connected in series, each adapted to, 'output an outgoing residue time to the subsequent fine time-to-digital converter in ...

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Номер записи: 69
18-02-2016 дата публикации

ALL DIGITAL PHASE LOCKED LOOP WITH CONFIGURABLE MULTIPLIER HAVING A SELECTABLE BIT SIZE

Номер: US20160049946A1
Автор: Liao Chia-Chun
Принадлежит:

An all digital phase locked loop comprises a time-to-digital converter and a configurable multiplier. The time-to-digital converter is configured to output a digital code based on a phase difference between a reference clock signal and a variable clock signal. The configurable multiplier is coupled with the time-to-digital converter. The configurable multiplier has a selectable bit size. The selectable bit size is based on a defined minimum number of bits to obtain a reciprocal of a variable clock period. The minimum number of bits is based on a comparison of a first number of bits of a divisor with a second number of bits of a quotient. The time-to-digital converter is configured to multiply the digital code by the reciprocal of the variable clock period to output a fractional error correction value. 1. An all digital phase locked loop , comprising:a time-to-digital converter configured to output a digital code based on a phase difference between a reference clock signal and a variable clock signal; anda configurable multiplier coupled with the time-to-digital converter, the configurable multiplier having a selectable bit size, the selectable bit size being based on a defined minimum number of bits to obtain a reciprocal of a variable clock period, the minimum number of bits being based on a comparison of a first number of bits of a divisor with a second number of bits of a quotient,wherein the time-to-digital converter is configured to multiply the digital code by the reciprocal of the variable clock period to output a fractional error correction value.2. The all digital phase locked loop of claim 1 , wherein the time-to-digital converter is configured to communicate a signal to cause the first number of bits of the quotient to be less than or equal to a third number of bits of 1−DX claim 1 , where D is the divisor and Xis the quotient.3. The all digital phase locked loop of claim 2 , wherein the time-to-digital converter is configured to communicate a signal to ...

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Номер записи: 70
25-02-2016 дата публикации

Fractional-N All Digital Phase Locked Loop Incorporating Look Ahead Time To Digital Converter

Номер: US20160056825A1
Автор: Staszewski Robert Bogdan, Vlachogiannakis Gerasimos S., Ximenes Augusto Ronchini
Принадлежит:

A novel and useful look-ahead time to digital converter (TDC) that is applied to an all digital phase locked loop (ADPLL) as the fractional phase error detector. The deterministic nature of the phase error during frequency/phase lock is exploited to achieve a reduction in power consumption of the TDC. The look-ahead TDC circuit is used to construct a cyclic DTC-TDC pair which functions to reduce fractional spurs of the output spectrum in near-integer channels by randomly rotating the cyclic DTC-TDC structure so that it starts from a different point every reference clock thereby averaging out the mismatch of the elements. Associated rotation and dithering methods are also presented. The ADPLL is achieved using the look-ahead TDC and/or cyclic DTC-TDC pair circuit. 1. A look-ahead time to digital converter (TDC) for use in an all digital phase locked loop (ADPLL) , comprising:a plurality of controllable delay elements configured in a sequential chain configuration; anda phase prediction circuit coupled to a frequency reference (FREF) clock and operative to predict reference frequency clock edge timing and based thereon to select a number of delay elements in said chain to function as a digital to time converter and a portion of a remainder of delay elements in said chain to function as a time to digital converter.2. The look-ahead time to digital converter according to claim 1 , wherein said plurality of controllable delay elements are operative to generate an output code representing a fractional portion of a phase error used by said ADPLL to adjust the frequency of the variable clock (CKV).3. The look-ahead time to digital converter according to claim 1 , wherein said phase prediction circuit is coupled to a fractional part of a frequency command word (FCW) signal.4. The look-ahead time to digital converter according to claim 3 , wherein said fractional part of FCW signal is accumulated at said FREF clock.5. A look-ahead time to digital converter (TDC) for use in an ...

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Номер записи: 71
25-02-2016 дата публикации

Fractional-N Frequency Synthesizer Incorporating Cyclic Digital-To-Time And Time-To-Digital Circuit Pair

Номер: US20160056827A1
Автор: Staszewski Robert Bogdan, Vlachogiannakis Gerasimos S., Ximenes Augusto Ronchini
Принадлежит:

A novel and useful look-ahead time to digital converter (TDC) that is applied to an all digital phase locked loop (ADPLL) as the fractional phase error detector. The deterministic nature of the phase error during frequency/phase lock is exploited to achieve a reduction in power consumption of the TDC. The look-ahead TDC circuit is used to construct a cyclic DTC-TDC pair which functions to reduce fractional spurs of the output spectrum in near-integer channels by randomly rotating the cyclic DTC-TDC structure so that it starts from a different point every reference clock thereby averaging out the mismatch of the elements. Associated rotation and dithering methods are also presented. The ADPLL is achieved using the look-ahead TDC and/or cyclic DTC-TDC pair circuit. 1. A cyclic digital to time converter and time to digital converter (DTC-TDC) circuit for use in an all digital phase locked loop (ADPLL) circuit , comprising:a plurality of controllable delay elements configured in a cyclical sequential chain configuration;a phase prediction circuit coupled to a frequency reference (FREF) clock and operative to predict reference frequency clock edge timing and based thereon to select a starting delay element in said chain, a first number of delay elements in said chain to function as a digital to time converter (DTC) and a second number of delay elements in said chain to function as a time to digital converter (TDC); andwherein said DTC and TDC elements are dynamically selected.2. The circuit according to claim 1 , wherein said the selection of said DTC and TDC elements is randomized thereby scrambling mismatches between said delay elements with a resultant reduction in fractional frequency spurs output by said ADPLL.3. The circuit according to claim 1 , wherein said plurality of controllable delay elements comprises a cyclic chain of inverter circuits.4. The circuit according to claim 1 , further comprising a dithering circuit operative to generate FREF dithering.5. The ...

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Номер записи: 72
26-02-2015 дата публикации

SESSIONS AND GROUPS

Номер: US20150057944A1
Автор: Campbell Jenny, Orenstein Michael L., Self Christina S., Walker Elizabeth, White Kristen L.
Принадлежит: Nike, Inc.

Athletic activity may be tracked while providing encouragement to perform athletic activity. For example, energy expenditure values and energy expenditure intensity values may be calculated and associated with a duration and type of activity performed by an individual. These values and other movement data may be displayed on an interface in a manner to motivate the individual and maintain the individual's interest. The interface may track one or more discrete “sessions”. The sessions may be associated with energy expenditure values during a duration that is within a second duration, such as a day, that is also tracked with respect to variables, such as energy expenditure. Other individuals (e.g., friends) may also be displayed on an interface through which a user's progress is tracked. This may allow the user to also view the other individuals' progress toward completing an activity goal and/or challenge. 1. A computer-implemented method comprising:automatically initiating a first time clock for measuring athletic activity for a first time period;receiving a first portion of movement data during the first time period;using at least the first portion of movement data, calculating a cumulative energy expenditure value and an energy expenditure intensity values for the first time period;within the first time period, determining that the energy expenditure intensity value exceeds a threshold level; and based upon the determination, initiating a second time clock for measuring athletic activity for a second time period that is within the first time period;using at least a second portion of movement data that is collected during the second time period, calculating a cumulative energy expenditure value for the second time period and an energy expenditure intensity value for the second time period;terminating the second time clock prior to the termination of the first time clock; andautomatically determining a final energy expenditure value for the first time period and a ...

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Номер записи: 73
26-02-2015 дата публикации

SESSIONS AND GROUPS

Номер: US20150057945A1
Автор: Campbell Jenny, Orenstein Michael L., Self Christina S., Walker Elizabeth, White Kristen L.
Принадлежит:

Athletic activity may be tracked while providing encouragement to perform athletic activity. For example, energy expenditure values and energy expenditure intensity values may be calculated and associated with a duration and type of activity performed by an individual. These values and other movement data may be displayed on an interface in a manner to motivate the individual and maintain the individual's interest. The interface may track one or more discrete “sessions”. The sessions may be associated with energy expenditure values during a duration that is within a second duration, such as a day, that is also tracked with respect to variables, such as energy expenditure. Other individuals (e.g., friends) may also be displayed on an interface through which a user's progress is tracked. This may allow the user to also view the other individuals' progress toward completing an activity goal and/or challenge. 1. A computer-implemented method comprising:for each of a plurality of individual body worn devices, each being associated with a corresponding different user within a plurality of users, automatically initiating a first time clock for measuring athletic activity during a first predetermined time period;receiving movement data from each of the plurality of user's during the first predetermined time period;based on the movement data, initiate calculating energy expenditure values for each user for the first time period,after initiation of the calculating the energy expenditure values for the first time period, initiating a second time clock for measuring athletic activity during a second non-predetermined time period that is within the first time period;receiving locational data of the plurality of users during the second time period;determining that at least two of the plurality of user's are participating in a common athletic activity based upon the energy expenditure values and the locational data for the first user and the second users during the second time, ...

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Номер записи: 74
23-02-2017 дата публикации

RESCUE TIME TRACKER

Номер: US20170053512A1
Автор: Coutier Jon P., FREEMAN Gary A., Herken Ulrich, Resnick Jeffrey, Thomas Colin, Totman Mark
Принадлежит:

This document relates to systems and techniques for providing response to emergency situations, such as traffic accidents, cardiac arrest, or other medical emergencies. 1. A rescue time tracker device comprising:a time counter configured to track at least one interval of elapsed time wherein the at least one interval of elapsed time corresponds to a rescue-related event;a display configured to display one or more of the at least one interval of elapsed time and a status indicator for the rescue-related event; anda communication interface comprising one or more of a wireless transmitter and an input/output port, wherein the communication interface is configured to transmit the at least one interval of elapsed time and information corresponding to the rescue-related event to a computing device.2. The rescue time tracker device of wherein the at least one interval of elapsed time is an elapsed time from an initialization of the rescue time tracker device.3. The rescue time tracker device of wherein the at least one interval of elapsed time is an elapsed time from an occurrence of the rescue-related event.4. The rescue time tracker device of wherein the at least one interval of elapsed time is indicative of a remaining time in a time period between a first rescue-related event and a second rescue-related event.5. The rescue time tracker of wherein the display portion is further configured to provide a reminder for the rescuer to perform the second rescue-related event when the time period has concluded.6. The rescue time tracker device of wherein the at least one interval of elapsed time is a time interval corresponding to a medical condition of a victim.7. The rescue time tracker device of wherein the status indicator comprises indicia indicative of the time interval corresponding to the medical condition of the victim.8. The rescue time tracker device of claim 1 , configured to be disposed in a medical device.9. The rescue time tracker device of wherein the medical ...

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Номер записи: 75
21-02-2019 дата публикации

APPARATUS AND METHOD FOR GENERATING TEMPERATURE-INDICATING SIGNAL USING CORRELATED-OSCILLATORS

Номер: US20190056274A1
Автор: Fan Philex Ming-Yan, Nguyen Richard, Poojary Manjunatha
Принадлежит:

A temperature sensor configured to generate a temperature-indicating signal with improved accuracy over a wide temperature range is disclosed. The temperature sensor includes a first oscillator configured to generate a first oscillating signal with a first frequency that varies with a sensed temperature and a reference parameter; a second oscillator configured to generate a second oscillating signal with a second frequency that varies with the reference parameter; and a time-to-digital converter (TDC) configured to generate a digital output indicative of the sensed temperature based on a ratio of the first frequency to the second frequency. Because the first and second frequencies depend on the reference parameter, and the temperature-indicating signal is a function of the ratio of the first and second frequencies, temperature-variation in the reference parameter cancels out in the temperature-indicating signal. 1. An apparatus , comprising:a first oscillator configured to generate a first oscillating signal with a first frequency that varies with a sensed temperature and a reference parameter;a second oscillator configured to generate a second oscillating signal with a second frequency that varies with the reference parameter; anda time-to-digital converter (TDC) configured to generate a digital output indicative of the sensed temperature based on a ratio of the first frequency to the second frequency.2. The apparatus of claim 1 , wherein the first frequency of the first oscillating signal is based on a proportional to absolute temperature (PTAT) parameter.3. The apparatus of claim 1 , wherein the first frequency of the first oscillating signal is based on a complementary to absolute temperature (CTAT) parameter.4. The apparatus of claim 1 , wherein the first oscillator comprisesa ring oscillator including a set of cascaded series-connected inverter-transmission gate pairs including a first inverter-transmission gate pair and a last inverter-transmission gate pair, ...

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Номер записи: 76
05-03-2015 дата публикации

ELECTRONIC DEVICE

Номер: US20150063076A1
Автор: YAMAGUCHI Eiichiro
Принадлежит:

A running watch includes: a time measurement portion which measures a lapse of time; an operation button which indicates a measurement with respect to the time measurement portion; a display portion which displays a measurement result in the time measurement portion on a display screen; and a display color switching portion which switches a display color of the display screen corresponding to a measurement state of the time measurement portion. 1. An electronic device , comprising:a measurement portion which measures a lapse of time;a display portion which displays a measurement result measured by the measurement portion on a display screen; anda display control portion which switches a display color of the display screen corresponding to a measurement state of the measurement portion.2. The electronic device according to claim 1 , further comprising:an indication portion which indicates an initiation or a stop of the measurement,wherein the measurement portion transits to a measurement state or a non-measurement state according to the indication of the indication portion, andwherein the display control portion switches the display color to a first color when the measurement portion is in the measurement state, and switches the display color to a second color when the measurement portion is in the non-measurement state.3. The electronic device according to claim 1 ,wherein, the display control portion switches the display color of at least a part of an area of the display screen corresponding to the state of the measurement portion.4. The electronic device according to claim 1 ,wherein, the display screen includes a character area and a background area, and the display control portion switches at least one display color of the character area and the background area.5. The electronic device according to claim 1 ,wherein the display screen is displayed in white and in black, and the display control portion switches the white color and the black color to each other.6. ...

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Номер записи: 77
21-02-2019 дата публикации

TIME TO DIGITAL CONVERTER WITH INCREASED RANGE AND SENSITIVITY

Номер: US20190056698A1
Автор: Testi Nicolo
Принадлежит:

Systems and methods are described for determining a phase measurement difference between a received modulated signal and a local clock signal. An adjusted local clock phase measurement may be determined by subtracting, from the phase measurement difference, a phase correction that is based on the frequency difference between the modulator signal's carrier frequency and the local clock's frequency. A phase modulation value may be generated by scaling the adjusted local clock phase measurement. The scaling may be based on a ratio of the modulated signal's carrier frequency and the local clock's frequency. The phase correction may be based on (i) a count of periods of the modulated signal occurring between each corrected phase measurement and (ii) a difference between the carrier frequency and the local clock frequency. 1. A method comprising:receiving, at a receive phase-to-digital conversion (PDC) circuit, a modulated signal having a carrier frequency;obtaining a phase measurement between the modulated signal and a local clock signal;generating a carrier-based phase correction value by accumulating a phase-correction increment;generating a corrected phase measurement value based on a difference between the phase measurement and the carrier-based phase correction value; andgenerating a carrier phase measurement by scaling the corrected phase measurement value.2. The method of claim 1 , wherein generating the phase-correction increment is based on (i) a count of periods of the modulated signal occurring between each generation of a corrected phase measurement claim 1 , and (ii) a difference between the carrier frequency and a frequency of the local clock signal.3. The method of claim 2 , wherein generating the carrier-based phase correction value is inhibited if a rising edge of the modulated signal does not occur within a timing window.4. The method of claim 1 , wherein obtaining the phase measurement comprises:determining a coarse measurement by determining a phase ...

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Номер записи: 78
03-03-2016 дата публикации

STOPWATCH AND TIMER USER INTERFACES

Номер: US20160062582A1
Автор: BUTCHER Gary Ian, Chaudhri Imran, DASCOLA Jonathan R., DYE Alan C., Lemay Stephen O., MARIC Natalia, Wilson Christopher, Wilson Eric Lance, YANG Lawrence Y.
Принадлежит: Apple Inc.

An electronic device may display a first lap time representation, and may move the first lap time representation in accordance with a first amount of elapsed time. While moving the first lap time representation, the electronic device may detect a lap input. In response to the lap input, the electronic device may cease movement of the first lap time representation, display a second lap time representation, and move the second lap time representation in accordance with a second amount of elapsed time. A relative positioning of the first lap time representation and the second lap time representation may correspond to a difference between a first lap time and a second lap time. In some embodiments, the electronic device may update the timescales of lap time representation(s) in accordance with a rotational input. In some embodiments, the electronic device may update a timer duration setting in accordance with a rotational input. 1. A non-transitory computer readable storage medium storing one or more programs , the one or more programs comprising instructions , which when executed by one or more processors of an electronic device with a display , cause the device to:display, at a first time, a first representation of a first lap time in a user interface;move the first representation along a first axis in the user interface in accordance with a first amount of time elapsed since the first time, the first amount of time corresponding to the first lap time;while moving the first representation, detect a first lap input at the device at a second time; cease movement of the first representation along the first axis; and', 'display a second representation of a second lap time in the user interface; and, 'in response to the first lap inputmove the second representation along the first axis in the user interface in accordance with a second amount of time elapsed since the second time, the second amount of time corresponding to the second lap time, wherein a relative positioning ...

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Номер записи: 79
04-03-2021 дата публикации

FREQUENCY MEASUREMENT CIRCUIT AND FREQUENCY MEASUREMENT APPARATUS

Номер: US20210063451A1
Автор: Haneda Hideo, SUDO Yasuhiro, Takahashi Tomoaki
Принадлежит:

A frequency measurement circuit includes a first counter that counts a pulse number of a reference clock signal and generates first count data, a second counter that counts a pulse number of a measurement target clock signal and generates second count data, a time-to-digital conversion circuit that generates first time difference data indicating a time difference between a first timing at which the first counter starts counting of the pulse number and a second timing at which the second counter starts counting of the pulse number, and second time difference data indicating a time difference between a third timing at which the first counter ends counting of the pulse number and a fourth timing at which the second counter ends counting of the pulse number, and a calculation circuit that performs calculation based on the second count data, the first time difference data, and the second time difference data and generates frequency data indicating a frequency of the measurement target clock signal. 1. A frequency measurement circuit comprising:an oscillation circuit that generates a reference clock signal;a first counter that counts a pulse number of the reference clock signal and generates first count data;a second counter that counts a pulse number of a measurement target clock signal and generates second count data;a time-to-digital conversion circuit that generates first time difference data indicating a time difference between a first timing at which the first counter starts counting of the pulse number of the reference clock signal and a second timing at which the second counter starts counting of the pulse number of the measurement target clock signal, and second time difference data indicating a time difference between a third timing at which the first counter ends counting of the pulse number of the reference clock signal and a fourth timing at which the second counter ends counting of the pulse number of the measurement target clock signal; anda calculation ...

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Номер записи: 80
10-03-2022 дата публикации

Spur cancellation for spur measurement

Номер: US20220077863A1
Автор: Rajesh Thirugnanam, Timothy A. Monk
Принадлежит: Skyworks Solutions Inc

A spur measurement system uses a first device with a spur cancellation circuit that cancel spurs responsive to a frequency control word identifying a spurious tone of interest. A device under test generates a clock signal and supplies the clock signal to the first device through an optional divider. The spur cancellation circuit in the first device generates sine and cosine weights at the spurious tone of interest as part of the spur cancellation process. A first magnitude of the spurious tone in a phase-locked loop in the first device is determined according to the sine and cosine weights and a second magnitude of the spurious tone in the clock signal is determined by the first magnitude divided by gains associated with the first device.

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Номер записи: 81
04-03-2021 дата публикации

METHOD AND COMPUTING DEVICE WITH A MULTIPLIER-ACCUMULATOR CIRCUIT

Номер: US20210064367A1
Автор: JUNG Seungchul, Kim Sang Joon
Принадлежит: SAMSUNG ELECTRONICS CO., LTD.

Provided is a multiplier-accumulator (MAC) system, circuit, and method. The MAC system includes a MAC circuit, including a plurality of resistors, having respective resistances, a capacitor connected to the plurality of resistors to charge, in response to a plurality of input signals, the capacitor with electric charge, and a time-to-digital converter (TDC) configured to convert information of a charge time of the capacitor, due to the electric charge, into a digital value, wherein the digital value is an accumulation result of the MAC circuit. 1. A multiplier-accumulator (MAC) system , comprising: a plurality of resistors, having respective resistances;', 'a capacitor connected to the plurality of resistors to charge, in response to a plurality of input signals, the capacitor with electric charge; and', 'a time-to-digital converter (TDC) configured to convert information of a charge time of the capacitor, due to the electric charge, into a digital value,', 'wherein the digital value is an accumulation result of the MAC circuit., 'a MAC circuit, including2. The system of claim 1 ,wherein the plurality of resistors and the capacitor are configured as a first output line,wherein the MAC circuit further comprises one or more other output lines, each respectively including respective plural resistors, having respective resistances, connected to a respective other capacitor,wherein the respective other capacitor, of each of the one or more other output lines, is configured to be charged, in response to the plurality of input signals, with respective electric charge, andwherein the respective other capacitor and the capacitor have a same capacitance.3. The system of claim 2 ,wherein the time-to-digital converter (TDC) is configured to convert respective information of respective charge times of the respective other capacitor of the one or more other output lines, into respective digital values, andwherein the digital value and the respective digital values are the ...

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Номер записи: 82
01-03-2018 дата публикации

Digital Phase Locked Loop and Method for Operating the Same

Номер: US20180062660A1
Автор: Liu Yao-Hong, Van Den Heuvel Johan
Принадлежит: STICHTING IMEC NEDERLAND

The present disclosure relates to a Digital Phase Locked Loop (DPLL) for phase locking an output signal to a reference clock signal. The DPLL comprises a phase detector for detecting a phase error of a feedback signal with respect to the reference clock signal. The DPLL comprises a digitally controlled oscillator for generating the output signal based at least on a frequency control word and at least one control signal representative of the phase error. The phase detector comprises an integer circuit for generating a first control signal representative of an integer phase error. The phase detector comprises a fractional circuit comprising a Time-to-Digital Converter (TDC) for processing the feedback signal and a delayed reference clock signal. The fractional circuit is provided for generating from the TDC output a second control signal representative of a fractional phase error. The DPLL comprises an unwrapping unit for unwrapping the TDC output. 1. A Digital Phase Locked Loop (DPLL) for phase locking an output signal to a reference clock signal , the DPLL comprising: an integer circuit configured for generating a first control signal representative of an integer phase error; and', 'a fractional circuit comprising a Time-to-Digital Converter (TDC) configured for processing the feedback signal and a delayed reference clock signal to generate a TDC output, wherein the fractional circuit is configured for generating from the TDC output a second control signal representative of a fractional phase error;, 'a phase detector configured for detecting a phase error of a feedback signal with respect to the reference clock signal, wherein the feedback signal is the output signal of the DPPL fed back to an input of the phase detector, wherein the phase detector comprisesa digitally controlled oscillator (DCO) configured for generating the output signal based at least on a frequency control word and at least one control signal representative of the phase error detected by the ...

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Номер записи: 83
08-03-2018 дата публикации

Nursing Garment

Номер: US20180064177A1
Автор: Akerson Deeanne, Akerson Garret
Принадлежит:

A nursing garment computing system includes a nursing garment having a pair of breast cups with an electronic sensor to indicate the status of a breast in the pair of breast cups and a computing device to record the sensor data indicative of whether the breast cup is open or closed. The data can be electronically sent to an external device such as a cell phone or personal digital assistant to keep track of which breast cup has been opened for breastfeeding event, time between breastfeeding event, amount of time for breastfeeding from each side of the breast, a record of which side was nursed last, and a record of which side was nursed first during the last breastfeeding event. 1. A nursing garment computing system , comprising:a nursing garment for breasts support having a pair of breast cups, shoulder straps and a body support having a front portion connected extending through side portions to a back portion, the front portion connecting to a middle section and each of the pair of breast cups, the side portion connecting to the front portion with one side portion connecting to one each of the pair of breast cups;a pair of clips clasping each shoulder strap configured with a clasp sensor to generate data of a state of a breast in the pair of breast cups;a computing device to record clasp sensor data indicative of whether the breast cup is open;wherein, the clasp sensor data is indicative of an amount of time each breast cup is open when the clip is unclasped and indicative of breastfeeding event by the breast,wherein, the computing device records the clasp sensor data, the clasp sensor data is indicative of the amount of time when the breast cup is open, thus starts counting as breastfeeding time, andwherein, the computing device further stores the clasp sensor data and the clasp sensor data can be downloaded via Bluetooth or another electronic means onto cell phone or other personal digital assistant device.2. The system of claim 1 , wherein the computing device is ...

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Номер записи: 84
17-03-2022 дата публикации

MEASUREMENT APPARATUS, RANGING APPARATUS, AND MEASUREMENT METHOD

Номер: US20220082669A1
Автор: Hiyama Hiroki, SAKAZUME SHUNSUKE
Принадлежит:

A measurement apparatus (A) according to an embodiment includes: a time-to-digital converter circuit () that measures a time period between an emission timing at which light is emitted from a light emitting unit () and a time point at which a light receiving unit () receives the light; a delay means (A) that adds, to the time period measured by the time-to-digital converter circuit, a positive or a negative delay having a length that is different from a cycle of a clock used by the time-to-digital converter circuit and that is used as a unit amount of delay; and a storage unit () that stores therein time information that indicates the time period measured by the time-to-digital converter circuit and delay information that indicates an amount of delay to be added by the delay means, in association with each other, related to each of a case in which a delay is added by the delay means and a case in which a delay is not added by the delay means. 1. A measurement apparatus comprising:a time-to-digital converter circuit that measures a time period between an emission timing at which light is emitted from a light emitting unit and a time point at which a light receiving unit receives the light;a delay means that adds, to the time period measured by the time-to-digital converter circuit, a positive or a negative delay having a length that is different from a cycle of a clock used by the time-to-digital converter circuit and that is used as a unit amount of delay; anda storage unit that stores therein time information that indicates the time period measured by the time-to-digital converter circuit and delay information that indicates an amount of delay to be added by the delay means, in association with each other, related to each of a case in which a delay is added by the delay means and a case in which a delay is not added by the delay means.2. The measurement apparatus according to claim 1 , whereinthe time-to-digital converter circuit is configured to start measurement ...

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Номер записи: 85
28-02-2019 дата публикации

DELAY TIME CALIBRATION OF OPTICAL DISTANCE MEASUREMENT DEVICES, AND ASSOCIATED SYSTEMS AND METHODS

Номер: US20190064329A1
Автор: GAO Mingming, HONG Xiaoping, LIU Xiang, Wu Di
Принадлежит:

Representative embodiments of the present technology include a device for measuring distance to an object. The device comprises a light emitter configured to emit an outbound light pulse and a light sensor configured to receive a returning light pulse and output a pulse signal representing the returning light pulse. The device further comprises a field-programmable gate array (FPGA) coupled to the light sensor and including a time-to-digital converter (TDC) having a series of sequentially coupled delay units. Individual sequentially coupled delay units are associated with corresponding individual delay times. At least some of the sequentially coupled delay units have different individual delay times. The TDC is configured to measure timing information of the pulse signal based at least in part on the individual delay times of the sequentially coupled delay units. The device further includes a controller configured to calculate the distance to the object based on the timing information. 1. A device for measuring distance to an object , the device comprising:a light emitter configured to emit an outbound light pulse;a light sensor configured to receive a returning light pulse reflected from the object and output a pulse signal representing the returning light pulse;a field-programmable gate array (FPGA) coupled to the light sensor and including a time-to-digital converter (TDC) having a series of sequentially coupled delay units, individual sequentially coupled delay units associated with corresponding individual delay times, wherein at least some of the sequentially coupled delay units have different individual delay times, and wherein the TDC is configured to measure timing information of the pulse signal based at least in part on the individual delay times of the sequentially coupled delay units; anda controller configured to calculate the distance to the object based on the timing information.2. The device of wherein the light emitter claim 1 , light sensor claim ...

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Номер записи: 86
28-02-2019 дата публикации

TIME-TO-DIGITAL CONVERTER, CIRCUIT DEVICE, PHYSICAL QUANTITY MEASUREMENT APPARATUS, ELECTRONIC APPARATUS, AND VEHICLE

Номер: US20190064747A1
Автор: Haneda Hideo, SUDO Yasuhiro
Принадлежит:

A time-to-digital converter includes a clock signal generation circuit that generates a first cycle signal having a voltage level that monotonously increases or decreases in a cycle corresponding to the clock frequency of a reference clock signal and further generates a first clock signal based on a first signal and the first cycle signal, a clock signal generation circuit that generates a second cycle signal having a voltage level that monotonously increases or decreases in a cycle corresponding to the clock frequency of a reference clock signal and further generates a second clock signal based on a second signal and the second cycle signal, and a processing circuit that converts a time difference between the transition timing of the first signal and the transition timing of the second signal into a digital value based on the first and second clock signals. 1. A time-to-digital converter comprising:a first clock signal generation circuit configured to receive a first reference clock signal having a first clock frequency and generate a first cycle signal having a voltage level that monotonously increases or decreases in a cycle corresponding to the first clock frequency, and further generate a first clock signal based on a first signal and the first cycle signal;a second clock signal generation circuit configured to receive a second reference clock signal having a second clock frequency different from the first clock frequency and generate a second cycle signal having a voltage level that monotonously increases or decreases in a cycle corresponding to the second clock frequency, and further generate a second clock signal based on a second signal and the second cycle signal; anda processing circuit configured to convert a time difference between a transition timing of the first signal and a transition timing of the second signal into a digital value based on the first and second clock signals.2. The time-to-digital converter according to claim 1 ,wherein the first ...

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Номер записи: 87
28-02-2019 дата публикации

TIME-TO-DIGITAL CONVERTER, CIRCUIT DEVICE, PHYSICAL QUANTITY MEASURING DEVICE, ELECTRONIC APPARATUS, AND VEHICLE

Номер: US20190064748A1
Автор: Haneda Hideo
Принадлежит:

A time-to-digital converter includes first and second oscillation circuits, first and second sampling circuits, and a processing circuit. The first and second oscillation circuits start an oscillation operation in accordance with first and second signals and output first and second clock signals, respectively. The first and second sampling circuits perform sampling of the first and second clock signals by a first reference clock signal and output first and second output signals, respectively. The processing circuit obtains first frequency information and first phase information of the first clock signal and second frequency information and second phase information of the second clock signal based on the first and second output signals of the first and second sampling circuits, and obtains a digital value corresponding to a time difference of a transition timing between the first and second signals. 1. A time-to-digital converter comprising:a first oscillation circuit that starts an oscillation operation in accordance with a first signal and outputs a first clock signal;a second oscillation circuit that starts an oscillation operation in accordance with a second signal and outputs a second clock signal;a first sampling circuit that performs sampling of the first clock signal by a first reference clock signal and outputs a first output signal;a second sampling circuit that performs sampling of the second clock signal by the first reference clock signal and outputs a second output signal; anda processing circuit that obtains first frequency information and first phase information of the first clock signal and second frequency information and second phase information of the second clock signal based on the first output signal of the first sampling circuit and the second output signal of the second sampling circuit, and obtains a digital value corresponding to a time difference of a transition timing between the first signal and the second signal based on the first ...

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Номер записи: 88
28-02-2019 дата публикации

Time-To-Digital Converter, Circuit Device, Physical Quantity Measurement Apparatus, Electronic Instrument, And Vehicle

Номер: US20190064749A1
Автор: SUDO Yasuhiro
Принадлежит:

A time-to-digital converter includes a first oscillation circuit that starts oscillating at the transition timing of a first signal and generates a first clock signal having a first clock frequency, a second oscillation circuit that starts oscillating at the transition timing of a second signal and generates a second clock signal having a second clock frequency, a first adjustment circuit that adjusts the oscillation frequency of the first oscillation circuit based on a reference clock signal, a second adjustment circuit that adjusts the oscillation frequency of the second oscillation circuit based on the reference clock signal, and a processing circuit that converts the time difference between the transition timing of the first signal and the transition timing of the second signal into a digital value based on the first and second clock signals. 1. A time-to-digital converter comprising:a first oscillation circuit that starts oscillating at a transition timing of a first signal and generates a first clock signal having a first clock frequency;a second oscillation circuit that starts oscillating at a transition timing of a second signal and generates a second clock signal having a second clock frequency different from the first clock frequency;a first adjustment circuit that measures the first clock frequency based on a reference clock signal and adjusts an oscillation frequency of the first oscillation circuit in such a way that the first clock frequency is equal to a first target frequency;a second adjustment circuit that measures the second clock frequency based on the reference clock signal and adjusts an oscillation frequency of the second oscillation circuit in such a way that the second clock frequency is equal to a second target frequency; anda processing circuit that converts a time difference between the transition timing of the first signal and the transition timing of the second signal into a digital value based on the first and second clock signals.2. ...

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Номер записи: 89
28-02-2019 дата публикации

BODY INFORMATION ANALYSIS APPARATUS AND METHOD OF ESTIMATING REMAINING CAPACITY OF COSMETIC PRODUCT THEREOF

Номер: US20190065531A1
Автор: CHI Min-Chang, SHEN Shyh-Yong, TSAI Ching-Sheng
Принадлежит:

A body information analysis apparatus () and method of estimating remaining capacity of cosmetic product thereof are disclosed. The method includes following steps of: controlling a body information analysis apparatus () to configure a plurality of cosmetic product data respectively corresponding to different cosmetic products; updating an remaining capacity of each cosmetic product data according to a use record of the body information analysis apparatus () and a reference consumption amount of each cosmetic product data; sending a reminder message when the remaining capacity of any of the plurality of cosmetic product data is less than a safety capacity; and, retrieving feedback data corresponding to the cosmetic product data and updating the remaining capacity of the cosmetic product data according to the feedback data. 1. A method of estimating remaining capacity of cosmetic product , the method comprising:{'b': '10', 'a) using a body information analysis apparatus () to receive a cosmetic product configuration operation to configure a plurality of cosmetic product data and configure a remaining capacity for each of the cosmetic product data, wherein each of the cosmetic product data is corresponding to a cosmetic product;'}{'b': '10', 'b) adjusting the remaining capacity for each of the cosmetic product data based on a usage record of the body information analysis apparatus () and a reference consumption amount of the cosmetic product data;'}c) sending a reminder message when the remaining capacity of any of the cosmetic product data is less than a safety capacity;d) receiving a feedback operation to configure a feedback data for any of the cosmetic product data; ande) modifying the remaining capacity of the cosmetic product data based on the feedback data for the cosmetic product.2. The method in claim 1 , wherein the step a) further comprises:{'b': 20', '10, 'a1) photo-taking an image of any of the cosmetic product by an image fetching unit () of the body ...

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Номер записи: 90
05-06-2014 дата публикации

Oversampling time-to-digital converter

Номер: US20140152484A1
Автор: Masao Takayama, Shiro Dosho
Принадлежит: Panasonic Corp

An oversampling time-to-digital converter includes an input pulse generation circuit generating two pulse signals, a reference pulse generation circuit generating two pulse signals, a swap circuit swapping two pulse signals, a multiplexer selecting an output of the input pulse generation circuit or the swap circuit, a time-to-current conversion circuit outputting two pulse currents in accordance with an output of the multiplexer, a current mirror circuit whose input and output terminals receive the two pulse currents, an integration circuit integrating a differential current between the pulse current connected to the output terminal of the current mirror circuit and an output current of the current mirror circuit, and a comparison circuit comparing an output signal of the integration circuit to a threshold voltage. An output signal of the comparison circuit is given to the swap circuit as a control signal.

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Номер записи: 91
19-03-2015 дата публикации

ENVIRONMENT-RESOLUTION CORRELATED TIMER

Номер: US20150078142A1
Автор: Loomis Jason
Принадлежит: Loominocity, Inc.

Apparatus and associated methods relate to a timer having multiple time resolutions corresponding to multiple environmental climates. Climates may include, for example, temperature, humidity, pressure, or any of these taken alone or in combination. Climates may include, for example, carbon monoxide content, oxygen content, toxic gases, or any of these taken alone or in combination. The resolutions and climates may be particular to selected applications, including but not limited to, perishable foods, chemicals (e.g. alcohol, cement, pharmaceuticals), or perishable evidence (e.g. crime scene materials). In one embodiment, a breast-milk timer may have three times scales, an hourly scale corresponding to room-temperature environment, a daily scale corresponding to refrigeration, and a monthly scale corresponding to a freezer environment. As time elapses, the timer may automatically transition from the hourly scale to the daily scale and then to the monthly scale. Such a timer may quickly communicate breast milk freshness. 1. A perishable-food timer for indicating the elapsed time of storage of a perishable-food item , the perishable-food timer comprising:a input control device, configured to accept inputs from a user;an elapsed-time counter coupled to the input control device and configured to be supplied power by a battery, the elapsed-time counter counts the elapsed time as measured from the time a begin-count-mode command is input by the user to the input control device;a display face comprising three display regions, a first display region indicating to the user that the timing is for storage of the perishable-food item in a room-temperature environmental climate, a second display region indicating to the user that the timing is for storage of the perishable-food item in a refrigerator environmental climate, and a third display region indicating to the user that the timing is for storage of the perishable-food item in a freezer environmental climate;an attachment ...

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Номер записи: 92
24-03-2022 дата публикации

PHOTON-BASED TARGET DETECTION USING COARSE AND FINE BINNING

Номер: US20220091239A1
Автор: BOLATKALE Muhammed, Kulesh Maxim, SON Dongjin
Принадлежит:

Exemplary aspects of the present disclosure involve a SPAD receiver having circuitry for photon detection and having a plurality TDCs (time-to-digital converters) to detect multiple photons. Such circuitry may be set to accumulate photon counts over relatively coarse time ranges. In such accumulation of photons in relatively coarse time ranges, photon counts may be binned for each time range. Possible targets may then be identified by examination of the bins. Upon identification of the possible targets, a plurality of TDCs may be used over a more refined time ranges such as the time ranges corresponding to the identified possible target or targets. 1. A method comprising:operating a receiver, having SPAD (single-photon avalanche photodiode) circuitry for photon detection, with multiple photon detections using a plurality of TDCs (time-to-digital converters) being set to accumulate detected photon counts over relatively coarse time ranges;binning and identifying one or more possible target bins associated with the detected photon counts accumulated over the relatively coarse time ranges; andusing the plurality of TDCs to accumulate detected photon counts over one or more relatively fine time ranges corresponding to the identified one or more possible target bins.2. The method of claim 1 , wherein operating the receiver is for Lidar (Light Detection and Ranging) detection of at least one object that is among said one or more possible target bins associated with said binning and identification claim 1 , and further including operating the receiver is for more refined Lidar detection of said at least one object.3. The method of claim 1 , further including: accumulating detected photon counts in an array of bins in response to being detected; and operating the receiver for Lidar (Light Detection and Ranging) detection of at least one object in an environment that causes at least one of the bins in said array of bins to be associated with said at least one object and at ...

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Номер записи: 93
16-03-2017 дата публикации

Method and apparatus for conversion of time interval to digital word using successive approximation sheme

Номер: US20170075311A1
Автор: Dariusz Koscielnik, Marek Miskowicz
Принадлежит: Akademia Gomiczo Hutnicza

A method and apparatus for conversion of a time interval to a digital word, the time interval being mapped to a difference of a length of a reference time and a length of a signal time. Reference time is generated from an instant when the beginning of the time interval is detected, and the signal time is generated from an instant when the end of the time interval is detected by the use the control module. The generation of the reference time and the signal time is terminated at the same instant. In the apparatus, bottom plates of capacitors of the set of capacitors are connected to a ground of the circuit, and top plates of these capacitors are connected, respectively, to moving contacts of change-over switches. First, second, and third stationary contacts are connected to the signal rail, the ground of the circuit, and to the reference rail (R).

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Номер записи: 94
05-03-2020 дата публикации

CAPATICANCE-TO-DIGITAL CONVERTER

Номер: US20200073334A1
Автор: Buter Berry Anthony Johannus, Fan Hao, Pertijs Michiel
Принадлежит:

A capacitance-to-digital-converter includes a first delay block configured to output a first signal after a first delay based on a voltage at a capacitive sensor, the capacitive sensor configured to be iteratively discharged; a second delay block configured to output a second signal after a second delay; and a capacitance determination unit configured to determine a value indicative of a capacitance sensed by the capacitive sensor. This determination is based on: a number of clock periods during which the first delay is less than a third delay; a first time difference between receipt of the first signal and the second signal during a last clock period during which the first delay is less than the third delay; and a second time difference between receipt of the first signal and receipt of the second signal during a first clock period during which the first delay is greater than the third delay. 1. A capacitance to digital converter comprising:a first delay block having an input node configured to receive a voltage from a capacitive sensor and a clock node configured to receive a clock signal defining a clock period until a subsequent clock signal, the first delay block configured to output a first output signal after a first delay time in response to receiving the clock signal each clock period, the first delay time based on the voltage at the input node, and wherein the first delay block is configured to provide for iterative discharging of the capacitive sensor based on the clock signal;a second delay block having an input node configured to receive a first voltage and a clock node configured to receive the clock signal, the second delay block configured to output a second output signal after a second delay time in response to the clock signal, the second delay time based on the first voltage; and the number of clock periods during which the first delay time is less than a third delay time;', 'a first time difference between a time of receipt of the first output ...

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Номер записи: 95
15-03-2018 дата публикации

SYSTEM AND METHOD OF CALIBRATING INPUT SIGNAL TO SUCCESSIVE APPROXIMATION REGISTER (SAR) ANALOG-TO-DIGITAL CONVERTER (ADC) IN ADC-ASSISTED TIME-TO-DIGITAL CONVERTER (TDC)

Номер: US20180076821A1
Автор: Loke Wing-Fai, Yao Chih-Wei
Принадлежит:

An apparatus and a method. The apparatus includes a counter array; a ring oscillator that is electrically coupled to the counter array, where the counter array counts a number of cycles in the ring oscillator; an analog-to-digital converter (ADC) driver that is electrically coupled to the ring oscillator; and an ADC that is electrically coupled to the ADC driver, where an output of the ADC is electrically coupled to the ring oscillator. 1. An apparatus , comprising:a counter array;a ring oscillator that is electrically coupled to the counter array, where the counter array counts a number of cycles in the ring oscillator;an analog-to-digital converter (ADC) driver that is electrically coupled to the ring oscillator; andan ADC that is electrically coupled to the ADC driver, where an output of the ADC is electrically coupled to the ring oscillator.2. The apparatus of claim 1 , further comprising a phase/frequency detector (PFD) connected to the ring oscillator that includes a first input for receiving a reference clock signal claim 1 , a second input for receiving a feedback clock signal claim 1 , and an output for providing an enable signal.3. The apparatus of claim 1 , further comprising a plurality of time-to-digital-converter (TDC) buffers connected to the outputs of the ring oscillator.4. The apparatus of claim 3 , further comprising an interpolating resistive network connected to outputs of the plurality of TDC buffers.5. The apparatus of claim 3 , further comprising a multiplexer connected to the outputs of the TDC buffers.6. The apparatus of claim 5 , further comprising a programmable analog-to-digital converter (ADC) driver connected to an output of the multiplexer.7. The apparatus of claim 1 , wherein the ring oscillator includes a plurality of buffers connected in a ring claim 1 , and wherein each of the outputs of the ring oscillator are connected to one of the plurality of buffers claim 1 , respectively.8. The apparatus of claim 1 , further comprising a ...

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Номер записи: 96
16-03-2017 дата публикации

AUTO FREQUENCY CALIBRATION METHOD

Номер: US20170077932A1
Автор: CHEN Huan-Neng, CHEN Yen-Jen, JOU Chewn-PU, KUO Feng Wei
Принадлежит:

A method of generating an output signal includes determining a sampling period N according to a number of most significant bits (MSBs) of a divider number control signal. The method also includes determining a first logic value of a control signal by a comparing circuit based on the sampling period N, and generating a coarse tuning signal by a code generating circuit based on a phase difference signal and the control signal. When an M-th least significant bit (LSB) of the number of MSBs of the divider number control signal equals a second logic value, the sampling period N is set based on the M-th LSB of the number of MSBs of the divider number control signal. 1. A method of generating an output signal , the method comprising:determining a sampling period N according to a number of most significant bits (MSBs) of a divider number control signal;determining a first logic value of a control signal by a comparing circuit based on the sampling period N; andgenerating a coarse tuning signal by a code generating circuit based on a phase difference signal and the control signal, whereinwhen an M-th least significant bit (LSB) of the number of MSBs of the divider number control signal equals a second logic value, the sampling period N is set based on the M-th LSB of the number of MSBs of the divider number control signal.2. The method of claim 1 , further comprising:generating a fine tuning signal by a digital loop filter based on the phase difference signal.3. The method of claim 2 , further comprising:adjusting an output frequency of the output signal by a voltage controlled oscillator based on the coarse tuning signal and the fine tuning signal.4. The method of claim 1 , further comprising:determining if (M+1) LSB equals the second logic value when the M-th LSB of the number of MSBs of the divider number control signal does not equal the second logic value.5. The method of claim 1 , wherein determining the sampling period N according to the number of MSBs of the divider ...

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Номер записи: 97
18-03-2021 дата публикации

CIRCUIT, CHIP AND SEMICONDUCTOR DEVICE

Номер: US20210080503A1
Автор: CHANG Chih-Hsien, Li Chao Chieh, Liao Chia-Chun, YUAN Min-Shueh
Принадлежит:

A circuit is disclosed. The circuit includes a time-to-digital converter (TDC), and an evaluation circuit coupled to the TDC and a phase-locked loop (PLL) external to the circuit. 1. A circuit , comprising:a time-to-digital converter (TDC); andan evaluation circuit coupled to the TDC and a phase-locked loop (PLL) external to the circuit.2. The circuit of claim 1 , wherein the TDC is configured to receive a first signal having an identification and a first frequency claim 1 , and output a digital signal associated with the identification of the first signal to the evaluation circuit.3. The circuit of claim 2 , wherein the identification comprises a duty cycle.4. The circuit of claim 2 , further comprising: a frequency divider coupled to the TDC to provide a second signal having a second frequency to the TDC.5. The circuit of claim 4 , wherein the digital signal is generated based on the second signal from the frequency divider.6. The circuit of claim 4 , wherein the digital signal is generated by sampling the first signal by means of the second signal.7. The circuit of claim 1 , wherein the TDC comprises:a first buffer having a first input and a first output;a second buffer having a second input coupled to the first output of the first buffer, and a second output;a first sampling circuit having a first input coupled to the first output of the first buffer, a second input, and a first output; anda second sampling circuit having a third input coupled to the second output of the second buffer, a fourth input coupled to the second input of the first sampling circuit, and a second output.8. The circuit of claim 7 , wherein the first input of the first buffer is configured to receive a first signal having an identification and a first frequency.9. The circuit of claim 8 , further comprising a frequency divider claim 8 , wherein the second input of the first sampling circuit is coupled to the frequency divider to receive a second signal having a second frequency.10. The ...

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Номер записи: 98
26-03-2015 дата публикации

APPARATUS FOR MEASURING RESPONSE TIME, SYSTEM FOR MEASURING RESPONSE TIME AND METHOD FOR MEASURING RESPONSE TIME

Номер: US20150088460A1
Автор: LEE Sam Won
Принадлежит: DOOSAN HEAVY INDUSTRIES & CONSTRUCTION CO., LTD.

Example embodiments relate to a response time measurement apparatus, a response time measurement system and a response time measurement method for measuring a response output time from a facility corresponding to an input signal, and more particularly, a response time measurement apparatus, a response time measurement system and a response time measurement method in which the output display of a facility is captured through a capture device to detect an output time on the basis thereof. 1. A response time measurement apparatus , comprising:a transceiver configured to receive capture information from a capture device for capturing an output screen of a measurement facility; anda controller configured to apply a test signal to the measurement facility through the transceiver, and detect an output time, the output time being a time at which a response corresponding to the test signal is displayed on the output screen based on the capture information, the controller further configured to measure a response time of the measurement facility based on the output time.2. The response time measurement apparatus of claim 1 , wherein the capture information includes at least one of an image claim 1 , a video claim 1 , and time information associated with the capturing.3. The response time measurement apparatus of claim 1 , wherein the test signal is a control signal for inducing a desired output to be displayed on the output screen of the measurement facility.4. The response time measurement apparatus of claim 1 , wherein the controller is configured to calculate a time difference between a time at which the test signal is applied and the output time claim 1 , and measure the time difference as the response time of the measurement facility.5. The response time measurement apparatus of claim 1 , whereinthe capture information comprises a plurality of images consecutively captured by the capture device and time information for each captured image, andthe controller is configured ...

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Номер записи: 99
24-03-2016 дата публикации

PHASE TRACKER FOR A PHASE LOCKED LOOP

Номер: US20160087639A1
Автор: Mayer Andreas, Mayer Thomas, Tracht Thorsten, Wicpalek Christian
Принадлежит:

A phase locked loop includes a feedforward path receiving a reference signal having a reference frequency and outputting an output signal having an output frequency that is a function of the reference signal and a feedback signal. The phase locked loop further includes a feedback path having a divider circuit associated therewith that is configured to receive the output signal and generate the feedback signal having a reduced frequency based on a divide value of the divider circuit. The feedback signal is supplied to the feedforward path. The phase locked loop also includes a modulator circuit configured to receive modulation data and provide a divider control signal to the divider circuit to control the divide value thereof, and a phase tracker circuit configured to determine an amount of phase drift from an initial phase value of the output signal due to an interruption in a locked state of the phase locked loop. 1. A phase locked loop , comprising:a phase locked loop circuit configured to output an output signal based on a reference frequency and a current channel word; anda phase tracking circuit configured to determine a phase drift amount of the output signal based on a previous channel word and the current channel word of the phase locked loop circuit.2. The phase locked loop of claim 1 ,wherein the phase tracking circuit comprises an accumulator circuit that accumulates a difference between an input sequence and the previous channel word,wherein the input sequence includes the current channel word and modulation data, andwherein the accumulated difference represents the phase drift amount.3. The phase locked loop circuit of claim 1 , wherein the phase tracking circuit comprises:a first calculation circuit configured to calculate a frequency control word based on the current channel word and modulation data;a second calculation circuit configured to determine a difference between the frequency control word and the previous channel word, wherein the difference ...

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Номер записи: 100