МАТРИЦА ДЕТЕКТОРОВ С АНАЛОГО-ЦИФРОВЫМ ПРЕОБРАЗОВАНИЕМ ВРЕМЕНИ, ИМЕЮЩАЯ ПОВЫШЕННУЮ ВРЕМЕННУЮ ТОЧНОСТЬ

Изобретение относится к области регистрации излучения. Способ детектирования излучения содержит этапы, на которых регистрируют событие; генерируют инициирующий сигнал, ассоциированный с регистрацией события; генерируют первую метку (TS1) времени для инициирующего сигнала с использованием первого аналого-цифрового преобразователя времени (TDC); генерируют вторую метку (TS2) времени для инициирующего сигнала с использованием второго TDC, имеющего фиксированное смещение по времени относительно первого TDC; и связывают метку времени с событием на основе первой метки времени, второй метки времени и сравнения разницы по времени между второй меткой времени и первой меткой времени и фиксированного смещения по времени. Технический результат - повышение качества ПЭТ-изображения. 4 н. и 19 з.п. ф-лы, 9 ил.

СХЕМНОЕ УСТРОЙСТВО И СПОСОБ ИЗМЕРЕНИЯ ДРОЖАНИЯ ТАКТОВОГО СИГНАЛА

... 1. Способ, содержащий этапы, на которых: ! принимают тактовый сигнал в цепи задержки схемного устройства; ! определяют значение тактового сигнала в выбранной точке в цепи задержки; и ! регулируют выбранную точку, когда значение не указывает обнаружение требуемой части тактового сигнала. ! 2. Способ по п.1, в котором требуемая часть содержит одно из переднего фронта, заднего фронта и части уровня тактового сигнала. ! 3. Способ по п.1, дополнительно содержащий этап, на котором определяют тактовый интервал, когда выбранная точка указывает обнаружение требуемой части тактового сигнала. ! 4. Способ по п.3, дополнительно содержащий этапы, на которых: ! определяют допустимый запас на ошибку, ассоциированный с обнаружением требуемой части тактового сигнала; и ! сдвигают время, в которое тактовый сигнал принимают в цепи задержки, на известное временное приращение, когда допустимый запас на ошибку превышает пороговое значение ошибки. ! 5. Способ по п.4, в котором цепь задержки содержит множество ...

Vorrichtung für Zeitinterpolation

Histogramm-Ausleseverfahren und Histogramm-Ausleseschaltkreis zum Ermitteln der Flugzeit eines Photons

Es ist ein Histogrammerstellungs-Ausleseschaltkreis beschrieben. Der Ausleseschaltkreis umfasst einen Zeit/Digitalwandler (TDC), der ausgestaltet ist, um kontinuierlich Zeitstempel, die eine Ankunftszeit eines Lasertakts und einen Signalausgang von einem Fotosensor definieren, anzugeben. Es ist Speicher vorgesehen, um TDC-Ereignisse zu speichern. Ein programmierbarer Prozess ist konfiguriert, um eine Zustandsmaschine zu implementieren. Die Zustandsmaschine ist betreibbar, um einen Zeitstempel zu speichern, wenn ein TDC-Ereignis detektiert wird; die Flugzeit jedes der Photonen, die von dem Fotosensor detektiert werden, zu ermitteln; jede berechnete Flugzeit zu verwenden, um eine Speicherstelle zu adressieren; ein Histogramm der TDC-Datenwerte unter Verwendung der Speicherstellen als Zeit-Bins aufzubauen; und einen Zeiger auf einer Maximumspeicherstelle zu halten, wo sich die höchste Zahl von TDC-Ereignissen befindet. Ein Berechnungseinrichtung ist betreibbar, um den Wert der Maximumspeicherstelle ...

Ringförmiger Zeit-Digital-Wandler und dessen Verfahren

Die vorliegende Erfindung stellt einen ringförmigen Zeit-Digital-Wandler und dessen Verfahren zur Verfügung. Der ringförmige Zeit-Digital-Wandler weist auf: einen Impulsformer zur Formung des eingegebenen Startimpulses und Stoppimpulses in einen Impulsausgang mit der festen Breite; mindestens zwei Differenzvergleichseinheiten, die dazu dienen, dass bei der Anpassungsfreigabe der Trigger in der Differenzvergleichseinheit das Einstellende auf 1 einstellt; einen Kreiszähler zur Zählung der Anzahl der Ausbreitung eines Impulses im Kreis; eine Anpassungsfreigabelogikeinrichtung, die dazu dient, das Anpassungsfreigabesignal zu erzeugen und das erzeugte Anpassungsfreigabesignal an den Vergleichsfreigabeanschluss der Differenzvergleichseinheit zu übertragen; mindestens zwei Ringsinnenpositionscodierer zum Auffinden der Position der ersten angepassten Einheit in Übereinstimmung mit dem von den Differenzvergleichseinheiten übertragenen Anpassungssignal; ein Ergebnisaufnahmeregister zur Erfassung ...

Vorrichtung und Verfahren zum Schätzen von Daten, die sich auf eine Zeitdifferenz beziehen, und Vorrichtung und Verfahren zum Kalibrieren einer Verzögerungsleitung

Eine Vorrichtung zum Schätzen von Daten, die sich auf eine Zeitdifferenz zwischen zwei Ereignissen beziehen, umfasst eine Verzögerungsleitung (100) mit einer Mehrzahl von Stufen (101, 102, 103, 104). Jede Stufe weist eine Verzögerungsdifferenz auf zwischen einer ersten Verzögerung in einem ersten Teil und einer zweiten Verzögerung in einem zweiten Teil. Diese Verzögerungsdifferenz wird gemessen durch eine Phasenentscheidungsvorrichtung (105) in jeder Stufe, die ein Anzeigesignal ausgibt, das anzeigt, ob das erste Ereignis von zwei Ereignissen in dem ersten Teil einem zweiten Ereignis der zwei Ereignisse in dem zweiten Teil vorausgeht oder folgt. Eine Summationsvorrichtung (200) ist vorgesehen zum Summieren über die Anzeigesignale der Mehrzahl von Stufen, um einen Summenwert (201) zu erhalten. Der Summenwert zeigt eine Zeitdifferenzschätzung an.

Vorrichtung zur Zeit-zu-Digital-Wandlung mit geregelter zeitlicher Wavelet-Kompression mittels eines Sende-Wavelets mit geregelter Verzögerung und eines Analyse-Wavelets

Die Vorrichtung führt ein Verfahren zur Bestimmung der Verzögerungszeit eines ersten Wavelets in einer Übertragungsstrecke (I1) aus. Hierzu wird das erste Wavelet zu einem Zeitpunkt nach einem Referenzzeitpunkt in die Übertragungstrecke hineingesendet. Nach Durchgang durch die Übertragungsstrecke wird das verzögerte und typischerweise deformierte Wavelet mit einem zweiten Wavelet skalar-multipliziert. Das Ergebnis wird mit einem Referenzwert verglichen. Zu einem Schneidezeitpunkt (ts) schneidet der Skalar-Produktwert den Referenzwert. In Abhängigkeit von diesem Schneidezeitpunkt (ts) bezogen auf den Referenzzeitpunkt wird die Verzögerung des ersten und/oder zweiten Wavelets gegenüber dem Referenzzeitpunkt geregelt. Eine Amplitudenregelung findet nicht statt.

VERBESSERUNGEN AN ANALOG-DIGITAL-UMSETZERN AUF RAMPENBASIS

Methods for determining the frequency or period of a signal

IMPROVEMENTS ON ENCODERS ON RAMP BASIS

ULTRASCHNELLER TIME-NUMERIC TRANSFORMER.

Card detector and card detection method

Circuit device and method of measuring clock jitter

DEVICE AND METHOD FOR PRECISE EVENT DATING USING AN ANALOG-TO-DIGITAL CONVERTER

TIME-TO-DIGITAL CONVERTER-BASED ALL DIGITAL DELAY-LOCKED LOOP AND CONTROLLING METHOD THEREOF

The present invention relates to a time-to-digital converter-based complete digital delay-locked loop and a controlling method thereof. The present invention provides the time-to-digital converter-based complete digital delay-locked loop including: a phase reverse locking control circuit outputting an input clock or a reversed input clock by determining the use of a phase reverse locking algorithm by comparing a phase difference between the input clock and an output clock and a phase synchronization unit receiving output signals and controlling signals of the phase reverse locking control circuit and performing phase synchronization and the control method thereof. The phase synchronization unit includes a digital control delay line reducing a phase error between the input clock and the output clock by receiving the input clock or the reversed input clock outputted from the phase reverse locking control circuit. The digital control delay line includes: a coarse digital delay line removing ...

Hybrid analog-to-digital converter

An analog-to-time converter circuit includes a current source; a first amplifier coupled to the current source through a first discharging switch; and a second amplifier coupled to the first amplifier through a second discharging switch; wherein the first amplifier is configured to receive a residue signal of an analog input signal, upon the first discharging switch being turned on, the first amplifier amplifies the residue signal to generate an output signal and simultaneously the current source discharges the residue signal, upon the second discharging switch being turned on, the second amplifier detects when the output signal equals zero so as to determine a discharging time duration of the output signal.

INTEGRATED MULTI-CHANNEL TIME-TO-DIGITAL CONVERTER FOR TIME-OF-FLIGHT PET

In a radiation detector (10) for a time of flight positron emission tomography (PET) scanner (2), a radiation sensitive member (20) generates a signal (22) indicative of a radiation detection event. A time to digital converter (34) includes digital delay elements (40) operatively interconnected as a ring oscillator (36, 36') and readout circuitry (50, 52, 60, 82, 84, 86, 88) configured to generate a timestamp for the radiation detection event based at least on a state of the ring oscillator when the signal is generated. Delay trim elements (46) operatively connected to the digital delay elements set a substantially common delay for the digital delay elements. Additionally or alternatively, the digital delay elements (40) include readout buffers (48') having transition times substantially longer than a delay of the digital delay elements, analog to digital converters (82, 84) digitize values of the delay elements, and decoding circuitry (86, 88) computes the state of the ring oscillator ...

TIME INTERVAL VOLTAGE CONVERTER

The proposed converter consists of a pulse generator (1) connected to a pulse counter (2) whose outputs enter the inputs of the decoders (3 and 4). A short pulse from the output of the decoder (4) enters the control input of the switch (11) whose signal input is connected to the output of the controlled current generator (6), the sensor (8) and one input of the differential amplifier (7). The output of the switch (11) is connected to an analogue memory unit (10) whose output voltage is the reference for the functional converter (5) and comparator (9). A long pulse from the output of the decoder (3) enters the input of the functional converter (5) where it is converted into voltage of a particular form in accordance with the set program and enters the input of the controlled current generator (6) which forms a current at its output in accordance with the function of the functional converter (5). The signal from the output of the differential amplifier (7), whose inputs are connected to the ...

Detection arrangement, counter unit, phase locked loop, detection method and method for generating an oscillator signal

A detection arrangement includes a counter unit which receives a first clock signal and a reference clock signal. The counter unit derives a first data word as a function of a time deviation between clock edges of the first clock signal and the reference clock signal. The detection arrangement further includes a signal processing unit to determine a phase deviation word as a function of the first data word and a second data word, the second data word based on the duration of a clock period of the reference clock signal.

Aperture noise suppression using self-referred time measurements

A system and method for suppressing aperture noise resulting from clock jitter associated with a Nyquist analog-to-digital converter (ADC) using self-referred time measurements are provided. The system comprises of a clock, a delay element, a time subtractor, a time-to-digital converter, a filter element, a first digital subtractor, an integrator, a differentiator, and a multiplier. Each of the delay element, time subtractor, time-to-digital converter, filter element, first digital subtractor, integrator, and multiplier is electrically connected in parallel with the ADC, which allows the clock to generate a clock signal that advances into the system and the ADC in order to isolate and suppress the noise aperture associated with the ADC. As such, the architecture of the system is configured to isolate and suppress aperture noise resulting from clock jitter associated with an analog-to-digital converter (ADC) to allow the output signal of the system be independent of the aperture noise.

TIME-TO-DIGITAL CONVERTER

An apparatus is provided which comprises: a first clock line to provide a first clock; a second clock line to provide a second clock; a delay line having a plurality of delay cells, wherein the delay line is coupled to the first and second clock lines, wherein the first clock is to sample the second clock; and circuitry coupled to the delay line, wherein the circuitry is to determine first or latest edge transitions from the outputs of the plurality of delay cells.

High-resolution time-to-digital converter and method thereof

A circuit includes: a rectifier configured to receive a first clock signal and a second clock signal and output a rectified signal, wherein the second clock signal is the same as the first clock signal except for an offset in timing; a low-pass filter configured to receive the rectified signal and output a filtered signal; and an analog-to-digital converter configured to convert the filtered signal into a digital signal.

Noise-shaping time-to-digital converter

A noise-shaping time-to-digital converter has a large range and high resolution. The time-to-digital converter includes a phase detector configured to generate a phase error signal based on a phase-adjusted feedback signal and an input signal. The time-to-digital converter includes a loop filter configured to integrate the phase error signal and generate an analog integrated phase error signal. The time-to-digital converter includes an analog-to-digital converter configured to convert the analog integrated phase error signal to a digital phase error code. The time-to-digital converter includes a digital-to-time converter configured to convert at least a portion of the digital phase error code to a gating signal based on a reference signal and an enable signal. The time-to-digital converter includes a feedback circuit to generate the phase-adjusted feedback signal based on the reference signal and the gating signal.

METHOD FOR FORMING A DIGITAL VALUE FROM A CLOCK SIGNAL AND FROM A DATA SIGNAL

A method forms a digital value from a clock signal and a digital data signal. The method includes sampling the clock signal in order to obtain a clock signal digital value sequence and sampling the digital data signal in order to obtain a data signal digital value sequence. Sampling points are ascertained from the clock signal digital value sequence, at which data signal digital values are extracted from the data signal digital value sequence. The digital value is formed from the data signal digital values. 1. A method for forming a digital value from a clock signal and a digital data signal , the method comprising:sampling the clock signal in order to obtain a clock signal digital value sequence,sampling the digital data signal in order to obtain a data signal digital value sequence,ascertaining sampling points from the clock signal digital value sequence, at which data signal digital values are extracted from the data signal digital value sequence, andforming the digital value from the data signal digital values.2. The method as claimed in claim 1 , wherein the sampling points are determined from value changes in the clock signal digital value sequence.3. The method as claimed in claim 1 , wherein the clock signal digital value sequence is a binary value sequence.4. The method as claimed in claim 1 , wherein the clock signal is oversampled.5. The method as claimed in claim 1 , wherein the digital data signal is oversampled claim 1 , or is sampled only at the sampling points claim 1 , in order to obtain the data signal digital value sequence.6. The method as claimed in claim 1 , wherein the data signal digital value sequence is a binary value sequence.7. The method as claimed in claim 6 , wherein the digital value is formed from the data signal digital values claim 6 , in that the data signal digital values form the bits of the digital value.8. The method as claimed in claim 1 , further comprising sampling a frame signal in order to obtain a frame signal digital ...

Hybrid analog-to-digital converter

An analog-to-digital converter (ADC) circuit is configured to receive an analog input signal and convert the analog input signal to a digital output signal. The ADC circuit includes a first circuit that is configured to convert the analog input signal into a first digital signal that includes a first subset of bits of the digital output signal and further provide a residue signal based on the first digital signal; and a second circuit, coupled to the first circuit, and is configured to determine a discharging time duration by simultaneously amplifying and discharging the residue signal.

Time-to-digital converter (TDC) with offset cancellation

Described is an apparatus which comprises: a switching device to receive first and second inputs, and to generate first and second outputs; and a time-to-digital converter (TDC) core to receive the first and second outputs, and to generate a third output, wherein the switching device is operable to couple the first input to the first output or to couple the first input to the second output according to a control input.

Phase tracker for a phase locked loop

A phase locked loop includes a feedforward path receiving a reference signal having a reference frequency and outputting an output signal having an output frequency that is a function of the reference signal and a feedback signal. The phase locked loop further includes a feedback path having a divider circuit associated therewith that is configured to receive the output signal and generate the feedback signal having a reduced frequency based on a divide value of the divider circuit. The feedback signal is supplied to the feedforward path. The phase locked loop also includes a modulator circuit configured to receive modulation data and provide a divider control signal to the divider circuit to control the divide value thereof, and a phase tracker circuit configured to determine an amount of phase drift from an initial phase value of the output signal due to an interruption in a locked state of the phase locked loop.

SYSTEMS AND METHODS FOR PERFORMING ANALOG-TO-DIGITAL CONVERSION ACROSS MULTIPLE, SPATIALLY SEPARATED STAGES

The invention provides a signal processing system, for transferring analog signals from a probe to a remote processing unit. The system comprises a first ASIC at a probe, which is adapted to receive an analog probe signal. The first ASIC comprises an asynchronous sigma-delta modulator, wherein the asynchronous sigma-delta modulator is adapted to: receive the analog probe signal; and output a binary bit-stream. The system further comprises a second ASIC at the remote processing unit, adapted to receive the binary bit-stream. The asynchronous may further include a time gain function circuit, the first ASIC may further comprise a multiplexer, the second ASIC may further comprise a time-to-digital converter. The time to digital converter may be a pipelined time-to-digital converter. 1. A system for performing analog-to-digital conversion , the system comprising: receive an analog signal; and', 'output a binary bit-stream comprising asynchronous time-domain pulses;, 'a probe having a first ASIC, wherein the first ASIC is adapted to receive the binary bit-stream; and', 'generate a digital output from the binary bit-stream based on time-to-digital conversion; and, 'a processing unit having a second ASIC, wherein the second ASIC comprises a time-to-digital converter adapted toa data channel adapted to propagate the binary bit-stream from the first ASIC to the second ASIC, wherein the first and second ASICs are spatially separated.2. A system as claimed in claim 1 , wherein claim 1 , and wherein: [ receive the binary bit-stream; and', a coarse digital output; and', 'a coarse residue time; and, 'output], 'a coarse time-to-digital converter, wherein the coarse time-to-digital converter is adapted to, [ 'receive an incoming residue time from the previous fine, or coarse, time-to-digital converter in the series;', 'one or more fine time-to-digital converters connected in series, each adapted to, 'output an outgoing residue time to the subsequent fine time-to-digital converter in ...

APPARATUS AND METHOD FOR LOW LATENCY, RECONFIGURABLE AND PICOSECOND RESOLUTION TIME CONTROLLER

A reconfigurable and timely accurate method of generating, with a low latency, an output signal in response to multiple input signals, wherein said input signals occur at independent times, and wherein the occurrence of several input signals according to predetermined pattern is interpreted as a Super Event and wherein a detected Super Event triggers the production of a specific output signal heralding this Super Event, characterized in that said method comprises a first step of time acquisition of the occurrence of said input signals, a second step of adaptation of the acquisition data flow to the clock of the reconfigurable processing unit, a third step of determining the occurrence of a Super Event by comparing the events pattern to the super event definition, a fourth step identifying the Super Event and generating at least one event/signal corresponding to at least one trigger signal, a fifth step of adaptation of the generation data flow to the asynchronous generation device, a sixth ...

CANCELLATION OF SPURIOUS TONES WITHIN A PHASE-LOCKED LOOP WITH A TIME-TO-DIGITAL CONVERTER

A phase-locked loop (PLL) includes a spur cancellation circuit that receives a residue signal indicative of a first frequency and receives a residual phase error signal and generates a spur cancellation signal. A summing circuit combines the spur cancellation signal and a first phase error signal corresponding to a phase difference between a reference signal and a feedback signal in the PLL and generates a second phase error signal with a reduced spurious tone at the first frequency.

MEASURING PIN-TO-PIN DELAYS BETWEEN CLOCK ROUTES

A delay measurement circuit includes a first skew circuit disposed proximate to a first bonding pad configured to receive a first clock signal having a first frequency. The delay measurement circuit includes a second skew circuit disposed proximate to a second bonding pad configured to receive a second clock signal having a second frequency. The first and second skew circuits each have a first mode of operation as zero-delay-return path and a second mode of operation as a synchronized pass path. The delay measurement circuit includes a pair of conductive traces coupled to the first skew circuit, another pair of conductive traces coupled to the second skew circuit, a time-to-digital converter circuit, and a switch circuit configured to selectively couple the time-to-digital converter circuit to the first skew circuit via the pair of conductive traces and the second skew circuit via the other pair of conductive traces.

CIRCUIT AND METHOD TO ENHANCE EFFICIENCY OF SEMICONDUCTOR DEVICE

A circuit includes a period calculator and a pulse width calculator. The period calculator is configured for receiving a first predetermined digital code and a second predetermined digital code, and for calculating a first calculated period value according to the first predetermined digital code, and calculating a second calculated period value according to the second predetermined digital code. The first predetermined digital code has a first predetermined period value, and the second predetermined digital code has a second predetermined period value. The pulse width calculator is configured for receiving a predetermined pulse width, and calculating a first pulse width code corresponding to the predetermined pulse width according to the first predetermined period value, the second predetermined period value, the first calculated period value, the second calculated period value and the predetermined pulse width.

Circuit structure of high performance time-to-digital converter

The invention discloses a circuit structure of a high performance time-to-digital converter including a delay link loop generating low bit data, a counter generating high bit data and a compensated control source The delay link loop counts low bits and sends a thus-generated signal in a specific cycle to the counter. The counter accumulates a period of the signal in the specific cycle as high bits of the time-to-digital converter. The compensated control source compensates and controls a voltage signal of the delay link loop. The invention has the following advantages: a high measurement precision; a fast processing speed; the connection of the outputs of the latches with the high bit counter can ensure correctness of cycle and carry; the introduction of the compensated control source can ensure consistency of the system; and no high requirement is exerted on the components, and hence the circuit structure is easy to implement.

ИНТЕГРИРОВАННЫЙ МНОГОКАНАЛЬНЫЙ ПРЕОБРАЗОВАТЕЛЬ ВРЕМЕННЫХ ИНТЕРВАЛОВ В КОД ДЛЯ ВРЕМЯПРОЛЕТНОЙ ПОЗИТРОННО-ЭМИССИОННОЙ ТОМОГРАФИИ

Изобретение относится к дискретизации данных, назначению временных меток и связанным областям техники. Технический результат - обеспечение назначения временных меток со сверхнаносекундным разрешением. В детекторе (10) излучения, предназначенном для сканера томографии излучения позитронов (PET) времени пролета, элемент (20), чувствительный к излучению, генерирует сигнал (22), указывающий событие обнаружения излучения. Преобразователь (34) временных интервалов в код включает в себя цифровые элементы (40) задержки, оперативно соединенные друг с другом как кольцевой генератор (36, 36′), и схемы (50, 52, 60, 82, 84, 86, 88) считывания, сконфигурированные с возможностью генерации временной метки для события обнаружения излучения на основании, по меньшей мере, состояния кольцевого генератора, когда генерируют сигнал. Элементы (46) подстройки задержки, оперативно соединенные с цифровыми элементами задержки, устанавливают, по существу, общую задержку для цифровых элементов задержки. Дополнительно ...

ИНТЕГРИРОВАННЫЙ МНОГОКАНАЛЬНЫЙ ПРЕОБРАЗОВАТЕЛЬ ВРЕМЕННЫХ ИНТЕРВАЛОВ В КОД ДЛЯ ВРЕМЯПРОЛЕТНОЙ ПОЗИТРОННО-ЭМИССИОННОЙ ТОМОГРАФИИ

... 1. Времяпролетный РЕТ сканер, содержащий: ! детектор (10) излучения, расположенный с возможностью обнаружения излучения, испускаемого из области (8) формирования изображения, причем детектор излучения включает в себя, по меньшей мере, один преобразователь (34) временных интервалов в код, предназначенный для назначения временных меток событиям обнаружения излучения, причем преобразователь временных интервалов в код включает в себя: ! множество цифровых элементов (40) задержки, оперативно соединенных между собой в виде кольцевого генератора (36, 36'), ! элементы (46) подстройки задержки, оперативно соединенные с цифровыми элементами задержки и конфигурируемые с возможностью установки, по существу, общей задержки для цифровых элементов задержки, и ! схемы (50, 52, 60, 82, 84, 86, 88) считывания, сконфигурированные с возможностью генерации временной метки (58) на основании, по меньшей мере, состояния кольцевого генератора, реагирующего на событие обнаружения излучения. ! 2. Времяпролетный РЕТ ...

Analog-Digital-Wandler mit einer Impulsverzögerungsschaltung

Analog-Digital-Wandler zum Umwandeln eines analogen Spannungssignals in digitale Daten mit: einer Impulsverzögerungsschaltung, welche eine Vielzahl von invertierenden Schaltungen enthält, denen jeweils das analoge Spannungssignal durch ein erstes Paar von damit verbundenen Spannungsversorgungsleitungen eingegeben wird, wobei die invertierenden Schaltungen aufeinander folgend miteinander verbunden sind, jede invertierende Schaltung derart arbeitet, dass ein ihr eingegebenes Impulssignal invertiert wird, um eine Inversion des Impulssignals auszugeben, wobei die invertierende Operation jeder invertierenden Schaltung eine vorbestimmte Verzögerungszeit liefert und die Verzögerungszeit jeder invertierenden Schaltung von einem Pegel des Spannungssignals abhängt; einem Spannungssignaleingangsanschluss, welcher mit einer der Spannungsversorgungsleitungen des ersten Paars verbunden ist, durch welche das Spannungssignal angelegt wird; und einer logischen Schaltung, welche ein logisches Gatter und ...

Fensteraktivierter Zeit-zu-digital-Wandler und Verfahren zur Erfassung einer Phase eines Referenzsignals

Ein fensteraktivierter TDC und ein Verfahren zur Erfassung einer Phase eines Referenzsignals. Eine Ausführungsform des fensteraktivierten TDC umfasst: (1) einen Fenstergenerator, der ausgebildet ist, ein Referenzsignal und ein Taktsignal zu empfangen, und (2) eine TDC-Schaltung, die mit dem Fenstergenerator verbunden und ausgebildet ist, auf der Grundlage des Referenzsignals aktiviert und auf der Grundlage des Taktsignals deaktiviert zu werden.

MEHRCHIP-SYNCHRONISATION MIT ANWENDUNGEN IN MEHRFACHEINGANGS-/MEHRFACHAUSGANGS-RADARSYSTEMEN (MIMO-RADARSYSTEMEN)

Eine EC-Plattform, die einen Controller (103) enthält, um mehrere integrierte Schaltungen (ICs) (101) zu steuern, ein internes Betriebstaktsignal (135) einer IC (101) mit einem Haupttaktsignal (141) zu synchronisieren. Der Controller (103) erzeugt Anweisungen für die IC (101), eine Phasendifferenz oder eine Latenzdifferenz zwischen einem internen Anfangstaktsignal (134) der IC (101) und einem Eingangstaktsignal (133) zur IC (101) von einer übergeordneten IC zu messen. Der Controller (103) empfängt ferner ein Differenzsignal (136) von der IC (101) , um die Phasendifferenz oder die Latenzdifferenz anzugeben. Die IC (101) enthält eine Messchaltung, um die Phasendifferenz oder die Latenzdifferenz zu messen und ein Differenzsignal (136) zu erzeugen, um die Phasendifferenz oder die Latenzdifferenz anzugeben. Die IC (101) enthält ferner einen Synchronisationstaktgenerator (117), um auf der Grundlage des internen Anfangstaktsignals (134) und des Differenzsignals (136) ein internes Betriebstaktsignal ...

EIN VERFAHREN UND EIN SYSTEM ZUM KALIBRIEREN EINER PHASEN-NICHTLINEARITÄT EINES DIGITAL-ZEIT-WANDLERS

Ein Verfahren zum Kalibrieren einer Phasen-Nichtlinearität eines Digital-Zeit-Wandlers ist bereitgestellt. Das Verfahren umfasst das Erzeugen eines Referenzsignals basierend auf einem Steuerwort unter Verwendung einer Phasenregelschleife. Eine Frequenz des Referenzsignals ist gleich einer Frequenz eines Ausgangssignals des Digital-Zeit-Wandlers. Ferner umfasst das Verfahren ein Messen einer zeitlichen Ordnung eines Übergangs des Ausgangssignals von einem ersten Signalpegel zu einem zweiten Signalpegel und eines Übergangs des Referenzsignals von dem ersten Signalpegel zu dem zweiten Signalpegel. Das Verfahren umfasst zusätzlich das Anpassen eines ersten Eintrags einer Nachschlagtabelle basierend auf der gemessenen zeitlichen Ordnung.

Activity detection

A low-power, “always on” Voice Activity Detector (VAD, 100) generates a first Time Encoding Modulated (TEM) signal 101 (eg. a loop-filtered Pulse Width Modulated signal SPWM) from a microphone input SIN via a hysteretic comparator (201, fig. 4) and inputs this to a Time Decoding Convertor (TDC, 102) along with a clock signal (SCLK) generated from a midpoint reference voltage (VMID) via a second TEM (103) having a second hysteretic comparator (401, fig. 4). The TDC then outputs a count signal (SCT) to an activity monitor 104 to determine if signal activity lies above a threshold, whereupon a control signal EN is sent to wake other elements.

Period-to-digital converter

RAIL TON RAIL DELAY LINE FOR TIME ENCODERS

PHASE DETERMINING DEVICE AND FREQUENCY DETERMINING DEVICE

HIGH RESOLUTION TIME-TO-DIGITAL CONVERTER

Method and system for measuring distance

A method for measuring distance involves calculating a distance based on light speed and a time taken by a light signal to travel to an object and return therefrom. The method includes: calculating a time based on a cycle number of a reference signal under a clock mask synchronized with emission and reception of the light signal; correcting the time according to a plurality of phase shift signals generated based on the reference signal; and minimizing an error of the time by increasing the quantity of the phase shift signals. The method enhances the accuracy of the measured time taken by a light signal to travel to an object and return therefrom, speeds up measurement, and reduces the required circuit areas. A system for measuring distance is further provided for use with the method.

PHASE FREQUENCY TO DIGITAL CONVERTER

A circuit arrangement is described comprising a first receiver configured to receive a first input signal, a second receiver configured to receive a second input signal, a first signal generator configured to generate a first pulse signal, a second signal generator configured to generate a second pulse signal, wherein a delay between a rising edge of the first pulse signal and a rising edge of the second pulse signal is proportional to a difference between the first input signal and the second input signal, a first converter configured to convert the first pulse signal to a first digital number proportional to a width of the first pulse signal, a second converter configured to convert the second pulse signal to a second digital number proportional to a width of the second pulse signal, wherein at least one of the first converter and the second converter comprises a cascade of at least two converter stages, wherein each converter stage of the at least two converter stages is configured to ...

3D IMAGER AND METHOD FOR 3D IMAGING

... 3D imager comprising at least one pixel, each pixel comprising a photodetectorfor detecting photon incidence and a time-to-digital converter system configured for referencing said photon incidence to a reference clock, and further comprising a reference clock generator provided for generating the reference clock, wherein the reference clock generator is configured for adjusting the frequency of the reference clock on the basis of an estimated time up to a subsequent photon incidence ...

DELAY CIRCUIT, MULTI-STAGE DELAY CIRCUIT, TIME DIGITAL CONVERTER USING THEM, SEMICONDUCTOR TEST DEVICE, RING OSCILLATOR, AND DELAY LOCK LOOP CIRCUIT

A delay circuit (100) includes a MOSFET (1) and bias voltage sources (12a, 12b). The bias voltage sources (12a, 12b) apply voltage across a drain and a source of the MOSFET (1). The bias voltage source (12a) supplies a source voltage Vss to a source electrode (106a) of the MOSFET (1). The bias voltage source (12b) supplies a drain voltage Vdd to a drain electrode (106b) of the MOSFET (1). An input signal IN to be delayed is made to propagate in the gate width direction (y-axis direction) in the gate of the MOSFET (1).

INPUT CAPTURE PERIPHERAL WITH GATING LOGIC

A microcontroller has an input capture peripheral, wherein the input capture peripheral is configured to store timer values of an associated timer in a memory and wherein the input capture peripheral has a gating input which controls whether an input capture function is activated.

TIME-TO-DIGITAL CONVERTER

Embodiments of a time-to-digital converter are provided, comprising a delay stage matrix and a measurement circuit. The delay stage matrix comprises a first and a second delay lines coupled thereto, and is arranged to propagate a transition signal from a starting delay stage in the first and a second delay lines, wherein each of the first and second delay lines comprises a same number of delay stages coupled in series, each delay stage in one of the first and second delay lines is coupled to a corresponding delay stage in the other delay line and operative to generate a delayed signal. The measurement circuit is arranged to determine a time of the transition signal propagating along the delay stages by sampling the delayed signals using a measurement signal to generate and hold a digital representation of the time.

ROTARY CLOCK FLASH ANALOG TO DIGITAL CONVERTER SYSTEM AND METHOD

System and method for converting an analog voltage to a digital signal. The system includes an input voltage sampler, a ramp generator, a comparator, a time-to-digital converter (TDC), and a multiphase oscillator, preferably a rotary traveling wave oscillator, that provides the critical system timing. The phases of the multiphase oscillator define a sampling interval during which the input voltage is sampled and held and a conversion interval during which the ramp generator, comparator, and TDC operate to convert the sampled voltage to the digital signal. The TDC samples at times provided by the phases of the multiphase oscillator to form the bits of the digital signal. The sampler, ramp generator, and comparator can be constructed from multiple fragments, one of which is selectable for calibration while the rest of the fragments are joined for normal operation. Multiple converters can be interleaved to increase the sampling rate.

Analog-to-digital converter

A system and method for implementing an analog-to-digital converter (ADC). The ADC includes a converter for generating a timed pulse based on an analog signal and a control signal. The ADC also includes a timing analyzer for generating a digital signal based on the timed pulse. According to the system and method disclosed herein, the present invention achieves a high sampling rate and low latency at low power.

SYNTHESIZING METHOD OF SIGNAL HAVING VARIABLE FREQUENCY AND SYNTHESIZER OF SIGNAL HAVING VARIABLE FREQUENCY

A variable frequency signal synthesizer includes a phase locked loop including a time-to-digital converter configured to detect differences in phase and frequency between a reference signal and a feedback clock signal and output error signals corresponding to the detected differences, a digital loop filter, a digitally controlled oscillator, and a first frequency divider configured to divide output signals of the digitally controlled oscillator at a predetermined frequency division ratio, a feedback clock generation unit configured to generate sign signals and a phase-modulated feedback clock signal, and a frequency slope tracker configured to generate a frequency control signal by accumulating differences in the error signals according to signs corresponding to the sign signals. The digitally controlled oscillator receives the frequency control signal to supply an output variable frequency signal.

Calibration method and apparatus for high TDC resolution

Various embodiments include a time to digital converter device comprising: a medium resolution delay unit including a plurality of buffers, the medium resolution delay unit configured to receive as inputs a reference clock signal and a data clock signal and configured to output a plurality of delayed data clock signals wherein the delay between the plurality of delayed data clock signal is a medium resolution delay value; a fine resolution delay unit including a plurality of cores configured to receive as inputs the reference clock signal and the plurality of delayed data clock signals from the medium resolution delay unit, wherein the plurality of cores includes: a first bank of delays configured to receive one of the plurality of the delayed data clock signals, a second bank of delays configured to receive the reference clock signal, and; and a fast flip flop connected to the outputs of the first bank of delays and the second bank of delays, wherein the output of the fast flip flop is ...

High-speed, single-slope analog-to-digital converter

A system and method for converting an analog signal to a digital signal is disclosed. The system includes a multiphase oscillator preferable a rotary oscillator, a sample and hold circuit, an integrator and a time-to-digital converter. The multiphase oscillator has a plurality of phases that are used in the time-to-digital converter to measure the time of a pulse created by the integrator. The edges of the pulse may optionally be sharpened by passing the pulse through a non-linear transmission line to improve the accuracy of the measurement process. To cut down on noise a tuned power network provides power to the switching devices of the rotary oscillator. Calibration is performed by fragmenting the sample and hold circuit and integrator and performing a closed loop calibration cycle on one of the fragments while the other fragments are joined together for the normal operation of the sample and hold and integrator circuits.

Device and method for high resolution time measurements

The invention relates to a device for determining the temporal position of an analogue trigger signal with relation to an analogue clock signal, comprising an analogue cross-correlator (30), which carries out an analogue cross-correlation between the trigger signal and clock signal to provide a fine resolution.

DIGITAL-TO-TIME CONVERTER SPUR REDUCTION

This application discusses, among other things, apparatus and methods for improving spurious frequency performance of digital-to-time converters (DTCs). In an example, a method can include receiving a code at selection logic of a digital-to-time converter at a first instant, selecting a first delay path of the DTC to provide a delay associated with the code, associating a second delay path with the code, receiving the code at the selection logic at a second instant, and selecting the second delay path of the DTC to provide the delay associated with the code.

Rail-to-rail delay line for time analog-to-digital converters

A time-analog-to-digital converter (TAD) utilizes a time-to-digital approach for analog-to-digital conversion. The TAD includes two voltage-to-delay converters (VDCs), e.g., CMOS inverter chains, in order to increase the dynamic range of the TAD. Each VDC can handle a different range of input voltages. Comparators compare the input signal voltage to reference voltages corresponding to the different ranges of input voltage and a selector selects one of the VDC line outputs based on the range in which the input signal lies. A filter estimates the input signal voltage from a delay signal from the selected output.

Method and apparatus for Vernier ring time to digital converter with self-delay ratio calibration

Some embodiments of the present invention provide a method and apparatus for a Vernier ring time to digital converter having a single clock input and an all digital circuit that calculates a fixed delay relationship between a set of slow buffers and fast buffers. A method for calibrating a Vernier Delay Line of a TDC, comprising the steps of inputting a reference clock to a slow buffer and to a fast buffer, determining a delay ratio of the slow buffer and fast buffer; and adjusting the delay ratio of the slow buffer and fast buffer to a fixed delay ratio value wherein an up-down accumulator generates control signals to adjust the slow buffer.

Light sensor and calibration method thereof

A light sensor and its calibration method are provided. The light sensor includes a light source, a sensing sub-pixel, and a control circuit. The light source emits a sensing light beam. The sensing sub-pixel includes a diode, a quenching resistor, and a time-to-digital converter. The diode has a first terminal coupled to an operation voltage. The quenching resistor is coupled between a second terminal of the diode and a ground voltage. The time-to-digital converter is coupled to the second terminal of the diode. The control circuit is coupled to the sensing sub-pixel and calibrates a sensing sensitivity of the sensing sub-pixel according to at least one of a photon detection probability, an internal gain value, and a resistance value of the quenching resistor corresponding to the diode of the sensing sub-pixel, so that the sensing sub-pixel generates a single-photon avalanche diode sensing signal only when receiving the sensing light beam.

Arrayed time to digital converter

Methods and apparatus for an arrayed time to digital converter (TDC) having matched delay line sampling. In embodiments, a TDC includes a coarse counter circuit to provide an event coarse timing measurement for an event, a coarse counter delivery network to deliver a count value in the coarse counter circuit to a memory storage element circuit, and an array of matched delay lines to provide an event fine timing measurement to the memory storage element circuit. An array of event sample signal generators can generate signals for the event and an array of encoders can encode fine timing measurement information from the memory storage element circuit, where an output of the encoder and the event coarse timing measurement information provide a timestamp for the event. A global delay-locked loop can incorporate a matched delay line coupled to the array of matched delay lines.

A/D CONVERTER

PURPOSE: To use an A/D converter even at a high temperature without using an analog amplifier circuit by securing such a function of the A/D converter that can turn the minute change of the voltage signal into the numerical value. CONSTITUTION: The pulse signals PA and PB which are outputted from a control circuit 4 at a fixed interval are inputted to a pulse phase difference coding circuit 2 which converts the phase difference of the pulse signal into the digital data DO1. Thus the circuit 2 can code the time difference between both signals PA and PB. Meanwhile the voltage signal Vin to undergo the A/D conversion is inputted as the power voltage of the inverting circuits (NAND and INV) included in pulse rounding circuit 10 forming the circuit 2. As a result, the inverting time of each inverting circuit is changed by the signal Vin and the data DO1 outputted from the circuit 2 has the value corresponding to the signal Vin. COPYRIGHT: (C)1993,JPO&Japio ...

Schaltung zur Analog-/Digital-Umwandlung

PHASENSYNCHRONISATIONSSCHLEIFE NIEDRIGER LEISTUNG UND GERINGEM JITTER MIT DIGITALER LECKVERLUSTKOMPENSATION

Beschrieben ist eine Phasensynchronisationsschleife (PLL) mit geringer Leistung und geringem Jitter oder eine verzögerte Regelschleife (DLL) mit digitaler Leckverlustkompensation. Die Kompensation wird durch eine Vorrichtung bereitgestellt, welche Folgendes umfasst: einen Schaltkomplex, um einen Impuls mit einer digital gesteuerten Impulsbreite zu erzeugen, wobei die Impulsbreite proportional zu einem statischen Phasenfehler einer PLL oder einer DLL ist; und eine Ladungspumpe, welche mit dem Schaltkomplex gekoppelt ist, wobei die Ladungspumpe dazu dient, den Impuls zu empfangen und einen Strom in einen oder aus einem Knoten gemäß der Impulsbreite zu liefern oder zu entnehmen.

CIRCUIT DEVICE AND PROCEDURE FOR THE MEASUREMENT OF CLOCK FLUCTUATIONS

Time-to-digital converter

RESONATOR DEVICE, ELECTRONIC APPARATUS, AND VEHICLE

ELECTRONIC PROCESS OF INSTANTANEOUS MEASUREMENT Of an TIME INTERVAL USING a PROGRAMMABLE LOGICAL CIRCUIT (OR FPGA IN ENGLISH) AND a CLOCK OF REFERS

HIGH-SPEED CONVERTER TEMPS-NUMERIQUE

Electronic time measurement device for use in electronic test assembly, has calculation unit for determining time interval between event and reference using counter values, sampler values and values of number of transitions

L'invention proposée utilise un circuit logique programmable et une horloge de référence pour acquérir et mémoriser les intervalles de temps compris entre les différents événements présents a l'entrée du système. Le dispositif ne nécessite pas de temps mort entre les acquisitions, permettant par cela d'acquérir tout les événements et d'extraire la fréquence, la gigue cycle à cycle lorsqu'une horloge lui est appliquée. Selon une de ses mise en oeuvre, le dispositif est constitué des sous-ensembles suivants : un multiplexeur (MU) en entrée, un échantillonneur (ECH) qui utilise la chaîne de retenue du FPGA comme élément de ligne à retard et permet de mémoriser la position du front dans la période de l'horloge de référence, un détecteur de front (FCPT), un contrôleur de mémoire (CTRL), un compteur de cycles d'horloge (CPT), un système de mémorisation (MEM), et enfin un sous ensemble de calcul configurable (CAL). Le dispositif est principalement destiné aux instruments de mesures de temps ou ...

DELAY TIME MEASUREMENT CIRCUIT AND A METHOD FOR MEASURING A DELAY TIME, TO REDUCE THE NUMBER OF DELAY ELEMENTS REQUIRED FOR MEASURING THE DELAY TIME

PURPOSE: A delay time measurement circuit and a method for measuring a delay time are provided to measure totally a long delay time by setting a short delay time of each delay element. CONSTITUTION: A delay chain unit(130) receives a reference signal for indicating a delay time measurement start or a feedback output signal as an input signal, includes a plurality of delay elements to delay and invert the received signals, to output the feedback output signal, count a feedback number of the reference signal, and to output a repeated counting signal. A code generation unit(140) generates a code signal by comparing the input signal with delay signals applied to the residual delay elements except for the last delay element with a measurement signal for measuring a delay time on the basis of the reference signal. A decoder unit(150) decodes the code signal and the repeated counting signal and outputs a delay measurement value. © KIPO 2008 ...

TWO-STEP TIME-TO-DIGITAL CONVERTER-BASED FULLY DIGITAL DELAY LOCKED LOOP CIRCUIT AND CONTROL METHOD THEREOF

The present invention relates to a two-step time-to-digital converter-based fully digital delay locked loop circuit and a control method thereof wherein the two-step time-to-digital converter-based fully digital delay locked loop circuit has a fast locking time and performance of lower power and a smaller chip area. The two-step time-to-digital converter-based fully digital delay locked loop circuit comprises: a digital control delay line which changes a phase between an input clock signal (CLKIN) and an output clock signal (CLKOUT) and finally reduces phase errors between the CLKIN and a DQ clock signal (CLKDQ); a replica clock buffer which receives input of the CLKOUT, output from the digital control delay line, and makes a phase of a feedback clock signal (CLKFB) and a phase of the CLKDQ the same by outputting the CLKFB delayed by a predetermined time; a two-step time-to-digital converter which searches for a coarse lock point and a fine lock point and generates a code for removing error ...

Semiconductor body and method for measuring time of flight

TIME-TO-DIGITAL CONVERSION WITH DELAY CONTRIBUTION DETERMINATION OF DELAY ELEMENTS

Hybrid coarse-fine time-to-digital converter

Adaptive on-chip digital power estimator

Systems, apparatuses, and methods for implementing a dynamic power estimation (DPE) unit that adapts weights in real-time are described. A system includes a processor, a DPE unit, and a power management unit (PMU). The DPE unit generates a power consumption estimate for the processor by multiplying a plurality of weights by a plurality of counter values, with each weight multiplied by a corresponding counter. The DPE unit calculates the sum of the products of the plurality of weights and plurality of counters. The accumulated sum is used as an estimate of the processor's power consumption. On a periodic basis, the estimate is compared to a current sense value to measure the error. If the error is greater than a threshold, then an on-chip learning algorithm dynamically adjust the weights. The PMU uses the power consumption estimates to keep the processor within a thermal envelope.

Time-to-digital converting circuit and pressure sensing device using the same

A time-to-digital converting circuit and a pressure sensing device using the same are provided. The circuit includes: a delay time-varying unit generating a reference signal having a fixed delay time, and a sensing signal having a variable delay time in response to an impedance of an externally applied signal; and a delay time calculation and data generation unit calculating a delay time difference between the reference signal and the sensing signal, and generating digital data having a value corresponding to the calculated delay time difference. Accordingly, the digital data are generated using the delay time varied in response to the externally applied signal, so that the size of the time-to-digital circuit is significantly reduced. In addition, an affect due to circumferential noises is minimized.

DETECTOR ARRAY WITH TIME-TO-DIGITAL CONVERSION HAVING IMPROVED TEMPORAL ACCURACY

A detector (22) detects an event. First and second time-to-digital converters(TDCs) (70, 72) generate first and second time stamps (TS1, TS2) for the detection of the event. The first TDC and the second TDC are both synchronized with a common clock signal (62) that defines a fixed time offset between the second TDC and the first TDC. An autocalibration circuit (120) adjusts the first TDC and the second TDC to keep the time difference between the second time stamp and the first time stamp equal to the fixed time offset between the second TDC and the first TDC. The detector may be a detector array, and trigger circuitry (28) propagates a trigger signal from a triggering detector of the array of detectors to the first and second TDC's. Skew correction circuitry (132, 134, 136, 142, 60, 162) adjusts a timestamp (TS) based on which detector is the triggering detector.

TIME TO DIGITAL CONVERTING CIRCUIT AND PRESSURE SENSING DEVICE USING THE SAME

A time-to-digital converting circuit and a pressure sensing device using the same are provided. The circuit includes: a delay time-varying unit generating a reference signal having a fixed delay time, and a sensing signal having a variable delay time in response to an impedance of an externally applied signal; and a delay time calculation and data generation unit calculating a delay time difference between the reference signal and the sensing signal, and generating digital data having a value corresponding to the calculated delay time difference. Accordingly, the digital data are generated using the delay time varied in response to the externally applied signal, so that the size of the time-to-digital circuit is significantly reduced. In addition, an affect due to external noises is minimized.

ROTARY FLASH ADC

An analog to digital converter system comprises a multiphase oscillator preferable a rotary oscillator, a sample and hold circuit (psamp), an integrator (iramp), and a time to digtial converter (PFET). The multiphase oscillator has a plurality of phases that are used in the time to digital converter to measure the time of the pulses created by the integrator, Calibration is performed by fragmenting the sample and hold circuit and integrator and performing a closed loop calibration cycle on one of the fragments while the other fragments are joined foi the normal operation of the sample and hold and integrator circuits.

SYSTEM AND METHOD FOR TIME ENCODING ANALOG SIGNALS

Time encoding machines with multiplicative coupling, and optional feedforward or feedback are provided. The time encoding machines, which are based on common oscillator circuits, are input/output equivalent to either an integrate-and- fire neuron with a variable threshold sequence or to an asynchronous sigma-delta modulator with a variable threshold sequence. An input bandlimited signal, which is time-encoded using the time encoding machines, can be perfectly recovered from the zero crossings of the modulated signal and the threshold sequence.

TIME-TO-DIGITAL CONVERTER AND A/D CONVERTER PROVIDED WITH SAME

This time-to-digital converter is provided with: first and second phase distribution circuits (10A and 10B) which are configured so that a plurality of dividers (12A and 12B) are connected in a tree shape so that a signal which is input to a divider of the root node is divided by N in order to output N signals for which phases are different; and N time-to-digital converting circuits (20) which convert, to digital values, phase differences between ith (in this regard, i is an integer from 0 to N-1) signals which are output from each of the first and the second phase distribution circuits, respectively.

Time-to-digital conversion with analog dithering

There is described a time-to-digital conversion scheme using an arrangement of delay elements based Time-to-Digital Converter, TDC (20), wherein dithering is built in the digital domain and introduced in the analog domain as a modulation of a supply voltage (TDC-supply) supplying delay elements of the TDC, each having a propagation delay which exhibits a dependency to their supply voltage.

INTEGRAL A/D CONVERTER AND CMOS IMAGE SENSOR

The integral type Analog/Digital (AD) converter includes: a comparator configured to compare a reference voltage of a ramp waveform with an input voltage and output a comparison signal; a DLL circuit configured to generate a plurality of clock signals; a delay adjustment circuit configured to delay the comparison signal; a counter configured to count a time from starting of changing of the ramp waveform to the inversion of the outputting from the delay adjustment circuit and output the counted result as a high-order bit; and a TDC configured to latch and decode the plurality of clock signals when the output of the delay adjustment circuit is inverted and output the latched and decoded result as a low-order bit, wherein the TDC starts an operation thereof by the inversion of the comparison signal, and stops the operation thereof by the inversion of the output signal of the delay adjustment circuit.

Analog to digital conversion using irregular sampling

This disclosure relates to analog to digital conversion using irregular sampling.

CLOCK GENERATOR, PHASE LOCKED LOOP, APPARATUS, METHOD AND COMPUTER PROGRAM FOR GENERATING A CLOCK SIGNAL, TRANSCEIVER, AND MOBILE TERMINAL

Examples provide a system, a phase locked loop, an apparatus, a method and a computer program for generating a clock signal, a transceiver, and a mobile terminal. A system comprises clock generator (10) configured to output provide a clock signal having a predefined average clock rate, a reference signal generator (14) configured to provide a reference signal, and a clock divider (16) configured to divide the reference signal to generate the clock signal, wherein a time difference between a clock cycles and a subsequent clock cycle of the clock signal is irregular.

CALIBRATION OF DYNAMIC ERROR IN HIGH RESOLUTION DIGITAL-TO-TIME CONVERTERS

A calibration system operates to calibrate or correct a digital-to-time converter (DTC) that comprises a detector component and a distortion correction component. The DTC can receive one or more signals and a digital code to generate a modulation signal by controlling an offset of the one or more signals based on the digital code. The detector component can comprise a TDC or another DTC that operates to measure a dynamic behavior in response to detecting nonlinearities of the modulation signal. The distortion correction component can generate a set of distortion data that removes the dynamic behavior from an output of the DTC based on the measurement.

DIGITALIZATION DEVICE

A digitalization device includes a first pulse delay unit, a second pulse delay unit, and an addition output unit. The first pulse delay unit includes first delay units connected in series by (2n-(2m−1)), and outputs a first signal according to the number of first delay units through which a first pulse signal passes. The second pulse delay unit includes second delay units connected in series by (2n+(2m−1)), and outputs a second signal according to the number of the second delay units through which a second pulse signal passes. Here, n and m are natural numbers, and n≥m. The addition output unit outputs, as a digital value, an addition value obtained by adding a numerical value based on the output of the first pulse delay unit and a numerical value based on the output of the second pulse delay unit.

Digital phase locked loop

A digital phase locked loop realizing high bandwidth is disclosed. The digital locked loop generates a first digital code corresponding to a difference between a rising edge of a reference signal and a rising edge of a feedback signal and a second digital code corresponding to a difference between a falling edge of the reference signal and a falling edges of the feedback signal, generates a third digital code by adding the first digital code and the second digital code, generates a first frequency control code at the rising edge of the reference signal and a second frequency control code at the falling edge of the reference signal by filtering the third digital code, outputs a specific frequency depending on the first frequency control code and the second frequency control code.

CIRCUIT DEVICE, PHYSICAL QUANTITY MEASUREMENT DEVICE, ELECTRONIC APPARATUS, AND VEHICLE

A circuit device includes a clock generation circuit, a signal generation circuit, a phase comparison circuit, and a processing circuit. The signal generation circuit generates a first signal making the transition at a transition timing of a first clock signal, a fine-judging signal making the transition at a transition timing of a second clock signal, a first coarse-judging signal making the transition at a transition timing of the second clock signal anterior to the fine-judging signal, and a second coarse-judging signal making the transition at a transition timing of the second clock signal posterior to the fine-judging signal. The phase comparison circuit performs the phase comparison between the second signal making the transition based on the first signal and each of the fine-judging signal, the first coarse-judging signal, and the second coarse-judging signal. The processing circuit sets the transition timing of the first signal and the transition timing of the fine-judging signal based on the phase comparison result, and converts a time difference between the first signal and the second signal into a digital value based on the setting result. 1. A circuit device comprising:a clock generation circuit configured to generate a first clock signal and a second clock signal different in frequency from the first clock signal;a signal generation circuit configured to generate a first signal making a transition at a transition timing of the first clock signal, a fine-judging signal making a transition at a transition timing of the second clock signal, a first coarse-judging signal making a transition at a transition timing of the second clock signal anterior to the fine-judging signal, and a second coarse-judging signal making a transition at a transition timing of the second clock signal posterior to the fine-judging signal;a phase comparison circuit configured to perform a phase comparison between a second signal making a transition based on the first signal and ...

Matched delay line voltage converter

A method and apparatus for measuring or converting voltage, the method comprising: applying an input voltage to a primary delay line; applying a reference voltage to a timer delay line; propagating a delay signal through the primary delay line; propagating a timer signal through the timer delay line; establishing a sampling period based on the timer signal propagation; and measuring an extent of delay signal propagation along the primary delay line during the established sampling period, the measured signal propagation extent being indicative of a difference between the input voltage and the reference voltage.

Circuit Device, Physical Quantity Measurement Device, Electronic Apparatus, And Vehicle

The circuit device includes an integration period signal generation circuit, a polarity switching signal generation circuit, and first and second integration circuits. The integration period signal generation circuit generates a first integration period signal kept in an active state in the first integration period. The polarity switching signal generation circuit generates a first integration polarity switching signal making a transition at a timing synchronized with the reference clock signal in the first integration period, and a second integration polarity switching signal making a transition a predetermined clock count of the reference clock signal after the transition timing of the first integration polarity switching signal in the first integration period. The first integration circuit performs an integrating process in which an integration polarity is switched at the transition timing of the first integration polarity switching signal in the first integration period. The second ...

Time-to-digital converter and digital phase locked loop

A time-to-digital converter includes N stages of converting circuits, where N2, and N is an integer. Each stage of the converting circuit includes a first delayer and an arbiter; an output end of the first delayer in each stage of the converting circuit outputs a delayed signal of the stage of the converting circuit; and the arbiter in each stage of the converting circuit receives a sampling clock and the delayed signal of the stage of the converting circuit, and compares the sampling clock with the delayed signal to obtain an output signal of the stage of the converting circuit. The first delayer in each stage of the converting circuit includes at least one first delay cell circuit with a first time unit. The first delayer in any stage of the converting circuit includes a less number of first delay cell circuits than the first delayer in a next stage of the converting circuit.

CIRCUIT AND CALIBRATION METHOD OF ALL-DIGITAL PHASE-LOCKED LOOP CIRCUIT

An all-digital phase-locked loop (ADPLL) circuit and a calibration method thereof are provided. The ADPLL circuit includes a digitally controlled oscillator (DCO) circuit, a phase detector circuit, and a calibration circuit coupled between the DCO circuit and the phase detector circuit. The DCO circuit generates a clock signal according to a frequency control signal. The phase detector circuit generates a phase error value according to a reference signal and the clock signal. More particularly, after the ADPLL circuit performs a locking operation for a period of time, the frequency control signal is tied at a locked value which is obtained when the ADPLL circuit performs the locking operation, and the calibration circuit may modify a current of at least one current source within the DCO circuit according to the phase error value.

SPAD IMAGE SENSOR

A LiDAR system is disclosed that includes a SPAD unit array and J read group (RG) channels. The SPAD unit array is arranged in M rows and N columns of pixel read groups. Each row includes K pixel read groups. Each pixel read group outputs a detection signal in response to a light pulse that is incident on the pixel read group. Each RG channel corresponds to at least one row of pixel read groups and includes L time-to-digital converters that respectively generate timestamp information corresponding to detection event signals of each of L pixel read groups in the at least one row of pixel read groups in which J Подробнее

Circuit device and method of measuring clock jitter

Time interval to digital converter with smoothing

An up/down tracking counter (15) stores a digital count signal equal to the time interval to be converted and provides this signal as the parallel digital output of the converter. Prior to the interval to be converted, the count from the up/down counter (15) is loaded into a down counter (14). At the leading edge of the interval to be converted, the down counter (14) is counted down, from the count loaded therein, by a clock signal (17) until the occurrence of the trailing edge of the interval. A decision PROM (19) responsive to the output of the down counter (14) provides a message signal in accordance with the residual error count remaining in the down counter. The message signal commands a bit pattern generator (22) that applies pulse burst controllably to the count up input or count down input of the up/down counter (15) in accordance with the error count in the down counter so as to tend to reduce the error count in the down counter to zero.

TIME-TO-DIGITAL CONVERTER

Vorrichtung zur Zeit-zu-Digital-Wandlung mit geregelter zeitlicher Wavelet-Kompression mittels eines Sende-Wavelets und eines Analyse-Wavelets mit geregelter Verzögerung

Die Vorrichtung führt ein Verfahren zur Bestimmung der Verzögerungszeit eines ersten Wavelets in einer Übertragungsstrecke (I1) aus. Hierzu wird das erste Wavelet zu einem Zeitpunkt nach einem Referenzzeitpunkt in die Übertragungstrecke hineingesendet. Nach Durchgang durch die Übertragungsstrecke wird das verzögerte und typischerweise deformierte Wavelet mit einem zweiten Wavelet skalar-multipliziert. Das Ergebnis wird mit einem Referenzwert verglichen. Zu einem Schneidezeitpunkt (ts) schneidet der Skalar-Produktwert den Referenzwert. In Abhängigkeit von diesem Schneidezeitpunkt (ts) bezogen auf den Referenzzeitpunkt wird die Verzögerung des ersten und/oder zweiten Wavelets gegenüber dem Referenzzeitpunkt geregelt. Eine Amplitudenregelung findet nicht statt.

Time-to-digital converter and operating method

Provided are a TDC having a pipeline or cyclic structure and an operating method thereof. The TDC includes a first stage block and a second stage block. The first stage block detects a first bit of a digital code for a time difference between first and second input signals. The second stage block detects a second bit of the digital code for a time difference between first and second output signals of the first stage block. The first stage block amplifies a time difference between first and second delay signals for the first and second input signals to generate the first and second output signals, and transfers the first and second output signals to the second stage block.

DISTANCE MEASURING DEVICE AND RECEIVING DEVICES THEREOF

Provided are a distance measuring device using an impulse signal and a receiving device thereof. The distance measuring device includes: a transmitting device transmitting an impulse signal; and a receiving device receiving the impulse signal and measuring a time interval (hereinafter, referred to as a delay time) between a transmitting timing and a receiving timing of the impulse signal, wherein the receiving device measures the delay time through a Time to Digital Converter (TDC) technique. According to the present invention, the distance measuring device measures the distance accurately and speedly. 1. A distance measuring device comprising:a transmitting device transmitting an impulse signal; anda receiving device receiving the impulse signal and measuring a delay time between a transmitting timing and a receiving timing of the impulse signal,wherein the receiving device measures the delay time through a Time to Digital Converter (TDC) technique.2. The distance measuring device of claim 1 , wherein the receiving device measures the delay time by delaying a first signal synchronized at the transmitting timing of the impulse signal and a second signal synchronized at the receiving timing of the impulse signal claim 1 , with respectively different time intervals.3. The distance measuring device of claim 2 , wherein the first signal is delayed by a first time interval and the second signal is delayed by a second time interval shorter than the first time interval.4. The distance measuring device of claim 3 , wherein the first and second time intervals are longer than the delay time.5. The distance measuring device of claim 1 , wherein the transmitting device comprises:a transmit clock signal generator generating a transmit clock signal;an impulse generator converting the transmit clock signal into a digital impulse signal; anda signal distortion filter converting the digital impulse signal into the impulse signal.6. The distance measuring device of claim 5 , wherein ...

METHOD AND APPARATUS FOR CLOCKLESS CONVERSION OF TIME INTERVAL TO DIGITAL WORD

Method and apparatus for detecting the beginning and end of a time interval using the control module and in mapping this time interval to a portion of electric charge proportional to this time interval and accumulated in the sampling capacitor and then realizing the process of charge redistribution in the array of redistribution by changing states of signals from relevant control outputs and in assignment of relevant values to bits in the digital word by means of the control module. After detection of the beginning of the next time interval, the charge is aaccumulated in the additional sampling capacitor and then the process of charge redistribution is realized and relevant values are assigned to bits of the digital word. When the beginning of the subsequent time interval is detected, the next cycle begins and electric charge is accumulated in the sampling capacitor again. 1. Method for clockless conversion of time interval to digital word consisting in a detection of the beginning and of the end of the time interval by the use of the control module and in mapping this time interval to a portion of electric charge proportional to this time interval and delivered by the use of the current source while the portion of electric charge is accumulated in the sampling capacitor , or in the sampling capacitor and in the capacitor having the highest capacitance value in an array of redistribution , which is connected to the sampling capacitor in parallel , and then consisting in the realization of the process of accumulated electric charge redistribution in the array of redistribution in a known way by means of the control module by changes of states of signals from relevant control outputs , while the array of redistribution comprises an array of on-off switches , of change-over switches and of capacitors such that a capacitance value of each capacitor of a given index is twice as high as a capacitance value of a capacitor of the previous index , and also consisting in the ...

Multi-bit delta-sigma time digitizer circuit and calibration method thereof

According to one embodiment, a multi-bit delta-sigma time digitizer circuit includes a delay array including delay selection circuits respectively including a delay element and a multiplexer, a phase comparator calculating a time difference, an integrator integrating the time difference output, a flash A/D converter executing digital conversion, a ring oscillation circuit including the delay array, a counter measuring a number of clock signal pulses, a memory storing a delay value of the delay element, and a processor correcting an output result of the A/D converter based on the delay value when the rising timing interval is measured.

Low-power high-resolution time-to-digital converter

Disclosed is a low-power and high-resolution time-to-digital converter including: a coarse delay cell configured to delay a reference clock by a coarse delay time and output the reference clock; a rising-edge retimer configured to output a rising-edge retimed clock synchronized with the rising-edge of a DCO clock in response to the reference clock; a falling-edge retimer configured to output a falling-edge retimed clock synchronized with the falling-edge of the DCO clock; a firs sampler configured to latches output of the coarse delay cell in response to the rising-edge retimed clock and the falling-edge retimed clock; and a pseudo-thermometer code edge detector configured to detect a rising-edge fractional phase error between the reference clock and the rising-edge retimed clock as a coarse phase error from a signal output by the first sampler, and detect a falling-edge fractional phase error between the reference clock and the falling-edge retimed clock.

Method and System for Compensating a Delay Mismatch Between a First Measurement Channel and a Second Measurement Channel

A method and a system for compensating a delay mismatch between a first measurement channel and a second measurement channel is disclosed. A method for compensating a delay mismatch between a first measurement channel and a second measurement channel includes providing a reference point for starting the first and second measurement channel, and starting the first measurement channel after expiration of a first delay period which begins at the reference point. The method further includes starting the second measurement channel after expiry of a second delay period which begins at the reference point, wherein a difference between a length of the first delay period and a length of the second delay period is substantially equal to the delay mismatch between the first measurement channel and the second measurement channel.

Input capture peripheral with gating logic

A microcontroller has an input capture peripheral, wherein the input capture peripheral is configured to store timer values of an associated timer in a memory and wherein the input capture peripheral has a gating input which controls whether an input capture function is activated.

ZERO DEAD TIME, HIGH EVENT RATE, MULTI-STOP TIME-TO-DIGITAL CONVERTER

Time-to-digital converters adapted to analog and digital inputs and methods of use are described. A time-to-digital converter has an event frame latches and logic module with memory cells, an analog front-end module connected to the memory cells, and a bin increment generator module connected to the memory cells. The bin increment generator is configured to issue bin increments separated by a time increment, and the analog front end is configured to issue a start event followed by a plurality of stop events. Upon receipt of a first time increment following a start event, the event frame latches and logic module updates a first memory cell with a first bit-type; upon receipt of a second time increment following an intervening stop event, the event frame latches and logic module updates a second memory cell with a second bit-type different from the first bit-type. 1. A time-to-digital converter , comprising:an event frame latches and logic module having a plurality of memory cells;an analog front-end module connected to the event frame module; anda bin increment generator module connected to the event frame latches and logic module,wherein the bin increment generator module is configured to issue a sequence of bin increments to the event frame latches and logic module and wherein a successive bin increment follows a predecessor bin increment by a time interval,wherein the analog front-end module is configured to issue an event start indication to the event frame latches and logic module,wherein the analog front-end module is configured to issue at least one event stop indication to the event frame latches and logic module,wherein the event frame latches and logic module is configured to update at least one memory cell when the analog front-end module issues a bin increment, andwherein the memory cell update comprises a first bit-type following the issue of the start event indication, and wherein the memory cell update comprises a second bit-type following the issue of ...

Phase frequency detector

Described is an apparatus comprising: a first phase frequency detector (PFD) to determine a coarse phase difference between a first clock signal and a second clock signal, the first PFD to generate a first output indicating the coarse phase difference; and a second PFD, coupled to the first PFD, to determine a fine phase difference between the first clock signal and the second clock signal, the second PFD to generate a second output indicating the fine phase difference.

DTC BASED CARRIER SHIFT - ONLINE CALIBRATION

A digital to time converter (DTC) system is disclosed. The DTC system comprises a DTC circuit configured to generate a DTC output clock signal at a DTC output frequency, based on a DTC code. In some embodiments, the DTC system further comprises a calibration circuit comprising a period error determination circuit configured to determine a plurality of period errors respectively associated with a plurality consecutive edges of the DTC output clock signal. In some embodiments, each period error of the plurality of period errors comprises a difference in a measured time period between two consecutive edges of the DTC output clock signal from a predefined time period. In some embodiments, the calibration circuit further comprises an integral non-linearity (INL) correction circuit configured to determine a correction to be applied to the DTC code based on a subset of the determined period errors. 1. A digital to time converter (DTC) system , comprising:a DTC circuit configured to generate a DTC output clock signal at a DTC output frequency, based on a DTC code; and a period error determination circuit configured to determine a period error associated with successive edges of the DTC output clock signal; and', 'a correction circuit configured to determine a correction to be applied to the DTC code based on the determined period error., 'a calibration circuit comprising2. The DTC system of claim 1 , wherein the period error determination circuit is configured to determine a plurality of period errors associated with a plurality of successive edges of the DTC output clock signal.3. The DTC system of claim 2 , wherein the correction circuit is configured to determine the correction based on the plurality of period errors claim 2 , or a subset of the plurality of period errors.4. The DTC system of claim 1 , wherein the determined period error comprises a time period between a current edge of the DTC output signal and a delayed version of a pervious edge of the DTC output ...

INTEGRATED CIRCUIT, ELECTRONIC DEVICE INCLUDING THE SAME, AND OPERATING METHOD THEREOF

Disclosed is an integrated circuit, which includes a DTC block including DTCs, receiving a first reference signal and a first division signal, and outputting a second reference signal and a second division signal based on the first reference signal, the first division signal, and control codes, a TDC comparing phases of the second reference signal and the second division signal and outputting a comparison signal, a digital loop filter filtering the comparison signal, an oscillator generating an output signal based on the filtered comparison signal, a delta-sigma modulator outputting a first signal and a quantized noise signal based on first and second division ratio signals, a divider dividing a frequency of the output signal based on the first signal and outputting the first division signal, and a probability modulator generating the control codes based on the quantized noise signal. Probability density functions of the control codes are time-invariant. 1. An integrated circuit comprising:a digital-to-time converter (DTC) block including a plurality of DTCs, which receives a first reference signal and a first division signal and outputs a second reference signal and a second division signal based on the first reference signal, the first division signal, and a plurality of control codes;a time-to-digital converter (TDC) which compares a phase of the second reference signal and a phase of the second division signal and outputs a comparison signal;a digital loop filter which filters the comparison signal;an oscillator which generates an output signal based on the filtered comparison signal;a delta-sigma modulator which outputs a first signal and a quantized noise signal based on a first division ratio signal and a second division ratio signal;a divider which divides a frequency of the output signal based on the first signal and outputs the first division signal; anda probability modulator which generates the plurality of control codes based on the quantized noise ...

MODULATORS

This application relates to time-encoding modulators (TEMs). A TEM receives an input signal (S) and outputs a time-encoded output signal (S). A filter arrangement receives the input signal and also a feedback signal (S) from the TEM output, and generates a filtered signal (S) based, at least in part, on the feedback signal. A comparator receives the filtered signal and outputs a time-encoded signal (S) based at least in part on the filtered signal. The time encoding modulator is operable in a first mode with the filter arrangement configured as an active filter and in a second mode with the filter arrangement configured as a passive filter. The filter arrangement may include an op-amp, capacitance and switch network. In the first mode the op-amp is enabled, and coupled with the capacitance to provide the active filter. In the second mode the op-amp is disabled and the capacitance coupled to a signal path for the feedback signal to provide a passive filter. 146.-. (canceled)47. A photodiode module comprising:a photodiode;a time-encoding modulator (TEM) configured to receive an input signal from the photodiode;a bias node for receiving a bias voltage for operating the photodiode in a photoconductive mode;a reference node for receiving a reference voltage for operating the photodiode in a photovoltaic mode; a first state in which the photodiode is connected to the bias node to operate in the photoconductive mode; and', 'a second state in which the photodiode is connected to the reference node to operate in the photovoltaic node., 'at least one switch operable in at least48. A photodiode module according to claim 47 , wherein in the first state the photodiode is disconnected from the reference node.49. A photodiode module according to claim 47 , wherein in the second state the photodiode is disconnected from the bias node.50. A photodiode module according to claim 47 , wherein the photodiode comprises a first terminal and the at least one switch comprises a first switch ...

Resonator Device, Electronic Apparatus, And Vehicle

A resonator device includes first and second resonators and an integrated circuit device. The integrated circuit device includes a first oscillation circuit configured to oscillate the first resonator, a second oscillation circuit configured to oscillate the second resonator, and a processing circuit configured to perform processing by using frequency difference information or frequency comparison information between a first clock signal generated by oscillating the first resonator and a second clock signal generated by oscillating the second resonator. The first resonator is supported on the integrated circuit device by a first support portion. The second resonator is supported on the integrated circuit device by a second support portion.

APPARATUS AND METHODS FOR SYSTEM CLOCK COMPENSATION

Apparatus and methods for clock synchronization and frequency translation are provided herein. Clock synchronization and frequency translation integrated circuits (ICs) generate one or more output clock signals having a controlled timing relationship with respect to one or more reference signals. The teachings herein provide a number of improvements to clock synchronization and frequency translation ICs, including, but not limited to, reduction of system clock error, reduced variation in clock propagation delay, lower latency monitoring of reference signals, precision timing distribution and recovery, extrapolation of timing events for enhanced phase-locked loop (PLL) update rate, fast PLL locking, improved reference signal phase shift detection, enhanced phase offset detection between reference signals, and/or alignment to phase information lost in decimation. 1. An integrated circuit (IC) with system clock compensation , the IC comprising:a system clock generation circuit configured to generate a system clock signal based on a system reference signal;one or more circuit blocks having timing controlled by the system clock signal; anda system clock compensation circuit configured to generate one or more compensation signals operable to compensate the one or more circuit blocks for an error of the system clock signal.2. The IC of claim 1 , wherein the system clock compensation circuit comprises an error model configured to generate an estimate of the error of the system clock signal based on one or more operating conditions.3. The IC of claim 2 , wherein the error model is configured to receive a temperature signal indicating a temperature condition.4. The IC of claim 2 , wherein the error model is configured to receive a supply voltage signal indicating a supply voltage condition.5. The IC of claim 2 , wherein the IC is configured to receive one or more coefficients of the error model over an interface.6. The IC of claim 2 , wherein the system clock compensation ...

APPARATUS AND METHODS FOR COMPENSATION OF SIGNAL PATH DELAY VARIATION

Apparatus and methods for clock synchronization and frequency translation are provided herein. Clock synchronization and frequency translation integrated circuits (ICs) generate one or more output clock signals having a controlled timing relationship with respect to one or more reference signals. The teachings herein provide a number of improvements to clock synchronization and frequency translation ICs, including, but not limited to, reduction of system clock error, reduced variation in clock propagation delay, lower latency monitoring of reference signals, precision timing distribution and recovery, extrapolation of timing events for enhanced phase-locked loop (PLL) update rate, fast PLL locking, improved reference signal phase shift detection, enhanced phase offset detection between reference signals, and/or alignment to phase information lost in decimation. 1. An electronic system with compensation for signal path delay variation , the electronic system comprising: a timing circuit configured to generate an output signal based on timing of an input reference signal;', 'an output pin configured to receive the output signal from the timing circuit and', 'a delay compensation circuit configured to provide one or more compensation signals to the timing circuit; and, 'an integrated circuit (IC) comprisinga signal path configured to route the output signal from the output pin to a destination node,wherein the one or more compensation signals are operable to digitally compensate the timing circuit for a variation in delay of the signal path.2. The electronic system of claim 1 , wherein the delay compensation circuit comprises a delay model configured to generate an estimate of the variation in delay based on one or more operating conditions.3. The electronic system of claim 2 , wherein the delay model is configured to receive a temperature signal indicating a temperature condition.4. The electronic system of claim 2 , wherein the IC further comprises an interface ...

Multi-level signal clock and data recovery

A system for retiming a multi-level signal that forms an eye diagram when plotted, such as a PAM4 signal that includes an equalizer configured to create an equalized signal and a first amplifier configured to amplify the equalized signal, responsive to a first amplifier control signal, to create a first amplified signal, and a second amplifier configured to amplify the equalized signal, responsive to a second amplifier control signal, to create a second amplified signal. An eye monitor processes the equalized signal, the first amplified signal, and the second amplified signal to create a first retiming clock phase signal and a second retiming clock phase signal, which control sampling times for flip-flops. One or more delays and one or more emphasis modules are configured to delay and introduce emphasis into an output from the flip-flops, the resulting signals are combined in a summing junction to create the retimed signal.

TIME-TO-VOLTAGE CONVERTER USING CORRELATED DOUBLE SAMPLING

A time-to-voltage converter is configured to generate an output voltage signal and a correlated reference voltage signal. The time-to-voltage converter includes a current source configured to generate a bias current through a current source output node. The time-to-voltage converter includes a first switched-capacitor circuit coupled to the current source output node and configured to generate the output voltage signal based on an input time signal and the bias current during a first interval. The time-to-voltage converter includes a second switched-capacitor circuit coupled to the current source output node and configured to generate the correlated reference voltage signal based on a reference time signal and the bias current during a second interval. The first interval and the second interval are non-overlapping intervals. 1. An apparatus comprising:a time-to-voltage converter configured to generate an output voltage signal and a correlated reference voltage signal, a current source configured to generate a bias current through a current source output node;', 'a first switched-capacitor circuit coupled to the current source output node and configured to generate the output voltage signal based on an input time signal and the bias current during a first interval; and', 'a second switched-capacitor circuit coupled to the current source output node and configured to generate the correlated reference voltage signal based on a reference time signal and the bias current during a second interval, the first interval and the second interval being non-overlapping intervals., 'wherein the time-to-voltage converter comprises2. The apparatus claim 1 , as recited in claim 1 , wherein the second switched-capacitor circuit comprises:a reference capacitor configured to sample a current source output node to develop a reference voltage during the second interval; anda hold capacitor selectively coupled in parallel with the reference capacitor and configured to hold the reference ...

TIME-TO-DIGITAL CONVERTERS WITH LOW AREA AND LOW POWER CONSUMPTION

TDCs for converting time periods to digital values are disclosed. An example TDC includes a ring oscillator and a residue generation circuit. Each stage of the residue generation circuit is configured to operate on outputs from two different stages of the ring oscillator. The TDC further includes a counter for counting the number of times that an output of one of the stages of the ring oscillator switches between being at a first signal level and being at a second signal level during a time period that is being converted to a digital value. The TDC also includes a combiner for generating the digital value by combining a value indicative of the number of times counted by the counter and an output of the residue generation circuit. Such a TDC may have relatively low area and low power consumption compared to the conventional TDC designs, while yielding sufficiently linear behavior. 1. A device , comprising:a ring oscillator; anda residue generation circuit; an input of a first stage of the residue generation circuit is coupled to an output of a first stage of the ring oscillator and an output of a last stage of the ring oscillator,', 'an input of a second stage of the residue generation circuit is coupled to the output of the first stage of the ring oscillator and an output of a second stage of the ring oscillator, and', 'an input of a last stage of the residue generation circuit is coupled to an output of a one before last stage of the ring oscillator and the output of the last stage of the ring oscillator., 'wherein at least one of2. The device according to claim 1 , wherein:the ring oscillator includes a plurality of stages, the plurality of stages including the first stage of the ring oscillator, the second stage of the ring oscillator, the one before last stage of the ring oscillator, and the last stage of the ring oscillator, andthe device further includes a counter, coupled to an output of one of the plurality of stages of the ring oscillator, the counter to ...

TIME DOMAIN RATIOMETRIC READOUT INTERFACES FOR ANALOG MIXED-SIGNAL IN MEMORY COMPUTE CROSSBAR NETWORKS

A circuit configured to compute matrix multiply-and-add calculations that includes a digital-to-time converter configured to receive a digital input and output a signal proportional to the digital input and modulated in time-domain associated with a reference time, a memory including a crossbar network, wherein the memory is configured to receive the time modulated signal from the digital-to-time converter and output a weighted signal scaled in response to network weights of the crossbar network and the time modulated input signal, and an output interface in communication with the crossbar network and configured to receive its weighted output signal and output a digital value proportional to at least the reference time using a time-to-digital converter. 1. A circuit configured to compute matrix multiply-and-add calculations , comprising:a digital-to-time converter configured to receive a digital input and output a signal proportional to the digital input and modulated in time-domain associated with a reference time;a memory including a crossbar network, wherein the memory is configured to receive the time modulated signal from the digital-to-time converter and output a weighted signal scaled in response to network weights of the crossbar network and the time modulated signal; andan output interface in communication with the crossbar network and configured to receive its weighted output signal and output a digital value proportional to at least the reference time using a time-to-digital converter.2. The circuit of claim 1 , wherein the circuit includes a reference clock associated with the digital-to-time converter and the time-to-digital converter.3. The circuit of claim 1 , wherein the network weights include one or more electrical elements configured to scale the signal proportional to the digital input and modulated in time domain.4. The circuit of claim 1 , wherein the circuit includes an integrator for accumulation of the weighted signal scaled in response to ...

SYSTEMS AND METHODS FOR DETERMINING TRUE COINCIDENCE EVENTS

The present disclosure relates to systems and methods for determining true coincidence events. The systems and methods may determine original coincidence events based on time of occurrence of a plurality of single events. The systems and methods may also determine random coincidence events by processing the plurality of single events based on cycle offsets of detector units that detect the plurality of single events. A difference of any two cycle offsets may be greater than a predetermined coincidence window width. The systems and methods may then determine the true coincidence events based on the original coincidence events and the random coincidence events. 1. A device for determining coincidence events in a PET system , comprising:one or more detector rings; and a first coincidence event includes two first single events that are corresponding to each other, and', 'a second coincidence event includes a first single event and a second single event, the first single event being a single event from a detector ring corresponding to the coincidence module and the second single event being a single event from a detector ring not corresponding to the coincidence module., 'the coincidence events determined by a coincidence module include first coincidence events and second coincidence events, wherein, 'one or more coincidence modules, each corresponding to each of the one or more detector rings, respectively, the one or more coincidence modules being configured to determine coincidence events based on single events detected by the one or more detector rings, wherein2. The device of claim 1 , wherein the coincidence module includes a first coincidence unit and a second coincidence unit claim 1 , wherein:the first coincidence unit is configured to obtain multiple first single events and determine multiple first coincidence events based on the multiple first single events; andthe second coincidence unit is configured to obtain multiple first single events and multiple second ...

INTEGRAL A/D CONVERTER AND CMOS IMAGE SENSOR

The integral type Analog/Digital (AD) converter includes: a comparator configured to compare a reference voltage of a ramp waveform with an input voltage and output a comparison signal; a DLL circuit configured to generate a plurality of clock signals; a delay adjustment circuit configured to delay the comparison signal; a counter configured to count a time from starting of changing of the ramp waveform to the inversion of the outputting from the delay adjustment circuit and output the counted result as a high-order bit; and a TDC configured to latch and decode the plurality of clock signals when the output of the delay adjustment circuit is inverted and output the latched and decoded result as a low-order bit, wherein the TDC starts an operation thereof by the inversion of the comparison signal, and stops the operation thereof by the inversion of the output signal of the delay adjustment circuit. 1. An integral type Analog/Digital (AD) converter comprising:a comparator configured to compare a reference voltage of a ramp waveform linearly changed according to a passing of time with an input voltage and output a comparison signal for the reference voltage and the input voltage;a multi-phase clock generation circuit configured to generate a plurality of clock signals including a main clock signal and clock signals having phases different from that of the main clock signal;a delay adjustment circuit configured to delay the comparison signal output from the comparator by a time period longer than one period of the main clock signal, and output the delayed comparison signal;a counter configured to count a time from starting of changing of the ramp waveform to the inversion of the outputting from the delay adjustment circuit, based on the signals output from the delay adjustment circuit and the main clock signal, and output the counted result as a high order bit; anda time to digital converter configured to latch the plurality of clock signals generated by the multi-phase ...

Analog-digital converter

AD conversion is performed by using a combination of a parallel AD converter that includes a plurality of comparators to compare an input potential of an analog input signal sampled by a track and hold circuit and reference potentials different from one another and determines a value of a predetermined number of bits on the higher-order side of a digital signal and a single-slope AD converter that reduces the input potential of the analog input signal sampled by the track and hold circuit at a constant speed, converts a time taken until the reduced input potential becomes equal to a reference potential corresponding to the value determined by the parallel AD converter to a digital value, and determines a remaining value on the lower-order side of the digital signal, and thereby the number of bits of the single-slope AD converter can be reduced and high-speed AD conversion is enabled with a small area and low power consumption.

SYSTEM FOR PHASE CALIBRATION OF PHASE LOCKED LOOP

A system for phase control of a Phased Locked Loop, PLL, is disclosed. The system includes the PLL. The PLL includes an oscillator configured to generate an output signal; a frequency divider configured to generate a feedback signal by dividing the output signal from the oscillator; a first phase detector arrangement configured to output a first control signal to control the oscillator in response to a detection of a phase deviation between a reference signal and the feedback signal. A second phase detector is configured to receive the feedback signal from the frequency divider and the reference signal, and generate an output signal. A phase calibration circuit is configured to receive the output signal from the second phase detector and generate a second control signal to adjust a phase of the output signal of the oscillator. 1. A system for phase control of a Phased Locked Loop , PLL , the system comprising the PLL , an oscillator configured to generate an output signal;', 'a frequency divider configured to generate a feedback signal by dividing the output signal from the oscillator; and', 'a first phase detector arrangement configured to output a first control signal to control the oscillator in response to a detection of a phase deviation between a reference signal and the feedback signal; and, 'the PLL including a second phase detector configured to receive the feedback signal from the frequency divider and the reference signal, and generate an output signal; and', 'a phase calibration circuit configured to receive the output signal from the second phase detector and generate a second control signal to adjust a phase of the output signal of the oscillator., 'the system further comprises2. The system according to claim 1 , wherein the second phase detector is a binary phase detector.3. The system according to claim 1 , wherein the phase calibration circuit comprises:a summing component configured to sum the output signal from the second phase detector; anda ...

HETEROGENEOUS SAMPLING DELAY LINE-BASED TIME TO DIGITAL CONVERTER

A delay line-based time to digital converter includes: a coarse counter for counting a pulse of a timing clock and measuring a time when an edge of an input signal is detected; a fine time interpolator including a plurality of first delay elements and a plurality of second delay elements, a delay line with the input signal as an input, and a flip-flop unit with outputs of the first delay element or outputs of the second delay elements as inputs and the timing clock as an operation frequency; and a timestamp generator for receiving a digital value on a time measured by the coarse counter and the fine time interpolator, and generating a timestamp on the input signal by using the received digital value. 1. A delay line-based time-to-digital converter comprising:a coarse counter for counting a pulse of a timing clock and measuring a time when an edge of an input signal is detected;a fine time interpolator including a plurality of first delay elements and a plurality of second delay elements, a delay line with the input signal as an input, and a flip-flop unit with outputs of the first delay element or outputs of the second delay elements as inputs and the timing clock as an operation frequency; anda timestamp generator for receiving a digital value on a time measured by the coarse counter and the fine time interpolator, and generating a timestamp on the input signal by using the received digital value.2. The delay line-based time-to-digital converter of claim 1 , whereinthe fine time interpolator further includesa multiplexer unit having outputs of the first delay element and outputs of the second delay elements as inputs, and outputting one of the input signals, andthe output of the multiplexer unit is an input to the flip-flop unit.3. The delay line-based time-to-digital converter of claim 1 , further comprisinga fine time information generator for calculating a digital value of a fine code for measuring a fine time by adding numbers of a value that is passed through ...

Time-To-Digital Converter Circuit and Method for Single-Photon Avalanche Diode Based Depth Sensing

A self-calibration time-to-digital converter (TDC) integrated circuit for single-photon avalanche diode (SPAD) based depth sensing is disclosed. The circuit includes a SPAD matrix with a plurality of SPAD pixels arranged in m rows and n columns, the SPAD pixels in each column of SPAD pixels are connected by a column bus; a global DLL unit with n buffers and n clock signals; and an image signal processing unit for receiving image signals from the column TDC array. The circuit can also include a row control unit configured to enable one SPAD pixel in each row for a transmitting signal; a circular n-way multiplexer for circularly multiplexing n clock signals in the global DLL unit; a column TDC array with n TDCs, each TDC further comprises a counter and a latch, the latch of each TDC is connected to the circular n-way multiplexer for circular multiplexing. 1. A self-calibration time-to-digital converter (TDC) integrated circuit for single-photon avalanche diode (SPAD) based depth sensing , the circuit comprising:a SPAD matrix with a plurality of SPAD pixels arranged in m rows and n columns, wherein the SPAD pixels in each column of SPAD pixels are connected by a column bus;a global delay-locked loop (DLL) unit with n buffers and n clock signals; andan image signal processing unit for receiving image signals from the column TDC array.2. The circuit of claim 1 , wherein the circuit further comprises:a row control unit configured to enable one SPAD pixel in each row for a transmitting signal.3. The circuit of claim 2 , wherein the circuit further comprises:a circular n-way multiplexer for circularly multiplexing n clock signals in the global DLL unit.4. The circuit of claim 3 , wherein the circuit further comprises:a column TDC array with n TDCs, wherein each TDC further comprises a counter and a latch, wherein the latch of each TDC is connected to the circular n-way multiplexer for circular multiplexing.5. The circuit of claim 4 , wherein the SPAD matrix is implemented ...

TIME DIFFERENCE ADJUSTMENT CIRCUIT AND TIME-TO-DIGITAL CONVERTER INCLUDING THE SAME

A time difference adjustment circuit includes two flip-flop circuits, a delay circuit, and a reset circuit. The delay circuit includes first and second transistors of a first polarity and third and fourth transistors of a second polarity, wherein drains of the first and third transistors are coupled to each other, drains of the second and fourth transistors are coupled to each other, the drains of the first and third transistors and a gate of the fourth transistor are coupled to each other, an input signal is coupled to a gate of the first transistor, an output signal is supplied from the drains of the second and fourth transistors, and first and second reset signals are respectively coupled to gates of the second and third transistors. 1. A time difference adjustment circuit for adjusting a time difference between edges of two input signals , comprising:first and second flip-flop circuits each configured to receive a corresponding one of the two input signals as a clock input;a delay circuit configured to delay an output signal of the first flip-flop circuit to obtain a delayed signal, and output the delayed signal; anda reset circuit configured to detect an edge of an output signal of the delay circuit and an edge of an output signal of the second flip-flop circuit to output first and second reset signals having complementary logical values, whereinthe first and second flip-flop circuits are reset by the first or second reset signal,the delay circuit includes a plurality of cascade-connected minimum-delay units each including first and second transistors of a first polarity and third and fourth transistors of a second polarity,a drain of the first transistor is coupled to a drain of the third transistor,a drain of the second transistor is coupled to a drain of the fourth transistor,the drains of the first and third transistors are coupled to a gate of the fourth transistor,an input signal to each of the minimum-delay units is coupled to a gate of the first ...

OSCILLATION CIRCUIT AND INTERFACE CIRCUIT

An oscillation circuit has a voltage generator configured to generate a linearly changing voltage, a voltage level of which linearly changes as time passes, a first comparator configured to compare the linearly changing voltage with a first reference voltage, a second comparator configured to compare the linearly changing voltage with a second reference voltage having a higher voltage level than the first reference voltage, a time-to-digital converter configured to output a bit sequence signal in accordance with a time difference between a time when the first comparator detects that the linearly changing voltage matches the first reference voltage and a time when the second comparator detects that the linearly changing voltage matches the second reference voltage, and an oscillator configured to generate an oscillation signal that oscillates at a frequency according to the bit sequence signal. 1. An oscillation circuit comprising:a voltage generator configured to generate a linearly changing voltage, a voltage level of which linearly changes as time passes;a first comparator configured to compare the linearly changing voltage with a first reference voltage;a second comparator configured to compare the linearly changing voltage with a second reference voltage having a higher voltage level than the first reference voltage;a time-to-digital converter configured to output a bit sequence signal in accordance with a time difference between a time when the first comparator detects that the linearly changing voltage matches the first reference voltage and a time when the second comparator detects that the linearly changing voltage matches the second reference voltage; andan oscillator configured to generate an oscillation signal that oscillates at a frequency according to the bit sequence signal.2. The oscillation circuit according to claim 1 , further comprising a third comparator configured to compare the linearly changing voltage with a third reference voltage having a ...

Power Down Detection for Non-Destructive Isolation Signal Generation

A power detection circuit for detecting powering down of a voltage domain in an integrated circuit is disclosed. The power detection circuit is placed in or near the voltage domain in the integrated circuit to provide power detection on the integrated circuit. The power detection circuit detects powering down of the voltage domain to provide an isolation enable signal to another voltage domain that interfaces with the powering down voltage domain. The isolation enable signal may be used by an isolation cell coupled to the non-powering down voltage domain to prevent corrupted logic being received from the powering down voltage domain. 1. A device , comprising:a first time-to-digital converter circuit coupled to a first power supply, wherein the first time-to-digital converter circuit includes a series of first buffers coupled to a plurality of first flops; anda second time-to-digital converter circuit coupled to a second power supply, wherein the second time-to-digital converter circuit includes a series of second buffers coupled to a plurality of second flops;wherein the first time-to-digital converter circuit and the second time-to-digital converter circuit are configured to receive an input data signal; andwherein the device is configured to provide an isolation signal to at least one circuit block coupled to the second power supply when a value for a difference between a number of the first flops that receive the input data signal over a predetermined time period and a number of the second flops that receive the input data signal over the predetermined time period is below a threshold value for the difference.2. The device of claim 1 , wherein the first time-to-digital converter circuit and the second time-to-digital converter circuit operate at a lower frequency than the at least one circuit block.3. The device of claim 1 , wherein the second power supply is a substantially constant voltage power supply.4. The device of claim 1 , further comprising a level ...

FREQUENCY SYNTHESIZER WITH INJECTION PULLING/PUSHING SUPPRESSION/MITIGATION AND RELATED FREQUENCY SYNTHESIZING METHOD THEREOF

A frequency synthesizer includes a phase-locked loop (PLL) and a loop bandwidth controller. The PLL generates an output clock according to a reference clock. The loop bandwidth controller checks at least one indicator indicative of injection pulling/pushing of the PLL to configure a loop bandwidth of the PLL. In one exemplary design, the loop bandwidth controller sets the loop bandwidth of the PLL by controlling a configuration of a loop filter included in the PLL. For example, the PLL is an all-digital phase-locked loop (ADPLL), and the loop filter is a digital loop filter of the ADPLL. 1. A frequency synthesizer , comprising:a phase-locked loop (PLL), configured to generate an output clock according to a reference clock; anda loop bandwidth controller, configured to check at least one indicator indicative of injection pulling/pushing of the PLL to configure a loop bandwidth of the PLL.2. The frequency synthesizer of claim 1 , wherein the PLL includes a loop filter claim 1 , and the loop bandwidth controller configures the loop bandwidth of the PLL by controlling a configuration of the loop filter.3. The frequency synthesizer of claim 2 , wherein the configuration of the loop filter comprises at least one of a filter coefficient setting claim 2 , a filter type claim 2 , a filter order claim 2 , and a filter gain.4. The frequency synthesizer of claim 2 , wherein the PLL is an all-digital phase-locked loop (ADPLL) claim 2 , and the loop filter is a digital loop filter of the ADPLL.5. The frequency synthesizer of claim 1 , wherein the PLL is an all-digital phase-locked loop (ADPLL) claim 1 , the ADPLL comprises a time-to-digital converter (TDC) configured to generate a digital code of a time difference between the reference clock and a feedback clock derived from the output clock claim 1 , and the loop bandwidth controller obtains the at least one indicator based on at least an output of the TDC.6. The frequency synthesizer of claim 1 , wherein the PLL is an all- ...

VERTICAL GATE GUARD RING FOR SINGLE PHOTON AVALANCHE DIODE PITCH MINIMIZATION

A photon detection device includes a single photon avalanche diode (SPAD) including a multiplication junction defined at an interface between n doped and p doped layers of the SPAD in a first region of a semiconductor layer. A vertical gate structure surrounds the SPAD in the semiconductor layer to isolate the SPAD in the first region from a second region of the semiconductor layer on an opposite side of the vertical gate structure. The SPAD laterally extends within the first region of semiconductor layer to the vertical gate structure. An inversion layer is generated in the SPAD around a perimeter of the SPAD proximate to the vertical gate structure in response to a gate bias voltage coupled to the vertical gate structure. The inversion layer isolates the SPAD from the second region of the semiconductor layer on the opposite side of the vertical gate structure. 1. A photon detection device , comprising:a single photon avalanche diode (SPAD) disposed in a first region of a first semiconductor layer, wherein the SPAD includes a multiplication junction defined at an interface between an n doped layer and a p doped layer of the SPAD in the first region of the first semiconductor layer;a vertical gate structure disposed in the first semiconductor layer proximate to the SPAD, wherein the vertical gate structure surrounds the SPAD to isolate the SPAD in the first region of the first semiconductor layer from a second region of the first semiconductor layer on an opposite side of the vertical gate structure, wherein SPAD laterally extends within the first region of first semiconductor layer to the vertical gate structure; anda depletion layer generated around a perimeter of the SPAD proximate to the vertical gate structure in response to a gate bias voltage coupled to the vertical gate structure, wherein the depletion layer isolates the SPAD from the second region of the first semiconductor layer on the opposite side of the vertical gate structure.2. The photon detection ...

Mixed-Domain Circuit with Differential Domain-Converters

A mixed-domain circuit has a differential pair of Digital-to-Time Converters (DTCs), one receiving a reference clock and the other receiving a feedback clock. A Time-to-Digital Converter (TDC) compares outputs from the differential pair of DTCs and generates a digital error value that controls a digital loop filter that controls a Digitally-Controlled Oscillator (DCO) that generates an output clock. A Multi-Modulus Divider (MMD) generates the feedback clock. An accumulated modulation from a delta-sigma modulator is compared to the digital error value by a Least-Mean Square (LMS) correlator to adjust supply voltage or current sources in the pair of DTCs to compensate for errors. A capacitor in each DTC has a charging time adjusted by the accumulated modulation. The DTC can be reduced to a Time-to-Voltage Converter (TVC) and the analog voltages on the capacitors input to an Analog-to-Digital Converter (ADC) to generate the digital error value. 1. A mixed-domain circuit comprising:a first converter having a first input in a first domain, for generating a first output in a second domain;a second converter having a second input in the first domain, for generating a second output in the second domain;wherein the first domain is selected from the group consisting of a time domain, and a digital domain;wherein the second domain is selected from the group consisting of a time domain, a digital domain, and a voltage domain;wherein the first converter is matched to the second converter, wherein a signal injected to both the first input and to the second input adjusts the first output and adjusts the second output by a substantially same amount when a same adjustment signal is applied to both the first converter and to the second converter;wherein the second domain and the first domain are different domains;a differential converter that receives the first output from the first converter, and that receives the second output from the second converter, for generating an error ...

INTEGRATED CIRCUIT DEVICE, PHYSICAL QUANTITY MEASURING DEVICE, ELECTRONIC APPARATUS, AND VEHICLE

An integrated circuit device includes: an AFE circuit (analog front-end circuit) that receives a first signal and a second signal, carries out waveform shaping of the first signal and waveform shaping of the second signal, outputs the first signal whose waveform is shaped to a first signal line, and outputs the second signal whose waveform is shaped to a second signal line; and a time-to-digital converter that receives the first signal from the AFE circuit via the first signal line, receives the second signal from the AFE circuit via the second signal line, and converts a time difference between transition timings of the first signal and the second signal into a digital value. At least one of the first signal line and the second signal line has redundant wiring for isometric wiring. 1. An integrated circuit device comprising:an analog front-end circuit that receives a first signal and a second signal, carries out waveform shaping of the first signal and waveform shaping of the second signal, outputs the first signal whose waveform is shaped to a first signal line, and outputs the second signal whose waveform is shaped to a second signal line; anda time-to-digital converter that receives the first signal from the analog front-end circuit via the first signal line, receives the second signal from the analog front-end circuit via the second signal line, and converts a time difference between transition timings of the first signal and the second signal into a digital value,wherein at least one of the first signal line and the second signal line has redundant wiring for isometric wiring.2. The integrated circuit device according to claim 1 , whereinboth of the first signal line and the second signal line have the redundant wiring, andone signal line of the first signal line and the second signal line has a longer redundant wiring length than the other signal line.3. An integrated circuit device comprising:an analog front-end circuit that receives a first signal and a ...

TIME-RESOLVING IMAGE SENSOR FOR RANGE MEASUREMENT AND 2D GREYSCALE IMAGING

An image sensor includes a time-resolving sensor and a processor. The time-resolving sensor outputs a first signal and a second signal pair in response detecting one or more photons that have been reflected from an object. A first ratio of a magnitude of the first signal to a sum of the magnitude of the first signal and a magnitude of the second signal is proportional to a time of flight of the one or more detected photons. A second ratio of the magnitude of the second signal to the sum of the magnitude of the first signal and the magnitude of the second signal is proportional to the time of flight of the one or more detected photons. The processor determines a surface reflectance of the object where the light pulse has been reflected based on the first signal and the second signal pair and may generate a grayscale image. 1. An image sensor , comprising:a time-resolving sensor comprising at least one pixel, the time-resolving sensor outputting a first signal and a second signal pair in response to detecting by the at least one pixel one or more photons that have been reflected from an object corresponding to a light pulse projected toward the object, a first ratio of a magnitude of the first signal of the pair to a sum of the magnitude of the first signal and a magnitude of the second signal of the pair being proportional to a time of flight of the one or more detected photons, and a second ratio of the magnitude of the second signal of the pair to the sum of the magnitude of the first signal and the magnitude of the second signal of the pair being proportional to the time of flight of the one or more detected photons; anda processor that determines a surface reflectance of the object where the light pulse has been reflected based on the first signal and the second signal pair.2. The image sensor of claim 1 , wherein the processor further determines a distance to the object based on the first signal and second signal pair.3. The image sensor of claim 1 , wherein the ...

TIME TO DIGITAL CONVERTER AND APPLICATIONS THEREOF

A time to digital converter includes a sample module operable to sample an input signal at multiple different instances of time. A transition detection module, formed of comparison elements, processes the sampled input signal at successive time instances so as to detect transitions in the input signal in terms of time. An output module generates detected transitions in the input signal on multiple parallel outputs. 1. A time to digital converter , comprising:a sampling module configured to sample an input signal at multiple different instances of time;a transition detection module comprising a plurality of comparison elements, each comparison element configured to process the sampled input signal at successive time instances so as to detect transitions in the input signal in terms of time; andan output module comprising multiple parallel outputs operable to output in parallel said detected transitions in the input signal.2. The time to digital converter as claimed in claim 1 , wherein each of said comparison elements comprises a two-input logic gate claim 1 , each of its inputs being connected to a respective one of adjacent outputs of said sample module.3. The time to digital converter as claimed in claim 2 , wherein each two-input logic gate comprises one of a two-input exclusive-OR gate or a two-input exclusive-NOR gate.4. The time to digital converter as claimed in claim 1 , further comprising a toggle module operable to toggle the input signal between two states on each occasion that a timing event is detected.5. The time to digital converter as claimed in claim 4 , wherein said toggle module comprises a T-type flip-flop.6. The time to digital converter as claimed in claim 1 , wherein said sample module comprises a plurality of sample elements claim 1 , each sample element being operable to sample the input signal at a different time instance.7. The time to digital converter as claimed in claim 6 , wherein each of said sample elements comprises one of a flip- ...

TIME-TO-DIGITAL CONVERTER, FREQUENCY TRACKING APPARATUS AND METHOD

Embodiments of the present invention provide a time-to-digital converter, where the time-to-digital converter includes a delay unit, a first sampling unit, and a second sampling unit. The delay unit is connected to the first sampling unit and is configured to receive a first clock signal and delay the first clock signal; the first sampling unit is configured to perform sampling on the first clock signal and generate a first phase signal, so that a first phase-locked module adjusts a frequency of the first clock signal; the delay unit is further connected to the second sampling unit and is configured to receive a frequency-adjusted first clock signal and delay the frequency-adjusted first clock signal; and the second sampling unit is configured to perform sampling on the frequency-adjusted first clock signal and generate a second phase signal. 1. A time-to-digital converter , comprising a delay unit , a first sampling unit , and a second sampling unit , whereinthe delay unit is connected to the first sampling unit and is configured to: receive a first clock signal output by a first phase-locked module; and after delaying the first clock signal, output the first clock signal to the first sampling unit;the first sampling unit is configured to: perform, by using a reference clock signal, sampling on the first clock signal output by the delay unit; generate a first phase signal; and send the first phase signal to the first phase-locked module, so that the first phase-locked module adjusts a frequency of the first clock signal according to the first phase signal, and outputs a frequency-adjusted first clock signal to the delay unit;the delay unit is further connected to the second sampling unit and is configured to: receive the frequency-adjusted first clock signal output by the first phase-locked module; and after delaying the frequency-adjusted first clock signal, output the frequency-adjusted first clock signal to the second sampling unit; andthe second sampling unit ...

Local Oscillator Phase Synchronization for Beamforming and MIMO

An initial phase of each output signal generated by a plurality of radio frequency (RF) front-end circuits is determined by mixing an input signal with a mixing signal in a mixer of the corresponding RF front-end circuit. To that end, a time difference for each of the plurality of RF front-end circuits is determined by measuring a time difference between a reference signal (common to all of the RF front-end circuits) and the mixing signal of each RF front-end circuit. The initial phase for each output signal is then determined based on the measured time difference for the corresponding RF front-end circuit. Determining the initial phase in this manner accounts for any uncertainty of the phase when the RF front-end circuits are activated, enabling the phase of the corresponding antenna element to be accurately controlled.

COMPUTE IN MEMORY CIRCUITS WITH TIME-TO-DIGITAL COMPUTATION

A memory circuit has compute-in-memory (CIM) circuitry that performs computations based on time-to-digital conversion (TDC). The memory circuit includes an array of memory cells addressable with column address and row address. The memory circuit includes CIM sense circuitry to sense a voltage for multiple memory cells triggered together. The CIM sense circuitry including a TDC circuit to convert a time for discharge of the multiple memory cells to a digital value. A processing circuit determines a value of the multiple memory cells based on the digital value. 1. A memory circuit , comprising:an array of memory cells addressable with column address and row address;compute in memory (CIM) sense circuitry to sense a voltage for multiple memory cells triggered together, the CIM sense circuitry including a time to digital converter (TDC) circuit to convert a time for discharge of the multiple memory cells to a digital value; anda processing circuit to determine a value of the multiple memory cells based on the digital value.2. The memory circuit of claim 1 , wherein the array of memory cells includes 6-transistor (6T) static random access memory (SRAM) memory cells claim 1 , 8-transistor (8T) SRAM memory cells claim 1 , or 10-transistor (10T) SRAM memory cells.3. The memory circuit of claim 1 , wherein the array of memory cells includes resistive-based random access memory (RAM) memory cells.4. The memory circuit of claim 1 , wherein the column address is to activate a wordline claim 1 , and wherein the row address is to charge a bitline.5. The memory circuit of claim 4 , wherein the bitline comprises a differential bitline claim 4 , wherein the TDC is to convert the time for discharge from a differential signal from the differential bitline.6. The memory circuit of claim 1 , wherein the TDC circuit comprises a series of delay cells claim 1 , with a number of delays in the series to correspond to a number of bits of resolution of the digital value.7. The memory circuit ...

CLOCK SYNCHRONIZER TO SYNCHRONIZE A DEVICE CLOCK WITH A CLOCK OF A REMOTE DEVICE

A device ()) with an antenna that receives a target carrier signal () from a remote target () and transmits a device carrier signal () modulated with data to communicate data between the device () and the target (), which device () comprises: clock extraction means () to extract a target clock () from the target carrier signal (); driver means () to generate the device carrier signal () from a device clock (); synchronization means () to synchronize the frequency and phase of the device clock () with the target clock (), wherein that the synchronization means () comprise: time measurement means () to measure the phase difference between the target clock () and the device clock () or an internal device clock () related to the device clock () and to provide a phase information (φ); measurement control means () to initiate a first time measurement that results in a first phase information (φ) and to initiate a second time measurement a fixed time period (ΔT) after the first time measurement that results in a second phase information (φ); frequency correction means () to correct the frequency of the device clock () and/or the internal device clock () to the frequency of the target clock () based on an evaluation of the first phase information (φ) and second phase information (φ) by evaluation means (); which measurement control means () are built to initiate a third time measurement after the frequency correction of the device clock () and/or the internal device clock () that results in a third phase information (φ) evaluated by the evaluation means () and corrected by phase correction means () which correct the phase of the device clock () to the phase of the target clock (). 1. Device with an antenna that receives a target carrier signal from a remote target and transmits a device carrier signal modulated with data to communicate data between the device and the target , which device comprises:clock extraction means to extract a target clock from the target carrier ...

MULTIPLE INPUT ANALOG-TO-DIGITAL CONVERTER DEVICE AND CORRESPONDING METHOD

A multiple-input analog-to-digital converter device includes analog-to-digital converter circuits arranged between input nodes and output nodes. The analog-to-digital converter circuits operate over respective conversion times to provide simultaneous conversion of the analog input signals into respective conversion time signals. A time-to-digital converter circuit includes timer circuitry common to the plurality of analog-to-digital converter circuits. The timer circuitry cooperates with the analog-to-digital converter circuits to convert the conversion time signals into digital output signals at the output nodes. 1. A device , comprising:a plurality of input nodes configured to receive respective analog input signals;a plurality of output nodes configured to provide respective digital output signals;a plurality of analog-to-digital converter circuits arranged between the input nodes of said plurality of input nodes and the output nodes of said plurality of output nodes, wherein the analog-to-digital converter circuits of said plurality of analog-to-digital converter circuits are configured to operate over respective conversion times to provide simultaneous conversion of said analog input signals into respective conversion time signals; anda time-to-digital converter circuit comprising timer circuitry common to the analog-to-digital converter circuits of said plurality of analog-to-digital converter circuits, said timer circuitry configured to cooperate with the analog-to-digital converter circuits of said plurality of analog-to-digital converter circuits to convert said respective conversion time signals into said respective digital output signals.2. The device of claim 1 , wherein the analog-to-digital converter circuits of said plurality of analog-to-digital converter circuits comprise:converter stages configured to convert said analog input signals into respective conversion time signals, wherein said conversion time signals are a function of values of said ...

ALL DIGITAL PHASE LOCKED LOOP WITH CONFIGURABLE MULTIPLIER HAVING A SELECTABLE BIT SIZE

An all digital phase locked loop comprises a time-to-digital converter and a configurable multiplier. The time-to-digital converter is configured to output a digital code based on a phase difference between a reference clock signal and a variable clock signal. The configurable multiplier is coupled with the time-to-digital converter. The configurable multiplier has a selectable bit size. The selectable bit size is based on a defined minimum number of bits to obtain a reciprocal of a variable clock period. The minimum number of bits is based on a comparison of a first number of bits of a divisor with a second number of bits of a quotient. The time-to-digital converter is configured to multiply the digital code by the reciprocal of the variable clock period to output a fractional error correction value. 1. An all digital phase locked loop , comprising:a time-to-digital converter configured to output a digital code based on a phase difference between a reference clock signal and a variable clock signal; anda configurable multiplier coupled with the time-to-digital converter, the configurable multiplier having a selectable bit size, the selectable bit size being based on a defined minimum number of bits to obtain a reciprocal of a variable clock period, the minimum number of bits being based on a comparison of a first number of bits of a divisor with a second number of bits of a quotient,wherein the time-to-digital converter is configured to multiply the digital code by the reciprocal of the variable clock period to output a fractional error correction value.2. The all digital phase locked loop of claim 1 , wherein the time-to-digital converter is configured to communicate a signal to cause the first number of bits of the quotient to be less than or equal to a third number of bits of 1−DX claim 1 , where D is the divisor and Xis the quotient.3. The all digital phase locked loop of claim 2 , wherein the time-to-digital converter is configured to communicate a signal to ...

Fractional-N All Digital Phase Locked Loop Incorporating Look Ahead Time To Digital Converter

A novel and useful look-ahead time to digital converter (TDC) that is applied to an all digital phase locked loop (ADPLL) as the fractional phase error detector. The deterministic nature of the phase error during frequency/phase lock is exploited to achieve a reduction in power consumption of the TDC. The look-ahead TDC circuit is used to construct a cyclic DTC-TDC pair which functions to reduce fractional spurs of the output spectrum in near-integer channels by randomly rotating the cyclic DTC-TDC structure so that it starts from a different point every reference clock thereby averaging out the mismatch of the elements. Associated rotation and dithering methods are also presented. The ADPLL is achieved using the look-ahead TDC and/or cyclic DTC-TDC pair circuit. 1. A look-ahead time to digital converter (TDC) for use in an all digital phase locked loop (ADPLL) , comprising:a plurality of controllable delay elements configured in a sequential chain configuration; anda phase prediction circuit coupled to a frequency reference (FREF) clock and operative to predict reference frequency clock edge timing and based thereon to select a number of delay elements in said chain to function as a digital to time converter and a portion of a remainder of delay elements in said chain to function as a time to digital converter.2. The look-ahead time to digital converter according to claim 1 , wherein said plurality of controllable delay elements are operative to generate an output code representing a fractional portion of a phase error used by said ADPLL to adjust the frequency of the variable clock (CKV).3. The look-ahead time to digital converter according to claim 1 , wherein said phase prediction circuit is coupled to a fractional part of a frequency command word (FCW) signal.4. The look-ahead time to digital converter according to claim 3 , wherein said fractional part of FCW signal is accumulated at said FREF clock.5. A look-ahead time to digital converter (TDC) for use in an ...

Fractional-N Frequency Synthesizer Incorporating Cyclic Digital-To-Time And Time-To-Digital Circuit Pair

A novel and useful look-ahead time to digital converter (TDC) that is applied to an all digital phase locked loop (ADPLL) as the fractional phase error detector. The deterministic nature of the phase error during frequency/phase lock is exploited to achieve a reduction in power consumption of the TDC. The look-ahead TDC circuit is used to construct a cyclic DTC-TDC pair which functions to reduce fractional spurs of the output spectrum in near-integer channels by randomly rotating the cyclic DTC-TDC structure so that it starts from a different point every reference clock thereby averaging out the mismatch of the elements. Associated rotation and dithering methods are also presented. The ADPLL is achieved using the look-ahead TDC and/or cyclic DTC-TDC pair circuit. 1. A cyclic digital to time converter and time to digital converter (DTC-TDC) circuit for use in an all digital phase locked loop (ADPLL) circuit , comprising:a plurality of controllable delay elements configured in a cyclical sequential chain configuration;a phase prediction circuit coupled to a frequency reference (FREF) clock and operative to predict reference frequency clock edge timing and based thereon to select a starting delay element in said chain, a first number of delay elements in said chain to function as a digital to time converter (DTC) and a second number of delay elements in said chain to function as a time to digital converter (TDC); andwherein said DTC and TDC elements are dynamically selected.2. The circuit according to claim 1 , wherein said the selection of said DTC and TDC elements is randomized thereby scrambling mismatches between said delay elements with a resultant reduction in fractional frequency spurs output by said ADPLL.3. The circuit according to claim 1 , wherein said plurality of controllable delay elements comprises a cyclic chain of inverter circuits.4. The circuit according to claim 1 , further comprising a dithering circuit operative to generate FREF dithering.5. The ...

APPARATUS AND METHOD FOR GENERATING TEMPERATURE-INDICATING SIGNAL USING CORRELATED-OSCILLATORS

A temperature sensor configured to generate a temperature-indicating signal with improved accuracy over a wide temperature range is disclosed. The temperature sensor includes a first oscillator configured to generate a first oscillating signal with a first frequency that varies with a sensed temperature and a reference parameter; a second oscillator configured to generate a second oscillating signal with a second frequency that varies with the reference parameter; and a time-to-digital converter (TDC) configured to generate a digital output indicative of the sensed temperature based on a ratio of the first frequency to the second frequency. Because the first and second frequencies depend on the reference parameter, and the temperature-indicating signal is a function of the ratio of the first and second frequencies, temperature-variation in the reference parameter cancels out in the temperature-indicating signal. 1. An apparatus , comprising:a first oscillator configured to generate a first oscillating signal with a first frequency that varies with a sensed temperature and a reference parameter;a second oscillator configured to generate a second oscillating signal with a second frequency that varies with the reference parameter; anda time-to-digital converter (TDC) configured to generate a digital output indicative of the sensed temperature based on a ratio of the first frequency to the second frequency.2. The apparatus of claim 1 , wherein the first frequency of the first oscillating signal is based on a proportional to absolute temperature (PTAT) parameter.3. The apparatus of claim 1 , wherein the first frequency of the first oscillating signal is based on a complementary to absolute temperature (CTAT) parameter.4. The apparatus of claim 1 , wherein the first oscillator comprisesa ring oscillator including a set of cascaded series-connected inverter-transmission gate pairs including a first inverter-transmission gate pair and a last inverter-transmission gate pair, ...

TIME TO DIGITAL CONVERTER WITH INCREASED RANGE AND SENSITIVITY

Systems and methods are described for determining a phase measurement difference between a received modulated signal and a local clock signal. An adjusted local clock phase measurement may be determined by subtracting, from the phase measurement difference, a phase correction that is based on the frequency difference between the modulator signal's carrier frequency and the local clock's frequency. A phase modulation value may be generated by scaling the adjusted local clock phase measurement. The scaling may be based on a ratio of the modulated signal's carrier frequency and the local clock's frequency. The phase correction may be based on (i) a count of periods of the modulated signal occurring between each corrected phase measurement and (ii) a difference between the carrier frequency and the local clock frequency. 1. A method comprising:receiving, at a receive phase-to-digital conversion (PDC) circuit, a modulated signal having a carrier frequency;obtaining a phase measurement between the modulated signal and a local clock signal;generating a carrier-based phase correction value by accumulating a phase-correction increment;generating a corrected phase measurement value based on a difference between the phase measurement and the carrier-based phase correction value; andgenerating a carrier phase measurement by scaling the corrected phase measurement value.2. The method of claim 1 , wherein generating the phase-correction increment is based on (i) a count of periods of the modulated signal occurring between each generation of a corrected phase measurement claim 1 , and (ii) a difference between the carrier frequency and a frequency of the local clock signal.3. The method of claim 2 , wherein generating the carrier-based phase correction value is inhibited if a rising edge of the modulated signal does not occur within a timing window.4. The method of claim 1 , wherein obtaining the phase measurement comprises:determining a coarse measurement by determining a phase ...

FREQUENCY MEASUREMENT CIRCUIT AND FREQUENCY MEASUREMENT APPARATUS

A frequency measurement circuit includes a first counter that counts a pulse number of a reference clock signal and generates first count data, a second counter that counts a pulse number of a measurement target clock signal and generates second count data, a time-to-digital conversion circuit that generates first time difference data indicating a time difference between a first timing at which the first counter starts counting of the pulse number and a second timing at which the second counter starts counting of the pulse number, and second time difference data indicating a time difference between a third timing at which the first counter ends counting of the pulse number and a fourth timing at which the second counter ends counting of the pulse number, and a calculation circuit that performs calculation based on the second count data, the first time difference data, and the second time difference data and generates frequency data indicating a frequency of the measurement target clock signal. 1. A frequency measurement circuit comprising:an oscillation circuit that generates a reference clock signal;a first counter that counts a pulse number of the reference clock signal and generates first count data;a second counter that counts a pulse number of a measurement target clock signal and generates second count data;a time-to-digital conversion circuit that generates first time difference data indicating a time difference between a first timing at which the first counter starts counting of the pulse number of the reference clock signal and a second timing at which the second counter starts counting of the pulse number of the measurement target clock signal, and second time difference data indicating a time difference between a third timing at which the first counter ends counting of the pulse number of the reference clock signal and a fourth timing at which the second counter ends counting of the pulse number of the measurement target clock signal; anda calculation ...

Spur cancellation for spur measurement

A spur measurement system uses a first device with a spur cancellation circuit that cancel spurs responsive to a frequency control word identifying a spurious tone of interest. A device under test generates a clock signal and supplies the clock signal to the first device through an optional divider. The spur cancellation circuit in the first device generates sine and cosine weights at the spurious tone of interest as part of the spur cancellation process. A first magnitude of the spurious tone in a phase-locked loop in the first device is determined according to the sine and cosine weights and a second magnitude of the spurious tone in the clock signal is determined by the first magnitude divided by gains associated with the first device.

METHOD AND COMPUTING DEVICE WITH A MULTIPLIER-ACCUMULATOR CIRCUIT

Provided is a multiplier-accumulator (MAC) system, circuit, and method. The MAC system includes a MAC circuit, including a plurality of resistors, having respective resistances, a capacitor connected to the plurality of resistors to charge, in response to a plurality of input signals, the capacitor with electric charge, and a time-to-digital converter (TDC) configured to convert information of a charge time of the capacitor, due to the electric charge, into a digital value, wherein the digital value is an accumulation result of the MAC circuit. 1. A multiplier-accumulator (MAC) system , comprising: a plurality of resistors, having respective resistances;', 'a capacitor connected to the plurality of resistors to charge, in response to a plurality of input signals, the capacitor with electric charge; and', 'a time-to-digital converter (TDC) configured to convert information of a charge time of the capacitor, due to the electric charge, into a digital value,', 'wherein the digital value is an accumulation result of the MAC circuit., 'a MAC circuit, including2. The system of claim 1 ,wherein the plurality of resistors and the capacitor are configured as a first output line,wherein the MAC circuit further comprises one or more other output lines, each respectively including respective plural resistors, having respective resistances, connected to a respective other capacitor,wherein the respective other capacitor, of each of the one or more other output lines, is configured to be charged, in response to the plurality of input signals, with respective electric charge, andwherein the respective other capacitor and the capacitor have a same capacitance.3. The system of claim 2 ,wherein the time-to-digital converter (TDC) is configured to convert respective information of respective charge times of the respective other capacitor of the one or more other output lines, into respective digital values, andwherein the digital value and the respective digital values are the ...

Digital Phase Locked Loop and Method for Operating the Same

The present disclosure relates to a Digital Phase Locked Loop (DPLL) for phase locking an output signal to a reference clock signal. The DPLL comprises a phase detector for detecting a phase error of a feedback signal with respect to the reference clock signal. The DPLL comprises a digitally controlled oscillator for generating the output signal based at least on a frequency control word and at least one control signal representative of the phase error. The phase detector comprises an integer circuit for generating a first control signal representative of an integer phase error. The phase detector comprises a fractional circuit comprising a Time-to-Digital Converter (TDC) for processing the feedback signal and a delayed reference clock signal. The fractional circuit is provided for generating from the TDC output a second control signal representative of a fractional phase error. The DPLL comprises an unwrapping unit for unwrapping the TDC output. 1. A Digital Phase Locked Loop (DPLL) for phase locking an output signal to a reference clock signal , the DPLL comprising: an integer circuit configured for generating a first control signal representative of an integer phase error; and', 'a fractional circuit comprising a Time-to-Digital Converter (TDC) configured for processing the feedback signal and a delayed reference clock signal to generate a TDC output, wherein the fractional circuit is configured for generating from the TDC output a second control signal representative of a fractional phase error;, 'a phase detector configured for detecting a phase error of a feedback signal with respect to the reference clock signal, wherein the feedback signal is the output signal of the DPPL fed back to an input of the phase detector, wherein the phase detector comprisesa digitally controlled oscillator (DCO) configured for generating the output signal based at least on a frequency control word and at least one control signal representative of the phase error detected by the ...

MEASUREMENT APPARATUS, RANGING APPARATUS, AND MEASUREMENT METHOD

A measurement apparatus (A) according to an embodiment includes: a time-to-digital converter circuit () that measures a time period between an emission timing at which light is emitted from a light emitting unit () and a time point at which a light receiving unit () receives the light; a delay means (A) that adds, to the time period measured by the time-to-digital converter circuit, a positive or a negative delay having a length that is different from a cycle of a clock used by the time-to-digital converter circuit and that is used as a unit amount of delay; and a storage unit () that stores therein time information that indicates the time period measured by the time-to-digital converter circuit and delay information that indicates an amount of delay to be added by the delay means, in association with each other, related to each of a case in which a delay is added by the delay means and a case in which a delay is not added by the delay means. 1. A measurement apparatus comprising:a time-to-digital converter circuit that measures a time period between an emission timing at which light is emitted from a light emitting unit and a time point at which a light receiving unit receives the light;a delay means that adds, to the time period measured by the time-to-digital converter circuit, a positive or a negative delay having a length that is different from a cycle of a clock used by the time-to-digital converter circuit and that is used as a unit amount of delay; anda storage unit that stores therein time information that indicates the time period measured by the time-to-digital converter circuit and delay information that indicates an amount of delay to be added by the delay means, in association with each other, related to each of a case in which a delay is added by the delay means and a case in which a delay is not added by the delay means.2. The measurement apparatus according to claim 1 , whereinthe time-to-digital converter circuit is configured to start measurement ...

DELAY TIME CALIBRATION OF OPTICAL DISTANCE MEASUREMENT DEVICES, AND ASSOCIATED SYSTEMS AND METHODS

Representative embodiments of the present technology include a device for measuring distance to an object. The device comprises a light emitter configured to emit an outbound light pulse and a light sensor configured to receive a returning light pulse and output a pulse signal representing the returning light pulse. The device further comprises a field-programmable gate array (FPGA) coupled to the light sensor and including a time-to-digital converter (TDC) having a series of sequentially coupled delay units. Individual sequentially coupled delay units are associated with corresponding individual delay times. At least some of the sequentially coupled delay units have different individual delay times. The TDC is configured to measure timing information of the pulse signal based at least in part on the individual delay times of the sequentially coupled delay units. The device further includes a controller configured to calculate the distance to the object based on the timing information. 1. A device for measuring distance to an object , the device comprising:a light emitter configured to emit an outbound light pulse;a light sensor configured to receive a returning light pulse reflected from the object and output a pulse signal representing the returning light pulse;a field-programmable gate array (FPGA) coupled to the light sensor and including a time-to-digital converter (TDC) having a series of sequentially coupled delay units, individual sequentially coupled delay units associated with corresponding individual delay times, wherein at least some of the sequentially coupled delay units have different individual delay times, and wherein the TDC is configured to measure timing information of the pulse signal based at least in part on the individual delay times of the sequentially coupled delay units; anda controller configured to calculate the distance to the object based on the timing information.2. The device of wherein the light emitter claim 1 , light sensor claim ...

TIME-TO-DIGITAL CONVERTER, CIRCUIT DEVICE, PHYSICAL QUANTITY MEASUREMENT APPARATUS, ELECTRONIC APPARATUS, AND VEHICLE

A time-to-digital converter includes a clock signal generation circuit that generates a first cycle signal having a voltage level that monotonously increases or decreases in a cycle corresponding to the clock frequency of a reference clock signal and further generates a first clock signal based on a first signal and the first cycle signal, a clock signal generation circuit that generates a second cycle signal having a voltage level that monotonously increases or decreases in a cycle corresponding to the clock frequency of a reference clock signal and further generates a second clock signal based on a second signal and the second cycle signal, and a processing circuit that converts a time difference between the transition timing of the first signal and the transition timing of the second signal into a digital value based on the first and second clock signals. 1. A time-to-digital converter comprising:a first clock signal generation circuit configured to receive a first reference clock signal having a first clock frequency and generate a first cycle signal having a voltage level that monotonously increases or decreases in a cycle corresponding to the first clock frequency, and further generate a first clock signal based on a first signal and the first cycle signal;a second clock signal generation circuit configured to receive a second reference clock signal having a second clock frequency different from the first clock frequency and generate a second cycle signal having a voltage level that monotonously increases or decreases in a cycle corresponding to the second clock frequency, and further generate a second clock signal based on a second signal and the second cycle signal; anda processing circuit configured to convert a time difference between a transition timing of the first signal and a transition timing of the second signal into a digital value based on the first and second clock signals.2. The time-to-digital converter according to claim 1 ,wherein the first ...

TIME-TO-DIGITAL CONVERTER, CIRCUIT DEVICE, PHYSICAL QUANTITY MEASURING DEVICE, ELECTRONIC APPARATUS, AND VEHICLE

A time-to-digital converter includes first and second oscillation circuits, first and second sampling circuits, and a processing circuit. The first and second oscillation circuits start an oscillation operation in accordance with first and second signals and output first and second clock signals, respectively. The first and second sampling circuits perform sampling of the first and second clock signals by a first reference clock signal and output first and second output signals, respectively. The processing circuit obtains first frequency information and first phase information of the first clock signal and second frequency information and second phase information of the second clock signal based on the first and second output signals of the first and second sampling circuits, and obtains a digital value corresponding to a time difference of a transition timing between the first and second signals. 1. A time-to-digital converter comprising:a first oscillation circuit that starts an oscillation operation in accordance with a first signal and outputs a first clock signal;a second oscillation circuit that starts an oscillation operation in accordance with a second signal and outputs a second clock signal;a first sampling circuit that performs sampling of the first clock signal by a first reference clock signal and outputs a first output signal;a second sampling circuit that performs sampling of the second clock signal by the first reference clock signal and outputs a second output signal; anda processing circuit that obtains first frequency information and first phase information of the first clock signal and second frequency information and second phase information of the second clock signal based on the first output signal of the first sampling circuit and the second output signal of the second sampling circuit, and obtains a digital value corresponding to a time difference of a transition timing between the first signal and the second signal based on the first ...

Time-To-Digital Converter, Circuit Device, Physical Quantity Measurement Apparatus, Electronic Instrument, And Vehicle

A time-to-digital converter includes a first oscillation circuit that starts oscillating at the transition timing of a first signal and generates a first clock signal having a first clock frequency, a second oscillation circuit that starts oscillating at the transition timing of a second signal and generates a second clock signal having a second clock frequency, a first adjustment circuit that adjusts the oscillation frequency of the first oscillation circuit based on a reference clock signal, a second adjustment circuit that adjusts the oscillation frequency of the second oscillation circuit based on the reference clock signal, and a processing circuit that converts the time difference between the transition timing of the first signal and the transition timing of the second signal into a digital value based on the first and second clock signals. 1. A time-to-digital converter comprising:a first oscillation circuit that starts oscillating at a transition timing of a first signal and generates a first clock signal having a first clock frequency;a second oscillation circuit that starts oscillating at a transition timing of a second signal and generates a second clock signal having a second clock frequency different from the first clock frequency;a first adjustment circuit that measures the first clock frequency based on a reference clock signal and adjusts an oscillation frequency of the first oscillation circuit in such a way that the first clock frequency is equal to a first target frequency;a second adjustment circuit that measures the second clock frequency based on the reference clock signal and adjusts an oscillation frequency of the second oscillation circuit in such a way that the second clock frequency is equal to a second target frequency; anda processing circuit that converts a time difference between the transition timing of the first signal and the transition timing of the second signal into a digital value based on the first and second clock signals.2. ...

Oversampling time-to-digital converter

An oversampling time-to-digital converter includes an input pulse generation circuit generating two pulse signals, a reference pulse generation circuit generating two pulse signals, a swap circuit swapping two pulse signals, a multiplexer selecting an output of the input pulse generation circuit or the swap circuit, a time-to-current conversion circuit outputting two pulse currents in accordance with an output of the multiplexer, a current mirror circuit whose input and output terminals receive the two pulse currents, an integration circuit integrating a differential current between the pulse current connected to the output terminal of the current mirror circuit and an output current of the current mirror circuit, and a comparison circuit comparing an output signal of the integration circuit to a threshold voltage. An output signal of the comparison circuit is given to the swap circuit as a control signal.

PHOTON-BASED TARGET DETECTION USING COARSE AND FINE BINNING

Exemplary aspects of the present disclosure involve a SPAD receiver having circuitry for photon detection and having a plurality TDCs (time-to-digital converters) to detect multiple photons. Such circuitry may be set to accumulate photon counts over relatively coarse time ranges. In such accumulation of photons in relatively coarse time ranges, photon counts may be binned for each time range. Possible targets may then be identified by examination of the bins. Upon identification of the possible targets, a plurality of TDCs may be used over a more refined time ranges such as the time ranges corresponding to the identified possible target or targets. 1. A method comprising:operating a receiver, having SPAD (single-photon avalanche photodiode) circuitry for photon detection, with multiple photon detections using a plurality of TDCs (time-to-digital converters) being set to accumulate detected photon counts over relatively coarse time ranges;binning and identifying one or more possible target bins associated with the detected photon counts accumulated over the relatively coarse time ranges; andusing the plurality of TDCs to accumulate detected photon counts over one or more relatively fine time ranges corresponding to the identified one or more possible target bins.2. The method of claim 1 , wherein operating the receiver is for Lidar (Light Detection and Ranging) detection of at least one object that is among said one or more possible target bins associated with said binning and identification claim 1 , and further including operating the receiver is for more refined Lidar detection of said at least one object.3. The method of claim 1 , further including: accumulating detected photon counts in an array of bins in response to being detected; and operating the receiver for Lidar (Light Detection and Ranging) detection of at least one object in an environment that causes at least one of the bins in said array of bins to be associated with said at least one object and at ...

Method and apparatus for conversion of time interval to digital word using successive approximation sheme

A method and apparatus for conversion of a time interval to a digital word, the time interval being mapped to a difference of a length of a reference time and a length of a signal time. Reference time is generated from an instant when the beginning of the time interval is detected, and the signal time is generated from an instant when the end of the time interval is detected by the use the control module. The generation of the reference time and the signal time is terminated at the same instant. In the apparatus, bottom plates of capacitors of the set of capacitors are connected to a ground of the circuit, and top plates of these capacitors are connected, respectively, to moving contacts of change-over switches. First, second, and third stationary contacts are connected to the signal rail, the ground of the circuit, and to the reference rail (R).

CAPATICANCE-TO-DIGITAL CONVERTER

A capacitance-to-digital-converter includes a first delay block configured to output a first signal after a first delay based on a voltage at a capacitive sensor, the capacitive sensor configured to be iteratively discharged; a second delay block configured to output a second signal after a second delay; and a capacitance determination unit configured to determine a value indicative of a capacitance sensed by the capacitive sensor. This determination is based on: a number of clock periods during which the first delay is less than a third delay; a first time difference between receipt of the first signal and the second signal during a last clock period during which the first delay is less than the third delay; and a second time difference between receipt of the first signal and receipt of the second signal during a first clock period during which the first delay is greater than the third delay. 1. A capacitance to digital converter comprising:a first delay block having an input node configured to receive a voltage from a capacitive sensor and a clock node configured to receive a clock signal defining a clock period until a subsequent clock signal, the first delay block configured to output a first output signal after a first delay time in response to receiving the clock signal each clock period, the first delay time based on the voltage at the input node, and wherein the first delay block is configured to provide for iterative discharging of the capacitive sensor based on the clock signal;a second delay block having an input node configured to receive a first voltage and a clock node configured to receive the clock signal, the second delay block configured to output a second output signal after a second delay time in response to the clock signal, the second delay time based on the first voltage; and the number of clock periods during which the first delay time is less than a third delay time;', 'a first time difference between a time of receipt of the first output ...

SYSTEM AND METHOD OF CALIBRATING INPUT SIGNAL TO SUCCESSIVE APPROXIMATION REGISTER (SAR) ANALOG-TO-DIGITAL CONVERTER (ADC) IN ADC-ASSISTED TIME-TO-DIGITAL CONVERTER (TDC)

An apparatus and a method. The apparatus includes a counter array; a ring oscillator that is electrically coupled to the counter array, where the counter array counts a number of cycles in the ring oscillator; an analog-to-digital converter (ADC) driver that is electrically coupled to the ring oscillator; and an ADC that is electrically coupled to the ADC driver, where an output of the ADC is electrically coupled to the ring oscillator. 1. An apparatus , comprising:a counter array;a ring oscillator that is electrically coupled to the counter array, where the counter array counts a number of cycles in the ring oscillator;an analog-to-digital converter (ADC) driver that is electrically coupled to the ring oscillator; andan ADC that is electrically coupled to the ADC driver, where an output of the ADC is electrically coupled to the ring oscillator.2. The apparatus of claim 1 , further comprising a phase/frequency detector (PFD) connected to the ring oscillator that includes a first input for receiving a reference clock signal claim 1 , a second input for receiving a feedback clock signal claim 1 , and an output for providing an enable signal.3. The apparatus of claim 1 , further comprising a plurality of time-to-digital-converter (TDC) buffers connected to the outputs of the ring oscillator.4. The apparatus of claim 3 , further comprising an interpolating resistive network connected to outputs of the plurality of TDC buffers.5. The apparatus of claim 3 , further comprising a multiplexer connected to the outputs of the TDC buffers.6. The apparatus of claim 5 , further comprising a programmable analog-to-digital converter (ADC) driver connected to an output of the multiplexer.7. The apparatus of claim 1 , wherein the ring oscillator includes a plurality of buffers connected in a ring claim 1 , and wherein each of the outputs of the ring oscillator are connected to one of the plurality of buffers claim 1 , respectively.8. The apparatus of claim 1 , further comprising a ...

AUTO FREQUENCY CALIBRATION METHOD

A method of generating an output signal includes determining a sampling period N according to a number of most significant bits (MSBs) of a divider number control signal. The method also includes determining a first logic value of a control signal by a comparing circuit based on the sampling period N, and generating a coarse tuning signal by a code generating circuit based on a phase difference signal and the control signal. When an M-th least significant bit (LSB) of the number of MSBs of the divider number control signal equals a second logic value, the sampling period N is set based on the M-th LSB of the number of MSBs of the divider number control signal. 1. A method of generating an output signal , the method comprising:determining a sampling period N according to a number of most significant bits (MSBs) of a divider number control signal;determining a first logic value of a control signal by a comparing circuit based on the sampling period N; andgenerating a coarse tuning signal by a code generating circuit based on a phase difference signal and the control signal, whereinwhen an M-th least significant bit (LSB) of the number of MSBs of the divider number control signal equals a second logic value, the sampling period N is set based on the M-th LSB of the number of MSBs of the divider number control signal.2. The method of claim 1 , further comprising:generating a fine tuning signal by a digital loop filter based on the phase difference signal.3. The method of claim 2 , further comprising:adjusting an output frequency of the output signal by a voltage controlled oscillator based on the coarse tuning signal and the fine tuning signal.4. The method of claim 1 , further comprising:determining if (M+1) LSB equals the second logic value when the M-th LSB of the number of MSBs of the divider number control signal does not equal the second logic value.5. The method of claim 1 , wherein determining the sampling period N according to the number of MSBs of the divider ...

CIRCUIT, CHIP AND SEMICONDUCTOR DEVICE

A circuit is disclosed. The circuit includes a time-to-digital converter (TDC), and an evaluation circuit coupled to the TDC and a phase-locked loop (PLL) external to the circuit. 1. A circuit , comprising:a time-to-digital converter (TDC); andan evaluation circuit coupled to the TDC and a phase-locked loop (PLL) external to the circuit.2. The circuit of claim 1 , wherein the TDC is configured to receive a first signal having an identification and a first frequency claim 1 , and output a digital signal associated with the identification of the first signal to the evaluation circuit.3. The circuit of claim 2 , wherein the identification comprises a duty cycle.4. The circuit of claim 2 , further comprising: a frequency divider coupled to the TDC to provide a second signal having a second frequency to the TDC.5. The circuit of claim 4 , wherein the digital signal is generated based on the second signal from the frequency divider.6. The circuit of claim 4 , wherein the digital signal is generated by sampling the first signal by means of the second signal.7. The circuit of claim 1 , wherein the TDC comprises:a first buffer having a first input and a first output;a second buffer having a second input coupled to the first output of the first buffer, and a second output;a first sampling circuit having a first input coupled to the first output of the first buffer, a second input, and a first output; anda second sampling circuit having a third input coupled to the second output of the second buffer, a fourth input coupled to the second input of the first sampling circuit, and a second output.8. The circuit of claim 7 , wherein the first input of the first buffer is configured to receive a first signal having an identification and a first frequency.9. The circuit of claim 8 , further comprising a frequency divider claim 8 , wherein the second input of the first sampling circuit is coupled to the frequency divider to receive a second signal having a second frequency.10. The ...

PHASE TRACKER FOR A PHASE LOCKED LOOP

A phase locked loop includes a feedforward path receiving a reference signal having a reference frequency and outputting an output signal having an output frequency that is a function of the reference signal and a feedback signal. The phase locked loop further includes a feedback path having a divider circuit associated therewith that is configured to receive the output signal and generate the feedback signal having a reduced frequency based on a divide value of the divider circuit. The feedback signal is supplied to the feedforward path. The phase locked loop also includes a modulator circuit configured to receive modulation data and provide a divider control signal to the divider circuit to control the divide value thereof, and a phase tracker circuit configured to determine an amount of phase drift from an initial phase value of the output signal due to an interruption in a locked state of the phase locked loop. 1. A phase locked loop , comprising:a phase locked loop circuit configured to output an output signal based on a reference frequency and a current channel word; anda phase tracking circuit configured to determine a phase drift amount of the output signal based on a previous channel word and the current channel word of the phase locked loop circuit.2. The phase locked loop of claim 1 ,wherein the phase tracking circuit comprises an accumulator circuit that accumulates a difference between an input sequence and the previous channel word,wherein the input sequence includes the current channel word and modulation data, andwherein the accumulated difference represents the phase drift amount.3. The phase locked loop circuit of claim 1 , wherein the phase tracking circuit comprises:a first calculation circuit configured to calculate a frequency control word based on the current channel word and modulation data;a second calculation circuit configured to determine a difference between the frequency control word and the previous channel word, wherein the difference ...

CLOCK SCREENING WITH PROGRAMMABLE COUNTER-BASED CLOCK INTERFACE AND TIME-TO-DIGITAL CONVERTER WITH HIGH RESOLUTION AND WIDE RANGE OPERATION

A sub-ranging time-to-digital converter (TDC) is disclosed that includes two ring oscillators for determining a time difference between two clock edges. 1. A time-to-digital converter for measuring a time between a first clock edge and a second clock edge , comprising:a slow oscillator configured to oscillate a slow oscillator output signal responsive to the first clock edge;a coarse counter configured to count a coarse count responsive to cycles of the slow oscillator output signal;a fast oscillator configured to oscillate a fast oscillator output signal responsive to the second clock edge;a fine counter configured to count a fine count responsive to cycles of the fast oscillator output signal, wherein a frequency for the fast oscillator output signal is greater than a frequency for the slow oscillator output signal;a first current source coupled to an input of the slow oscillator and configured to selectively sink a first current; anda second current source coupled to an input of the fast oscillator and configured to selectively sink a second current.2. The time-to-digital converter of claim 1 , further comprising:a phase detector configured to latch the coarse counter responsive to a detection that a phase for the slow oscillator output signal is leading a phase for the fast oscillator output signal.3. The time-to-digital converter of claim 2 , wherein the phase detector is further configured to latch the fine counter responsive to the detection.4. The time-to-digital converter of claim 1 , wherein the fast oscillator is a first ring oscillator claim 1 , and wherein the slow oscillator is a second ring oscillator.5. The time-to-digital converter of claim 4 , wherein the first ring oscillator comprises a first set of at least three inverters claim 4 , and wherein the second ring oscillator comprises a second set of at least three inverters.6. The time-to-digital converter of claim 1 , wherein the first current source is further configured to sink the first current ...

HIGH-RESOLUTION AND AGILE FREQUENCY MEASUREMENT

An apparatus for generating a frequency estimate of an output signal includes a reference signal generator configured to generate a reference clock signal. The apparatus includes frequency estimation circuitry configured to generate a cycle count based frequency estimation of the output signal based on the reference clock signal and a clock cycle count of the output signal. The frequency estimation circuitry further generates a fractional frequency estimation of the output signal based on the reference clock signal and a plurality of time-to-digital conversion phase samples of the output signal. The frequency estimation circuitry further generates the frequency estimate of the output signal using the cycle count based frequency estimation within a range and a frequency error determined from the fractional frequency estimation. The plurality of time-to-digital conversion phase samples and the cycle count based frequency estimation use a same number of reference clock cycles of the reference clock signal. 1. An apparatus to generate a frequency estimate of an output signal , the apparatus comprising:a reference signal generator configured to generate a reference clock signal; and{'claim-text': ['generate a cycle count based frequency estimation of the output signal based on the reference clock signal and a clock cycle count of the output signal;', 'generate a fractional frequency estimation of the output signal based on the reference clock signal and a plurality of time-to-digital conversion phase samples of the output signal; and', 'generate the frequency estimate of the output signal using the cycle count based frequency estimation within a range and a frequency error determined from the fractional frequency estimation,', 'wherein the plurality of time-to-digital conversion phase samples and the cycle count based frequency estimation use a same number of reference clock cycles of the reference clock signal.'], '#text': 'frequency estimation circuitry configured to ...

PHYSICAL QUANTITY MEASUREMENT APPARATUS, ELECTRONIC APPARATUS, AND VEHICLE

A physical quantity measurement apparatus includes a first resonator, a second oscillator, and an integrated circuit device. The integrated circuit device includes a first oscillation circuit that causes the first resonator to oscillate, and thus generate a first clock signal having a first clock frequency, a second oscillation circuit that causes the second oscillator to oscillate, and thus generate a second clock signal having a second clock frequency which is different from the first clock frequency, and a measurement unit that is provided with a time-to-digital conversion circuit which converts time into a digital value by using the first clock signal and the second clock signal. 1. A physical quantity measurement apparatus comprising:a first resonator;a second oscillator; andan integrated circuit device, a first oscillation circuit configured to cause the first resonator to oscillate and generate a first clock signal having a first clock frequency,', 'a second oscillation circuit configured to cause the second oscillator to oscillate and generate a second clock signal having a second clock frequency, the second clock frequency being different from the first clock frequency, and', 'a measurement unit having a time-to-digital conversion circuit configured to convert time into a digital value based on the first clock signal and the second clock signal., 'wherein the integrated circuit device includes2. The physical quantity measurement apparatus according to claim 1 , a first terminal that connects one end of the first resonator to the first oscillation circuit;', 'a second terminal that connects the other end of the first resonator to the first oscillation circuit;', 'a third terminal that connects one end of the second oscillator to the second oscillation circuit; and', 'a fourth terminal that connects the other end of the second oscillator to the second oscillation circuit., 'wherein the integrated circuit device includes3. The physical quantity measurement ...

TIME-TO-DIGITAL CONVERTER WITH PHASE-SCALED COURSE-FINE RESOLUTION

A time-to-digital converter (TDC) measures a time interval ΔTbetween a leading signal and a triggering signal. A phase regulator incorporates a looped delay line to create pre-defined sub-intervals Tdetermined by the length of the delay line. The phase regulator has an input receiving the leading signal such that the leading signal loops around the delay line. A counter for counting the number of times m the leading signal loops around the delay line before said triggering signal arrives to obtain a coarse measurement of the time interval defined in terms of the sub-intervals T. A Vernier core for measures a residual time interval Twhere T=ΔT−mTto obtain a value for the time interval ΔT. The TDC uses simpler encoding logic with reduced power consumption and phase noise performance better than 5 dB. 1. A time-to-digital converter for measuring a time interval ΔTbetween a leading signal and a triggering signal , comprising:{'sub': 'NOR', 'a phase regulator incorporating a looped delay line to create pre-defined sub-intervals Tdetermined by the length of said delay line, said phase regulator having an input receiving said leading signal whereby said leading signal loops around said delay line;'}{'sub': 'NOR', 'a counter for counting the number of times m said leading signal loops around said delay line before said triggering signal arrives to obtain a coarse measurement of said time interval defined in terms of said sub-intervals T; and'}{'sub': R', 'R', 'Tot', 'NOR', 'Tot, 'a Vernier core for measuring a residual time interval Twhere T=ΔT−mTto obtain a value for the time interval ΔT.'}2. A time-to-digital converter as claimed in claim 1 , further comprising an evaluator responsive to outputs from said phase regulator claim 1 , said counter claim 1 , and said Vernier core to output said value for the time interval ΔT.3. A time-to-digital converter as claimed in claim 1 , comprising a first chain of delay elements claim 1 , a portion of said first chain of delay ...

CIRCUIT DEVICE, PHYSICAL QUANTITY MEASUREMENT DEVICE, ELECTRONIC APPARATUS, AND VEHICLE

A circuit device includes a time-to-digital conversion circuit, to which a first clock signal generated using a first resonator, and having a first clock frequency, and a second clock signal generated using a second resonator, and having a second clock frequency different from the first clock frequency are input, and which converts time into a digital value using the first and second clock signals, and a PLL circuit adapted to perform phase synchronization between the first and second clock signals. 1. A circuit device comprising:a time-to-digital conversion circuit, to which a first clock signal generated using a first resonator, and having a first clock frequency, and a second clock signal generated using a second resonator, and having a second clock frequency different from the first clock frequency are input, and which converts time into a digital value using the first clock signal and the second clock signal; anda PLL circuit adapted to perform phase synchronization between the first clock signal and the second clock signal.2. The circuit device according to claim 1 , whereinthe time-to-digital conversion circuit converts the time into the digital value with resolution corresponding to a frequency difference between the first clock frequency and the second clock frequency.3. The circuit device according to claim 2 , wherein {'br': None, 'i': t=|', 'f', 'f', 'f', 'f', 'f', 'f, 'Δ1/1−1/2|=|1−2≡/(1×2).'}, 'defining the first clock frequency as f1 and the second clock frequency as f2, the time-to-digital conversion circuit converts the time into the digital value with the resolution Δt expressed as follows4. The circuit device according to claim 1 , whereindefining the first clock frequency as f1 and the second clock frequency as f2, the PLL circuit performs the phase synchronization between the first clock signal and the second clock signal so as to fulfill N/f1=M/f2 (N, M are integers different from each other and each no smaller than 2).5. The circuit device ...

ALL-DIGITAL PHASE LOCKED LOOP USING SWITCHED CAPACITOR VOLTAGE DOUBLER

An all-digital phase locked loop (ADPLL) receives an analog input supply voltage which is utilized to operate analog circuitry within the ADPLL. The ADPLL of the present disclosure scales this analog input supply voltage to provide a digital input supply voltage which is utilized to operate digital circuitry within the ADPLL. The analog circuitry includes a time-to-digital converter (TDC) to measure phase errors within the ADPLL. The TDC can be characterized as having a resolution of the TDC which is dependent, at least in part, upon the digital input supply voltage. In some situations, process, voltage, and/or temperature (PVT) variations within the ADPLL can cause the digital input supply voltage to fluctuate, which in turn, can cause fluctuations in the resolution of the TDC. These fluctuations in the resolution of the TDC can cause in-band phase noise of the ADPLL to vary across the PVT variations. The digital circuitry regulates the digital input supply voltage to stabilize the resolution of the TDC across the PVT variations. This stabilization of the resolution of the TDC can cause the ADPLL to maintain a fixed in-band phase noise across the PVT variations. 1. A system for generating an input voltage within a phase locked loop (PLL) having a time-to-digital converter (TDC) , the system comprising: generate a switching clocking signal when a resolution of the TDC is less than or equal to a target resolution for the TDC, and', 'skip one or more clocking cycles of the switching clocking signal when the resolution of the TDC is greater than the target resolution for the TDC; and, 'an oscillator configured toone or more switchable capacitors configured to be charged or discharged in response to the switching clocking signal to generate the input voltage.2. The system of claim 1 , wherein the oscillator is further configured to receive an oscillator circuitry control signal at a first logical level when the resolution of the TDC is less than the target resolution ...

Time-to-digital system and associated frequency synthesizer

A time-to-digital system and associated frequency synthesizer are provided. The time-to-digital system receives a reference clock and a variable clock. The time-to-digital system includes a supplement circuit and a time-to-digital converter (TDC). The supplement circuit generates a delayed reference clock signal and at least one pulse of a variable clock ahead of a transition of the delayed reference clock signal. The delayed reference clock signal is generated according to a delay control signal and the reference clock signal. The delay control signal is determined in response to transitions of the variable clock, and frequency of the variable clock is significantly higher than frequency of the reference clock signal. Being coupled to the supplement circuit, the TDC receives the delayed reference clock signal and the at least one pulse of the variable clock and accordingly produces a TDC signal.

INTEGRATED CIRCUIT DEVICE, ELECTRONIC APPARATUS, AND VEHICLE

An integrated circuit device includes: a first oscillation circuit that oscillates a first resonator to generate a first clock signal with a first clock frequency; a second oscillation circuit that oscillates a second oscillation element to generate a second clock signal with a second clock frequency that is different from the first clock frequency; and a time-to-digital conversion circuit that converts a time into a digital value using the first and second clock signals. 1. An integrated circuit device comprising:a first oscillation circuit configured to oscillate a first resonator to generate a first clock signal with a first clock frequency;a second oscillation circuit configured to oscillate a second oscillation element to generate a second clock signal with a second clock frequency that is different from the first clock frequency; anda time-to-digital conversion circuit configured to convert a time into a digital value using the first and second clock signals.2. The integrated circuit device according to claim 1 , further comprising:a controller configured to control at least one of the first and second oscillation circuits.3. The integrated circuit device according to claim 2 ,wherein the controller is configured to control at least one of an oscillation frequency and a phase of an oscillation signal of at least the one oscillation circuit.4. The integrated circuit device according to claim 2 ,wherein the controller is configured to control at least the one oscillation circuit so that the first and second clock signals have a given frequency relation or a given phase relation.5. The integrated circuit device according to claim 4 ,{'b': '1', 'wherein the first clock frequency is f,'}{'b': '2', 'the second clock frequency is f, and'}{'b': 1', '2, 'the controller is configured to control at least the one oscillation circuit so that N/f=M/f,'}wherein N and M are mutually different integers equal to or greater than 2.6. The integrated circuit device according to ...

CIRCUIT DEVICE, PHYSICAL QUANTITY MEASUREMENT APPARATUS, ELECTRONIC APPARATUS, AND VEHICLE

A circuit device includes: a time-to-digital conversion circuit to which a first clock signal with a first clock frequency and a second clock signal with a second clock frequency different from the first clock frequency are input and that converts a time difference in transition timings of first and second signals into a digital value; and a synchronization circuit that synchronizes phases of the first and second clock signals. The time-to-digital conversion circuit calculates the digital value corresponding to the time difference by transitioning a signal level of the first signal based on the first clock signal after a phase synchronization timing of the first and second clock signals and compares the phase of the second clock signal to a phase of the second signal having a signal level is transitioned to correspond to the first signal. 1. A circuit device comprising:a time-to-digital conversion circuit configured to receive a first clock signal and a second clock signal, and to convert a time difference in transition timings of first and second signals into a digital value, the first clock signal having a first clock frequency, the second clock signal having a second clock frequency, the second clock frequency being a different frequency than the first clock frequency; anda synchronization circuit configured to synchronize phases of the first and second clock signals input to the time-to-digital conversion circuit,wherein the time-to-digital conversion circuit is configured to calculate the digital value corresponding to the time difference by transitioning a signal level of the first signal based on the first clock signal after a phase synchronization timing of the first and second clock signals and to compare the phase of the second clock signal to a phase of the second signal having a signal level transitioned to correspond to the first signal.2. The circuit device according to claim 1 ,wherein the time-to-digital conversion circuit is configured to transition ...

ADAPTIVE ON-CHIP DIGITAL POWER ESTIMATOR

Systems, apparatuses, and methods for implementing a dynamic power estimation (DPE) unit that adapts weights in real-time are described. A system includes a processor, a DPE unit, and a power management unit (PMU). The DPE unit generates a power consumption estimate for the processor by multiplying a plurality of weights by a plurality of counter values, with each weight multiplied by a corresponding counter. The DPE unit calculates the sum of the products of the plurality of weights and plurality of counters. The accumulated sum is used as an estimate of the processor's power consumption. On a periodic basis, the estimate is compared to a current sense value to measure the error. If the error is greater than a threshold, then an on-chip learning algorithm dynamically adjust the weights. The PMU uses the power consumption estimates to keep the processor within a thermal envelope. 1. A system comprising:a processing unit; apply a first set of weights to a plurality of counter values to generate a first prediction of power consumption of the processing unit;', 'determine an error of the first prediction of power consumption of the processing unit;', 'apply, based on the error, adjustments to the first set of weights to create a second set of weights; and, 'a dynamic power estimator circuit configured toapply the second set of weights to the plurality of counter values to generate a second prediction of power consumption of the processing unit; anda power management unit configured to adjust a power performance state of the processing unit based on the second prediction of power consumption.2. The system as recited in claim 1 , wherein the plurality of counter values is obtained from a plurality of event counters tracking events associated with operating conditions of the processing unit.3. The system as recited in claim 1 , wherein the dynamic power estimator circuit is configured to determine an error of the first prediction of power consumption of the processing ...

Electric Quantity Measuring Device Comprising An Analog-Digital Converter

It is described an electronic device () for measuring an electric quantity, comprising: an analog-digital conversion module () configured to digitally convert time portions of an analog signal (S(t)) to be measured alternated with time portions of a reference analog signal (S(t)), for supplying respective first (D) and second pluralities (D) of digital values and a digital processing module () configured to: calculate a first mean amplitude (A) of the first pluralities of digital values, and a second mean amplitude (A) of the second pluralities of digital values; the first and second mean amplitudes being proportional to a mean gain value of the analog-digital conversion module (); supply a ratio value (V) of the first mean amplitude to the second mean amplitude, representative of a measured amplitude of the analog signal (S(t)) to be measured. 1. Electric quantities measure electronic device , comprising:{'sub': M', 'R', 'SM', 'R, 'an analog-digital conversion module configured to digitally convert time portions of an analog signal (S(t)) to be measured alternated with time portions of a reference analog signal (S(t)), for supplying respective first (D) and second pluralities (D) of digital values; and'} [{'b': 1', '2, 'calculate a first mean amplitude (A) of the first plurality of digital values and a second mean amplitude (A) of the second plurality of digital values; the first and second mean amplitudes being proportional to a mean gain value of the analog-digital conversion module; and'}, {'sub': RT', 'M, 'supply a ratio value (V) of the first mean amplitude to the second mean amplitude, representative of a measured amplitude of the analog signal (S(t)) to be measured.'}], 'a digital processing module configured to2. Electronic device according to claim 1 , wherein the analog-digital conversion module is configured to digitally convert the time portions of the analog signal (S(t)) to be measured and the time portions of the reference analog signal (S(t)) ...

CIRCUIT, A TIME-TO-DIGITAL CONVERTER, AN INTEGRATED CIRCUIT, A TRANSMITTER, A RECEIVER AND A TRANSCEIVER

A circuit according to an example includes a controllable oscillator configured to generate an output signal based on a control signal, an input signal processing circuit configured to receive a reference signal and configured to generate a sequence of digital values indicative of a phase relation between the reference signal and the output signal or a signal derived from the output signal, and a digital data processing circuit configured to generate a sequence of processed values at a lower frequency than a frequency of the sequence of the digital values, each processed value being based on a plurality of the digital values of the sequence of digital values, wherein the control signal is based on the sequence of processed values. 1. A circuit comprising:a controllable oscillator configured to generate an output signal based on a control signal;an input signal processing circuit configured to receive a reference signal and generate a sequence of digital values indicating a phase relation between the reference signal and the output signal or a signal derived from the output signal;a digital data processing circuit configured to generate a sequence of processed values at a lower frequency than a frequency of the sequence of the digital values, wherein each processed value is based on a plurality of the digital values of the sequence of digital values,wherein the control signal is based on the sequence of processed values; anda noise cancellation circuit coupled between the input signal processing circuit and the controllable oscillator and configured to compensate a phase shift caused by a switching of a frequency divider coupled between the controllable oscillator and the input processing circuit,wherein the noise cancellation circuit outputs a value indicative of the phase shift.2. The circuit according to claim 1 , wherein the digital data processing circuit is configured to generate the sequence of processed values by digitally processing the plurality of the ...

Delay Circuit, Time To Digital Converter, And A/D Conversion Circuit

A delay circuit includes a state transition section configured to start state transition based on a trigger signal and output state information indicating the internal state and a transition-state acquisition section configured to latch and hold the state information. The state transition section includes a tapped delay line in which a plurality of delay elements are coupled, a logical circuit configured to generate a third signal based on a first signal based on the trigger signal and a second signal, which is an output signal of the delay element, and a synchronous transition section configured to count an edge of the third signal. The state information is having an output signal of the synchronous transition section and an output signal of the tapped delay line. A humming distance of the state information before and after the state transition is 1. A time from when the internal state transitions from a first internal state to a second internal state until when the internal state transitions to the first internal state again is longer than an interval of a time for updating the state information held by the transition-state acquisition section. 1. A delay circuit comprising:a state transition section configured to start state transition, in which an internal state transitions, based on a trigger signal and output state information indicating the internal state; anda transition-state acquisition section configured to latch and hold the state information based on a latch signal, wherein a tapped delay line in which a plurality of delay elements are coupled;', 'a logical circuit configured to generate a third signal based on a first signal and a second signal; and', 'a synchronous transition section configured to count an edge of the third signal,, 'the state transition section includesthe first signal is a signal based on the trigger signal,the second signal is any one of signals output from the plurality of delay elements,the state information is having a signal ...

Bang-Bang Time to Digital Converter Systems and Methods

A time to digital converter includes a mutual exclusion element and a sampling component. The mutual exclusion element is configured to receive a first clock and a second clock and to generate a first pulse and a second pulse. The mutual exclusion element is configured to drive the first pulse to a first logic state and the second pulse to a second logic state upon the first clock being earlier than the second clock and drive the second pulse to the first logic state and the first pulse to the second logic state upon the second clock being earlier than the first clock. The sampling component is configured to receive the first pulse and the second pulse and to generate a decision signal according to the first pulse and the second pulse. 1. A time to digital converter comprising:a mutual exclusion element configured to receive a first clock and a second clock and to generate a first pulse and a second pulse, wherein the mutual exclusion element is configured to drive the first pulse to a first logic state and the second pulse to a second logic state upon the first clock being earlier than the second clock and drive the second pulse to the first logic state and the first pulse to the second logic state upon the second clock being earlier than the first clock; anda sampling component configured to receive the first pulse and the second pulse and to generate a decision signal according to the first pulse and the second pulse,wherein the decision signal includes a first early indictor and a second early indicator, wherein the first early indicator is set to the first logic state upon the first clock being earlier than the second clock and the second early indicator is set to the first logic state upon the second clock being earlier than the first clock.2. The converter of claim 1 , further comprising a component configured to adjust timing of at least one of the first clock and the second clock according to the decision signal.3. The converter of claim 1 , further ...

CIRCUIT AND METHOD TO ENHANCE EFFICIENCY OF SEMICONDUCTOR DEVICE

A circuit includes a period calculator and a pulse width calculator. The period calculator is configured for receiving a first predetermined digital code and a second predetermined digital code, and for calculating a first calculated period value according to the first predetermined digital code, and calculating a second calculated period value according to the second predetermined digital code. The first predetermined digital code has a first predetermined period value, and the second predetermined digital code has a second predetermined period value. The pulse width calculator is configured for receiving a predetermined pulse width, and calculating a first pulse width code corresponding to the predetermined pulse width according to the first predetermined period value, the second predetermined period value, the first calculated period value, the second calculated period value and the predetermined pulse width. 1. A circuit , comprising:a period calculator, for receiving a first predetermined digital code and a second predetermined digital code, and for calculating a first calculated period value according to the first predetermined digital code, and calculating a second calculated period value according to the second predetermined digital code, the first predetermined digital code having a first predetermined period value, the second predetermined digital code having a second predetermined period value; anda pulse width calculator, for receiving a predetermined pulse width, and calculating a first pulse width code corresponding to the predetermined pulse width according to a ratio between the first predetermined period value and the second predetermined period value, the first calculated period value, the second calculated period value and the predetermined pulse width.5. The circuit of claim 4 , further comprising a first operator for comparing the first pulse width code and a check value.6. The circuit of claim 5 , further comprising a second operator for ...

DUTY CYCLE ERROR DETECTION DEVICE AND DUTY CYCLE CORRECTION DEVICE HAVING THE SAME

In a duty cycle error detection device, a first digital code generator is configured to generate high and low codes corresponding to a lengths of high level low level periods, respectively, of a clock signal, generate a sign signal representing the longer period between the high level period and the low level period, and output one of the high and low digital codes corresponding to the shorter period as a first digital code. A clock delay circuit is configured to generate a delay clock signal by delaying the clock signal for a time corresponding to the first digital code, and a second digital code generator is configured to generate a duty error digital code corresponding to a length from a start of the longer period of the delay clock signal to an end of the longer period of the clock signal based on the sign signal. 1. A duty cycle error detection device , comprising:a first digital code generator configured to generate a high digital code and a low digital code, which correspond to a length of a high level period of a clock signal and a length of a low level period of the clock signal, respectively, to determine a longer period and a shorter period between the high level period of the clock signal and the low level period of the clock signal based on the high digital code and the low digital code, to generate a sign signal representing the longer period of the clock signal, and to output one of the high digital code and the low digital code, which corresponds to the shorter period of the clock signal, as a first digital code;a clock delay circuit configured to generate a delay clock signal by delaying the clock signal for a time corresponding to the first digital code; anda second digital code generator configured to generate a duty error digital code, which corresponds to a length from a start of the longer period of the delay clock signal to an end of the longer period of the clock signal, based on a logic level of the sign signal.3. The duty cycle error ...

APPARATUS AND METHODS FOR ROTARY TRAVELING WAVE OSCILLATORS

Apparatus and methods for rotary traveling wave oscillators (RTWOs) are provided herein. In certain configurations, an RTWO includes a differential transmission line connected in a ring and a plurality of segments distributed around the ring. The segments include metal stubs extending from the RTWO's differential transmission line. The metal stubs aid in providing access to additional layout resources for tuning capacitors and other circuitry of the RTWO's segments, while permitting the length of RTWO's ring to be relative short. Thus, the metal stubs do not inhibit the RTWO from operating with relatively high oscillation frequency, while providing connectivity to tuning capacitors that tune the RTWO's oscillation frequency over a wide tuning range and/or provide fine frequency step size. 1. A rotary traveling wave oscillator (RTWO) comprising:an RTWO ring comprising a first transmission line conductor and a second transmission line conductor and configured to carry a traveling wave; and a pair of metal stubs comprising a first metal stub electrically connected to the first transmission line conductor and a second metal stub electrically connected to the second transmission line conductor; and', 'one or more capacitor tuning banks electrically connected to the pair of metal stubs and operable to control an oscillation frequency of the RTWO., 'a plurality of segments positioned around the RTWO ring, wherein a first segment of the plurality of segments comprises2. The RTWO of claim 1 , wherein the first segment further comprises a time-to-digital converter (TDC) latch electrically connected between the first metal stub and the second metal stub and operable to detect passage of the traveling wave.3. The RTWO of claim 1 , wherein the first metal stub and the second metal stub have substantially equal length.4. The RTWO of claim 1 , wherein the first metal stub and the second metal stub each have a length of at least a factor of 0.05 of a wavelength of the traveling ...

MODULATORS

This application relates to time-encoding modulators (TEMs). A TEM receives an input signal (S) and outputs a time-encoded output signal (S). A filter arrangement receives the input signal and also a feedback signal (S) from the TEM output, and generates a filtered signal (S) based, at least in part, on the feedback signal. A comparator receives the filtered signal and outputs a time-encoded signal (S) based at least in part on the filtered signal. The time encoding modulator is operable in a first mode with the filter arrangement configured as an active filter and in a second mode with the filter arrangement configured as a passive filter. The filter arrangement may include an op-amp, capacitance and switch network. In the first mode the op-amp is enabled, and coupled with the capacitance to provide the active filter. In the second mode the op-amp is disabled and the capacitance coupled to a signal path for the feedback signal to provide a passive filter. 1. A time encoding modulator apparatus comprising:a photodetector and a time-encoding modulator having an input for receiving an input signal and an output for outputting an output signal;a filter arrangement configured to receive the input signal and a feedback signal from the output and generate a filtered signal based at least in part on the feedback signal; anda comparator configured to receive the filtered signal and output a time-encoded signal based at least in part on the filtered signal,wherein the time encoding modulator is operable in a first mode with the filter arrangement configured as an active filter and in a second mode with the filter arrangement configured as a passive filter; andwherein the output signal is based on the time-encoded signal.2. The time encoding modulator apparatus as claimed in wherein the filter arrangement comprises a first operational amplifier which is enabled in the first mode and disabled in the second mode.3. The time encoding modulator apparatus as claimed in wherein the ...

Activity detection

This application relates an activity detector ( 100 ) for detecting signal activity in an input audio signal (S IN ), such as may be used for always-on speech detection. The activity detector has a first time-encoding modulator (TEM) 101 including a first hysteretic comparator ( 201 ) for generating a PWM (pulse-width modulation) signal based on the input audio signal. A second TEM ( 103 ) having a second hysteretic comparator ( 401 ) is arranged to receive a reference voltage (V MID ) and generate a clock signal (S CLK ). A time-decoding converter ( 102 ) receives the clock signal and generates count values of a number of cycles of the clock signal in periods defined by the PWM signal. An activity monitor ( 104 ) is responsive to a count signal (S CT ) from the TDC 102 to determine whether the input audio signal comprises signal activity above a defined threshold.

Device And Method For Determining Timing Of A Measured Signal

The invention is a device for determining timing of a measured signal, the device comprising a plurality of flip-flop units (), each having a clock signal input for receiving the measured signal () and a data input for receiving a secondary signal, and an evaluation module being adapted for evaluating outputs of the plurality flip-flop units (), and the flip-flop units () are arranged on an FPGA architecture. The device according to the invention comprises an allocating module for allocating at least one path consisting of flip-flop units (), wherein the measured signal () and the secondary signal are led to the flip-flop units () of the at least one path, and a calibration module being adapted for determining a time difference parameter of each flip-flop unit (), the time difference parameter specifying for each flip-flop unit () a time difference between a period of time in which the measured signal () reaches the given flip-flop unit () from an input point of the measured signal and a period time in which the secondary signal reaches the given flip-flop unit () from an input point of the secondary signal, wherein the evaluation module is adapted for determining the timing of the measured signal from the output of the flip-flop units () located along the at least one path, on the basis of the time difference parameters. The invention is furthermore a method for determining timing of a measured signal. 1. A device for determining timing of a measured signal , the device comprising{'b': 10', '20', '36', '46', '48', '80', '82', '96', '121', '138, 'a plurality of flip-flop units (), each having a clock signal input for receiving the measured signal (, , , , , , , , ) and a data input for receiving a secondary signal, and'}{'b': '10', 'an evaluation module being adapted for evaluating outputs of the flip-flop units (),'}characterised in that{'b': 10', '134, 'the flip-flop units () are arranged on an FPGA architecture (),'} [{'b': 10', '20', '36', '46', '48', '80', '82 ...

Fractional-N Phase-Locked Loop

A phase-locked loop (PLL) includes a time to voltage converter to convert a phase error between a reference signal and a feedback signal of the PLL to one or more voltage signals. An oscillator-based analog to digital converter (ADC) receives the one or more voltage signals and controls one or more oscillators according to the voltages. The oscillator-based ADC determines a digital value corresponding to the phase error based on the frequencies of the one or more oscillators. 1. A phase-locked loop (PLL) comprising:a capacitor based digital to analog converter (DAC) coupled to receive a digital indication of quantization noise and to supply a quantization noise correction voltage to adjust a phase error voltage to create a combined voltage signal with reduced quantization noise, wherein the phase error voltage is indicative of a phase error corresponding to a time difference between a reference signal and a feedback signal based on an output of a first oscillator, the first oscillator controlled at least in part based on a value of the combined voltage signal; andan oscillator-based analog to digital converter (ADC) coupled the capacitor based DAC to convert the combined voltage signal to a digital value, the oscillator-based ADC having a second oscillator having a frequency responsive to the combined voltage signal.2. The PLL as recited in wherein the second oscillator is a ring oscillator and the oscillator-based ADC comprises:first tuning transistors coupling stages of the ring oscillator to a first supply node and second tuning transistors coupling the stages of the ring oscillator to a second supply node.3. The PLL as recited in further comprising:a phase detector circuit to supply a charge control signal corresponding to the phase error; anda first capacitor circuit coupled to a first node to be charged by a current based on the charge control signal and supply the phase error voltage.4. The PLL as recited in further comprising:a discharge switch coupled to ...

Spur canceller with multiplier-less correlator

A spur cancellation circuit uses low cost multipliers in a correlation circuit. Each low cost multiplier multiplies a value of a sense node by a representation of a sinusoid and supplies a multiplication result. A compare circuit compares the sinusoid to one or more threshold values and supplies a compare indication. A multiplexer selects between two or more inputs including a positive value of the sense node and a negative value of the sense node, based on the compare result. A single threshold at zero converts the sinusoid to a square wave and the multiplexer supplies either the positive value or the negative value, which is equivalent to multiplying the value at the sense node by 1 or −1 depending on the sign of the sinusoid. Two thresholds may be used to represent the sinusoid with three values, the positive value, the negative value, or zero.

SPUR CANCELLATION WITH ADAPTIVE FREQUENCY TRACKING

A spur cancellation circuit receives a target spur frequency indicative of a frequency of a spur to be canceled and supplies a spur cancellation signal based on the frequency. A frequency tracking circuit tracks a change in the frequency of the spur to be canceled based on a change in phase of the spur cancellation signal and generates an updated target spur frequency based on the change in the frequency of the spur. 1. A method for tracking spur frequency comprising:generating a spur cancellation signal with a first phase using a target spur frequency;determining the first phase of the spur cancellation signal with the first phase from a first sample of parameters used in generating the spur cancellation signal with the first phase;generating the spur cancellation signal with a second phase;determining the second phase from a second sample of parameters used in determining the spur cancellation signal with the second phase;determining a phase difference between the first phase and the second phase;updating a target spur frequency to an updated target spur frequency based on the phase difference; andgenerating an updated spur cancellation signal using the updated target spur frequency.2. The method as recited in further comprising:scaling the phase difference and generating a scaled phase difference.3. The method as recited in claim 2 , further comprising:adding the scaled phase difference to the target spur frequency to generate the updated target spur frequency.4. The method as recited in claim 1 , wherein the first sample of parameters used in determining the spur cancellation signal with the first phase includes a first sine weight and a first cosine weight and wherein the second sample of parameters used in determining the spur cancellation signal with the second phase includes a second sine weight and a second cosine weight.5. The method as recited in claim 1 , further comprising:generating a first sine weight applied to a sine signal and a first cosine weight ...

Low-power, low-latency time-to-digital-converter-based serial link

A receiver is provided that includes a time-to-digital converter for converting a phase difference between a clock signal and a received data signal into a phase-difference digital code. The receiver also includes a logic circuit that controls a programmable delay line to delay the clock signal into a delayed clock signal by a delay that is responsive to a difference between the phase-difference code and a unit interval for the clock signal. The delayed clock signal clocks a flip-flop to register the received data signal.

Multiple Timing Measurements for Positron Emission Tomography

Timing is determined in positron emission tomography (PET). Two or more different types of timing detection are used for each event. The difference in time from the different types of timing detection may indicate whether or not an error has occurred. An average difference or other typical offset difference may be used to correct the error. During pile up, the difference information may be used to create a missing time, such as using an average difference between second derivative and constant fraction discrimination as an offset to determine constant fraction timing from second derivative timing.

TIME TO DIGITAL CONVERTER (TDC) WITH SYNCHRONOUS OUTPUT AND RELATED METHODS

A time to digital converter (TDC) may include a sampling stage configured to sample an input signal based upon a plurality of timing signals having different respective phases, and provide a respective output for each of the different timing signals. A first synchronization stage may be configured to receive the outputs from the sampling stage, synchronize a first subset of the outputs to a first one of the plurality of timing signals, and synchronize a second subset of the outputs to a second one of the plurality of timing signals. A second synchronization stage may be configured to receive the synchronized outputs from the first synchronization stage, and synchronize all of the synchronized outputs from the first synchronization stage to the first one of the plurality of timing signals. 1. A time to digital converter (TDC) comprising:a sampling stage configured to sample an input signal based upon a plurality of timing signals having different respective phases, and provide a respective output for each of the different timing signals;a first synchronization stage configured to receive the outputs from said sampling stage, synchronize a first subset of the outputs to a first one of the plurality of timing signals, and synchronize a second subset of the outputs to a second one of the plurality of timing signals; anda second synchronization stage configured to receive the synchronized outputs from said first synchronization stage, and synchronize all of the synchronized outputs from said first synchronization stage to the first one of the plurality of timing signals.2. The TDC of further comprising a re-sampling stage coupled between said sampling stage and said first synchronization stage and configured to re-sample the outputs of said sampling stage based upon the plurality of timing signals claim 1 , and provide the re-sampled outputs to said first synchronization stage.3. The TDC of further comprising a memory coupled to said second re-synchronizing stage and ...

TIME-TO-DIGITAL CONVERTER AND CONVERSION METHOD

A time-to-digital converter arrangement has a ring oscillator with a plurality of inverting elements and a first and a second counter coupled to the ring oscillator. The first counter is configured to increment a first counter value if a positive edge transition is present at one of the inverting elements. The second counter is configured to increment a second counter value if a negative edge transition is present at the one of the inverting elements. A storage element stores the first and the second counter value and logical states of the plurality of inverting elements. A decoder coupled to the storage element selects one of the first and the second counter value as a valid value based on an evaluation of the stored logical states, and outputs a total counter value based on the valid value and the stored logical states. 1. A time-to-digital converter arrangement , comprisinga ring oscillator with a plurality of inverting elements, each of the inverting elements providing a logical state;a first counter coupled to the ring oscillator and being configured to increment a first counter value if a positive edge transition is present at one of the inverting elements;a second counter coupled to the ring oscillator and being configured to increment a second counter value if a negative edge transition is present at the one of the inverting elements;a storage element configured to store the first counter value the second counter value and the logical states of the plurality of inverting elements; anda decoder coupled to the storage element and configured to select one of the first and the second counter value as a valid value based on an evaluation of the stored logical states, and to output a total counter value based on the valid value and the stored logical states.2. The time-to-digital converter arrangement according to claim 1 , wherein the decoder is configured to select the valid value based on an evaluation of a combination of the stored logical states.3. The time- ...

TIME TO DIGITAL CONVERTER WITH INCREASED RANGE AND SENSITIVITY

Systems and methods are described for determining a phase measurement difference between a received modulated signal and a local clock signal. An adjusted local clock phase measurement may be determined by subtracting, from the phase measurement difference, a phase correction that is based on the frequency difference between the modulator signal's carrier frequency and the local clock's frequency. A phase modulation value may be generated by scaling the adjusted local clock phase measurement. The scaling may be based on a ratio of the modulated signal's carrier frequency and the local clock's frequency. The phase correction may be based on (i) a count of periods of the modulated signal occurring between each corrected phase measurement and (ii) a difference between the carrier frequency and the local clock frequency. 1. A method comprising:receiving, at a receive phase-to-digital conversion (PDC) circuit, a modulated signal having a carrier frequency;obtaining a phase measurement between the modulated signal and a local clock signal;generating a carrier-based phase correction value by accumulating a phase-correction increment;generating a corrected phase measurement value based on a difference between the phase measurement and the carrier-based phase correction value; andgenerating a carrier phase measurement by scaling the corrected phase measurement value.2. The method of claim 1 , wherein generating the phase-correction increment is based on (i) a count of periods of the modulated signal occurring between each generation of a corrected phase measurement claim 1 , and (ii) a difference between the carrier frequency and a frequency of the local clock signal.3. The method of claim 2 , wherein generating the carrier-based phase correction value is inhibited if a rising edge of the modulated signal does not occur within a timing window.4. The method of claim 1 , wherein obtaining the phase measurement comprises:determining a coarse measurement by determining a phase ...

POWER AND AREA EFFICIENT DIGITAL-TO-TIME CONVERTER WITH IMPROVED STABILITY

A digital-to-time converter (DTC) converts a digital code into a time delay using a capacitor digital-to-analog converter (CDAC) that functions as a charging capacitor. The DTC includes a switched capacitor voltage-to-current converter for the formation of a charging current (or a discharging current) for charging (or for discharging) the charging capacitor responsive to a triggering clock edge that begins the time delay. A comparator compares a voltage on the charging capacitor to a threshold voltage to determine an end of the time delay. 1. A circuit , comprising:a charging capacitor including a common terminal;a switched capacitor voltage-to-current converter configured to convert a reference voltage into a first current;a current mirror configured to convert the first current into a second current and to provide the second current to charging capacitor through the common terminal; anda comparator having a first input terminal couped to the common terminal.2. The circuit of claim 1 , wherein the current mirror includes:a first switch coupled between the current mirror and the common terminal, the first switch being configured to close responsive to a timing signal.3. The circuit of claim 2 , wherein the switched capacitor voltage-to-current converter includes:a first transistor; andan error amplifier having an output terminal coupled to a gate of the first transistor, wherein the current mirror includes a diode-connected transistor in series with the first transistor and a second transistor having a gate connected to a gate of the diode-connected transistor.4. The circuit of claim 3 , wherein the first switch is coupled between the common terminal and the second transistor.5. The circuit of claim 3 , wherein the switched capacitor voltage-to-current converter further includes:a degeneration resistor coupled between ground and a source of the first transistor.6. The circuit of claim 3 , wherein the switched capacitor voltage-to-current converter further includes: ...

PHASE-CONTINUOUS REFERENCE CLOCK FREQUENCY SHIFT FOR DIGITAL PHASE LOCKED LOOP

Systems, circuitries, and methods are described for phase-continuous shifting of a reference clock frequency from fto Nfor a DPLL that includes a DCO and a feedback loop that generates a feedback signal. The DPLL generates a local oscillator signal based on an analog reference signal having a reference clock frequency fand a digital reference signal having the reference clock frequency f. In one example, the method includes receiving a target time and at expiration of a first nonzero interval after the target time, generating a subsequent feedback signal having the target reference clock frequency Nf; at expiration of a second nonzero interval after the target time, generating a subsequent analog reference signal having the target reference clock frequency Nf; and at expiration of a third nonzero interval after the target time, generating a subsequent digital reference clock signal having the target reference clock frequency Nf. 1. A reference clock frequency shifting circuitry for a digital phase locked loop (DPLL) including a digitally controlled oscillator (DCO) and a feedback loop , wherein the DPLL generates a local oscillator signal based on an analog reference signal having a reference clock frequency f , the circuitry comprising: a multiplier configured to multiply an oscillator signal by N to generate a multiplied oscillator signal;', 'a multiplexor configured to output an analog reference signal selectively based on either the oscillator signal or the multiplied oscillator signal;, 'a multiplier circuitry comprising{'sup': 'th', 'a digital clock circuitry comprising clock gating circuitry configured to receive a master clock signal and pass every xpulse of the master clock signal to generate a digital reference clock signal;'} a divider configured to divide an input channel word by N to generate a scaled channel word;', 'a multiplexor configured to selectively output either the channel word or the scaled channel word to control the feedback loop to ...

Event driven signal converters

In some implementations, a method comprises: generating, by an event system of an integrated circuit, a first event signal in response to a clock signal; distributing the first event signal to a first digital converter, where the first event signal triggers conversion of a first analog signal to a first digital value by the first digital converter; generating, by the event system, a second event signal in response to the clock signal; and distributing the second event signal to a second digital converter, where the second event signal triggers conversion of a second analog signal to a second digital value.

A METHOD AND A SYSTEM FOR CALIBRATING A PHASE NONLINEARITY OF A DIGITAL-TO-TIME CONVERTER

A method for calibrating a phase nonlinearity of a digital-to-time converter is provided. The method includes generating, based on a control word, a reference signal using a phase-locked loop. A frequency of the reference signal is equal to a frequency of an output signal of the digital-to-time converter. Further, the method includes measuring a temporal order of a transition of the output signal from a first signal level to a second signal level, and a transition of the reference signal from the first signal level to the second signal level. The method additionally includes adjusting a first entry of a look-up table based on the measured temporal order. 125-. (canceled)26. A method for calibrating a phase nonlinearity of a digital-to-time converter , comprising:generating, based on a control word, a reference signal using a phase-locked loop, wherein a frequency of the reference signal is substantially equal to a frequency of an output signal of the digital-to-time converter;measuring a temporal order of a transition of the output signal from a first signal level to a second signal level, and a transition of the reference signal from the first signal level to the second signal level; andadjusting a first entry of a look-up table based on the measured temporal order.27. The method of claim 26 , wherein the digital-to-time converter generates the output signal based on the first entry of the look-up table claim 26 , and wherein the first entry is assigned to a first control code for the digital-to-time converter which is based on the control word for controlling the frequency of the output signal.28. The method of claim 26 , further comprising:adjusting a phase of the reference signal to be substantially equal to a phase of the output signal generated by the digital-to-time converter based on a second entry in the look-up table, wherein the second entry is assigned to a second control code for the digital-to-time converter for which the digital-to-time converter is ...

OPERATING PARAMETER CIRCUITRY AND METHOD

An operating parameter method and circuitry are provided that generate operating parameter signals that are compensated for noise. Such operating parameter circuitry includes control loop circuitry that operates from a first power supply to provide an operating parameter signal to functional circuitry operating from a second power supply separate from the first power supply. The control loop circuitry comprises generator circuitry to generate the operating parameter signal based on an input signal. Replica generator circuitry operates from the second power supply to generate a further operating parameter signal based on the input signal. Adjustment circuitry performs a comparison on the operating parameter signal and the further operating parameter signal and causes an adjusted input signal to be produced in dependence on a result of the comparison. The adjusted input signal is received by the generator circuitry. Consequently, the generator circuitry is able to produce an operating parameter signal that has been compensated for noise in the circuit. 1. Operating parameter circuitry , comprising:control loop circuitry operating from a first power supply to provide an operating parameter signal to functional circuitry operating from a second power supply separate from the first power supply, the control loop circuitry comprising generator circuitry to generate the operating parameter signal based on an input signal;replica generator circuitry operating from the second power supply to generate a further operating parameter signal based on the input signal; andadjustment circuitry to perform a comparison on the operating parameter signal and the further operating parameter signal and to cause an adjusted input signal to be produced in dependence on a result of the comparison, wherein the adjusted input signal is received by the generator circuitry.2. The operating parameter circuitry according to claim 1 , wherein the adjustment circuitry comprises:comparison circuitry ...

Successive approximation analog-to-digital converter and conversion method

The present invention discloses a successive approximation analog-to-digital converter capable of improving the accuracy of analog-to-digital conversion. An embodiment of this converter comprises: a successive approximation analog-to-digital converting circuit operable to generate M bits according to an analog input signal in which the M bits include a most significant bit (MSB) and successive M−1 bit(s) in succession to the MSB while the number M is an integer greater than one; and a multi-bit generating circuit operable to receive a capacitor array output signal and a comparison signal outputted from the successive approximation analog-to-digital converting circuit for a predetermined time after the generation of the M bits, and then generate N bits at a time accordingly in which the N bits include a least significant bit (LSB) and successive N−1 bit(s) ahead of the LSB while the number N is an integer greater than one. 1. A successive approximation analog-to-digital converter capable of improving the accuracy of analog-to-digital conversion , comprising:a successive approximation analog-to-digital converting circuit operable to generate M bits according to an analog input signal in which the M bits include a most significant bit (MSB) and successive M−1 bit(s) in succession to the MSB while M is an integer greater than one; and an accumulation signal generating circuit operable to accumulate a capacitor array output signal and a comparison signal from the successive approximation analog-to-digital converting circuit after the generation of the M bits and thereby generate an accumulation signal; and', 'a multibit analog-to-digital converting circuit operable to generate N bits according to the accumulation signal in which the N bits include a least significant bit (LSB) and successive N−1 bit(s) ahead of the LSB while N is an integer greater than one., 'a multibit generating circuit including2. The successive approximation analog-to-digital converter of claim 1 , ...

AUTO FREQUENCY CALIBRATION FOR A PHASE LOCKED LOOP AND METHOD OF USE

An apparatus comprises a code generator configured to generate a coarse tuning signal and a reset signal based on a reference frequency and a phase difference signal. The apparatus also comprises a digital loop filter configured to generate a fine tuning signal based on the phase difference signal. The apparatus further comprises a voltage control oscillator configured to generate an output signal based on the coarse tuning signal and the fine tuning signal. The apparatus additionally comprises a divider configured to generate a divider frequency based on a divider control signal and the output signal. The phase difference signal is based, at least in part, on the divider frequency, and the divider is configured to be reset based on the reset signal. 1. An apparatus comprising:a code generator configured to generate a coarse tuning signal and a reset signal based on a reference frequency and a phase difference signal;a digital loop filter configured to generate a fine tuning signal based on the phase difference signal;a voltage control oscillator configured to generate an output signal based on the coarse tuning signal and the fine tuning signal; anda divider configured to generate a divider frequency based on a divider control signal and the output signal,wherein the phase difference signal is based, at least in part, on the divider frequency, and the divider is configured to be reset based on the reset signal.2. The apparatus of claim 1 , further comprising:a phase difference detector configured to generate the phase difference signal based on a comparison of the reference frequency and the divider frequency.3. The apparatus of claim 2 , wherein the phase difference detector comprises a time-to-digital converter (TDC) circuit.4. The apparatus of claim 3 , wherein the phase difference detector further comprises an analog-to-digital converter (ADC) circuit.5. The apparatus of claim 1 , wherein the code generator comprises:a first comparator configured to generate a ...

Fully-digital fully-synthesizable delay-line analog to digital converter

The present invention relates to the realization of an ADC by using a one shot time cell as an analog-to-time converter and a time-to-digital converter. The present invention relates in general, to the design and Integrated Circuit (IC) implementation of a fully-digital fully-synthesizable, delay-line analog-to-digital converter (DL-ADC). The present invention is specifically relevant for power management applications where the silicon area of the controller is of key importance. The design of the ADC is based on the approach of delay cells string to reduce design complexity and the resultant of the silicon area.