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Небесная энциклопедия

Космические корабли и станции, автоматические КА и методы их проектирования, бортовые комплексы управления, системы и средства жизнеобеспечения, особенности технологии производства ракетно-космических систем

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Мониторинг СМИ

Мониторинг СМИ и социальных сетей. Сканирование интернета, новостных сайтов, специализированных контентных площадок на базе мессенджеров. Гибкие настройки фильтров и первоначальных источников.

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Форма поиска

Поддерживает ввод нескольких поисковых фраз (по одной на строку). При поиске обеспечивает поддержку морфологии русского и английского языка
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Применить Всего найдено 18165. Отображено 100.
29-08-2017 дата публикации

Вычислительный модуль авиационного комплекса

Номер: RU0000173478U1

Полезная модель относится к области вычислительной техники и интегрированной модульной авионики и может быть использована в малогабаритных авиационных комплексах, предназначенных для оснащения, преимущественно воздушных судов легкой и сверхлегкой авиации. Сущность полезной модели - вычислительный комплекс выполнен в виде безвентиляторной процессорной платы формата РС/104 с LAN (10/100) с возможностью соединения по системной шине ввода-вывода с двухканальным интерфейсом с первым и вторым резистивными цифро-аналоговыми преобразователями, с интерфейсом инерциальной навигационной системы, с интерфейсом спутниковой навигационной системы, с интерфейсом транспондера, с интерфейсом системы радионавигации, с интерфейсом аудиосистемы, с интерфейсом системы УКВ радиосвязи, соединенным линейным аудиоканалом с интерфейсом аудиосистемы, с интерфейсом цифро-аналогового преобразования, а также с интерфейсом резервного источника питания, с интерфейсом Flash-накопителей и через два последовательных USB-интерфейса с планшетными компьютерами. 1 ил. Ц 1 173478 ко РОССИЙСКАЯ ФЕДЕРАЦИЯ (19) (11) зе аз га (13) (51) МПК ВбАР 47/00 (2006.01) СОбЕ 1/00 (2006.01) ФЕДЕРАЛЬНАЯ СЛУЖБА ПО ИНТЕЛЛЕКТУАЛЬНОЙ СОБСТВЕННОСТИ (12) ОПИСАНИЕ ПОЛЕЗНОЙ МОДЕЛИ К ПАТЕНТУ (21)(22) Заявка: 2016152754, 30.12.2016 (24) Дата начала отсчета срока действия патента: 30.12.2016 Дата регистрации: 29.08.2017 Приоритет(ы): (22) Дата подачи заявки: 30.12.2016 (45) Опубликовано: 29.08.2017 Бюл. № 25 Адрес для переписки: 117405, Москва, М-405, Варшавское ш., 143, корп. 1, кв. 110, Борисову Э.В. (72) Автор(ы): Васин Павел Владимирович (КО), Великовский Сергей Михайлович (КП), Плешков Дмитрий Васильевич (КП) (73) Патентообладатель(и): Васин Павел Владимирович (КО), Великовский Сергей Михайлович (КП), Плешков Дмитрий Васильевич (КО) (56) Список документов, цитированных в отчете о поиске: КО 135428 01, 10.12.2013. КО 47096 01, 10.08.2005. 05 20130083960 АТ, 04.04.2013. 0$ 8301867 В1, 30.10.2012. (54) Вычислительный модуль ...

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02-03-2018 дата публикации

Устройство управления питанием встраиваемого компьютера

Номер: RU0000177621U1

Предлагаемая полезная модель относится к способам управления питанием для промышленных и бытовых устройств, использующих в своем составе компьютер, и может быть использована в машиностроении, приборостроении, робототехнике.Устройство управления питанием содержит кнопку включения, электромагнитное или иное реле, подключенное к цепи компьютера, в которой присутствует напряжение во время работы операционной системы компьютера и пропадает при завершении его работы. В частном случае выполнения присутствует дополнительное реле. В другом частном случае выполнения используется контактор и дополнительное реле. В третьем частном случае выполнения основное реле включается по схеме с самоблокировкой, и присутствует дополнительное реле, отключающее самоблокировку при появлении сигнала от компьютера. В частном случае выполнения основное реле включается по схеме с самоблокировкой, и присутствует дополнительное реле, отключающее самоблокировку по сигналу от компьютера с задержкой времени. В другом частном случае выполнения основное реле включается по схеме с самоблокировкой, и присутствует дополнительное реле, отключающее самоблокировку при пропадании сигнала от компьютера.Предложенное устройство обеспечивает повышение надежности работы с установкой, содержащей встраиваемый компьютер, за счет исключения ошибок оператора при включении и выключении установки, повышения электробезопасности и пожарной безопасности. РОССИЙСКАЯ ФЕДЕРАЦИЯ (19) RU (11) (13) 177 621 U1 (51) МПК G06F 1/26 (2006.01) ФЕДЕРАЛЬНАЯ СЛУЖБА ПО ИНТЕЛЛЕКТУАЛЬНОЙ СОБСТВЕННОСТИ (12) ОПИСАНИЕ ПОЛЕЗНОЙ МОДЕЛИ К ПАТЕНТУ (52) СПК G06F 1/00 (2006.01); G06F 1/26 (2006.01); G06F 1/263 (2006.01); G06F 1/266 (2006.01); H03K 17/00 (2006.01) (21)(22) Заявка: 2017115094, 28.04.2017 28.04.2017 Дата регистрации: 02.03.2018 (45) Опубликовано: 02.03.2018 Бюл. № 7 1 7 7 6 2 1 R U (56) Список документов, цитированных в отчете о поиске: CN 104460915 A, 25.03.2015. RU 2109324 C1, 20.04.1998. US 8726050 B2, 13.05.2014. RU 2573238 C2, 20.01 ...

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09-02-2012 дата публикации

Optical memory expansion

Номер: US20120033978A1
Принадлежит: Hewlett Packard Development Co LP

Various embodiments of the present invention are directed to optical-based methods and expansion memory systems for disaggregating memory of computer systems. In one aspect, an expansion memory system comprises a first optical/electronic interface in electrical communication with a processor, a memory expansion board configured with memory, and a second optical/electronic interface attached to the memory expansion board. The first interface converts optical signals into electronic signals that are sent to the processor and converts electronic signals produced by the processor into optical signals. The second interface converts optical signals into electronic signals that are sent to the memory and converts electronic signals produced by the memory into optical signals. The optical signals are exchanged between the first and second interfaces. Embodiments also include methods for sending and receiving data in an expansion memory system.

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08-03-2012 дата публикации

Precision synchronisation architecture for superspeed universal serial bus devices

Номер: US20120059965A1
Автор: Peter Graham Foster
Принадлежит: CHRONOLOGIC PTY LTD

A method of providing a synchronisation channel to a SuperSpeed USB device is provided. The method including a SuperSpeed communication channel connection to the SuperSpeed USB device with a USB cable that has USB 2.0 D+ and D− data signalling lines disabled or disconnected at an upstream connection point; multiplexing synchronization information onto the D+/D− data signalling lines at the upstream connection point; and demultiplexing the synchronization information from the D+/D− signalling lines at a downstream connection point of the cable; whereby the synchronisation channel is maintained across the D+/D− data signalling lines.

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15-03-2012 дата публикации

Synchronous network of superspeed and non-superspeed usb devices

Номер: US20120066418A1
Автор: Peter Graham Foster
Принадлежит: CHRONOLOGIC PTY LTD

A method of synchronising the operation of a plurality of SuperSpeed USB devices and a plurality of non-SuperSpeed USB devices is provided. The method includes establishing a SuperSpeed synchronisation channel for each of the plurality of SuperSpeed USB devices; establishing a non-SuperSpeed synchronisation channel for each of the plurality of non-SuperSpeed USB devices; synchronising a respective local clock of each of the plurality of SuperSpeed USB devices; synchronising a respective local clock of each of the plurality of non-SuperSpeed USB devices; and synchronising the SuperSpeed and non-SuperSpeed synchronisation channels so that the SuperSpeed and non-SuperSpeed devices can operate in synchrony.

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15-03-2012 дата публикации

Compound universal serial bus architecture providing precision synchronisation to an external timebase

Номер: US20120066537A1
Автор: Peter Graham Foster
Принадлежит: CHRONOLOGIC PTY LTD

A method of synchronising a compound Super Speed USB device, comprising: providing data communication between a host computing device and the compound Super Speed USB device across the Super Speed USB communication channel; establishing a Super Speed USB communication channel to a Super Speed USB function of the compound USB device; establishing a non-Super Speed synchronisation channel to a non-Super Speed USB function of the compound USB device; and synchronising a local clock of the compound USB device to a periodic data structure within a data stream in the non-Super Speed synchronisation channel so that the local clock can enable synchronous operation of the compound USB device with one or more comparable USB devices.

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29-03-2012 дата публикации

Providing per core voltage and frequency control

Номер: US20120079290A1
Принадлежит: Intel Corp

In one embodiment, the present invention includes a processor having a plurality of cores and a control logic to control provision of a voltage/frequency to a first core of the plurality of cores independently of provision of a voltage/frequency to at least a second core of the plurality of cores. In some embodiments, the voltages may be provided from one or more internal voltage regulators of the processor. Other embodiments are described and claimed.

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05-04-2012 дата публикации

Dynamically adjusting pipelined data paths for improved power management

Номер: US20120084540A1
Принадлежит: International Business Machines Corp

A design structure embodied in a machine readable, non-transitory storage medium used in a design process includes a system for dynamically varying the pipeline depth of a computing device. The system includes a state machine that determines an optimum length of a pipeline architecture based on a processing function to be performed. A pipeline sequence controller, responsive to the state machine, varies the depth of the pipeline based on the optimum length. A plurality of clock splitter elements, each associated with a corresponding plurality of latch stages in the pipeline architecture, are coupled to the pipeline sequence controller and adapted to operate in a functional mode, one or more clock gating modes, and a pass-through flush mode. For each of the clock splitter elements operating in the pass-through flush mode, data is passed through the associated latch stage without oscillation of clock signals associated therewith.

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03-05-2012 дата публикации

Data paths using a first signal to capture data and a second signal to output data and methods for providing data

Номер: US20120110368A1
Автор: Eric Lee
Принадлежит: Micron Technology Inc

Data paths, memories, and methods for providing data from memory are disclosed. An example read data path includes a delay path, and a clocked data register. The data path has a data propagation delay and is configured to receive data and propagate the data therethrough. The delay path is configured to receive a clock signal and provide a delayed clock signal having a delay relative to the clock signal that models the data propagation delay. The clocked data register is configured to clock in data responsive at least in part to the delayed clock signal. The clocked data register is further configured to clock out data responsive at least in part to the clock signal.

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10-05-2012 дата публикации

System and method for synchronizing operations among a plurality of independently clocked digital data processing devices

Номер: US20120117200A1
Принадлежит: Individual

A system is described for maintaining synchrony of operations among a plurality of devices having independent clocking arrangements. A task distribution device is to distribute tasks to a synchrony group comprising a plurality of devices to perform tasks distributed by the task distribution device in synchrony. The task distribution device distributes each task to synchrony group members over a network. Each task is associated with a time stamp that indicates a time, relative to a clock maintained by the task distribution device, at which synchrony group members are to execute the task. Each synchrony group member periodically obtains from the task distribution device an indication of current time indicated by its clock, determines a time differential between the task distribution device's clock and its respective clock and determines therefrom a time at which, according to its respective clock, the time stamp indicates that it is to execute the task.

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10-05-2012 дата публикации

Providing fault-tolerant spread spectrum clock signals in a system

Номер: US20120117415A1
Принадлежит: Hewlett Packard Development Co LP

To provide fault-tolerant, spread spectrum clock signals, a plurality of processing modules having respective spread spectrum control circuits are provided. Clock signals of redundant clock sources are provided to the plurality of processing modules. Failover control logic selects a corresponding one of the clock signals from the redundant clock sources for use in each of the processing modules. Frequency spreading is applied to the corresponding selected clock signal in each of at least some of the plurality of processing module.

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24-05-2012 дата публикации

Stabilized Digital Quadrature Oscillator

Номер: US20120126903A1
Принадлежит: Applied Micro Circuits Corp

A stabilized quadrature oscillator providing consistently high signal quality is disclosed. The stabilized quadrature oscillator includes an iterative quadrature oscillator and a quadrature signal stabilizer. The iterative quadrature oscillator generates an iterative cosine signal and an iterative sine signal using a stabilized cosine signal and a stabilized sine signal from the quadrature signal stabilizer. The quadrature signal stabilizer generates the stabilized cosine signal and the stabilized sine signal based on an energy measure of the iterative cosine signal and the iterative sine signal. Specifically, if the energy measure is less than a low threshold then the quadrature signal stabilizer generates the stabilized sine signal and the stabilized cosine signal to have a greater magnitude than the iterative sine signal and the iterative cosine signal, respectively. Conversely, if the energy measure is greater than a high threshold then the quadrature signal stabilizer generates the stabilized sine signal and the stabilized cosine signal to have a lesser magnitude than the iterative sine signal and the iterative cosine signal, respectively.

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21-06-2012 дата публикации

Method and apparatus for phase selection acceleration

Номер: US20120154011A1
Принадлежит: Advanced Micro Devices Inc

A method and apparatus for generating a clock that can be switched in phase within a reduced interval of dead time are disclosed.

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12-07-2012 дата публикации

Oscillator circuit

Номер: US20120176204A1
Принадлежит: Mitsumi Electric Co Ltd

An oscillator circuit includes a clock oscillator which outputs a main clock signal having an oscillating frequency switched between a high frequency and a low frequency in response to a frequency selection signal, and a frequency divider circuit which outputs a sub-clock signal having a divided frequency equivalent to a frequency division ratio of the oscillating frequency of the main clock signal, the frequency division ratio being switched in response to the frequency selection signal. The divided frequency of the sub-clock signal is predetermined for each of the high frequency and the low frequency to which the oscillating frequency is switched in response to the frequency selection signal.

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19-07-2012 дата публикации

Wireless network connection system and method

Номер: US20120185606A1
Автор: Iulian Mocanu
Принадлежит: Sierra Wireless Inc

The present invention provides a device, system, method and computer-program product for transferring information between a host computer and a wireless network. The device and system comprise an operatively linked mass storage module and modem module. The mass storage module is configured to transfer information with a host computer. The modem module is configured to transfer information with one or more wireless networks. Communication between the host computer and the mass storage module is at least in part using file system input/output protocols. One or more virtual drivers are provided on the host computer to enable communication with the modem module without installation of modem specific drivers.

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26-07-2012 дата публикации

System and method for synchronizing operations among a plurality of independently clocked digital data processing devices

Номер: US20120192071A1
Принадлежит: Individual

A system is described for maintaining synchrony of operations among a plurality of devices having independent clocking arrangements. A task distribution device is to distribute tasks to a synchrony group comprising a plurality of devices to perform tasks distributed by the task distribution device in synchrony. The task distribution device distributes each task to synchrony group members over a network. Each task is associated with a time stamp that indicates a time, relative to a clock maintained by the task distribution device, at which synchrony group members are to execute the task. Each synchrony group member periodically obtains from the task distribution device an indication of current time indicated by its clock, determines a time differential between the task distribution device's clock and its respective clock and determines there from a time at which, according to its respective clock, the time stamp indicates that it is to execute the task.

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02-08-2012 дата публикации

Program execution device

Номер: US20120198243A1
Принадлежит: Individual

A program execution device capable of protecting a program against unauthorized analysis and alteration is provided. The program execution device includes an execution unit, a first protection unit, and a second protection unit. The execution unit executes a first program and a second program, and is connected with an external device that is capable of controlling the execution. The first protection unit disconnects the execution unit from the external device while the execution unit is executing the first program. The second protection unit protects the first program while the execution unit is executing the second program.

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09-08-2012 дата публикации

System and method for reducing holdover duration

Номер: US20120200361A1
Автор: Russell Smiley
Принадлежит: ROCKSTAR BIDCO LP

A device is provided having a local oscillator (LO) configured to generate a first signal comprising at least one of timing information, frequency information, phase information and combinations thereof. The device also has a LO error corrector comprising an input, the input configured to receive a second signal comprising at least one of timing information, frequency information, phase information and combinations thereof. The second signal is used for disciplining the LO. The LO error corrector is capable of disciplining the LO using a source that is less accurate than a preferred second signal, if the preferred second signal is unavailable to discipline the LO.

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09-08-2012 дата публикации

Autonomous, Scalable, Digital System For Emulation of Wired-Or Hardware Connection

Номер: US20120203537A1
Автор: Daniel J. Barus
Принадлежит: International Business Machines Corp

A method and device for preserving the wired-OR nature of the clock signal connection between two devices without a direct analog connection between the lines and in an infinitely scalable fashion. The method includes detecting a logic state at a first connector and a second connector and driving an appropriate connector of the device to an active state in response to determining that a connector is driving an active state. The device includes first and second connectors for communicating logic states and driving active states in response to detected logic states.

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13-09-2012 дата публикации

Methods and systems for data interchange between a network-connected thermostat and cloud-based management server

Номер: US20120233478A1
Принадлежит: Nest Labs Inc

Aspects of the present invention provide energy conserving communications for networked thermostats powered, in part, by batteries. A thermostat communication server stores a thermostat battery-level to determine what data should be sent to the thermostat. The thermostat communication server classifies types of data to be transmitted to the thermostat according to a data priority ranging from a low-priority to a high-priority data type. If the battery-level associated with the battery on the thermostat is at a low battery-level, the thermostat communication server may only transmit data classified under a high-priority data type. This conserves the power used by the thermostat, allows the battery on the thermostat time to recharge and perform other functions. If the battery-level of the thermostat is at a high level, the thermostat communication server may transmit a range of data to the thermostat classified from a low-priority type to a high-priority data type.

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20-09-2012 дата публикации

Synchronous data processing system and method

Номер: US20120239961A1
Принадлежит: FREESCALE SEMICONDUCTOR INC

A synchronous data processing system includes a memory module to store data and a memory controller coupled to the memory module. The memory controller includes a clock inverter to receive an input clock signal and to transmit an inverted clock signal to the memory module. The inverted clock signal incurs a first propagation delay prior to reaching the memory module as a memory clock signal. A write data buffer is coupled to the memory module. The write data buffer transmits data to the memory module in response to the input clock signal. An asynchronous first-in-first-out (ASYNC FIFO) buffer is coupled to the memory module. The ASYNC FIFO buffer reads data from the memory module in response to a feedback signal generated by feeding back the memory clock signal to the ASYNC FIFO buffer.

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18-10-2012 дата публикации

Display Panel Attachment Mechanism

Номер: US20120260483A1
Принадлежит: Barco Inc

A light-emitting display system has interlocking tiles. In an implementation, each tile has a portion of a clamp that joins with another portion of the clamp on another tile. A tile is removed from the display by unlocking the clamp portions. The tile is removed without affecting the position of the other tiles in the display.

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25-10-2012 дата публикации

Clock gating cell circuit

Номер: US20120268168A1

A clock gate includes a first Muller gate that receives at its inputs a clock signal and an enable signal. The output of the first Muller gate is applied, with a delayed version of the clock signal, to a second Muller gate. A logic circuit operates to logically combine the output of the second Muller gate with a delayed version of the clock signal. The output of the logic circuit provides a gated clock output.

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25-10-2012 дата публикации

Interface

Номер: US20120272089A1
Принадлежит: Wolfson Microelectronics plc

The present invention relates to methods and apparatus for data transfer. A data interface is described with at least a first data terminal for either outputting or receiving a data signal. In bi-directional embodiments there may be one terminal for receiving data and one terminal for outputting data. A bit clock terminal outputs or receives a bit clock signal; and a frame clock terminal for outputs or receives a frame clock signal. Interface control circuitry is configurable to associate data outputted or received in each frame with time slots (1-8) of a predetermined number of bits (x, y, z) wherein the control circuitry is adapted such that the frequency of the bit clock signal can be changed at any time so as to vary the number of time slots in a frame.

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08-11-2012 дата публикации

Semiconductor integrated circuit and abnormal oscillation detection method for semiconductor integrated circuit

Номер: US20120280757A1
Автор: Masanori Honda
Принадлежит: Renesas Electronics Corp

A semiconductor device includes a first oscillator that generates a first clock signal, a second oscillator that generates a second clock signal in response to the first clock signal, a third oscillator that generates a third clock signal, a counter that counts a signal corresponding to the first clock signal or a signal corresponding to the second clock signal during a predetermined period that is set based on the third clock signal to generate an overflow signal indicating that a count value of the signal corresponding to the first clock signal or the signal corresponding to the second clock signal exceeds a predetermined value, and an abnormality notice unit that receives the overflow signal to generate an abnormal signal indicating that an abnormal oscillation occurs in at least one of the first to third clock signals.

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22-11-2012 дата публикации

User authentication by combining speaker verification and reverse turing test

Номер: US20120296651A1
Автор: Kuansan Wang
Принадлежит: Microsoft Corp

Methods and system for authenticating a user are disclosed. The present invention includes accessing a collection of personal information related to the user. The present invention also includes performing an authentication operation that is based on the collection of personal information. The authentication operation incorporates at least one dynamic component and prompts the user to give an audible utterance. The audible utterance is compared to a stored voiceprint.

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22-11-2012 дата публикации

Maintaining privacy for transactions performable by a user device having a security module

Номер: US20120297185A1
Автор: Jan Camenisch
Принадлежит: International Business Machines Corp

A method and system for maintaining privacy for transactions performable by a user device having a security module with a privacy certification authority and a verifier are disclosed. The system includes an issuer providing an issuer public key; a user device having a security module for generating a first set of attestation-signature values; a privacy certification authority computer for providing an authority public key and issuing second attestation values; and a verification computer for checking the validity of the first set of attestation signature values with the issuer public key and the validity of a second set of attestation-signature values with the authority public key, the second set of attestation-signature values being derivable by the user device from the second attestation values, where it is verifiable that the two sets of attestation-signature values relate to the user device.

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13-12-2012 дата публикации

Power management in a data-capable strapband

Номер: US20120316471A1
Принадлежит: AliphCom LLC

Embodiments of the invention relates generally to electrical and electronic hardware, computer software, wired and wireless network communications, and computing devices, and more specifically to structures and techniques for managing power generation, power consumption, and other power-related functions in a data-capable strapband. Embodiments relate to a wearable band including sensors, a controller coupled to the sensors, an energy storage device, a power port configured to receive power and control signals, and a power manager. The power manager includes at least a transitory power manager configured to control an application of power to one or more components of the wearable band in one or more power modes. The band can be configured as a wearable communications device and sensor platform.

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20-12-2012 дата публикации

Clock Integrated Circuit

Номер: US20120319756A1
Принадлежит: Macronix International Co Ltd

The clock circuit of an integrated circuit operates with variations such as temperature, ground noise, and power noise. Various aspects of an improved clock integrated circuit address one or more of the variations in temperature, ground noise, and power noise.

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10-01-2013 дата публикации

Semiconductor device, radio communication terminal using same, and clock frequency control method

Номер: US20130009687A1
Принадлежит: Renesas Mobile Corp

A semiconductor device 1 includes a clock generation circuit 15 that changes a frequency of an output clock signal according to a control signal div, an arithmetic circuit (e.g., CPU 0 ) that operates according to the clock signal, a storage circuit (e.g., IC 0 ) that is activated according to access from the arithmetic circuit CPU 0 , a memory access detection unit 12 that detects a number of accesses from the arithmetic circuit CPU 0 to the storage circuit IC 0 , and when the number of accesses increases, outputs a request signal (e.g., psreq 1 ), and a clock control circuit 14 that generates the control signal div for lowering the frequency of the clock signal according to the request signal psreq 1.

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10-01-2013 дата публикации

Method of and system for dynamically controlling during run time a multifunction peripheral (mfp) touch panel user interface (ui) from an external remote network-connected computer

Номер: US20130010332A1
Принадлежит: eCopy Inc

In a system for dynamically and remotely providing user interface (UI) display and processing information to a touch panel embedded within a multifunction peripheral (MFP) such as a digital copier having an internal computer for controlling the touch panel, a method that comprises linking the internal computer to an external data communication network having an external remote computer on the network; and upon the inputting of desired selections by a user at the UI and communicating the same over the network to the external computer, providing information from the external computer via the network back to the internal computer that enables dynamically changing or updating the UI display and behavior during run time of the MFP.

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17-01-2013 дата публикации

Method and system for reducing thermal load by forced power collapse

Номер: US20130019120A1
Принадлежит: Qualcomm Inc

A system and method for reducing heat in a portable computing device includes clocking a processor such that it is provided with a full frequency over time t 0 to t 1 . A timer is set to trigger a forced power collapse (“FPC”) that removes all power to the processor from time t 1 to time t 2 . At time t 2 , the processor may be awakened such that it can resume processing at the full frequency. Advantageously, during the FPC, no leakage power (“P L ”) is consumed by the processor between t 1 and t 2 . The result is that the processor averages the same processing efficiency over time t 0 to t 2 as it otherwise would have if a reduced frequency had been provided to it. However, because no P L was consumed during the FPC, the generation of heat between time t 1 and t 2 that is related to P L is avoided.

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21-02-2013 дата публикации

Glitch free clock switching circuit

Номер: US20130043905A1
Автор: Saya Goud Langadi
Принадлежит: Texas Instruments Inc

A glitch free clock switching circuit includes a first enable synchronization logic that generates a first clock enable in response to a first enable from a first enable generation logic. The clock switching circuit includes a second enable synchronization logic that generates a second clock enable in response to a second enable from a second enable generation logic. A logic gate is coupled to an output of the second enable synchronization logic that selects the second clock signal as a logic gate output if the second enable is logic high. A priority multiplexer receives a first clock signal, the first enable and the logic gate output. The multiplexer configured to select the first clock signal as the clock output if the first enable is logic high, irrespective of the logic gate output.

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28-03-2013 дата публикации

Minimizing the Use of Chip Routing Resources When Using Timestamped Instrumentation Data

Номер: US20130080820A1
Автор: Swoboda Gary L.
Принадлежит: TEXAS INSTRUMENTS INCORPORATED

A timestamp generator generates a timestamp value having a predetermined number of most significant bits and a predetermined number of least significant bits. The least significant bits are transmitted to a client via a parallel data bus. The most significant bits are transmitted to the client sequentially via a series data bus. Each client receives the parallel least significant bits and the series most significant bits and assembles a complete time stamp value. 1. A time stamping subsystem of an electronic apparatus comprising:a timestamp generator generating a timestamp value having a first predetermined number of most significant bits and a second predetermined number of least significant bits;a parallel data bus connected to said timestamp generator having said second predetermined number of data lines transmitting in parallel said least significant bits of said timestamp;a series data bus connected to said timestamp generator having a single data line sequentially transmitting in series said most significant bits of said timestamp; and a parallel register connected to said parallel data bus receiving in parallel and storing said least significant bits of said time stamp,', 'a series register connected to said series data bus receiving in series and storing said most significant bits of said time stamp, and', 'a merged register connected to said parallel register and said series register storing a merged timestamp value by concatenation of said least significant bits of said time stamp stored in said parallel register and said most significant bits of said time stamp stored in said series register., 'at least one client, each client including'}2. The time stamping system of claim 1 , wherein: a shift register having a data input connected to said series bus, an enable input receiving a serial clock and a parallel output, said shift register capturing data on said series bus and shifting previously stored data upon each serial clock, and', 'a register having a ...

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18-04-2013 дата публикации

System and method for synchronizing operations among a plurality of independently clocked digital data processing devices

Номер: US20130094670A1
Принадлежит: Sonos Inc

An audio information source interface that receives first audio information from an audio information source directly connected to the audio playback device; an ADC configured to sample the first audio information; a network interface configured to connect the audio playback device to a network and to receive packets from the network containing second audio information and playback timing information from a network audio information source; a DAC for generating an analog audio signal based on either the first or second audio information; an audio amplifier interconnected with the DAC and configured to amplify the audio signal; an audio reproduction device interface interconnected with the audio amplifier; and, a control module configured to receive commands via the network interface and to provide to the DAC one of the first or second audio information.

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25-04-2013 дата публикации

COMPUTER SYSTEM AND METHOD OF CONFIGURING CLOCK THEREOF

Номер: US20130103971A1
Принадлежит: Huawei Technologies Co., Ltd.

The present invention relates to a computer system and a clock configuring method. The computer system comprises at least two nodes, wherein each of the at least two nodes includes a selecting module and a CPU, inputs to the selecting module of any node comprise a clock of the node and a clock output from other node, and an output terminal of the selecting module is connected to the CPU and an input terminal of the selecting module of other node; the computer system further comprises a clock controlling module, whose output terminal is connected to a control terminal of the selecting module to control the clocks of the at least two nodes to be the same clock. When clocks of plural nodes are abnormal, the computer system can still normally operate as long as there is a normal clock in the computer system. 1. A computer system , comprising:at least two nodes, wherein each of the at least two nodes includes a selecting module and a processor, wherein inputs to the selecting module of any node comprise clock of the node and clock output from another node, and an output terminal of the selecting module is connected to the processor of the node and an input terminal of the selecting module of another node; anda clock controlling module, wherein an output terminal of the clock controlling module is connected to a control terminal of the selecting module, for controlling the clocks of the at least two nodes to have the same clock.2. The computer system according to claim 1 , wherein the computer system comprises four nodes connected to one another via selecting modules into a loop claim 1 , wherein inputs to the selecting module of each node comprise the clock of the node and outputs from the selecting modules of two nodes connected to the node.3. The computer system according to claim 1 , wherein the computer system comprises eight nodes respectively located at each vertex of a cuboid claim 1 , wherein four nodes within various surfaces of the cuboid are cross connected to ...

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02-05-2013 дата публикации

Circuit Arrangement for a Data Processing System and Method for Data Processing

Номер: US20130111189A1
Принадлежит: ROBERT BOSCH GMBH

A circuit arrangement for a data processing system is configured to process data in multiple modules. The circuit arrangement is configured to provide a clock as well as a time base and/or a base of at least one further physical quantity for each of the multiple modules. The circuit arrangement also comprises a central routing unit, which is connected to several of the multiple modules. Via the central routing unit, the modules can periodically exchange data based on the time base and/or on the base of the at least one further physical quantity. The several modules are configured to process data independently of and in parallel to other modules of the several modules.

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09-05-2013 дата публикации

Clock circuit for providing an electronic device with a clock signal, electronic device with a clock circuit and method for providing an electronic device with a clock signal

Номер: US20130113527A1
Автор: Martin Mienkina
Принадлежит: FREESCALE SEMICONDUCTOR INC

This invention relates to a clock circuit for providing an electronic device with a clock signal having an adjustable clock frequency. The clock circuit is adapted to receive information regarding a context level of the electronic device and to dynamically control the clock frequency of the clock signal according to the context level. The dynamical control of the clock circuit output frequency based on the context level enables automated power-to-performance control of the electronic device. The invention also relates to an electronic device comprising a context setting unit adapted to set a context level in which the electronic device is operated and a clock circuit. Furthermore, it relates to a method of providing an electronic device with a clock signal having an adjustable clock frequency, wherein a clock circuit receives information regarding a context level of the electronic device; and wherein the clock circuit dynamically controls the clock frequency of the clock signal according to the context level.

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09-05-2013 дата публикации

Clock circuit for a microprocessor

Номер: US20130113539A1
Принадлежит: Research in Motion Ltd

A mobile communication device includes an analog clock and a digital clock circuit. The analog clock circuit is configured to generate an oscillating output. The digital clock circuit is configured to generate a digital clock output having a frequency that is substantially equal to the frequency of the oscillating output.

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16-05-2013 дата публикации

SMART CARD READER WITH A SECURE LOGGING FEATURE

Номер: US20130119130A1
Автор: BRAAMS HARM
Принадлежит: Vasco Data Security, Inc.

A secure smart card reader is disclosed that is enabled to make reader signatures on data representative of events and actions which may be security related and which may include data representative of reader commands received from a host or remote application, smart card commands exchanged with an inserted smart card, data presented to a user for approval, and/or configuration parameters applied when dealing with any of the foregoing. The smart card reader may be adapted to maintain logs of events and actions which may include exchanging reader commands, exchanging smart card commands, and/or interactions with a user. The logs may include data representative of the reader commands received, the smart card commands exchanged, data presented to the user for approval, and/or configuration parameters applied when dealing with any of the foregoing. The secure smart card reader may be adapted to generate a reader signature over the logs. 1. A smart card reader for generating electronic signatures in conjunction with an inserted smart card comprising:a communication interface for communicating with a host computer;a smart card connector for communicating with the smart card;a first memory component for securely storing one or more cryptographic keys;a second memory component for storing a log;a user interface comprising a user output interface for presenting information to the user and a user input interface for receiving user indications;a data processing component for communicating with the host computer, communicating with the smart card and driving the user interface;said smart card reader adapted to exchange smart card commands with a smart card using the smart card connector;said smart card reader further adapted to operate in a secure logging mode in which the smart card reader logs in said log security related events relative to the reader or the reader's usage; andsaid smart card reader further adapted to generate a reader signature on said log using at least one ...

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16-05-2013 дата публикации

CLOCK GATING CIRCUIT AND BUS SYSTEM

Номер: US20130124907A1
Автор: Aoki Sumie
Принадлежит: SONY CORPORATION

The present technology provides an excellent advantageous effect in terms of reducing power consumption of a bus system adapted to treat a transaction as a unit. Disclosed herein is a clock gating circuit including: a clock enable signal generation portion adapted to count the number of outstanding transactions in each of a plurality of regions into which a bus system is divided so as to generate a clock enable signal for each of the plurality of regions; and a masked clock generation portion adapted to mask a clock by using the clock enable signal for each of the plurality of regions so as to generate a masked clock. 1. A clock gating circuit comprising:a clock enable signal generation portion adapted to count the number of outstanding transactions in each of a plurality of regions into which a bus system is divided so as to generate a clock enable signal for each of the plurality of regions; anda masked clock generation portion adapted to mask a clock by using the clock enable signal for each of the plurality of regions so as to generate a masked clock.2. The clock gating circuit of claim 1 , whereinthe clock enable signal generation portion increments the number of the outstanding transactions when a request is input to each of the plurality of regions, and decrements the number of the outstanding transactions when a response to the request is output therefrom so as to count the number of the outstanding transactions, andthe masked clock generation portion masks the clock and outputs the masked clock when the number of the outstanding transactions is zero, and outputs the clock as it is as the masked clock when the number of the outstanding transactions is one or more.3. The clock gating circuit of claim 1 , whereinthe clock enable signal generation portion includes a counter adapted to increment the number of the outstanding transactions when a request is input to each of the plurality of regions and decrement the number of the outstanding transactions when a ...

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30-05-2013 дата публикации

Multi-phase clock signal generation circuits

Номер: US20130135020A1
Принадлежит: Institute of Microelectronics of CAS

Disclosed is a multi-phase clock signal generation circuit including two circuit blocks, each of which includes a cross-coupled structure and two delay units, and the delay units are adjustable. The circuit block MD 1 includes two NMOS transistors, two PMOS transistors, and two delay units. The circuit block MD 2 may include two NMOS transistors, two PMOS transistors, and two delay units. The circuit can generate clock signals with respective phases whose relationship is relatively independent of integration process, operating voltage and temperature, thereby allowing guaranteed efficiency for a multi-phase charge pump.

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30-05-2013 дата публикации

Semiconductor device, a parallel interface system and methods thereof

Номер: US20130135956A1
Принадлежит: Individual

A memory device includes a clock receiving block, a data transceiver block, a phase detection block, and a phase information transmitter. The clock receiving block is configured to receive a clock signal from a memory controller through a clock signal line and generate a data sampling clock signal and an edge sampling clock signal. The data transceiver block is configured to receive a data signal from the memory controller through a data signal line. The phase detection block is configured to generate phase information in response to the data sampling clock signal, the edge sampling clock signal and the data signal. The phase information transmitter is configured to transmit the phase information to the memory controller through a phase information signal line that is separate from the data signal line.

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30-05-2013 дата публикации

Modular integrated circuit with uniform address mapping

Номер: US20130138936A1
Принадлежит: Broadcom Corp

A modular integrated circuit includes a hub module that is coupled to a plurality of spoke modules via a plurality of hub interfaces. A memory module stores hub software and hub data and configuration data. The hub software operates in accordance with a memory map that includes a plurality of first reserved blocks corresponding to memory reserved for the plurality of spoke modules, and at least one second reserved block corresponding to memory reserved for at least one optional spoke module. The plurality of first reserved blocks are activated based on the configuration data and the at least one second reserved block is deactivated based on the configuration data.

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30-05-2013 дата публикации

CLOCK SYNCHRONIZATION IN AN IMPLANTABLE MEDICAL DEVICE SYSTEM

Номер: US20130138991A1
Принадлежит: Medtronic, Inc.

This disclosure is directed to the synchronization of clocks of a secondary implantable medical device (IMD) to a clock of a primary IMD. The secondary IMD includes a communications clock. The communications clock may be synchronized based on at least one received communications pulse. The secondary IMD further includes a general purpose clock different than the communications clock. The general purpose clock may be synchronized based on at least one received power pulse. The communications clock may also be synchronized based on the at least one received power pulse. 1. A system comprising:at least one primary implantable medical device (IMD) configured to operate based on a local clock;at least one secondary IMD communicatively coupled to the primary IMD and configured to receive at least one communication pulse and at least one power pulse from the primary IMD, wherein the at least one power pulse comprises a first power pulse and the secondary IMD is operable to estimate, based on the first power pulse, an estimated arrival time of a subsequent power pulse;a communications clock unit configured to generate a first clock of the secondary IMD based on the at least one communication pulse; anda general purpose clock unit configured to generate a second clock different than the first clock based on the at least one power pulse.2. The system of claim 1 , wherein the communications clock unit is configured to generate the second clock by synchronizing the second clock to the local clock of the primary IMD.3. The system of claim 2 , wherein the local clock of the primary IMD is based on a crystal oscillator.4. The system of claim 1 , wherein the first clock of the secondary IMD is an intermittent clock configured to turn off when the secondary IMD is not operating to communicate.5. The system of claim 1 , wherein the secondary IMD is further operable to detect claim 1 , via at least one sensor of the secondary IMD claim 1 , at least one condition based on an estimated ...

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06-06-2013 дата публикации

Data processing device and data processing system

Номер: US20130145190A1
Принадлежит: Renesas Electronics Corp

A central processing unit sets which of the following modes a data processing device is to operate in accordance with a user program. The high-speed operation mode allows operation within a first range in which an external supply voltage is relatively high. The wide voltage range operation mode allows operation within a second range in which the external supply voltage includes the first range and a relatively low voltage range, and an upper limit of a frequency of the first clock in the wide voltage range operation mode is lower than an upper limit of a frequency of the first clock in the high-speed operation mode. The frequency of the first clock in the low power consumption operation mode is lower than the frequency of the first clock in the high-speed operation mode and the frequency of the first clock in the wide voltage range operation mode.

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06-06-2013 дата публикации

METHOD AND SYSTEM TO IMPROVE THE OPERATIONS OF A REGISTERED MEMORY MODULE

Номер: US20130145197A1
Принадлежит:

A method and system to improve the operations of a registered memory module. In one embodiment of the invention, the registered memory module allows asynchronous read and write operations when a clock circuit in the registered memory module is being activated. In another embodiment of the invention, the registered memory module allows enabling or disabling of its clock circuit without any interruption of its operation. When the clock circuit in the registered memory module is disabled, the power consumption of the registered memory module can be reduced. In yet another embodiment of the invention, the registered memory module is allowed to enter or exit an asynchronous operation mode without entering or exiting a self-refresh or pre-charge power down operation mode of the registered memory module. 1. An apparatus comprising:a phase-locked loop (PLL) to provide a differential clock to a memory; andlogic to facilitate enabling or disabling the PLL without any interruption to operation of the memory.2. The apparatus of claim 1 , wherein the logic to facilitate enabling or disabling the PLL comprises logic to select between an input differential clock to the PLL and an output differential clock of the PLL as the provided differential clock to the memory.3. The apparatus of claim 1 , wherein the logic to facilitate enabling or disabling the PLL comprises logic to enable or disable a connection between the input differential clock to the PLL and the PLL.4. The apparatus of claim 1 , wherein the logic to facilitate enabling or disabling the PLL comprises logic to enable or disable power to the PLL.5. The apparatus of claim 1 , wherein the apparatus is coupled with an external logic and wherein the external logic is to enable or disable power to the PLL.6. The apparatus of claim 1 , further comprising decode logic to:decode a received command;determine that the decoded received command is to enable or disable the PLL; andprovide one or more control signals to the logic to ...

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06-06-2013 дата публикации

Ram-based event counters using transposition

Номер: US20130145200A1
Принадлежит: International Business Machines Corp

Methods and structures that implement an event counter in a RAM are provided. A method includes providing a count-RAM, a carry-RAM, and a pre-counter corresponding to an event source. A column in the count-RAM and a column in the carry-RAM represent a value of a value of the event counter. The method further includes storing a count of the event counter received via the pre-counter in the count-RAM and the carry-RAM in a transposed, bit-serial format, such that location zero of the count-RAM and the carry-RAM counts the least significant bit (LSB) of the event counter.

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20-06-2013 дата публикации

Programmable Drive Strength in Memory Signaling

Номер: US20130159612A1
Автор: Marc Loinaz
Принадлежит: Netlogic Microsystems Inc

Embodiments of the invention relate to programmable data register circuits and programmable clock generation circuits For example, some embodiments include a buffer circuit for receiving input data and sending output data signals along a series of signal lines with a signal strength, and a signal modulator configured to determine the signal strength based on a control input. Some embodiments include a clock generation circuit for receiving clock reference and sending output clock signals along a series of signal lines with a signal character, and a signal modulator configured to determine the signal character based on a control input.

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27-06-2013 дата публикации

Clock generator intermittently generating synchronous clock

Номер: US20130162295A1
Автор: Takahiro Minaki
Принадлежит: Renesas Electronics Corp

A clock generator includes a counter unit receiving a reference clock signal to generate a timing signal, a selector receiving the timing signal to output a clock enable based on bit string data stored in a storage unit and a clock gate cell receiving the reference clock signal based on the clock, thinning some pulses out from the reference clock signal based on the clock enable so that a clock signal is maskable, and outputting an inter intermittent clock signal.

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04-07-2013 дата публикации

Image processing apparatus, upgrade apparatus, display system including the same, and control method thereof

Номер: US20130169625A1
Принадлежит: SAMSUNG ELECTRONICS CO LTD

An image processing apparatus, upgrade apparatus, display system and control method are provided. The image processing apparatus includes a signal input unit; a first image processing unit which processes an input signal input by the signal input unit to output a first output signal; an upgrade apparatus connection unit connected to an upgrade apparatus which includes a second image processing unit; and a first controller which controls at least one of the input signal processed by the first image processing unit and the first output signal to be transmitted to the upgrade apparatus and processed by the second image processing unit if the upgrade apparatus is connected to the upgrade apparatus connection unit.

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04-07-2013 дата публикации

Image processing apparatus, upgrade apparatus, display system including the same, and control method thereof

Номер: US20130169652A1
Принадлежит: SAMSUNG ELECTRONICS CO LTD

An image processing apparatus, upgrade apparatus, display system and control method are provided. The image processing apparatus includes a signal input unit; a first image processing unit which processes an input signal input by the signal input unit to output a first output signal; an upgrade apparatus connection unit connected to an upgrade apparatus which includes a second image processing unit; and a first controller which controls at least one of the input signal processed by the first image processing unit and the first output signal to be transmitted to the upgrade apparatus and processed by the second image processing unit if the upgrade apparatus is connected to the upgrade apparatus connection unit

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04-07-2013 дата публикации

Frequency And Voltage Scaling Architecture

Номер: US20130173948A1
Принадлежит:

A method and apparatus for scaling frequency and operating voltage of at least one clock domain of a microprocessor. More particularly, embodiments of the invention relate to techniques to divide a microprocessor into clock domains and control the frequency and operating voltage of each clock domain independently of the others. 1. A processor comprising:a first clock domain to operate at a first clock frequency, the first clock domain including a renaming unit and a decoding unit;a second clock domain to operate at a second clock frequency, the second clock domain including at least one execution unit; anda third clock domain to operate at a third clock frequency, the third clock domain including a cache memory, wherein the first clock frequency is to be adjusted to minimize a ratio of an energy performance product of the first clock domain between a first time interval and a second time interval.2. The processor of claim 1 , wherein the first time interval is prior to the second time interval.3. The processor of claim 1 , wherein the processor is to estimate energy and delay of the first clock domain for the second time interval.4. The processor of claim 3 , wherein the processor is to calculate energy and delay of the first clock domain for the first time interval.8. The processor of claim 5 , wherein if the ratio is the same for multiple pairs of the first clock frequency and the first operating voltage claim 5 , the pair having a minimum first clock frequency is selected.9. The processor of wherein the first clock domain claim 1 , the second clock domain and the third clock domain each comprise an independent voltage domain.10. The processor of claim 9 , wherein the first clock domain comprises at least one first-in-first out (FIFO) queue.11. The processor of claim 1 , wherein the first clock frequency is to be controlled independently of the second clock frequency.12. A method comprising:determining energy and delay of a processor clock domain of a multi-domain ...

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04-07-2013 дата публикации

HS-CAN BUS CLOCK RECOVERY USING A TRACKING OSCILLATOR CIRCUIT

Номер: US20130173949A1
Автор: Cai Panny, Huag Martin

A method for recovering a clock frequency of a CAN bus, the method including: receiving a data signal, wherein the data signal includes at least one state transition; detecting the state transition; and adjusting a frequency of a clocking signal generated by an oscillator circuit, wherein the frequency is adjusted when the state transition is detected and adjusting the frequency is for recovering the clock frequency of the CAN bus. 1. A method for recovering a clock frequency of a CAN bus , the method comprising:receiving a data signal, wherein the data signal comprises at least one state transition;detecting the state transition; andadjusting a frequency of a clocking signal generated by an oscillator circuit, wherein the frequency is adjusted when the state transition is detected and adjusting the frequency is for recovering the clock frequency of the CAN bus.2. The method of further comprising computing a restart time for resetting the oscillator and generating a synchronization signal based on the computed restart time claim 1 , wherein the synchronization signal is configured to restart the oscillator when the state transition is detected.3. The method of further comprising computing a compensation time for charging and discharging a capacitive element of the oscillator circuit such that the frequency is adjusted and an operational frequency of the oscillator circuit is maintained.4. The method of further comprising determining an increase and decrease of the frequency based on the signal level of the clocking signal when the state transition is detected.5. The method of further comprising generating a sampling signal that determines a sampling point of the received data signal claim 1 , wherein the duty cycle of the sampling signal is programmable and sampling of the received data signal recovers at least one CAN bit of the received data signal.6. The method of wherein the state transition is a falling edge.7. A tracking oscillator circuit configured to ...

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04-07-2013 дата публикации

METHOD AND APPARATUS FOR COMMUNICATING TIME INFORMATION BETWEEN TIME AWARE DEVICES

Номер: US20130173950A1
Принадлежит: MARVELL WORLD TRADE LTD.

According to one embodiment, an apparatus includes a first processing unit operating according to a first clock, a second processing unit operating according to a second clock running separately from the first clock, and a synchronization controller coupled to the first communication unit and the second communication unit. The synchronization controller is configured to (i) cause the first communication unit to generate a first indication of time at which the first processing unit transmits a signal to the second processing unit, according to the first clock, (ii) cause the second processing unit to generate a second indication of time at which the second processing unit receives the signal, according to the second clock, and (iii) determine an offset between the first clock and the second clock based on the first indication of time and the second indication of time. 1. An apparatus comprising:a first processing unit operating according to a first clock;a second processing unit operating according to a second clock running separately from the first clock; and (i) cause the first communication unit to generate a first indication of time at which the first processing unit transmits a signal to the second processing unit, according to the first clock,', '(ii) cause the second processing unit to generate a second indication of time at which the second processing unit receives the signal, according to the second clock, and', '(iii) determine an offset between the first clock and the second clock based on the first indication of time and the second indication of time., 'a synchronization controller coupled to the first communication unit and the second communication unit; wherein the synchronization controller is configured to'}2. The apparatus of claim 1 , further comprising a generic interface via which the first communication unit transmits the signal to the second communication unit.3. The apparatus of claim 2 , wherein the generic interface includes one of (i) a ...

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11-07-2013 дата публикации

USING PULSES TO CONTROL WORK INGRESS

Номер: US20130179721A1
Принадлежит: MICROSOFT CORPORATION

The present invention extends to methods, systems, and computer program products for using pulses to control work ingress. Generally, embodiments of the invention use a variable-speed clock for accepting work for lower-priority services. A clock rate is controlled by a load monitor. The load monitor periodically collects sensor measurements of resources available after allocations by higher-priority services. Based on the sensor measurements, the load monitor adjusts the clock speed up or down (i.e., depending on the amount of resources available after allocations by higher-priority services). At the boundary of the lower-priority service (e.g., where work enters the system), work requests are enqueued to be associated with a future pulse of the clock. Work is accepted or rejected based on a determination of whether the work request can be allocated a clock pulse within a defined period of time. 1. A computing system comprising:one or more processors;a variable speed clock, the variable speed clock defining a clock frequency for emitting clock pulses, the clock frequency being based on a resource load being consumed by processes of the computing system;a pulse controller, the pulse controller matching work items to emitted clock pulses; and an act of a work ingress component receiving a work request for a particular process, the work request sent from an external service;', 'an act of the work ingress component creating a work reservation for the work request;', 'an act of the pulse controller enqueueing the work reservation in a work queue;', 'an act of the pulse controller receiving a pulse, the clock pulse emitted from the variable speed clock in accordance with the clock frequency;', 'an act of the pulse controller dequeueing the work reservation from the work queue in response to receiving the pulse;', 'an act of the pulse controller providing notification to the work ingress component that the work reservation has been fulfilled; and', 'an act of the work ...

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18-07-2013 дата публикации

High Accuracy Sin-Cos Wave and Frequency Generators, and Related Systems and Methods

Номер: US20130181753A1
Автор: David J. Hoyle
Принадлежит: Qualcomm Inc

High accuracy sin-cos wave and frequency generators, and related systems and methods. In non-limiting embodiments disclosed herein, the sin-cos wave generators can provide highly accurate sin-cos values for sin-cos wave generation with low hardware costs and small lookup table requirements. The embodiments disclosed herein may include a circuit to conduct an arithmetic approximation of a sin-cos curve based on a phase input. The circuit may be in communication with a point lookup table and a correction lookup table. The tables may receive the phase input and match the phase input to main sin-cos endpoints associated with the phase, and to a correction value for the phase. These values which are selected based on the phase input, may be communicated to a converter circuit where the arithmetic functions are applied to the values resulting in a sin-cos curve value.

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18-07-2013 дата публикации

Method, apparatus, and system for optimizing frequency and performance in a multidie microprocessor

Номер: US20130185577A1
Принадлежит: Individual

With the progress toward multi-core processors, each core is can not readily ascertain the status of the other dies with respect to an idle or active status. A proposal for utilizing an interface to transmit core status among multiple cores in a multi-die microprocessor is discussed. Consequently, this facilitates thermal management by allowing an optimal setting for setting performance and frequency based on utilizing each core status.

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01-08-2013 дата публикации

Moisture Barrier for Electronic Devices

Номер: US20130194281A1
Принадлежит: Apple Inc.

An electronic display configured to provide a visual output, such as a liquid crystal display. The electronic display includes an optical shutter and a first polarizer operably connected to the optical shutter. The first polarizer includes an optical filter layer, a protective layer, and a moisture barrier positioned on a first surface of either the optical filter or the protective layer. The moisture barrier substantially prevents water molecules from being transmitted therethrough. 1. An electronic display configured to provide a visual output comprising:an optical shutter; and an optical filter layer;', 'a protective layer; and', 'a moisture barrier positioned on a first surface of either the optical filter or the protective layer., 'a first polarizer operably connected to the optical shutter comprising2. The electronic display of claim 1 , wherein the optical filter is polyvinyl alcohol.3. The electronic display of claim 1 , wherein the protective layer is tri-acetyl cellulose.4. The electronic display of claim 1 , wherein the protective layer further comprises a first protective layer and a second protective layer and the optical filter is positioned between the first protective layer and the second protective layer.5. The electronic display of claim 4 , wherein the moisture barrier is positioned between the first protective layer and optical filter.6. The electronic display of claim 4 , wherein the moisture barrier is positioned between the second protective layer and the optical filter.7. The electronic display of claim 4 , wherein the moisture barrier is positioned on the first protective layer on a side opposite of the optical filter.8. The electronic device of claim 1 , wherein the moisture barrier is an inorganic material.9. The electronic device of claim 1 , wherein the moisture barrier has an optical transmittance greater than eighty percent.10. The electronic device of claim 1 , wherein the moisture barrier has a permeability less than ten grams per ...

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01-08-2013 дата публикации

Apparatus and Method for TPM and LAN Power Management

Номер: US20130198543A1
Принадлежит: BROADCOM CORPORATION

In Gigibit Ethernet Systems, the Trusted Platform Module (TPM) is designed to provide trust and security to a platform through integrity measurement, protected storage, and other cryptographic functions. The present invention relates to a TPM-LAN chip with separate TPM and LAN power management. The TPM-LAN chip is designed such a way that power is reduced significantly in different power management modes compared to the legacy devices. This is accomplished by turning off certain clocks during certain operating modes. 1. A system comprising:a primary clock coupled to a first clock selector and a second clock selector;an alternate clock coupled to the first clock selector;a third clock coupled to the second clock selector;a local area network (LAN) module coupled to the first clock selector;a trusted platform module (TPM) coupled to the second clock selector; anda state monitor coupled to the TPM and the LAN module for reporting TPM information to the LAN module, wherein the first clock selector is configured to output either the primary dock or the alternate clock based on an operating status of the LAN module, and wherein the second clock selector is configured to output either the primary clock or the third clock based on the reported TPM information.2. The system of claim 1 , wherein the alternate clock operates at a slower frequency than the primary clock.3. The system of claim 1 , wherein the primary clock operates at 62.5 MHz.4. The system of claim 1 , wherein the third clock operates at 6.25 MHz.5. The system of claim 1 , further comprising a flash interface coupled to the TPM.6. The system of claim 5 , further comprising:a second state monitor coupled to the LAN module and the flash interface for reporting LAN information to the flash interface and flash interface information to the LAN module.7. The system of claim 6 , wherein the LAN information comprises information regarding whether the LAN module is operating using the alternate clock or the primary ...

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15-08-2013 дата публикации

System and method for synchronizing operations among a plurality of independently clocked digital data processing devices

Номер: US20130208911A1
Принадлежит: Sonos Inc

In a network comprising at least a first zone player and a second zone player, a method comprising: receiving, at a user interface module, a command to establish a synchrony group, wherein the synchrony group comprises at least the first zone player and the second zone player; and displaying, at the user interface module, a list of information identifying a plurality of items queued for playback by the synchrony group, wherein (i) at least one of the items on the list has associated location data indicating the at least one item is located on a device attached to the local area network, and (ii) at least one other of the items on the list has associated location data indicating the at least one other item is located on a wide area network.

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15-08-2013 дата публикации

Inter-component communication including slave component initiated transaction

Номер: US20130212311A1
Принадлежит: Intel Corp

Component apparatuses with inter-component communication capabilities, and system having such component apparatuses are disclosed. A component may include a number of control pins including a clock pin, a number of data pins, and a logic unit. The logic unit may be configured to receive a clock signal from another component through the clock pin, to provide an alert signal to the other component through a selected one of the control and data pins to initiate a transaction with the other component, to receive in response to the alert signal from the other component through the data pins a status request to determine nature of the transaction, and to provide in response to the status request to the other component through the data pins a status to indicate the nature of the transaction. Other embodiments may be disclosed or claimed.

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15-08-2013 дата публикации

Using pulses to control work ingress

Номер: US20130212421A1
Принадлежит: Microsoft Corp

Clock pulses of a variable speed clock are adjusted relative to system utilization. A load monitor periodically collects sensor measurements of resources and based on the sensor measurements, the load monitor adjusts the clock speed up or down.

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22-08-2013 дата публикации

Power converting apparatus and power converting system

Номер: US20130214599A1
Автор: Satoshi Taira
Принадлежит: Mitsubishi Electric Corp

A power converting apparatus is connected to a second power converting apparatus via a power supply line and an earth line, and includes: a carrier-signal generating unit configured to switch a frequency to a frequency selected from a plurality of candidate frequencies or a candidate frequency range according to information to be transmitted to the second power converting apparatus and generate a carrier signal having the switched frequency; a PWM-signal generating unit configured to generate a PWM signal using the generated carrier signal; and a switching element for controlling a control target, which makes switching according to the PWM signal to thereby perform an operation for power conversion and transmits a voltage-to-earth signal corresponding to the information to be transmitted, to the second power converting apparatus via the power supply line and the earth line.

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22-08-2013 дата публикации

METHOD OF CORRECTING A DUTY RATIO OF A DATA STROBE SIGNAL

Номер: US20130219208A1
Принадлежит: SAMSUNG ELECTRONICS CO., LTD.

A method of correcting a duty ratio of a data strobe signal is provided. By the method, a duty ratio of a data strobe signal output from a semiconductor memory device is detected and a duty ratio of a clock signal input to the semiconductor memory device is adjusted based on the duty ratio of the data strobe signal. 1. A method of correcting a duty ratio of a data strobe signal , the method comprising:detecting a duty ratio of a data strobe signal output from a semiconductor memory device; andadjusting a duty ratio of a clock signal input to the semiconductor memory device based on the duty ratio of the data strobe signal.2. The method of claim 1 , wherein the semiconductor memory device is a double data rate synchronous dynamic random access memory (DDR SDRAM) device.3. The method of claim 1 , wherein the adjusting is repeatedly performed until the duty ratio of the data strobe signal is a desired ratio.4. The method of claim 3 , wherein the desired ratio is 50%.5. The method of claim 3 , wherein the repeatedly performing the adjusting ends claim 3 , if the duty ratio of the data strobe signal is equal to the desired ratio.6. The method of claim 5 , wherein the data strobe signal includes a first period and a second period claim 5 , the first period corresponding to a period where the data strobe signal has a logic high level and the second period corresponding to a period where the data strobe signal has a logic low level claim 5 , andwherein the duty ratio of the data strobe signal corresponds to a ratio of the first period to a sum of the first period and the second period.7. The method of claim 6 , wherein the clock signal includes a third period and a fourth period claim 6 , the third period corresponding to a period where the clock signal has a logic high level and the fourth period corresponding to a period where the clock signal has a logic low level period of the clock signal claim 6 , andwherein the duty ratio of the clock signal corresponds to a ratio of ...

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22-08-2013 дата публикации

Flat Panel Display Driver Method and System

Номер: US20130219210A1
Автор: Kobayashi Alan Osamu
Принадлежит: STMicroelectronics, Inc.

Methods and systems are described for enabling display system data transmission during use. An integrated circuit package includes input interface circuitry configured to receive an audio-video data stream having a video signal and timing information and timing extraction circuitry that can identify blanking patterns for the video signal. The package includes input processing circuitry for receiving audio-video signal and converting the audio-video data stream input into a low voltage differential signal (LVDS). The package includes a timing controller having timing extraction circuitry, a set of symbol buffers, a scheduler, and timing control circuitry. All configured to implement LVDS data transfer and in some implementation enable point to point data transfer from data buffers to associated column drivers. 126.-. (canceled)27. An integrated circuit configured to operate in a video display device , the integrated circuit comprising:input processing circuitry configured to receive incoming audio-video signal comprising an audio-video data stream having embedded timing information associated with the audio-video data of the audio-video data stream and convert the audio-video data stream into an output signal; timing extraction circuitry for receiving the output signal comprising a stream of data symbols, the circuitry configured to identify a timing pattern for the output signal using the embedded timing information;', 'a set of symbol buffers configured to receive the data symbols of the output signal;', 'a scheduler configured to populate the set of symbol buffers with the data symbols in a pattern consistent with the embedded timing information; and', 'timing control circuitry configured to support a display device for displaying the output signal, wherein the timing control circuitry is arranged to forward the data symbols from the symbol buffers at a specified time associated with characteristics of the display device., 'timing controller configured to receive ...

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29-08-2013 дата публикации

System and method for synchronizing operations among a plurality of independently clocked digital data processing devices

Номер: US20130226323A1
Принадлежит: Sonos Inc

An audio processing device comprising: a network interface configured to connect the audio processing device to a network; an audio information channelization device connected to the network interface and configured to receive audio via the network interface; an audio reproduction device interface configured to output audio to a playback device; a user interface module interface configured to transmit, via the network interface to a user interface module, status information pertaining to the status of a synchrony group, wherein the audio processing device is a member of the synchrony group with at least one additional audio processing device.

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05-09-2013 дата публикации

System and method for synchronizing operations among a plurality of independently clocked digital data processing devices

Номер: US20130231766A1
Принадлежит: Sonos Inc

A plurality of zone players, including at least a first player and a second zone player, wherein the first zone player is designated as a master device of a synchrony group, a method comprising: determining, by the first zone player, that the second zone player should be designated as the master device of the synchrony group; instructing, by the first zone player, the second zone player to be designated as the master device of the synchrony group; and causing, at the first zone player, the first zone player to lose its designation as the master device of the synchrony group.

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05-09-2013 дата публикации

System and method for synchronizing operations among a plurality of independently clocked digital data processing devices

Номер: US20130232214A1
Принадлежит: Sonos Inc

In a network comprising a plurality of zone players, including at least a first zone player and a second zone player, a method comprising: receiving, by the first zone player, first control information from a user interface module; based on the received first control information, transmitting, by the first zone player, second control information to the second zone player, wherein the second control information comprises (i) a network address of an audio information channelization device that provides audio information and playback timing information, and (ii) a multicast address that the audio information channelization device uses to broadcast audio information and playback timing information to the network; and playing, by the first zone player, the audio information in synchrony with the second zone player.

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05-09-2013 дата публикации

INTEGRATED CIRCUIT, VOLTAGE VALUE ACQUISITION METHOD, AND TRANSMISSION AND RECEPTION SYSTEM

Номер: US20130232372A1
Принадлежит: FUJITSU LIMITED

An integrated circuit includes a data signal reception unit that receives a data signal transmitted from a transmission circuit, a timing signal reception unit that receives a timing signal transmitted from the transmission circuit and indicating a reading timing of the data signal, a timing adjustment unit that adjusts an output timing of the timing signal received by the timing signal reception unit, a reading unit that reads the data signal received by the data signal reception unit according to an adjusted timing signal of which the output timing is adjusted by the timing adjustment unit, and a voltage value acquisition unit that acquires a voltage value of the data signal received by the data signal reception unit and a voltage value of the adjusted timing signal of which the output timing is adjusted by the timing adjustment unit. 1. An integrated circuit comprising:a data signal reception unit that receives a data signal transmitted from a transmission circuit;a timing signal reception unit that receives a timing signal transmitted from the transmission circuit and indicating a reading timing of the data signal;a timing adjustment unit that adjusts an output timing of the timing signal received by the timing signal reception unit;a reading unit that reads the data signal received by the data signal reception unit according to an adjusted timing signal of which the output timing is adjusted by the timing adjustment unit; anda voltage value acquisition unit that acquires a voltage value of the data signal received by the data signal reception unit and a voltage value of the adjusted timing signal of which the output timing is adjusted by the timing adjustment unit.2. The integrated circuit according to claim 1 , further comprising:a detection unit that detects that there is an error in the data signal read by the reading unit,wherein the voltage value acquisition unit acquires the voltage value of the data signal and the voltage value of the adjusted timing ...

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19-09-2013 дата публикации

Input capture peripheral with gating logic

Номер: US20130241626A1
Принадлежит: Microchip Technology Inc

A microcontroller has an input capture peripheral, wherein the input capture peripheral is configured to store timer values of an associated timer in a memory and wherein the input capture peripheral has a gating input which controls whether an input capture function is activated.

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19-09-2013 дата публикации

FOOTER-LESS NP DOMINO LOGIC CIRCUIT AND RELATED APPARATUS

Номер: US20130246819A1
Принадлежит:

A domino logic circuit includes a pre-charge circuit pre-charging a first dynamic node in response to a clock signal, a first logic network determining a logic level of the first dynamic node in response to first data signals, an inverter receiving the clock signal, a discharge circuit discharging a second dynamic node in response to an output signal of the inverter, and a second logic network determining a logic level of the second dynamic node in response to at least one second data signal and an output signal of the first dynamic node. 1. A domino logic circuit comprising:a pre-charge circuit that pre-charges a first dynamic node in response to a clock signal;a first logic network that determines a logic level of the first dynamic node in response to first data signals;an inverter that receives the clock signal;a discharge circuit that discharges a second dynamic node in response to an output signal of the inverter; anda second logic network that determines a logic level of the second dynamic node in response to one or more second data signals and an output signal of the first dynamic node.2. The circuit of claim 1 , wherein at least one of the first logic network and the second logic network is a NAND gate.3. The circuit of claim 1 , wherein at least one of the first logic network and the second logic network is a NOR gate.4. The circuit of claim 1 , wherein at least one of the first logic network and the second logic network is either an AND-OR-Invert (AOI) gate or an OR-AND-Invert (OAI) gate.5. The circuit of claim 1 , wherein the pre-charge circuit comprises a first PMOS transistor connected between a power node and the first dynamic node and having a gate receiving the clock signal claim 1 ,the first logic network comprises first NMOS transistors connected in series between the first dynamic node and ground, each of the first NMOS transistors having a gate receiving one of the first data signals,the second logic network comprises second PMOS transistors ...

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19-09-2013 дата публикации

CLOCK GENERATOR AND INFORMATION PROCESSING APPARATUS

Номер: US20130246833A1
Автор: FUKUSHIMA Kimihiro
Принадлежит: RICOH COMPANY, LTD.

A clock generator includes a first clock generating unit configured to generate a first clock signal based on a system clock signal, a second clock generating unit configured to generate a second clock signal with a frequency higher than the frequency of the first clock signal based on the system clock signal, a counting unit configured to count the number of clock pulses of the second clock signal in a cycle of the first clock signal, and an adjusting unit configured to adjust a falling edge or a rising edge of the second clock signal to synchronize with a falling edge or a rising edge of the first clock signal based on an assert signal that is output when the number of clock pulses of the second clock signal counted by the counting unit reaches a predetermined value. 1. A clock generator , comprising:a first clock generating unit configured to generate a first clock signal based on a system clock signal;a second clock generating unit configured to generate a second clock signal with a frequency higher than a frequency of the first clock signal based on the system clock signal;a counting unit configured to count a number of clock pulses of the second clock signal in a cycle of the first clock signal; andan adjusting unit configured to adjust a falling edge or a rising edge of the second clock signal to synchronize with a falling edge or a rising edge of the first clock signal based on an assert signal that is output when the number of clock pulses of the second clock signal counted by the counting unit reaches a predetermined value.2. The clock generator as claimed in claim 1 , further comprising:a system clock counting unit configured to count a number of clock pulses of the system clock signal in a cycle of the second clock signal,wherein when a last clock pulse of the second clock signal is generated immediately before the falling edge or the rising edge of the first clock signal, the adjusting unit causes the system clock counting unit to not count the number ...

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19-09-2013 дата публикации

PSEUDO-STATIC DOMINO LOGIC CIRCUIT AND APPARATUSES INCLUDING SAME

Номер: US20130246834A1
Принадлежит:

A domino logic circuit includes a plurality of domino logic stages connected in series between a latch and a flip-flop and a clock signal generator generating a clock signal having a first duty cycle and a flip-flop clock signal having a second duty cycle. The latch and the domino logic stages respectively operate in response to a domino clock signals derived from the first clock signal. The flip-flop operates in response to the flip-flop clock signal. 1. A domino logic circuit comprising:a plurality of domino logic stages connected in series between a latch and a flip-flop; anda clock signal generator that generates a clock signal having a first duty cycle and a flip-flop clock signal having a second duty cycle different from the first duty cycle,wherein the latch and each one of the plurality of domino logic stages respectively operates in response to one of a plurality of domino clock signals related to the clock signal, and the flip-flop operates in response to the flip-flop clock signal.2. The domino logic circuit of claim 1 , wherein the first duty cycle is greater than the second duty cycle.3. The domino logic circuit of claim 1 , further comprising:an inverter chain that receives the clock signal and includes a plurality of inverters connected in series such that the plurality of domino clock signals are alternatingly provided by the inverter chain as the clock signal and an inverted clock signal,wherein each one of the plurality of domino logic stages comprises a dynamic node including at least one transistor having a gate receiving one of the plurality of domino clock signals and being connected to a power supply node, and a logic network connected between the dynamic node and another power supply node, the logic network being configured to determine a logic level for the dynamic node in response to an output signal and at least one input data signal.4. The domino logic circuit of claim 3 , wherein the plurality of domino logic stages comprises a first odd ...

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19-09-2013 дата публикации

COMMAND DECODING METHOD AND CIRCUIT OF THE SAME

Номер: US20130246836A1
Автор: Lin Yung-Feng
Принадлежит: MACRONIX INTERNATIONAL CO., LTD.

A decoding circuit includes a pre-trigger signal generating unit, a comparing unit, and a starting signal generating unit. The pre-trigger signal generating unit receives the former encoded data and generates a pre-trigger signal when the former encoded data of the received command matches the corresponding former encoded data of a predetermined command. The comparing unit generates a match signal when the latter encoded data of the received command is the same with the latter encoded data of the predetermined command. The starting signal generating unit outputs a starting signal according to the pre-trigger signal and the match signal. The starting signal starts a corresponding operation of the predetermined command. 1. A decoding circuit for decoding a received command , the received command being transmitted during at least two clock periods of a clock signal , the received command being divided to a former encoded data and a latter encoded data , the decoding circuit comprising:a pre-trigger signal generating unit for receiving the former encoded data of the received command and generating a pre-trigger signal wherein the pre-trigger signal is generated before receiving the latter encoded data.2. The decoding circuit for decoding the command according to claim 1 , wherein the pre-trigger signal is generated when the former encoded data of the received command matches the corresponding former encoded data of a predetermined command.3. The decoding circuit according to claim 2 , wherein the decoding circuit is for use in a memory claim 2 , and the predetermined command is for reading identification-related information of the memory.4. The decoding circuit for decoding the command according to claim 2 , further comprising:a comparing unit, for generating a match signal when the latter encoded data of the received command is the same with the latter encoded data of the predetermined command; anda starting signal generating unit, for outputting an starting signal ...

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26-09-2013 дата публикации

CLOCK GENERATION FOR TIMING COMMUNICATIONS WITH RANKS OF MEMORY DEVICES

Номер: US20130254585A1
Принадлежит: RAMBUS INC.

A memory controller includes a clock generator to generate a first clock signal and a timing circuit to generate a second clock signal from the first clock signal. The second clock signal times communications with any of a plurality of memory devices in respective ranks, including a first memory device in a first rank and a second memory device in a second rank. The timing circuit is configured to adjust a phase of the first clock signal, when the memory controller is communicating with the second memory device, based on calibration data associated with the second memory device and timing adjustment data associated with feedback from at least the first memory device. 140.-. (canceled)41. A memory controller to control a plurality of memory devices in respective ranks , including a first memory device in a first rank and a second memory device in a second rank , comprising:a clock generator to generate a first clock signal; anda timing circuit to generate a second clock signal to time communications with the second memory device, the timing circuit to generate the second clock signal by adjusting a phase of the first clock signal based on calibration data associated with the second memory device and feedback from at least the first memory device.42. The memory controller of claim 41 , wherein the feedback is from both the first memory device and the second memory device.43. The memory controller of claim 41 , wherein the memory controller includes edge tracking circuitry to generate timing adjustment data associated with respective memory devices based on feedback from the respective memory devices claim 41 , the timing adjustment data associated with the second memory device to be used to update the calibration data associated with the second memory device.44. The memory controller of claim 41 , wherein the timing circuit comprises:a first phase adjuster to adjust the phase of the first clock signal; anda plurality of respective storage elements, each to store ...

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03-10-2013 дата публикации

LAYER-ID DETECTOR FOR MULTILAYER 3D-IC AND METHOD OF THE SAME

Номер: US20130257503A1
Принадлежит: National Tsing Hua University

A layer-ID detector for multilayer 3D-IC, including a random generator to generate a random signal, a layer-ID designation mechanism circuit coupled to the random generator to generate a layer-ID designating signal, and a counter coupled to the layer-ID designating signal to output a layer-ID signal. 1. A layer-ID detector for multilayer 3D-IC , comprising:a random generator to generate a random signal;a layer-ID designation mechanism circuit coupled to said random generator to generate a layer-ID designating signal; anda counter coupled to said layer-ID designating signal to output a layer-ID signal.2. The detector of claim 1 , wherein said layer-ID designation mechanism circuit comprises:a first flipflop, an output of said random generator being coupled to an input end of said first flipflop, a clock (CK) end of said first flipflop being coupled to an output end of a first AND gate.3. The detector of claim 2 , wherein said layer-ID designation mechanism circuit further comprises:a first input end of said first AND gate being coupled to a clock signal, an output end of said first flipflop being coupled to a first input end of a second AND gate.4. The detector of claim 3 , wherein said layer-ID designation mechanism circuit further comprises:a second input end of said second AND gate being coupled to an output end of a second flipflop, a reset end of said second flipflop being coupled to a reset signal.5. The detector of claim 4 , wherein said layer-ID designation mechanism circuit further comprises:an output of said second AND gate being coupled to a first input end of a third AND gate and a second input end of said first AND gate.6. The detector of claim 5 , wherein said layer-ID designation mechanism circuit further comprises:{'sub': 'EN', 'a common end of said output of said second AND gate and said second input end of said first AND gate being coupled to a Vinput end (negative input end) of an operational amplifier.'}7. The detector of claim 6 , wherein said ...

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03-10-2013 дата публикации

System-on-chip, electronic system including same, and method controlling same

Номер: US20130262894A1
Принадлежит: SAMSUNG ELECTRONICS CO LTD

A system-on-chip (SoC) operates with a memory device and includes a performance monitoring unit (PMU) that measures memory usage for the memory device, and a central processing unit (CPU) configured to implement a dynamic voltage frequency scaling (DVFS) controller that compares the memory usage during a performance monitoring period with a reference value and selects a control scheme accordingly.

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03-10-2013 дата публикации

PROCESSING DEVICE AND METHOD FOR CONTROLLING PROCESSING DEVICE

Номер: US20130262908A1
Автор: GOMYO Norihito
Принадлежит: FUJITSU LIMITED

A processing device includes: a clock generating circuit that outputs a clock; an instruction executing circuit that is capable of a state change between an instruction executing state where an instruction is executed and an instruction stop state where an instruction is stopped; a first circuit that inhibits the supply of the clock to an internal circuit when a first clock inhibition signal is input; a second circuit that inhibits the supply of the clock to an internal circuit when a second clock inhibition signal is input; and a control circuit, and the control circuit outputs the second clock inhibition signal to the second circuit after outputting the first clock inhibition signal to the first circuit, when the instruction executing circuit changes from the instruction executing state to the instruction stop state. 1. A processing device comprising:a clock generating circuit that outputs a clock;an instruction executing circuit that is capable of a state change between an instruction executing state where an instruction is executed and an instruction stop state where an instruction is stopped;a first circuit that inhibits the supply of the clock to a first internal circuit built in the first circuit when a first clock inhibition signal is input;a second circuit that inhibits the supply of the clock to a second internal circuit built in the second circuit when a second clock inhibition signal is input; anda control circuit that outputs the second clock inhibition signal to the second circuit after outputting the first clock inhibition signal to the first circuit, when the instruction executing circuit changes from the instruction executing state to the instruction stop state.2. The processing device according to claim 1 , wherein:the first circuit further continues the supply of the clock to the first internal circuit irrespective of the first clock inhibition signal, when a first clock continuation signal is input;the second circuit further continues the supply ...

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03-10-2013 дата публикации

CLOCK RECOVERY, RECEIVER, AND COMMUNICATION SYSTEM FOR MULTIPLE CHANNELS

Номер: US20130262909A1
Принадлежит:

Disclosed are various exemplary embodiments of a clock recovery apparatus for recovering clock signals of multiple data channels. In one exemplary embodiment a clock recovery apparatus for a plurality of data channels may include a plurality of channel blocks, where each channel block may include a frequency detection block configured to generate an intermediate signal based on a respective data signal received from a respective data channel and a global signal, and a recovery block configured to recover a clock signal for the respective data channel in response to the respective data signal and the global signal. The apparatus may also include a global signal generation block configured to receive and combine the intermediate signals from the plurality of channel blocks to generate the global signal. 1. A clock recovery apparatus for a plurality of data channels , the apparatus comprising: a frequency detection block configured to generate an intermediate signal based on a respective data signal received from a respective data channel and a global signal; and', 'a recovery block configured to recover a clock signal for the respective data channel in response to the respective, data signal and the global signal; and, 'a plurality of channel blocks, each channel block comprisinga global signal generation block configured to receive and combine the intermediate signals from the plurality of channel blocks to generate the global signal.2. The apparatus of claim 1 , wherein the frequency detection block in each channel block comprises:a reference signal generator configured to generate a reference signal based on the respective data signal;a feedback signal generator configured to generate a feedback signal based on the global signal; anda frequency detector configured to generate the intermediate signal representing a frequency difference between the reference signal and the feedback signal.3. The apparatus of claim 2 , wherein:the reference signal generator in each ...

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17-10-2013 дата публикации

Method and system for operating accessory in terminal and terminal supporting the same

Номер: US20130275633A1
Автор: Kiwook HAN
Принадлежит: SAMSUNG ELECTRONICS CO LTD

A method and a system for operating an accessory in a terminal capable of variously differentiating key input signals transceived between a portable terminal and an accessory, and a terminal supporting the same, are provided. The system for operating an accessory device in a terminal includes the terminal including a Universal Serial Bus (USB) port and an ear jack port, and the accessory device configured to simultaneously connect with the USB port and the ear jack port of the terminal, and to transfer a signal corresponding to a key input signal to the terminal through the USB port and the ear jack port.

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17-10-2013 дата публикации

SEMICONDUCTOR DEVICE, CONTROL METHOD FOR THE SEMICONDUCTOR DEVICE AND INFORMATION PROCESSING SYSTEM INCLUDING THE SAME

Номер: US20130275798A1
Принадлежит:

The core chips each include a timing control circuit that outputs a timing signal synchronized with the outputting of parallel data to the interface chip. The interface chip includes a data input circuit that captures parallel data in synchronization with the timing signal. With this arrangement, the timing to output the parallel data and the timing to capture the parallel data are both synchronized with the timing signal generated in the core chips. Therefore, even if there is a difference in operation speed between each core chip and the interface chip, the parallel data can be accurately captured on the interface chip side. 1. A device comprising: a plurality of first terminals;', 'a plurality of second terminals;', 'a plurality of first memory blocks each including a plurality of first memory cells, each of the first memory blocks being configured to be accessed to produce first data;', 'a plurality of first circuits each producing a first output timing control signal;', 'a plurality of first buffers each coupled to an associated one of the first terminals, an associated one of the first memory blocks and an associated one of the first circuits and configured to respond to the first output timing control signal produced from the associated one of the first circuits to drive the associated one of the first terminals in accordance with the first data produced from the associated one of the first memory blocks; and', 'a plurality of second buffers each coupled to an associated one of the second terminals and an associated one of the first circuits and configured to respond to the first output timing control signal produced from the associated one of the first circuits to drive the associated one of the second terminals;, 'a first semiconductor chip that comprises a plurality of first through-vias each penetrating the second semiconductor chip and having first and second ends;', 'a plurality of second through-vias each penetrating the second semiconductor chip and ...

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17-10-2013 дата публикации

CIRCUIT, SYSTEM AND METHOD FOR SELECTIVELY TURNING OFF INTERNAL CLOCK DRIVERS

Номер: US20130275799A1
Автор: Raad George B.
Принадлежит:

The present invention includes a circuit, system and method for selectively turning off internal clock drivers to reduce operating current. The present invention may be used to reduce power consumption by reducing operating current in a memory device. Operating current may be reduced by turning off internal clock drivers that deliver a clock signal during selected periods of time. According to an embodiment of clock control circuitry of the present invention, an internal clock is disabled if a no operation command is detected during periods of time when no read or write burst operation is taking place. Methods, memory devices and computer systems including the clock control circuitry and its functionality are also disclosed. 1a memory array; and command detection circuitry configured to generate a gating signal indicating idle time in a memory device based on command signal input to the memory device; and', 'clock gating circuitry coupled to said command detection circuitry for receiving said system clock and for selectively gating said system clock in response to said gating signal., 'clock control circuitry in communication with said memory array and for receiving a system clock, said clock control circuitry comprising. A memory device, comprising: This application is a continuation of U.S. application Ser. No. 12/652,897, filed Jan. 6, 2010, which is a continuation of U.S. application Ser. No. 11/449,499, filed Jun. 7, 2006, now U.S. Pat. No. 7,669,068, issued Feb. 23, 2010, which is a continuation of U.S. application Ser. No. 10/179,882, filed Jun. 25, 2002, now U.S. Pat. No. 7,089,438, issued Aug. 8, 2006. The entire teachings of the above applications are incorporated herein by reference.There are many reasons why reducing operating current in digital electronics, especially computer systems, is desirable. Portable computer systems, for example, rely on battery power when not plugged into a recharger. By reducing power consumption, batteries will last longer ...

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24-10-2013 дата публикации

Color Calibration System for a Video Display

Номер: US20130278932A1
Принадлежит: BARCO, INC.

Large digital displays for entertainment, architectural and advertising displays have interconnected display panels with pluralities of light emitting elements. To solve calibration problems, each of the display panels stores measured luminance and chromaticity data for each of the light emitting elements of the panel. The luminance data is independent of the chromaticity data. A central controller can then perform calibration procedures so that the light emitting elements are matched across the entire display.

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31-10-2013 дата публикации

ARITHMETIC PROCESSING DEVICE, METHOD FOR CONTROLLING ARITHMETIC PROCESSING DEVICE, AND SYSTEM

Номер: US20130290768A1
Автор: Kitamura Yasuhiro
Принадлежит: FUJITSU LIMITED

An arithmetic processing device includes: a communicating unit that communicates with another arithmetic processing device; a clock controller that requests a change in the frequency of a clock signal; a sequence controller that instructs the other arithmetic processing device to change the amount of data to be transmitted by the other arithmetic processing device to the arithmetic processing device per unit time when the sequence controller is requested by the clock controller to change the frequency of the clock signal; and a control circuit that changes the amount of data to be transmitted by the communicating unit to the other arithmetic processing device per unit time when the other arithmetic processing device instructs the arithmetic processing device to change the amount of data to be transmitted by the arithmetic processing device to the other arithmetic processing device per unit time. 1. An arithmetic processing device comprising:a communicating unit that communicates with another arithmetic processing device;a clock controller that requests a change in the frequency of a clock signal;a sequence controller that instructs the other arithmetic processing device to change the amount of data to be transmitted by the other arithmetic processing device to the arithmetic processing device per unit time when the sequence controller is requested by the clock controller to change the frequency of the clock signal; anda control circuit that changes the amount of data to be transmitted by the communicating unit to the other arithmetic processing device per unit time when the other arithmetic processing device instructs the arithmetic processing device to change the amount of data to be transmitted by the arithmetic processing device to the other arithmetic processing device per unit time.2. The arithmetic processing device according to claim 1 ,wherein when the clock controller requests a reduction in the frequency of the clock signal, the sequence controller ...

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07-11-2013 дата публикации

CONTROL SYSTEM

Номер: US20130297953A1
Автор: Hayashi Masakazu
Принадлежит: NEC CASIO MOBILE COMMUNICATIONS, LTD.

If switching function occurs in such a manner that the frequency of a clock signal supplied from clock supply section (), that supplies the clock signal having the highest frequency in frequencies corresponding to functions with which CPU () is provided, to CPU () for the latter function is lower than that for the former function, after the frequency of the clock signal for the latter function has been set up, said power supply unit () supplies the power voltage corresponding to the changed frequency to CPU (). If switching function occurs in such a manner that the frequency of the clock signal supplied from clock supply section () for the latter function is higher than that for the former function, after the voltage supplied from power supply unit () has been changed, clock supply section () supplies the clock signal having the frequency corresponding to the latter function. 1. A control system , comprising:a power supply unit that supplies a plurality of power voltages; anda control unit connected to the power supply unit and a CPU,wherein said control unit includes:a storage section that correlatively stores power voltages and frequencies of a clock signal that a plurality of functions with which said CPU is provided need;a power supply control section that causes said power supply unit to supply the highest power voltage from among those power voltages corresponding to functions that operate in said plurality of functions stored in said storage section; anda clock supply section that supplies the clock signal having the highest frequency from among those frequencies corresponding to functions that operate in said plurality of functions stored in said storage section,wherein said power supply unit includes:a power supply section that supplies the power voltage specified by said power supply control section to said CPU; andan interrupt notification section that notifies said control unit that the power voltage supplied from said power supply section has changed, ...

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07-11-2013 дата публикации

Systems And Methods For DQS Gating

Номер: US20130297961A1
Принадлежит:

Systems and methods for timing read operations with a memory device are provided. A timing signal is received from the memory device at a gating circuit. The timing signal is passed through as a filtered timing signal during a gating window. The gating window is configured to open the gating window based on a control signal and to close the gating window based on a falling edge of the timing signal. The falling edge is determined based on a counter that is triggered to begin counting by the control signal. The control signal is generated at a timing control circuit after receiving a read request from a memory controller. The timing control circuit is configured to delay generation of the control signal to cause the gating window to open during a preamble portion of the timing signal.

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07-11-2013 дата публикации

BRIDGE DEVICE

Номер: US20130297962A1
Принадлежит:

A clock generator is provided. The clock generator includes a crystal oscillator, an inverter coupled to the crystal oscillator in parallel, a first circuit and a second circuit. The crystal oscillator has a first terminal and a second terminal The inverter generates a first signal and a second signal at the first and second terminals of the crystal oscillator, respectively. The first circuit coupled to the first terminal of the crystal oscillator generates a first clock signal with a constant frequency according to the first signal. The second circuit coupled to the second terminal of the crystal oscillator generates a second clock signal with a variable frequency according to the second signal. 1. A bridge device providing data transfer between a PCIE standard and a USB standard , comprising:a clock generator, comprising:a crystal oscillator, having a first terminal and a second terminal;an inverter coupled to the crystal oscillator in parallel, generating a first signal and a second signal at the first and second terminals of the crystal oscillator, respectively;a first circuit coupled to the first terminal of the crystal oscillator, generating a first clock signal with a constant frequency according to the first signal; anda second circuit coupled to the second terminal of the crystal oscillator, generating a second clock signal with a variable frequency according to the second signal.a PCIE module coupled to the clock generator; anda USB module coupled to the PCIE module, and performing data transfer complying with the USB standard according to the first clock signal and the second clock signal.2. The bridge device as claimed in claim 1 , wherein the first circuit is a phase locked loop circuit and the second circuit is a spread spectrum clock generator.3. The bridge device as claimed in claim 1 , wherein the second circuit provides the second clock signal to the USB module for performing SuperSpeed data transfer.4. The bridge device as claimed in claim 3 , ...

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14-11-2013 дата публикации

SYSTEM ON CHIP (SOC), METHOD OF OPERATING THE SOC, AND SYSTEM HAVING THE SOC

Номер: US20130305078A1
Принадлежит:

A data processing system, comprising: a PLL configured to receive a reference clock and to generate a common clock; a processing unit configured to output an operation condition data based on one of temperature, voltage, or process information; and at least two data processing circuits, each comprising: a first clock signal generator configured to receive the common clock signal, the first clock signal generator having a first clock latency adjusting circuit configured to adjust clock signal propagation delay based on the operation condition data; and a second clock signal generator configured to receive the common clock signal, the second clock signal generator having a second clock latency adjusting circuit configured to adjust clock signal propagation delay based on the operation condition data. 1. A data processing system , comprising:at least two data processing circuits, each comprising:a first clock signal generator having a first clock latency adjusting circuit configured to adjust clock signal propagation delay based on operation condition data; anda second clock signal generator having a second clock latency adjusting circuit configured to adjust clock signal propagation delay based on the operation condition data,wherein the first clock signal generator and the second clock signal generator receive a common clock signal.2. The system of claim 1 , wherein the first or second clock latency adjusting circuit comprises a plurality of selectable delay paths claim 1 , each path is configured to provide a different amount of delay from another path.3. The system of claim 2 , wherein one of the at least two data processing circuits is provided power from a first power domain and another data processing circuit is provided power from a second power domain different from the first power domain.4. The system of claim 1 , wherein the one of the at least two data processing circuits is configured with a reset controlled independently from a reset of another data ...

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21-11-2013 дата публикации

Providing Adaptive Frequency Control For A Processor

Номер: US20130311815A1
Автор: Werner James B.
Принадлежит:

In one embodiment, the present invention includes a method for receiving utilization data from thread units of one or more processor cores, determining an operating frequency for a core clock signal based on the utilization data, a target utilization value, and an operating mode of the processor, and generating the core clock signal based on the determined operating frequency. Other embodiments are described and claimed. 1at least first and second thread units each including a first counter to provide a first count value and a second counter to provide a second count value, wherein the first counter and the second counter are to run at a first core clock frequency, the first count value corresponding to a number of total clock cycles and the second count value corresponding to a number of active clock cycles; anda controller coupled to the at least first and second thread units to receive the first and second count values and to calculate a utilization value for each of the first and second thread units based thereon, and to determine a ratio used to set a core clock frequency based at least in part on the utilization values, a target utilization value, and a current ratio.. A processor comprising: This application is a continuation of U.S. patent application Ser. No. 12/545,937, filed Aug. 24, 2009, the content of which is hereby incorporated by reference.In modern processors, power consumption is in direction proportion to the frequency at which a processor (or core) operates. Reducing consumption thus can be achieved by reducing core frequency such that frequency control provides a means to control processor power consumption. However, that reduction unconditionally applied would result in degraded system performance.In contrast, when a processor (or core) runs at a fixed frequency, it uses more power than necessary while running at reduced loads, where its utilization is less than 100%. Thus many systems provide some type of frequency control. Typically, ...

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21-11-2013 дата публикации

CIRCUIT AND METHOD FOR CONTROLLABLY DELAYING AN INPUT SIGNAL, AND MICROSCOPE, AND METHOD FOR CONTROLLING A MICROSCOPE

Номер: US20130311816A1
Автор: KOESTER Thorsten
Принадлежит: Leica Microsystems CMS GmbH

A circuit for delaying an input signal includes first and second delay units. The input signal is switched to the first delay unit which is configured to delay the input signal by k cycles of a first clock signal so as to generate a value xand transfer the input signal to the second delay unit. The second delay unit includes a converter and a second shift register. The converter is connected to the second shift register by n leads. The value xand a value xare present at the converter, where xis the input signal delayed by k− cycles of the first clock signal, The converter is configured such that the value xis present on leads 1 to m and the value xis present on leads m+1 to n. The second shift register is configured to successively output values present on leads 1 to n. 1. A circuit for controllably delaying an input signal , the circuit comprising:{'sub': t', {'sub2': '—'}, 'k, 'a first delay unit and a second delay unit, the input signal being switched to the first delay unit which is configured to delay the input signal by k cycles of a first clock signal so as to generate a value x, and transfer the input signal to the second delay unit,'}wherein the second delay unit comprises a converter and a second shift register, the converter being connected to the second shift register by n leads,{'sub': t', {'sub2': '—'}, 'k', 't', {'sub2': '—'}, 'k−1', 't', {'sub2': '—'}, 'k−1, 'wherein the value xand a value xare present at the converter, xbeing the input signal delayed by k−1 cycles of the first clock signal,'}{'sub': t', {'sub2': '—'}, 'k−1', 't', {'sub2': '—'}, 'k', 't', {'sub2': '—'}, 'k−1', 't', {'sub2': '—'}, 'k, 'wherein the converter is configured such that the value xis present on leads 1 to m and the value xis present on leads m+1 to n, where 1≦m≦n−1, or such that the value xor xis present at all leads 1 to n, and'}wherein the second shift register is configured to successively output values present on leads 1 to n as an output signal of the circuit.2. The ...

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21-11-2013 дата публикации

SCALABLE, COMMON REFERENCE-CLOCKING ARCHITECTURE USING A SEPARATE, SINGLE CLOCK SOURCE FOR BLADE AND RACK SERVERS

Номер: US20130311817A1
Автор: Huang Choupin, Kim Inho
Принадлежит:

Scalable, common reference-clocking architecture and method for blade and rack servers. A common reference clock source is configured to provide synchronized clock input signals to a plurality of blades in a blade server or servers in a rack server. The reference clock signals are then used for clock operations related to serial interconnect links between blades and/or servers, such as QuickPath Interconnect (QPI) links or PCIe links. The serial interconnect links may be routed via electrical or optical cables between blades or servers. The common reference clock input and inter-blade or inter-server interconnect scheme is scalable, such that the plurality of blades or servers can be linked together in communication. Moreover, when QPI links are used, coherent memory transactions across blades or servers are provided, enabling fine grained parallelism to be used for parallel processing applications. 1. A system , comprising:a plurality of server blades or servers, each having an external reference clock signal input port and at least one link interconnect interface;a clock synthesizer board, configured to generate a plurality of common reference clock signals at a plurality of output connectors;a plurality of reference clock signal cables, each coupled between a respective output connector on the clock synthesizer board and an input port on a respective server blade or server; anda plurality of interconnect link cables coupled at opposing ends to the link interconnect interfaces and linking the plurality of server blades or servers in communication,wherein, during operation of the system, the common reference clock signals are used as interconnect system clock inputs to facilitate communication between the server blades or servers over the plurality of interconnect link cables.2. The system of claim 1 , wherein at least one of the interconnect links comprises a QuickPath Interconnect (QPI) link.3. The system of claim 1 , wherein at least one of the interconnect link ...

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21-11-2013 дата публикации

METHODS AND APPARATUSES FOR MASTER-SLAVE DETECTION

Номер: US20130311818A1
Принадлежит: MICRON TECHNOLOGY, INC.

Apparatuses, master-slave detect circuits, memories, and methods are disclosed. One such method includes performing a master detect phase during which a memory unit in a memory group is determined to be a master memory unit, determining at each memory unit its location relative to other memory units, and determining at each memory unit its location in the memory group based on a total number of slave memory units and its location relative to other memory units. 1. An apparatus , comprising: first circuitry configured to provide a first signal indicative of a number of memory units between the memory unit and an end of the memory group;', 'second circuitry configured to provide a second signal indicative of a total number of memory units in the memory group; and', 'a comparator unit coupled to the first and second circuitry and configured to compare the first and second signals and provide a location count signal based at least in part on the comparison, the location count signal indicative of a location of the memory unit in the memory group., 'a memory unit of a memory group comprising2. The apparatus of claim 1 , wherein the first circuitry comprises:a pulse generator coupled to a first memory unit input and to a second memory unit output, the pulse generator configured to provide a pulse to the second memory unit output responsive to each pulse received from the first memory unit input, the pulse generator further configured to provide a pulse to the second memory unit output responsive to each pulse provided to a first memory unit output; anda counter coupled to the first memory unit input and configured to count a number of pulses received from the first memory unit input, wherein the first signal includes the count of the number of pulses received via the first memory unit input.3. The apparatus of claim 2 , wherein the pulse generator is coupled to the first memory unit input via a pulse delay claim 2 , the pulse delay configured to delay pulses received from ...

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21-11-2013 дата публикации

CONTROLLER

Номер: US20130311819A1
Принадлежит: Panasonic Corporation

This controller is used in a system in which initiators and targets are connected via distributed buses to control transmission timing of an access request received from the initiators. The controller stores intermittent information including information about an intermittent period in which interference between packets can be restricted and bus operating frequency information indicating a bus operating frequency at which real-time performance is guaranteed for each initiator and which has been generated based on system configuration information and flow configuration information indicating, on a flow basis, a specification required for each initiator to access the target. The controller includes a clock generator; communications circuitry; and transmission interval setting circuitry which sets a time to send transmission permission responsive to a transmission request based on the intermittent period, a time when the transmission request is detected, and a previous transmission time. 1. A controller for use in a system in which initiators and targets are connected together via distributed buses to control transmission timing of an access request that has been received from any of the initiators through the buses , the controller comprising:an intermittent information storage configured to store intermittent period information that has been generated based on system configuration information about the system's configuration and flow configuration information indicating, on a flow basis, a specification required for each said initiator to access one of the targets;communications circuitry configured to obtain a clock signal to be driven at a bus operating frequency that guarantees real-time performance for each said initiator and that has been generated based on the system configuration information and the flow configuration information, configured to packetize data supplied from the initiator, configured to send a packet to a router and configured to record a ...

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28-11-2013 дата публикации

Frequency Synthesizer with Zero Deterministic Jitter

Номер: US20130314130A1
Принадлежит: Individual

A frequency synthesizer system may generate two intermediate clock signals, each intermediate clock signal having the same nominal frequency (f N ), the same cycle pattern with deterministic jitter, and the same corresponding average frequency (f A ). However, the cycle pattern in one intermediate clock signal may be a specified number (N) of cycles out of phase with respect to the cycle pattern in the other intermediate clock signal. The cycle pattern may recur every 2N cycles in each intermediate clock signal. The duration of each cycle in each of the two intermediate clock signals is defined by f N and the deterministic jitter in the cycle pattern. An output clock signal may be generated by phase interpolating by two (2) the two intermediate clock signals, and dividing the resulting phase interpolated clock signal by N. The resulting output clock signal has an accurate frequency commensurate with f A /N, and is free of deterministic jitter.

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28-11-2013 дата публикации

BRIDGING DEVICE HAVING A FREQUENCY CONFIGURABLE CLOCK DOMAIN

Номер: US20130318287A1
Принадлежит: MOSAID TECHNOLOGIES INCORPORATED

A composite memory device including discrete memory devices and a bridge device for controlling the discrete memory devices. A configurable clock controller receives a system clock and generates a memory clock having a frequency that is a predetermined ratio of the system clock. The system clock frequency is dynamically variable between a maximum and a minimum value, and the ratio of the memory clock frequency relative to the system clock frequency is set by loading a frequency register with a Frequency Divide Ratio (FDR) code any time during operation of the composite memory device. In response to the FDR code, the configurable clock controller changes the memory clock frequency. 1. A method for controlling a selected memory device of a plurality of discrete memory devices , comprising:receiving a global command synchronously with a system clock;generating a memory clock using one of at least two clock divide ratios of the system clock;converting the global command into a local command to be synchronized with the memory clock; andissuing the local command from one of a plurality of sets of dedicated local input/outputs to the selected memory device.2. The method of claim 1 , further including receiving information at the one of the plurality of sets of dedicated local input/outputs from the selected memory device.3. The method of claim 2 , wherein receiving information includes receiving and storing read data in memory from the selected memory device in response to the local command executed by the selected memory device.4. The method of claim 3 , wherein receiving and storing read data includes providing the read data at a first data rate corresponding to a frequency of the memory clock for writing to the memory.5. The method of claim 4 , further including providing the read data from the memory at a second data rate corresponding to a frequency of the system clock.6. The method of claim 1 , further including receiving and storing write data in memory after ...

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05-12-2013 дата публикации

DETERMINISTIC CLOCK CROSSING

Номер: US20130326205A1
Принадлежит:

Techniques and apparatuses for clock crossing. A reset circuit on a first die generates a forwarded FIFO reset signal synchronous to a reference clock that identifies a single edge. A clock generation circuit on the first die generates the reference clock signal. Control circuitry on the first die generates a forwarded signal, synchronous to the forwarded clock that identifies a forwarded clock edge with fixed timing relationship to the forwarded clock edge a transmit PLL locks to the single reference edge. A phase locked loop (PLL) on a second die is coupled to receive the reference clock signal, the PLL to generate a local clock signal. A circular FIFO with a write pointer advanced by the forwarded clock and a read pointer advanced by the local clock. 1. An apparatus comprising:a reset circuit on a first die to generate a forwarded FIFO reset signal synchronous to a reference clock which identifies a single edge;a clock generation circuit on the transmitter die to generate the reference clock signal;control circuitry on the first die to generate a forwarded signal, synchronous to the forwarded clock which identifies a forwarded clock edge with fixed timing relationship to the forwarded clock edge a transmit PLL locks to the single reference edge;a phase locked loop (PLL) on a second die coupled to receive the reference clock signal, the PLL to generate a local clock signal; anda circular FIFO with a write pointer advanced by the forwarded clock and a read pointer advanced by the local clock.2. The apparatus of claim 1 , wherein the write pointer is initialized by the forwarded signal and the read pointer are initialized by the local clock edge compared to the reference clock edge by the PLL.3. The apparatus of further comprising:a first set of single-ended transmitter circuits on the first die to transmit one or more of the reset signal, the reference clock signal, the clock signal and the valid signal;a first set of single-ended receiver circuits on the second ...

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05-12-2013 дата публикации

Predicting Timing Violations

Номер: US20130326258A1
Принадлежит: Utah State University

For predicting timing violations, a prediction module predicts a timing violation for a first instruction in a semiconductor device in response to use by the first instruction of a specified sensitized path. The prediction module further mitigates the predicted timing violation. 1. A method comprising:predicting a timing violation for a first instruction in a semiconductor device in response to use by the first instruction of a specified sensitized path; andmitigating the predicted timing violation.2. The method of claim 1 , wherein the timing violation is further predicted in response to an environmental condition and the use by the first instruction of the specified sensitized path.3. The method of claim 2 , wherein the environmental condition comprises a supply voltage falling below a voltage threshold.4. The method of claim 2 , wherein the environmental condition comprises a temperature exceeding a temperature threshold.5. The method of claim 1 , wherein the sensitized path is identified for a specified instruction set of a functional unit selected from the group consisting of an arithmetic logic unit (ALU) claim 1 , an instruction scheduler claim 1 , a load address generator claim 1 , a memory address generator claim 1 , and forward check logic.6. The method of claim 5 , wherein benchmark instructions that are most frequently executed by the functional unit are selected as the specified instruction set.7. The method of claim 5 , wherein the sensitized path is selected from an architectural simulation of the specified instruction set.8. The method of claim 5 , wherein the sensitized path is selected from an architectural simulation of the specified instruction set.9. The method of claim 1 , wherein the timing violation is mitigated by adding at least one instruction cycle for the first instruction.10. The method of claim 9 , further comprising delaying a tag broadcast for the at least one instruction cycle in response to predicting the timing failure.11. The ...

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12-12-2013 дата публикации

ACTIVE FUNCTIONAL LIMITING OF A MICROCONTROLLER

Номер: US20130332046A1
Принадлежит: ROBERT BOSCH GMBH

A microcontroller for use in a control device for an internal combustion engine includes: an analysis access via which internal data in the microcontroller can be accessed from outside the microcontroller; a clock generator which generates clock timing for data communication of the microcontroller with other units. The microcontroller is configured to change over from a first clock to a second clock when there is an access to the microcontroller via the analysis access. 1. A microcontroller for a control device of an internal combustion engine , comprising:an analysis access via which internal data in the microcontroller are accessed from outside the microcontroller; andat least one clock generating unit which generates at least one clock for data communication of the microcontroller with other units;wherein the microcontroller is configured to change over from a first clock to a second clock which differs from the first clock, when an access to the microcontroller via the analysis access occurs.2. The microcontroller as recited in claim 1 , wherein at least one of:the first clock is a highly precise clock generated with an external quartz crystal and internal phase-locked loop; andthe second clock is less precise than the first clock, the second clock being generated as a result of a changeover to one of an uncalibrated internal RC oscillator or a pseudorandom clock generator.3. The microcontroller as recited in claim 2 , wherein:when an access to the microcontroller via the analysis access occurs, a marker is irrevocably set in the microcontroller and causes the changeover to the second clock.4. The microcontroller as recited in claim 3 , wherein the access to the microcontroller via the analysis access is protected by a password claim 3 , and wherein an inputting of the password causes the setting of the marker.5. The microcontroller as recited in claim 3 , wherein the second clock prevents a communication between the control device and another unit in the ...

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12-12-2013 дата публикации

System and Method for Providing Input/Output Functionality to a Processing Node

Номер: US20130332719A1
Принадлежит: DELL PRODUCTS, LP

A remote component controller of a server rack includes a real time clock information unit to maintain real clock time and to respond to requests for real time clock information, and a communication module to receive over a communication link a request from a processing node of the server rack for real time clock information, to forward the request to the real time clock information unit, to receive from the real time clock information unit a response to the request, and to transmit the response to the request to the processing node over the communication link. 1. A remote component controller of a server rack , the remote component controller comprising:a real time clock information unit to maintain real clock time and to respond to requests for real time clock information; anda communication module to receive over a communication link a request from a processing node of the server rack for real time clock information, to forward the request to the real time clock information unit, to receive from the real time clock information unit a response to the request, and to transmit the response to the request to the processing node over the communication link.2. The remote component controller of claim 1 , wherein the communication link comprises a Peripheral Component Interconnect-Express (PCIe) link.3. The remote component controller of claim 2 , wherein the communication module includes a PCIe endpoint.4. The remote component controller of claim 1 , further comprising:a firmware component to store BIOS code for the processing nodes and to determine a BIOS code associated with for a first processing node based upon an identification of the first processing node;wherein the communication module is operable to receive over the communication link a request from the first processing node for the BIOS code, the request including an identification of the first processing node, to forward the request and the identification to the firmware component, to receive the BIOS code ...

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