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Небесная энциклопедия

Космические корабли и станции, автоматические КА и методы их проектирования, бортовые комплексы управления, системы и средства жизнеобеспечения, особенности технологии производства ракетно-космических систем

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Мониторинг СМИ

Мониторинг СМИ и социальных сетей. Сканирование интернета, новостных сайтов, специализированных контентных площадок на базе мессенджеров. Гибкие настройки фильтров и первоначальных источников.

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Поддерживает ввод нескольких поисковых фраз (по одной на строку). При поиске обеспечивает поддержку морфологии русского и английского языка
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Применить Всего найдено 15019. Отображено 100.
19-01-2012 дата публикации

Information Handling System with Processing System, Low-power Processing System and Shared Resources

Номер: US20120013795A1
Автор: Andrew T. Sultenfuss, Steven L. Belt
Принадлежит: Dell Products LP

An information handling system includes a processing system, a low-power processing system, and a chipset. The processing system is configured to operate using a power system configured to power a shared resource of the processing system and a non-shared resource of the processing system, and to disable the non-shared resource during a reduced operating state of the processing system. The low-power processing system is configured to access the shared resource of the processing system during operation of the low-power processing system, wherein the operation of the low-power processing system is separate from the operation of the processing system. The chipset includes a processor of the processing system and operable to be enabled during operation of the processing system, wherein the processor is configured to be disabled during operation of the low-power processing system.

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Номер записи: 1
02-02-2012 дата публикации

Method, Mobile Terminal and Computer Program Product for Sharing Storage Device

Номер: US20120030433A1
Автор: Chunhui Sun, Fuliang Zhang, Jinmei Yang, Wenying Shan
Принадлежит: Lenovo Beijing Ltd

The invention discloses a method of sharing a storage device and a mobile terminal. The mobile terminal comprises a first processor, a second processor and a readable and writable nonvolatile storage device. A processing capacity of the first processor is different from that of the second processor. A state in which the first processor is operating and using the storage device is a second state. A state in which the second processor is operating and using the storage device is a third state. The method comprising: the first processor receiving a switch instruction; the first processor controlling the storage device to enter the second state or the third state according to the switch instruction. As compared with the prior art, by controlling the sharing of the storage device by the first processor, the invention reduces the elements in the mobile terminal and saves the hardware cost of the mobile terminal; moreover, the physical connection between the components in the mobile terminal is simple and easily controlled.

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Номер записи: 2
09-02-2012 дата публикации

Computer system with enhanced user interface for images

Номер: US20120036438A1
Автор: Chris Guzak, Franc Camara, Michael G. Sheldon, Rajesh Ganesan, Todd Ouzts
Принадлежит: Microsoft Corp

A computer system and method are presented that enhance a user experience when viewing images displayed on the computer. The system includes a user interface for the computer that displays a number of thumbnail images that are small representations of image files existing on the computer. The thumbnail images are arranged in alignment with one another, such as at the bottom of a viewing window. An enlarged preview image is positioned adjacent the thumbnail images. The enlarged preview image corresponds to a selected thumbnail image and is a larger representation of an image file corresponding with the selected thumbnail image. A control is displayed in the window that enables the user to iterate through the thumbnail images in at least one direction. As the user iterates through the thumbnail images, the enlarged preview image changes correspondingly.

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Номер записи: 3
23-02-2012 дата публикации

Power Managers for an Integrated Circuit

Номер: US20120043812A1
Автор: Barry Alan Hoberman, Daniel L. Hillman, Jon Shiell
Принадлежит: Individual

A system for an integrated circuit comprising a plurality of power islands includes a first power manager and a second power manager. The first power manager manages a first power consumption for the integrated circuit based on needs and operation of the integrated circuit. The second power manager communicates with the first power manager and manages a second power consumption for one of the power islands.

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Номер записи: 4
23-02-2012 дата публикации

Fail safe adaptive voltage/frequency system

Номер: US20120044005A1
Автор: Chittoor Parthasarathy, Kallol Chatterjee, Nitin Chawla, Promod Kumar
Принадлежит: STMICROELECTRONICS PVT LTD

A system on chip (SoC) has a digital domain. An adaptive voltage/frequency scaling circuit includes a critical path replica circuit with respect to that digital domain. The critical path replica circuit generates a margin signal, and the adaptive voltage scaling circuit responds to the margin signal by decreasing bias voltage (and/or increasing clock frequency) applied to the digital domain of the system on chip so as to recover available margin. A fail-safe timing sensor is included within the digital domain of the system on chip. The timing sensor generates a flag signal when timing criteria within the digital domain are violated. The adaptive voltage scaling circuit responds to the flag signal by increasing the bias voltage (and/or decreasing the clock frequency) applied to the digital domain of the system on chip so as to implement a recovery operation.

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Номер записи: 5
01-03-2012 дата публикации

Electronic device with sleep mode and method for awaking electronic device

Номер: US20120054522A1
Автор: Bo-Ching Lin, Hsien-Chung Shih, Sha-Sha Hu, Yan-Xiang Huang, Yu-Liang Yang
Принадлежит: Hon Hai Precision Industry Co Ltd, Hongfujin Precision Industry Shenzhen Co Ltd

An electronic device with a sleep mode includes a CPU and a monitoring unit. The monitoring unit includes a testing module, a storage module, a comparing module, and a signal generating module. The CPU falls into standby mode when the electronic device is in the sleep mode. When the comparing module determines any one of one or more parameters of a battery which supplies power to the electronic device measured by the testing module is not within a corresponding predetermined range stored in the storage module, the signal generating module generates signals to awake the CPU. The awaked CPU executes protection operation to protect the electronic device. A related method is also provided.

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Номер записи: 6
22-03-2012 дата публикации

Systems and methods for optimizing the configuration of a set of performance scaling algorithms

Номер: US20120071216A1
Автор: Brian J. Salsbery, Norman S. Gargash
Принадлежит: Qualcomm Inc

Systems and methods for optimizing performance scaling algorithms designated for operation on a mobile device are disclosed. A system memory includes program, use case, and results stores in addition to test logic. The program store contains a set of programs defined by the combination of a performance scaling algorithm and a set of parameters. The use case store contains information that identifies expected tasks to be performed by end users of the mobile device over time. The results store organizes a respective merit value determined after each of the set of programs has been executed for tasks defined by each use case. When executed, the test logic adjusts the mobile device and associates a select program for each of the use cases in response to the stored merit values. The merit values are determined as a function of a performance metric and a power metric.

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Номер записи: 7
29-03-2012 дата публикации

Cache with Multiple Access Pipelines

Номер: US20120079204A1
Автор: Abhijeet Ashok Chachad, Jonathan (Son) Hung Tran, Raguram Damodaran, Sanjive Agarwala, Timothy David Anderson
Принадлежит: Texas Instruments Inc

Parallel pipelines are used to access a shared memory. The shared memory is accessed via a first pipeline by a processor to access cached data from the shared memory. The shared memory is accessed via a second pipeline by a memory access unit to access the shared memory. A first set of tags is maintained for use by the first pipeline to control access to the cache memory, while a second set of tags is maintained for use by the second pipeline to access the shared memory. Arbitrating for access to the cache memory for a transaction request in the first pipeline and for a transaction request in the second pipeline is performed after each pipeline has checked its respective set of tags.

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Номер записи: 8
29-03-2012 дата публикации

Providing per core voltage and frequency control

Номер: US20120079290A1
Автор: Christopher Houghton, David A. Biermann, Hang Nguyen, Pankaj Kumar
Принадлежит: Intel Corp

In one embodiment, the present invention includes a processor having a plurality of cores and a control logic to control provision of a voltage/frequency to a first core of the plurality of cores independently of provision of a voltage/frequency to at least a second core of the plurality of cores. In some embodiments, the voltages may be provided from one or more internal voltage regulators of the processor. Other embodiments are described and claimed.

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Номер записи: 9
29-03-2012 дата публикации

Energy efficient heterogeneous systems

Номер: US20120079298A1
Автор: Abhinandan Majumdar, Srihari Cadambi, Srimat Chakradhar
Принадлежит: NEC Laboratories America Inc

Low-power systems and methods are disclosed for executing an application software on a general purpose processor and a plurality of accelerators with a runtime controller. The runtime controller splits a workload across the processor and the accelerators to minimize energy. The system includes building one or more performance models in an application-agnostic manner; and monitoring system performance in real-time and adjusting the workload splitting to minimize energy while conforming to a target quality of service (QoS).

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Номер записи: 10
05-04-2012 дата публикации

Power Budget Allocation in Multi-Processor Systems

Номер: US20120084580A1
Автор: Anshul Gandhi, Jeffrey Kephart, Mor Harchol-Balter, Rajarshi Das
Принадлежит: CARNEGIE MELLON UNIVERSITY, International Business Machines Corp

Systems, apparatuses, methods, and software that implement power budget allocation optimization algorithms in multi-processor systems, such as server farms. The algorithms are derived from a queuing theoretic model that minimizes the mean response time of the system to the jobs in the workload while accounting for a variety of factors. These factors include, but are not necessarily limited to, the type of power (frequency) scaling mechanism(s) available within the processors in the system, the power-to-frequency relationship(s) of the processors for the scaling mechanism(s) available, whether or not the system is an open or closed loop system, the arrival rate of jobs incoming into the system, the number of jobs within the system, and the type of workload being processed.

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Номер записи: 11
03-05-2012 дата публикации

Motherboard

Номер: US20120106097A1
Автор: Ming-Chih Hsieh
Принадлежит: Hon Hai Precision Industry Co Ltd

A motherboard includes a power circuit, a system power supply, and a central processor unit (CPU). The power circuit includes a direct current (DC) voltage input terminal. A first control circuit receives a direct current (DC) voltage through the DC voltage input terminal and outputs a first control signal. A second control circuit receives the first control signal and outputs a second control signal to the CPU and output a third control signal. A switching circuit includes a number of switches. The second control signal controls the corresponding switches to be on or off. A voltage converting circuit receives the third control signal and converts the DC voltage from the DC voltage input terminal, and outputs the converted DC voltage to the system power supply. The CPU receives the second control signal and controls the motherboard operation.

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Номер записи: 12
03-05-2012 дата публикации

Device For Controlling The Power Supply Of A Computer

Номер: US20120110361A1
Автор: Nicolas Marchand, Sylvain Durand
Принадлежит: CENTRE NATIONAL DE LA RECHERCHE SCIENTIFIQUE CNRS, Institut National de Recherche en Informatique et en Automatique INRIA

The invention relates to a device for controlling a computer ( 4 ) capable of being powered with a plurality of voltage levels, including a controller ( 2 ) arranged so as to receive charge data (Ci), deadline data (Ni), and instantaneous speed data (w) for said computer ( 4 ), in order to calculate a reference speed that enables said computer to nm an amount of calculations drawn from the charge data (Ci) in a period drawn from the deadline data (Ni), and to calculate a control voltage level (V_lvl ) and operating frequency (f_op) for said computer from said reference speed. At least one element from among the reference speed and the operating frequency (f_op) is calculated using the instantaneous speed data (w).

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Номер записи: 13
10-05-2012 дата публикации

Low power dual processor architecture for multi mode devices

Номер: US20120115456A1
Автор: Albert S. Ludwin, Ranganathan Krishnan, William R. Gardner
Принадлежит: Qualcomm Inc

A mobile computing device with multiple modes, for example, wireless communication and personal computing, has an application processor and a communication processor. In the computing mode, the application processor is the master processor. In the communication mode, the application processor is deenergized to conserve battery power, with the communication processor functioning as the master processor by accessing the device's peripheral bus using the memory interface of the communication processor.

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Номер записи: 14
17-05-2012 дата публикации

Dynamic Voltage and Frequency Management

Номер: US20120119777A1
Автор: Vincent R. von Kaenel
Принадлежит: Individual

In one embodiment, an integrated circuit includes a self calibration unit configured to iterate a test on a logic circuit in the integrated circuit at respectively lower supply voltage magnitudes until the test fails. A lowest supply voltage magnitude at which the test passes is used to generate a requested supply voltage magnitude for the integrated circuit. In an embodiment, an integrated circuit includes a series connection of logic gates physically distributed over an area of the integrated circuit, and a measurement unit configured to launch a logical transition into the series and detect a corresponding transition at the output of the series. The amount of time between the launch and the detection is used to request a supply voltage magnitude for the integrated circuit.

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Номер записи: 15
07-06-2012 дата публикации

Fast computer startup

Номер: US20120144177A1
Автор: Brian E. King, Emily N. Wilson, Kirsten V. Stark, Mehmet Iyigun, Neel Jain, Patrick L. Stemen, Sushu Zhang, Vasilios Karagounis, Yevgeniy Bak
Принадлежит: Microsoft Corp

Fast computer startup is provided by, upon receipt of a shutdown command, recording state information representing a target state. In this target state, the computing device may have closed all user sessions, such that no user state information is included in the target state. However, the operating system may still be executing. In response to a command to startup the computer, this target state may be quickly reestablished from the recorded target state information. Portions of a startup sequence may be performed to complete the startup process, including establishing user state. To protect user expectations despite changes in response to a shutdown command, creation and use of the file holding the recorded state information may be conditional on dynamically determined events. Also, user and programmatic interfaces may provide options to override creation or use of the recorded state information.

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Номер записи: 16
14-06-2012 дата публикации

Apparatus and method for adaptive back bias control of an integrated circuit

Номер: US20120151227A1
Автор: Darius D. Gaskins
Принадлежит: Via Technologies Inc

An apparatus includes an adaptive bias generator and a state processor. The adaptive bias generator is disposed on the integrated circuit, and is configured to generate a variable bias voltage according to a value received over a bias bus, where the variable bias voltage is applied to the substrate. The state processor is coupled to the adaptive bias generator, and is configured to receive one or more power management states, and is configured to provide the value over the bias bus, where the value is a function of the one or more power management states.

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Номер записи: 17
28-06-2012 дата публикации

Power and thermal optimization of processor and cooling

Номер: US20120166015A1
Автор: Casey R. Winkel, Robin A. Steinbrecher, Sandeep Ahuja
Принадлежит: Intel Corp

In some embodiments a processor is adapted to store a relationship of power as a function of temperature and voltage, wherein the stored relationship data is to be used for managing power in a system including the processor. Other embodiments are described and claimed.

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Номер записи: 18
05-07-2012 дата публикации

Method, apparatus, and system for energy efficiency and energy conservation including balancing power among multi-frequency domains of a processor based on efficiency rating scheme

Номер: US20120173895A1
Автор: Jay D. Schwartz, Jeremy Shrall, SeongWoo Kim, Stephen H. Gunther, Travis C. Furrer
Принадлежит: Intel Corp

The efficiency rating (ER) of each domain, in a processor, may be compared and then the power budget may be allocated, effectively, among the domains based on the ERs of the domains. The ER may indicate relative advantage among domains in terms of performance return for a given power budget, i.e., a higher effectiveness may be expected in power utilization if the ER is higher for a domain. The ER of a domain may be defined as (scalability factor/cost factor*alpha). The scalability factor may be defined as a performance increase (in %) brought about by an increase in the clock frequency (in %) provided to the domain. The cost factor may be defined as a power budget value required in bringing about an increase in the clock frequency provided to the domain and alpha is an adjustment factor.

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Номер записи: 19
12-07-2012 дата публикации

Method and system for managing thermal policies of a portable computing device

Номер: US20120179416A1
Автор: Bohuslav Rychlik, Jeffrey A. NIEMANN, Jon James Anderson, Sumit Sur
Принадлежит: Qualcomm Inc

A method and system for managing one or more thermal policies of a portable computing device (PCD) includes monitoring temperature of the portable computing device with internal thermal sensors and external thermal sensors. If a change in temperature has been detected by at least one thermal sensor, then a thermal policy manager may increase a frequency in which temperature readings are detected by the thermal sensors. The thermal policy manager may also determine if a current temperature of the portable computing device as detected by one or more of the thermal sensors falls within one or more predetermined thermal states. Each thermal state may be assigned a unique set of thermal mitigation techniques. Each set of thermal mitigation techniques may be different from one another. The sets of thermal mitigation techniques may differ according to quantity of techniques and impacts on performance of the PCD.

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Номер записи: 20
26-07-2012 дата публикации

Semiconductor Integrated Circuit and Control Method for Clock Signal Synchronization

Номер: US20120187993A1
Автор: Makoto Saen, Masafumi Onouchi, Shigenobu Komatsu, Yusuke Kanno
Принадлежит: Individual

There is a need to ensure operation performance of a circuit region under DVFS control at low costs and highly precisely while a power-supply voltage change is made to the region. A first circuit (FVA) uses a first power-supply voltage (VDDA) for operation. A second circuit (NFVA) uses a second power-supply voltage (VDDB) for operation. A clock delay may be adjusted between paths for transmitting a clock to these circuits. When VDDA equals VDDB, a clock is distributed to FVA through a path that does not contain a delay device for phase adjustment. When the power-supply voltage for the FVA region is reduced, a clock is distributed to the FVA region based on a phase equivalent to one or two cycles of the clock displaced. Synchronization control is provided to synchronize clocks (CKAF and CKBF) and ensures operation so that a phase of two clocks to be compared fits in a range of design values while the power-supply voltage for the first circuit is changed.

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Номер записи: 21
02-08-2012 дата публикации

Memory Attribute Sharing Between Differing Cache Levels of Multilevel Cache

Номер: US20120198166A1
Автор: Joseph Raymond Michael Zbiciak, Naveen Bhoria, Raguram Damodaran
Принадлежит: Texas Instruments Inc

The level one memory controller maintains a local copy of the cacheability bit of each memory attribute register. The level two memory controller is the initiator of all configuration read/write requests from the CPU. Whenever a configuration write is made to a memory attribute register, the level one memory controller updates its local copy of the memory attribute register.

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Номер записи: 22
02-08-2012 дата публикации

Establishing an operating range for dynamic frequency and voltage scaling

Номер: US20120198255A1
Автор: Andrew J. Geissler, Harold W. Chase, Jagat V. Pokala, Joshua D. Friedrich, Malcolm S. Ware, Norman K. James, Soraya Ghiasi
Принадлежит: International Business Machines Corp

During manufacture, an operating range for dynamic voltage and frequency scaling can be established. A nominal operating point is identified based on a design nominal operating frequency for a computer processor. The nominal operating point comprises a nominal operating voltage identified for the design nominal operating frequency. In dependence upon the nominal operating point, an operating range of frequency and voltage over which the computer processor is to function is determined. Information specifying the nominal operating point and the operating range is stored in non-volatile storage associated with the computer processor.

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Номер записи: 23
09-08-2012 дата публикации

Apparatus and methods for processor power supply voltage control using processor feedback

Номер: US20120204047A1
Автор: Jae Kwan Ryoo
Принадлежит: SAMSUNG ELECTRONICS CO LTD

Methods of operating an integrated circuit include determining a difference between a reference level and a level of a power supply voltage at a processor circuit of the integrated circuit, generating a digital code responsive to the determined difference and transmitting the digital code to a power management integrated circuit that provides power to the integrated circuit. The power management integrated circuit may adjust the power supply voltage responsive to the transmitted code. Integrated circuits and data processing systems are also provided.

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Номер записи: 24
25-10-2012 дата публикации

Method and system for thermal load management in a portable computing device

Номер: US20120271481A1
Автор: James M. ARTMEIER, Jeffrey A. NIEMANN, Jon James Anderson, Sumit Sur
Принадлежит: Qualcomm Inc

Methods and systems for leveraging temperature sensors in a portable computing device (“PCD”) are disclosed. The sensors may be placed within the PCD near known thermal energy producing components such as a central processing unit (“CPU”) core, graphical processing unit (“GPU”) core, power management integrated circuit (“PMIC”), power amplifier, etc. The signals generated by the sensors may be monitored and used to trigger drivers running on the processing units. The drivers are operable to cause the reallocation of processing loads associated with a given component's generation of thermal energy, as measured by the sensors. In some embodiments, the processing load reallocation is mapped according to parameters associated with pre-identified thermal load scenarios. In other embodiments, the reallocation occurs in real time, or near real time, according to thermal management solutions generated by a thermal management algorithm that may consider CPU and/or GPU performance specifications along with monitored sensor data.

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Номер записи: 25
15-11-2012 дата публикации

Managing Bandwidth Allocation in a Processing Node Using Distributed Arbitration

Номер: US20120290756A1
Автор: Abhijeet Ashok Chachad, David Quintin Bell, Dheera Balasubramanian, Raguram Damodaran, Roger Kyle Castille
Принадлежит: Texas Instruments Inc

Management of access to shared resources within a system comprising a plurality of requesters and a plurality of target resources is provided. A separate arbitration point is associated with each target resource. An access priority value is assigned to each requester. An arbitration contest is performed for access to a first target resource by requests from two or more of the requesters using a first arbitration point associated with the first target resource to determine a winning requester. The request from the winning requester is forwarded to a second target resource. A second arbitration contest is performed for access to the second target resource by the forwarded request from the winning requester and requests from one or more of the plurality of requesters using a second arbitration point associated with the second target resource.

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Номер записи: 26
06-12-2012 дата публикации

Information Handling System with Processing System, Low-power Processing System and Shared Resources

Номер: US20120311364A1
Автор: Andrew T. Sultenfuss, Steven L. Belt
Принадлежит: Dell Products LP

An information handling system includes a processing system, a low-power processing system, and a chipset. The processing system is configured to operate using a power system configured to power a shared resource of the processing system and a non-shared resource of the processing system, and to disable the non-shared resource during a reduced operating state of the processing system. The low-power processing system is configured to access the shared resource of the processing system during operation of the low-power processing system, wherein the operation of the low-power processing system is separate from the operation of the processing system. The chipset includes a processor of the processing system and operable to be enabled during operation of the processing system, wherein the processor is configured to be disabled during operation of the low-power processing system.

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Номер записи: 27
13-12-2012 дата публикации

Power management in a data-capable strapband

Номер: US20120316471A1
Автор: Hosain Sadequr RAHMAN, II Max Everett Utter, Jeremiah Robison, Michael Edward Smith Luna, Richard Lee DRYSDALE, Scott Fullam, Thomas Alan Donaldson, Travis Austin BOGARD
Принадлежит: AliphCom LLC

Embodiments of the invention relates generally to electrical and electronic hardware, computer software, wired and wireless network communications, and computing devices, and more specifically to structures and techniques for managing power generation, power consumption, and other power-related functions in a data-capable strapband. Embodiments relate to a wearable band including sensors, a controller coupled to the sensors, an energy storage device, a power port configured to receive power and control signals, and a power manager. The power manager includes at least a transitory power manager configured to control an application of power to one or more components of the wearable band in one or more power modes. The band can be configured as a wearable communications device and sensor platform.

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Номер записи: 28
13-12-2012 дата публикации

Processor bridging in heterogeneous computer system

Номер: US20120317321A1
Автор: Teng-Chang Chang
Принадлежит: INSTITUTE FOR INFORMATION INDUSTRY

A bridge logic device for a heterogeneous computer system that has at least one performance processor, a processor supporting logic supporting the at least one performance processor to execute tasks of the software, and a hypervisor processor consuming less power than the at least one performance processor is disclosed. The bridge logic device comprises a hypervisor operation logic that maintains status of the system under the at least one performance processor; a processor language translator logic that translates between processor languages of the at least one performance and the hypervisor processors; and a high-speed bus switch that has first, second and third ports for relaying data across any two of the three ports bidirectionally. The switch is connected to the at least one performance processor, the hypervisor processor via the processor language translator logic, and to the processor supporting logic respectively at the first, second, and third port.

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Номер записи: 29
27-12-2012 дата публикации

Power-supply control apparatus and power-supply control method

Номер: US20120326692A1
Автор: Kensuke Ishida, Tohru Koizumi
Принадлежит: Fujitsu Ltd

A power-supply control apparatus uses a margin setting unit to set the value of a margin that is added to a request voltage value VID 1 of an electronic device, which dynamically changes the operation voltage. A margin adding unit calculates a control voltage value VID 2 by adding the margin to the request voltage value VID 1 and outputs the control voltage value VID 2 to a power-supply apparatus. Therefore, the power-supply apparatus can supply a margin-included voltage value that is changed in accordance with a change in the operation voltage of the electronic device. Accordingly, it is possible to check the electronic device, which dynamically changes its operation voltage, by using a margin that is properly set.

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Номер записи: 30
03-01-2013 дата публикации

Adaptive Power Management

Номер: US20130007473A1
Автор: Reinierus Hendricus Maria van der Lee
Принадлежит: Broadcom Corp

Disclosed are various embodiments of adaptive management of a device. The adaptive management includes, e.g., power management, energy management, and diagnostics. In one embodiment, a device including a power management unit (PMU) communicatively coupled to a processor is configured to transmit a status notification to the processor in response to an interrupt signal; obtain a high level state command from the processor in response to the status notification, and modify power operation of the device in response to the high level state command. In another embodiment, a method for charging a power source includes obtaining, by a PMU of a device, operational characteristics of a power supply in communication with the device; determining a power supply type based at least in part upon the operational characteristics; and controlling charging of the power source based at least in part upon the power supply type.

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Номер записи: 31
14-02-2013 дата публикации

Systems and methods for reducing power consumption during communication between link partners

Номер: US20130039363A1
Автор: Robert Hays
Принадлежит: Intel Corp

Generally, this disclosure describes an energy-efficient Ethernet communications approach. In at least one embodiment described herein, an Ethernet controller may be configured to operate in an active power state to transmit or receive data packets at a maximum available link speed. The maximum available link speed may be determined by a negotiation between the Ethernet controller and a link partner coupled to the Ethernet controller. Once the data packets are transmitted or received, the Ethernet controller may be configured to operate in an idle power state to reduce energy consumption.

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Номер записи: 32
21-02-2013 дата публикации

Semiconductor Device Predictive Dynamic Thermal Management

Номер: US20130046999A1
Автор: Hwisung JUNG
Принадлежит: Broadcom Corp

A semiconductor device includes a memory storing a lookup table including stored values associated with modes of operation of a component of the semiconductor device. A monitor monitors an operating parameter of the component in real-time, and reports a calculated value associated with the same. A power manager determines a change in the mode of operation of the component based on a comparison of the calculated value with a corresponding stored value, and adjusts a current mode of operation of the component in real-time.

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Номер записи: 33
07-03-2013 дата публикации

System and method of monitoring a central processing unit in real time

Номер: US20130061069A1
Автор: Ali Iranli, Christopher Kong Yee Chun, Haw-Jing Lo, Michael J. Drop, Moinul H. Khan, Steven S. Thomson, Tao Xue, Vinodh R. Cuppu
Принадлежит: Qualcomm Inc

Devices and methods for monitoring one or more central processing units in real time is disclosed. The method may include monitoring state data associated with the one or more CPUs in real-time, filtering the state data, and at least partially based on filtered state data, selectively altering one or more system settings. A device may include means for monitoring state data associated with the one or more CPUs in real-time, means for filtering the state data, and means for selectively altering one or more system settings at least partially based on filtered state data. A device may also include a sub-sampling circuit configured to receive a hardware core signal from the central processing unit and output a central processing unit state indication, and an infinite impulse response filter connected to the sub-sampling circuit and configured to receive the central processing unit state indication from the sub-sampling circuit.

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Номер записи: 34
21-03-2013 дата публикации

Controlling Method, Power Supply, Power Controller, and Power Controlling Method

Номер: US20130070483A1
Автор: Yu-Yun Huang
Принадлежит: Leadtrend Technology Corp

A power supply has an inductor and determines loading state of the power supply according to a compensation signal. When the loading state is determined to be a light loading state or a no-loading state, a switch is operated at a low operating frequency. When the loading state is determined to be a heavy loading state, the switch is operated at a high operating frequency. If the compensation signal exceeds a critical value, it is determined that the loading state is an overloaded state. When the overloaded state continues past a tolerable duration, the switch is turned off. The tolerable duration is determined by an external capacitor and is independent of the operating frequency.

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Номер записи: 35
25-04-2013 дата публикации

Method and Apparatus for Power Control

Номер: US20130104130A1
Автор: David A. Carlson, Richard E. Kessler
Принадлежит: Cavium LLC

Embodiments of the present invention relate to limiting maximum power dissipation occurred in a processor. Therefore, when an application that requires excessive amounts of power is being executed, the execution of the application may be prevented to reduce dissipated or consumed power.

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Номер записи: 36
02-05-2013 дата публикации

ELECTRIC DEVICE

Номер: US20130111246A1
Автор: YAMAGUCHI Tatsumi
Принадлежит: Oki Data Corporation

An electric device is capable of operating in a normal operation mode and a power save operation mode. The electric device includes a first processor for processing information input externally in the normal operation mode, and a second processor for processing an internal operation of the electric device in the normal operation mode. The second processor consumes power smaller than that of the first processor. In the electric device, power of the first processor is restricted through a restriction process in the power save operation mode. Further, in the power save operation mode, the second processor restricts the internal operation and processes the information input externally. When the second processor detects the information input externally, power of the first processor is released through a restriction releasing process. 1. An electric device capable of operating in a normal operation mode and a power save operation mode , comprising:a first processor for processing information input externally in the normal operation mode; anda second processor for processing an internal operation of the electric device in the normal operation mode, said second processor having power consumption smaller than that of the first processor, said second processor restricting the internal operation and processing the information input externally in the power save operation mode,wherein said first processer is configured to switch an operation of the second processor from an operation in the normal operation mode to an operation in the power save operation mode when the first processor detects a transition factor to the power save operation mode,power of the first processor is restricted through a restriction process in the power save operation mode, andsaid power of the first processor is released through a restriction releasing process when the second processor detects the information input externally.2. The electric device according to claim 1 , wherein said first processer is ...

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Номер записи: 37
02-05-2013 дата публикации

ACCESSING A LOCAL STORAGE DEVICE USING AN AUXILIARY PROCESSOR

Номер: US20130111249A1
Автор: Chang Jichuan, Ranganathan Parthasarathy, Shah Mehul A.
Принадлежит:

The present disclosure includes accessing a local storage device using an auxiliary processor An example computing device () includes a local storage device (), a first processor () able to access the local storage device (), an auxiliary processor () able to access the local storage device () while the first processor () is shut down, wherein the auxiliary processor () uses less power than the first processor (), and a management agent () to initiate an accessing of the local storage device () by the auxiliary processor () if a load associated with the computing device () falls below a particular threshold. One of the first processor () and the auxiliary processor () is able to access the local storage device () at a time. 1100202303. A computing device ( , , ) , comprising:{'b': 110', '210', '310, 'a local storage device (, , ){'b': 112', '212', '312, 'a first processor (, , ) able to access the local storage device;'}{'b': 114', '220', '360', '110', '210', '310', '112', '212', '312', '114', '220', '360', '112', '212', '312, 'an auxiliary processor (, , ) able to access the local storage device (, , ) while the first processor (, , ) is shut down, wherein the auxiliary processor (, , ) uses less power than the first processor (, , ); and'}{'b': 125', '225', '370', '110', '210', '310', '114', '220', '360', '100', '202', '303, 'a management agent (, , ) to initiate an accessing of the local storage device (, , ) by the auxiliary processor (, , ) if a load associated with the computing device (, , ) falls below a particular threshold, and'}{'b': 112', '212', '312', '114', '220', '360', '110', '210', '310, 'wherein one of the first processor (, , ) and the auxiliary processor (, , ) is able to access the local storage device (, , ) at a time.'}2100202303125225370112212312. The computing device ( claim 1 , claim 1 , ) of claim 1 , wherein the management agent ( claim 1 , claim 1 , ) is able to shut down the first processor ( claim 1 , claim 1 , ) if the load falls ...

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Номер записи: 38
09-05-2013 дата публикации

Offline communication in a voltage scaling system

Номер: US20130117582A1
Автор: Anand Satyamoorthy, Sean Fitzpatrick
Принадлежит: Mediatek Singapore Pte Ltd

The subject matter of this application is embodied in an apparatus that includes a data processor, and a hardware monitor. The hardware monitor can be configured to emulate a critical path of the data processor, measure a parameter associated with the emulated critical path, process the measurement value, and generate an interrupt signal if the processing result meets a criterion. The apparatus also includes a power supply to provide power to the data processor and the hardware monitor, and a controller to control the power supply to adjust an output voltage level of the power supply. The controller upon receiving an interrupt signal from the hardware monitor queries the hardware monitor to obtain a measurement of the parameter and controls the power supply to adjust the output voltage level according to the measurement value.

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Номер записи: 39
09-05-2013 дата публикации

Run-Time Task-Level Dynamic Energy Management

Номер: US20130117588A1
Автор: Amit Dugar, Prathiba Kumar, Sangram Alapati, Satish K. Sadasivam
Принадлежит: International Business Machines Corp

A mechanism is provided for run-time task-level dynamic energy management. An instruction address for a first instruction of the application is mapped to a portion of application code in the application in response to an application being marked for energy management. A monitoring of the hardware resource activities is done for the portion of the application code. A level of energy management is then implemented for the portion of the application code based on a value of the tick indicator, resource activities, and an intensity indicator.

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Номер записи: 40
09-05-2013 дата публикации

POWER CAPPING SYSTEM

Номер: US20130117592A1
Автор: Gerbozy Zachary J., Humphrey Daniel, Mohr David Paul
Принадлежит:

A method for power capping is disclosed. The power supplied to a load from a power supply is compared to a power capping limit When the power drawn by the load exceeds the power capping limit, power to the load is supplied by both the power supply and an energy storage device 1. A method for power capping , comprising:supplying power to a load from a power source; 'supplying power to the load using only the power source;', 'when the amount of power supplied is below a power capping limit then (a) supplying power to the load from both an energy storage device and the power source;', '(b) reducing the power drawn by the load., 'when the amount of power supplied is not below the power capping limit then2. The method of claim 1 , further comprising: the power draw from the energy storage device is above a first power draw threshold amount;', 'the total energy drawn from the energy storage device exceeds an energy threshold amount;', 'the power draw of the load exceeds a second power draw threshold;', 'the energy remaining in the energy storage device falls below a energy level threshold., 'reducing the power drawn by the load only when at least one of the following occur;'}3. The method of claim 1 , further comprising:when the amount of power being supplied to the load is below the power capping limit then supplying power to the load from only the power source.when the amount of power being supplied to the load is above the power capping limit then repeat steps (a) and (b).4. The method of claim 1 , wherein the energy storage device automatically starts supplying power to the load claim 1 , without the intervention of a power manager claim 1 , when the power supplied is not below the power capping limit.5. The method of claim 1 , further comprising:when the amount of power being supplied to the load is below the power capping limit then charging the energy storage device.6100102104110116120118. The method of claim 1 , wherein the load is comprised of at least one of the ...

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Номер записи: 41
16-05-2013 дата публикации

Processor with power control via instruction issuance

Номер: US20130124900A1
Автор: Ali Ibrahim, Brian D. Emberling, Jeff Herman, Krishna Sitaraman, Seth Hendrickson, Stephen D. Presant
Принадлежит: Advanced Micro Devices Inc

Methods and apparatuses are provided for power control in a processor. The apparatus comprises a plurality of operational units arranged as a group of operational units. A power consumption monitor determines when cumulative power consumption of the group of operational units exceeds a threshold (e.g., either or both of the cumulative power threshold and the cumulative power rate threshold) during a time interval, after which a filter for issuing instructions to the group of operational units suspends instruction issuance to the group of operational units for the remainder of the time interval. The method comprises monitoring cumulative power consumption by a group of operational units within a processor over a time interval. If the cumulative power consumption of the group of operational units exceeds the threshold, instruction issuance to the group of operational units is suspended for the remainder of the time interval.

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Номер записи: 42
23-05-2013 дата публикации

Reducing power consumption by masking a process from a processor performance management system

Номер: US20130132754A1
Автор: Peter HANAPPE
Принадлежит: Sony Corp

Energy savings can be obtained by masking a computationally-intensive task from a processor performance management system which selects the processor performance state based on the load on the processor (CPU). By preventing the PPM system from reacting to the computational load the application places on the processor, the time to complete execution of the application increases but the energy used by the application may be greatly reduced and thermal stress on the CPU is also reduced (preventing noisy fans from operating). This approach makes it convenient to run a computationally intensive task as a background task. The masking can be achieved by running the task in tiny bursts, with micro-sleeps in between them, so that the average CPU load is low over a time period that the PPM system uses for measuring CPU activity/load.

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Номер записи: 43
30-05-2013 дата публикации

Modular integrated circuit with uniform address mapping

Номер: US20130138936A1
Автор: Bhupesh Kharwa, Lawrence J. Madar, III, Mark N. Fullerton
Принадлежит: Broadcom Corp

A modular integrated circuit includes a hub module that is coupled to a plurality of spoke modules via a plurality of hub interfaces. A memory module stores hub software and hub data and configuration data. The hub software operates in accordance with a memory map that includes a plurality of first reserved blocks corresponding to memory reserved for the plurality of spoke modules, and at least one second reserved block corresponding to memory reserved for at least one optional spoke module. The plurality of first reserved blocks are activated based on the configuration data and the at least one second reserved block is deactivated based on the configuration data.

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Номер записи: 44
30-05-2013 дата публикации

Voltage control

Номер: US20130138993A1
Автор: John David Frank FRANKLIN
Принадлежит: Astrium Ltd

An apparatus for controlling a supply voltage to an electronic processing arrangement comprising a processor or a memory element, the apparatus being configured to receive an output of the electronic processing arrangement and comprising: error detection means for detecting errors in an output of the electronic processing arrangement; and means for adaptively varying the supply voltage to the electronic processing arrangement based on an analysis of errors detected in the output of the electronic processing arrangement. The apparatus may further comprise means for correcting errors detected in the output of the electronic processing arrangement.

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Номер записи: 45
06-06-2013 дата публикации

Data processing device and data processing system

Номер: US20130145190A1
Автор: Jun Setogawa, Mamoru Sakugawa, Masamichi Fujito, Masaru Takahashi, Shinsuke Yoshimura
Принадлежит: Renesas Electronics Corp

A central processing unit sets which of the following modes a data processing device is to operate in accordance with a user program. The high-speed operation mode allows operation within a first range in which an external supply voltage is relatively high. The wide voltage range operation mode allows operation within a second range in which the external supply voltage includes the first range and a relatively low voltage range, and an upper limit of a frequency of the first clock in the wide voltage range operation mode is lower than an upper limit of a frequency of the first clock in the high-speed operation mode. The frequency of the first clock in the low power consumption operation mode is lower than the frequency of the first clock in the high-speed operation mode and the frequency of the first clock in the wide voltage range operation mode.

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Номер записи: 46
06-06-2013 дата публикации

DATA PROCESSING DEVICE AND DATA PROCESSING SYSTEM

Номер: US20130145193A1
Автор: Ishikura Hiromichi, Takahashi Masaru
Принадлежит: RENESAS ELECTRONICS CORPORATION

A data processing device includes: a first power-on reset circuit; a second power-on reset circuit with higher power consumption and higher reset voltage accuracy than the first power-on reset circuit; a storage unit storing information for determining whether to keep the second power-on reset circuit in an active state or an inactive state; and a central processing unit initialized in response to respective outputs of the first and second power-on reset circuits and setting the information in the storage unit. 1. A data processing device comprising:a first power-on reset circuit;a second power-on reset circuit with higher power consumption and higher reset voltage accuracy than said first power-on reset circuit;a storage unit storing information for determining whether to keep said second power-on reset circuit in an active state or an inactive state; anda central processing unit initialized in response to respective outputs of said first and second power-on reset circuits and setting said information in said storage unit.2. The data processing device according to claim 1 , whereinsaid data processing device has a normal mode and a standby mode, andsaid central processing unit sets said information in said storage unit so that, in said standby mode, said second power-on reset circuit is inactivated while said first power-on reset circuit is used to detect that a power supply voltage has decreased to a voltage which meets a reset condition.3. The data processing device according to claim 2 , whereinprior to switch from said normal mode to said standby mode, said central processing unit sets said information in said storage unit so that said second power-on reset circuit is inactivated, and thereafter switches to said standby mode.4. The data processing device according to claim 3 , further comprising a control unit receiving respective outputs of said first and second power-on reset circuits claim 3 , whereinin a case where the output of said first power-on reset ...

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Номер записи: 47
13-06-2013 дата публикации

Computing platform interface with memory management

Номер: US20130151569A1
Автор: Andrew Henroid, Anil Aggarwal, Efraim Rotem, Eliezer Weissmann, Guy Therien, Jeremy Shrall, Jose Andy Vargas, Krishnakanth Sistla, Mark Doran, Michael A. Rothman, Mohan Kumar, Neelam Chandwani, Paul Diefenbaugh, Robert Gough, Sarathy Jayakumar
Принадлежит: Individual

In some embodiments, a PPM interface may be provided with functionality to facilitate to an OS memory power state management for one or more memory nodes, regardless of a particular platform hardware configuration, as long as the platform hardware is in conformance with the PPM interface.

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Номер записи: 48
13-06-2013 дата публикации

Linked shell

Номер: US20130151874A1
Автор: Andrew John Fuller, Erik Michael Geidl, Gregory H. Parks
Принадлежит: Microsoft Corp

An apparatus and method is provided for controlling a display device for displaying a user interface associated with an application. A processor for controlling peripheral devices and/or the display may be selected based on characteristics of a requested function to be performed. For example, a processor may be selected with a power characteristic corresponding to a power level needed to perform the requested function. Also, an instantiation of a user interface may be switched based on selection of the processor for controlling peripheral devices. In another example, the transition from one instantiation of the user interface to another instantiation of the user interface may be smooth such that a user may be unaware a change has been made.

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Номер записи: 49
13-06-2013 дата публикации

SYSTEMS AND METHODS FOR PREDICTIVE CONTROL OF POWER EFFICIENCY

Номер: US20130151877A1
Автор: Bacchus Reza M., Kadri Rachid M.
Принадлежит:

A computer power management system () can include power demand logic () of a computer component () that can generate a power demand signal corresponding to a predicted power demand determined for the computer component (). A voltage regulator down (VRD) system () includes at least one power phase (). The VRD system () can selectively adjust an input power to the computer component () based on power efficiency in response to the power demand signal. 110. A system () comprising:{'b': 20', '12, 'power demand logic () to generate a power demand signal corresponding to a predicted power demand determined for an associated computer component (); and'}{'b': 14', '18', '14', '12, 'a voltage regulator down (VRD) system () comprising at least one power phase (), the VRD system () to selectively adjust an input power to the computer component () based on power efficiency in response to the power demand signal.'}220121612. The system of claim 1 , wherein the power demand logic () is to adjust a magnitude of the power demand signal commensurate with a change in the power demand prior to the computer component () one of activating and deactivating functionality () that requires adjustment in the input power provided to the computer component ().3. The system of claim 1 , wherein the power demand signal comprises one of an analog signal having a magnitude corresponding to the power demand and a digital signal having a duty-cycle corresponding to the power demand.41818141812. The system of claim 1 , wherein the at least one power phase () comprises a plurality of power phases () claim 1 , and wherein the VRD system () is to selectively enable and disable at least a portion of the plurality of power phases () to provide the input power to the computer component () based on the power efficiency in response to the power demand signal.518181418. The system of claim 1 , wherein the at least one power phase () comprises a single power phase () claim 1 , and wherein the VRD system () is ...

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Номер записи: 50
13-06-2013 дата публикации

SYSTEM AND METHOD FOR CONTROLLING CENTRAL PROCESSING UNIT POWER WITH GUARANTEED TRANSIENT DEADLINES

Номер: US20130151879A1
Автор: Gargash Norman S., Iranli Ali, Rychlik Bohuslav, Sur Sumit, Thomson Steven S.
Принадлежит: QUALCOMM INCORPORATED

Methods, systems and devices that include a dynamic clock and voltage scaling (DCVS) solution configured to compute and enforce performance guarantees for a group of processors to ensure that the processors does not remain in a busy state (e.g., due to transient workloads) for a combined period that is more than a predetermined amount of time above that which is required for one of the processors to complete its pre-computed steady state workload. The DCVS may adjust the frequency and/or voltage of one or more of the processors based on a variable delay to ensure that the multiprocessor system only falls behind its steady state workload by, at most, a predefined maximum amount of work, irrespective of the operating frequency or voltage of the processors. 1. A method of improving performance on a computing device having multiple processors , the method comprising:determining a steady state workload of a first processor;determining an amount of work required to perform the determined steady state workload on the first processor;computing a performance guarantee value for a processing group that includes the first processor and a second processor;transitioning the first processor from an idle state to a busy state;performing dynamic clock and voltage scaling operations to scale a frequency of the first processor based on an actual workload of the first processor;determining whether the first and second processors have remained in the busy state for a combined period greater than or equal to a sum of the determined amount of work and the performance guarantee value; andincreasing the frequency of one of the first and second processors when it is determined that the first and second processors have remained in the busy state for a combined period that is greater than or equal to a sum of the determined amount of work and the performance guarantee value.2. The method of claim 1 , wherein increasing the frequency of one of the first and second processors when it is ...

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Номер записи: 51
13-06-2013 дата публикации

BRIDGING DEVICE AND POWER SAVING METHOD THEREOF

Номер: US20130151881A1
Автор: CHEN Yen-Chang, LIN Hui-Chih
Принадлежит: VIA TECHNOLOGIES, INC.

A bridging device and a power saving method thereof are disclosed. When a bridging chip of the bridging device receives a power saving command transferred from a host and thereby enters a power saving state, a voltage converter of the bridging device is disabled accordingly and a selection circuit selects to couple a bus voltage to the bridging chip to power the bridging chip. The bus voltage is transferred from the host through a power pin of a connector of the bridging device. The connector is coupled to the host. 1. A bridging device configured to connect to a host , comprising:a connector for coupling to the host, wherein the connector has a power pin and a command pin;a voltage converter, down converting a first voltage to generate a second voltage;a bridging chip coupled to the command pin and the voltage converter, the bridging chip disabling the voltage converter when receiving a power saving command from the host through the command pin to enter a power saving state; anda selection circuit coupled to the power pin, the voltage converter and the bridging chip, the selection circuit conveying a bus voltage to the bridging chip when the voltage converter is disabled by the bridging chip, wherein the bus voltage is transferred from the host through the power pin.2. The bridging device as claimed in claim 1 , wherein the bridging chip leaves the power saving state according to a resume command transferred from the host and the bus voltage conveyed through the selection circuit.3. The bridging device as claimed in claim 2 , wherein the bridging chip enables the voltage converter to generate the second voltage to power the selection circuit when the bridging chip leaves the power saving state claim 2 , and the selection circuit selects to convey the second voltage to the bridging chip and thereby the bridge chip is powered by the second voltage to return to a normal operating state.4. The bridging device as claimed in claim 1 , wherein the selection circuita ...

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Номер записи: 52
20-06-2013 дата публикации

Power management in multiple processor system

Номер: US20130155081A1
Автор: Oleksandr Khodorkovsky, Stephen Presant
Принадлежит: Advanced Micro Devices Inc, ATI TECHNOLOGIES ULC

Power management for a processing system that has multiple processing units, (e.g., multiple graphics processing units (GPUs), is described herein. The processing system includes a power manager that obtains performance, power, operational or environmental data from a power management unit associated with each processor (e.g., GPU). The power manager determines, for example, an average value with respect to at least one of the performance, power, operational or environmental data. If the average value is below a predetermined threshold for a predetermined amount of time, then the power manager notifies a configuration manager to alter the number of active processors (e.g., GPUs), if possible. The power may then be distributed among the remaining GPUs or other processors, if beneficial for the operating and environmental conditions.

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Номер записи: 53
20-06-2013 дата публикации

OPTIMIZING POWER CONSUMPTION AND PERFORMANCE IN A HYBRID COMPUTER ENVIRONMENT

Номер: US20130159745A1
Автор: Barsness Eric L., Darrington David L., Peters Amanda, Santosuosso John M.
Принадлежит: INTERNATIONAL BUSINESS MACHINES CORPORATION

A method for optimizing efficiency and power consumption in a hybrid computer system is disclosed. The hybrid computer system may comprise one or more front-end nodes connected to a multi-node computer system. Portions of an application may be offloaded from the front-end nodes to the multi-node computer system. By building historical profiles of the applications running on the multi-node computer system, the system can analyze the trade offs between power consumption and performance. For example, if running the application on the multi-node computer system cuts the run time by 5% but increases power consumption by 20% it may be more advantageous to simply run the entire application on the front-end. 1. A hybrid computer system comprising:a plurality of computer platforms connected together including a front-end computer system and a multi-node computer system;an application with an application profile, wherein the application includes a portion of the application which can be accelerated and where the application profile includes historical information for the application and user preferences, wherein the historical information records a historical power consumption and run time of the portion of the application executing on the multi-node computer system and a historical power consumption and run time of the portion of the application running on the front-end system;when the portion of the application that can be accelerated is encountered upon execution of the application on the front-end system, a resource scheduler analyzes the application profile to determine whether to accelerate the portion of the application based on the historical information and the user preferences in the application profile;wherein the resource scheduler determines an increased power consumption and a run time improvement by comparing the historical power consumption and run time on the portion of the application executing on the multi-node computer system and the historical power ...

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Номер записи: 54
04-07-2013 дата публикации

Image forming apparatus, system on chip unit and driving method thereof

Номер: US20130173943A1
Автор: Ho-Beom Park, Sung-Uk Bin
Принадлежит: SAMSUNG ELECTRONICS CO LTD

An image forming apparatus connected to a host apparatus includes a first memory; a second memory; a USB interface to receive a USB control signal or a USB data signal from the host apparatus; a first CPU to perform an operation using the first memory in a normal mode and being deactivated if the normal mode is converted into a power saving mode; and a second CPU to perform an operation using the second memory in the power saving mode. In the image forming apparatus, if the USB data signal is input in the power saving mode, the second CPU activates the first CPU to convert the power saving mode into the normal mode, and if the USB control signal is input in the power saving mode, the second CPU retains the power saving mode and performs an operation corresponding to the USB control signal using the second memory.

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Номер записи: 55
18-07-2013 дата публикации

IMAGE FORMING APPARATUS AND CONTROL METHOD FOR EXECUTING A PROXY IN RESPONSE TO A HEARTBEAT

Номер: US20130185573A1
Автор: Okubo Yuzuru
Принадлежит: CANON KABUSHIKI KAISHA

An image forming apparatus automatically recognizes and responds to an encrypted heartbeat packet only with a small amount of calculation, without causing a sub control unit to execute an SSL/TLS decryption process. As a result, the image forming apparatus can execute a proxy response with less power consumption. 1. An image forming apparatus , comprising:a main control unit configured to control an image forming processing unit configured to execute an image forming process; anda sub control unit configured to exchange data with an information processing apparatus via a network,wherein the main control unit includes a power-saving control unit configured to shift the main control unit to a power-saving state, in which power supply to the image forming processing unit is reduced, andwherein the sub control unit comprises:a determination unit configured to determine, if an encryption communication protocol is used for exchanging messages and a message is transmitted from the information processing apparatus, whether the main control unit needs to be shifted to a non-power-saving state from the power-saving state based on a bit pattern of the message, without executing a decryption process on the message;a return unit configured to give, if the determination unit determines that the main control unit needs to be shifted to the non-power-saving state, a return instruction for shifting the main control unit to the non-power-saving state, to cause the main control unit to transmit information in response to the message to the information processing apparatus; anda response unit configured to transmit, if the determination unit determines that the main control unit does not need to be shifted to the non-power-saving state, information in response to the transmitted message to the information processing apparatus, without giving the return instruction for shifting the main control unit to the non-power-saving state.2. The image forming apparatus according to claim 1 , ...

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Номер записи: 56
18-07-2013 дата публикации

SEMICONDUCTOR DEVICE, RADIO COMMUNICATION TERMINAL USING THE SAME, AND INTER-CIRCUIT COMMUNICATION SYSTEM

Номер: US20130185574A1
Автор: NISHIKAWA Takuro
Принадлежит: RENESAS MOBILE CORPORATION

Disclosed as one aspect is a semiconductor device including a transmission/reception interface that is used for transmission and reception of data, a processing unit that processes the data, a monitoring unit that monitors received data and detects a specific frame allowed to be transmitted regardless of a state of a circuit to transmit/receive the data, and a power management unit that controls power consumption of a circuit including the processing unit. 1. A semiconductor device that switches consumption power from first consumption power to second consumption power lower than the first consumption power upon end of transmission/reception of data , comprising:a transmission/reception interface that transmits and receives the data;a processing unit that processes the data;a monitoring unit that detects a specific frame allowed to be transmitted regardless of a state of a circuit to transmit/receive the data, and outputs a first return instruction signal in accordance with a detected result; anda power management unit that switches a circuit at least including the processing unit from a second operating mode operating with the second consumption power to a first operating mode operating with the first consumption power in response to the first return instruction signal.2. The semiconductor device according to claim 1 , whereinthe transmission/reception interface outputs a sleep permission notification to the processing unit upon receiving a sleep permission frame permitting transition to a stop mode as the data,the processing unit outputs a power down control signal to the power management unit based on the sleep permission notification and end of transmission of transmission data output from the transmission/reception interface, andthe power management unit switches consumption power of a circuit at least including the processing unit from the first consumption power to the second consumption power in response to the power down control signal.3. The semiconductor ...

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Номер записи: 57
25-07-2013 дата публикации

Methods and Apparatuses for Controlling Thread Contention

Номер: US20130191666A1
Автор: Andrew Herdrich, Donald Newell, Ramesh Illikkal, Ravishankar Iyer, Vineet Chadha
Принадлежит: Individual

An apparatus comprises a plurality of cores and a controller coupled to the cores. The controller is to lower an operating point of a first core if a first number based on processor clock cycles per instruction (CPI) associated with a second core is higher than a first threshold. The controller is operable to increase the operating point of the first core if the first number is lower than a second threshold.

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Номер записи: 58
01-08-2013 дата публикации

Systems and methods of task allocation in a multiprocessing environment having power management

Номер: US20130198542A1
Автор: Arvind Kandhalu Raghu, Sandeep Bhadra, Sejoong Lee, Soon-Hyeok Choi, Xiaolin Lu
Принадлежит: Texas Instruments Inc

Systems and Methods for task allocation in a multiprocessor environment employing power management techniques are described wherein tasks are allocated relative to the density given by the ratio of worst-case-execution time and deadline of a task and also the harmonicity of a task's period with respect to a task-set. Tasks are allocated to a given processor based on either minimum density or maximum harmonicity depending on which allocation results in a lower clock frequency. Assigning a task to the processor with lowest density results in balancing the density across processors while assigning task to the processor with maximum harmonicity attempts to maximize the utilization of the processor.

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Номер записи: 59
08-08-2013 дата публикации

LIMITATION OF LEAKAGE POWER VIA DYNAMIC ENABLEMENT OF EXECUTION UNITS TO ACCOMMODATE VARYING PERFORMANCE DEMANDS

Номер: US20130205144A1
Автор: Eastlack Jeffrey R.
Принадлежит:

In an embodiment, a method of controlling performance of a processor having a first execution unit and a second execution unit includes maintaining an operational state of the first execution unit of the processor at active, monitoring a utilization of the processor, and based on the utilization, determining whether to alter the operational state of the second execution unit of the processor. When the utilization of the processor is below a first threshold and the performance capability of the second execution unit is less than the performance capability of the first execution unit, the system may change the operational state of the second execution unit of the processor to active, and the operational state of the first execution unit to inactive. When the utilization of the processor is above a second threshold, the system may change the operational state of the second execution unit of the processor to active. 1. A method of controlling performance of a processor having a first execution unit and a second execution unit , the method comprising:maintaining an operational state of the first execution unit of the processor at active;monitoring a utilization of the processor; andbased on the utilization, determining whether to alter the operational state of the second execution unit of the processor.2. The method of claim 1 , wherein the first execution unit and the second execution unit have different performance capabilities.3. The method of claim 1 , wherein the first execution unit and the second execution unit have the same performance capabilities.4. The method of claim 1 , further comprising:when the utilization of the processor is below a first threshold, changing the operational state of the second execution unit of the processor from inactive to active; andchanging the operational state of the first execution unit from active to inactive.5. The method of claim 1 , further comprising:when the utilization of the processor is above a second threshold, changing ...

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Номер записи: 60
15-08-2013 дата публикации

Systems and methods for dynamic management of switching frequency for voltage regulation

Номер: US20130207630A1
Автор: Abey K. Mathew, Johan Rahardjo, John J. Breen
Принадлежит: Individual

Systems and methods are provided that may be implemented to dynamically manage voltage regulator switching frequency. In one embodiment, the disclosed systems and methods may be implemented to dynamically find the optimal voltage regulator switching frequency based on the load current (I OUT ) and efficiency in a switching voltage regulator device (VR), such as a voltage regulator down device (VRD) that is embedded on a system board of an information handling system.

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Номер записи: 61
15-08-2013 дата публикации

Reducing performance degradation in backup semiconductor chips

Номер: US20130212414A1
Автор: Aditya Bansal, Barry P. Linder, Jae-Joon Kim, Kai Zhao, Keith A. Jenkins, Manjul Bhushan
Принадлежит: International Business Machines Corp

A system has at least a first circuit portion and a second circuit portion. The first circuit portion is operated at normal AC frequency. The second circuit portion is operated in a back-up mode at low AC frequency, such that the second circuit portion can rapidly come-online but has limited temperature bias instability degradation. The second circuit portion can then be brought on-line and operated at the normal AC frequency. A system including first and second circuit portions and a control unit, as well as a computer program product, are also provided.

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Номер записи: 62
29-08-2013 дата публикации

Method and apparatus for controlling task execution

Номер: US20130227576A1
Автор: Yu Liu
Принадлежит: Huawei Technologies Co Ltd

A method and an apparatus for controlling task execution are disclosed in the present invention which relates to the field of wireless communications technologies, addressing the problem that power consumption of a terminal in standby mode is wasted because tasks of the terminal in a standby state are fixed and corresponding time periods cannot be flexibly set for different tasks. The method includes: receiving standby state parameters sent by a terminal management module; configuring the terminal according to the standby parameters so that the terminal enters a sleeping state; enabling a timer to start timing; stopping timing when the time of the timer reaches the time point at which a current task will be executed; configuring the terminal according to working state parameters of the terminal so that the terminal enters a working state; and receiving paging information sent by the terminal management module.

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Номер записи: 63
05-09-2013 дата публикации

CONSERVING POWER BY REDUCING VOLTAGE SUPPLIED TO AN INSTRUCTION-PROCESSING PORTION OF A PROCESSOR

Номер: US20130232363A1
Автор: Youngs Lynn R.
Принадлежит: Apple Inc.

One embodiment of the present invention provides a system that facilitates reducing static power consumption of a processor. During operation, the system receives a signal indicating that instruction execution within the processor is to be temporarily halted. In response to this signal, the system halts an instruction-processing portion of the processor, and reduces the voltage supplied to the instruction-processing portion of the processor. Full voltage is maintained to a remaining portion of the processor, so that the remaining portion of the processor can continue to operate while the instruction-processing portion of the processor is in reduced power mode. 1. A method for operating a processor , comprising:determining if the processor has been taking long naps;if not, causing the processor to enter a normal nap mode, wherein entering the normal nap mode comprises halting the processor without reducing voltages to a non-core power area of the processor or a core power area of the processor; andotherwise, causing the processor to enter a deep nap mode, wherein entering the deep nap mode comprises halting the processor and reducing a voltage to the core power area of the processor.2. The method of claim 1 , wherein reducing the voltage to the core power area of the processor comprises reducing the voltage of the core power area of the processor to zero.3. The method of claim 2 , wherein entering the deep nap mode further comprises saving state information from the core power area of the processor to a location outside the core power area of the processor.4. The method of claim 3 , wherein saving the state information from the core power area of the processor comprises saving the state information in one of:a cache;a main memory; ora dedicated memory.5. The method of claim 1 , wherein reducing the voltage to the core power area of the processor comprises reducing the voltage to a level that is sufficient to maintain state information in the core power area of the ...

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Номер записи: 64
05-09-2013 дата публикации

MANAGING POWER CONSUMPTION IN A MULTI-CORE PROCESSOR

Номер: US20130232368A1
Автор: BOWHILL WILLIAM, FETZER Eric, Garg Vivek, Kumar Rakesh, Naveh Alon, RIEDLINGER REID, Rotem Efraim, Sharma Lokesh, SHRIMALI SATISH, Sistla Krishnakanth, Soltis Don
Принадлежит:

A processor may include a core and an uncore area. The power consumed by the core area may be controlled by controlling the Cdyn of the processor such that the Cdyn is within an allowable Cdyn value irrespective of the application being processed by the core area. The power management technique includes measuring digital activity factor (DAF), monitoring architectural and data activity levels, and controlling power consumption by throttling the instructions based on the activity levels. As a result of throttling the instructions, throttling may be implemented in 3droop and thermal design point (TDP). Also, the idle power consumed by the uncore area while the core area is in deep power saving states may be reduced by varying the reference voltage VR and the VP provided to the uncore area. As a result, the idle power consumed by the uncore area may be reduced. 1. A processor comprising:a core area including a plurality of cores; andan uncore area having a power management unit and a voltage regulator, wherein the voltage regulator is to provide a regulated voltage (VR) to the uncore area, wherein the power management unit is to detect an event based on which the core area is to enter a deep power saving state and in response provide a first voltage value to the voltage regulator, the voltage regulator to decrease the VR from a first reference voltage value to a second reference voltage value based on the first voltage value, the decrease to cause a reduction in a pin voltage value provided at a supply pin of the uncore area, wherein the reduction in the pin voltage value is to decrease power consumption of the uncore area, wherein the pin voltage value is decreased to a level sufficient to maintain a minimum pin voltage value to operate the processor at a specified frequency value.2. The processor of claim 1 , wherein the uncore area is to consume a reduced amount of power until the core area is in the deep power saving state.3. The processor of claim 2 , wherein the ...

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Номер записи: 65
12-09-2013 дата публикации

Energy management system

Номер: US20130238157A1
Автор: Andrew Katsouris, David Hall, Jonathan Luke, Stavros Antoniou, Yann Bussard-Mogrovejo
Принадлежит: SENSELOGIX Ltd

An energy management system ( 1 ) comprising: policy establishment means ( 3 ) for establishing one or more energy policies, the or each said policy being configured for managing the energy consumption of at least one energy consuming appliance ( 7 ); and at least one energy node ( 5 ) configured to communicate with said energy policy establishing means ( 3 ) to implement an energy policy for the control of at least one energy consuming appliance ( 7 ) with which said energy node ( 5 ) is configured to communicate.

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Номер записи: 66
19-09-2013 дата публикации

Integer and Half Clock Step Division Digital Variable Clock Divider

Номер: US20130243148A1
Автор: Anthony Lell, Raguram Damodaran, Ramakrishnan Venkatasubramanian
Принадлежит: TEXAS INSTRUMENTS INCORPORATED

A clock divider is provided that is configured to divide a high speed input clock signal by an odd, even or fractional divide ratio. The input clock may have a clock cycle frequency of 1 GHz or higher, for example. The input clock signal is divided to produce an output clock signal by first receiving a divide factor value F representative of a divide ratio N, wherein the N may be an odd or an even integer. A fractional indicator indicates the divide ratio is N.5 when the fractional indicator is one and indicates the divide ratio is N when the fractional indicator is zero. F is set to 2(N.5)/2 for a fractional divide ratio and F is set to N/2 for an integer divide ratio. A count indicator is asserted every N/2 input clock cycles when N is even. The count indicator is asserted alternately N/2 input clock cycles and then 1+N/2 input clock cycles when N is odd. One period of an output clock signal is synthesized in response to each assertion of the count indicator when the fractional indicator indicates the divide ratio is N.5. One period of the output clock signal is synthesized in response to two assertions of the count indicator when the fractional indicator indicates the divide ratio is an integer.

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Номер записи: 67
19-09-2013 дата публикации

Information processing apparatus, information processing method, and medium

Номер: US20130245790A1
Автор: Hironori SAKAKIHARA
Принадлежит: Fujitsu Ltd

An information processing apparatus controls position measurement performed by a position measurement device. The apparatus includes a memory and a processor that executes a process in the memory. The process includes acquiring schedule information associated with the position measurement device and including a start time and an end time, acquiring position information acquired by the position measurement device, and extending a position measurement cycle of the position measurement device compared to a position measurement cycle before the start time of the schedule information when positions that respectively correspond to a plurality of pieces of position information acquired between the start time and the end time are in a given area.

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Номер записи: 68
19-09-2013 дата публикации

METHOD FOR ADAPTIVE PERFORMANCE OPTIMIZATION OF THE SOC

Номер: US20130246820A1
Автор: Branover Alexander J., Jain Ashish, Ling Ann M., Steinman Maurice B.
Принадлежит: Advanced Micro Devices, Inc.

An apparatus and method for dynamically adjusting power limits for processing nodes and other components, such as peripheral interfaces, is disclosed. The apparatus includes multiple processing nodes and other components, and further includes a power management unit configured to set a first frequency limit for at least one of the processing nodes responsive to receiving an indication of a first detected temperature greater than a first temperature threshold. Initial power limits are set below guard-band power limits for components that do not have reliable reporting of power consumption or for cost or power saving reasons. The amount of throttling of processing nodes is used to adjust the power limits for the processing nodes and these components. 1. A system comprising:a plurality of processing nodes;one or more interfaces to external devices; and increase a respective initial power limit for one or more of the plurality of processing nodes based at least on a respective initial power limit for the one or more interfaces;', 'maintain a respective count of throttling for each of the plurality of processing nodes during operation; and', 'in response to a count of throttling exceeding a first threshold within a time interval for a given processing node of the plurality of processing nodes, reduce the power limit for the given processing node., 'a power management unit configured to2. The system as recited in claim 1 , wherein in response to the count of throttling exceeding the first threshold within the time interval for the given processing node claim 1 , the power management unit is further configured to increase the power limit of at least one of the one or more interfaces based at least on the reduction of the power limit of the given processing node.3. The system as recited in claim 2 , wherein the power management unit is further configured to set the respective initial power limit for the one or more interfaces at a respective low power limit associated with ...

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Номер записи: 69
03-10-2013 дата публикации

Optimizing power consumption by dynamic workload adjustment

Номер: US20130261826A1
Автор: Nagapramod Mandagere, Pin Zhou, Sandeep M. Uttamchandani, Seshashayee S. Murthy
Принадлежит: International Business Machines Corp

A method and system for optimizing power consumption of a data center by dynamic workload adjustment. At least one candidate workload solution for the data center is generated. Each candidate workload solution represents a respective application map that specifies a respective workload distribution among application programs of the data center. Workload of the data center is dynamically adjusted from a current workload distribution to an optimal workload solution. The optimal workload solution is a candidate workload solution of the at least one candidate workload solution having a lowest sum of a respective power cost and a respective migration cost. Dynamically adjusting the workload of the data center includes: estimating a respective overall cost of each candidate workload solution, selecting the optimal workload solution that has a lowest overall cost as determined from the estimating, and transferring the optimal workload solution to devices of a computer system for deployment.

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Номер записи: 70
03-10-2013 дата публикации

Methods and apparatus to avoid surges in di/dt by throttling gpu execution performance

Номер: US20130262831A1
Автор: Jack Hilaire Choquette, Olivier Giroux, Peter Michael NELSON
Принадлежит: Nvidia Corp

Systems and methods for throttling GPU execution performance to avoid surges in DI/DT. A processor includes one or more execution units coupled to a scheduling unit configured to select instructions for execution by the one or more execution units. The execution units may be connected to one or more decoupling capacitors that store power for the circuits of the execution units. The scheduling unit is configured to throttle the instruction issue rate of the execution units based on a moving average issue rate over a large number of scheduling periods. The number of instructions issued during the current scheduling period is less than or equal to a throttling rate maintained by the scheduling unit that is greater than or equal to a minimum throttling issue rate. The throttling rate is set equal to the moving average plus an offset value at the end of each scheduling period.

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Номер записи: 71
03-10-2013 дата публикации

System-on-chip, electronic system including same, and method controlling same

Номер: US20130262894A1
Автор: Boo-Jin Kim, Jae Cheol Lee, Jong Hwan Choi, Jung Hi Min
Принадлежит: SAMSUNG ELECTRONICS CO LTD

A system-on-chip (SoC) operates with a memory device and includes a performance monitoring unit (PMU) that measures memory usage for the memory device, and a central processing unit (CPU) configured to implement a dynamic voltage frequency scaling (DVFS) controller that compares the memory usage during a performance monitoring period with a reference value and selects a control scheme accordingly.

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Номер записи: 72
03-10-2013 дата публикации

POWER EFFICIENT PROCESSOR ARCHITECTURE

Номер: US20130262902A1
Автор: Herdrich Andrew J., Illikkal Rameshkumar G., Iyer Ravishankar, Makineni Srihari, Moses Jaideep, Srinivasan Sadogopan
Принадлежит:

In one embodiment, the present invention includes a method for receiving an interrupt from an accelerator, sending a resume signal directly to a small core responsive to the interrupt and providing a subset of an execution state of the large core to the first small core, and determining whether the small core can handle a request associated with the interrupt, and performing an operation corresponding to the request in the small core if the determination is in the affirmative, and otherwise providing the large core execution state and the resume signal to the large core. Other embodiments are described and claimed. 1. An apparatus comprising:a first core to execute instructions;a second core to execute instructions, the second core heterogeneous to and smaller than the first core; anda logic to cause the second core and not the first core to be woken responsive to an interrupt when the first and second cores are in a low power state.2. The apparatus of claim 1 , wherein the logic is to always cause the second core and not the first core to be woken responsive to the interrupt.3. The apparatus of claim 1 , wherein the logic is to provide a subset of an execution state of the first core to the second core responsive to the interrupt.4. The apparatus of claim 3 , wherein the second core is to determine whether the second core can handle the interrupt claim 3 , and if not claim 3 , to cause a wakeup signal to be sent the first core.5. The apparatus of claim 4 , wherein responsive to the determination that the second core cannot handle the interrupt claim 4 , the logic is to obtain the subset of the execution state of the first core from the second core and to merge the execution state subset with a remainder of the execution state of the first core stored in a temporary storage area.6. The apparatus of claim 1 , wherein the apparatus comprises a multicore processor including the first and second cores and a power control unit (PCU) claim 1 , the PCU including the logic ...

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Номер записи: 73
10-10-2013 дата публикации

INFORMATION PROCESSING APPARATUS, CONTROL METHOD, AND COMPUTER-READABLE RECORDING MEDIUM

Номер: US20130268791A1
Автор: GOTSUBO Kenji, KONDOU Hiroshi, YAMANA Fumiaki
Принадлежит: FUJITSU LIMITED

An information processing apparatus includes a memory and a processor coupled to the memory. The processor is configured to: determine whether or not a difference between a total of power consumption values of physical or virtual computers and a preset upper-limit value satisfies a certain condition; select, in ascending order of priorities stored in a first storage and set based on details of processing executed by the computers, any of the computers as a target whose power consumption is to be reduced, when the difference satisfies the certain condition; and switch the computer selected to a state in which the power consumption is reduced. 1. An information processing apparatus comprising:a memory; anda processor coupled to the memory and configured to:determine whether or not a difference between a total of power consumption values of physical or virtual computers and a preset upper-limit value satisfies a certain condition;select, in ascending order of priorities stored in a first storage and set based on details of processing executed by the computers, any of the computers as a target whose power consumption is to be reduced, when the difference satisfies the certain condition; andswitch the computer selected to a state in which the power consumption is reduced.2. The information processing apparatus according to claim 1 ,wherein the processor is configured to switch the selected computer from an operating state in which the power consumption is relatively large to an operating state in which the power consumption is relatively small.3. The information processing apparatus according to claim 2 ,wherein, by referring to a second storage in which information indicating a limit value of the power consumption to be reduced when the operating state is switched for each computer, the processor is configured to assign an amount of reduction in a power consumption value to the computers in ascending order of the priorities thereof so that the amount of reduction is ...

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Номер записи: 74
17-10-2013 дата публикации

Dynamic Voltage and Frequency Management

Номер: US20130271179A1
Автор: von Kaenel Vincent R.
Принадлежит:

In one embodiment, an integrated circuit includes a self calibration unit configured to iterate a test on a logic circuit in the integrated circuit at respectively lower supply voltage magnitudes until the test fails. A lowest supply voltage magnitude at which the test passes is used to generate a requested supply voltage magnitude for the integrated circuit. In an embodiment, an integrated circuit includes a series connection of logic gates physically distributed over an area of the integrated circuit, and a measurement unit configured to launch a logical transition into the series and detect a corresponding transition at the output of the series. The amount of time between the launch and the detection is used to request a supply voltage magnitude for the integrated circuit. 1. An integrated circuit comprising:a logic circuit; anda self calibration unit within the integrated circuit and configured to execute a test on the logic circuit, wherein the self calibration unit is configured to iterate the test at respectively lower requested supply voltage magnitudes until the test fails, and wherein a lowest requested supply voltage magnitude at which the test passes is used to generate the requested supply voltage magnitude for operation of the integrated circuit, and wherein the test is programmable in the integrated circuit to an updated test after the integrated circuit has been provided to a user in a product, and wherein the self calibration unit is configured to iterate the updated test as programmed into the integrated circuit to determine the lowest requested supply voltage magnitude during operation by the user.2. The integrated circuit as recited in further comprising a local power manager coupled to the logic circuit and configured to transmit the indication of a requested supply voltage magnitude to an external power supply.3. The integrated circuit as recited in wherein the self calibration unit is configured to iterate the updated test and determine the ...

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Номер записи: 75
17-10-2013 дата публикации

Collaborative processor and system performance and power management

Номер: US20130275737A1
Автор: Andrew D. Henroid, Anil Aggarwal, Efraim Rotem, Eliezer Weissmann, Guy M. Therien, Jeremy J. Shrall, Krishnakanth V. Sistla, Paul S. Diefenbaugh
Принадлежит: Individual

The present invention relates to a platform power management scheme. In some embodiments, a platform provides a relative performance scale using one or more parameters to be requested by an OSPM system.

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Номер записи: 76
17-10-2013 дата публикации

Method and system for building a low power computer system

Номер: US20130275740A1
Автор: Townsend Jackson SMITH, III, Vihar Ramnath Rai, William Ernest MAPP, III
Принадлежит: SERVERGY, INC.

Various embodiments disclosed herein relate to an efficient computer server system comprising an efficient power supply unit utilizing a plurality of power-rails to supply electric power to the system components, a special-purpose processor configured to operate as an efficient general purpose server processor while maintaining high performance, and a platform manager configured to control the power supplied to the system components to minimize the system's overall power consumption. Some disclosed embodiments relate to a method of reducing power consumption in information handling server systems comprising configuring a special-purpose processor to be function as a general purpose server processor, selecting a set of power efficient system components based on performance and power efficiency, utilizing an efficient power supply unit and a platform manager to control the power supplied by the power supply unit, and adjusting the processor's frequency to achieve an optimal performance/power-consumption ratio.

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Номер записи: 77
17-10-2013 дата публикации

Mobile phone

Номер: US20130275786A1
Автор: Masahide Tanaka
Принадлежит: ROHM CO LTD

A main processor of mobile phone changes from power saving state to active state for changing display in response to a sub processor for sensors, the main processor returning to the power saving state after changing the display. The main processor changes from power saving state to active state for storing information from the sub processor, the main processor returning to the power saving state after the storing function. The main processor selects the stored display data on the basis of the information from the sub processor to change display. The main processor receives and stores information from the sub processor in the boot up process or before finishing the operation. The sub processor is in the active state so as to control the sensor even in a case where the main processor is in the power saving state.

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Номер записи: 78
17-10-2013 дата публикации

CREDIT BASED POWER MANAGEMENT

Номер: US20130275789A1
Автор: Maciocco Christian, Tai Tsung-Yuan C., Tsai Jr-Shian, Wang Ren
Принадлежит:

An embodiment may include circuitry to determine whether to issue at least one credit to at least one sender of at least one packet. The credit(s) may be to grant permission to the at least one sender to issue the at least one packet to at least one receiver of the at least one packet. The determination of whether to issue the credit(s) may be based, at least in part, upon whether a time in which the at least one receiver is in a relatively lower power state prior to issuance of the credit(s) is at least sufficient to provide at least a predetermined amount of reduction in power consumption. The relatively lower power state may be relative to a relatively higher power state of the at least one receiver that prevails at the issuance of the credit(s). Additionally or alternatively, the circuitry may be to receive such credit(s). 1. An apparatus comprising: determine, at least in part, whether to issue at least one credit to at least one sender of at least one packet, the at least one credit being to grant permission, at least in part, to the at least one sender to issue the at least one packet to at least one receiver of the at least one packet, determination of whether to issue the at least one credit being based, at least in part, upon whether a time in which the at least one receiver is in a relatively lower power state prior to issuance of the at least one credit is at least sufficient to provide at least a predetermined amount of reduction in power consumption, the relatively lower power state being relative to a relatively higher power state of the at least one receiver that prevails at the issuance of the at least one credit; and', 'receive, at least in part, the at least one credit., 'circuitry to at least one of2. The apparatus of claim 1 , wherein: quality of service associated, at least in part, with of the at least one packet; and', 'one or more patterns of previous network traffic., 'the determination is also based, at least in part, upon3. The apparatus ...

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Номер записи: 79
17-10-2013 дата публикации

Method and System for Tracking and Selecting Optimal Power Conserving Modes of a PCD

Номер: US20130275791A1
Автор: Norman S. Gargash, Tracy A. Ulmer
Принадлежит: Qualcomm Inc

A method and system for tracking and selecting optimal power conserving modes of a PCD includes detecting enablement or disablement of a reduced power mode and detecting one of a new and a change in a latency restriction. Next, a low power mode which has a minimum entry and exit latency may be identified. Then, it may be determined if a lowest latency restriction is less than the minimum entry and exit latency. A function pointer may be adjusted based on the output of the determining step. The function pointer may reference a halt state and a reduced power state for the PCD. Then, conditions favorable for at least one of an idle state and a reduced power mode of the PCD may be assessed. If conditions are favorable for an idle state or a reduced power mode for the PCD, then status of the function pointer may be read.

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Номер записи: 80
17-10-2013 дата публикации

Collaborative processor and system performance and power management

Номер: US20130275796A1
Автор: Andrew D. Henroid, Anil Aggarwal, Efraim Rotem, Eliezer Weissmann, Guy M. Therien, Jeremy J. Shrall, Krishnakanth V. Sistla, Paul S. Diefenbaugh
Принадлежит: Individual

The present invention relates to a platform power management scheme. In some embodiments, a platform provides a relative performance scale using one or more parameters to be requested by an OSPM system.

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Номер записи: 81
17-10-2013 дата публикации

Information processing apparatus, electrical power control method, and computer product

Номер: US20130276001A1
Автор: Ryosuke Oishi
Принадлежит: Fujitsu Ltd

An information processing apparatus includes a processor programmed to detect scheduled starting times of two events to be executed at a current time or thereafter; calculate a difference of the scheduled starting times of the two events, when the scheduled starting times of the two events have been detected; and correct, based on the calculated difference and to an extent that a restriction indicated in restriction information of an event to be corrected is observed, the scheduled starting time of at least any one of the two events, as the event to be corrected, such that an interval between the scheduled starting times of the two events is shortened.

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Номер записи: 82
24-10-2013 дата публикации

POWER SUPPLY CONTROL DEVICE AND SYSTEM USING THE SAME

Номер: US20130283071A1
Автор: Ushiro Takahiro
Принадлежит: CANON KABUSHIKI KAISHA

A power supply control circuit includes: a power supply unit that outputs the DC voltage for the load operation; a first switch of which opening/closing is controlled by applying the DC voltage from the power supply unit; a second switch which is manually operated to switch over the power supply; and a control unit. The second switch achieves a first state when not manually operated, and achieves a second state when manually operated. The control unit closes the first switch, if the second switch is changed to the second state and thereafter changed to the first state, when the second switch is in the first state and the DC voltage output from the power supply unit is not less than a predetermined value. 1. A power supply control device for equipment , comprising:a power supply unit which inputs AC power and outputs a DC voltage for operating a load inside the equipment;a first switch of which opening/closing is controlled by applying the DC voltage which is output by the power supply unit;a second switch which is manually operated to switch over ON/OFF of the power supply for the equipment, and achieves a first state when not manually operated and achieves a second state when manually operated, the second switch being connected to the first switch in series, the second switch reducing the DC voltage, which is output by the power supply unit, to less than a predetermined value when the first switch is closed, in the first state, and opens the first switch in the second state; anda control unit which closes the first switch so as to reduce the DC voltage to less than the predetermined value, if the second switch is changed to the second state and thereafter changed to the first state, when the second switch is in the first state and the DC voltage is not reduced to less than the predetermined value.2. The power supply control device according to claim 1 , wherein a state where the power supply of the equipment is turned on is a state where the first switch is opened ...

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Номер записи: 83
31-10-2013 дата публикации

System and method of controlling devices operating within different voltage ranges

Номер: US20130285731A1
Автор: Thomas H. Friddell
Принадлежит: Boeing Co

Semiconductor devices, systems, and methods are disclosed to facilitate power management. A method includes operating a first voltage range island of a semiconductor device within a first voltage range. The first voltage range includes a first midpoint. The first voltage range is provided in part by a voltage source that includes a tracking voltage regulator. The method also includes operating a second voltage range island of the semiconductor device within a second voltage range. The second voltage range includes a second midpoint. The first voltage range is different than the second voltage range.

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Номер записи: 84
31-10-2013 дата публикации

Frequency reduction of mobile device cores based on application processing requirements

Номер: US20130290751A1
Автор: Ashfaque Mansur, Kavitha Vallari Devara, Shyama Prasad Mondal
Принадлежит: Qualcomm Innovation Center Inc

This disclosure describes systems, methods, and apparatus for reducing power consumption of an application processor in a user equipment. State information of applications that indicate an expected load requirement that the applications will likely place on the application processor, can be used to control power management features of the application processor. For instance, an operating frequency of the application processor, or online cores of the application processor, can be reduced. The number of online cores (those that are not idled) can also be changed to tailor performance and power consumption to the load requirement. Other power management techniques such as adjusting core operational voltage can also be implemented.

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Номер записи: 85
31-10-2013 дата публикации

MEMORY COLUMN DROWSY CONTROL

Номер: US20130290753A1
Автор: HOEKSTRA GEORGE P., Jetton Mark W., Liston Thomas W., Ramaraju Ravindraraj, Russell Andrew C., Yang Jianan
Принадлежит:

In accordance with at least one embodiment, column level power control granularity is provided to control a low power state of a memory using a drowsy column control bit to control the low power state at an individual column level to protect the memory from weak bit failure. In accordance with at least one embodiment, a method of using a dedicated row of bit cells in a memory array is provided wherein each bit in the row controls the low power state of a respective column in the array. A special control signal is used to access the word line, and the word line is outside of the regular word line address space. A mechanism is provided to designate the weak bit column and set the control bit corresponding to that particular column to disable the drowsy/low power state for that column. 1. (canceled)2. (canceled)3. (canceled)4. (canceled)5. (canceled)6. (canceled)7. Apparatus comprising:a memory array comprising a plurality of memory cells organized according to a plurality of rows and a plurality of columns; anda control row comprising a plurality of power control memory cells for controlling power provided to the memory array, the plurality of power control memory cells organized according to the plurality of columns.8. The apparatus of wherein a power control memory cell of the control row controls a power state of a column of the plurality of columns.9. The apparatus of further comprising:a plurality of power control circuits coupled to the power control memory cells and to the memory array, the plurality of power control circuits for gating power to the memory array.10. The apparatus of wherein a power control memory cell of the plurality of power control memory cells stores a value that indicates a voltage provided to the memory cells corresponding to the power control memory cell.11. The apparatus of wherein the plurality of power control memory cells store power control data to select among the full voltage level and the reduced voltage level on a per column ...

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Номер записи: 86
07-11-2013 дата публикации

Energy Alert Power System and Method

Номер: US20130297959A1
Автор: Fisher Matthew T., Simon Timothy M., Smith Blaine M.
Принадлежит:

An energy control system, helping to reduce energy consumption from an energy grid, includes a power meter which receives first power-save signal and generates a second power-save signal for receipt by a control device. The target temperature of a thermostat is changed for a period of time in response to the second power-save signal. The control device can create a third power-save signal for receipt by a power-save adapter for an associated energy-consuming unit to permit only limited operation of the energy-consuming unit. 1. A method for temporarily reducing energy demand on an energy grid comprising:receiving, from a power company, a first power-save signal by a power meter of a user, the power meter being a remotely accessible power meter through which power is supplied to the user;transmitting a second power-save signal from the power meter to a control device, the control device associated with a thermostat;changing a target temperature of the thermostat to a power-save target temperature in response to the second power-save signal; andthe target temperature being changed to the power-save target temperature for a period of time chosen by the power company.2. The method according to claim 1 , wherein the first power save signal is received before a need to reduce power consumption.3. The method according to claim 1 , wherein the first power-save signal is a price event power-save signal; andoptionally overriding the first power-save signal by the user.4. The method according to claim 3 , further comprising:receiving a supplemental first power-save signal by the power meter, the supplemental first power-save signal being an emergency event power-save signal;transmitting a supplemental second power-save signal from the power meter to the control device;temporarily changing the target temperature of the thermostat to a supplemental power-save target temperature in response to the supplemental second power-save signal; andpreventing the user from overriding the ...

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Номер записи: 87
14-11-2013 дата публикации

Method and Apparatus for Monitoring Timing of Critical Paths

Номер: US20130300463A1
Автор: Gemmeke Tobias, Konijnenburg Mario
Принадлежит: STICHTING IMEC NEDERLAND

An apparatus for monitoring timing of a plurality of critical paths of a functional circuit includes a plurality of canary circuits, each configured to be coupled to a critical path of a functional circuit for detecting and outputting critical timing events. Each canary circuit includes an adjustable delay element and an analyser circuit for receiving a count of the critical timing event output from at least one of the plurality of canary circuits for a predetermined time interval for a plurality of delay values of the adjustable delay elements and for determining a probability distribution of critical timing events of the at least one of the plurality of critical paths for the predetermined time interval for the plurality of delay values. 1. Apparatus for monitoring timing of a plurality of critical paths of a functional circuit , the apparatus comprising:a plurality of canary circuits, each configured to be coupled to a critical path of a functional circuit for detecting and outputting critical timing events, each canary circuit including an adjustable delay element; andan analyser circuit for receiving a count of the critical timing event outputs from at least one of the plurality of canary circuits for a predetermined time interval for each of a plurality of delay values of the adjustable delay element of the at least one critical path and determining a probability distribution of critical timing events of the at least one of the plurality of critical paths for the predetermined time interval for the plurality of delay values.2. The apparatus according to claim 1 , wherein each of the plurality of canary circuits includes a canary register; wherein the adjustable delay element is coupled between the critical path and an input of the canary register; and wherein an output of the canary register indicates a critical timing event.3. The apparatus according to claim 2 , wherein each of the plurality of canary circuits are coupled to the input of a sequential ...

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Номер записи: 88
14-11-2013 дата публикации

Timing Controller Capable of Switching Between Graphics Processing Units

Номер: US20130300925A1
Автор: Culbert Michael F., Nugent Michael, Sakariya Kapil V.
Принадлежит: Apple Inc.

A display system is disclosed that is capable of switching between graphics processing units (GPUs). Some embodiments may include a display system, including a display, a timing controller (T-CON) coupled to the display, the T-CON including a plurality of receivers, and a plurality of GPUs, where each GPU is coupled to at least one of the plurality of receivers, and where the T-CON selectively couples only one of the plurality of GPUs to the display at a time. 1. A system , comprising:a display;a host computer;a plurality of graphics processing units (GPUs), wherein each GPU of the plurality of GPUs is configured to generate a respective one of a plurality of video image signals; and receive the plurality of video image signals;', 'process each video image signal of the plurality of video image signals;', 'send a first processed video image signal to the display;', 'select a second processed video image signal dependent upon a power consumption of a respective one of the plurality of GPUs; and', 'send the selected second processed video image signal to the display., 'a timing controller coupled to the host computer and the plurality of GPUs, wherein the timing controller is configured to2. The system of claim 1 , wherein each video image signal of the plurality of video image signals includes one or more synchronization signals.3. The system of claim 2 , wherein to process each video image signal of the plurality of video image signals claim 2 , the timing controller is further configured to determine one or more blanking intervals dependent upon the one or more synchronization signals.4. The system of claim 2 , wherein the one or more synchronization signals include a frame synchronization signal and a lines synchronization signal.5. The system of claim 1 , wherein to process each video image signal of the plurality of video image signals claim 1 , the timing controller is further configured to translate each video image signal of the plurality of video image ...

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Номер записи: 89
14-11-2013 дата публикации

Dynamic management of thermal loads

Номер: US20130305067A1
Автор: Charles Robert Lefurgy, Freeman Leigh Rawson, III, Guillermo Jesus Silva
Принадлежит: International Business Machines Corp

A method, system, and computer program product for dynamic management of thermal load in a data processing system are provided in the illustrative embodiments. A component of the data processing system is identified whose temperature has reached a temperature threshold, the component forming a critical component. A workload is selected from a set of workloads that is using the critical component. The workload is modified such that work performed by the critical component is reduced, the modifying further causing the temperature of the critical component to reduce below the temperature threshold. A power consumption of a cooling system associated with the thermal zone is reduced responsive to the temperature reducing below the temperature threshold.

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Номер записи: 90
21-11-2013 дата публикации

Intelligent power controller

Номер: US20130311796A1
Автор: Benoit de Lescure, Raymond G. Brinks, Stephen W. Hamilton
Принадлежит: Sonics Inc

A method, apparatus, and system in which an interconnect for an integrated circuit communicates transactions between one or more initiator Intellectual Property (IP) cores and one or more target IP cores coupled to the interconnect, including a power manager having a hierarchy of two or more layers including a hardware logic portion to control a power consumption of two or more domains in the integrated circuit, where each layer of the power manager performs its own function; wherein the power manager has its own dedicated CPU or dedicated state machine to execute power management instructions; and wherein the power manager controls the power consumption of two or more domains without using a CPU IP core utilized by other IP cores on the integrated circuit to execute power management instructions.

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Номер записи: 91
21-11-2013 дата публикации

ENERGY-SAVING DEVICE AND METHOD FOR PORTABLE TERMINAL

Номер: US20130311803A1
Автор: Wang XiaoWei, Yin Tianci
Принадлежит: ZTE CORPORATION

An energy-saving apparatus and method for a portable terminal are disclosed in the present document. The apparatus includes: an electricity meter module, configured to detect battery power consumption parameters under driving of a data acquisition module; the data acquisition module, configured to drive the detection of the electricity meter module, and output the collected battery power consumption parameters to a data analysis module; the data analysis module, configured to estimate power consumptions of all running devices at present in the terminal according to the input battery power consumption parameters, and output a power consumption optimization instruction to a power consumption optimization execution module; and the power consumption optimization execution module, configured to adopt corresponding power consumption optimization approaches according to the input power consumption optimization instruction. 1. An energy-saving apparatus for a portable terminal , comprising an electricity meter module , a data acquisition module , a data analysis module and a power consumption optimization execution module , wherein:the electricity meter module is configured to: detect battery power consumption parameters under driving of the data acquisition module;the data acquisition module is configured to: drive the detection of the electricity meter module, and output the collected battery power consumption parameters to the data analysis module;the data analysis module is configured to: estimate power consumptions of all currently running devices in the terminal according to the input battery power consumption parameters, and output a power consumption optimization instruction to the power consumption optimization execution module; andthe power consumption optimization execution module is configured to: adopt corresponding power consumption optimization approaches according to the input power consumption optimization instruction.2. The apparatus according to claim 1 , ...

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Номер записи: 92
21-11-2013 дата публикации

REDUCED POWER STATE NETWORK PROCESSING

Номер: US20130311809A1
Автор: Sood Kapil
Принадлежит:

Technologies for reduced power network processing include a main processor, a low-power co-processor, and a network interface controller. The network interface controller receives one or more network packets while the computing device is in a sleep state, filters the one or more network packets to identify network packets to be handled by the low-power co-processor without waking the main processor from the sleep state, and wakes the low-power co-processor, without waking the main processor, to handle at least one network packet of the identified network packets to be handled by the low-power co-processor. 1. A computing device for operating in a sleep state , the computing device comprising:a main processor;a low-power co-processor; anda network interface controller to (i) receive one or more network packets while the computing device is in a sleep state, (ii) filter the one or more network packets to identify network packets to be handled by the low-power co-processor without waking the main processor from the sleep state, and (iii) wake the low-power co-processor, without waking the main processor, to handle at least one network packet of the identified network packets to be handled by the low-power co-processor.2. The computing device of claim 1 , wherein the low-power co-processor comprises a manageability engine to perform remote attestation.3. The computing device of claim 1 , wherein each of the main processor and the low-power co-processor is to operate in a low-power state when in the sleep state.4. The computing device of claim 1 , further comprising a second low-power co-processor claim 1 , wherein:the low-power co-processor is a first low-power co-processor; andthe network interface controller is to (i) filter the one or more network packets to identify network packets to be handled by the second low-power co-processor without waking the main processor from the sleep state and (ii) wake the second low-power co-processor, without waking the main ...

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Номер записи: 93
21-11-2013 дата публикации

DISTRIBUTED SYSTEM, DEVICE, METHOD, AND PROGRAM

Номер: US20130312004A1
Автор: KAN MASAKI, Kobayashi Dai, Ohno Yoshiyuki
Принадлежит: NEC Corporation

A distributed system includes: a plurality of ordinary nodes provided with reduced-power states having different times of recovery to a normal operating state; and a management node for assigning a job to an ordinary node for carrying out the job. The management node has: node select means for selecting an ordinary node from ordinary nodes each put in one of the reduced-power states, assigning a job to the selected ordinary node and driving the selected ordinary node to carry out the assigned job; and node control means for executing control to restore an ordinary node selected by the node select means to the normal operating state. The node select means selects an ordinary node from the ordinary nodes each put in one of the reduced-power states having different times of recovery to the normal operating state in accordance with an ordinary-node order starting with an ordinary node existing in a reduced-power state and having a short time of recovery to the normal operating state. 1. A distributed system comprising: a plurality of ordinary nodes which can each be put in any one of reduced-power states having different times of recovery to a normal operating state; and a management node for assigning a job to said ordinary nodes and for driving said ordinary nodes to carry out said assigned job ,wherein said management node has: a node select unit for selecting an ordinary node from said ordinary nodes each put in one of said reduced-power states, assigning a job to said selected ordinary node and driving said selected ordinary node to carry out said assigned job; and a node control unit for executing control to restore said ordinary node selected by said node select unit to said normal operating state, andwherein said node select unit selects an ordinary node from said ordinary nodes each put in one of said reduced-power states having different times of recovery to said normal operating state in accordance with an ordinary-node order starting with said ordinary node ...

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Номер записи: 94
28-11-2013 дата публикации

DISTRIBUTION OF TASKS AMONG ASYMMETRIC PROCESSING ELEMENTS

Номер: US20130318373A1
Автор: Carmean Doug, Hum Herbert, Kumar Rajesh, Sprangle Eric
Принадлежит:

Techniques to control power and processing among a plurality of asymmetric cores. In one embodiment, one or more asymmetric cores are power managed to migrate processes or threads among a plurality of cores according to the performance and power needs of the system 1a graphics processing unit;a memory controller;an input-output (I/O) unit;video control unit;a digital signal processing unit;a cache;a first and second processing cores, and a third low-power processing core having the same instruction set architecture, wherein the first and second processing cores are able to operate at a higher performance level than the third low-power processing core and wherein the first and second processing cores are able to operate at a higher power consumption level than the third low-power processing core, wherein high performance tasks are to be performed by the first and second cores and tasks requiring lower performance relative to the high performance tasks are able to be performed by the third low-power processing core; andhardware logic to help software to monitor an activity level of the first and second processing cores and the third low-power processing core and migrate tasks between the processing cores, in response to monitoring the activity level, to optimize performance and power of the processing system.. A processing system comprising: This Application is a Continuation, which claims benefit under 35 USC §120 of application Ser. No. 12/220,092, filed Jul. 22, 2008, currently pending; which claims benefit under 35 USC §119(e) of Provisional Application Ser. No. 61/067,737, filed Feb. 29, 2008.Embodiments of the invention relate generally to the field of information processing and more specifically, to the field of distributing program tasks among various processing elements.As more processing throughput is required from modern microprocessors, it is often at the expense of power consumption. Some applications, such as mobile internet devices (MIDs), ultra-mobile ...

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Номер записи: 95
28-11-2013 дата публикации

DISTRIBUTION OF TASKS AMONG ASYMMETRIC PROCESSING ELEMENTS

Номер: US20130318374A1
Автор: Carmean Doug, Hum Herbert, Kumar Rajesh, Sprangle Eric
Принадлежит:

Techniques to control power and processing among a plurality of asymmetric cores. In one embodiment, one or more asymmetric cores are power managed to migrate processes or threads among a plurality of cores according to the performance and power needs of the system 1a graphics processing unit;a memory controller;an input-output (I/O) unit;video control unit;a digital signal processing unit;a cache;a first and second processing cores, and a third low-power processing core having the same instruction set architecture, wherein the first and second processing cores are able to operate at a higher performance level than the third low-power processing core and wherein the first and second processing cores are able to operate at a higher power consumption level than the third low-power processing core, wherein high performance tasks are to be performed by the first and second cores and tasks requiring lower performance relative to the high performance tasks are able to be performed by the third low-power processing core; andsoftware to monitor an activity level of the first and second processing cores and the third low-power processing core and migrate tasks between the processing cores, in response to monitoring the activity level, to optimize performance and power of the processing system.. A processing system comprising: This Application is a Continuation, which claims benefit under 35 USC §120 of application Ser. No. 12/220,092, filed Jul. 22, 2008, currently pending; which claims benefit under 35 USC §119(e) of Provisional Application Ser. No. 61/067,737, filed Feb. 29, 2008.Embodiments of the invention relate generally to the field of information processing and more specifically, to the field of distributing program tasks among various processing elements.As more processing throughput is required from modern microprocessors, it is often at the expense of power consumption. Some applications, such as mobile internet devices (MIDs), ultra-mobile personal computers ( ...

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Номер записи: 96
28-11-2013 дата публикации

DATA PROCESSING SYSTEM HAVING POWER CAPPING FUNCTION IN RESPONSE TO OUTPUT STATE OF POWER SUPPLY MODULE

Номер: US20130318376A1
Автор: Hasegawa Koichi, MURE Yusuke, Sawai Ryo, Taniguchi Kazuya
Принадлежит: Hitachi, Ltd.

A data processing system includes a plurality of power supply modules each having a comparing unit for comparing an output-current value supplied to a computer with a threshold value, the plurality of power supply modules continue the comparison when the output-current value is equal to or less than the threshold value and outputs an output-current excess signal to a plurality of server blades when the output-current value is equal to or greater than the threshold value, and the plurality of server blades control respectively power consumptions of the server blades to make a power consumption value of the server blades to an equal to or less than a predetermined value on a power source non-redundancy. 1wherein the power supply module includes a power-source supply line connected electrically with the input power source and the computer, a current measurement unit which measures an output-current value supplied to the computer on the power source supply line, and a comparing unit which compares the measured output current value with a predetermined threshold value,and wherein by comparing the output current value with the threshold value in the comparing unit,when the output current value is equal to or smaller than the threshold value, the power supply module continues the comparison,when the output current value is greater than the threshold value, the power supply module outputs an output-current excess signal to the plurality of server blades, and the plurality of server blades control a power consumption of the each server blade to an equal to or smaller than a power consumption value Wp of the server blades on a power source non-redundancy.. A data processing system comprising a plurality of computers, a plurality of input power sources, a plurality of power supply modules that convert a power supplied from the input power source into a voltage to output to the computers, and a management module connected with the computers and the power supply modules via ...

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Номер записи: 97
28-11-2013 дата публикации

SCHEDULING TASKS AMONG PROCESSOR CORES

Номер: US20130318379A1
Автор: Mansoor Illyas, Muralidhar Rajeev, Rudramuni Vishwesh M., Seshadri Harinarayanan
Принадлежит:

Embodiments of apparatus, computer-implemented methods, computing devices, systems, and computer-readable media (transitory and non-transitory) are described herein for scheduling a plurality of tasks among a plurality of processor cores. A first processor core of a plurality of processor cores of a computing device may be transitioned to a shielded state, in which no new tasks are to be assigned to the first processor core and tasks already assigned to the first processor core are executed to completion, in response to a determination that a criterion has been met. In various embodiments, the criterion may be based on a condition of the computing device, such as power available to the computing device or a temperature associated with the computing device. In various embodiments, the first processor core may transition to a reduced-power state after the tasks already assigned to the first processor core execute completion. 1. At least one non-transitory computer-readable medium having computer-readable code embodied therein , the computer-readable code comprising instructions configured to enable a computing device , in response to execution of the instructions by the computing device , to transition a first processor core of a plurality of processor cores of the computing device to a shielded state , in which no new tasks are to be assigned to the first processor core and one or more tasks already assigned to the first processor core are executed to completion , in response to a determination that a criterion has been met , the criterion based at least in part on a condition of the computing device , and to transition the first processor core to a reduced-power state after the one or more tasks already assigned to the first processor core are executed to completion.2. The at least one computer-readable medium of claim 1 , wherein the reduced-power state comprises a state in which one or more core phase lock loops associated with the first processor core are shut ...

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Номер записи: 98
28-11-2013 дата публикации

POWER MANAGEMENT APPARATUS, IMAGE FORMING APPARATUS AND POWER MANAGEMENT METHOD

Номер: US20130318384A1
Автор: Yoshihara Toshio
Принадлежит: CANON KABUSHIKI KAISHA

A sleep mode in which power consumption is reduced to a prescribed value or smaller is achieved, while convenience for a user is maintained by shortening the time taken to recover from the sleep mode. The temperature of an LSI is measured or estimated when shifting to the sleep mode, and an apparatus enters a power supply shutoff sleep mode using power supply separation or a clock-gating sleep mode in accordance with the measured or estimated value of the temperature. In the case where power supply shutoff is selected, after entering the sleep mode, power supply is resumed and then the apparatus enters the clock-gating sleep mode in accordance with the measured temperature or the estimated temperature of the LSI. 1. A power management apparatus for a circuit including a power shutoff domain that can be shut off independently of another domain of the circuit , the apparatus comprising:a power management unit that turns the power shutoff domain on and off;a clock generating unit that stops and supplies a clock signal to the power shutoff domain; anda control unit that, if a condition for shifting to a sleep mode is satisfied, controls the clock generation unit to stop the clock signal and shifts to the sleep mode in a case where a measured or estimated temperature of the circuit is lower than a predetermined value, and in other cases, controls the power management unit to turn the power shutoff domain off and shifts to the sleep mode.2. The power management apparatus according to claim 1 ,wherein, in the case where the control unit has controlled the power management unit to turn the power shutoff domain off and has shifted to the sleep mode, the control unit controls the power management unit to turn the power shutoff domain on, thereafter controls the clock generation unit to stop the clock signal in the sleep mode, if the measured or estimated temperature of the circuit is lower than the predetermined value.3. The power management apparatus according to claim 1 , ...

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Номер записи: 99
28-11-2013 дата публикации

System and Method of Modifying Power Use within an Information Handling System

Номер: US20130318386A1
Автор: Khatri Mukund P., Loffink John S.
Принадлежит:

A system and method of modifying power use within an information handling system is disclosed. In one form, a method of managing power within an information handling system is disclosed. The method can include establishing a threshold power level of a first information handling system, and detecting a first power demand of a first operating state in excess of the threshold power level. The method can also include detecting a request to invoke a first forced reduced power state of the first information handling system, and determining a first alternative power state different from the threshold power level and the first forced reduced power state. The method can further include initiating the first alternative power state. 1. A method of managing power within an information handling system , the method comprising:establishing a threshold power level of the information handling system;detecting that a power level of a first power demand of a first operating state of the information handling system is in excess of the threshold power level;detecting a request to invoke a forced reduced power state of the information handling system;determining an alternative power state, wherein a power level of the alternative power state is different from the threshold power level and a power level of the forced reduced power state;initiating the alternative power state;detecting that the power level of the alternative power state exceeds the threshold power level; andcontinually switching between different forced reduced power states and different alternative power states until a power level of a current alternative power state is below the threshold power level, wherein each successive forced reduced power state is higher than a previous forced reduced power state, and each successive alternative power state is lower than a previous alternative power state.2. The method of claim 1 , further comprising:determining the alternative power state from an operating characteristic of the ...

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Номер записи: 100