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Небесная энциклопедия

Космические корабли и станции, автоматические КА и методы их проектирования, бортовые комплексы управления, системы и средства жизнеобеспечения, особенности технологии производства ракетно-космических систем

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Мониторинг СМИ

Мониторинг СМИ и социальных сетей. Сканирование интернета, новостных сайтов, специализированных контентных площадок на базе мессенджеров. Гибкие настройки фильтров и первоначальных источников.

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Применить Всего найдено 21437. Отображено 100.
12-01-2012 дата публикации

Method and apparatus for wireless broadband systems direct data transfer

Номер: US20120011295A1
Автор: Assaf Touboul, Meir Tsadik, Moshe Tanach
Принадлежит: DESIGNART NETWORKS LTD

Apparatus and method for direct data transfer in a wireless broadband system having an operating system, the apparatus including a central processing unit (CPU), at least one dedicated Direct Memory Access unit (DMA) local to the CPU, coupled directly to the CPU, and a commands FIFO (First In First Out) receiving commands from the CPU and automatically transferring the commands in sequence to the DMA for implementation by the DMA, in the absence of intervention by the operating system.

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Номер записи: 1
09-02-2012 дата публикации

Systems and methods for using a shared buffer construct in performance of concurrent data-driven tasks

Номер: US20120036288A1
Автор: David Goodwin, Peter Mattson
Принадлежит: Calos Fund LLC

Disclosed herein are techniques to execute tasks with a computing device. A first task is initiated to perform an operation of the first task. A buffer construct that represents a region of memory accessible to the operation of the first task is created. A second task is initiated to perform of an operation of the second task that is configured to be timed to initiate in response to the buffer construct being communicated to the second task from the first task.

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Номер записи: 2
09-02-2012 дата публикации

Data Flow Control Within and Between DMA Channels

Номер: US20120036289A1
Автор: Dominic Go, Mark D. Hayter, Puneet Kumar
Принадлежит: Individual

In one embodiment, a direct memory access (DMA) controller comprises a transmit circuit and a data flow control circuit coupled to the transmit circuit. The transmit circuit is configured to perform DMA transfers, each DMA transfer described by a DMA descriptor stored in a data structure in memory. There is a data structure for each DMA channel that is in use. The data flow control circuit is configured to control the transmit circuit's processing of DMA descriptors for each DMA channel responsive to data flow control data in the DMA descriptors in the corresponding data structure.

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Номер записи: 3
22-03-2012 дата публикации

Memory system having high data transfer efficiency and host controller

Номер: US20120072618A1
Автор: Akihisa Fujimoto
Принадлежит: Individual

According to one embodiment, the host controller includes a register set to issue command, and a direct memory access (DMA) unit and accesses a system memory and a device. First, second, third and fourth descriptors are stored in the system memory. The first descriptor includes a set of a plurality of pointers indicating a plurality of second descriptors. Each of the second descriptors comprises the third descriptor and fourth descriptor. The third descriptor includes a command number, etc. The fourth descriptor includes information indicating addresses and sizes of a plurality of data arranged in the system memory. The DMA unit sets, in the register set, the contents of the third descriptor forming the second descriptor, from the head of the first descriptor as a start point, and transfers data between the system memory and the host controller in accordance with the contents of the fourth descriptor.

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Номер записи: 4
12-04-2012 дата публикации

Query sampling information instruction

Номер: US20120089816A1
Автор: Damian L. Osisek, Donald W. Schmidt, Jane H. Bartik, Lisa Cranton Heller, Patrick M. West, Jr., Phil C. Yeh
Принадлежит: International Business Machines Corp

A measurement sampling facility takes snapshots of the central processing unit (CPU) on which it is executing at specified sampling intervals to collect data relating to tasks executing on the CPU. The collected data is stored in a buffer, and at selected times, an interrupt is provided to remove data from the buffer to enable reuse thereof. The interrupt is not taken after each sample, but in sufficient time to remove the data and minimize data loss.

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Номер записи: 5
26-04-2012 дата публикации

Solid State Drive Architecture

Номер: US20120102263A1
Автор: Ajoy Aswadhati
Принадлежит: FASTOR SYSTEMS Inc

Embodiments of apparatuses, methods and systems of solid state drive are disclosed. One embodiment of a solid state drive includes a non-blocking fabric, wherein the non-blocking fabric comprises a plurality of ports, wherein a subset of the plurality of ports are each connected to a flash controller that is connected to at least one array of flash memory. Further, this embodiment includes a flash scheduler for scheduling data traffic through the non-blocking fabric, wherein the data traffic comprises a plurality of data packets, wherein the flash scheduler extracts flash fabric header information from each of the data packets and schedules the data traffic through the non-blocking fabric based on the extracted flash fabric header information. The scheduled data traffic provides transfer of data packets through the non-blocking fabric from at least one array of flash memory to at least one other array of flash memory.

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Номер записи: 6
10-05-2012 дата публикации

Fencing Direct Memory Access Data Transfers In A Parallel Active Messaging Interface Of A Parallel Computer

Номер: US20120117281A1
Автор: Amith R. Mamidala, Michael A. Blocksome
Принадлежит: International Business Machines Corp

Fencing direct memory access (‘DMA’) data transfers in a parallel active messaging interface (‘PAMI’) of a parallel computer, the PAMI including data communications endpoints, each endpoint including specifications of a client, a context, and a task, the endpoints coupled for data communications through the PAMI and through DMA controllers operatively coupled to segments of shared random access memory through which the DMA controllers deliver data communications deterministically, including initiating execution through the PAMI of an ordered sequence of active DMA instructions for DMA data transfers between two endpoints, effecting deterministic DMA data transfers through a DMA controller and a segment of shared memory; and executing through the PAMI, with no FENCE accounting for DMA data transfers, an active FENCE instruction, the FENCE instruction completing execution only after completion of all DMA instructions initiated prior to execution of the FENCE instruction for DMA data transfers between the two endpoints.

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Номер записи: 7
17-05-2012 дата публикации

Technique for communicating interrupts in a computer system

Номер: US20120124264A1
Автор: James B. Crossland, Keshavan Tiruvallur, Luke Hood, Rajesh Parthasarathy, Shivnanda Kaushik
Принадлежит: Individual

A technique to enable efficient interrupt communication within a computer system. In one embodiment, an advanced programmable interrupt controller (APlC) is interfaced via a set of bits within an APIC interface register using various interface instructions or operations, without using memory-mapped input/output (MMIO).

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Номер записи: 8
17-05-2012 дата публикации

Serial i/o using jtag tck and tms signals

Номер: US20120124438A1
Автор: Lee D. Whetsel
Принадлежит: Texas Instruments Inc

The present disclosure describes a novel method and apparatus of using the JTAG TAP's TMS and TCK terminals as a general purpose serial Input/Output (I/O) bus. According to the present disclosure, the TAP's TMS terminal is used as a clock signal and the TCK terminal is used as a bidirectional data signal to allow serial communication to occur between; (1) an IC and an external controller, (2) between a first and second IC, or (3) between a first and second core circuit within an IC.

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Номер записи: 9
31-05-2012 дата публикации

Computing device and serial communication method of the computing device

Номер: US20120137035A1
Автор: Ji-Zhi Yin, Jian Peng
Принадлежит: Hon Hai Precision Industry Co Ltd, Hongfujin Precision Industry Shenzhen Co Ltd

A serial communication method is applied in a computing device to communicate serially with any external serial device. The computing device includes a baseboard management controller (BMC) and an operating system (OS). The BMC includes at least one physical serial port. The method generates a virtual serial port for the OS by emulating serial port functionality of the physical serial port. When the BMC is initializing the physical serial port and a serial device is connected to the physical serial port, an interrupt handler is activated to handle an interrupt triggered to the BMC by the serial device. The interrupt handler is deactivated when the physical serial port has been initialized by the BMC.

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Номер записи: 10
07-06-2012 дата публикации

Memory address re-mapping of graphics data

Номер: US20120139927A1
Автор: Aditya Navale, Balaji Vembu, Wishwesh A. Gandhi
Принадлежит: Individual

A method and apparatus for creating, updating, and using guest physical address (GPA) to host physical address (HPA) shadow translation tables for translating GPAs of graphics data direct memory access (DMA) requests of a computing environment implementing a virtual machine monitor to support virtual machines. The requests may be sent through a render or display path of the computing environment from one or more virtual machines, transparently with respect to the virtual machine monitor. The creating, updating, and using may be performed by a memory controller detecting entries sent to existing global and page directory tables, forking off shadow table entries from the detected entries, and translating GPAs to HPAs for the shadow table entries.

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Номер записи: 11
21-06-2012 дата публикации

Direct memory access (dma) controlled stimulation

Номер: US20120158096A1
Автор: Neil S. Sherman
Принадлежит: Spinal Modulation LLC

An implantable stimulation system (e.g., an implantable neurostimulation system (INS)) comprises memory including a first table and a second table. The first table stores blocks of stimulation event data corresponding to stimulation events that are to be performed during a period of time (e.g., a 0.5 sec. or 1 sec. period of time). The second table stores blocks of next stimulation event time data corresponding to the period of time. The implantable stimulation system also includes a direct memory access (DMA) controller including a first DMA channel and a second DMA channel. The first DMA channel selectively transfers one of the blocks stimulation event data from the first table to one or more registers that are used to control stimulation events. The second DMA channel selectively transfers one of the blocks of next stimulation event time data from the second table to a timer that is used to control timing associated with the stimulation events. In this manner, the DMA controller is able to control stimulation.

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Номер записи: 12
21-06-2012 дата публикации

System and method for peripheral device communications

Номер: US20120159018A1
Автор: Alon Tsafrir, Mark N. Fullerton, Ofer Bar-Shalom
Принадлежит: Alon Tsafrir, Fullerton Mark N, Ofer Bar-Shalom

A method for operating a host device includes comparing a predetermined response of a peripheral device to a response token received from the peripheral device. The predetermined response and the response token are generated based on a first command transmitted from the host device to the peripheral device. The method further includes controlling a transfer of first data from a first memory to a peripheral control module based on the comparison between the predetermined response and the response token without interrupting a host control module, and selectively passing interrupts to the host control module when the predetermined response does not match the response token.

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Номер записи: 13
21-06-2012 дата публикации

Memory Module With Reduced Access Granularity

Номер: US20120159061A1
Автор: Craig E. Hampel, Frederick A. Ware
Принадлежит: RAMBUS INC

A memory module having reduced access granularity. The memory module includes a substrate having signal lines thereon that form a control path and first and second data paths, and further includes first and second memory devices coupled in common to the control path and coupled respectively to the first and second data paths. The first and second memory devices include control circuitry to receive respective first and second memory access commands via the control path and to effect concurrent data transfer on the first and second data paths in response to the first and second memory access commands.

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Номер записи: 14
21-06-2012 дата публикации

Ieee 1149.1 and p1500 test interfaces combined circuits and processes

Номер: US20120159275A1
Автор: Lee D. Whetsel
Принадлежит: Texas Instruments Inc

In a first embodiment a TAP of IEEE standard 1149.1 is allowed to commandeer control from a WSP of IEEE standard P1500 such that the P1500 architecture, normally controlled by the WSP, is rendered controllable by the TAP. In a second embodiment (1) the TAP and WSP based architectures are merged together such that the sharing of the previously described architectural elements are possible, and (2) the TAP and WSP test interfaces are merged into a single optimized test interface that is operable to perform all operations of each separate test interface. One approach provides for the TAP to maintain access and control of the TAP instruction register, but provides for a selected data register to be accessed and controlled by either the TAP+ATC or by the discrete CaptureDR, UpdateDR, TransferDR, ShiftDR, and ClockDR WSP data register control signals.

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Номер записи: 15
28-06-2012 дата публикации

Selectively enabling a host transfer interrupt

Номер: US20120166685A1
Автор: Jing Booth, Rebekah A. Wilson
Принадлежит: Western Digital Technologies Inc

Embodiments of the invention are directed to systems and methods for reducing the number of interrupts on a controller for a non-volatile storage device to improve data transfer performance of the storage system. The embodiments described herein selectively enable an interrupt generated by host transfer hardware for a host command. The interrupt can be enabled or disabled by considering the command type, availability of interface resources to accept additional host transfers, and the command size. Embodiments described herein are useful for host interfaces implementing a tagging scheme for host transfers with a limited range of identification tags.

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Номер записи: 16
26-07-2012 дата публикации

System and methods for protecting users from malicious content

Номер: US20120192277A1
Автор: Bjorn Markus Jakobsson, William Leddy
Принадлежит: Individual

A method, system and device for allowing the secure collection of sensitive information is provided. The device includes a display, and a user interface capable of receiving at least one user-generated interrupt in response to a stimulus generated in response to content received by the device, wherein the action taken upon receiving the user-generated interrupt depends on a classification of the content, the classification identifying the content as trusted or not trusted. The method includes detecting a request for sensitive information in content, determining if an interrupt is generated, determining if the content is trusted, allowing the collection of the sensitive information if the interrupt is generated and the content is trusted, and performing an alternative action if the interrupt is generated and the content is not trusted. The method may include instructions stored on a computer readable medium.

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Номер записи: 17
13-09-2012 дата публикации

Host device suspending communication link to client device based on client device notification

Номер: US20120233361A1
Автор: Anand Dalal, Haining Zhang, Mitchell D. Adler
Принадлежит: Apple Inc

A communication link between a host device and a client device can be suspended based on a suspend request or notification provided by the client device. The suspend request can be transmitted by a client device to a host device if the client device determines that suspension is appropriate, and can be sent in response to receiving a polling request from the host device. After receiving a suspend request, the host device can initiate an operation to suspend the communication link between the devices.

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Номер записи: 18
13-09-2012 дата публикации

Data transfer control device, integrated circuit of same, data transfer control method of same, data transfer completion notification device, integrated circuit of same, data transfer completion notification method of same, and data transfer control system

Номер: US20120233372A1
Автор: Hideki Taniguchi, Masaaki Harada, Satomi Amano, Satoru Kuriki, Yuusaku Ohta
Принадлежит: Panasonic Corp

A data transfer control device 1061 includes a read pointer update unit 5004 updating a value of a global read pointer RPg with a value of a local read pointer (first local read pointer) RP 11 held by a local read pointer hold unit 5007 when completion of data transfer is recognized and a position, in an order of reading descriptors, of a descriptor D 3010 a indicated by the local read pointer RP 11 is earlier than positions of descriptors D 3010 b and D 3010 c respectively indicated by local read pointers (second local read pointers) RP 12 and RP 13 held by the other data transfer control devices 1062 and 1063.

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Номер записи: 19
13-09-2012 дата публикации

Meta Garbage Collection for Functional Code

Номер: US20120233592A1
Автор: Alexander G. Gounares
Принадлежит: Concurix Corp

An execution environment for functional code may treat application segments as individual programs for memory management. A larger program of application may be segmented into functional blocks that receive an input and return a value, but operate without changing state of other memory objects. The program segments may have memory pages allocated to the segments by the operating system as other full programs, and may deallocate memory pages when the segments finish operating. Functional programming languages and imperative programming languages may define program segments explicitly or implicitly, and the program segments may be identified at compile time or runtime.

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Номер записи: 20
25-10-2012 дата публикации

Data transfer system and data transfer method

Номер: US20120271973A1
Автор: Masaharu Adachi
Принадлежит: Ricoh Co Ltd

A data transfer system includes: a processor; a main memory that is connected to the processor; a peripheral controller that is connected to the processor; and a peripheral device that is connected to the peripheral controller and includes a register set, wherein the peripheral device transfers data stored in the register set to a predetermined memory region of the main memory or the processor by a DMA (Data Memory Access) transfer, and the processor reads out the data transferred to the memory region by the DMA transfer without accessing to the peripheral device.

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Номер записи: 21
13-12-2012 дата публикации

Storage architecture for backup application

Номер: US20120317379A1
Автор: Abid Ali, Amit Singla, Pankaj Khanzode, Sachin Durge, Vanita Prabhu, Vijay Sen
Принадлежит: Microsoft Corp

Aspects of the subject matter described herein relate to a storage architecture. In aspects, an address provided by a data source is translated into a logical storage address of virtual storage. This logical storage address is translated into an identifier that may be used to store data on or retrieve data from a storage system. The address space of the virtual storage is divided into chunks that may be streamed to the storage system.

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Номер записи: 22
27-12-2012 дата публикации

Delivering Interrupts Directly To A Virtual Processor

Номер: US20120331467A1
Автор: Andrew V. Anderson, Erik C. Cota-Robles, Gilbert Neiger, Rajesh Sankaran Madukkarumukumana, Richard A. Uhlig, Sebastian Schoenberg, Sridhar Muthrasanallur, Steven M. Bennett, Udo Steinberg
Принадлежит: Individual

Embodiments of apparatuses, methods, and systems for delivering an interrupt to a virtual processor are disclosed. In one embodiment, an apparatus includes an interface to receive an interrupt request, delivery logic, and exit logic. The delivery logic is to determine, based on an attribute of the interrupt request, whether the interrupt request is to be delivered to the virtual processor. The exit logic is to transfer control to a host if the delivery logic determines that the interrupt request is not to be delivered to the virtual processor.

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Номер записи: 23
10-01-2013 дата публикации

Data transfer control device and data transfer control method

Номер: US20130013821A1
Автор: Masaki Okada
Принадлежит: Fujitsu Semiconductor Ltd

A data transfer control device that selects one of a plurality of DMA channels and transfers data to or from memory includes a request holding section configured to hold a certain number of data transfer requests of the plurality of DMA channels and a request rearranging section configured to select and rearrange the data transfer requests that are held in a basic transfer order so that the data transfer requests of each of the plurality of DMA channels are successively outputted for a number of successive transfers set in advance.

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Номер записи: 24
10-01-2013 дата публикации

Hot-swapping active memory for virtual machines with directed i/o

Номер: US20130013877A1
Автор: Kun Tian
Принадлежит: Intel Corp

Embodiments of the invention describe a DMA Remapping unit (DRU) to receive, from a virtual machine monitor (VMM), a hot-page swap (HPS) request, the HPS request to include a virtual address, in use by at least one virtual machine (VM), mapped to a first memory page location, and a second memory page location. The DRU further blocks DMA requests to addresses of memory being remapped until the HPS request is fulfilled, copies the content of the first memory page location to the second memory page location, and ramps the virtual address from the first memory page location to the second memory page location.

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Номер записи: 25
24-01-2013 дата публикации

System and method for high-performance, low-power data center interconnect fabric with broadcast or multicast addressing

Номер: US20130022040A1
Автор: David James Borland, Mark Davis
Принадлежит: Calxeda Inc

A system and method are provided that support a routing using a tree-like or graph topology that supports multiple links per node, where each link is designated as an Up, Down, or Lateral link, or both, within the topology. The system may use a segmented MAC architecture which may have a method of re-purposing MAC IP addresses for inside MACs and outside MACs, and leveraging what would normally be the physical signaling for the MAC to feed into the switch.

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Номер записи: 26
31-01-2013 дата публикации

Using a dma engine to automatically validate dma data paths

Номер: US20130031281A1
Автор: Jane W. Yan, John R. Feehrer, Matthew G. Noel
Принадлежит: Oracle International Corp

The disclosed embodiments provide a system that uses a DMA engine to automatically validate DMA data paths for a computing device. During operation, the system configures the DMA engine to perform a programmable DMA operation that generates a sequence of memory accesses which validate the memory subsystem and DMA paths of the computing device. For instance, the operation may include a sequence of reads and/or writes that generate sufficient data traffic to exercise the computing device's I/O controller interface and DMA data paths to memory to a specified level. The system initiates this programmable DMA operation, and then checks outputs for the operation to confirm that the operation executed successfully.

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Номер записи: 27
07-03-2013 дата публикации

System and method of monitoring a central processing unit in real time

Номер: US20130061069A1
Автор: Ali Iranli, Christopher Kong Yee Chun, Haw-Jing Lo, Michael J. Drop, Moinul H. Khan, Steven S. Thomson, Tao Xue, Vinodh R. Cuppu
Принадлежит: Qualcomm Inc

Devices and methods for monitoring one or more central processing units in real time is disclosed. The method may include monitoring state data associated with the one or more CPUs in real-time, filtering the state data, and at least partially based on filtered state data, selectively altering one or more system settings. A device may include means for monitoring state data associated with the one or more CPUs in real-time, means for filtering the state data, and means for selectively altering one or more system settings at least partially based on filtered state data. A device may also include a sub-sampling circuit configured to receive a hardware core signal from the central processing unit and output a central processing unit state indication, and an infinite impulse response filter connected to the sub-sampling circuit and configured to receive the central processing unit state indication from the sub-sampling circuit.

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Номер записи: 28
14-03-2013 дата публикации

Methods and structure for improved processing of i/o requests in fast path circuits of a storage controller in a clustered storage system

Номер: US20130067125A1
Автор: Adam Weiner, Gerald E. Smith, James A. Rizzo, Vinu Velayudhan
Принадлежит: LSI Corp

Methods and structure for improved processing of fast path I/O requests in a clustered storage system. In a storage controller of a clustered storage system, the controller comprises a fast path I/O request processing circuit tightly coupled with host system drivers for fast processing of requests directed to storage devices of a logical volume. The controller also comprises a logical volume I/O processing stack (typically implemented as programmed instructions) for processing I/O requests from a host system directed to a logical volume. Based on detecting a change of ownership of a device or volume and/or a change to logical to physical mapping of a logical volume, fast path I/O requests may be converted to logical volume requests based on mapping context information within the fast path I/O request and shipped within the clustered storage system for processing.

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Номер записи: 29
14-03-2013 дата публикации

Electric power information management apparatus, electric power information management system, and electric power information management method

Номер: US20130067253A1
Автор: Yoshiaki Tsuda
Принадлежит: Mitsubishi Electric Corp

An electric power information management apparatus includes a power meter that measures electric power data on electric power to be supplied from a storage battery of a vehicle to an electric power facility; a security module that associates and encrypts identification information corresponding to the vehicle and the measured electric power data; a communication device that transmits to an electric power management database the identification information corresponding to the vehicle and the electric power data encrypted by the security module to store the electric power data associated with the identification information in the electric power management database; and an electric power control device that extracts necessary electric power from the electric power facility and supplies the electric power to the storage battery of the vehicle corresponding to the identification information, based on the electric power data stored in the electric power management database, being associated with the identification information.

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Номер записи: 30
14-03-2013 дата публикации

Methods and structure for managing visibility of devices in a clustered storage system

Номер: US20130067569A1
Автор: Adam Weiner, Basavaraj G. Hallyal, Gerald E. Smith, James A. Rizzo, Vinu Velayudhan
Принадлежит: LSI Corp

Methods and system for implementing a clustered storage solution are provided. One embodiment is a storage controller that communicatively couples a host system with a storage device. The storage controller comprises an interface and a control unit. The interface is operable to communicate with the storage device. The control unit is operable to identify ownership information for a storage device, and to determine if the storage controller is authorized to access the storage device based on the ownership information. The storage controller is operable to indicate the existence of the storage device to the host system if the storage controller is authorized, and operable to hide the existence of the storage device from the host system if the storage controller is not authorized.

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Номер записи: 31
28-03-2013 дата публикации

System and method for reducing cross coupling effects

Номер: US20130076424A1
Автор: Baker S. Mohammad, Martin Saint-Laurent, Paul D. Bassett
Принадлежит: Qualcomm Inc

A device includes a plurality of driver circuits coupled to a plurality of bus lines. A first driver circuit of the plurality of driver circuits is coupled to a first bus line of the plurality of bus lines. The first driver circuit includes one of a skewed inverter, a level shifter, a latch, and a sense amplifier configured to produce an output signal that transitions after a first delay in response to a first digital value transition of an input signal from high to low and transitions after a second delay in response to a second digital value transition of the input signal from low to high. The first delay is different from the second delay by an amount sufficient to reduce power related to transmission of signals over the first bus line and over a second bus line in close physical proximity to the first bus line.

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Номер записи: 32
28-03-2013 дата публикации

Source Core Interrupt Steering

Номер: US20130080674A1
Автор: Foong Annie, Veal Bryan E.
Принадлежит:

An embodiment of the invention includes (i) receiving a core identifier that corresponds with a processor source core; (ii) receiving an input/output request, produced from the source core, that is associated with the core identifier; (iii) and directing an interrupt, which corresponds to the request, to the source core based on the core identifier. Other embodiments are described herein. 1. At least one machine readable medium comprising instructions that when executed on a computing device cause the computing device to perform a method comprising:receiving a core identifier that corresponds with a source core that is included in a processor;receiving an input/output request, produced and originating from the source core, that is associated with the core identifier;storing the core identifier in a memory coupled to the processor;directing an interrupt, which corresponds to the request, to the source core based on the core identifier;wherein the processor is coupled to an additional core and the request includes the core identifier.2. The at least one medium of claim 1 , the method comprising directing the interrupt to the source core claim 1 , but not the additional core claim 1 , based on the core identifier.3. The at least one medium of claim 2 , the method comprising directing a message-signaled interrupt message to the source core based on the core identifier.4. The at least one medium of claim 1 , the method comprising determining a message-signaled interrupt address based on the core identifier.5. The at least one medium of claim 1 , the method comprising storing the core identifier in the memory before directing the interrupt to the source core.6. At least one machine readable medium comprising instructions that when executed on a computing device cause the computing device to perform a method comprising:receiving an input/output request, produced and originating from a source core, which includes a message-signaled interrupt (MSI) message that corresponds ...

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Номер записи: 33
28-03-2013 дата публикации

Multi-Lane Concurrent Bag for Facilitating Inter-Thread Communication

Номер: US20130081061A1
Автор: David Dice, Oleksandr Otenko
Принадлежит: Oracle International Corp

A method, system, and medium are disclosed for facilitating communication between multiple concurrent threads of execution using a multi-lane concurrent bag. The bag comprises a plurality of independently-accessible concurrent intermediaries (lanes) that are each configured to store data elements. The bag provides an insert function executable to insert a given data element into the bag by selecting one of the intermediaries and inserting the data element into the selected intermediary. The bag also provides a consume function executable to consume a data element from the bag by choosing one of the intermediaries and consuming (removing and returning) a data element stored in the chosen intermediary. The bag guarantees that execution of the consume function consumes a data element if the bag is non-empty and permits multiple threads to execute the insert or consume functions concurrently.

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Номер записи: 34
04-04-2013 дата публикации

INTERRUPTION FACILITY FOR ADJUNCT PROCESSOR QUEUES

Номер: US20130086289A1
Автор: Gainey, JR. Charles W., Meissner Klaus, Osisek Damian L., Werner Klaus
Принадлежит: INTERNATIONAL BUSINESS MACHINES CORPORATION

Interruption facility for adjunct processor queues. In response to a queue transitioning from a no replies pending state to a reply pending state, an interruption is initiated. This interruption signals to a processor that a reply to a request is waiting on the queue. In order for the queue to take advantage of the interruption capability, it is enabled for interruptions. 1. A method for making a computer program product for facilitating processing of queues of a processing environment , the method comprising:first assembling instructions for causing a computer to determine that a queue of the processing environment has transitioned from a no replies pending state to a reply pending state, wherein the queue is indirectly accessible to user programs, and wherein the no replies pending state is a state in which the queue is empty, and the reply pending state is a state in which the queue is not empty, and storing the first assembling instructions on a tangible computer storage medium;second assembling instructions for causing a computer to enable the queue for interruption, the enabling comprising employing a process adjunct processor queue (PQAP) instruction to enable the queue for interruption, wherein the PQAP instruction employs general registers 0, 1 and 2 for input, and general register 1 for output, and storing the second assembling instructions on a tangible computer storage medium; andthird assembling instructions for causing a computer to initiate, by a processor, an interrupt for the queue, wherein the initiating is based on enabling the queue and determining that the queue has transitioned from the no replies pending state to the reply pending state, wherein the interrupt is initiated based on the queue transitioning from an empty state to a non-empty state, and the interrupt is not initiated based on the queue not transitioning from the empty state to the non-empty state, and storing the third assembling instructions on a tangible computer storage medium. ...

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Номер записи: 35
11-04-2013 дата публикации

MODULAR INTEGRATED CIRCUIT WITH COMMON INTERFACE

Номер: US20130091316A1
Автор: Bhasin Vinay, Flake Lance Leslie, Fullerton Mark N., Hayek Claude G., III Lawrence J., Kharwa Bhupesh, Liu Sam, Madar, Morris Robert, Nath Joyjit, Zhao Chaoyang
Принадлежит: BROADCOM CORPORATION

A modular integrated circuit includes a hub module that is coupled to a plurality of spoke modules via a plurality of hub interfaces. The plurality of hub interfaces provide a plurality of signal interfaces between the hub module and each of the plurality of spoke modules, wherein each of the plurality of signal interfaces is isolated from each of the other signal interfaces of the plurality of signals interface, and wherein each of the plurality of signal interfaces operates in accordance with a common signaling format. 1. A modular integrated circuit comprising:a plurality of spoke modules; and a power management unit, coupled to the plurality of hub interfaces, that selectively supplies a plurality of power supply signals to the plurality of spoke modules via the plurality of hub interfaces; and', 'a clock control circuit, coupled to the plurality of hub interfaces, that selectively supplies a plurality of clock signals to the plurality of spoke modules via the plurality of hub interfaces;', 'wherein the plurality of hub interfaces provides a plurality of signal interfaces between the hub module and each of the plurality of spoke modules, wherein each of the plurality of signal interfaces is isolated from each of the other signal interfaces of the plurality of signals interface, and wherein each of the plurality of signal interfaces operates in accordance with a common signaling format., 'a hub module that is coupled to the plurality of spoke modules to facilitate inter-spoke communications via a corresponding plurality of hub interfaces, the hub module including2. The modular integrated circuit of wherein the common signaling format for each of the plurality of hub interfaces includes:a clock request signal received from a corresponding one of the plurality of spoke modules; andat least one of the plurality of clock signals.3. The modular integrated circuit of wherein the common signaling format for each of the plurality of hub interfaces includes:a power ...

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Номер записи: 36
18-04-2013 дата публикации

System and Method for High-Performance, Low-Power Data Center Interconnect Fabric

Номер: US20130097351A1
Автор: David James Borland, Mark Bradley Davis
Принадлежит: Calxeda Inc

A system and method are provided that support a routing using a tree-like or graph topology that supports multiple links per node, where each link is designated as an Up, Down, or Lateral link, or both, within the topology. The system may use a segmented MAC architecture which may have a method of re-purposing MAC IP addresses for inside MACs and outside MACs, and leveraging what would normally be the physical signaling for the MAC to feed into the switch.

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Номер записи: 37
02-05-2013 дата публикации

DATA TRANSFER CONTROL APPARATUS, DATA TRANSFER CONTROL METHOD, AND COMPUTER PRODUCT

Номер: US20130111078A1
Автор: KURIHARA Koji, SUZUKI Takahisa, YAMASHITA Koichiro, YAMAUCHI Hiromasa
Принадлежит: FUJITSU LIMITED

A data transfer control apparatus includes a transferring unit that transfers data from a transfer source memory to a transfer destination memory, according to an instruction from a first processor; and a first processor configured to detect a process execute by the first processor, determine whether transfer of the data is urgent, based on the type of the detected process, and control the transferring unit or the first processor to transfer the data, based on a determination result. 1. A data transfer control apparatus comprising:a transferring unit that transfers data from a transfer source memory to a transfer destination memory, according to an instruction from a first processor; and detect a process execute by the first processor,', 'determine whether transfer of the data is urgent, based on the type of the detected process, and', 'control the transferring unit or the first processor to transfer the data, based on a determination result., 'a first processor configured to2. The data transfer control apparatus according to claim 1 , whereinthe first processor further detects a state change of the first processor, andthe first processor determines whether the transfer of the data is urgent, based on the type of the process and a state change of the first process.3. The data transfer control apparatus according to claim 1 , whereinthe first processor further detects that a state of the process changes from an active state to an inactive state or from the inactive state to the active state, andthe first processor determines whether the transfer the data is urgent, based on the type of the process and a detection result concerning the state of the process.4. The data transfer control apparatus according to claim 1 , whereinthe first processor upon determining that the transfer is urgent, controls the transferring unit such that the data is transferred.5. The data transfer control apparatus according to claim 1 , whereinthe first processor determines whether storage ...

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Номер записи: 38
02-05-2013 дата публикации

DATA PROCESSING DEVICE, CHAIN AND METHOD, AND CORRESPONDING COMPUTER PROGRAM

Номер: US20130111079A1
Автор: Ben Abdallah Riadh, Fraboulet Antoine, Martin Jerome, Risset Tanguy
Принадлежит:

A data processing device includes a memory, a direct memory access controller including a receiving module configured to receive data coming from outside the device and for writing the data in a main buffer memory of the memory, and a processing unit programmed to read and process data written by the receiving module in a work area of the main buffer memory. The main buffer memory is divided between a used space, where the receiving module is configured not to write, and free space, where the receiving module is configured to write. The processing unit is further programmed to define the work area, and the direct memory access controller includes a buffer memory manager configured to free data written in the main buffer memory, by defining a location of this data as a free space, only when this data is outside the work area. 111-. (canceled)12. A data processing device comprising:a memory;a direct memory access controller comprising a receiving module configured to receive data coming from outside the device and for writing the data in a predetermined portion of the memory, as a main buffer memory;a processing unit programmed to read and process data written by the receiving module in the main buffer memory area as a work area,wherein:the main buffer memory is divided between used space and free space;the processing unit is further programmed to define the work area; andthe direct memory access controller comprises a buffer memory manager configured to free data written in the main buffer memory, by defining a location of this data as a free space, only when this data is outside the work area.13. A device according to claim 12 , wherein the processing unit is programmed to wait until the receiving module writes data received in the entire work area before reading and processing the data of the work area.14. A device according to claim 12 , wherein:the receiving module is configured to write each data item received in a location of the main buffer memory indicated by ...

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Номер записи: 39
02-05-2013 дата публикации

Digital Signal Processing Data Transfer

Номер: US20130111159A1
Автор: Adrian J. Anderson, Gareth J. Davies, Gary C. Wass
Принадлежит: Imagination Technologies Ltd

A technique for transferring data in a digital signal processing system is described. In one example, the digital signal processing system comprises a number of fixed function accelerators, each connected to a memory access controller and each configured to read data from a memory device, perform one or more operations on the data, and write data to the memory device. To avoid hardwiring the fixed function accelerators together, and to provide a configurable digital signal processing system, a multi-threaded processor controls the transfer of data between the fixed function accelerators and the memory. Each processor thread is allocated to a memory access channel, and the threads are configured to detect an occurrence of an event and, responsive to this, control the memory access controller to enable a selected fixed function accelerator to read data from or write data to the memory device via its memory access channel.

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Номер записи: 40
09-05-2013 дата публикации

METHOD AND A SYSTEM FOR POLLING AND PROCESSING DATA

Номер: US20130117482A1
Автор: Jain Sandeep, Tiwary Prakash Chandra
Принадлежит:

The embodiments herein provide a method and system for polling and processing data. The method comprises computing a maximum time from a source after a last update time, waiting for a preset time to ensure that all transactions with respect to a change in a data is completed, querying for a plurality of changes after an elapse of the preset waiting time since the last update time and up to the maximum time, generating a time window, collecting a list of changes occurred within the generated time window, sending the collected list of changes for processing; and updating the processed data at the destination. The time window comprises a time interval between the last update time and the maximum time. 1. A method for polling and processing data from a source to a destination comprises:computing a maximum time from a source after a last update time;waiting for a preset time to ensure that all transactions with respect to a change in a data is completed , and wherein the preset time is set such that all transactions that are in flight at a time of lust query are completed;querying for a plurality of changes after an elapse of the preset waiting time since the last update time and up to the maximum time;generating a time window and wherein the time window comprises a time interval between the last update time and the maximum time collecting a list of changes occurred within the generated time window;sending the collected list of changes for processing; andupdating the processed data at the destination.2. A system for polling and processing a data from a source to a destination comprises:a connector framework and wherein the connector framework comprises two connector modules, a polling module and an adopter module;a processing manager and wherein the processing manager processes a poll event using a processing engine;a mapping manager and wherein the mapping manager maps a plurality of fields of the source to a corresponding fields of a destination;a recovery manager and ...

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Номер записи: 41
16-05-2013 дата публикации

Host-Based Messaging Framework for PCIE Device Management

Номер: US20130124768A1
Автор: Mukund P. Khatri, Surender V. Brahmaroutu
Принадлежит: Dell Products LP

A method of routing data in an information handling system can include receiving a notification from a management controller at a basic input/output system (BIOS) that includes a system management interrupt (SMI) handler. The a notification can indicate that the management controller has a data packet bound for a peripheral component interconnect express input/output (PCIe I/O) device coupled to a secondary processor. The method can include generating a system management interrupt at the information handling system via the BIOS SMI handler in response to the notification. The method can also include retrieving the data packet from the management controller via the BIOS SMI handler and sending a payload associated with the data packet from the BIOS SMI handler to the PCIe I/O device.

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Номер записи: 42
16-05-2013 дата публикации

EMULATION OF AN INPUT/OUTPUT ADVANCED PROGRAMMABLE INTERRUPT CONTROLLER

Номер: US20130124769A1
Автор: Fleming Bruce, Mandhani Arvind
Принадлежит:

Embodiments of systems, apparatuses, and methods for emulating an input/output Advanced Programmable Interrupt Controller are disclosed. In one embodiment, an apparatus includes a first interrupt controller having a first programming model, and emulation logic to emulate a second interrupt controller having a second programming model that is different from the first programming model, The emulation logic is also to mask one of a plurality of interrupt requests to the first interrupt controller for each of the plurality of interrupt requests handled by the emulation logic. 1. An apparatus co p sing:a first intern controller having a first programming model; andemulation logic to emulate a second interrupt controller having a second programming model different from the first programming model, and to mask one of a plurality of interrupt requests to the first interrupt controller for each of the plurality of interrupt requests handled by the emulation logic.2. The apparatus of claim 1 , wherein the second interrupt controller is an input/output Advanced Programmable Interrupt Controller.3. The apparatus of claim 1 , wherein he first interrupt controller includes a plurality of mask indicators claim 1 , and the emulation logic is to mask one of the plurality of interrupt requests to the first interrupt controller using one of the plurality of mask indicators.4. The apparatus of claim 1 , further comprising a random access memory to store information corresponding to contents of the register set of the second interrupt controller.5. The apparatus of claim 4 , further comprising a decoder to decode transactions intended for the second interrupt controller.6. The apparatus of claim 5 , further comprising redirection logic to redirect transactions intended for the second interrupt controller to the random access memory.7. The apparatus of claim 1 , further comprising messaging logic to construct an interrupt message for each of the plurality of interrupts handled by the ...

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Номер записи: 43
23-05-2013 дата публикации

ROUTING SWITCH APPARATUS, NETWORK SWITCH SYSTEM, AND ROUTING SWITCHING METHOD

Номер: US20130132634A1
Автор: DIAO Junfeng, Liu Yunhai
Принадлежит: Huawei Technologies Co., Ltd.

The present disclosure relates to a routing switch apparatus, a network switch system, and a routing switch method. The routing switch apparatus includes one or more direct memory access modules and at least two protocol conversion interfaces. The direct memory access module is configured to generate a continuous access request of a cross network node, and control data transmission in the at least two protocol conversion interfaces; each protocol conversion interface is configured to convert a communication protocol of data transmitted inside and outside the routing switch apparatus and connect the routing switch module and an external network node. The routing switch apparatus may be introduced to replace a network switch, so that cross-node memory access and IO space access can be performed directly rather than through a proxy, thereby reducing delay of the cross-node memory access and IO space access and improving overall performance of a system. 1. A routing switch apparatus , comprising:one or more direct memory access modules; andat least two protocol conversion interfaces; wherein:the direct memory access module is configured to generate a continuous access request of a cross network node and control data transmission in the at least two protocol conversion interfaces, andeach protocol conversion interface is configured to convert a communication protocol of data transmitted inside and outside the routing switch apparatus and connect the routing switch module and an external network node.2. The routing switch apparatus according to claim 1 , wherein the direct memory access module comprises:a direct memory access controller; anda direct memory access channel; whereinthe direct memory access controller controls a connection between the direct memory access channel and the protocol conversion interface according to configuration information.3. The routing switch apparatus according to claim 2 , wherein the direct memory access module further comprises a storage ...

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Номер записи: 44
30-05-2013 дата публикации

Efficient Memory and Resource Management

Номер: US20130138840A1
Автор: Andrew Kegel, Anthony Asaro, Mark Hummel, Phillip Ng
Принадлежит: Advanced Micro Devices Inc, ATI TECHNOLOGIES ULC

The present system enables passing a pointer, associated with accessing data in a memory, to an input/output (I/O) device via an input/output memory management unit (IOMMU). The I/O device accesses the data in the memory via the IOMMU without copying the data into a local I/O device memory. The I/O device can perform an operation on the data in the memory based on the pointer, such that I/O device accesses the memory without expensive copies.

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Номер записи: 45
30-05-2013 дата публикации

Multi-pass system and method supporting multiple streams of video

Номер: US20130138842A1
Автор: Darren Neuman, David Baer, Patrick Law
Принадлежит: Broadcom Corp

Systems and methods are disclosed for performing multiple processing of data in a network. In one embodiment, the network comprises a first display pipeline that is formed in real time from a plurality of possible display pipelines and that performs at least a first processing step on received data. A buffer stores the processed data and a second display pipeline that is formed in real time from a plurality of possible display pipelines performs at least a second processing step on stored data.

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Номер записи: 46
30-05-2013 дата публикации

DELEGATING A POLL OPERATION TO ANOTHER DEVICE

Номер: US20130138843A1
Автор: Espig Michael J., Fang Zhen, Harriman David J., Iyer Ravishankar
Принадлежит:

In one embodiment, the present invention includes a method for handling a registration message received from a host processor, where the registration message delegates a poll operation with respect to a device from the host processor to another component. Information from the message may be stored in a poll table, and the component may send a read request to poll the device and report a result of the poll to the host processor based on a state of the device. Other embodiments are described and claimed. 1. An apparatus comprising:a core to generate a registration message to delegate a poll operation to an input/output (IO) interconnect;the IO interconnect coupled to the core, the IO interconnect to include a poll table having a plurality of entries each having a first address field to store a first address to be received in a registration message and a destination address field to store a destination address in a system memory to be received in the registration message; andat least one device coupled to the IO interconnect to perform an operation for an application to be executed on the core and to include at least one status register, the IO interconnect including a poll delegation logic to poll the at least one status register responsive to information in a poll table entry, and to issue a write transaction to the destination address if a polled value of the at least one status register differs from an initial value of the at least one status register.2. The apparatus of claim 1 , wherein each of the plurality of entries includes an initial value field to store an initial value associated with the first address received in the registration message.3. The apparatus of claim 1 , wherein the poll delegation logic is to issue a read request to the at least one device at a predetermined interval to perform the poll.4. The apparatus of claim 3 , wherein the poll delegation logic is to perform a comparison between data received from the at least one device responsive to ...

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Номер записи: 47
30-05-2013 дата публикации

MULTICORE PROCESSOR SYSTEM, COMPUTER PRODUCT, ASSIGNING METHOD, AND CONTROL METHOD

Номер: US20130138849A1
Автор: KURIHARA Koji, SUZUKI Takahisa, YAMASHITA Koichiro, YAMAUCHI Hiromasa
Принадлежит: FUJITSU LIMITED

A multicore processor system includes core configured to detect a process assignment instruction; acquire a remaining time obtained by subtracting a processing time of interrupt processing assigned to an arbitrary core of a multicore processor from a period that is from a calling time of the interrupt processing to an execution time limit of the interrupt processing, upon detecting the process assignment instruction; judge if the remaining time acquired at the acquiring is greater than or equal to a processing time of processing defined to limit an interrupt in the process; and assign the process to the arbitrary core, upon judging that the remaining time is greater than or equal to the processing time of the processing defined to limit an interrupt in the process. 1. A multicore processor system comprising core configured to:detect a process assignment instruction;acquire a remaining time obtained by subtracting a processing time of interrupt processing assigned to an arbitrary core of a multicore processor from a period that is from a calling time of the interrupt processing to an execution time limit of the interrupt processing, upon detecting the process assignment instruction;judge if the remaining time acquired at the acquiring is greater than or equal to a processing time of processing defined to limit an interrupt in the process; andassign the process to the arbitrary core, upon judging that the remaining time is greater than or equal to the processing time of the processing defined to limit an interrupt in the process.2. A multicore processor system comprising a core configured to:add an execution time of given interrupt processing and an execution time of interrupt processing assigned to an arbitrary core of a multicore processor;judge whether the arbitrary core can meet an execution time limit from a time of calling of the given interrupt processing and an execution time limit from a time of calling of the assigned interrupt processing, based on a sum ...

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Номер записи: 48
30-05-2013 дата публикации

INTERRUPT CONTROL METHOD AND MULTICORE PROCESSOR SYSTEM

Номер: US20130138850A1
Автор: KURIHARA Koji, SUZUKI Takahisa, YAMASHITA Koichrio, YAMAUCHI Hiromasa
Принадлежит: FUJITSU LIMITED

In an interrupt control method of a multicore processor system including cores, a cache coherency mechanism, and a device, a first core detecting an interrupt signal from the device writes into an area prescribing an interrupt flag in the cache memory of the first core, first data indicating detection of the interrupt signal, and notifies the other cores of an execution request for interrupt processing corresponding to the interrupt signal, consequent to the cache coherency mechanism establishing coherency among at least cache memories of the other cores when the first data is written; and a second core different from the first core, maintaining the first data written as the interrupt flag, and notified of the execution request executes the interrupt processing, and writes over the area prescribing the interrupt flag written in the cache memory of the second core, with second data indicating no-detection of the interrupt signal. 1. An interrupt control method of a multicore processor system comprising a plurality of cores , a cache coherency mechanism establishing coherency among cache memories of the cores other than an arbitrary core when data is written into a cache memory of the arbitrary core , and a device , wherein first-writing into an area prescribing an interrupt flag in the cache memory of the first core, first data indicating detection of the interrupt signal, and', 'notifying the cores, other than the first core, of an execution request for interrupt processing corresponding to the interrupt signal, consequent to the cache coherency mechanism establishing coherency among at least the cache memories of the cores other than the first core when the first data is written at the first-writing; and, 'a first core that is among the cores and detects an interrupt signal from the device executes'} the interrupt processing, and', 'second-writing over the area prescribing the interrupt flag written in the cache memory of the second core, with second data ...

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Номер записи: 49
06-06-2013 дата публикации

Direct Device Assignment

Номер: US20130145051A1
Автор: Andrew Kegel, Mark Hummel
Принадлежит: Advanced Micro Devices Inc

A system is enabled for configuring an IOMMU to provide direct access to system memory data by at least one I/O device/peripheral. Further, the IOMMU is configured to pass a pointer to at least one I/O device without having to translate the pointer. Further, commands are sent from a process within a guest operating system (OS) directly to a peripheral without intervention from a hypervisor. Further, the IOMMU is configured to grant peripherals access permissions to memory blocks to maintain isolation among peripherals.

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Номер записи: 50
06-06-2013 дата публикации

Microcontroller resource sharing

Номер: US20130145063A1
Автор: Alain Vergnes, Franck Lunadier, Guillaume Pean
Принадлежит: Atmel Rousset SAS

A system includes one or more master modules configured to execute instructions embedded in non-transitory machine-readable media and controllable by a processor. The system also includes one or more peripheral modules that are configured to execute instructions embedded in non-transitory machine-readable media and controllable by the processor. The system also includes a system bus with instructions embedded in a non-transitory machine-readable medium and configured to allow data transfer between the processor and the one or more peripheral modules. A data processing module of the one or more peripheral modules includes a master interface and a slave interface. Both master and slave interfaces are coupled to the system bus.

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Номер записи: 51
13-06-2013 дата публикации

NETWORK ADAPTOR OPTIMIZATION AND INTERRUPT REDUCTION

Номер: US20130151743A1
Автор: Isrel, JR. Edward, JR. Maurice, RATCLIFF Bruce H., Stevens Jerry W., Zebrowski
Принадлежит: INTERNATIONAL BUSINESS MACHINES CORPORATION

A method and system are disclosed for network adaptor optimization and interrupt reduction. The method may also build an outbound buffer list based on outgoing data and add the outgoing data to an outbound buffer queue. Furthermore, the method may set a buffer state from an empty state to a primed state to indicate that the outgoing data is prepared for transmitting and signal a network adaptor with a notification signal. 1. A method for network adaptor optimization and interrupt reduction , the method comprising:building an outbound buffer list based on outgoing data, the outgoing data comprising data to be transmitted to a network;adding the outgoing data to an outbound buffer queue;setting a buffer state from an empty state to a primed state to indicate that the outgoing data is prepared for transmitting; andsignaling a network adaptor with a notification signal, the network adaptor configured to process the outbound buffer queue and transmit the outgoing data to the network in response to the notification signal, the network adaptor configured to set the buffer state to a polling state indicating that the network adaptor is polling for additional outgoing data, the network adaptor configured to poll for additional outgoing data for a predetermined time interval.2. The method of claim 1 , further comprising releasing the outgoing data in the outbound buffer queue such that the outbound buffer queue may accept additional outgoing data.3. The method of claim 1 , further comprising detecting that the network adaptor is polling based on the polling state and refraining from signaling the network adaptor with an additional notification signal claim 1 , the network adaptor configured to directly process the outbound buffer queue and directly transmit the additional outgoing data to the network.4. The method of claim 1 , wherein the buffer state comprises a Queued Direct I/O (QDIO) Storage-List-State Block (SLSB).5. The method of claim 1 , wherein the outbound buffer ...

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Номер записи: 52
13-06-2013 дата публикации

Interrupt Moderation

Номер: US20130151744A1
Автор: Somesh Gupta, Venkatesh Nagapudi
Принадлежит: Brocade Communications Systems LLC

A technique for interrupt moderation allows coalescing interrupts from a device into groups to be processed as a batch by a host processor. Receive and send completions may be processed differently. When the host is interrupted for receive completions, it may check for send completions, reducing the need for interrupts related to send completions. Timers and a counter allow coalescing interrupts into a single interrupt that can be used to signal the host to process multiple completions. The technique is suitable for both dedicated interrupt line and message-signaled interrupts.

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Номер записи: 53
20-06-2013 дата публикации

Semiconductor data processing device, time-triggered communication system, and communication system

Номер: US20130159577A1
Автор: Makoto Fujii
Принадлежит: Renesas Electronics Corp

The variation of the timing of starting interrupt processing in response to a timer interrupt request is reduced regardless of the condition of processing of other interrupts. A semiconductor data processing device incorporated in each of plural electronic control devices coupled to a network for time-triggered communication system is provided with a central processing unit, a communication control circuit and an interrupt control circuit. The communication control circuit has a local time timer for use in time-triggered communication and issues, based on time counting by the local time timer, a timer interrupt request for time-triggered communication. When a timer interrupt request for time-triggered communication is received, the interrupt control circuit performs control to cause the central processing unit to delay, by a predetermined reservation time, starting the interrupt processing to be performed in response to the timer interrupt request.

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Номер записи: 54
20-06-2013 дата публикации

System and method for Automatic Hardware Interrupt Handling

Номер: US20130159578A1
Автор: Lau David, NORDEN Erik K., Robinson James H.
Принадлежит: MIPS Technologies, Inc.

A processing system is provided consisting of an interrupt pin, multiple registers, a stack pointer, and an automatic interrupt system. The multiple registers store a number of processor states values. When the system detects an interrupt on the interrupt pin the system prepares to enter an exception mode where the automatic interrupt system causes an interrupt vector to be fetched, the stack pointer to be updated, and the processor state values to be read in parallel from the registers and stored in memory locations based on the updated stack pointer, prior to the execution of an interrupt service routine. A method for automatic hardware interrupt handling is also presented. 1. A method of interrupt handling , comprising:determining a privilege level associated with a first interrupt;updating a first stack pointer register with a value copied from a first fixed register,storing a value associated with the first interrupt in a first memory address at a location identified by the first stack pointer register, anddisallowing access to the first fixed register from a process operating at a second privilege level, wherein the second privilege level is lower than the privilege level of the first interrupt.2. The method of claim 1 , further comprising:determining a privilege level of a second interrupt;updating a second stack pointer register with a value copied from a third stack pointer register associated with an interrupted process operating at a third privilege level, wherein the third privilege level is equal to the privilege level of the second interrupt;modifying the value in the second stack pointer register, andstoring a value associated with the second interrupt in a second memory address at a location identified by the second stack pointer register. This application is a divisional of U.S. application Ser. No. 12/847,772, filed Jul. 30, 2010, (now allowed), which is incorporated by reference herein in its entirety.1. Field of InventionEmbodiments of the ...

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Номер записи: 55
20-06-2013 дата публикации

BUS CONTROL DEVICE AND BUS CONTROL METHOD

Номер: US20130159589A1
Автор: Takayama Kazuyoshi
Принадлежит: FUJITSU LIMITED

A bus control device includes a storing unit that stores therein a threshold related to bus width of a bus that is a transfer path for data, a comparing unit that compares, when the bus width is reduced, the reduced bus width with the threshold stored in the storing unit, and a selecting unit that selects, on the basis of the result of the comparison performed by the comparing unit, an interrupt operation performed on a processor that performs a process related to a reduction of the bus width. 1. A bus control device comprising:a storing unit that stores therein a threshold related to bus width of a bus that is a transfer path for data;a comparing unit that compares, when the bus width is reduced, the reduced bus width with the threshold stored in the storing unit; anda selecting unit that selects, on the basis of the result of the comparison performed by the comparing unit, an interrupt operation performed on a processor that performs a process related to a reduction of the bus width.2. The bus control device according to claim 1 , wherein the selecting unit selects claim 1 , on the basis of the result of the comparison performed by the comparing unit claim 1 , whether to generate an interrupt in the processor.3. The bus control device according to claim 1 , wherein the selecting unit selects claim 1 , on the basis of the result of the comparison performed by the comparing unit claim 1 , a priority of an interrupt performed on the processor.4. The bus control device according to claim 1 , whereinthe storing unit stores therein multiple thresholds,the comparing unit compares the reduced bus width with each of the multiple thresholds stored in the storing unit, andthe selecting unit selects, on the basis of the result of the comparison performed by the comparing unit, the presence or absence of an interrupt performed on the processor and a priority of an interrupt.5. The bus control device according to claim 1 , wherein the storing unit stores therein claim 1 , in ...

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Номер записи: 56
27-06-2013 дата публикации

IMAGE PROCESSING METHOD, IMAGE PROCESSING APPARATUS, AND CONTROL PROGRAM

Номер: US20130166792A1
Автор: SHIMMOTO Takafumi
Принадлежит:

An image processing method includes: dividing received data into a header and a body; and writing the data in at least one buffer through a direct memory access (DMA) transfer. 1. An image processing method comprising:dividing received data into a header and a body; andwriting the data in at least one buffer through a direct memory access (DMA) transfer.2. The image processing method according to claim 1 , further comprising:analyzing the header; andselecting a buffer as a write destination of the DMA transfer according to contents of data contained in the body.3. The image processing method according to claim 1 , wherein the writing includes:if data contained in the body is content data, writing the data in a projection buffer through the DMA transfer; andif data contained in the body is a command, writing the data in a reception buffer through the DMA transfer.4. The image processing method according to claim 1 , further comprising:adding dummy data to each of the header and the body to adjust alignment thereof when subjecting the divided received data to the DMA transfer.5. The image processing method according to claim 1 , wherein the writing includes:writing the received data in a reception buffer; andif data contained in a body is content as a result of analysis, writing the data in a projection buffer through the DMA transfer.6. The image processing method according to claim 1 , wherein the writing includes:out of the received data, writing data having a size required for an analysis of the header, in a reception buffer through the DMA transfer; andwriting content data in a projection buffer, the content data being included in part of the body written in the reception buffer and a rest of the body.7. An image processing apparatus comprising:a network board that analyzes received data and outputs image data; anda projection unit that projects the image data output from the network board as an optical image, wherein a division unit that divides the received ...

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Номер записи: 57
27-06-2013 дата публикации

INFORMATION PROCESSING APPARATUS AND RECORDING APPARATUS USING THE SAME

Номер: US20130166804A1
Автор: Kitai Satoshi, Nishitani Eriko
Принадлежит: CANON KABUSHIKI KAISHA

A memory control unit is connected to a first bus and a second bus and that controls writing and reading of data to a memory; a control unit controls the information processing apparatus; a first circuit device is connected to the first bus and outputs a data write request to the memory control unit and a notification signal; a second circuit device is connected to the first bus and outputs a data read request to the memory control unit in accordance with the notification signal and an interrupt signal to the control unit in response to the data read request; and a third circuit device is connected to the second bus and outputs a data read request stored in the memory to the memory control unit in accordance with an instruction from the control unit which has received an interrupt signal. 1. An information processing apparatus including a memory control unit that is connected to a first bus and a second bus and that controls writing of data to a memory and reading of data from the memory , the information processing apparatus comprising:a control unit that controls the information processing apparatus;a first circuit device that is connected to the first bus and that outputs a data write request to the memory control unit and outputs a notification signal;a second circuit device that is connected to the first bus and that outputs a data read request to the memory control unit in accordance with the notification signal and outputs an interrupt signal to the control unit in accordance with a response to the data read request; anda third circuit device that is connected to the second bus and that outputs a data read request stored in the memory to the memory control unit in accordance with an instruction from the control unit to which the interrupt signal has been input.2. The information processing apparatus according to claim 1 , further comprising a fourth circuit device that is connected to the first bus and that outputs a data write request to the memory control ...

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Номер записи: 58
27-06-2013 дата публикации

INTERRUPT CAUSE MANAGEMENT DEVICE AND INTERRUPT PROCESSING SYSTEM

Номер: US20130166805A1
Автор: Osagawa Daisuke
Принадлежит: Mitsubishi Electric Corporation

A peripheral device sends an interrupt generation notification to a bus bridge. The bus bridge receives the interrupt generation notification, transfers the received interrupt generation notification to a CPU, reads an interrupt cause from the peripheral device that has sent the interrupt generation notification, and writes to a memory the interrupt cause that has been read. Upon receiving the interrupt generation notification, the CPU reads the interrupt cause from the memory which allows fast access, and begins interrupt processing corresponding to the interrupt cause. Interrupt processing time up to commencement of the interrupt processing can be reduced. 14-. (canceled)5. An interrupt cause management device comprising:an interrupt generation notification receiving unit that receives an interrupt generation notification sent from a device;an interrupt cause reading unit that, when the interrupt generation notification is received by the interrupt generation notification receiving unit, reads an interrupt cause from the device that has sent the interrupt generation notification;an interrupt cause writing unit that writes the interrupt cause read by the interrupt cause reading unit to a memory device to be accessed by a processor device that processes the interrupt generation notification; andan interrupt generation notification sending unit that sends to the processor device the interrupt generation notification received by the interrupt generation notification receiving unit,wherein under a condition that an amount of read time required for the processor device to read the interrupt cause written in the memory device is shorter than an amount of time required for the processor device to read the interrupt cause from the device that has sent the interrupt generation notification,the interrupt cause writing unit writes to the memory device the interrupt cause read by the interrupt cause reading unit before a timing when the processor device, upon receiving the ...

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Номер записи: 59
11-07-2013 дата публикации

Increasing Turbo Mode Residency Of A Processor

Номер: US20130179615A1
Автор: Bhattacharyya Binata, Guddeti Jayakrishna
Принадлежит:

In one embodiment, the present invention includes a method for accessing a task stored in an entry of a task queue that identifies the task and a first core of a processor on which the task has been scheduled, reassigning the task to a coldest idle core of the processor, and sending the task to the coldest idle core and maintaining the processor in a turbo mode. Other embodiments are described and claimed. 1. A processor comprising:a plurality of cores each to execute instructions, each of the plurality of cores including at least one front end unit, at least one execution unit and at least one cache memory;a mapping table including a plurality of entries each to store a mapping of an advanced programmable interrupt controller (APIC) identifier (ID) to a core of the plurality of cores; anda power control unit (PCU) coupled to the plurality of cores and the mapping table and to access a task queue including a plurality of entries each to store a task identifier for a task and a corresponding identifier for a core on which the task is scheduled, wherein the PCU is to reassign a first task obtained from the task queue from a first core to a second core.2. The processor of claim 1 , wherein the PCU is to reassign the first task based at least in part on a temperature of the first and second cores.3. The processor of claim 2 , wherein the PCU is to reassign the first task when the second core is cooler than the first core.4. The processor of claim 1 , wherein the PCU is to reassign the first task in a manner that is not visible to an operating system.5. The processor of claim 1 , further comprising a plurality of thermal sensors each associated with one of the plurality of cores claim 1 , wherein each of the plurality of thermal sensors is to communicate temperature information to the PCU.6. The processor of claim 1 , wherein the second core includes an APIC register to store the APIC ID corresponding to the second core claim 1 , wherein the second core is to access the ...

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Номер записи: 60
11-07-2013 дата публикации

Super i/o module and control method thereof

Номер: US20130179671A1
Автор: Hao-Yang Chang, Hsi-Jung Tsai, Yueh-Yao Nain
Принадлежит: Nuvoton Technology Corp

A super input/output (I/O) module for controlling a universal serial bus (USB) port of a computer system is provided. The super I/O module includes a USB host, a switch and a processor. The switch selectively couples the USB port of the computer system to the USB host or a controller of the computer system according to a switching signal. When a trigger event occurs, the processor provides the switching signal to control the switch, so as to couple the USB port of the computer system to the USB host and to transmit a basic input/output system (BIOS) code to a flash memory of the computer system via the switch and the USB port.

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Номер записи: 61
18-07-2013 дата публикации

Fencing Direct Memory Access Data Transfers In A Parallel Active Messaging Interface Of A Parallel Computer

Номер: US20130185465A1
Автор: BLOCKSOME Michael A., MAMIDALA AMITH R.
Принадлежит: INTERNATIONAL BUSINESS MACHINES CORPORATION

Fencing direct memory access (‘DMA’) data transfers in a parallel active messaging interface (‘PAMI’) of a parallel computer, the PAMI including data communications endpoints, each endpoint including specifications of a client, a context, and a task, the endpoints coupled for data communications through the PAMI and through DMA controllers operatively coupled to segments of shared random access memory through which the DMA controllers deliver data communications deterministically, including initiating execution through the PAMI of an ordered sequence of active DMA instructions for DMA data transfers between two endpoints, effecting deterministic DMA data transfers through a DMA controller and a segment of shared memory; and executing through the PAMI, with no FENCE accounting for DMA data transfers, an active FENCE instruction, the FENCE instruction completing execution only after completion of all DMA instructions initiated prior to execution of the FENCE instruction for DMA data transfers between the two endpoints. 1. A method of fencing direct memory access (‘DMA’) data transfers in a parallel active messaging interface (‘PAMI’) of a parallel computer , the parallel computer comprising a plurality of compute nodes that execute a parallel application , the PAMI comprising data communications endpoints , the compute nodes and the endpoints coupled for data communications through the PAMI and through data communications resources including DMA controllers operatively coupled to segments of shared random access memory through which the DMA controllers deliver data communications deterministically , in the same order in which the communications are transmitted , the method comprising:initiating execution through the PAMI of an ordered sequence of active DMA instructions for DMA data transfers between two endpoints, an origin endpoint and a target endpoint, each DMA instruction effecting a deterministic DMA data transfer through a DMA controller and a segment of shared ...

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Номер записи: 62
18-07-2013 дата публикации

INTERRUPT SIGNAL ACCEPTING APPARATUS AND COMPUTER APPARATUS

Номер: US20130185469A1
Автор: Motai Hirotaka, Yamaguchi Tomohisa
Принадлежит: Mitsubishi Electric Corporation

An interrupt signal accepting apparatus manages two OSs, relates devices sharing the same interrupt number respectively with an OS caused to perform an interrupt processing and an interrupt priority unique to a device, and manages an interrupt number priority conversion table showing the relation between the interrupt number and the interrupt priority. Each device continuously outputs an interrupt request having the same interrupt number until the interrupt processing is completed. An interrupt controller converts the interrupt number into the interrupt priority in accordance with the interrupt number priority conversion table when there is an interrupt signal from the devices. An interrupt signal control section causes a running OS to perform the interrupt processing to change the interrupt priority in the interrupt number priority conversion table when the converted interrupt priority matches an interrupt priority related to the running OS, and stops the running OS and starts the other OS when the interrupt priorities do not match. 1. An interrupt signal accepting apparatus , managing operations of at least two operating systems (OSs) and accepting interrupt signals from a plurality of devices , wherein an interrupt number notified by an interrupt signal and an OS caused to process the interrupt signal as a specified OS are specified to each of the plurality of devices , the interrupt signal accepting apparatus comprising:an OS unique value information storing section that stores OS unique value information to relate each of at least two number sharing devices which share the same interrupt number, to the specified OS of each number sharing device, a unique value which is unique to each number sharing device, and a shared interrupt number which is shared by the at least two number sharing devices;a conversion value information storing section that stores conversion value information to specify a unique value selected from among at least two unique values related ...

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Номер записи: 63
01-08-2013 дата публикации

INTERRUPT HANDLING SYSTEMS AND METHODS FOR PCIE BRIDGES WITH MULTIPLE BUSES

Номер: US20130198432A1
Автор: ALTHOFF Markus, Dolling Steffen, NING Xiongzhi
Принадлежит: MARVELL WORLD TRADE LTD.

A bridge includes buses, a memory, a component module, an interface and an interrupt module. The component module transfers data between a host control module and a network device via the memory and the buses. The interface is connected between the memory and the network device and transmits status information to the memory via one of the buses. The status information indicates completion of a last data transfer between the network device and the host control module. An interrupt module, subsequent to the status information being transmitted to the memory, detects a first interrupt generated by the network device, and transmits an interrupt message to the component module via the memory and the one of the buses. The component module then generates a second interrupt detectable by the host control module. The second interrupt indicates completion of data transfer between the network device and the host control module. 1. A bridge comprising:a plurality of buses;a memory;a component module configured to transfer data between a host control module and a network device via the memory and the plurality of buses;an interface connected between the memory and the network device and configured to transmit status information to the memory via one of the plurality of buses, wherein the status information indicates completion of a last data transfer between the network device and the host control module; andan interrupt module configured to, subsequent to the status information being transmitted to the memory, detect a first interrupt generated by the network device, and transmit an interrupt message to the component module via the memory and the one of the plurality of buses,wherein the component module is configured to, based on the interrupt message, generate a second interrupt detectable by the interrupt module, and wherein the second interrupt indicates completion of data transfer between the network device and the host control module.2. The bridge of claim 1 , wherein:the ...

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Номер записи: 64
01-08-2013 дата публикации

METHODS AND SYSTEMS FOR DEVICES WITH SELF-SELECTING BUS DECODER

Номер: US20130198433A1
Автор: King Stephen P., Noyes Harold B
Принадлежит: MICRON TECHNOLOGY, INC.

Disclosed are methods and devices, among which is a device including a self-selecting bus decoder. In some embodiments, the device may be coupled to a microcontroller, and the self-selecting bus decoder may determine a response of the peripheral device to requests from the microcontroller. In another embodiment, the device may include a bus translator and a self-selecting bus decoder. The bus translator may be configured to translate between signals from a selected one of a plurality of different types of buses. A microcontroller may be coupled to a selected one of the plurality of different types of buses of the bus translator. 1. A system , comprising:a microcontroller; anda device coupled to the microcontroller via a bus, wherein the device comprises a decoder configured to select the device in response to a request from the microcontroller.2. The system of claim 1 , wherein the device comprises a pattern recognition processor.3. The system of claim 1 , wherein the decoder is configured to receive a memory mapping configuration.4. The system of claim 3 , wherein the memory mapping configuration comprises an indication of a plurality of memory addresses provided by the device.5. The system of claim 3 , wherein the memory mapping configuration comprises an indication of a plurality of memory addresses provided by the microcontroller.6. The system of claim 3 , wherein the decoder is configured to determine if a memory address associated with the request is provided by the device based on the memory mapping configuration.7. The system of claim 3 , wherein the decoder is configured to determine a type of the request.8. The system of claim 3 , wherein the decoder is configured to determine a response to the request.9. The system of claim 1 , wherein the device comprises double data rate two (DDR2) RAM.10. The system of claim 1 , wherein the request comprises a memory read claim 1 , a memory write claim 1 , a memory refresh claim 1 , a DMA request claim 1 , or any ...

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Номер записи: 65
08-08-2013 дата публикации

MULTI-THREAD PROCESSOR AND ITS INTERRUPT PROCESSING METHOD

Номер: US20130205058A1
Автор: ADACHI Koji, Miyamoto Kazunori
Принадлежит: RENESAS ELECTRONICS CORPORATION

A multi-thread processor includes a plurality of hardware threads each of which generates an independent instruction flow, a thread scheduler that manages in what order a plurality of hardware threads are processed with a pre-established schedule, and an interrupt controller that receives an input interrupt request signal and assigns the interrupt request to an associated hardware thread, wherein the interrupt controller comprises a register in which information is stored for each channel of an interrupt request signal, and the information includes information regarding to which one or more than one of the plurality of hardware threads the interrupt request signal is associated. 1. A multi-thread processor comprising:a plurality of hardware threads each of which generates an independent instruction flow;a thread scheduler that manages in what order the plurality of hardware threads are processed with a pre-established schedule; andan interrupt controller that receives an interrupt request and assigns the interrupt request to one certain hardware thread to be managed by the thread scheduler.2. The multi-thread processor according to claim 1 , wherein the interrupt controller comprises a register in which information of an interrupt request signal including the interrupt request is stored claim 1 , and the information of the interrupt request signal comprises information regarding to which one hardware thread the interrupt request is associated.3. The multi-thread processor according to claim 1 , wherein the interrupt controller comprises a register in which information is stored for each channel of an interrupt request signal including the interrupt request claim 1 , and the information comprises information regarding to which one or more of the plurality of hardware threads the interrupt request signal is associated claim 1 , andwherein in the register for each channel of an interrupt request signal, information about a relation between any one of the plurality of ...

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Номер записи: 66
15-08-2013 дата публикации

Technique to share information among different cache coherency domains

Номер: US20130207987A1
Автор: Altug Koker, Ariel Berkovits, Opher Kahn, Robert L. Farrell, Thomas A. Piazza, Zeev Offen
Принадлежит: Individual

A technique to enable information sharing among agents within different cache coherency domains. In one embodiment, a graphics device may use one or more caches used by one or more processing cores to store or read information, which may be accessed by one or more processing cores in a manner that does not affect programming and coherency rules pertaining to the graphics device.

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Номер записи: 67
22-08-2013 дата публикации

PROGRAMMABLE EVENT DRIVEN YIELD MECHANISM WHICH MAY ACTIVATE OTHER THREADS

Номер: US20130219096A1
Автор: DESAI PIYUSH N., GIRKAR MILIND, HAMMARLUND PER, SHEN JOHN P., TIAN XINMIN, WANG Hong, WANG PERRY H., ZOU XIANG
Принадлежит:

Method, apparatus, and program means for a programmable event driven yield mechanism that may activate other threads. In one embodiment, an apparatus includes execution resources to execute a plurality of instructions and a monitor to detect a condition indicating a low level of progress. The monitor can disrupt processing of a program by transferring to a handler in response to detecting the condition indicating a low level of progress. In another embodiment, thread switch logic may be coupled to a plurality of event monitors which monitor events within the multithreading execution logic. The thread switch logic switches threads based at least partially on a programmable condition of one or more of the performance monitors. 1execution resources to execute a plurality of instructions;a monitor to detect a low progress indicating condition of said execution resources, said monitor to selectively disrupt processing of at least one program by transferring to a handler in response to detecting said low progress indicating condition.. An apparatus comprising: This application is a continuation of application Ser. No. 10/982,261, filed Nov. 5, 2004, which is a divisional of application Ser. No. 10/370,251, filed Feb. 19, 2003, which issued as U.S. Pat. No. 7,487,502 on Feb. 3, 2009, which are hereby incorporated by reference.1. FieldThe present disclosure pertains to the field of processing apparatuses and systems that process sequences of instructions or the like, as well as certain instruction sequences to program such apparatuses and/or systems. Some embodiments relate to monitoring and/or responding to conditions or events within execution resources of such processing apparatuses.2. Description of Related ArtVarious mechanism are presently used to change the flow of control (i.e., the processing path or instruction sequence being followed) in a processing system. For example, a jump instruction in a program sequence explicitly and precisely causes a jump to a new ...

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Номер записи: 68
29-08-2013 дата публикации

Storage device

Номер: US20130227347A1
Автор: Hyunsik Kim, Youngjin Cho
Принадлежит: SAMSUNG ELECTRONICS CO LTD

A storage device is provided which includes a nonvolatile memory device and a controller configured to write meta information, indicating that a transfer of unit data is completed, in a buffer memory when the unit data is transferred to the buffer memory from the nonvolatile memory device.

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Номер записи: 69
05-09-2013 дата публикации

POSTING INTERRUPTS TO VIRTUAL PROCESSORS

Номер: US20130232288A1
Автор: Falik Ohad, Gerzon Gideon, Madukkarumukumana Rajesh Sankaran, Muthrasanallur Sridhar, Neiger Gilbert
Принадлежит:

Embodiments of systems, apparatuses, and methods for posting interrupts to virtual processors are disclosed. In one embodiment, an apparatus includes look-up logic and posting logic. The look-up logic is to look-up an entry associated with an interrupt request to a virtual processor in a data structure. The posting logic is to post the interrupt request in a data structure specified by information in the first data structure. 1. An apparatus comprising: look-up logic to look up an entry associated with an interrupt request to a virtual processor in a first data structure; and posting logic to post the interrupt request in a second data structure specified by first information in the first data structure.2. The apparatus of claim 1 , wherein the first information includes the address of the second data structure.3. The apparatus of claim 1 , wherein the posting logic is also to generate a notify event to a physical processor claim 1 , the notify event to indicate that an interrupt request is posted for the virtual processor.4. The apparatus of claim 1 , wherein the second data structure is to include a plurality of posted-interrupt request indicators claim 1 , each of the plurality of posted-interrupt request indicators corresponding to one of a plurality of virtual interrupt vectors associated with the virtual processor.5. The apparatus of claim 3 , wherein the second data structure is to include an identifier of the physical processor.6. The apparatus of claim 3 , wherein the notify event is an interrupt request to the physical processor.7. The apparatus of claim 6 , wherein the second data structure is to include a physical interrupt vector to be included in an interrupt message to the physical processor.8. The apparatus of claim 3 , wherein the posting logic is to use second information from the second data structure to determine whether to generate the notify event.9. The apparatus of claim 8 , wherein the second information includes an indication of whether a ...

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Номер записи: 70
19-09-2013 дата публикации

Input capture peripheral with gating logic

Номер: US20130241626A1
Автор: James E. Bartling, Stephen Bowling
Принадлежит: Microchip Technology Inc

A microcontroller has an input capture peripheral, wherein the input capture peripheral is configured to store timer values of an associated timer in a memory and wherein the input capture peripheral has a gating input which controls whether an input capture function is activated.

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Номер записи: 71
26-09-2013 дата публикации

Direct memory access system and method using the same

Номер: US20130254433A1
Автор: Kuo-Cheng Lu
Принадлежит: Ralink Technology Corp Taiwan

The invention discloses a DMA system capable of being adapted to various interfaces. The DMA system includes the following advantages: 1) the software porting effort can be reduced when different interfaces are integrated into a SoC; 2) a flexible DMA that could provide protocol transparency and could be ported into different interfaces easily; 3) a scalable DMA that can support unlimited TX/RX scattering/gathering data segments; 4) a reusable DMA that provides user defined TX information (or RX information) and TX message (or RX message) field; and 5) a high performance DMA that support unaligned segment data pointers and unlimited scattering/gathering data segments, so as to reduce extra memory copies by CPU.

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Номер записи: 72
03-10-2013 дата публикации

Data compression for direct memory access transfers

Номер: US20130262538A1
Автор: Albert W. Wegener
Принадлежит: Samplify Systems Inc

Memory system operations are extended for a data processor by DMA, cache, or memory controller to include a DMA descriptor, including a set of operations and parameters for the operations, which provides for data compression and decompression during or in conjunction with processes for moving data between memory elements of the memory system. The set of operations can be configured to use the parameters and perform the operations of the DMA, cache, or memory controller. The DMA, cache, or memory controller can support moves between memory having a first access latency, such as memory integrated on the same chip as a processor core, and memory having a second access latency that is longer than the first access latency, such as memory on a different integrated circuit than the processor core.

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Номер записи: 73
03-10-2013 дата публикации

SEMICONDUCTOR INTEGRATED CIRCUIT AND DMA CONTROL METHOD OF THE SAME

Номер: US20130262732A1
Автор: TANABATA Masatoshi
Принадлежит: FUJITSU SEMICONDUCTOR LIMITED

A semiconductor integrated circuit includes a bus, a memory connected to the bus, an arithmetic processing unit connected to the bus, a first DMA controller connected to the bus, and at least one functional block connected to the bus. The functional block includes a functional macro which is configured to perform a process that realizes a given function, a second DMA controller which is configured to control data transfer between the memory and the functional macro, and an access condition setting unit which is configured to set an access condition regarding the DMA transfer between the memory and the functional macro. 1. A semiconductor integrated circuit comprising:a bus;a memory connected to the bus;an arithmetic processing unit connected to the bus;a first DMA controller connected to the bus; andat least one functional block connected to the bus, the functional block including a functional macro which is configured to perform a process that realizes a given function, a second DMA controller which is configured to control data transfer between the memory and the functional macro, and an access condition setting unit which is configured to set an access condition regarding the DMA transfer between the memory and the functional macro.2. The semiconductor integrated circuit as claimed in claim 1 , whereinthe access condition setting unit includes a register and a control code storing unit, which are configured to set the access condition including an address of the memory and transfer size in a unit of instruction.3. The semiconductor integrated circuit as claimed in claim 2 , whereinthe control code storing unit is an instruction memory provided in the second DMA controller, anda control code which defines the access condition set in the unit of instruction is written in the instruction memory at the time of initial setting.4. The semiconductor integrated circuit as claimed in claim 3 , whereinthe control code is written in the instruction memory by the arithmetic ...

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Номер записи: 74
10-10-2013 дата публикации

MEMORY CONTROLLERS, MEMORY SYSTEMS, SOLID STATE DRIVES AND METHODS FOR PROCESSING A NUMBER OF COMMANDS

Номер: US20130268701A1
Автор: Asnaashari Mehdi, Liao Yu-Song, Nemazie Siamack, Yang Jui-Yao
Принадлежит: MICRON TECHNOLOGY, INC.

The present disclosure includes methods and devices for a memory controller. In one or more embodiments, a memory controller includes a plurality of back end channels, and a command queue communicatively coupled to the plurality of back end channels. The command queue is configured to hold host commands received from a host. Circuitry is configured to generate a number of back end commands at least in response to a number of the host commands in the command queue, and distribute the number of back end commands to a number of the plurality of back end channels. 1. A memory system , comprising:a number of memory devices; anda controller having a front end direct memory access module (DMA) and a number of back end channels communicatively coupled between a respective one of the number of memory devices and the front end DMA; the front end DMA being configured to process a payload associated with a single host command communicated by the host, wherein respective portions of the payload are associated with corresponding multiple back end commands that are being substantially simultaneously executed across the number of back end channels.2. The memory system of claim 1 , wherein the single host command is a write command claim 1 , and the front end DMA is configured to distribute the payload associated with the single host command amongst more than one of the number of back end channels corresponding to the multiple back end commands.3. The memory system of claim 1 , wherein the single host command is a read command claim 1 , and the front end DMA is configured to assemble a payload associated with the single host command from amongst more than one of the number of back end channels corresponding to the multiple back end commands.4. The memory system of claim 1 , wherein the front end DMA is configured to determine a logical block address and sector count for each respective portion of the payload associated with each of the multiple back end commands claim 1 , wherein ...

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Номер записи: 75
17-10-2013 дата публикации

DATA PROCESSING METHOD AND DATA PROCESSING UNIT USING THE SAME

Номер: US20130275634A1
Автор: KIM Ju-Young
Принадлежит:

A data processing unit includes a main controller configured to receive data requirement information from a host and to generate processing information based on the data requirement information; a pre-processing unit configured to pre-process n types of data output from the main controller according to the processing information and to generate n types of pre-processed data where n is an integer equal to or greater than 2; and a pre-processed data storing unit configured to store the n types of pre-processed data and to output the n types of pre-processed data in an output order determined based on the processing information, wherein the processing information includes information about at least one of type, format, order, size and transmission mode of the n types of pre-processed data. 1. A data processing unit comprising:a main controller configured to receive data requirement information from a host and to generate processing information based on the data requirement information;a pre-processing unit configured to pre-process n types of data output from the main controller according to the processing information and to generate n types of pre-processed data where n is an integer equal to or greater than 2; anda pre-processed data storing unit configured to store the n types of pre-processed data and to output the n types of pre-processed data in an output order determined based on the processing information,wherein the processing information includes information about at least one of type, format, order, size and transmission mode of the n types of pre-processed data.2. The data processing unit of claim 1 , whereinthe main controller is configured to receive data from a data generator and generate the n types of data, andthe n types of data include pointer data corresponding to information about an absolute or relative memory address of each of remaining ones of the n types of data.3. The data processing unit of claim 1 , further comprising:a processing ...

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Номер записи: 76
17-10-2013 дата публикации

Interrupt Virtualization

Номер: US20130275638A1
Автор: Hummel Mark D., Kaplan David A., Schmidt Rodney W., SEREBRIN Benjamin C.
Принадлежит:

In an embodiment, a device interrupt manager may be configured to receive an interrupt from a device that is assigned to a guest. The device interrupt manager may be configured to transmit an operation targeted to a memory location in a system memory to record the interrupt for a virtual processor within the guest, wherein the interrupt is to be delivered to the targeted virtual processor. In an embodiment, a virtual machine manager may be configured to detect that an interrupt has been recorded by the device interrupt manager for a virtual processor that is not currently executing. The virtual machine manager may be configured to schedule the virtual processor for execution on a hardware processor, or may prioritize the virtual processor for scheduling, in response to the interrupt. 1. A computer readable storage medium storing a plurality of instructions which , when executed on a computer:read a first memory location in a memory system, wherein the first memory location stores a log of events detected in the computer, wherein the log of events is updated by a hardware device interrupt manager in the computer responsive to the hardware device interrupt manager recording an interrupt in a second memory location in the memory system, wherein the second memory location is assigned to store interrupt data corresponding to a virtual processor in a virtual machine executing on the computer, wherein the hardware device interrupt manager is configured to receive the interrupt and to determine that the interrupt is targeted at the virtual processor, and wherein the interrupt is sourced by a device that is assigned to the virtual machine; andschedule the virtual processor for execution on a hardware processor in the computer responsive to detecting that the interrupt has been recorded for the virtual processor as indicated in the log of events, wherein the virtual processor is scheduled in order to service the interrupt.2. The computer readable storage medium as recited in ...

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Номер записи: 77
17-10-2013 дата публикации

METHOD TO EMULATE MESSAGE SIGNALED INTERRUPTS WITH MULTIPLE INTERRUPT VECTORS

Номер: US20130275639A1
Автор: CHEW YEN HSIANG
Принадлежит: Intel Corporation

Methods to emulate a message signaled interrupt (MSI) with multiple interrupt vectors are described herein. An embodiment of the invention includes a memory decoder to monitor a predetermined memory location allocated to a device and to generate an emulated message signaled interrupt (MSI) signal in response to a posted write transaction to the predetermined memory location initiated from the device, and an interrupt controller, in response to the emulated MSI signal from the memory decoder, to invoke processing of a plurality of interrupts based on a plurality of interrupt vectors retrieved from the predetermined memory location, without receiving an actual MSI interrupt request from the device. 1. A processor , comprising:a memory decoder to monitor a predetermined memory location allocated to a device and to generate an emulated message signaled interrupt (MSI) signal in response to a posted write transaction to the predetermined memory location initiated from the device; andan interrupt controller, in response to the emulated MSI signal from the memory decoder, to invoke processing of a plurality of interrupts based on a plurality of interrupt vectors retrieved from the predetermined memory location, without receiving an actual MSI interrupt request from the device.2. The processor of claim 1 , further comprising one or more execution units to execute one or more interrupt service routines (ISRs) associated with the device to service the MSI interrupts using interrupt data retrieved from the predetermined memory location claim 1 , without having to access the device via an input output (IO) transaction.3. The processor of claim 1 , wherein the emulated MSI signal is generated based on the posted write transaction from the predetermined memory location other than a system defined address for the MSI.4. The processor of claim 1 , wherein the memory location is allocated from one of a cache memory associated with the execution unit and a system memory during ...

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Номер записи: 78
17-10-2013 дата публикации

Electronic devices

Номер: US20130275659A1
Автор: Asbjorn Djupdal, Borgar Ljosland, Thomas Langas, Torstein Hernes Dybdahl
Принадлежит: FXI Tech AS

A storage device ( 3 ), such as an SD card, that is coupled to a host device ( 2 ), such as a mobile phone, includes a computing environment ( 8 ). The computing environment ( 8 ) includes an application processing part ( 6 ), and a separate interface processing part ( 7 ). The application processing part ( 6 ) of the computing environment 8 is operable to execute one or more applications on the storage device ( 3 ). The interface processing part ( 7 ) of the computing environment 8 includes an interface processor that interfaces between a communications protocol used between the host device ( 2 ) and the storage device ( 3 ), and a communications protocol used by the application processor in the application processing part ( 6 ) of the storage device ( 3 ). The interface processor communicates with the application processor via interrupts and a shared memory ( 9 ).

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Номер записи: 79
24-10-2013 дата публикации

Methods and Systems for Protecting Data in USB Systems

Номер: US20130282934A1
Автор: Dunn John C., England Paul, Peinado Marcus, Ray Kenneth D., Slick Glen, Willman Bryan
Принадлежит:

The various embodiments described below are directed to providing authenticated and confidential messaging from software executing on a host (e.g. a secure software application or security kernel) to and from I/O devices operating on a USB bus. The embodiments can protect against attacks that are levied by software executing on a host computer. In some embodiments, a secure functional component or module is provided and can use encryption techniques to provide protection against observation and manipulation of USB data. In other embodiments, USB data can be protected through techniques that do not utilized (or are not required to utilize) encryption techniques. In accordance with these embodiments, USB devices can be designated as “secure” and, hence, data sent over the USB to and from such designated devices can be provided into protected memory. Memory indirection techniques can be utilized to ensure that data to and from secure devices is protected. 1. A method comprising:receiving a request from an application for a USB transaction;querying the application for a memory location that is to be the subject of the transaction;receiving a memory location indication from the application, the memory location indication comprising, in an event that the application is a secure application, an indication associated with protected memory;processing the memory location indication into a transaction description (TD); andprocessing the TD with a host controller effective to either copy in or copy out data relative to the protected memory location associated with the memory location indication.2. The method of claim 1 , wherein protected memory is only accessible by a USB host controller.3. The method of claim 1 , wherein the act of processing the TD comprises copying in or copying out the data only if the protected memory location is associated with a secure USB device that is the subject of the USB transaction.4. The method of claim 1 , wherein the host controller copies ...

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Номер записи: 80
24-10-2013 дата публикации

System and method for system wide self-managing storage operations

Номер: US20130282948A1
Автор: "OBrien John", Brazao Duarte Miguel
Принадлежит:

The present invention presents a system and method to provide a storage system wide approach to better manage IO requests and better manage the prefetch transfers of data to and from the drives. 1a) connecting at least one host or client to a to an IO or network connection on one Storage Nodes;b) connecting at least one host or client to a to an IO or network connection on one or more additional Storage Nodes;c) performing multicast IO transfers over an interconnected bus connected to the memory of each Storage Node in the storage system to write to a volume on that node.d) responding to host IO requests and managing a Logical Storage Capacity for each Storage Node to aggregate and track the storage capacities of data drives are available within the Storage Node including which Nodes may access the drives.. A method for providing access from one or more host computer systems to a multi-node data storage system where access to a storage space could be made via any connected host with access permission connected to a Storage Node, said Storage Nodes connected by an Interconnected Bus, said storage space of the Storage Nodes being made up of one or more physical storage elements, or portions of one or more storage elements, comprising the steps of: This application claims priority of U.S. provisional application Ser. No. 61/631,272, filed Dec. 31, 2010, entitled, “System and Method for System Wide Self-Managing Storage Operations”The present invention relates to a computer system, storage system, and more particularly, to disk drive operations.shows a prior art storage system for disk drive operation with a plurality of storage elements . As depicted in , an individual storage element is comprised of a controller interface , processing capability , memory and a driver program .The storage system of the prior art in , shows a plurality of storage elements , connected to a controller or adapter board , and connected via the bus from the controller board to one or more ...

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Номер записи: 81
24-10-2013 дата публикации

Data integrity in memory controllers and methods

Номер: US20130283124A1
Автор: Jui-Yao Yang, Mehdi Asnaashari, Ronald Yamada, Siamack Nemazie
Принадлежит: Micron Technology Inc

The present disclosure includes methods, devices, and systems for data integrity in memory controllers. One memory controller embodiment includes a host interface and first error detection circuitry coupled to the host interface. The memory controller can include a memory interface and second error detection circuitry coupled to the memory interface. The first error detection circuitry can be configured to calculate error detection data for data received from the host interface and to check the integrity of data transmitted to the host interface. The second error detection circuitry can be configured to calculate error correction data for data and first error correction data transmitted to the memory interface and to check integrity of data and first error correction data received from the memory interface.

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Номер записи: 82
31-10-2013 дата публикации

Adjusting direct memory access transfers used in video decoding

Номер: US20130286029A1
Автор: Alexander Rabinovitch, Amichay Amitay, Leonid Dubrovin
Принадлежит: LSI Corp

An apparatus having a first memory and a circuit is disclosed. The first memory may be configured to store a list having a plurality of read requests. The read requests generally (i) correspond to a plurality of blocks of a reference picture and (ii) are used to decode a current picture in a bitstream carrying video. The circuit may be configured to (i) rearrange the read requests in the list based on at least one of (a) a size of a buffer in a second memory and (b) a width of a data bus of the second memory and (ii) copy a portion of the reference picture from the second memory to a third memory using one or more direct memory access transfers in response to the list.

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Номер записи: 83
31-10-2013 дата публикации

ACCESS DEVICE, COMMUNICATION DEVICE, COMMUNICATION SYSTEM, AND DATA ACCESS METHOD

Номер: US20130290586A1
Автор: Maeda Takuji, NAKAMURA Masahiro
Принадлежит:

The access device comprises a memory and a device controller configured to send and receive a data control right between the data recording device and a central controller provided in a host device. When having received a request to interrupt transfer of data from the central controller while data is being transferred from the data recording device, the device controller releases the data control right from the data recording device, and has the data recording device determine whether or not mismatching has occurred in file system management information for data stored in the memory. The device controller then returns the data control right to the data recoding device when it is determined that mismatching has occurred in the file system management information. The data recording device releases the data control right after eliminating the mismatching in the file system management information according to the returned data control right. 1. An access device provided in a host device and configured to control reading or writing of data from or to a memory , in a communication system including a data recording device and the host device that are wirelessly connected to each other , the access device comprising:the memory configured to store data; anda device controller configured to send and receive a data control right between the data recording device and a central controller provided in the host device, the data control right being an exclusive right to execute the reading or the writing of data that is managed by a file system provided in the memory;wherein the device controller is configured to:when having received a request to interrupt transfer of data from the central controller provided in the host device while data is being transferred from the data recording device after the data control right has been granted to the data recording device, release the data control right from the data recording device, and have the data recording device determine whether or ...

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Номер записи: 84
31-10-2013 дата публикации

MICROCOMPUTER

Номер: US20130290587A1
Автор: OGINO Tetsuya
Принадлежит: Denso Corporation

A rewriting area of a flash ROM stores a main program, which includes a user vector with respect to each of interrupt factors that are different from each other in respect of types. The user vector with respect to a subject interrupt factor indicates an address, which stores an interrupt processing program that is executed when the subject interrupt factor arises. This user vector is stored in a predetermined address dedicated for the subject interrupt factor. The predetermined address of the user vector is enabled to be specified by an interrupt vector or interrupt changeover program, both of which are stored in a non-rewriting area of the flash ROM. Even when an address of the interrupt processing program is changed, the changed address is enabled to be indicated by using the user vector. 1. A microcomputer comprising:a CPU that executes selectively (i) a main program and (ii) an onboard rewriting program that executes an onboard rewriting of the main program; anda nonvolatile memory that includes (i) a rewriting permitted area where data are enabled to be rewritten and (ii) a rewriting forbidden area where data are forbidden from being rewritten,the rewriting permitted area storing the main program,the rewriting forbidden area storing the onboard rewriting program,the rewriting forbidden area further storing an interrupt vector with respect to each of a plurality of interrupt factors, the interrupt factors being different from each other,the interrupt vector indicating an address of a branch destination when each of the plurality of interrupt factors arises,the microcomputer further comprising:a change section that uses the address indicated by the interrupt vector and changes a CPU-accessed address, which is an address accessed by the CPU, into either an address within the main program or an address within the onboard rewriting program according to the main program or the onboard rewriting program, whichever is executed,wherein:the main program includes a user ...

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Номер записи: 85
31-10-2013 дата публикации

CORE-DRIVEN TRANSLATION AND LOOPBACK TEST

Номер: US20130290594A1
Автор: CALLAHAN TIMOTHY J., Jutras Brenton S.
Принадлежит:

A translation and loopback test for input/output ports is described. In one example, a method includes receiving a test packet on an output of a high speed processor link, looping the test packet back to an input of the high speed processor link, and detecting the receipt of the looped back test packet to test operation of the high speed link. 1. A method comprising:receiving a test packet on an output of a high speed processor link;looping the test packet back to an input of the high speed processor link; anddetecting the receipt of the looped back test packet to test operation of the high speed link.2. The method of claim 1 , wherein looping back comprises conducting the test packet from an output pin of the processor to a corresponding input pin of the processor.3. The method of claim 2 , wherein looping back comprises conducting the test packet from an output pin of the processor through a circuit board to which the processor is connected to a jumper coupled to the corresponding input pin.4. The method of claim 1 , wherein looping back comprises applying the test packet to an input of a multiplexer of the processor claim 1 , the multiplexer also having the input of the high speed processor link as an input claim 1 , and selecting the looped back test packet input of the multiplexer.5. The method of claim 1 , wherein the test packet comprises a header having a write command to an external component claim 1 , the method further comprising translating the write command to a read command before looping back.6. The method of claim 5 , wherein translating the write command comprises performing a simple logical operation on the write command.7. The method of claim 5 , wherein the test packet comprises a payload of data to support the write command and wherein the translating comprises removing the payload from the test packet.8. The method of claim 5 , wherein the test packet comprises a payload of data to support the write command and wherein translating comprises ...

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Номер записи: 86
07-11-2013 дата публикации

Interrupt coalescing for outstanding input/output completions

Номер: US20130297832A1
Автор: Irfan AHMAD, Mallik Mahalingam, Maxime AUSTRUY
Принадлежит: VMware LLC

In a computer system, a method of controls interrupts which correspond to input/output (I/O) processing. For each delivery of an I/O completion interrupt, the method provides a recordation of a delivery time; identifies I/O completions for which deliveries of corresponding I/O completion interrupts involve deliveries of inter-processor interrupts; and for each of the identified I/O completions, accesses the recordation of the most recent delivery time to determine whether a selected period of time has elapsed since a last delivery of an inter-processor interrupt. As a response to a determination that the selected period has elapsed, an inter-processor interrupt is delivers. As a response to a determination that less than the duration of the selected period has elapsed, the method refrains from delivering an inter-processor interrupt.

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Номер записи: 87
14-11-2013 дата публикации

Managing A Direct Memory Access ('DMA') Injection First-In-First-Out ('FIFO') Messaging Queue In A Parallel Computer

Номер: US20130304948A1
Автор: Brian E. Smith, Josheph D. Ratterman, Michael A. Blocksome, Patrick J. McCarthy, Todd A. Inglett
Принадлежит: International Business Machines Corp

Managing a direct memory access (‘DMA’) injection first-in-first-out (‘FIFO’) messaging queue in a parallel computer, including: inserting, by a messaging unit management module, a DMA message descriptor into the injection FIFO messaging queue; determining, by the messaging unit management module, the number of extra slots in an immediate messaging queue required to store DMA message data associated with the DMA message descriptor; and responsive to determining that the number of extra slots in the immediate message queue required to store the DMA message data is greater than one, inserting, by the messaging unit management module, a number of DMA dummy message descriptors into the injection FIFO messaging queue, wherein the number of DMA dummy message descriptors is at least as many as the number of extra slots in the immediate messaging queue that are required to store the DMA message data.

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Номер записи: 88
14-11-2013 дата публикации

COMPUTER AND INPUT/OUTPUT CONTROL METHOD OF COMPUTER

Номер: US20130304949A1
Автор: HASEGAWA Megumu, MARUYAMA Takafumi
Принадлежит: Hitachi, Ltd.

An HBA driver manages a queue number for enqueuing and dequeuing data to an I/O queue by the main storage, and HBA-F/W manages a storage region at inside of HBA. The HBA driver reduces the number of access times by way of the PCIe bus by noticing an enqueued queue number or a dequeued queue number of an I/O queue to HBA-F/W by utilizing an MMIO area of the main storage in which a storage region on HBA is mapped. 1. An input/output control method of a computer comprising CPU , a main storage connected to the CPU via a bridge , and a host bus adapter (HBA) connected to the CPU and the main storage via a PCIe bus connected to the bridge for transmitting and receiving a data to and from an I/O device ,wherein the HBA comprises an HBA firmware and a storage region,wherein the CPU executes an OS and an HBA driver operated on the OS for controlling the HBA,wherein the main storage comprises an I/O queue from which the data is enqueued or dequeued, a management queue of managing a queue number of the data which is enqueued or dequeued from the I/O queue, an Memory Mapped I/O (MMIO) area in which a storage region of the HBA is mapped,wherein the HBA driver writes a piece of management information of an updated management queue to the MMIO area when the management queue is updated, andwherein the OS writes the piece of management information written to the MMIO area to a storage region of the HBA in correspondence with the MMIO area of the main storage.2. The input/output control method according to claim 1 , wherein claim 1 , when the management queue is updated claim 1 , the HBA driver writes a queue number one queue number before the updated management queue to the MMIO area as the piece of management information.3. The input/output control method according to claim 1 , wherein the I/O queue is at least either one of an I/O activation queue and an I/O response queue.4. The input/output control method according to claim 3 ,wherein in a case where the computer receives the ...

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Номер записи: 89
14-11-2013 дата публикации

Method, System, and Apparatus for Dynamic Reconfiguration of Resources

Номер: US20130304957A1
Автор: Ayyar Mani, Delano Eric Richard, Jayasimha Doddaballapur, Kumar Akhilesh, Schoinas Ioanns Y., Vargas Jose A.
Принадлежит:

A dynamic reconfiguration to include on-line addition, deletion, and replacement of individual modules of to support dynamic partitioning of a system, interconnect (link) reconfiguration, memory RAS to allow migration and mirroring without OS intervention, dynamic memory reinterleaving, CPU and socket migration, and support for global shared memory across partitions is described. To facilitate the on-line addition or deletion, the firmware is able to quiesce and de-quiesce the domain of interest so that many system resources, such as routing tables and address decoders, can be updated in what essentially appears to be an atomic operation to the software layer above the firmware. 12-. (canceled)3. An apparatus comprising:input/output (“I/O”) logic coupled to a point-to-point interconnect capable of coupling caching agents and home agents, the I/O logic including a physical layer to receive an operation based on an interrupt generated in response to an insertion of a resource into a computing system, wherein, in response to the physical layer receiving the operation, the I/O logic to enter a state where no protocol transactions are generated, and wherein during state routing, tables associated with the resource are updated without rebooting an operating system (“OS”) of the computing system.4. The apparatus of claim 3 , wherein if multiple resources are added to multiple OS partitions claim 3 , multiple interrupts are sent to the multiple OS partitions.5. The apparatus of claim 3 , wherein the caching agents and the home agents are coupled to a network fabric adhered to layered protocol scheme and used for transporting messages from one protocol to another protocol claim 3 , wherein the network fabric includes one or more of a link layer claim 3 , a physical layer claim 3 , a protocol layer claim 3 , a routing layer claim 3 , and a transport layer.6. The apparatus of claim 3 , wherein the resource comprises a processor node claim 3 , a memory-only node claim 3 , or an ...

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Номер записи: 90
28-11-2013 дата публикации

DIRECT MEMORY ACCESS (DMA) CONTROLLED MEDICAL DEVICES

Номер: US20130318259A1
Автор: Sherman Neil S.
Принадлежит: SPINAL MODULATION, INC.

A sub-system for controlling a medical device comprises memory including a first table and a second table. The first table stores blocks of event data corresponding to events that are to be performed during a period of time (e.g., a 0.5 sec. or 1 sec. period of time). The second table stores blocks of time data corresponding to the period of time. The implantable stimulation system also includes a direct memory access (DMA) controller including a first DMA channel and a second DMA channel. The first DMA channel selectively transfers one of the blocks event data from the first table to one or more registers that are used to control events. The second DMA channel selectively transfers one of the blocks of time data from the second table to a timer that is used to control timing associated with the events. 1. A sub-system for use in controlling a medical device , the sub-system comprising:a central processing unit (CPU); a plurality of blocks of event data, wherein each said block of event data corresponds to an event that is to occur during a period of time, and', 'a plurality of blocks of time data, wherein each said block of time data is used to specify when a next event is to occur during the period of time;, 'memory that stores'}one or more registers that are used to control events that are to occur during the period of time;a timer that is used to control timing associated with events that are to occur during the period of time; and a first DMA channel that, without CPU intervention, transfers one of the blocks of event data at a time from the memory to the one or more registers that are used to control events that are to occur during the period of time, and', 'a second DMA channel that, without CPU intervention, transfers one of the blocks of time data at a time from the memory to the timer., 'a direct memory access (DMA) controller including'}2. The sub-system of claim 1 , wherein: a count register that stores a count value and increments the count value in ...

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Номер записи: 91
28-11-2013 дата публикации

PROCESSING STRUCTURED AND UNSTRUCTURED DATA USING OFFLOAD PROCESSORS

Номер: US20130318277A1
Автор: Belair Stephen Paul, Dalal Parin Bhadrik
Принадлежит:

A structured data processing system is disclosed that can include a plurality of XIMM modules connected to a memory bus in a first server, with the XIMM modules each respectively having a DMA slave module connected to the memory bus and an arbiter for scheduling tasks, with the XIMM modules providing an in-memory database; and a central processing unit (CPU) in the first server connected to the XIMM modules by the memory bus, with the CPU arranged to process and direct structured queries to the plurality of XIMM modules. 1. A structured data processing system , comprising:a plurality of XIMM modules connected to a memory bus in a first server, with the XIMM modules each respectively having a DMA slave module connected to the memory bus and an arbiter for scheduling tasks, with the XIMM modules providing an in-memory database; anda central processing unit (CPU) in the first server connected to the XIMM modules by the memory bus, with the CPU arranged to process and direct structured queries to the plurality of XIMM modules.2. The structured data processing system of claim 1 , wherein the XIMM modules communicate with each other without requiring access to a processor of the first server.3. The structured data processing system of claim 1 , wherein the XIMM modules are mounted on different servers in the same rack claim 1 , and further comprising a top of the rack switch to mediate communication therebetween.4. The structured data processing system of claim 1 , wherein a XIMM driver executes a mmap routine to transfer a query from the CPU to the XIMM in the form of memory reads/writes.5. The structured data processing system of claim 1 , wherein the XIMM module is configured for insertion into a DIMM socket claim 1 , and the XIMM module further comprises offload processors connected to memory and a computational FPGA.6. A data processing system for unstructured data claim 1 , comprising:a plurality of XIMM modules connected to a memory bus, with the XIMM modules each ...

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Номер записи: 92
05-12-2013 дата публикации

Providing real-time interrupts over ethernet

Номер: US20130322264A1
Автор: Alexander P. Campbell, Keshav G. Kamble, Vijoy A. Pandey
Принадлежит: International Business Machines Corp

In one embodiment, a method includes sending a request to one or more distributed fabric protocol (DFP) system members in order to retrieve one or more events from the one or more DFP system members, wherein the one or more events are received as data encapsulated in a packet(s), receiving one or more acknowledgements to the request from the one or more DFP system members at a local network switch of the DFP system master, upon receipt of the at least one packet: decoding the at least one packet to retrieve details of the one or more events using a dedicated processor of the DFP system master, creating and sending a message signaled interrupt (MSI) comprising the details of the one or more events to a local processor of the DFP system master using the dedicated processor, and reading the MSI using the local processor of the DFP system master.

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Номер записи: 93
05-12-2013 дата публикации

Memory Look Ahead Engine for Video Analytics

Номер: US20130322551A1
Автор: Animesh Mishra, Jose M. Rodriguez, Naveen Doddapuneni
Принадлежит: Intel Corp

Video analytics may be used to assist video encoding by selectively encoding only portions of a frame and using, instead, previously encoded portions. Previously encoded portions may be used when succeeding frames have a level of motion less than a threshold. In such case, all or part of succeeding frames may not be encoded, increasing bandwidth and speed in some embodiments.

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Номер записи: 94
05-12-2013 дата публикации

INTERRUPT RETURN INSTRUCTION WITH EMBEDDED INTERRUPT SERVICE FUNCTIONALITY

Номер: US20130326101A1
Автор: Fang Zhen, ILLIKKAL Ramesh G., Iyer Ravishankar, Jiang Xiaowei, Makineni Shihari
Принадлежит:

An instruction pipeline implemented on a semiconductor chip is described. The semiconductor chip includes an execution unit having the following to execute an interrupt handling instruction. Storage circuitry to hold different sets of micro-ops where each set of micro-ops is to handle a different interrupt. First logic circuitry to execute a set of said sets of micro-ops to handle an interrupt that said set is designed for. Second logic circuitry to return program flow to an invoking program upon said first logic circuitry having handled said interrupt. 1. An instruction pipeline implemented on a semiconductor chip , comprising: a) storage circuitry to hold different sets of micro-ops, each set of micro-ops to handle a different interrupt;', 'b) first logic circuitry to execute a set of said sets of micro-ops to handle an interrupt that said set is designed for;', 'c) second logic circuitry to return program flow to an invoking program upon said first logic circuitry having handled said interrupt., 'an execution unit having the following to execute an interrupt handling instruction2. The instruction pipeline of wherein said storage circuitry is a ROM.3. The instruction pipeline of wherein said execution unit further includes look up table circuitry claim 1 , said look up table circuitry to provide a pointer to one of said sets in said storage circuitry in response to a problem code for said interrupt being presented to said look-up table circuitry.4. The instruction pipeline of wherein said look up table circuitry includes a ROM.5. The instruction pipeline of wherein said look up table circuitry is coupled to a register claim 3 , said register to store said problem code.6. The instruction pipeline of wherein further comprising a register to store a return pointer address.7. The instruction pipeline of wherein said register is coupled to said second logic circuitry.8. An instruction pipeline implemented on a semiconductor chip claim 6 , comprising: a) storage ...

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Номер записи: 95
05-12-2013 дата публикации

Hardware Apparatus for a System, System and Memory Access Method

Номер: US20130326107A1
Автор: Nikolai Horst-Dieter
Принадлежит: ROBERT BOSCH GMBH

A hardware apparatus for a system comprises an interface and a direct memory access device. The interface is configured to connect the hardware apparatus to a system bus, which the hardware apparatus can use to communicate with a central control unit in the system and/or with another hardware apparatus in the system. The direct memory access device is configured to directly access a main memory of the central control unit, and to set an identifier for data flow control in the main memory of the central control unit when the direct memory access device has terminated direct access to a main memory of the system. 1. A hardware apparatus for a system , comprising:an interface configured to connect the hardware apparatus to a system bus, the system bus being usable by the hardware apparatus to communicate with at least one of (i) a central control unit in the system, and (ii) another hardware apparatus in the system; anda direct memory access device configured (i) to directly access a main memory of the central control unit, and (ii) to set an identifier in the main memory of the central control unit for data flow control when the direct memory access device has terminated direct access to a main memory of the system.2. The hardware apparatus according to claim 1 , wherein the direct memory access device is configured to set the identifier separately for each direct memory access channel of a plurality of direct memory access channels of the main memory of the central control unit.3. The hardware apparatus according to claim 1 , wherein the hardware apparatus is a hardware apparatus with master capability.4. A system claim 1 , comprising:a central control unit configured to control the system;a main memory associated with the central control unit and configured to store data used for controlling the system; andat least one hardware apparatus connected to the central control unit via a system bus and configured to directly access the main memory,wherein the main memory ...

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Номер записи: 96
12-12-2013 дата публикации

SELF CLOCKING INTERRUPT GENERATION IN A NETWORK INTERFACE CARD

Номер: US20130332638A1
Автор: MUPPALLA Dharmadeep C.
Принадлежит: JUNIPER NETWORKS, INC.

A network interface card may issue interrupts to a host in which the determination of when to issue an interrupt to the host may be based on the incoming packet rate. In one implementation, an interrupt controller of the network interface card may issue interrupts to that informs a host of the arrival of packets. The interrupt controller may issue the interrupts in response to arrival of a predetermined number of packets, where the interrupt controller re-calculates the predetermined number based on an arrival rate of the incoming packets. 123-. (canceled)24. A method comprising: [ the value being based on an initial number, a number of interrupts generated during another period of time, and a threshold number of interrupts,', 'the other period of time occurring prior to the first period of time, and, 'applying a function to a value to produce a result,'}, 'using the produced result to determine the number;, 'the number being used to generate an interrupt and being determined based on, 'determining, by a device, a number associated with a first quantity of packets to receive during a first period of time,'}receiving, by the device, the first quantity of packets during the first period of time; 'the second number being different than the number;', 'updating, by the device and based on the received first quantity of packets, the number to a second number,'} 'the second period of time being subsequent to the first period of time;', 'receiving, by the device, a second quantity of packets during a second period of time,'}updating, by the device, the second number based on a relationship between the received second quantity of packets and the second number; andissuing, by the device, the interrupt based on the updated second number.25. The method of claim 24 , further comprising:identifying one or more parameters associated with a rate of issuing the interrupt, 'issuing the interrupt based on the one or more parameters.', 'where, when issuing the interrupt, the method ...

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Номер записи: 97
12-12-2013 дата публикации

Computer system

Номер: US20130332925A1
Автор: Hirotaka Motai, Hitoshi Suzuki, Koji Adachi, Yasuhiro Tawara
Принадлежит: Renesas Electronics Corp

There is a need to provide a computer system capable of preventing a failure from propagating and recovering from the failure. VCPU# 0 through VCPU# 2 each operate different OS's. VCPU# 0 operates a management OS that manages the other OS's. When notified of bus error occurrence, a virtual CPU execution portion 201 operates only VCPU# 0 regardless of an execution sequence stored in schedule register A. VCPU# 0 reinitializes a bus where an error occurred.

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Номер записи: 98
19-12-2013 дата публикации

Facilitating transaction completion subsequent to repeated aborts of the transaction

Номер: US20130339327A1
Автор: Brenton F. Belmar, Christian Jacobi, Randall W. Philley, Timothy J. Slegel
Принадлежит: International Business Machines Corp

Processing of transactions within a computing environment is facilitated by taking actions to increase the chances of successfully executing a transaction. A counter is maintained that provides a count of how often a transaction has aborted. The counter increments the count each time the transaction is aborted, and it is reset to zero upon successful completion of the transaction or an interruption leading to no more re-executions of the transaction. If the count reaches a threshold value, then an interrupt is presented and transaction execution is unsuccessful. However, before the count reaches the threshold, a number of actions may be taken to increase the chances of successfully executing the transaction. These actions include actions to be performed within the processor executing the transaction, and/or actions to be performed against conflicting processors.

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Номер записи: 99
19-12-2013 дата публикации

PROGRAM EVENT RECORDING WITHIN A TRANSACTIONAL ENVIRONMENT

Номер: US20130339562A1
Автор: Greiner Dan F., Jacobi Christian, Osisek Damian L., Slegel Timothy J.
Принадлежит: INTERNATIONAL BUSINESS MACHINES CORPORATION

A transaction is initiated within a computing environment, and based on detecting a program event recording event, an interrupt is presented for the transaction. Subsequent to the interrupt, one or more controls are set to inhibit presentation of another interrupt based on detecting another PER event. Thereafter, the transaction is re-executed and PER events detected during execution of the transaction are ignored. 1. A method of controlling transactional execution in a computing environment , the method comprising:initiating, by a processor, a transaction within a computing environment, the transaction effectively delaying committing transactional stores to main memory until completion of a selected transaction, and wherein presentation of interrupts for the transaction is managed by one or more controls, the one or more controls having state associated therewith;presenting an interrupt for the transaction based on detecting a program event recording (PER) event and the state having a first value, PER being defined as presenting an interrupt based on detecting a PER event, the interrupt causing an address to be saved of a next transaction instruction to be executed; andsuppressing PER event detection for the transaction based on the state having a second value.2. The method of claim 1 , further comprising re-executing the transaction based on the interrupt claim 1 , and wherein the state has the second value indicating suppression of PER event detection claim 1 , wherein presentation of another interrupt based on another PER event is prevented.3. The method of claim 2 , wherein the another PER event is a same event as the PER event or a different event than the PER event.4. The method of claim 1 , wherein the one or more controls comprise an event suppression control to specify a suppression of selected PER events claim 1 , and a transaction end event control to trigger an event based on the selected transaction ending.5. The method of claim 4 , wherein the ...

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Номер записи: 100