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Небесная энциклопедия

Космические корабли и станции, автоматические КА и методы их проектирования, бортовые комплексы управления, системы и средства жизнеобеспечения, особенности технологии производства ракетно-космических систем

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Мониторинг СМИ

Мониторинг СМИ и социальных сетей. Сканирование интернета, новостных сайтов, специализированных контентных площадок на базе мессенджеров. Гибкие настройки фильтров и первоначальных источников.

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Поддерживает ввод нескольких поисковых фраз (по одной на строку). При поиске обеспечивает поддержку морфологии русского и английского языка
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Применить Всего найдено 136153. Отображено 100.
05-01-2012 дата публикации

Method and system for managing execution of virtual applications

Номер: US20120005246A1
Автор: Kenji C. Obata
Принадлежит: Code Systems Corp

A system and method for directing download and execution of an application. A runtime engine receives an identifier of a block of shared memory from a directing process. The shared memory stores a map indicating which portions of an application file have been stored in a local copy of the application file. The runtime engine also receives an instruction from the directing process to execute the local copy when the local copy stores less than the entire application file. As the application executes, the runtime engine identifies requests from the application to access portions of the local copy and uses the map to determine whether the requested portions have been stored in the local copy. If the requested portions are not stored in the local copy, the runtime engine prevents the executing application from accessing the local copy until the map indicates the requested portions have been stored therein.

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Номер записи: 1
05-01-2012 дата публикации

Method and apparatus for processing distributed data

Номер: US20120005253A1
Автор: Geert Denys, Kim Marivoet
Принадлежит: EMC Corp

Some embodiments are directed to processing content units stored on a distributed computer system that comprises a plurality of independent nodes. The content units may be processed by determining which content units are stored on each node and identifying which content units warrant processing. Nodes may be selected to process the content units that warrant processing and instructions may be sent to these nodes to instruct them to process these content units.

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Номер записи: 2
05-01-2012 дата публикации

Communication circuit of inter-integrated circuit device

Номер: US20120005385A1
Автор: Ming-Yuan Hsu
Принадлежит: Hon Hai Precision Industry Co Ltd

A communication circuit of an Inter-Integrated Circuit (I2C) includes a master device, a switch circuit, first and second groups of slave devices. Each slave device includes a data signal pin and a clock signal pin, which are connected to the switch circuit. The master device includes a data signal pin, a clock signal pin, and a general purpose input output (GPIO) pin, which are connected to the switch circuit. The GPIO pin of the master device outputs a control signal to the switch circuit, to allow communication between the first group of slave devices and the master device or communication between the second group of slave devices and the master device.

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Номер записи: 3
05-01-2012 дата публикации

Communication between a host device and an accessory via an intermediate device

Номер: US20120005395A1
Автор: Gregory T. Lydon, Jay S. Laefer, John Ananny, Terry Tikalsky
Принадлежит: Apple Inc

A host device and an accessory exchange information (e.g., commands and data) via an intermediate device. The host device and accessory can each connect to the intermediate device through a direct wired path and can exchange commands and data with the intermediate device. The host device and the accessory can also “tunnel” information to each other through the intermediate device, by packaging the tunneled information as a payload of a command recognizable by the intermediate device; the intermediate device can repackage and forward the payload. In some embodiments, the tunneled information relates to configuring a wireless link (e.g., a Bluetooth pairing) between the host device and the accessory.

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Номер записи: 4
05-01-2012 дата публикации

Pre-Emptive Garbage Collection of Memory Blocks

Номер: US20120005405A1
Автор: Jianmin Huang, Neil David Hutchison, Shai Traister, Steven Sprouse, William Wu
Принадлежит: SanDisk Technologies LLC

A method and system pre-emptively perform garbage collection operations of a forced amount on update blocks in a memory device. The amount of garbage collection needed by a certain data write is monitored and adjusted to match the forced amount if necessary. Update blocks may be selected on the basis of their recent usage or the amount of garbage collection required. Another method and system may store control information about update blocks in a temporary storage area so that a greater number of update blocks are utilized. The sequential write performance measured by the Speed Class test may be optimized by using this method and system.

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Номер записи: 5
05-01-2012 дата публикации

Garbage Collection of Memory Blocks Using Volatile Memory

Номер: US20120005406A1
Автор: Neil David Hutchison, Steven Sprouse
Принадлежит: SanDisk Technologies LLC

A method and system for performing garbage collection operations on update blocks in a memory device using volatile memory is disclosed. When performing a garbage collection operation, a first part of the data related to the garbage collection operation is written to a volatile memory in the memory device, and a second part of the data related to the garbage collection operation is written to a non-volatile memory in the memory device. The first part of the data that is written to the volatile memory (such as a random access memory) may comprise control information (such as mapping information of the logical addressable unit to a physical metablock). The second part of the data related to the garbage collection that is written to the non-volatile memory (such as a flash memory) may comprise the consolidated data in the update block.

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Номер записи: 6
05-01-2012 дата публикации

Apparatus for reallocating logical to physical disk devices using a storage controller and method of the same

Номер: US20120005447A1
Автор: Akira Yamamoto, Takao Satoh, Yasutomo Yamamoto
Принадлежит: HITACHI LTD

A storage controller calculates an access frequency of each logical disk; that is selects a first logical disk device of which the access frequency exceeds a first predetermined value, the first logical disk device being allocated to a first physical disk device; selects a second logical disk device which has the access frequency equal to or less than a second predetermined value, the second logical disk device being allocated to a second physical disk device; and reallocates the first and second logical device; and reallocates the first and second logical devices to the second and the first physical disk device, respectively.

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Номер записи: 7
12-01-2012 дата публикации

Optical communication module, universal serial bus cable with the same and processing method of data transfer thereof

Номер: US20120011286A1
Автор: Fukming Lam, Kwokleung Wong, Tinhoi Siu, Wai Hung
Принадлежит: SAE Magnetics HK Ltd

The present invention discloses an optical communication module comprising a second mode supporting a data transfer of USB 3.0 standard and a third mode supporting a data transfer of USB 2.0 standard, and the second mode comprises A mode and B mode with a different power consumption and supported data rate, and a detect unit operative to detect idle state of the data traffic on the data path of USB 3.0 standard to determine to stay on the A mode or enter to the B mode automatically during operation in the second mode. The control circuitry can work in different modes to support different status of devices attachment and removal, different data rate of USB 2.0 and 3.0 standards; and it can real time monitor the data traffic to switch different modes to save power consumption. The present invention also discloses a USB cable and a processing method of data transfer for an optical communication module.

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Номер записи: 8
19-01-2012 дата публикации

Vehicle information unification method which combines with a hand-held electronic device

Номер: US20120016554A1
Автор: Chun-Jung Huang
Принадлежит: ATAN PLASTIC Co Ltd

In a vehicle information unification method which combines with a hand-held electronic device, a hand-held electronic device, which includes a first processor, a first screen and a first transmission interface, is connected with a receiving system of a vehicle. The hand-held electronic device and the receiving system are interconnected within an effective distance through the first transmission interface and a second transmission interface of the receiving system, allowing the receiving system to access digital messages in a storage unit of the hand-held electronic device. The digital messages are computed and a result of computation is outputted for use by the vehicle. By the interconnection between the hand-held electronic device and the receiving system of the vehicle, the vehicle can access and apply information of various hand-held electronic devices to provide the vehicle information that is personalized, convenient and safe.

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Номер записи: 9
19-01-2012 дата публикации

Sharing memory spaces for access by hardware and software in a virtual machine environment

Номер: US20120017029A1
Автор: Jose Renato G. Santos, Yoshio Turner
Принадлежит: Hewlett Packard Development Co LP

Example methods, apparatus, and articles of manufacture to share memory spaces for access by hardware and software in a virtual machine environment are disclosed. A disclosed example method involves enabling a sharing of a memory page of a source domain executing on a first virtual machine with a destination domain executing on a second virtual machine. The example method also involves mapping the memory page to an address space of the destination domain and adding an address translation entry for the memory page in a table. In addition, the example method involves sharing the memory page with a hardware device for direct memory access of the memory page by the hardware device.

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Номер записи: 10
19-01-2012 дата публикации

Caching using virtual memory

Номер: US20120017039A1
Автор: Julien MARGETTS
Принадлежит: PLX Technology Inc

In a first embodiment of the present invention, a method for caching in a processor system having virtual memory is provided, the method comprising: monitoring slow memory in the processor system to determine frequently accessed pages; for a frequently accessed page in slow memory: copy the frequently accessed page from slow memory to a location in fast memory; and update virtual address page tables to reflect the location of the frequently accessed page in fast memory.

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Номер записи: 11
19-01-2012 дата публикации

Managing extended raid caches using counting bloom filters

Номер: US20120017041A1
Автор: Ross E. Zwisler
Принадлежит: LSI Corp

Contentual metadata of an extended cache is stored within the extended cache. The contentual metadata of the extended cache is approximated utilizing a counting Bloom filter. The counting Bloom filter is stored within a primary cache. Contentual metadata of the primary cache is stored within the primary cache. One of a data read or a data write is executed without accessing the contentual metadata of the extended cache stored within the extended cache.

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Номер записи: 12
19-01-2012 дата публикации

Information Handling System Universal Memory Wear Leveling System and Method

Номер: US20120017052A1
Автор: William F. Sauber
Принадлежит: Individual

An information handling system universal memory architecture assigns memory blocks to information handling system functions, such as a persistent storage function and a working storage function, that have different relative rates of writes of information. The blocks are periodically analyzed for remaining memory life to reassign blocks to functions that result in wear leveling across the blocks. For example, blocks having relatively low life remaining that are assigned to functions having a relatively high number of writes have their function switched with blocks that have a relatively high life remaining that are assigned to functions having a relatively low number of writes. In addition, wear leveling performed within a block ensures even wear of the memory cells within the block.

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Номер записи: 13
26-01-2012 дата публикации

Method for Performing a Cryptographic Task in an Electronic Hardware Component

Номер: US20120020476A1
Автор: Gilles Macario-Rat, Henri Gilbert, Olivier Billet
Принадлежит: France Telecom SA

A method and apparatus are provided to perform a cryptographic task on at least one numerical datum in an electronic hardware component. The method includes a step of at least partial use of an encryption function. This encryption function includes a basic encryption function obtained by the addition between an intermediate function arising from composition of a coding function with a first function, and a second function. This method can be applied to the encryption of a datum or to the decryption of a datum. Also, a method is provided for generating a public key and a device able to implement one of these methods.

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Номер записи: 14
26-01-2012 дата публикации

Non-volatile memory with dynamic multi-mode operation

Номер: US20120023285A1
Автор: Jin-Ki Kim
Принадлежит: Mosaid Technologies Inc

A method and system for extending the life span of a flash memory device. The flash memory device is dynamically configurable to store data in the single bit per cell (SBC) storage mode or the multiple bit per cell (MBC) mode, such that both SBC data and MBC data co-exist within the same memory array. One or more tag bits stored in each page of the memory is used to indicate the type of storage mode used for storing the data in the corresponding subdivision, where a subdivision can be a bank, block or page. A controller monitors the number of program-erase cycles corresponding to each page for selectively changing the storage mode in order to maximize lifespan of any subdivision of the multi-mode flash memory device.

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Номер записи: 15
02-02-2012 дата публикации

Automated detection of sleep and waking states

Номер: US20120029378A1
Автор: Philip Low
Принадлежит: SALK INSTITUTE FOR BIOLOGICAL STUDIES

Determining low power frequency range information from spectral data. Raw signal data can be adjusted to increase dynamic range for power within low power frequency ranges as compared to higher-power frequency ranges to determine adjusted source data valuable for acquiring low power frequency range information. Low power frequency range information can be used in the analysis of a variety of raw signal data. For example, low power frequency range information within electroencephalography data for a subject from a period of sleep can be used to determine sleep states. Similarly, automated full-frequency spectral electroencephalography signal analysis can be useful for customized analysis including assessing sleep quality, detecting pathological conditions, and determining the effect of medication on sleep states.

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Номер записи: 16
09-02-2012 дата публикации

Semiconductor storage device with volatile and nonvolatile memories

Номер: US20120033496A1
Автор: Hidenori Matsuzaki, Hirokuni Yano, Kazuya Kitsunai, Shigehiro Asano, Shinichi Kanno, Toshikatsu Hida
Принадлежит: Individual

A semiconductor storage device includes a first memory area configured in a volatile semiconductor memory, second and third memory areas configured in a nonvolatile semiconductor memory, and a controller which executes following processing. The controller executes a first processing for storing a plurality of data by the first unit in the first memory area, a second processing for storing data outputted from the first memory area by a first management unit in the second memory area, and a third processing for storing data outputted from the first memory area by a second management unit in the third memory area.

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Номер записи: 17
09-02-2012 дата публикации

Information Processing Apparatus, Information Processing Method, and Program

Номер: US20120035927A1
Автор: Keiichi Yamada, Tsutomu Sawada
Принадлежит: Sony Corp

An information processing apparatus includes a plurality of information input units that inputs observation information of a real space, an event detection unit that generates event information including estimated position information and estimated identification (ID) information of a user present in the real space based on analysis of the information input from the information input unit, and an information integration processing unit that inputs the event information, and generates target information including a position and user ID information of each user based on the input event information and signal information representing a probability value for an event generating source. Here, the information integration processing unit includes an utterance source probability calculation unit having an identifier, and calculates an utterance source probability based on input information using the identifier in the utterance source probability calculation unit.

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Номер записи: 18
09-02-2012 дата публикации

Rule based aggregation of files and transactions in a switched file system

Номер: US20120036107A1
Автор: Peter Nickolov, Vladimir Miloushev
Принадлежит: F5 Networks Inc

A switched file system, also termed a file switch, is logically positioned between client computers and file servers in a computer network. The file switch distributes user files among multiple file servers using aggregated file, transaction and directory mechanisms. The file switch distributes and aggregates the client data files in accordance with a predetermined set of aggregation rules. Each rule can be modified independently of the other rules. Different aggregation rules can be used for different types of files, thereby adapting the characteristics of the switched file system to the intended use and to the expected or historical access patterns for different data files.

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Номер записи: 19
09-02-2012 дата публикации

Coordinated garbage collection for raid array of solid state disks

Номер: US20120036309A1
Автор: David A. Dillow, Feiyi Wang, Galen M. Shipman, Hakki S. Oral, Youngjae Kim
Принадлежит: UT Battelle LLC

An optimized redundant array of solid state devices may include an array of one or more optimized solid-state devices and a controller coupled to the solid-state devices for managing the solid-state devices. The controller may be configured to globally coordinate the garbage collection activities of each of said optimized solid-state devices, for instance, to minimize the degraded performance time and increase the optimal performance time of the entire array of devices.

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Номер записи: 20
09-02-2012 дата публикации

Wear Leveling Technique for Storage Devices

Номер: US20120036312A1
Автор: Jonathan Haines, Timothy Feldman
Принадлежит: SEAGATE TECHNOLOGY LLC

A method for managing wear levels in a storage device having a plurality of data blocks, the method comprising moving data to data blocks having higher erasure counts based on a constraint on static wear levelness that tightens over at least a portion of the lives of the plurality of data blocks.

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Номер записи: 21
16-02-2012 дата публикации

Scatter-Gather Intelligent Memory Architecture For Unstructured Streaming Data On Multiprocessor Systems

Номер: US20120042121A1
Автор: Christopher J. Hughes, Daehyun Kim, Partha Kundu, Yen-Kuang Chen
Принадлежит: Individual

A scatter/gather technique optimizes unstructured streaming memory accesses, providing off-chip bandwidth efficiency by accessing only useful data at a fine granularity, and off-loading memory access overhead by supporting address calculation, data shuffling, and format conversion.

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Номер записи: 22
16-02-2012 дата публикации

Intelligent cache management

Номер: US20120042123A1
Автор: Curt Kolovson
Принадлежит: Curt Kolovson

An exemplary storage network, storage controller, and methods of operation are disclosed. In one embodiment, a method of managing cache memory in a storage controller comprises receiving, at the storage controller, a cache hint generated by an application executing on a remote processor, wherein the cache hint identifies a memory block managed by the storage controller, and managing a cache memory operation for data associated with the memory block in response to the cache hint received by the storage controller.

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Номер записи: 23
23-02-2012 дата публикации

Multiplexing application and debug channels on a single usb connection

Номер: US20120047295A1
Автор: Chi Kwok Wong
Принадлежит: Individual

A computer system for software development and debugging for an embedded system includes a Universal Serial Bus (USB), a host computer comprising a USB driver interfaced with the USB, wherein the USB driver can multiplex application data and debug data to and from the USB, and an embedded system comprising a USB module interfaced with the USB. The USB module can multiplex the application data and the debug data to and from the host computer via the USB.

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Номер записи: 24
23-02-2012 дата публикации

Redundant array of independent clouds

Номер: US20120047339A1
Автор: Allen Samuels, Dan Decasper, Jonathan Stone
Принадлежит: CIRTAS SYSTEMS Inc

A computing device executing a reliable cloud storage module divides data into a first data block and a second data block. The computing device stores the first data block in a first storage cloud provided by a first storage service, and stores the second data block in a second storage cloud provided by a second storage service. The computing device thereafter receives a command to read the data. In response, the computing device retrieves the first data block from the first storage cloud and the second data block from the second storage cloud. The computing device then reproduces the original data from the first data block and the second data block.

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Номер записи: 25
23-02-2012 дата публикации

Virtualization with fortuitously sized shadow page tables

Номер: US20120047348A1
Автор: Gerald A. FRY, Lawrence S. Rogel, Prashanth P. BUNGALE, Scott W. Devine
Принадлежит: VMware LLC

One or more embodiments provides a shadow page table used by a virtualization software wherein at least a portion of the shadow page table shares computer memory with a guest page table used by a guest operating system (OS) and wherein the virtualization software provides a mapping of guest OS physical pages to machine pages.

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Номер записи: 26
01-03-2012 дата публикации

Sampling phase correcting host controller, semiconductor device and method

Номер: US20120049919A1
Автор: Masayoshi Murayama, Noriyo Fujii
Принадлежит: Toshiba Corp

One embodiment provides a host controller which performs a phase shift correction of a sampling clock when sampling a signal received, includes a phase shift judging section which judges whether or not it is necessary to shift a phase of the sampling clock, and up/down counts a counter in accordance with a shift direction when judging that it is necessary to shift the phase, a limit value storage section which stores a variance range limit value of the phase shift, and a shift limit judging section which judges whether or not a value of the counter exceeds the limit value of the phase shift, notifies a host device of an error when judging that the counter value exceeds the limit value, and shifts the phase of the sampling clock in accordance with the counter value of the counter when judging that the counter value does not exceed the limit value.

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Номер записи: 27
01-03-2012 дата публикации

Object File System

Номер: US20120054252A1
Автор: Craig Robertson, Dan Olster, Dave Fellinger, Doug Schafer, Jan Olderdissen
Принадлежит: Individual

An object based file system for storing and accessing objects is disclosed. The file system may be implemented as a method in hardware, firmware, software, or a combination thereof. The method may include receiving from an application program an object write request. A selected storage node on which to store the object may be selected, including identifying a least busy storage node and/or a least full storage node. The object and the object write request may be sent to the selected storage node. A write success message may be received from the selected storage node. The successful writing of the object may be reported to the application program. An object identifier and object data may be stored in a database.

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Номер записи: 28
01-03-2012 дата публикации

Methods and apparatus for improved serial advanced technology attachment performance

Номер: US20120054403A1
Автор: Brian A. Day
Принадлежит: LSI Corp

Methods and apparatus for improved performance in communications with a SATA target device. Features and aspects hereof provide for continuing DMA transfers from a storage controller (e.g., a SATA host or a SAS/STP initiator) to a SATA target device without regard to receipt of DMA ACTIVATE Frame Information Structures (FIS). Logic to implement these features may be provided by bridge logic within an enhanced SAS expander coupled with an enhanced SAS/STP initiator or may be provided by suitable logic in an enhanced SATA host coupled directly with an enhanced SATA target device. By continuing DMA transfer of data from the initiator/host to the SATA target device without regard to receipt of a DMA ACTIVATE FIS, more of the available bandwidth of the SAS/SATA communication link may be utilized. Other standard features of the SAS/SATA protocols provide for flow control to prevent overrun of the SATA target device's buffers.

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Номер записи: 29
01-03-2012 дата публикации

Memory device and operating method thereof

Номер: US20120054419A1
Автор: CHEN Xiu, LIANG Chen
Принадлежит: Via Technologies Inc

The invention provides a memory device. In one embodiment, the memory device comprises a flash memory, a memory, and a controller. The flash memory comprises a plurality of blocks for data storage. The memory stores an address mapping table recording relationships between logical addresses and physical addresses of the blocks therein. The controller divides the address mapping table stored in the memory to a plurality of mapping table units, updates relationships between the logical addresses and the physical addresses stored in the mapping table units, determines whether data access performed to the flash memory fulfills the conditions of a first specific requirement, and when the data access fulfills the conditions of the first requirement, the controller selects a target mapping table unit from the mapping table units, and stores the target mapping table unit and a corresponding time stamp as a mapping table unit data to the flash memory.

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Номер записи: 30
01-03-2012 дата публикации

Load Balancing Scheme In Multiple Channel DRAM Systems

Номер: US20120054423A1
Автор: Feng Wang, Jonghae Kim, Matthew Michael Nowak, Shiqun Gu
Принадлежит: Qualcomm Inc

A load balancing in a multiple DRAM system comprises interleaving memory data across two or more memory channels. Access to the memory channels is controlled by memory controllers. Bus masters are coupled to the memory controllers via an interconnect system and memory requests are transmitted from the bus masters to the memory controller. If congestion is detected in a memory channel, congestion signals are generated and transmitted to the bus masters. Memory requests are accordingly withdrawn or rerouted to less congested memory channels based on the congestion signals.

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Номер записи: 31
01-03-2012 дата публикации

Method and system for placement of data on a storage device

Номер: US20120054433A1
Автор: George J. Scholhamer, III, Ryan A. Callison, William C. Galloway
Принадлежит: Pivot3 Inc

Embodiments of systems and methods for a storage system are disclosed. More particularly, in certain embodiments locations of storage devices may be allocated to store data when commands pertaining to that data are received. Specifically, in one embodiment a distributed RAID system comprising a set of data banks may be provided where the different performance characteristics associated with different areas of disks in the data bank may be taken into account when allocating physical segments to corresponding logical segments of a volume by allocating certain physical segments to a particular logical segment based upon a location of the physical segment or criteria associated with the logical segment.

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Номер записи: 32
01-03-2012 дата публикации

Method and apparatus for fuzzy stride prefetch

Номер: US20120054449A1
Автор: Shiliang Hu, Youfeng Wu
Принадлежит: Intel Corp

In one embodiment, the present invention includes a prefetching engine to detect when data access strides in a memory fall into a range, to compute a predicted next stride, to selectively prefetch a cache line using the predicted next stride, and to dynamically control prefetching. Other embodiments are also described and claimed.

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Номер записи: 33
08-03-2012 дата публикации

Distribution processing method, distribution processing device, print data processing method, print data processing device, and recording medium

Номер: US20120057202A1
Автор: Akio Takamoto, Hitoshi Oyama, Tadashi Furuhata, Tomohiro Kodama
Принадлежит: Seiko Epson Corp

Data output from an existing application to specific devices can be easily distributed to plural devices. A method of distributing device-specific data output from an application on a computer that executes a specific process according to an application and has two or more communication ports causes the computer to execute a step of acquiring device-specific data output by an executed program to one specific communication port at the operating system kernel layer before the device-specific data is received at the communication port; and a step of analyzing the device-specific data acquired at the application layer, determines the device to which the device-specific data, and outputs the device-specific data to the communication port to which the device is connected.

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Номер записи: 34
08-03-2012 дата публикации

Method for Assigning Addresses to Nodes of a Bus System, and Installation

Номер: US20120059959A1
Автор: Olaf Simon
Принадлежит: SEW Eurodrive GmbH and Co KG

A method for assigning addresses to nodes of a bus system, and installation, bus nodes being furnished with an identical delivery address, where (i) an assigning entity, particularly a central computer, start-up computer or bus node sends information to the delivery address via the bus system, (ii) the information includes a first address, (iii) an action is performed whose effect is detected by a first bus node, (iv) the first bus node accepts the first address, (v) the first bus node sends a response to the assigning entity, (vi) steps (i) through (v) are repeated, each time with a further address for a further bus node.

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Номер записи: 35
08-03-2012 дата публикации

Precision synchronisation architecture for superspeed universal serial bus devices

Номер: US20120059965A1
Автор: Peter Graham Foster
Принадлежит: CHRONOLOGIC PTY LTD

A method of providing a synchronisation channel to a SuperSpeed USB device is provided. The method including a SuperSpeed communication channel connection to the SuperSpeed USB device with a USB cable that has USB 2.0 D+ and D− data signalling lines disabled or disconnected at an upstream connection point; multiplexing synchronization information onto the D+/D− data signalling lines at the upstream connection point; and demultiplexing the synchronization information from the D+/D− signalling lines at a downstream connection point of the cable; whereby the synchronisation channel is maintained across the D+/D− data signalling lines.

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Номер записи: 36
08-03-2012 дата публикации

Method and apparatus for handling critical blocking of store-to-load forwarding

Номер: US20120059971A1
Автор: Bradley Burgess, Christopher D. Bryant, David Kaplan, Tarun Nakra
Принадлежит: Advanced Micro Devices Inc

The present invention provides a method and apparatus for handling critical blocking of store-to-load forwarding. One embodiment of the method includes recording a load that matches an address of a store in a store queue before the store has valid data. The load is blocked because the store does not have valid data. The method also includes replaying the load in response to the store receiving valid data so that the valid data is forwarded from the store queue to the load.

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Номер записи: 37
08-03-2012 дата публикации

Hybrid memory management

Номер: US20120059992A1
Автор: John Geldman, Martin Ragnar Furuhjelm, Michael Murray, William H. Radke
Принадлежит: Micron Technology Inc

Methods and apparatus for managing data storage in hybrid memory devices utilizing single level and multi level memory cells. Logical addresses can be distributed between single level and multilevel memory cells based on a frequency of write operations performed. Initial storage of data corresponding to a logical address in memory can be determined by various methods including initially writing all data to single level memory or initially writing all data to multilevel memory. Other methods permit a host to direct logical address writes to single level or multilevel memory cells based on anticipated usage.

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Номер записи: 38
08-03-2012 дата публикации

Method for using bad blocks of flash memory

Номер: US20120060054A1
Автор: Junhong Weng, Yingtong Sun
Принадлежит: Nationz Technologies Inc

A method is provided for using bad blocks in flash memory. The method includes placing in a replacement area of the flash memory a special bad block that meets a “still usable” condition from the bad blocks of the flash memory. The method also includes receiving a use request for using the special bad block in the replacement area to store user data, writing the user data into the special bad block, and determining whether the user data is successfully written into the special bad block. Further, the method includes placing the special bad block back into the replacement area for a next use request when it is determined that the user data is not successfully written into the special bad block.

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Номер записи: 39
15-03-2012 дата публикации

Synchronous network of superspeed and non-superspeed usb devices

Номер: US20120066418A1
Автор: Peter Graham Foster
Принадлежит: CHRONOLOGIC PTY LTD

A method of synchronising the operation of a plurality of SuperSpeed USB devices and a plurality of non-SuperSpeed USB devices is provided. The method includes establishing a SuperSpeed synchronisation channel for each of the plurality of SuperSpeed USB devices; establishing a non-SuperSpeed synchronisation channel for each of the plurality of non-SuperSpeed USB devices; synchronising a respective local clock of each of the plurality of SuperSpeed USB devices; synchronising a respective local clock of each of the plurality of non-SuperSpeed USB devices; and synchronising the SuperSpeed and non-SuperSpeed synchronisation channels so that the SuperSpeed and non-SuperSpeed devices can operate in synchrony.

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Номер записи: 40
15-03-2012 дата публикации

Method and system for transferring high-speed data within a portable device

Номер: US20120066422A1
Автор: Morgan Monks
Принадлежит: Standard Microsystems LLC

A system for high-speed data transfer within a portable device, such as, cell phone or a set-top box, which includes a memory medium and a processor. The system includes a first port for coupling to the processor, and a second port for coupling to the memory medium. Further, the system includes an embedded Universal Serial Bus (USB) host configured for receiving data transfer commands from the processor, and transferring data at high speed between a USB device on the processor and the memory medium. Moreover, a data path is provided between the embedded USB host and the first port.

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Номер записи: 41
15-03-2012 дата публикации

Scheduling of i/o writes in a storage environment

Номер: US20120066435A1
Автор: Bo Hong, Craig Harmer, Ethan MILLER, Feng Wang, John Colgrove, John Hayes
Принадлежит: Pure Storage Inc

A system and method for effectively scheduling read and write operations among a plurality of solid-state storage devices. A computer system comprises client computers and data storage arrays coupled to one another via a network. A data storage array utilizes solid-state drives and Flash memory cells for data storage. A storage controller within a data storage array comprises an I/O scheduler. The data storage controller is configured to receive requests targeted to the data storage medium, said requests including a first type of operation and a second type of operation. The controller is further configured to schedule requests of the first type for immediate processing by said plurality of storage devices, and queue requests of the second type for later processing by the plurality of storage devices. Operations of the first type may correspond to operations with an expected relatively low latency, and operations of the second type may correspond to operations with an expected relatively high latency.

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Номер записи: 42
15-03-2012 дата публикации

Apparatus, system, and method for managing lifetime of a storage device

Номер: US20120066439A1
Автор: Jeremy Fillingim
Принадлежит: Fusion IO LLC

An apparatus, system, and method are disclosed for managing lifetime for a data storage device. A target module determines a write bandwidth target for a data storage device. An audit module monitors write bandwidth of the data storage device relative to the write bandwidth target. A throttle module adjusts execution of one or more write operations on the data storage device in response to the write bandwidth of the data storage device failing to satisfy the write bandwidth target.

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Номер записи: 43
15-03-2012 дата публикации

Systems and methods for averaging error rates in non-volatile devices and storage systems

Номер: US20120066441A1
Автор: Hanan Weingarten
Принадлежит: Densbits Technologies Ltd

A system for storing a plurality of logical pages in a set of at least one flash device, each flash device including a set of at least one erase block, the system comprising apparatus for distributing at least one of the plurality of logical pages over substantially all of the erase blocks in substantially all of the flash devices, thereby to define, for at least one logical page, a sequence of pagelets thereof together including all information on the logical page and each being stored within a different erase block in the set of erase blocks; and apparatus for reading each individual page from among the plurality of logical pages including apparatus for calling and ordering the sequence of pagelets from different erase blocks in the set of erase blocks.

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Номер записи: 44
15-03-2012 дата публикации

System and method of page buffer operation for memory devices

Номер: US20120066442A1
Автор: Hakjune Oh, Hong Beom Pyeon, Jin-Ki Kim
Принадлежит: Mosaid Technologies Inc

Systems and methods are provided for using page buffers of memory devices connected to a memory controller through a common bus. A page buffer of a memory device is used as a temporary cache for data which is written to the memory cells of the memory device. This can allow the memory controller to use memory devices as temporary caches so that the memory controller can free up space in its own memory.

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Номер записи: 45
15-03-2012 дата публикации

Compound universal serial bus architecture providing precision synchronisation to an external timebase

Номер: US20120066537A1
Автор: Peter Graham Foster
Принадлежит: CHRONOLOGIC PTY LTD

A method of synchronising a compound Super Speed USB device, comprising: providing data communication between a host computing device and the compound Super Speed USB device across the Super Speed USB communication channel; establishing a Super Speed USB communication channel to a Super Speed USB function of the compound USB device; establishing a non-Super Speed synchronisation channel to a non-Super Speed USB function of the compound USB device; and synchronising a local clock of the compound USB device to a periodic data structure within a data stream in the non-Super Speed synchronisation channel so that the local clock can enable synchronous operation of the compound USB device with one or more comparable USB devices.

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Номер записи: 46
22-03-2012 дата публикации

Memory system having high data transfer efficiency and host controller

Номер: US20120072618A1
Автор: Akihisa Fujimoto
Принадлежит: Individual

According to one embodiment, the host controller includes a register set to issue command, and a direct memory access (DMA) unit and accesses a system memory and a device. First, second, third and fourth descriptors are stored in the system memory. The first descriptor includes a set of a plurality of pointers indicating a plurality of second descriptors. Each of the second descriptors comprises the third descriptor and fourth descriptor. The third descriptor includes a command number, etc. The fourth descriptor includes information indicating addresses and sizes of a plurality of data arranged in the system memory. The DMA unit sets, in the register set, the contents of the third descriptor forming the second descriptor, from the head of the first descriptor as a start point, and transfers data between the system memory and the host controller in accordance with the contents of the fourth descriptor.

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Номер записи: 47
22-03-2012 дата публикации

Selection of Units for Garbage Collection in Flash Memory

Номер: US20120072639A1
Автор: Mark Allen Gaertner, Ryan James Goss
Принадлежит: SEAGATE TECHNOLOGY LLC

A data structure is formed that references a garbage collection metric for each of a plurality of associated garbage collection units of a flash memory device. Each garbage collection metric is based on one or more device state characteristics of the associated garbage collection unit. In response to a threshold change in the one or more device state variables, a region of interest within the data structure is sorted based on the garbage collection metrics. One or more garbage collection units are selected for garbage collection operations from the sorted region of interest.

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Номер записи: 48
22-03-2012 дата публикации

Different types of memory integrated in one chip by using a novel protocol

Номер: US20120072647A1
Автор: Fu-Chang Hsu, Peter Wung Lee
Принадлежит: Aplus Flash Technology Inc

A semiconductor chip contains four different memory types, EEPROM, NAND Flash, NOR Flash and SRAM, and a plurality of major serial/parallel interfaces such as I 2 C, SPI, SDI and SQI in one memory chip. The memory chip features write-while-write and read-while-write operations as well as read-while-transfer and write-while-transfer operations. The memory chip provides for eight pins of which two are for power and up to four pins have no connection for specific interfaces and uses a novel unified nonvolatile memory design that allow the integration together of the aforementioned memory types integrated together into the same semiconductor memory chip.

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Номер записи: 49
29-03-2012 дата публикации

Hierarchical Memory Addressing

Номер: US20120075319A1
Автор: William James Dally
Принадлежит: Nvidia Corp

One embodiment of the present invention sets forth a technique for addressing data in a hierarchical graphics processing unit cluster. A hierarchical address is constructed based on the location of a storage circuit where a target unit of data resides. The hierarchical address comprises a level field indicating a hierarchical level for the unit of data and a node identifier that indicates which GPU within the GPU cluster currently stores the unit of data. The hierarchical address may further comprise one or more identifiers that indicate which storage circuit in a particular hierarchical level currently stores the unit of data. The hierarchical address is constructed and interpreted based on the level field. The technique advantageously enables programs executing within the GPU cluster to efficiently access data residing in other GPUs using the hierarchical address.

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Номер записи: 50
29-03-2012 дата публикации

Nonvolatile semiconductor memory device with advanced multi-page program operation

Номер: US20120079173A1
Автор: Dong-Hyuk Chae, Young-Ho Lim
Принадлежит: SAMSUNG ELECTRONICS CO LTD

A nonvolatile semiconductor memory device includes a memory cell array having a plurality of banks and a cache block corresponding to each of the plurality of banks. The cache block has a predetermined data storage capacity. A page buffer is included which corresponds to each of the plurality of banks. A programming circuit programs all of the plurality of banks except a last of said banks with page data. The page data is loaded through each page buffer and programmed into each cache block such that when page data for the last bank is loaded into the page buffer, the loaded page data and the page data programmed into the respective cache blocks are programmed into respective corresponding banks.

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Номер записи: 51
29-03-2012 дата публикации

Intra-device data protection in a raid array

Номер: US20120079189A1
Автор: Bo Hong, Ethan MILLER, John Colgrove, John Hayes
Принадлежит: Pure Storage Inc

A system and method for intra-device data protection in a RAID array. A computer system comprises client computers and data storage arrays coupled to one another via a network. A data storage array utilizes solid-state drives and Flash memory cells for data storage. A storage controller within a data storage array is configured to identify a unit of data stored in the data storage subsystem, wherein said unit of data is stored across at least a first storage device and a second storage device of the plurality of storage devices, each of the first storage device and the second storage device storing intra-device redundancy data corresponding to the unit of data; and change an amount of intra-device redundancy data corresponding to the unit of data on only the first storage device.

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Номер записи: 52
29-03-2012 дата публикации

Cache with Multiple Access Pipelines

Номер: US20120079204A1
Автор: Abhijeet Ashok Chachad, Jonathan (Son) Hung Tran, Raguram Damodaran, Sanjive Agarwala, Timothy David Anderson
Принадлежит: Texas Instruments Inc

Parallel pipelines are used to access a shared memory. The shared memory is accessed via a first pipeline by a processor to access cached data from the shared memory. The shared memory is accessed via a second pipeline by a memory access unit to access the shared memory. A first set of tags is maintained for use by the first pipeline to control access to the cache memory, while a second set of tags is maintained for use by the second pipeline to access the shared memory. Arbitrating for access to the cache memory for a transaction request in the first pipeline and for a transaction request in the second pipeline is performed after each pipeline has checked its respective set of tags.

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Номер записи: 53
29-03-2012 дата публикации

Method and apparatus for reducing processor cache pollution caused by aggressive prefetching

Номер: US20120079205A1
Автор: Patrick Conway
Принадлежит: Advanced Micro Devices Inc

A method and apparatus for controlling a first and second cache is provided. A cache entry is received in the first cache, and the entry is identified as having an untouched status. Thereafter, the status of the cache entry is updated to accessed in response to receiving a request for at least a portion of the cache entry, and the cache entry is subsequently cast out according to a preselected cache line replacement algorithm. The cast out cache entry is stored in the second cache according to the status of the cast out cache entry.

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Номер записи: 54
05-04-2012 дата публикации

Method and apparatus for compressed sensing

Номер: US20120082344A1
Автор: David Leigh Donoho
Принадлежит: David Leigh Donoho

Method and apparatus for compressed sensing yields acceptable quality reconstructions of an object from reduced numbers of measurements. A component x of a signal or image is represented as a vector having m entries. Measurements y, comprising a vector with n entries, where n is less than m, are made. An approximate reconstruction of the m-vector x is made from y. Special measurement matrices allow measurements y=Ax+z, where y is the measured m-vector, x the desired n-vector and z an m-vector representing noise. “A” is an n by m matrix, i.e. an array with fewer rows than columns. “A” enables delivery of an approximate reconstruction, x # ′ of x. An embodiment discloses approximate reconstruction of x from the reduced-dimensionality measurement y. Given y, and the matrix A, approximate reconstruction x # of x is possible. This embodiment is driven by the goal of promoting the approximate sparsity of x # .

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Номер записи: 55
05-04-2012 дата публикации

Wireless accessory device pairing transfer between multiple host devices

Номер: US20120083208A1
Автор: Adrian E. Sun, Christopher T. MULLENS, Craig P. Dooley, Jack I-Chieh Fu, Michael J. Giles
Принадлежит: Apple Inc

A wireless communications system includes an accessory device and multiple host devices. A host device pairs wirelessly with an accessory device using a unique link key, detects a primary trigger event and responds by transferring automatically its pairing with the accessory device to a second host device while all devices remain within wireless range of each other. The pairing transfer involves communicating the link key to the second host device, unpairing the accessory device from the first host device, and establishing a wireless pairing of the accessory device to the second host device. The primary trigger event can involve establishing a ported connection between host devices. A secondary trigger event results in the first host device automatically reclaiming its pairing with the accessory device. An accessory device can also select and pair with one of multiple host devices in response to a specific user gesture detected by the accessory device.

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Номер записи: 56
05-04-2012 дата публикации

Tracking written addresses of a shared memory of a multi-core processor

Номер: US20120084498A1
Автор: Charles Edwards Peet, JR., Chris Randall Stone, David Sonnier
Принадлежит: LSI Corp

Described embodiments provide a method of controlling processing flow in a network processor having one or more processing modules. A given one of the processing modules loads a script into a compute engine. The script includes instructions for the compute engine. The given one of the processing modules loads a register file into the compute engine. The register file includes operands for the instructions of the loaded script. A tracking vector of the compute engine is initialized to a default value, and the compute engine executes the instructions of the loaded script based on the operands of the loaded register file. The compute engine updates corresponding portions of the register file with updated data corresponding to the executed script. The tracking vector tracks the updated portions of the register file. The compute engine provides the tracking vector and the updated register file to the given one of the processing modules.

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Номер записи: 57
05-04-2012 дата публикации

Reconstruct reads in a raid array with dynamic geometries

Номер: US20120084505A1
Автор: Bo Hong, Ethan MILLER, John Colgrove, John Hayes
Принадлежит: Pure Storage Inc

A system and method for dynamic RAID geometries. A computer system comprises client computers and data storage arrays coupled to one another via a network. A data storage array utilizes solid-state drives and Flash memory cells for data storage. A storage controller within a data storage array is configured to configure a first subset of the storage devices for use in a first RAID layout, the first RAID layout including a first set of redundant data. The controller further configures a second subset of the storage devices for use in a second RAID layout, the second RAID layout including a second set of redundant data. Additionally, the controller configure an additional device not included in either the first subset or the second subset to store redundant data for both the first RAID layout and the second RAID layout. The controller is further configured to initiate a reconstruct read corresponding to a given read request directed to a particular storage device of the plurality of storage devices, in response to determining the particular storage device is exhibiting a non-error related relatively slow read response.

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Номер записи: 58
05-04-2012 дата публикации

Circuit and method for determining memory access, cache controller, and electronic device

Номер: US20120084513A1
Автор: Kazuhiko Okada
Принадлежит: Fujitsu Semiconductor Ltd

A memory access determination circuit includes a counter that switches between a first reference value and a second reference value in accordance with a control signal to generate a count value based on the first reference value or the second reference value. A controller performs a cache determination based on an address that corresponds to the count value and outputs the control signal in accordance with the cache determination. A changing unit changes the second reference value in accordance with the cache determination.

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Номер записи: 59
12-04-2012 дата публикации

Pedobarographic biometric system

Номер: US20120086550A1
Автор: Donald Joseph LeBlanc, Julia Petruescu, Paul A. Bennett
Принадлежит: Individual

A method and system to characterize the wearer of at least one item of footwear having a sensor means which, while the item is being worn, collects from the wearer current pedobarometric data that is characteristic of the wearer, and the current pedobarometric data is compared with corresponding reference data for a specified wearer, preferably previously collected via the same or a similar item of footwear while worn by the specified wearer under controlled conditions, the results of the comparison being used to characterize the present wearer according to prescribed criteria.

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Номер записи: 60
12-04-2012 дата публикации

Method of adjusting transfer speed after initialization of SATA interface

Номер: US20120089755A1
Автор: Hsieh-Huan Yen, Huei-Chiang Shiu, Teng-Chuan Hsieh
Принадлежит: Individual

In a method of adjusting transfer speed after initialization of a SATA interface, a SATA link device transmits a first predetermined primitive to a SATA link partner for requesting to change a first transfer speed of the SATA link device from a first speed to a second speed, the SATA link partner replies to the SATA link device with a second predetermined primitive according to the first predetermined primitive, and the SATA link device and the SATA link partner respectively adjust the first transfer speed of the SATA link device and a second transfer speed of the SATA link partner according to the second predetermined primitive.

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Номер записи: 61
12-04-2012 дата публикации

Memory storage device, memory controller thereof, and method for automatically creating fill-file thereof

Номер: US20120089805A1
Автор: Sing-Chang Liu
Принадлежит: Phison Electronics Corp

A memory storage device, a memory controller thereof, and a method for automatically creating a fill-file thereof are provided. In the present method, a plurality of logical addresses is configured and grouped into a plurality of logical blocks to be mapped to physical blocks of a memory chip in the memory storage device. When a host system is powered on, whether the logical addresses have been formatted into a partition is determined. If the logical addresses have been formatted into a partition, whether a fill-file of a predetermined file capacity exists is determined. If the fill-file does not exist, data related to the fill-file is respectively filled into a file allocation table (FAT) and a root directory of the formatted partition when the host system reads the FAT and the root directory, so as to automatically create the fill-file.

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Номер записи: 62
12-04-2012 дата публикации

Query sampling information instruction

Номер: US20120089816A1
Автор: Damian L. Osisek, Donald W. Schmidt, Jane H. Bartik, Lisa Cranton Heller, Patrick M. West, Jr., Phil C. Yeh
Принадлежит: International Business Machines Corp

A measurement sampling facility takes snapshots of the central processing unit (CPU) on which it is executing at specified sampling intervals to collect data relating to tasks executing on the CPU. The collected data is stored in a buffer, and at selected times, an interrupt is provided to remove data from the buffer to enable reuse thereof. The interrupt is not taken after each sample, but in sufficient time to remove the data and minimize data loss.

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Номер записи: 63
19-04-2012 дата публикации

Cache memory device, cache memory control method, program and integrated circuit

Номер: US20120096213A1
Автор: Kazuomi Kato
Принадлежит: Panasonic Corp

To aim to provide a cache memory device that performs a line size determination process for determining a refill size, in advance of a refill process that is performed at cache miss time. According to the line size determination process, the number of reads/writes of a management target line that belongs to a set is acquired (S 51 ), and in the case where the numbers of reads completely match one another and the numbers of writes completely match one another (S 52 : Yes), the refill size is determined to be large (S 54 ). Otherwise (S 52 : No), the refill size is determined to be small (S 55 ).

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Номер записи: 64
19-04-2012 дата публикации

System and Method for the Synchronization of a File in a Cache

Номер: US20120096228A1
Автор: David Thomas, Scott Wells
Принадлежит: Individual

The present invention provides a system and method for bi-directional synchronization of a cache. One embodiment of the system of this invention includes a software program stored on a computer readable medium. The software program can be executed by a computer processor to receive a database asset from a database; store the database asset as a cached file in a cache; determine if the cached file has been modified; and if the cached file has been modified, communicate the cached file directly to the database. The software program can poll a cached file to determine if the cached file has changed. Thus, bi-directional synchronization can occur.

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Номер записи: 65
19-04-2012 дата публикации

Data processing method and semiconductor integrated circuit

Номер: US20120096335A1
Автор: Nobuhiro Tsuboi, Tomohisa Sezaki, Tsukasa Takahashi, Yoshiteru Mino
Принадлежит: Panasonic Corp

A read process is performed on an ith designated block storing an ith divided data string. If the ith divided data string is not normally read, the read process is sequentially executed on ith ordinary blocks each storing the ith divided data string, where the ith ordinary blocks are included in ordinary block groups, respectively. When the ith divided data string is normally read, it is determined whether or not reading p divided data strings has been completed. If it is determined that the reading the p divided data strings has not been completed, the read process is performed on an (i+1)th designated block storing an (i+1)th divided data string following the ith divided data string.

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Номер записи: 66
26-04-2012 дата публикации

Multiplexing Users and Enabling Virtualization on a Hybrid System

Номер: US20120102138A1
Автор: Carl Joseph Parris, Rajaram B. Krishnamurthy, Yuk Lung Chan
Принадлежит: International Business Machines Corp

A method, hybrid server system, and computer program product, support multiple users in an out-of-core processing environment. At least one accelerator system in a plurality of accelerator systems is partitioned into a plurality of virtualized accelerator systems. A private client cache is configured on each virtualized accelerator system in the plurality of virtualized accelerator systems. The private client cache of each virtualized accelerator system stores data that is one of accessible by only the private client cache and accessible by other private client caches associated with a common data set. Each user in a plurality of users is assigned to a virtualized accelerator system from the plurality of virtualized accelerator systems.

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Номер записи: 67
26-04-2012 дата публикации

Allocation of an Operating Address to a Bus-Compatible Operating Device for Luminous Means

Номер: US20120102235A1
Автор: Andre Mitterbacher, Markus Kuenzli, Patrick Zueger, Reinhard Boeckle, Reto Sprenger, Roger Kistler
Принадлежит: Tridonic GmbH and Co KG

The invention relates to a method for allocating an operating address to an operating device for luminous means, in which the operating address is transmitted to the operating device in digitally coded form via an interface which is configured to connect a light sensor. The operating address is allocated by a user using a handheld device to transmit optical digital signals to a light sensor or infrared sensor which is connected to the interface.

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Номер записи: 68
26-04-2012 дата публикации

Serial attached small computer system interface (sas) domain access through a universal serial bus interface of a data processing device

Номер: US20120102251A1
Автор: Gooty Bharat Kumar Reddy, Shashi Ranjan
Принадлежит: LSI Corp

A method, an apparatus and/or a system of serial attached small computer system interface (SAS) domain access through a universal serial bus (USB) interface of a data processing device. A method includes communicatively coupling a serial attached small computer system interface (SAS) domain to the data processing device through the universal serial bus (USB) interface of the data processing device via an expander device. The method also includes accessing a SAS device of the SAS domain and/or the SAS domain through the USB interface of the data processing device via the expander device. The method further includes bridging through a firmware of the expander device between a USB command of the data processing device and a SAS command of the SAS domain to communicate between the data processing device and the SAS domain.

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Номер записи: 69
03-05-2012 дата публикации

Image-based barcode reader

Номер: US20120104100A1
Автор: Orazio Gallo, Roberto Manduchi
Принадлежит: University of California Santa Cruz

Barcode decoding bypassing binarization is provided which relies on deformable templates to makes use of all the gray level information of each pixel in the barcode image. Parameterization of the deformable templates allow for efficiently performing maximum likelihood estimation independently on each barcode digit and enforcing spatial coherence across the barcode digits.

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Номер записи: 70
03-05-2012 дата публикации

System and method for a scanning api

Номер: US20120110174A1
Автор: Bruce Wootton, Kevin Patrick Mahaffey, Timothy Micheal Wyatt
Принадлежит: LookOut Inc

Application programs for mobile communication devices are stored in a data store. The applications may be collected from any number of different sources such as through an application programming interface (API), from web crawling, from users, or combinations of these. The applications are analyzed and the analysis results reported. The applications may be “continuously” analyzed so that any changes in assessments can be reported. If an application for which an analysis is sought is not in the data store, information about a different, but related application may be provided.

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Номер записи: 71
03-05-2012 дата публикации

Tiered data storage system with data management and method of operation thereof

Номер: US20120110259A1
Автор: Andrew Mills, Marshall Lee
Принадлежит: ENMOTUS Inc

A method of operation of a data storage system includes: enabling a system interface for receiving host commands; updating a mapping register for monitoring transaction records of a logical block address for the host commands including translating a host virtual block address to a physical address for storage devices; accessing by a storage processor, the mapping register for comparing the transaction records with a tiering policies register; and enabling a tiered storage engine for transferring host data blocks by the system interface and concurrently transferring between a tier zero, a tier one, or a tier two if the storage processor determines the transaction records exceed the tiering policies register.

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Номер записи: 72
10-05-2012 дата публикации

System And Method For Processing Multimedia Messaging Service

Номер: US20120115516A1
Автор: Hengsheng Zhang
Принадлежит: ZTE Corp

The disclosure disclosed a system and method for processing a Multimedia Messaging Service (MMS). The system comprises: a first and second storage units for storing MMS data, a first control unit for controlling the storage of received MMS data outside the system into the first storage unit and data acquisition from the first storage unit, and a second control unit for controlling the writing of the MMS data stored in the first storage unit into the second storage unit according to performance of the second storage unit. The disclosure improves the processing performance of a Multimedia Messaging Service Center (MMSC) system, lowers the construction cost of an MMS server of the MMSC system, and guarantees the stable running of the MMSC system.

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Номер записи: 73
10-05-2012 дата публикации

Hybrid Server with Heterogeneous Memory

Номер: US20120117312A1
Автор: Carl Joseph Parris, Rajaram B. Krishnamurthy, Yuk Lung Chan
Принадлежит: International Business Machines Corp

A method, hybrid server system, and computer program product, for managing access to data stored on the hybrid server system. A memory system residing at a server is partitioned into a first set of memory managed by the server and a second set of memory managed by a set of accelerator systems. The set of accelerator systems are communicatively coupled to the server. The memory system comprises heterogeneous memory types. A data set stored within at least one of the first set of memory and the second set of memory that is associated with at least one accelerator system in the set of accelerator systems is identified. The data set is transformed from a first format to a second format, wherein the second format is a format required by the at least one accelerator system.

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Номер записи: 74
10-05-2012 дата публикации

Invalidating a Range of Two ro More Translation Table Entries and Instruction Therefore

Номер: US20120117356A1
Автор: Erwin F. Pfeffer, Kenneth E. Plambeck, Lisa C. Heller, Timothy J. Slegel
Принадлежит: International Business Machines Corp

An instruction is provided to perform invalidation of an instruction specified range of segment table entries or region table entries. The instruction can be implemented by software emulation, hardware, firmware or some combination thereof.

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Номер записи: 75
17-05-2012 дата публикации

Hybrid storage device and electronic system using the same

Номер: US20120124266A1
Автор: Byung-Hoon Chung, Jae-won You, Kyu-yeol Park, Tae-yung Kim
Принадлежит: SAMSUNG ELECTRONICS CO LTD

A hybrid storage device is provided. The hybrid storage device includes a first storage part that comprises an interface device based on a first standard, a second storage part that comprises an interface device based on a second standard, and a connector for interface devices that is shared by the first storage part and the second storage part and comprises a plurality of pins.

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Номер записи: 76
17-05-2012 дата публикации

Location of Memory Management Translations in an Emulated Processor

Номер: US20120124271A1
Автор: Matthew L. Evans
Принадлежит: International Business Machines Corp

A method and system for location of memory management translations in an emulated processor. The method includes: detecting a page miss of a process on an emulated processor, wherein the emulated processor software refills a translation lookaside buffer (TLB); locating a secondary data structure in memory; fetching a missing translation from a secondary data structure in memory; and inserting the missing translation in a guest translation lookaside buffer; wherein the steps are carried out in a trap handler in the emulated environment. The steps may be carried out in the emulated processor or in a host server of the emulated processor instead of invoking a guest operating system trap handler.

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Номер записи: 77
24-05-2012 дата публикации

Memory instruction including parameter to affect operating condition of memory

Номер: US20120127807A1
Автор: Federico Pio
Принадлежит: Micron Technology Inc

Subject matter disclosed herein relates to techniques to operate memory.

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Номер записи: 78
24-05-2012 дата публикации

Real-time detection system and the method thereof

Номер: US20120130682A1
Автор: Fuh-Yu Chang, Jia Wang
Принадлежит: National Taiwan University of Science and Technology NTUST

The invention discloses a real-time detection system for detecting the real-time machining by a rotating machine or rotating quality of a rotating machine. The real-time detection system of the invention comprises a signal capture module, a preprocessor, a processor and a comparison module. The signal capture module is used to capture a time-sequence signal of the rotating machine. The preprocessor is coupled to the signal capture module for receiving the time-sequence signal and generating a stationary time-sequence signal by a Fourier Transform. The processor is coupled to the preprocessor for receiving the stationary time-sequence signal and calculating a plurality of entropy of the stationary time-sequence signal by a predetermined way. The comparison module with an entropy table or a feature judgment mechanism of the entropy variation is coupled to the processor for receiving the plurality of entropy and comparing the plurality of entropy according to the entropy table or the feature judgment of the entropy variation and generating a quality signal.

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Номер записи: 79
24-05-2012 дата публикации

Fstp expert system

Номер: US20120131055A1
Автор: Sigram Schindler
Принадлежит: Sigram Schindler Beteiligungs GmbH

Be TT.p the “technique teaching” of a patent or venture, RS a “reference set” of prior art “technique teachings TT.i”, any “element” of any TT described by its properties, and all this information be presented as meaningful items. Then the FSTP Expert System supports managing an analysis of TT.p over RS such that it is able to reply automatically and instantly to any query for any item in this information. These answers may describe any interrelation between any items or properties/facts or comment on such interrelations or on some insights into them achieved while generating these items by or interactively with the FSTP Expert System. By formalization of these properties it also supports determining the value of q dependably indicating TT.p as trivial/obvious over RS iff q=0 and for q>0 showing the “creative height of TT.p over RS” and quantifying the “power” of this indication.

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Номер записи: 80
24-05-2012 дата публикации

Signal processing system, integrated circuit comprising buffer control logic and method therefor

Номер: US20120131241A1
Автор: Alistair Robertson, Joseph Circello, Mark Maiolani
Принадлежит: FREESCALE SEMICONDUCTOR INC

A signal processing system comprising buffer control logic arranged to allocate a plurality of buffers for the storage of information fetched from at least one memory element. Upon receipt of fetched information to be buffered, the buffer control logic is arranged to categorise the information to be buffered according to at least one of: a first category associated with sequential flow and a second category associated with change of flow, and to prioritise respective buffers from the plurality of buffers storing information relating to the first category associated with sequential flow ahead of buffers storing information relating to the second category associated with change of flow when allocating a buffer for the storage of the fetched information to be buffered.

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Номер записи: 81
24-05-2012 дата публикации

Data archiving using data compression of a flash copy

Номер: US20120131293A1
Автор: Alfred Emilio Sanchez, Lokesh Mohan Gupta, Michael Thomas Benhase, Yu-Cheng Hsu
Принадлежит: International Business Machines Corp

Embodiments of the disclosure relate to archiving data in a storage system. An exemplary embodiment comprises making a flash copy of data in a source volume, compressing data in the flash copy wherein each track of data is compressed into a set of data pages, and storing the compressed data pages in a target volume. Data extents for the target volume may be allocated from a pool of compressed data extents. After each stride worth of data is compressed and stored in the target volume, data may be destaged to avoid destage penalties. Data from the target volume may be decompressed from a flash copy of the target volume in a reverse process to restore each data track, when the archived data is needed. Data may be compressed and uncompressed using a Lempel-Ziv-Welch process.

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Номер записи: 82
24-05-2012 дата публикации

Correlation-based instruction prefetching

Номер: US20120131311A1
Автор: Yuan C. Chou
Принадлежит: Oracle International Corp

The disclosed embodiments provide a system that facilitates prefetching an instruction cache line in a processor. During execution of the processor, the system performs a current instruction cache access which is directed to a current cache line. If the current instruction cache access causes a cache miss or is a first demand fetch for a previously prefetched cache line, the system determines whether the current instruction cache access is discontinuous with a preceding instruction cache access. If so, the system completes the current instruction cache access by performing a cache access to service the cache miss or the first demand fetch, and also prefetching a predicted cache line associated with a discontinuous instruction cache access which is predicted to follow the current instruction cache access.

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Номер записи: 83
24-05-2012 дата публикации

Memory controller and information processing system

Номер: US20120131382A1
Автор: Masanori Higeta
Принадлежит: Fujitsu Ltd

A information processing system comprises a memory module having a plurality of unit memory regions, a memory controller, connected to the memory module via memory interface, configured to control access to the memory module, an error detector, which is in the memory controller, configured to perform an error detection on data read from the memory module, a failure inspection controller configured to switch a mode of the memory controller from a normal mode to a failure inspection mode, read data from an address, where data was written, to be inspected for each of the plurality of unit memory regions, causes the error detector to detect an error in the read data and perform a failure inspection and a determining unit configured to determine a memory failure or a transmission path failure on the basis of the state of the error detected from the unit memory regions.

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Номер записи: 84
24-05-2012 дата публикации

Method and system for protecting against multiple failures in a raid system

Номер: US20120131383A1
Автор: Choon-Seng Tan, Greg J. Pellegrino, Ryan A. Callison, William C. Galloway
Принадлежит: Pivot3 Inc

Embodiments of methods of protecting RAID systems from multiple failures and such protected RAID systems are disclosed. More particularly, in certain embodiments of a distributed RAID system each data bank has a set of associated storage media and executes a similar distributed RAID application. The distributed RAID applications on each of the data banks coordinate among themselves to distribute and control data flow associated with implementing a level of RAID in conjunction with data stored on the associated storage media of the data banks. Furthermore, one or more levels of RAID may be implemented within one or more of the data banks comprising the distributed RAID system.

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Номер записи: 85
31-05-2012 дата публикации

Semiconductor device and method of controlling the same

Номер: US20120134222A1
Автор: Hiroki Fujisawa, Kazuhisa Ureshino
Принадлежит: Elpida Memory Inc

A semiconductor device includes a data input/output circuit connected to the memory cell array via a sense circuit, and an access control circuit that controls access to the memory cell array. The access control circuit includes: a first signal unit outputting a first signal for activating or inactivating a word line; a second signal unit outputting a second signal for activating or inactivating a bit line and the sense circuit; a third signal unit outputting a third signal for starting or stopping a supply of an overdrive voltage to the sense circuit; and a fourth signal unit outputting a fourth signal for inactivating the word line. The period during which the third signal remains activated is determined in accordance with the magnitude of an external voltage. In the fourth signal unit, the timing to generate the fourth signal is determined independently of the magnitude of the external voltage.

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Номер записи: 86
31-05-2012 дата публикации

Method of pattern recognition in a signal

Номер: US20120136813A1
Автор: Dmitry Grigoryev, Julien Caroux
Принадлежит: Goodyear Tire and Rubber Co

The invention is directed to a method for pattern recognition in a signal corresponding for example to the steering angle of a vehicle for testing tires. The method comprises three major steps, namely step a) consisting in identifying phases in the signal by detecting phase changes; step b) consisting in classifying at least some of the identified phases based on their shapes and step c) consisting in detecting the presence of predetermined patterns in the signal where each predetermined pattern corresponds to a specific sequence of classes of phases. The phase changes are determined by extrema of the signal and its first derivative. The classification of the phase is made by means of parameters of the phases, namely the length dL, the amplitude dH, and a form factor S. The definition of the different classes is adjusted in a parameter space by means of manual recognition of maneuvers.

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Номер записи: 87
31-05-2012 дата публикации

Method and apparatus for selectively performing explicit and implicit data line reads

Номер: US20120136857A1
Автор: Greggory D. Donley
Принадлежит: Advanced Micro Devices Inc

A method and apparatus are described for selectively performing explicit and implicit data line reads. When a data line request is received, a determination is made as to whether there are currently sufficient data resources to perform an implicit data line read. If there are not currently sufficient data resources to perform an implicit data line read, a time period (number of clock cycles) before sufficient data resources will become available to perform an implicit data line read is estimated. A determination is then made as to whether the estimated time period exceeds a threshold. An explicit tag request is generated if the estimated time period exceeds the threshold. If the estimated time period does not exceed the threshold, the generation of a tag request is delayed until sufficient data resources become available. An implicit tag request is then generated.

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Номер записи: 88
31-05-2012 дата публикации

Method and System for Initializing Storage in a Storage System

Номер: US20120137069A1
Автор: Choon-Seng Tan, George J. Scholhamer, III, Greg J. Pellegrino, Ryan A. Callison, William C. Galloway
Принадлежит: Pivot3 Inc

Embodiments of systems and methods for a high availability storage system are disclosed. More particularly, in certain embodiments desired locations of storage devices may be zeroed out during operation of the storage system and areas that have been zeroed out allocated to store data when commands pertaining to that data are received. Specifically, in one embodiment a distributed RAID system comprising a set of data banks may be provided where each data bank in the set of data banks may execute a background process which zeroes areas of the storage devices of the data bank. When a command pertaining to a logical location is received a zeroed area of the physical storage devices on the data bank may be allocated to store data associated with that logical location.

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Номер записи: 89
07-06-2012 дата публикации

Memory address re-mapping of graphics data

Номер: US20120139927A1
Автор: Aditya Navale, Balaji Vembu, Wishwesh A. Gandhi
Принадлежит: Individual

A method and apparatus for creating, updating, and using guest physical address (GPA) to host physical address (HPA) shadow translation tables for translating GPAs of graphics data direct memory access (DMA) requests of a computing environment implementing a virtual machine monitor to support virtual machines. The requests may be sent through a render or display path of the computing environment from one or more virtual machines, transparently with respect to the virtual machine monitor. The creating, updating, and using may be performed by a memory controller detecting entries sent to existing global and page directory tables, forking off shadow table entries from the detected entries, and translating GPAs to HPAs for the shadow table entries.

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Номер записи: 90
07-06-2012 дата публикации

Methods and apparatus for automated true object-based image analysis and retrieval

Номер: US20120140990A1
Автор: Jamie E. Retterath, Robert A. Laumeyer
Принадлежит: Google LLC

An automated and extensible system for analysis and retrieval of images based on region-of-interest (ROI) analysis of one or more true objects depicted by an image is provided. The system uses an database that is a relational or analytical database containing searchable vectors that represent the images stored in a repository. Entries in the database are created by an image locator and ROI classifier working together to locate images within the repository and extract relevant information to be stored in the ROI database. The ROI classifier analyzes objects in an image to arrive at actual features of the true object. Graphical searches are performed by the collaborative workings of an image retrieval module, an image search requestor and an ROI query module. The image search requestor is an abstraction layer that translates user or agent search requests into the language understood by the ROI query.

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Номер записи: 91
07-06-2012 дата публикации

Dynamic adjustment of read/write ratio of a disk cache

Номер: US20120144109A1
Автор: Brian M. Rogers, Ganesh Balakrishnan, Gordon B. Bell, MVV Anil Krishna, Timothy H. Heil
Принадлежит: International Business Machines Corp

Embodiments of the invention are directed to optimizing the performance of a split disk cache. In one embodiment, a disk cache includes a primary region having a read portion and write portion and one or more smaller, sample regions also including a read portion and a write portion. The primary region and one or more sample region each have an independently adjustable ratio of a read portion to a write portion. Cached reads are distributed among the read portions of the primary and sample region, while cached writes are distributed among the write portions of the primary and sample region. The performance of the primary region and the performance of the sample region are tracked, such as by obtaining a hit rate for each region during a predefined interval. The read/write ratio of the primary region is then selectively adjusted according to the performance of the one or more sample regions.

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Номер записи: 92
07-06-2012 дата публикации

Recommendation based caching of content items

Номер: US20120144117A1
Автор: Christopher B. Weare, Eric N. Lockard
Принадлежит: Microsoft Corp

Content item recommendations are generated for users based on metadata associated with the content items and a history of content item usage associated with the users. Each content item recommendation identifies a user and a content item and includes a score that indicates how likely the user is to view the content item. Based on the content item recommendations, and constraints of one or more caches, the content items are selected for storage in one or more caches. The constraints may include users that are associated with each cache, the geographical location of each cache, the size of each cache, and/or costs associated with each cache such as bandwidth costs. The content items stored in a cache are recommended to users associated with the cache.

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Номер записи: 93
07-06-2012 дата публикации

Read-ahead processing in networked client-server architecture

Номер: US20120144123A1
Автор: Konstantin Mushkin, Lior Aronovich, Oded SONIN
Принадлежит: International Business Machines Corp

Various embodiments for read-ahead processing in a networked client-server architecture by a processor device are provided. Read messages are grouped by a plurality of unique sequence identifications (IDs), where each of the sequence IDs corresponds to a specific read sequence, consisting of all read and read-ahead requests related to a specific storage segment that is being read sequentially by a thread of execution in a client application. The storage system uses the sequence id value in order to identify and filter read-ahead messages that are obsolete when received by the storage system, as the client application has already moved to read a different storage segment. Basically, a message is discarded when its sequence id value is less recent than the most recent value already seen by the storage system. The sequence IDs are used by the storage system to determine corresponding read-ahead data to be loaded into a read-ahead cache.

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Номер записи: 94
07-06-2012 дата публикации

Custom atomics using an off-chip special purpose processor

Номер: US20120144128A1
Автор: Benjamin C. Serebrin, Stephen D. Glaser
Принадлежит: Advanced Micro Devices Inc

An apparatus for executing an atomic memory transaction comprises a processing core in a multi-processing core system, where the processing core is configured to store an atomic program in a cache line. The apparatus further comprises an atomic program execution unit that is configured to execute the atomic program as a single atomic memory transaction with a guarantee of forward progress.

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Номер записи: 95
07-06-2012 дата публикации

Usb hub and power management method thereof

Номер: US20120144213A1
Автор: Chen-Chao Chang, Chih-Chiang Chang, Ling-Sheng Yang
Принадлежит: WISTRON NEWEB CORP

A USB HUB is provided. The USB HUB comprises a wireless communication module, a storage module, a USB interface connected to a host outside of the USB HUB and a HUB controller. The storage module stores a driver program of the wireless communication module. The USB interface transfers data with the host. The HUB controller is coupled to the USB interface, the wireless communication module and the storage module. The HUB controller disables the storage module and enables the wireless communication module when the driver program has been installed in the host.

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Номер записи: 96
14-06-2012 дата публикации

Systems and methods for background destaging storage tracks

Номер: US20120151148A1
Автор: Binny S. Gill, Brent C. Beardsley, Lokesh M. Gupta, Michael T. Benhase, Sonny E. WILLIAMS
Принадлежит: International Business Machines Corp

Systems and methods for background destaging storage tracks from cache when one or more hosts are idle are provided. One system includes a write cache configured to store a plurality of storage tracks and configured to be coupled to one or more hosts, and a processor coupled to the write cache. The processor includes code that, when executed by the processor, causes the processor to perform the method below. One method includes monitoring the write cache for write operations from the host(s) and determining if the host(s) is/are idle based on monitoring the write cache for write operations from the host(s). The storage tracks are destaged from the write cache if the host(s) is/are idle and are not destaged from the write cache if one or more of the hosts is/are not idle. Also provided are physical computer storage mediums including a computer program product for performing the above method.

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Номер записи: 97
14-06-2012 дата публикации

Memory apparatus for collective volume memory and method for managing metadata thereof

Номер: US20120151175A1
Автор: Dong Jae Kang, Eun Ji Lim, Gyu II Cha, Sung In JUNG, Young Ho Kim
Принадлежит: Electronics and Telecommunications Research Institute ETRI

Disclosed are a memory apparatus for a collective volume memory and a method for managing metadata thereof. The memory apparatus for a collective volume memory includes a CVM (Collective Volume Memory) command tool configured to provide a command tool for CVM operation and translate a command input by a user to control the CVM operation; and a CVM engine configured to perform at least one of CVM configuration and initialization, and CVM allocation and access according to data transmitted from the CVM command tool.

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Номер записи: 98
14-06-2012 дата публикации

Memory stacks management

Номер: US20120151179A1
Автор: Mark Gaertner, Mark Heath
Принадлежит: SEAGATE TECHNOLOGY LLC

A method for managing a memory stack provides mapping a part of the memory stack to a span of fast memory and a part of the memory stack to a span of slow memory, wherein the fast memory provides access speed substantially higher than the access speed provided by the slow memory.

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Номер записи: 99
14-06-2012 дата публикации

Security usb storage medium generation and decryption method, and medium recorded with program for generating security usb storage medium

Номер: US20120151219A1
Автор: Daegull Ryu, Secheol Oh
Принадлежит: MW STORY CO Ltd

The present invention relates to a security USB storage medium generation and decryption method, and a medium having the record of a program for the generation of a security USB storage medium. The generation method of the present invention is for a USB host constituted by a USB connection port, an input interface, an output interface, a storage unit and a host control unit to code a USB storage medium constituted by a USB interface, a storage region and a USB control unit so as to generate a security USB storage medium, the method comprising the steps of: in the host control unit, outputting through the output interface information that requests for the input of a 1st user password to be set, when the connection of the USB interface to the USB connection port is detected; generating a random key and a disk key based on a 1st user password that is input from the input interface in response to the request for the input of the 1st user password; hashing the 1st user password and the random key after the random key and the disk key are generated, so as to generate a 1st encryption and decryption key; and generating a security volume header by dividing the storage region into a header and a body using the 1st encryption and decryption key, encrypting a 1st data and then storing the data in the header, and also generating a security volume body by encrypting a 2nd data using the disk key and then storing the data in the body. In this manner, no one is allowed to read the content stored in the USB storage medium through a disk dump for example without inputting a user password that was input during the generation of security volume, thereby increasing the security of the USB storage medium.

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Номер записи: 100