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Небесная энциклопедия

Космические корабли и станции, автоматические КА и методы их проектирования, бортовые комплексы управления, системы и средства жизнеобеспечения, особенности технологии производства ракетно-космических систем

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Мониторинг СМИ

Мониторинг СМИ и социальных сетей. Сканирование интернета, новостных сайтов, специализированных контентных площадок на базе мессенджеров. Гибкие настройки фильтров и первоначальных источников.

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Применить Всего найдено 14357. Отображено 100.
19-01-2012 дата публикации

Caching using virtual memory

Номер: US20120017039A1
Автор: Julien MARGETTS
Принадлежит: PLX Technology Inc

In a first embodiment of the present invention, a method for caching in a processor system having virtual memory is provided, the method comprising: monitoring slow memory in the processor system to determine frequently accessed pages; for a frequently accessed page in slow memory: copy the frequently accessed page from slow memory to a location in fast memory; and update virtual address page tables to reflect the location of the frequently accessed page in fast memory.

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Номер записи: 1
19-01-2012 дата публикации

Managing extended raid caches using counting bloom filters

Номер: US20120017041A1
Автор: Ross E. Zwisler
Принадлежит: LSI Corp

Contentual metadata of an extended cache is stored within the extended cache. The contentual metadata of the extended cache is approximated utilizing a counting Bloom filter. The counting Bloom filter is stored within a primary cache. Contentual metadata of the primary cache is stored within the primary cache. One of a data read or a data write is executed without accessing the contentual metadata of the extended cache stored within the extended cache.

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Номер записи: 2
15-03-2012 дата публикации

System and method of page buffer operation for memory devices

Номер: US20120066442A1
Автор: Hakjune Oh, Hong Beom Pyeon, Jin-Ki Kim
Принадлежит: Mosaid Technologies Inc

Systems and methods are provided for using page buffers of memory devices connected to a memory controller through a common bus. A page buffer of a memory device is used as a temporary cache for data which is written to the memory cells of the memory device. This can allow the memory controller to use memory devices as temporary caches so that the memory controller can free up space in its own memory.

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Номер записи: 3
29-03-2012 дата публикации

Hierarchical Memory Addressing

Номер: US20120075319A1
Автор: William James Dally
Принадлежит: Nvidia Corp

One embodiment of the present invention sets forth a technique for addressing data in a hierarchical graphics processing unit cluster. A hierarchical address is constructed based on the location of a storage circuit where a target unit of data resides. The hierarchical address comprises a level field indicating a hierarchical level for the unit of data and a node identifier that indicates which GPU within the GPU cluster currently stores the unit of data. The hierarchical address may further comprise one or more identifiers that indicate which storage circuit in a particular hierarchical level currently stores the unit of data. The hierarchical address is constructed and interpreted based on the level field. The technique advantageously enables programs executing within the GPU cluster to efficiently access data residing in other GPUs using the hierarchical address.

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Номер записи: 4
29-03-2012 дата публикации

Cache with Multiple Access Pipelines

Номер: US20120079204A1
Автор: Abhijeet Ashok Chachad, Jonathan (Son) Hung Tran, Raguram Damodaran, Sanjive Agarwala, Timothy David Anderson
Принадлежит: Texas Instruments Inc

Parallel pipelines are used to access a shared memory. The shared memory is accessed via a first pipeline by a processor to access cached data from the shared memory. The shared memory is accessed via a second pipeline by a memory access unit to access the shared memory. A first set of tags is maintained for use by the first pipeline to control access to the cache memory, while a second set of tags is maintained for use by the second pipeline to access the shared memory. Arbitrating for access to the cache memory for a transaction request in the first pipeline and for a transaction request in the second pipeline is performed after each pipeline has checked its respective set of tags.

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Номер записи: 5
19-04-2012 дата публикации

System and Method for the Synchronization of a File in a Cache

Номер: US20120096228A1
Автор: David Thomas, Scott Wells
Принадлежит: Individual

The present invention provides a system and method for bi-directional synchronization of a cache. One embodiment of the system of this invention includes a software program stored on a computer readable medium. The software program can be executed by a computer processor to receive a database asset from a database; store the database asset as a cached file in a cache; determine if the cached file has been modified; and if the cached file has been modified, communicate the cached file directly to the database. The software program can poll a cached file to determine if the cached file has changed. Thus, bi-directional synchronization can occur.

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Номер записи: 6
26-04-2012 дата публикации

Multiplexing Users and Enabling Virtualization on a Hybrid System

Номер: US20120102138A1
Автор: Carl Joseph Parris, Rajaram B. Krishnamurthy, Yuk Lung Chan
Принадлежит: International Business Machines Corp

A method, hybrid server system, and computer program product, support multiple users in an out-of-core processing environment. At least one accelerator system in a plurality of accelerator systems is partitioned into a plurality of virtualized accelerator systems. A private client cache is configured on each virtualized accelerator system in the plurality of virtualized accelerator systems. The private client cache of each virtualized accelerator system stores data that is one of accessible by only the private client cache and accessible by other private client caches associated with a common data set. Each user in a plurality of users is assigned to a virtualized accelerator system from the plurality of virtualized accelerator systems.

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Номер записи: 7
10-05-2012 дата публикации

Hybrid Server with Heterogeneous Memory

Номер: US20120117312A1
Автор: Carl Joseph Parris, Rajaram B. Krishnamurthy, Yuk Lung Chan
Принадлежит: International Business Machines Corp

A method, hybrid server system, and computer program product, for managing access to data stored on the hybrid server system. A memory system residing at a server is partitioned into a first set of memory managed by the server and a second set of memory managed by a set of accelerator systems. The set of accelerator systems are communicatively coupled to the server. The memory system comprises heterogeneous memory types. A data set stored within at least one of the first set of memory and the second set of memory that is associated with at least one accelerator system in the set of accelerator systems is identified. The data set is transformed from a first format to a second format, wherein the second format is a format required by the at least one accelerator system.

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Номер записи: 8
07-06-2012 дата публикации

Dynamic adjustment of read/write ratio of a disk cache

Номер: US20120144109A1
Автор: Brian M. Rogers, Ganesh Balakrishnan, Gordon B. Bell, MVV Anil Krishna, Timothy H. Heil
Принадлежит: International Business Machines Corp

Embodiments of the invention are directed to optimizing the performance of a split disk cache. In one embodiment, a disk cache includes a primary region having a read portion and write portion and one or more smaller, sample regions also including a read portion and a write portion. The primary region and one or more sample region each have an independently adjustable ratio of a read portion to a write portion. Cached reads are distributed among the read portions of the primary and sample region, while cached writes are distributed among the write portions of the primary and sample region. The performance of the primary region and the performance of the sample region are tracked, such as by obtaining a hit rate for each region during a predefined interval. The read/write ratio of the primary region is then selectively adjusted according to the performance of the one or more sample regions.

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Номер записи: 9
07-06-2012 дата публикации

Recommendation based caching of content items

Номер: US20120144117A1
Автор: Christopher B. Weare, Eric N. Lockard
Принадлежит: Microsoft Corp

Content item recommendations are generated for users based on metadata associated with the content items and a history of content item usage associated with the users. Each content item recommendation identifies a user and a content item and includes a score that indicates how likely the user is to view the content item. Based on the content item recommendations, and constraints of one or more caches, the content items are selected for storage in one or more caches. The constraints may include users that are associated with each cache, the geographical location of each cache, the size of each cache, and/or costs associated with each cache such as bandwidth costs. The content items stored in a cache are recommended to users associated with the cache.

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Номер записи: 10
14-06-2012 дата публикации

Systems and methods for background destaging storage tracks

Номер: US20120151148A1
Автор: Binny S. Gill, Brent C. Beardsley, Lokesh M. Gupta, Michael T. Benhase, Sonny E. WILLIAMS
Принадлежит: International Business Machines Corp

Systems and methods for background destaging storage tracks from cache when one or more hosts are idle are provided. One system includes a write cache configured to store a plurality of storage tracks and configured to be coupled to one or more hosts, and a processor coupled to the write cache. The processor includes code that, when executed by the processor, causes the processor to perform the method below. One method includes monitoring the write cache for write operations from the host(s) and determining if the host(s) is/are idle based on monitoring the write cache for write operations from the host(s). The storage tracks are destaged from the write cache if the host(s) is/are idle and are not destaged from the write cache if one or more of the hosts is/are not idle. Also provided are physical computer storage mediums including a computer program product for performing the above method.

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Номер записи: 11
14-06-2012 дата публикации

Memory apparatus for collective volume memory and method for managing metadata thereof

Номер: US20120151175A1
Автор: Dong Jae Kang, Eun Ji Lim, Gyu II Cha, Sung In JUNG, Young Ho Kim
Принадлежит: Electronics and Telecommunications Research Institute ETRI

Disclosed are a memory apparatus for a collective volume memory and a method for managing metadata thereof. The memory apparatus for a collective volume memory includes a CVM (Collective Volume Memory) command tool configured to provide a command tool for CVM operation and translate a command input by a user to control the CVM operation; and a CVM engine configured to perform at least one of CVM configuration and initialization, and CVM allocation and access according to data transmitted from the CVM command tool.

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Номер записи: 12
14-06-2012 дата публикации

System and method for maintaining a data redundancy scheme in a solid state memory in the event of a power loss

Номер: US20120151253A1
Автор: Robert L. Horn
Принадлежит: Western Digital Technologies Inc

Embodiments of the invention are directed to systems and methods for reducing an amount of backup power needed to provide power fail safe preservation of a data redundancy scheme such as RAID that is implemented in solid state storage devices where new write data is accumulated and written along with parity data. Because new write data cannot be guaranteed to arrive in integer multiples of stripe size, a full stripe's worth of new write data may not exist when power is lost. Various embodiments use truncated RAID stripes (fewer storage elements per stripe) to save cached write data when a power failure occurs. This approach allows the system to maintain RAID parity data protection in a power fail cache flush case even though a full stripe of write data may not exist, thereby reducing the amount of backup power needed to maintain parity protection in the event of power loss.

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Номер записи: 13
21-06-2012 дата публикации

System and method for handling io to drives in a raid system

Номер: US20120159067A1
Автор: Allen Kelton, Michael Richmond
Принадлежит: LSI Corp

A system and method for handling IO to drives in a RAID system is described. In one embodiment, the method includes providing a multiple disk system with a predefined strip size. IO request with a logical block address is received for execution on the multiple disk system. A plurality of sub-IO requests with a sub-strip size is generated, where the sub-strip size is smaller than the strip size. The generated sub-IO commands are executed on the multiple disk system. In one embodiment, a cache line size substantially equal to the sub-strip size is assigned to process the IO request.

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Номер записи: 14
12-07-2012 дата публикации

Global instructions for spiral cache management

Номер: US20120179872A1
Автор: Volker Strumpen
Принадлежит: International Business Machines Corp

A method of operation of a pipelined cache memory supports global operations within the cache. The cache may be a spiral cache, with a move-to-front M2F network for moving values from a backing store to a front-most tile coupled to a processor or lower-order level of a memory hierarchy and a spiral push-back network for pushing out modified values to the backing-store. The cache controller manages application of global commands by propagating individual commands to the tiles. The global commands may provide zeroing, flushing and reconciling of the given tiles. Commands for interrupting and resuming interrupted global commands may be implemented, to reduce halting or slowing of processing while other global operations are in process. A line detector within each tile supports reconcile and flush operations, and a line patcher in the controller provides for initializing address ranges with no processor intervention.

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Номер записи: 15
19-07-2012 дата публикации

Method and system for cache endurance management

Номер: US20120185638A1
Автор: Daniel Schreiber, Judah Gamliel Hahn, Robert K. KHEDOURI
Принадлежит: Sandisk IL Ltd

A system and method for cache endurance management is disclosed. The method may include the steps of querying a storage device with a host to acquire information relevant to a predicted remaining lifetime of the storage device, determining a download policy modification for the host in view of the predicted remaining lifetime of the storage device and updating the download policy database of a download manager in accordance with the determined download policy modification.

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Номер записи: 16
26-07-2012 дата публикации

Method and apparatus for memory management

Номер: US20120191901A1
Автор: John Peter Norair
Принадлежит: Blackbird Technology Holdings Inc

One or more circuits of a device may comprise a memory. A first portion of a first block of the memory may store program code and/or program data, a second portion of the first block may store an index associated with a second block of the memory, and a third portion of the first block may store an indication of a write status of the first portion. Each bit of the third portion of the first block may indicate whether an attempt to write data to a corresponding one or more words of the first portion of the first block has failed since the last erase of the corresponding one or more words of the first portion of the first block. Whether data to be written to a particular virtual address is written to the first block or the second block may depend on the write status of the first block and the second block.

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Номер записи: 17
26-07-2012 дата публикации

One-Die Flotox-Based Combo Non-Volatile Memory

Номер: US20120191902A1
Автор: Fu-Chang Hsu, Peter Wung Lee
Принадлежит: Aplus Flash Technology Inc

A memory access apparatus that controls access to at least one memory array has an array of programmable comparison cells that retain a programmed pass code and compare it with an access pass code. When there is a match between the access pass code and the programmed pass code, the memory access apparatus generates a match signal for allowing access to the at least one memory array. If there is no match, the data within the at least one memory array may be corrupted or destroyed. Each nonvolatile comparison cell has a pair of series connected charge retaining transistors. The programmed pass code is stored in the charge retaining transistors. Primary and complementary query pass codes are applied to the charge retaining transistors and are logically compared with the stored pass code and based on the programmed threshold voltage levels determine if the query pass code is correct.

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Номер записи: 18
26-07-2012 дата публикации

Managing Access to a Cache Memory

Номер: US20120191917A1
Автор: Subhendu Das, Xiao Jun Dai, ZHANG Yue, Zhi Gan
Принадлежит: International Business Machines Corp

Managing access to a cache memory includes dividing said cache memory into multiple of cache areas, each cache area having multiple entries; and providing at least one separate lock attribute for each cache area such that only a processor thread having possession of the lock attribute corresponding to a particular cache area can update that cache area.

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Номер записи: 19
26-07-2012 дата публикации

Semiconductor device

Номер: US20120192282A1
Автор: Hiroki Wakamatsu, Hiroko Suyama, Kenichiro Shibata
Принадлежит: Fujitsu Semiconductor Ltd

A semiconductor device includes a nonvolatile memory, and an interface configured to transfer data to and from the nonvolatile memory. The interface includes a security logic unit which controls a security level for the data written to the nonvolatile memory, in accordance with a plurality of preset security codes and a lock code that is written to a specific area in the nonvolatile memory.

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Номер записи: 20
02-08-2012 дата публикации

Memory Attribute Sharing Between Differing Cache Levels of Multilevel Cache

Номер: US20120198166A1
Автор: Joseph Raymond Michael Zbiciak, Naveen Bhoria, Raguram Damodaran
Принадлежит: Texas Instruments Inc

The level one memory controller maintains a local copy of the cacheability bit of each memory attribute register. The level two memory controller is the initiator of all configuration read/write requests from the CPU. Whenever a configuration write is made to a memory attribute register, the level one memory controller updates its local copy of the memory attribute register.

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Номер записи: 21
30-08-2012 дата публикации

Universal cache management system

Номер: US20120221768A1
Автор: Prasad V. Bagal, Rich Long
Принадлежит: Oracle International Corp

Techniques for universal cache management are described. In an example embodiment, a plurality of caches are allocated, in volatile memory of a computing device, to a plurality of data-processing instances, where each one of the plurality of caches is exclusively allocated to a separate one of the plurality of data-processing instances. A common cache is allocated in the volatile memory of the computing device, where the common cache is shared by the plurality of data-processing instances. Each instance of the plurality of data-processing instances is configured to: indentify a data block in the particular cache allocated to that instance, where the data block has not been changed since the data block was last persistently written to one or more storage devices; cause the data block to be stored in the common cache; and remove the data block from the particular cache. Data blocks in the common cache are maintained without being persistently written to the one or more storage devices.

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Номер записи: 22
20-09-2012 дата публикации

Flash storage device with read disturb mitigation

Номер: US20120239990A1
Автор: Mark Moshayedi, Po-Jen Hsueh, Richard A. Mataya
Принадлежит: Stec Inc

A method for managing a flash storage device includes initiating a read request and reading requested data from a first storage block of a plurality of storage blocks in the flash storage device based on the read request. The method further includes incrementing a read count for the first storage block and moving the data in the first storage block to an available storage block of the plurality of storage blocks when the read count reaches a first threshold value.

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Номер записи: 23
27-09-2012 дата публикации

Register file segments for supporting code block execution by using virtual cores instantiated by partitionable engines

Номер: US20120246450A1
Автор: Mohammad Abdallah
Принадлежит: Soft Machines Inc

A system for executing instructions using a plurality of register file segments for a processor. The system includes a global front end scheduler for receiving an incoming instruction sequence, wherein the global front end scheduler partitions the incoming instruction sequence into a plurality of code blocks of instructions and generates a plurality of inheritance vectors describing interdependencies between instructions of the code blocks. The system further includes a plurality of virtual cores of the processor coupled to receive code blocks allocated by the global front end scheduler, wherein each virtual core comprises a respective subset of resources of a plurality of partitionable engines, wherein the code blocks are executed by using the partitionable engines in accordance with a virtual core mode and in accordance with the respective inheritance vectors. A plurality register file segments are coupled to the partitionable engines for providing data storage.

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Номер записи: 24
04-10-2012 дата публикации

Numa-aware garbage collection

Номер: US20120254266A1
Автор: Antonios Printezis, Igor Veresov, John Coomes, Paul Henry Hohensee
Принадлежит: Oracle International Corp

Methods and systems for garbage collection are described. In some embodiments, Garbage collector threads may maximize local accesses and minimize remote access by copying Young objects and Old objects differently. When copying a Young object, a garbage collector thread may determine the lgroup of the pool that contains the object and copy the object to a pool of the same lgroup. The garbage collector thread may spread Old objects among lgroups by copying Old objects to pools of the same lgroup as the respective garbage collector thread. Additional methods and systems are disclosed.

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Номер записи: 25
04-10-2012 дата публикации

Method for giving read commands and reading data, and controller and storage system using the same

Номер: US20120254522A1
Автор: Chih-Kang Yeh
Принадлежит: Phison Electronics Corp

A method for giving a read command to a flash memory chip to read data to be accessed by a host system is provided. The method includes receiving a host read command; determining whether the received host read command follows a last host read command; if yes, giving a cache read command to read data from the flash memory chip; and if no, giving a general read command and the cache read command to read data from the flash memory chip. Accordingly, the method can effectively reduce time needed for executing the host read commands by using the cache read command to combine the host read commands which access continuous physical addresses and pre-read data stored in a next physical address.

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Номер записи: 26
01-11-2012 дата публикации

Memory device capable of preventing specific data from being erased

Номер: US20120278536A1
Автор: Hideo Aizawa, Takeaki Kato
Принадлежит: Individual

According to one embodiment, a memory device includes a nonvolatile semiconductor memory, and control section. The nonvolatile semiconductor memory includes a first memory area, and second memory area other than the first memory area. The control section receives a first command from a host, and permits use of the second memory area on the basis of the first command. The control section receives a second command from the host, and transmits a parameter indicating the capacity of the first memory area to the host on the basis of the second command. The control section further receives a third command from the host, and accesses the first memory area on the basis of the third command. When use of the second memory area is permitted, the control section receives the third command from the host, and accesses the second memory area on the basis of the third command.

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Номер записи: 27
15-11-2012 дата публикации

Managing Bandwidth Allocation in a Processing Node Using Distributed Arbitration

Номер: US20120290756A1
Автор: Abhijeet Ashok Chachad, David Quintin Bell, Dheera Balasubramanian, Raguram Damodaran, Roger Kyle Castille
Принадлежит: Texas Instruments Inc

Management of access to shared resources within a system comprising a plurality of requesters and a plurality of target resources is provided. A separate arbitration point is associated with each target resource. An access priority value is assigned to each requester. An arbitration contest is performed for access to a first target resource by requests from two or more of the requesters using a first arbitration point associated with the first target resource to determine a winning requester. The request from the winning requester is forwarded to a second target resource. A second arbitration contest is performed for access to the second target resource by the forwarded request from the winning requester and requests from one or more of the plurality of requesters using a second arbitration point associated with the second target resource.

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Номер записи: 28
22-11-2012 дата публикации

Optimized flash based cache memory

Номер: US20120297113A1
Автор: Assaf NITZAN, Binny S. Gill, Daniel F. Smith, Edi Shmueli, Eyal Lotem, James L. Hafner, Steven R. Hetzler, Venu G. Nayar, Wendy A. Belluomini
Принадлежит: International Business Machines Corp

Embodiments of the invention relate to throttling accesses to a flash memory device. The flash memory device is part of a storage system that includes the flash memory device and a second memory device. The throttling is performed by logic that is external to the flash memory device and includes calculating a throttling factor responsive to an estimated remaining lifespan of the flash memory device. It is determined whether the throttling factor exceeds a threshold. Data is written to the flash memory device in response to determining that the throttling factor does not exceed the threshold. Data is written to the second memory device in response to determining that the throttling factor exceeds the threshold.

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Номер записи: 29
22-11-2012 дата публикации

Dynamic hierarchical memory cache awareness within a storage system

Номер: US20120297142A1
Автор: Binny S. Gill, Edi Shmueli, Haim Helman
Принадлежит: International Business Machines Corp

Described is a system and computer program product for implementing dynamic hierarchical memory cache (HMC) awareness within a storage system. Specifically, when performing dynamic read operations within a storage system, a data module evaluates a data prefetch policy according to a strategy of determining if data exists in a hierarchical memory cache and thereafter amending the data prefetch policy, if warranted. The system then uses the data prefetch policy to perform a read operation from the storage device to minimize future data retrievals from the storage device. Further, in a distributed storage environment that include multiple storage nodes cooperating to satisfy data retrieval requests, dynamic hierarchical memory cache awareness can be implemented for every storage node without degrading the overall performance of the distributed storage environment.

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Номер записи: 30
29-11-2012 дата публикации

Populating strides of tracks to demote from a first cache to a second cache

Номер: US20120303875A1
Автор: Lokesh M. Gupta, Matthew J. Kalos, Michael T. Benhase
Принадлежит: International Business Machines Corp

Provided are a computer program product, system, and method for populating strides of tracks to demote from a first cache to a second cache. A first cache maintains modified and unmodified tracks from a storage system subject to Input/Output (I/O) requests. A determination is made to demote tracks from the first cache. A determination is made as to whether there are enough tracks ready to demote to form a stride, wherein tracks are written to a second cache in strides defined for a Redundant Array of Independent Disk (RAID) configuration. A stride is populated with tracks ready to demote in response to determining that there are enough tracks ready to demote to form the stride. The stride of tracks, to demote from the first cache, are promoted to the second cache. The tracks in the second cache that are modified are destaged to the storage system.

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Номер записи: 31
29-11-2012 дата публикации

Intelligent caching

Номер: US20120303896A1
Автор: Kathleen A. McGroddy-Goetz, Pamela A. Nesbitt, Sandeep R. Patil
Принадлежит: International Business Machines Corp

Intelligent caching includes defining a cache policy for a data source, selecting parameters of data in the data source to monitor, the parameters forming a portion of the cache policy, and monitoring the data source for an event based on the cache policy. Upon an occurrence of an event, the intelligent caching also includes retrieving target data subject to the cache policy from a first location and moving the target data to a second location.

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Номер записи: 32
29-11-2012 дата публикации

Managing track discard requests to include in discard track messages

Номер: US20120303899A1
Автор: Kenneth W. Todd, Kevin J. Ash, Lokesh M. Gupta, Michael T. Benhase
Принадлежит: International Business Machines Corp

Provided are a computer program product, system, and method for managing track discard requests to include in discard track messages. A backup copy of a track in a cache is maintained in the cache backup device. A track discard request is generated to discard tracks in the cache backup device removed from the cache. Track discard requests are queued in a discard track queue. In response to detecting that a predetermined number of track discard requests are queued in the discard track queue while processing in a discard multi-track mode, one discard multiple tracks message is sent indicating the tracks indicated in the queued predetermined number of track discard requests to the cache backup device instructing the cache backup device to discard the tracks indicated in the discard multiple tracks message. In response to determining a predetermined number of periods of inactivity while processing in the discard multi-track mode, processing the track discard requests is switched to a discard single track mode.

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Номер записи: 33
20-12-2012 дата публикации

Systems and methods providing wear leveling using dynamic randomization for non-volatile memory

Номер: US20120324141A1
Автор: Dong Hyuk Woo, Hsien-Hsin S. Lee, Nak Hee Seong
Принадлежит: Georgia Tech Research Corp

Systems and methods for dynamically remapping elements of a set to another set based on random keys. Application of said systems and methods to dynamically mapping regions of memory space of non-volatile memory, e.g., phase-change memory, can provide a wear-leveling technique. The wear leveling technique can be effective under normal execution of typical applications, and in worst-case scenarios including the presence of malicious exploits and/or compromised operating systems, wherein constantly migrating the physical location of data inside the PCM avoids information leakage and increases security; wherein random relocation of data results in the distribution of memory requests across the physical memory space increases durability; and wherein such wear leveling schemes can be implemented to provide fine-grained wear leveling without overly-burdensome hardware overhead e.g., a look-up table.

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Номер записи: 34
27-12-2012 дата публикации

Information processing method for determining weight of each feature in subjective hierarchical clustering

Номер: US20120330957A1
Автор: Masafumi Nishimura, Ryuki Tachibana, TAKASHIMA Ryoichi, Toru Nagano
Принадлежит: International Business Machines Corp

An information processing apparatus determines a weight of each physical feature for hierarchical clustering by acquiring training data of multiple pieces of content in triplets with label information indicating a pair specified by a user as having a highest degree of similarity among three contents of the triplet and executing hierarchical clustering using a feature vector of each piece of content of the training data and the weight of each feature to determine the hierarchical structure of the training data. The information processing apparatus updates the weight of each feature so that the degree of agreement between a pair combined first as being the same clusters among three contents of the triplet in a determined hierarchical structure and a pair indicated by label information corresponding to the triplet increases.

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Номер записи: 35
10-01-2013 дата публикации

Flash management techniques

Номер: US20130013856A1
Автор: Andrew Rogers, Sachin C. Patel, Yadhu N. Gopalan
Принадлежит: Microsoft Corp

Various flash management techniques may be described. An apparatus may comprise a processor, a flash memory coupled to the processor, and a flash management module. The flash management module may be executed by the processor to receive a write request to write data to the flash memory, write a first control sector with a sequence number to the flash memory, and write the sequence number, an address for a logical sector, and data to at least one physical sector corresponding to the logical sector of the flash memory. Other embodiments are described and claimed.

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Номер записи: 36
17-01-2013 дата публикации

Handheld imaging device with image processor provided with multiple parallel processing units

Номер: US20130016232A1
Автор: Kia Silverbrook
Принадлежит: Google LLC

A handheld imaging device includes an image sensor for sensing an image; a micro-controller integrating therein a dedicated image processor for processing the sensed image, a bus interface, and an image sensor interface; and a plurality of processing units connected in parallel by a crossbar switch, the plurality of processing units provided within the micro-controller to form a multi-core processing unit for the processor. The image sensor interface provides communication between the micro-controller and the image sensor. The bus interface provides communication between the micro-controller and devices external to the micro-controller other than the image sensor.

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Номер записи: 37
17-01-2013 дата публикации

Handheld imaging device with multi-core image processor integrating image sensor interface

Номер: US20130016236A1
Автор: Kia Silverbrook
Принадлежит: Google LLC

A handheld imaging device includes an image sensor for sensing an image; a processor for processing the sensed image; a multi-core processing unit provided in the processor, the multi-core processing unit having a plurality of processing units connected in parallel by a crossbar switch; and an image sensor interface for converting signals from the image sensor to a format readable by the multi-core processing unit, the image sensor interface sharing a wafer substrate with the processor. A transfer of data from the image sensor interface to the plurality of processing units is conducted entirely on the shared wafer substrate.

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Номер записи: 38
17-01-2013 дата публикации

Handheld imaging device with vliw image processor

Номер: US20130016266A1
Автор: Kia Silverbrook
Принадлежит: Google LLC

A handheld imaging device includes an image sensor for sensing an image: a Very Long Instruction Word (VLIW) processor for processing the sensed image; a plurality of processing units provided in the VLIW processor, the plurality of processing units connected in parallel by a crossbar switch to form a multi-core processing unit for the VLIW processor; and an image sensor interface for receiving signals from the image sensor and converting the signals to a format readable by the VLIW processor, the image sensor interface sharing a wafer substrate with the VLIW processor. A transfer of data from the image sensor interface to the VLIW processor is conducted entirely on the shared wafer substrate.

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Номер записи: 39
17-01-2013 дата публикации

Multi-partitioning of memories

Номер: US20130019058A1
Автор: Danilo Caraccio, Emanuele Confalonieri, Federico Tiziani
Принадлежит: Individual

Various embodiments comprise apparatuses and methods including a method of reconfiguring partitions in a memory device as directed by a host. The method includes managing commands through a first interface controller to mapped portions of a first memory not having an attribute enhanced set, and mapping portions of a second memory having the attribute enhanced set through a second interface controller. Additional apparatuses and methods are described.

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Номер записи: 40
24-01-2013 дата публикации

Camera system with color display and processor for reed-solomon decoding

Номер: US20130021443A1
Автор: Kia Silverbrook
Принадлежит: Google LLC

A camera system including: a substrate having a coding pattern printed thereon and a handheld digital camera device. The camera device includes: a digital camera unit having a first image sensor for capturing images and a color display for displaying captured images to a user; an integral processor configured for: controlling operation of the first image sensor and color display; decoding an imaged coding pattern printed on a substrate, the printed coding pattern employing Reed-Solomon encoding; and performing an action in the handheld digital camera device based on the decoded coding pattern. The decoding includes the steps of: detecting target structures defining the extent of the data area; determining the data area using the detected target structures; and Reed-Solomon decoding the coding pattern contained in the determined data area.

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Номер записи: 41
28-03-2013 дата публикации

Non-Uniform Memory Access (NUMA) Enhancements for Shared Logical Partitions

Номер: US20130080712A1
Автор: Mark R. Funk, Mysore S. Srinivas, Randal C. Swanberg, Ronald D. Young, Steven R. Kunkel, Vaijayanthimala K. Anand
Принадлежит: International Business Machines Corp

In a NUMA-topology computer system that includes multiple nodes and multiple logical partitions, some of which may be dedicated and others of which are shared, NUMA optimizations are enabled in shared logical partitions. This is done by specifying a home node parameter in each virtual processor assigned to a logical partition. When a task is created by an operating system in a shared logical partition, a home node is assigned to the task, and the operating system attempts to assign the task to a virtual processor that has a home node that matches the home node for the task. The partition manager then attempts to assign virtual processors to their corresponding home nodes. If this can be done, NUMA optimizations may be performed without the risk of reducing the performance of the shared logical partition.

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Номер записи: 42
02-05-2013 дата публикации

Storage device and computer using the same

Номер: US20130111116A1
Автор: Ryo Fujita, Ryoichi Inada, Takuma Nishimura
Принадлежит: HITACHI LTD

A storage device includes a non-volatile memory, a cache memory and a memory controller. The non-volatile memory stores a logical-to-physical address translation table for managing partitioned data and storage locations thereof. The cache memory stores a data cache and a logical-to-physical address translation table cache which holds a portion of the logical-to-physical address translation table. When the memory controller receives a data read-out request from outside, in the case no empty entry is found in the data cache, among the partitioned data in the data cache, it creates an empty entry to read out the data thereto by evacuating partitioned data of which entries in the logical-to-physical address translation table exist in the logical-to-physical address translation table cache into the non-volatile memory prior to other partitioned data.

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Номер записи: 43
02-05-2013 дата публикации

Dynamically adjusted threshold for population of secondary cache

Номер: US20130111133A1
Автор: Evangelos S. Eleftheriou, Ioannis Koltsidas, Lokesh M. Gupta, Michael T. Benhase, Robert Haas, Roman A. Pletka, Stephen L. Blinick, Xiao-yu HU
Принадлежит: International Business Machines Corp

The population of data to be inserted into secondary data storage cache is controlled by determining a heat metric of candidate data; adjusting a heat metric threshold; rejecting candidate data provided to the secondary data storage cache whose heat metric is less than the threshold; and admitting candidate data whose heat metric is equal to or greater than the heat metric threshold. The adjustment of the heat metric threshold is determined by comparing a reference metric related to hits of data most recently inserted into the secondary data storage cache, to a reference metric related to hits of data most recently evicted from the secondary data storage cache; if the most recently inserted reference metric is greater than the most recently evicted reference metric, decrementing the threshold; and if the most recently inserted reference metric is less than the most recently evicted reference metric, incrementing the threshold.

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Номер записи: 44
02-05-2013 дата публикации

Digital Signal Processing Data Transfer

Номер: US20130111159A1
Автор: Adrian J. Anderson, Gareth J. Davies, Gary C. Wass
Принадлежит: Imagination Technologies Ltd

A technique for transferring data in a digital signal processing system is described. In one example, the digital signal processing system comprises a number of fixed function accelerators, each connected to a memory access controller and each configured to read data from a memory device, perform one or more operations on the data, and write data to the memory device. To avoid hardwiring the fixed function accelerators together, and to provide a configurable digital signal processing system, a multi-threaded processor controls the transfer of data between the fixed function accelerators and the memory. Each processor thread is allocated to a memory access channel, and the threads are configured to detect an occurrence of an event and, responsive to this, control the memory access controller to enable a selected fixed function accelerator to read data from or write data to the memory device via its memory access channel.

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Номер записи: 45
09-05-2013 дата публикации

Managing Chip Multi-Processors Through Virtual Domains

Номер: US20130117521A1
Автор: Naveen Muralimanohar, Norman Paul Jouppi, SHENG Li
Принадлежит: Hewlett Packard Development Co LP

A chip multi-processor (CMP) with virtual domain management. The CMP has a plurality of tiles each including a core and a cache, a mapping storage, a plurality of memory controllers, a communication bus interconnecting the tiles and the memory controllers, and machine-executable instructions. The tiles and memory controllers are responsive to the instructions to group the tiles into a plurality of virtual domains, each virtual domain associated with at least one memory controller, and to store a mapping unique to each virtual domain in the mapping storage.

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Номер записи: 46
16-05-2013 дата публикации

System and method for data inversion in a storage resource

Номер: US20130124779A1
Автор: Gary B. Kotzur, William Price Dawkins
Принадлежит: Dell Products LP

A method may comprise receiving a page of data to be stored on a storage resource. The method may also comprise determining, for each particular inversion mode of a plurality of inversion modes, the number of bits of the page of data to be inverted to store a representation of the page of data in accordance with the particular inversion mode. The method may additionally comprise determining a selected inversion mode from the plurality of inversion modes for the page of data, the selected inversion mode comprising the inversion mode for which the least number of physical bit transitions are required to store the representation of the page of data in accordance with the selected inversion mode. The method may further comprise storing the representation of the page of data in a data memory in accordance with the inversion mode.

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Номер записи: 47
23-05-2013 дата публикации

Storage system, storage apparatus and method of controlling storage system

Номер: US20130132673A1
Автор: Akira Yamamoto, Hideo Saito, Yoshiaki Eguchi
Принадлежит: HITACHI LTD

A storage system enables a core storage apparatus to execute processing requiring securing of data consistency, while providing high write performance to a host computer. A storage system includes an edge storage apparatus 20 configured to communicate with a host computer 10 and including a cache memory 25 , and a core storage apparatus 30 that communicates with the edge storage apparatus 20 and perform I/O processing on a storage device 39 . When receiving a write request from the host computer 10 , the edge storage apparatus 20 processes the write request by writeback. When about to execute storage function control processing, on condition that data consistency is be secured, such as pair split processing of a local copy function, the core storage apparatus 30 requests the edge storage apparatus 20 to perform forced destage of dirty data in the cache memory 25 and then executes the storage function control processing after the completion of the forced destage.

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Номер записи: 48
23-05-2013 дата публикации

Optimizing distributed data analytics for shared storage

Номер: US20130132967A1
Автор: Gokul Soundararajan, Madalin Mihailescu
Принадлежит: NetApp Inc

Methods, systems, and computer executable instructions for performing distributed data analytics are provided. In one exemplary embodiment, a method of performing a distributed data analytics job includes collecting application-specific information in a processing node assigned to perform a task to identify data necessary to perform the task. The method also includes requesting a chunk of the necessary data from a storage server based on location information indicating one or more locations of the data chunk and prioritizing the request relative to other data requests associated with the job. The method also includes receiving the data chunk from the storage server in response to the request and storing the data chunk in a memory cache of the processing node which uses a same file system as the storage server.

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Номер записи: 49
30-05-2013 дата публикации

Systems, methods, and devices for running multiple cache processes in parallel

Номер: US20130138865A1
Автор: JunSeok Shim, Youngsun Park
Принадлежит: SEAGATE TECHNOLOGY LLC

Certain embodiments of the present disclosure related to systems, methods, and devices for increasing data access speeds. In certain embodiments, a method includes running multiple cache retrieval processes in parallel, in response to a read command. In certain embodiments, a method includes initiating a first cache retrieval process and a second cache retrieval process to run in parallel, in response to a single read command.

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Номер записи: 50
18-07-2013 дата публикации

Populating a first stride of tracks from a first cache to write to a second stride in a second cache

Номер: US20130185478A1
Автор: Karl A. Nielsen, Kevin J. Ash, Lokesh M. Gupta, Matthew J. Kalos, Michael T. Benhase
Принадлежит: International Business Machines Corp

Provided are a computer program product, system, and method for managing data in a cache system comprising a first cache, a second cache, and a storage system. A determination is made of tracks stored in the storage system to demote from the first cache. A first stride is formed including the determined tracks to demote. A determination is made of a second stride in the second cache in which to include the tracks in the first stride. The tracks from the first stride are added to the second stride in the second cache. A determination is made of tracks in strides in the second cache to demote from the second cache. The determined tracks to demote from the second cache are demoted.

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Номер записи: 51
18-07-2013 дата публикации

Writing adjacent tracks to a stride, based on a comparison of a destaging of tracks to a defragmentation of the stride

Номер: US20130185507A1
Автор: Lokesh M. Gupta
Принадлежит: International Business Machines Corp

Compressed data is maintained in a plurality of strides of a redundant array of independent disks, wherein a stride is configurable to store a plurality of tracks. A request is received to write one or more tracks. The one or more tracks are written to a selected stride of the plurality of strides, based on comparing the number of operations required to destage selected tracks from the selected stride to the number of operations required to defragment the compressed data in the selected stride.

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Номер записи: 52
25-07-2013 дата публикации

Managing addressable memory in heterogeneous multicore processors

Номер: US20130191605A1
Автор: Yan Solihin
Принадлежит: EMPIRE TECHNOLOGY DEVELOPMENT LLC

Technologies described herein generally describe technologies for managing addressable memories in a heterogeneous multicore chip. Technologies may be adapted to determine whether swapping a first data segment and a second data segment is suitable. The first data segment may be stored in a first addressable memory, and the second data segment may be stored in a second addressable memory. If the swapping is determined to be suitable, then the technologies may be adapted to swap the first data segment and the second data segment. As a result of the swap, the first data segment will be stored in the second addressable memory, and the second data segment will be stored in the first addressable memory. The technologies may also be adapted to update corresponding swap status indicators to indicate that the first data segment and the second data segment have moved.

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Номер записи: 53
01-08-2013 дата публикации

Content addressable stores based on sibling groups

Номер: US20130198475A1
Автор: Bertrand Serlet, Emanuele Altieri, Roger Bodamer
Принадлежит: UpThere Inc

A content addressable storage (CAS) system is provided in which each storage unit is assigned to one of a plurality of sibling groups. Each sibling group is assigned the entire hash space. Within each sibling group, the hash space is partitioned into hash segments which are assigned to the individual storage units that belong to the sibling group. Chunk retrieval requests are submitted to all sibling groups. Chunk storage requests are submitted to a single sibling group. The sibling group to which a storage request is submitted depends on whether any sibling group already stores the chunk, and which sibling groups are considered full.

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Номер записи: 54
15-08-2013 дата публикации

Technique to share information among different cache coherency domains

Номер: US20130207987A1
Автор: Altug Koker, Ariel Berkovits, Opher Kahn, Robert L. Farrell, Thomas A. Piazza, Zeev Offen
Принадлежит: Individual

A technique to enable information sharing among agents within different cache coherency domains. In one embodiment, a graphics device may use one or more caches used by one or more processing cores to store or read information, which may be accessed by one or more processing cores in a manner that does not affect programming and coherency rules pertaining to the graphics device.

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Номер записи: 55
29-08-2013 дата публикации

Data Migration between Memory Locations

Номер: US20130227218A1
Автор: Jichuan Chang, Justin James Meza, Parthasarathy Ranganathan
Принадлежит: Hewlett Packard Development Co LP

Migrating data may include determining to copy a first data block in a first memory location to a second memory location and determining to copy a second data block in the first memory location to the second memory location based on a migration policy.

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Номер записи: 56
05-09-2013 дата публикации

Method and Apparatus of Accessing Data of Virtual Machine

Номер: US20130232303A1
Автор: Xiao Fei Quan
Принадлежит: Alibaba Group Holding Ltd

A methods and device for accessing virtual machine (VM) data are described. A computing device for accessing virtual machine comprises an access request process module, a data transfer proxy module and a virtual disk. The access request process module receives a data access request sent by a VM and adds the data access request to a request array. The data transfer proxy module obtains the data access request from the request array, maps the obtained data access request to a corresponding virtual storage unit, and maps the virtual storage unit to a corresponding physical storage unit of a distributed storage system. A corresponding data access operation may be performed based on a type of the data access request.

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Номер записи: 57
05-09-2013 дата публикации

Communication management apparatus, communication management method, and computer program product

Номер: US20130232314A1
Автор: Kosuke Takahashi, Masataka Goto, Nobuhiko Sugasawa, Shinya Murai, Yuta Kobayashi
Принадлежит: Toshiba Corp

According to an embodiment, a communication management apparatus mediates data between an information processing terminal having a temporary memory and an external memory device that is installed outside the information processing terminal. The apparatus includes a receiving unit configured to receive a write request issued by a device other than the information processing terminal for writing the data in the external memory device; a reading-writing unit configured to control reading of the data from the external memory device and control writing of the data in the external memory device; and a delete command issuing unit configured to, when the write request with respect to the external memory device is received, issue a delete command to the information processing terminal for deleting temporary data that is stored in the temporary memory.

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Номер записи: 58
19-09-2013 дата публикации

Integer and Half Clock Step Division Digital Variable Clock Divider

Номер: US20130243148A1
Автор: Anthony Lell, Raguram Damodaran, Ramakrishnan Venkatasubramanian
Принадлежит: TEXAS INSTRUMENTS INCORPORATED

A clock divider is provided that is configured to divide a high speed input clock signal by an odd, even or fractional divide ratio. The input clock may have a clock cycle frequency of 1 GHz or higher, for example. The input clock signal is divided to produce an output clock signal by first receiving a divide factor value F representative of a divide ratio N, wherein the N may be an odd or an even integer. A fractional indicator indicates the divide ratio is N.5 when the fractional indicator is one and indicates the divide ratio is N when the fractional indicator is zero. F is set to 2(N.5)/2 for a fractional divide ratio and F is set to N/2 for an integer divide ratio. A count indicator is asserted every N/2 input clock cycles when N is even. The count indicator is asserted alternately N/2 input clock cycles and then 1+N/2 input clock cycles when N is odd. One period of an output clock signal is synthesized in response to each assertion of the count indicator when the fractional indicator indicates the divide ratio is N.5. One period of the output clock signal is synthesized in response to two assertions of the count indicator when the fractional indicator indicates the divide ratio is an integer.

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Номер записи: 59
19-09-2013 дата публикации

Optimizing signature computation and sampling for fast adaptive similarity detection based on algorithm-specific performance

Номер: US20130243190A1
Автор: Pulkit Misra, QING Yang
Принадлежит: Velobit Inc

A set of similarity detection algorithms and techniques for determining which signature calculation, sampling, and generation algorithms may be most beneficially applied to application related data are described herein. These algorithms work well with SSD caching software to product high speed, high accuracy, and low false-positive detections. Because the different algorithms may show different performance depending on data sets and different applications, to achieve optimal performance, a calibration process may be applied to each application and associated data set to select the best combination of signature computation and sampling technique. The new algorithms are also very fast with execution times an order of magnitude smaller than existing techniques. While some of the algorithms are presented using examples for the purpose of easy readability, these algorithms are very general and can be easily applied to broad range of cases.

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Номер записи: 60
03-10-2013 дата публикации

Parallel computer system and control method

Номер: US20130262683A1
Автор: Naoki HAYASHI, Tsuyoshi Hashimoto
Принадлежит: Fujitsu Ltd

A disclosed control method is executed by a node of plural nodes that are connected in a parallel computer system through a network. The control method includes obtaining property data representing a property of accesses to data stored in a storage device in a first node of the plural nodes for a job to be executed by using data stored in the storage device, and determining a resource to be allocated to a cache among resources included in the parallel computer system and the network based on the obtained property data.

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Номер записи: 61
10-10-2013 дата публикации

Apparatus and method for implementing a multi-level memory hierarchy having different operating modes

Номер: US20130268728A1
Автор: Glenn J. Hinton, Raj K. Ramanujan, Rajat Agarwal
Принадлежит: Individual

A system and method are described for integrating a memory and storage hierarchy including a non-volatile memory tier within a computer system. In one embodiment, PCMS memory devices are used as one tier in the hierarchy, sometimes referred to as “far memory.” Higher performance memory devices such as DRAM placed in front of the far memory and are used to mask some of the performance limitations of the far memory. These higher performance memory devices are referred to as “near memory.” In one embodiment, the “near memory” is configured to operate in a plurality of different modes of operation including (but not limited to) a first mode in which the near memory operates as a memory cache for the far memory and a second mode in which the near memory is allocated a first address range of a system address space with the far memory being allocated a second address range of the system address space, wherein the first range and second range represent the entire system address space.

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Номер записи: 62
24-10-2013 дата публикации

Hierarchical memory magnetoresistive random-access memory (mram) architecture

Номер: US20130279244A1
Автор: Seung H. Kang, Xiaochun Zhu
Принадлежит: Qualcomm Inc

A hierarchical memory magnetoresistive random-access memory architecture is disclosed. In a particular embodiment, an apparatus includes a first magnetoresistive random-access memory (MRAM) device corresponding to a first level in a hierarchical memory system. The apparatus includes a second MRAM device corresponding to a second level in the hierarchical memory system. The first MRAM device has a first access latency and includes a first magnetic tunnel junction (MTJ) device having a first physical configuration. The second MRAM device has a second access latency and includes a second WI device having a second physical configuration. The first access latency is less than the second access latency.

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Номер записи: 63
24-10-2013 дата публикации

Communicating to Update a Memory

Номер: US20130282966A1
Автор: Sreekrishnan Venkiteswaran
Принадлежит: International Business Machines Corp

Embedded devices typically have an operating system, one or more file-systems, as well as a bootloader and other data components resident in flash memory. During software development and testing, there is frequently a need to selectively update a combination of such images. The described technique organizes the images in the flash memory such that one can speed up the update process by eliminating relocation of existing images. A command-driven update mechanism provides a flexible process—eg, one can upload the images back to a host, one can update the update code itself, etc. A start handshake is used that enables auto-detection of the embedded serial port that is used for the update.

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Номер записи: 64
31-10-2013 дата публикации

Managing memory

Номер: US20130290636A1
Автор: Meichun Hsu, Qiming Chen, Ren WU
Принадлежит: Hewlett Packard Development Co LP

Methods, and apparatus to cause performance of such methods, for managing memory. The methods include requesting a particular unit of data from a first level of memory. If the particular unit of data is not available from the first level of memory, the methods further include determining whether a free unit of data exists in the first level of memory, evicting a unit of data from the first level of memory if a free unit of data does not exist in the first level of memory, and requesting the particular unit of data from a second level of memory. If the particular unit of data is not available from the second level of memory, the methods further include reading the particular unit of data from a third level of memory. The methods still further include writing the particular unit of data to the first level of memory.

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Номер записи: 65
28-11-2013 дата публикации

Apparatus and method for accelerating operations in a processor which uses shared virtual memory

Номер: US20130318323A1
Автор: Boris Ginzburg, Eliezer Weissmann, Karthikeyan Karthik VAITHIANATHAN, Ronny Ronen, Yoav ZACH
Принадлежит: Intel Corp

An apparatus and method are described for coupling a front end core to an accelerator component (e.g., such as a graphics accelerator). For example, an apparatus is described comprising: an accelerator comprising one or more execution units (EUs) to execute a specified set of instructions; and a front end core comprising a translation lookaside buffer (TLB) communicatively coupled to the accelerator and providing memory access services to the accelerator, the memory access services including performing TLB lookup operations to map virtual to physical addresses on behalf of the accelerator and in response to the accelerator requiring access to a system memory.

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Номер записи: 66
12-12-2013 дата публикации

Information processing apparatus and method and program

Номер: US20130332662A1
Автор: Hiroki Nagahama, Tomohiro Katori
Принадлежит: Sony Corp

There is provided an information processing apparatus including a table saving unit configured to copy an address conversion table stored in a first storage area of a memory to a storage area other than the first storage area and save the copied address conversion table, a table recovery unit configured to recover the address conversion table of a saving time point by copying the saved address conversion table to the first storage area of the memory, and a rewrite control unit configured to, when there is a rewrite request for data of a virtual address associated with a physical address on the address conversion table after the address conversion table has been saved, change the physical address associated with the virtual address, and cause the rewritten data to be stored in a storage area corresponding to the changed physical address.

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Номер записи: 67
19-12-2013 дата публикации

Optimizing write performance to flash memory

Номер: US20130339573A1
Автор: Adrian C. Gerhard, Charles E. Mari, Clark A. Anderson, Dustin J. VanStee, Edward W. Chencinski, Elpida Tzortzatos, Jon S. Entwistle, Kenneth J. Oakes, Peter G. Sutton, Steven M. Partlow, Thomas J. Griffin
Принадлежит: International Business Machines Corp

Embodiments relate to optimizing write performance of a flash device. Aspects include receiving a request to evict a plurality of pages from a main memory and determining a block size for the flash device. Aspects also include grouping the plurality of pages from the main memory into a move specification block, wherein a size of the move specification block is the block size and writing the move specification block to the flash device. The block size being determined based on one or more operational characteristics of the flash device.

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Номер записи: 68
02-01-2014 дата публикации

Cache Collaboration in Tiled Processor Systems

Номер: US20140006713A1
Автор: Ahmad Ahmad SAMIH, Christian Maciocco, Ren Wang, Tsung-Yuan C. Tai
Принадлежит: Intel Corp

The present invention may provide a computer system including a plurality of tiles divided into multiple virtual domains. Each tile may include a router to communicate with others of said tiles, a private cache to store data, and a spill table to record pointers for data evicted from the private cache to a remote host, wherein the remote host and the respective tile are provided in the same virtual domain. The spill tables may allow for faster retrieval of previously evicted data because the home registry does not need to be referenced if requested data is listed in the spill table. Therefore, embodiments of the present invention may provide a distance-aware cache collaboration architecture without incurring extraneous overhead expenses.

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Номер записи: 69
09-01-2014 дата публикации

Managing Data Writing to Memories

Номер: US20140010014A1
Автор: Christopher P. Dudte, Michael J. Cornwell
Принадлежит: Apple Inc

Systems and processes may use a first memory, a second memory, and a memory controller. The second memory is at least as large as a block of the first memory. Data is received and stored in the second memory for further writing to the second memory.

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Номер записи: 70
09-01-2014 дата публикации

Computer system, cache control method and computer program

Номер: US20140012936A1
Автор: Kazuhide Aikoh, Keisuke Hatasaki
Принадлежит: HITACHI LTD

The first application program and/or the second application program send(s) an access request to the second cache management module. The second cache management module receives the access request from the first application program and/or the second application program, and references the second cache management table to identify the storage location of the access-target data conforming to the access request. When access-target data exists in first cache area, the second cache management module sends a data transfer request to the first cache management module storing the access-target data, and where access-target data does not exist in the first cache area, acquires the access-target data from the second storage device. When the access-target data is in first cache area, the first cache management module acquires the access-target data conforming to the data transfer request from the relevant first cache area, and sends access-target data to the second cache management module.

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Номер записи: 71
09-01-2014 дата публикации

Nonvolatile random access memory and data management method

Номер: US20140013034A1
Автор: Jihyuk Oh, Oh-seong Kwon
Принадлежит: SAMSUNG ELECTRONICS CO LTD

A data management method for a main memory including a memory controller and a nonvolatile RAM includes; designating code page data temporarily stored in a standby area of the nonvolatile RAM as set, copying the code page data from the standby area to an in-use area of the nonvolatile RAM, designating the code page data stored in the in-use area as reset, and thereafter, during rebooting of a user device incorporating the main memory, invalidating the reset code page data while retaining the set code page data in the nonvolatile RAM.

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Номер записи: 72
23-01-2014 дата публикации

Nonvolatile memory, reading method of nonvolatile memory, and memory system including nonvolatile memory

Номер: US20140026232A1
Автор: JINYUB LEE, SEUNGJAE LEE
Принадлежит: SAMSUNG ELECTRONICS CO LTD

A nonvolatile memory device includes a memory cell array and a read/write circuit connected to the memory cell array through bit lines. The read method of the nonvolatile memory device includes receiving a security read request, receiving security information, and executing a security read operation in response to the security read request. The security read operation includes reading of security data from the memory cell array using the read/write circuit, storing of the read security data in a register, performing security decoding on the read security data stored in the register using the received security information, resetting the read/write circuit, and outputting a result of the security decoding.

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Номер записи: 73
30-01-2014 дата публикации

Providing a hybrid memory

Номер: US20140032818A1
Автор: Jichuan Chang, Parthasarathy Ranganathan
Принадлежит: Hewlett Packard Development Co LP

A hybrid memory has a volatile memory and a non-volatile memory. The volatile memory is dynamically configurable to have a first portion that is part of a memory partition, and a second portion that provides a cache for the non-volatile memory.

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Номер записи: 74
30-01-2014 дата публикации

Systems and methods for maintaining the coherency of a store coalescing cache and a load cache

Номер: US20140032856A1
Автор: Karthikeyan Avudaiyappan, Mohammad Abdallah
Принадлежит: Soft Machines Inc

A method for maintaining the coherency of a store coalescing cache and a load cache is disclosed. As a part of the method, responsive to a write-back of an entry from a level one store coalescing cache to a level two cache, the entry is written into the level two cache and into the level one load cache. The writing of the entry into the level two cache and into the level one load cache is executed at the speed of access of the level two cache.

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Номер записи: 75
13-02-2014 дата публикации

Tunable multi-tiered stt-mram cache for multi-core processors

Номер: US20140047184A1
Автор: Seung H. Kang, Xiaochun Zhu, Xiaoxia Wu
Принадлежит: Qualcomm Inc

A multi-core processor is presented. The multi-core processor includes a first spin transfer torque magnetoresistive random-access memory (STT-MRAM) cache associated with a first core of the multi-core processor and tuned according to first attributes and a second STT-MRAM cache associated with a second core of the multi-core processor and tuned according to second attributes.

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Номер записи: 76
13-02-2014 дата публикации

System and method of caching information

Номер: US20140047191A1
Автор: David Presotto, Timo Burkard
Принадлежит: Google LLC

A system and method is provided wherein, in one aspect, a currently-requested item of information is stored in a cache based on whether it has been previously requested and, if so, the time of the previous request. If the item has not been previously requested, it may not be stored in the cache. If the subject item has been previously requested, it may or may not be cached based on a comparison of durations, namely (1) the duration of time between the current request and the previous request for the subject item and (2) for each other item in the cache, the duration of time between the current request and the previous request for the other item. If the duration associated with the subject item is less than the duration of another item in the cache, the subject item may be stored in the cache.

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Номер записи: 77
13-03-2014 дата публикации

Fast programming memory device

Номер: US20140071767A1
Автор: Demetrio Pellicone, Giuseppe Giannini, Marco Maccarrone
Принадлежит: Micron Technology Inc

In an embodiment of a memory device including a matrix of memory cells wherein the memory cells are arranged in a plurality of memory cells strings each one including at least two serially-connected memory cells, groups of at least two memory cells strings being connected to a respective bit line, and wherein said memory cells are adapted to be programmed into at least a first programming state and a second programming state, a method of storing data comprising exploiting a single memory cell for each of the memory cells string for writing the data, wherein said exploiting includes bringing the single memory cell to the second programming state, the remaining memory cells of the string being left in the first programming state.

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Номер записи: 78
13-03-2014 дата публикации

Replicating tracks from a first storage site to a second and third storage sites

Номер: US20140075114A1
Автор: Brian D. HATFIELD, Gail A. Spear, Lokesh M. Gupta, Michael T. Benhase
Принадлежит: International Business Machines Corp

Provided are a computer program product, system, and method for replicating tracks from a first storage to a second and third storages. A determination is made of a track in the first storage to transfer to the second storage as part of a point-in-time copy relationship and of a stride of tracks including the target track. The stride of tracks including the target track is staged from the first storage to a cache according to the point-in-time copy relationship. The staged stride is destaged from the cache to the second storage. The stride in the cache is transferred to the third storage as part of a mirror copy relationship. The stride of tracks in the cache is demoted in response to destaging the stride of the tracks in the cache to the second storage and transferring the stride of tracks in the cache to the third storage.

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Номер записи: 79
13-03-2014 дата публикации

Modifying memory space allocation for inactive tasks

Номер: US20140075139A1
Автор: David C. Reed, Max D. Smith, Michael R. Scott, Ryan J. Wisniewski
Принадлежит: International Business Machines Corp

Provided are a computer program product, system, and method for modifying memory space allocation for inactive tasks. Information is maintained on computational resources consumed by tasks running in the computer system allocated memory space in the memory. The information on the computational resources consumed by the tasks is used to determine inactive tasks of the tasks. The allocation of the memory space allocated to at least one of the determined inactive tasks is modified.

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Номер записи: 80
20-03-2014 дата публикации

Method and server for managing redundant arrays of independent disks cards

Номер: US20140082245A1
Автор: Chih-Huang WU
Принадлежит: Hon Hai Precision Industry Co Ltd

In a method for managing redundant arrays of independent disks (RAID) cards and a server for executing the method, the server calculates a theoretical percentage of a load of each RAID card according to a number of the RAID cards, and loads an actual percentage of the load of each RAID card through a multi input output (MIO) interface, and detects peripheral component interconnect-express (PCI-E) bandwidth of each RAID card. When the load of each RAID card is unbalanced or the PCI-E bandwidth of the RAID card is saturated, the server transfers the load from a RAID card having a greater actual percentage of the load into a RAID card having a less actual percentage of the load, and transfers the load from a RAID card whose PCI-E bandwidth is saturated into a RAID card whose PCI-E bandwidth is unsaturated according to differential signals through the MIO interface.

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Номер записи: 81
20-03-2014 дата публикации

Recovery from cache and nvs out of sync

Номер: US20140082254A1
Автор: Kenneth Wayne Todd, Kevin John Ash, Lokesh Mohan Gupta, Michael Thomas Benhase
Принадлежит: International Business Machines Corp

For cache/data management in a computing storage environment, incoming data segments into a Non Volatile Storage (NVS) device of the computing storage environment are validated against a bitmap to determine if the incoming data segments are currently in use. Those of the incoming data segments determined to be currently in use are designated to the computing storage environment to protect data integrity.

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Номер записи: 82
03-04-2014 дата публикации

Storage system

Номер: US20140095793A1
Автор: Atushi Ishikawa, Yuko Matsui
Принадлежит: HITACHI LTD

An object of the present invention is to provide a storage system which is shared by a plurality of application programs, wherein optimum performance tuning for a cache memory can be performed for each of the individual application programs. The storage system of the present invention comprises a storage device which provides a plurality of logical volumes which can be accessed from a plurality of application programs, a controller for controlling input and output of data to and from the logical volumes in response to input/output requests from the plurality of application programs, and a cache memory for temporarily storing data input to and output from the logical volume, wherein the cache memory is logically divided into a plurality of partitions which are exclusively assigned to the plurality of logical volumes respectively.

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Номер записи: 83
05-01-2017 дата публикации

MEMORY STATE INDICATOR CHECK OPERATIONS

Номер: US20170003884A1
Автор: Mak Pak-Kin, Slegel Timothy J., Walters Craig R., Webb Charles F.
Принадлежит:

Aspects include a computer-implemented method that includes receiving an instruction at a processor to perform an operation on a memory block having an address and accessing a state indicator by the processor without altering a value of the state indicator. The state indicator is stored in a memory location independent of the memory block, and accessing includes sending a request to an operator to return the value of the state indicator to the processor. The method also includes determining based on the value of the state indicator whether the memory block is in a pre-defined state. 1. A computer-implemented method , comprising:receiving an instruction at a processor to perform an operation on a memory block having an address;accessing a state indicator by the processor without altering a value of the state indicator, the state indicator stored in a memory location independent of the memory block, wherein accessing includes sending a request to an operator to return the value of the state indicator to the processor; anddetermining based on the value of the state indicator whether the memory block is in a pre-defined state.2. The method of claim 1 , wherein determining is performed without changing the value of the state indicator.3. The method of claim 1 , further comprising:based on the value of the state indicator indicating that the memory block is in the pre-defined state, sending a request to return a subset of the memory block to the processor; andidentifying the pre-defined state of the memory block based on the subset of the memory block.4. The method of claim 1 , further comprising:based on the value of the state indicator indicating that the memory block is in the pre-defined state, identifying the pre-defined state based on the value of the state indicator without at least one of directly inspecting any contents of the memory block and returning any of the contents to the processor.5. The method of claim 1 , further comprising:based on the state indicator ...

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Номер записи: 84
05-01-2017 дата публикации

MEMORY STATE INDICATOR CHECK OPERATIONS

Номер: US20170003886A1
Автор: Mak Pak-Kin, Slegel Timothy J., Walters Craig R., Webb Charles F.
Принадлежит:

Aspects include a computer-implemented method includes receiving an instruction at a processor to perform an operation on a memory block having an address and accessing a state indicator by the processor without altering a value of the state indicator. The state indicator is stored in a memory location independent of the memory block, and accessing includes sending a request to an operator to return the value of the state indicator to the processor. The method also includes determining based on the value of the state indicator whether the memory block is in a pre-defined state. 18-. (canceled)9. A system comprising:a memory having computer readable instructions; and [ 'accessing a state indicator by the processor without altering a value of the state indicator, the state indicator stored in a memory location independent of the memory block, wherein accessing includes sending a request to an operator to return the value of the state indicator to the processor; and', 'receiving an instruction at a processor to perform an operation on a memory block having an address;'}, 'determining based on the value of the state indicator whether the memory block is in a pre-defined state., 'one or more processing devices for executing the computer readable instructions, the computer readable instructions comprising10. The system of claim 9 , wherein determining is performed without changing the value of the state indicator.11. The system of claim 9 , the instructions further comprising:based on the value of the state indicator indicating that the memory block is in the pre-defined state, sending a request to return a subset of the memory block to the processor; andidentifying the pre-defined state of the memory block based on the subset of the memory block.12. The system of claim 9 , the instructions further comprising:based on the value of the state indicator indicating that the memory block is in the pre-defined state, identifying the pre-defined state based on the value of the ...

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Номер записи: 85
05-01-2017 дата публикации

STORAGE DEVICE INCLUDING NONVOLATILE SEMICONDUCTOR MEMORIES WITH DIFFERENT CHARACTERISTICS, METHOD FOR CONTROLLING STORAGE DEVICE, AND COMPUTER-READABLE NONVOLATILE STORAGE MEDIUM FOR STORING PROGRAM

Номер: US20170003892A1
Автор: SEKIDO Kazunori
Принадлежит:

According to one embodiment, a storage device includes a storage, first data in which a sequence number indicating a write-completion order is associated with each erase unit area included in areas of the storage, second data indicating a relationship between each write interval and each write destination, a selection module which obtains the erase unit area corresponding to a logical address of target data to be written, calculates a write interval of the target data from a difference between the sequence number at an occurrence time of writing and the sequence number corresponding to the erase unit area of the first data, and selects the write destination corresponding to the write interval of the target data, and a write module which writes the target data to the selected write destination, and changes the sequence number when writing is completed for one erase unit area. 1. A storage device comprising:a storage module including a plurality of areas having different upper limits in the number of erases;a management storage module which stores first management data in which a sequence number indicating an order of write-completion is associated with each erase unit area included in the plurality of areas, second management data indicating a relationship between each write interval and each write destination area, and address translation data in which a logical address is associated with the erase unit area;a selection module which, when target data to be written is written to the storage module, obtains the erase unit area corresponding to the logical address of the target data to be written based on the address translation data, calculates a write interval of the target data to be written from a difference between the sequence number at a time of occurrence of writing the target data to be written and the sequence number corresponding to the erase unit area of the first management data based on the first management data, and selects the write destination area ...

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Номер записи: 86
05-01-2017 дата публикации

MEMORY SYSTEM FOR CONTROLLING SEMICONDUCTOR MEMORY DEVICES THROUGH PLURALITY OF CHANNELS

Номер: US20170003909A1
Автор: CHO Sung Yeob
Принадлежит:

A memory system includes a plurality of channels; a plurality of semiconductor memory devices connected to the channels; and a controller that controls the semiconductor memory devices through the channels, wherein the controller writes program data in a first semiconductor memory device of the plurality of semiconductor memory devices, and wherein, when the writing of the program data fails, the program data is temporarily stored in a page buffer unit of a second semiconductor memory device of the plurality of semiconductor memory devices connected to a channel other than the channel corresponding to the first semiconductor memory device. 1. A memory system , comprising:a plurality of channels;a plurality of semiconductor memory devices connected to the channels; anda controller that controls the semiconductor memory devices through the channels,wherein the controller writes program data in a first semiconductor memory device of the plurality of semiconductor memory devices, and wherein, when the writing of the program data is failed, the program data is temporarily stored in a page buffer unit of a second semiconductor memory device of the plurality of semiconductor memory devices connected to a channel other than the channel corresponding to the first semiconductor memory device.2. The memory system of claim 1 , wherein the controller retrieves the program data from the page buffer unit of the second semiconductor memory device claim 1 , and re-writes the program data in one of the semiconductor memory devices.3. The memory system of claim 1 , wherein the first semiconductor memory device is connected to a first channel among the channels claim 1 ,the second semiconductor memory device is connected to a second channel among the channels, andwhen the writing of the program data is failed, the controller retrieves the program data from the first semiconductor memory device through the first channel, and temporarily stores the program data in the page buffer unit of ...

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Номер записи: 87
05-01-2017 дата публикации

COMPUTER

Номер: US20170004081A1
Автор: Hatta Yukari, HAYAKAWA Norimitsu, KONAGAYA Masatoshi, TOTSUKA Takao
Принадлежит:

A computer, on which a plurality of operating systems run, wherein the plurality of operating systems includes a first operating system and a second operating system configured to generate a plurality of virtual computers. The first operating system runs on a first logical resource, and the second operating system runs on a second logical resource. A third operating system runs on each of the plurality of virtual computers. The third operating system secures a cache memory area in a virtual memory. The second operating system generates location information, which indicates a location of the cache memory area in a physical address space that the second operating system manages. The first operating system obtain data stored in the cache memory area based on the location information. 1. A computer , on which a plurality of operating systems run , the computer comprising , as physical resources:a processor;a volatile memory coupled to the processor;a non-volatile memory coupled to the processor; andan I/O device coupled to the processor,wherein the plurality of operating systems includes a first operating system and a second operating system configured to generate a plurality of virtual computers,wherein the first operating system is configured to run on a first logical resource, the first logical resource including a first logical processor, which is created by logically dividing the processor, a first logical volatile memory, which is created by logically dividing the volatile memory, and a first logical I/O device, which is created by logically dividing the I/O device,wherein the first operating system includes a power cut detecting unit configured to detect cutting of power to the computer,wherein the second operating system is configured to run on a second logical resource, the second logical resource including a second logical processor, which is created by logically dividing the processor, a second logical volatile memory, which is created by logically dividing ...

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Номер записи: 88
05-01-2017 дата публикации

System, method and mechanism to efficiently coordinate cache sharing between cluster nodes operating on the same regions of a file or the file system blocks shared among multiple files

Номер: US20170004083A1
Автор: Abhishek Gupta, Anindya Banerjee, Sanjay Jain, Shirish Vijayvargiya
Принадлежит: Veritas Technologies LLC

Various systems, methods and apparatuses for coordinating the sharing of cache data between cluster nodes operating on the same data objects. One embodiment involves a first node in a cluster receiving a request for a data object, querying a global lock manager to determine if a second node in the cluster is the lock owner of the data object, receiving an indication identifying the second node as the lock owner and indicating that the data object is available in the second node's local cache, requesting the data object from the second node, and then receiving the data object from the second node's local cache. Other embodiments include determining whether the lock is a shared lock or an exclusive lock, and either pulling the data object from the local node of the second cache or receiving the data object that is pushed from the second node, as appropriate.

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Номер записи: 89
05-01-2017 дата публикации

ADAPTIVE CACHE MANAGEMENT METHOD ACCORDING TO ACCESS CHARACTERISTICS OF USER APPLICATION IN DISTRIBUTED ENVIRONMENT

Номер: US20170004087A1
Автор: AN Jae Hoon, KIM Young Hwan
Принадлежит:

An adaptive cache management method according to access characteristic of a user application in a distributed environment is provided. The adaptive cache management method includes: determining an access pattern of a user application; and determining a cache write policy based on the access pattern. Accordingly, a delay in speed which may occur in an application can be minimized by efficiently using resources established in a distributed environment and using an adaptive policy. 1. An adaptive cache management method comprising:determining an access pattern of a user application; anddetermining a cache write policy based on the access pattern.2. The adaptive cache management method of claim 1 , wherein the determining the cache write policy comprises claim 1 , when the access pattern indicates that recently referred data is referred to again claim 1 , determining a cache write policy of storing data recorded on a cache in a storage medium afterward.3. The adaptive cache management method of claim 1 , wherein the determining the cache write policy comprises claim 1 , when the access pattern indicates that referred data is referred to again after a predetermined interval claim 1 , determining a cache write policy of immediately storing data recorded on a cache in a storage medium.4. The adaptive cache management method of claim 1 , wherein the determining the cache write policy comprises claim 1 , when the access pattern indicates that referred data is not referred to again claim 1 , determining a cache write policy of immediately storing data in a storage medium without recording on a cache.5. The adaptive cache management method of claim 1 , further comprising:selecting data which is most likely to be referred to based on the access pattern; andloading the selected data into a cache.6. A storage server comprising:a cache; anda processor configured to determine an access pattern of a user application and determine a cache write policy based on the access pattern. The ...

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Номер записи: 90
07-01-2016 дата публикации

Buffered Automated Flash Controller Connected Directly to Processor Memory Bus

Номер: US20160004457A1
Автор: Andrew D. Walls, James S. Fields, Jr.
Принадлежит: International Business Machines Corp

A mechanism is provided for buffer linking in a buffered solid state drive controller. Responsive to the buffered flash memory module receiving from a memory bus of a processor a memory command specifying a write operation, the mechanism initializes a first memory buffer in the buffered flash memory module. The mechanism associates the first memory buffer with an address of the write operation. The mechanism performs a compare operation to compare a previous and a next address with respect to an address associated with the first memory buffer with a plurality of buffers. The mechanism assigns a link tag to at least one buffer identified in the compare operation and the first memory buffer to form a linked buffer set. The mechanism writes to the first memory buffer based on the memory command. The mechanism builds at least one input/output command to persist contents of the linked buffer set and writes the contents of the linked buffer set to at least one solid state drive according to the at least one input/output command.

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Номер записи: 91
07-01-2016 дата публикации

DATA-STORAGE DEVICE AND FLASH MEMORY CONTROL METHOD

Номер: US20160004468A1
Автор: CHENG Chang-Kai
Принадлежит:

A data-storage device having a flash memory allocated to provide data-storage space, a valid page count table, logical-to-physical address mapping information, and an invalid block record. The data-storage device further having a controller, allocating the data-storage space to store data issued from a host, and establishing and maintaining the valid page count table, the logical-to-physical address mapping information, and the invalid block record in the FLASH memory to manage the data-storage space. A FLASH memory control method is also provided. 1. A data-storage device , comprising:a FLASH memory, allocated to provide data-storage space, a valid page count table, logical-to-physical address mapping information, and an invalid block record; anda controller, allocating the data-storage space to store data issued from a host, and establishing and maintaining the valid page count table, the logical-to-physical address mapping information, and the invalid block record in the FLASH memory to manage the data-storage space, the controller updates the logical-to-physical address mapping information after an update of the valid page count table is completed; and', 'the controller maintains the invalid block record based on the valid page count table., 'wherein2. The data-storage device as claimed in claim 1 , wherein the controller further records an event record into the FLASH memory to record memory allocations occurring after the latest complete round of updates of the valid page count table claim 1 , the logical-to-physical address mapping information claim 1 , and the invalid block record.3. The data-storage device as claimed in claim 2 , wherein the controller updates the valid page count table based on a comparison between the event record and the logical-to-physical address mapping information.4. The data-storage device as claimed in claim 3 , wherein:every round of updating the valid page count table, the logical-to-physical address mapping information, and the ...

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Номер записи: 92
07-01-2016 дата публикации

INTERNAL STORAGE, EXTERNAL STORAGE CAPABLE OF COMMUNICATING WITH THE SAME, AND DATA PROCESSING SYSTEM INCLUDING THE STORAGES

Номер: US20160004634A1
Автор: Kim Dong Min
Принадлежит:

A memory controller, a data processing system, and an electronic device are provided. The memory controller is configured to share a function of one of an internal storage and an external storage in a union mode in which the external storage and the internal storage are logically unified with each other. 1. A memory controller configured to share a function of one of an internal storage and an external storage in a union mode in which the external storage and the internal storage are logically unified with each other ,wherein the memory controller is configured to translate a logical address into a physical address based on a global mapping table which maps the logical address to the physical address of each of the internal storage and the external storage and is further configured to determine which of the internal storage and the external storage processes data transmitted from a host.2. The memory controller of claim 1 , wherein claim 1 , in the union mode claim 1 , the memory controller is configured to control all data of a file to be stored in either of the internal storage and the external storage according to control of the host.3. The memory controller of claim 1 , wherein the memory controller is configured to store data in the internal storage and the external storage in a distributed fashion at a write request of the host.4. The memory controller of claim 1 , wherein in response to the memory controller receiving a request from the host to read data from the internal storage while the external storage is performing a write operation claim 1 , the memory controller is configured to perform a read operation to read the data from the internal storage to be performed.5. The memory controller of claim 1 , wherein the memory controller is configured to collect feature information of the internal storage claim 1 , provide the feature information of the internal storage to the external storage claim 1 , and receive feature information of the external storage ...

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Номер записи: 93
07-01-2016 дата публикации

NVRAM CACHING AND LOGGING IN A STORAGE SYSTEM

Номер: US20160004637A1
Автор: Kimmel Jeffrey S.
Принадлежит:

In one embodiment, a node coupled to solid state drives (SSDs) of a plurality of storage arrays executes a storage input/output (I/O) stack having a plurality of layers. The node includes a non-volatile random access memory (NVRAM). A first portion of the NVRAM is configured as a write-back cache to store write data associated with a write request and a second portion of the NVRAM is configured as one or more non-volatile logs (NVLogs) to record metadata associated with the write request. The write data is passed from the write-back cache over a first path of the storage I/O stack for storage on a first storage array and the metadata is passed from the one or more NVLogs over a second path of the storage I/O stack for storage on a second storage array, wherein the first path is different from the second path. 1. A system comprising:a central processing unit (CPU) of a node of a cluster coupled to solid state drives (SSDs) of a plurality of storage arrays;a memory coupled to the CPU and configured to store a storage input/output (I/O) stack having a plurality of layers executable by the CPU; anda non-volatile random access memory (NVRAM) coupled to the CPU, a first portion of the NVRAM configured as a write-back cache to store write data associated with a write request and a second portion of the NVRAM configured as one or more non-volatile logs (NVLogs) to record metadata associated with the write request, the write data passed from the write-back cache over a first path of the storage I/O stack for storage on a first storage array and the metadata passed from the one or more NVLogs over a second path of the storage I/O stack for storage on a second storage array, wherein the first path is different from the second path.2. The system of wherein the write data is preserved in the write-back cache until successfully stored on the first storage array and the metadata is preserved in the one or more NVLogs until successfully stored on the second storage array.3. The ...

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Номер записи: 94
07-01-2016 дата публикации

Dynamically Configurable Memory

Номер: US20160004638A1
Автор: Lewsey David Matthew
Принадлежит:

A device includes a memory including ways and a processor in communication with the memory. The processor is configured to execute logic. The logic can monitor a parameter of the processor or a device connected with the processor. The logic can allocate, based on the parameter, a number a ways and a size of ways of the memory for use by the processor. The logic can power down an unallocated number of ways and unused portions of the ways of the memory. 1. A device , comprising:a cache memory;a processor in communication with the cache memory, the processor configured to execute logic operable to:dynamically allocate a portion of the cache memory for use by the processor;modify an index function in accordance with the allocated portion of the cache memory;apply the modified index function to a system memory address to determine an index of a cache line corresponding to the system memory address, the cache line included among a group of cache lines identified with the modified index function as being in the allocated portion of the cache memory; andconstrain operation of the cache memory to the group of cache lines identified with the modified index function.2. The device of claim 1 , wherein the processor is further configured to execute logic operable to generate and store a tag in association with the index to uniquely identify contents of the cache line as data stored at the system memory address claim 1 , the tag generated as a function of the system memory address.3. The device of claim 2 , wherein the processor is further configured to execute logic operable to store a state of the cache line in association with the tag and the index claim 2 , the state indicative of a validity of the cache line.4. The device of claim 1 , wherein the cache memory includes a plurality of groups of cache lines claim 1 , and the index is indicative of the cache line in each of the plurality of groups of cache lines.5. The device of claim 4 , wherein the processor is further ...

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Номер записи: 95
07-01-2016 дата публикации

STORAGE DEVICE AND METHOD FOR CONTROLLING STORAGE DEVICE

Номер: US20160004642A1
Автор: HIRONAKA Kazuei, Sugimoto Sadahiro, YAMAMOTO Akira
Принадлежит:

The storage device of the present invention provides a decompression VOL having no corresponding relationship (mapping) with a final storage media to a superior device, and receives accesses from the superior device to the decompression VOL. Then, data written into the decompression VOL is compressed on-line in a cache memory, and the compressed data is mapped to a compression VOL which is a volume mapped to a final storage media. At the same time, by maintaining and managing a mapping information between an area in the decompression VOL where data has been written and a location in the compression VOL to which compressed data of the relevant data is mapped, when a read request is received from a superior device regarding the decompression VOL, the storage device converts a location information in the decompression VOL designated by the read request to a location information of the final storage media. 1. A storage device connected to a host computer , and having a processor , a cache device and a plurality of final storage media ,the storage device comprising:a first volume capable of being accessed from the host computer;a second volume which is a volume mapped to the first volume, and storing the data written from the host computer to the first volume in a compressed state; whereinwhen the processor receives a write request to the first volume and a write target data regarding the write request from the host computer, the processor(1) sets the write target data in a compressed state in the cache device and stores the same in a storage area within the cache device;(2) determines a storage location in the second volume of the write target data in the compressed state;(3) allocates a storage area in the final storage media to be mapped to the storage location in the second volume of the write target data in the compressed state, in response to the storage location being determined; and(4) reads the write target data in the compressed state from the cache device, and ...

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Номер записи: 96
07-01-2016 дата публикации

Storage Controller and Method for Managing Modified Data Flush Operations From a Cache

Номер: US20160004644A1
Автор: Mark Ish, Suagata Das Purkayastha, Sumanesh Samanta
Принадлежит: Avago Technologies General IP Singapore Pte Ltd

A storage controller maintaining a cache manages modified data flush operations. A set-associative map or relationship between individual cache lines in the cache and a corresponding portion of the host managed or source data store is generated in such a way that a quotient can be used to identify modified data in the cache in the order of the source data's logical block addresses. The storage controller uses a collision bitmap, a dirty bit map and a flush table when flushing data from the cache. The storage controller selects a quotient and identifies modified cache lines in the cache identified by the quotient. As long as the quotient remains the same, the storage controller flushes or transfers the modified cache lines to the data store. Otherwise, when the quotient is not the same, the data in the cache is skipped. A linked list is used to traverse skipped cache lines.

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Номер записи: 97
07-01-2016 дата публикации

ENCRYPTION AND RECORDING APPARATUS, ENCRYPTION AND RECORDING SYSTEM, AND ENCRYPTION AND RECORDING METHOD

Номер: US20160004646A1
Автор: INOUE Shinji, Katoh Yoshikazu, Maeda Takuji
Принадлежит:

An encryption and recording apparatus storing data, the apparatus including: a first nonvolatile memory; a second nonvolatile memory; and an encryption and decryption control unit, wherein the encryption and decryption control unit: manages an area included in the second nonvolatile memory on a per-block basis, and manages association between a block and a block-unique key using key management information stored in the first nonvolatile memory; receives the data and corresponding information associated with the data; encrypts the data, using one or more block-unique keys associated with one or more blocks included in the second nonvolatile memory and writes the data to the one or more blocks; and stores the corresponding information into the key management information, associating the corresponding information and the one or more block-unique keys. 1. An encryption and recording apparatus storing data , comprising:a first nonvolatile memory;a second nonvolatile memory; andan encryption and decryption control unit configured to encrypt and write the data to the second nonvolatile memory, and read the encrypted data from the second nonvolatile memory and decrypt the encrypted data, wherein manage an area included in the second nonvolatile memory on a per-block basis and manage association between a block and a block-unique key using key management information stored in the first nonvolatile memory;', 'when receiving a write indication for writing the data from an access apparatus external to the encryption and recording apparatus, receive the data and corresponding information associated with the data, encrypt the data using a plurality of block-unique keys associated with a plurality of blocks included in the second nonvolatile memory and write the data to the plurality of blocks; and', 'store the corresponding information into the key management information, associating the corresponding information from the access data apparatus and the plurality of block-unique ...

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Номер записи: 98
07-01-2016 дата публикации

CACHING SYSTEMS AND METHODS WITH SIMULATED NVDRAM

Номер: US20160004653A1
Автор: Purkayastha Saugata Das, Sampathkumar Kishore Kaniyar
Принадлежит:

Systems and methods presented herein provide for simulated NVDRAM operations. In a host system, a host memory is sectioned into pages. An HBA in the host system comprises a DRAM and an SSD for cache operations. The DRAM and the SSD are sectioned into pages and mapped to pages of the host memory. The SSD is further sectioned into regions comprising one or more pages of the SSD. The HBA is operable to load a page of data from the SSD into a page of the DRAM when directed by a host processor, to determine that the page of the DRAM is occupied with other data, to determine a priority of the region of the page of other data occupying the page of the DRAM, and to flush the other data from the DRAM to the SSD based on the determined priority. 1. A system , comprising:a host processor;a host memory communicatively coupled to the host processor and sectioned into pages;a host bus adapter (HBA) communicatively coupled to the host processor and comprising a Dynamic Random Access Memory (DRAM) and a Solid State Memory (SSD) for cache operations andan HBA driver operable on the host processor,wherein the DRAM is sectioned into pages mapped to pages of the host memory and the SSD is sectioned into pages mapped to pages of the DRAM,wherein the SSD is further sectioned into regions comprising one or more pages of the SSD, andwherein the HBA driver is operable to load a page of data from the SSD into a page of the DRAM when directed by the host processor, to determine that the page of the DRAM is occupied with other data, to determine a priority of a region of the page of the other data occupying the page of the DRAM, and to flush the other data from the DRAM to the SSD based on the determined priority.2. The system of claim 1 , further comprising:a storage device comprising an operating system executable by the host processor, wherein the operating system comprises an application that is operable to change priorities of the regions of the SSD.3. The system of claim 2 , wherein:the ...

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Номер записи: 99
07-01-2016 дата публикации

Computing system and operating method of the same

Номер: US20160004655A1
Автор: Jin-Hyeok Choi, Sun-Young Lim, Young-Jin Cho, Young-Kwang Yoo
Принадлежит: SAMSUNG ELECTRONICS CO LTD

A computing system includes a first unified module including a first storage device and a second storage device that are different from each other, and a unified module interface configured to provide a direct memory access (DMA) request signal to control a first DMA with respect to the first storage device and to perform a second DMA on the second storage device. An application processor is configured to receive the DMA request signal from the unified module interface, and provide a DMA request response signal to the unified module interface and control the second DMA with respect to the second storage device.

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Номер записи: 100