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Небесная энциклопедия

Космические корабли и станции, автоматические КА и методы их проектирования, бортовые комплексы управления, системы и средства жизнеобеспечения, особенности технологии производства ракетно-космических систем

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Мониторинг СМИ

Мониторинг СМИ и социальных сетей. Сканирование интернета, новостных сайтов, специализированных контентных площадок на базе мессенджеров. Гибкие настройки фильтров и первоначальных источников.

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Форма поиска

Поддерживает ввод нескольких поисковых фраз (по одной на строку). При поиске обеспечивает поддержку морфологии русского и английского языка
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Применить Всего найдено 37625. Отображено 100.
26-01-2012 дата публикации

Parallel loop management

Номер: US20120023316A1
Автор: Brian Flachs, Charles R. Johns, Ulrich Weigand
Принадлежит: International Business Machines Corp

The illustrative embodiments comprise a method, data processing system, and computer program product having a processor unit for processing instructions with loops. A processor unit creates a first group of instructions having a first set of loops and second group of instructions having a second set of loops from the instructions. The first set of loops have a different order of parallel processing from the second set of loops. A processor unit processes the first group. The processor unit monitors terminations in the first set of loops during processing of the first group. The processor unit determines whether a number of terminations being monitored in the first set of loops is greater than a selectable number of terminations. In response to a determination that the number of terminations is greater than the selectable number of terminations, the processor unit ceases processing the first group and processes the second group.

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Номер записи: 1
02-02-2012 дата публикации

Constructing runtime state for inlined code

Номер: US20120030659A1
Автор: Christopher Arthur Lattner, Eric Marshall Christopher, Francois Jouaux, jia-hong Chen, Pratik Solanki, Robert John McCall, Roger Scott Hoover, Thomas John O'brien, Victor Leonel Hernandez Porras
Принадлежит: Apple Inc

Techniques for processing computer code are disclosed. In one example, an indication that a computer code is to begin execution at a portion of code other than a starting portion of the code is received, and a runtime state associated with the portion of the code at which execution is to begin is constructed. In some examples, execution of the portion of code is initiated. In some examples, a program counter associated with the portion of the code is used to initiate execution of the code. In some examples, the computer code comprises a fallback code associated with a previously executing code.

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Номер записи: 2
02-02-2012 дата публикации

Development tool for footprint reduction

Номер: US20120030662A1
Автор: Brendan Conoboy, Clark Williams
Принадлежит: Red Hat Inc

A method and apparatus for reducing a memory footprint of an embedded system. The method may include analyzing packages installed in a root file system of the embedded system, and determining which package components are not required for the operation of the embedded system. The method further includes reducing a memory footprint of the embedded system based on the above determination.

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Номер записи: 3
23-02-2012 дата публикации

Virtualization with fortuitously sized shadow page tables

Номер: US20120047348A1
Автор: Gerald A. FRY, Lawrence S. Rogel, Prashanth P. BUNGALE, Scott W. Devine
Принадлежит: VMware LLC

One or more embodiments provides a shadow page table used by a virtualization software wherein at least a portion of the shadow page table shares computer memory with a guest page table used by a guest operating system (OS) and wherein the virtualization software provides a mapping of guest OS physical pages to machine pages.

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Номер записи: 4
01-03-2012 дата публикации

method and system for code generation and inlining

Номер: US20120054725A1
Автор: Derek B. Inglis, Kiyokuni Kawachiya, Michiaki Tatsubori, Tamiya Onodera
Принадлежит: International Business Machines Corp

A method and system for code generation and inlining. The method includes: scanning a code, where the code includes a method; determining whether the method includes a branch if the method is too large in size to be inlined, where the branch is based on runtime types of argument; profiling runtime types of actual arguments at a call site in the method if the method includes the branch; generating a polymorphic inline cache (PIC) code from a plurality of arguments, where the plurality of arguments are based on a result of the profiling step; generating a specialized method for a frequently appearing combination of the runtime types of argument and arguments that can be invoked from the PIC code; and inlining body of the specialized method into the call site if the specialized method has a body size within a permissible range.

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Номер записи: 5
08-03-2012 дата публикации

Computer-aided parallelizing of computation graphs

Номер: US20120056888A1
Автор: Craig W. Stanfill
Принадлежит: Ab Initio Technology LLC

An approach to automatically specifying, or assisting with the specification of, a parallel computation graph involves determining data processing characteristics of the linking elements that couple data processing elements of the graph. The characteristics of the linking elements are determined according to the characteristics of the upstream and/or downstream data processing elements associated with the linking element, for example, to enable computation by the parallel computation graph that is equivalent to computation of an associated serial graph.

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Номер записи: 6
08-03-2012 дата публикации

Allocating register halves independently

Номер: US20120060011A1
Автор: Christopher A. Lapkowski, Chwan-Hang Lee, David P. Bélanger
Принадлежит: International Business Machines Corp

Register halves are allocated independently when performing register allocation during program compilation, thereby effectively doubling the number of registers which are available for allocation, which in turn may reduce spill code and improve run-time performance. When hardware registers are 64 bits wide, for example, an architecture supporting the present invention provides some number of separate hardware instructions that operate on the 32-bit high-word and/or the 32-bit low word of the hardware registers as if those 32-bit words are separate registers. Such hardware instructions are able to manipulate the register halves independently, leaving the other register half untouched. A register coloring algorithm using in the compilation process is invoked using the number of register halves, instead of the number of hardware registers.

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Номер записи: 7
15-03-2012 дата публикации

C/c++ language extensions for general-purpose graphics processing unit

Номер: US20120066668A1
Автор: Bastiaan Aarts, Ian Buck
Принадлежит: Nvidia Corp

A general-purpose programming environment allows users to program a GPU as a general-purpose computation engine using familiar C/C++ programming constructs. Users may use declaration specifiers to identify which portions of a program are to be compiled for a CPU or a GPU. Specifically, functions, objects and variables may be specified for GPU binary compilation using declaration specifiers. A compiler separates the GPU binary code and the CPU binary code in a source file using the declaration specifiers. The location of objects and variables in different memory locations in the system may be identified using the declaration specifiers. CTA threading information is also provided for the GPU to support parallel processing.

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Номер записи: 8
22-03-2012 дата публикации

Domain specific language creation

Номер: US20120072886A1
Автор: Francis G. McCabe, Kenneth R. MacKenzie
Принадлежит: Starview Tech Inc

In one embodiment of the present invention, a method for using a domain specific computer language to extend an existing computer language is provided, comprising: creating a rule for validation for a compiler, the rule for validation created in a rule description language created specifically to describe rules for validation, the rule defining a part of the domain specific computer language; examine source text to identify a domain specific language to use for compiling; and compiling the source text using a compiler for an existing computer language using the identified domain specific language, wherein the compiler contains a rules interpretation engine that runs the rules for validation for the identified domain specific language, wherein the rules for validation are external to the compiler.

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Номер записи: 9
29-03-2012 дата публикации

Compile-time bounds checking for user-defined types

Номер: US20120079465A1
Автор: Daniel Stephen Harvey
Принадлежит: Microsoft Corp

Compile-time optimized bounds checking of user-defined types is provided. A user-defined class has an annotated memory-accessing method, and an annotated bound-providing member such as an integer field containing a bound or a method that returns a bound when called. The user-defined-bounds check may supply bounds checking where the programming language has none, or it may supplement existing bounds checks, e.g., by wrapping a built-in array type or a garbage-collector-managed type. Bounds checking can be extended beyond arrays and other types whose layout is controlled by a compiler, allowing efficient systems programming in a managed code environment. A bounds-check representation is inserted by the compiler in intermediate language code. Optimization then reduces duplicative bounds checking.

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Номер записи: 10
26-04-2012 дата публикации

Software development

Номер: US20120102454A1
Автор: Andrew Wright, Mark Todd, Philip R. Lee, Stephen J. Burghard
Принадлежит: International Business Machines Corp

A method, system and computer program product for developing software in which the software comprises a plurality of programs. A change to a program is received. A data structure checking procedure may then be invoked. The changed program is parsed for a reference to a data structure. Other instances of the data structure are located in other programs within the software. The referenced data structure is compared to the located other instances of the data structure. A predefined action (such as notifying a programmer or correcting the inconsistencies) is performed in response to any detected differences between the referenced data structure and the located other instances of the data structure. These steps are repeated for all data structures within the changed program.

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Номер записи: 11
31-05-2012 дата публикации

Method, a computer program and apparatus for analyzing symbols in a computer

Номер: US20120136652A1
Автор: Graham Kenneth Thwaites, Stephen Anthony Moyle
Принадлежит: Oracle International Corp

The invention provides a computer-implemented method of analyzing symbols in a computer system, the symbols conforming to a specification for the symbols, in which the specification has been codified into a set of computer-readable rules; and, the symbols analyzed using the computer-readable rules to obtain patterns of the symbols by determining the path that is taken by the symbols through the rules that successfully terminates, and grouping the symbols according to said paths, the method comprising; upon receipt of a message at a computer, performing a lexical analysis of the message; and, in dependence on lexical analysis of the message assigning the message to one of the groups identified according to said paths. The invention also provides a computer programmed to perform the method and a computer program comprising program instructions for causing a computer to perform the method.

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Номер записи: 12
31-05-2012 дата публикации

Skip list generation

Номер: US20120136871A1
Автор: Alexander Zaphob Barnes, David Karlov, Herve Soulard
Принадлежит: Canon Inc

A method of generating a skip list is disclosed. The skip list comprises a data structure for referencing a plurality of ordered nodes, the data structure having a plurality of linked lists, a total number of the plurality of linked lists being constrained by an available memory of a memory system, the method comprising the steps of: inserting a first node of the plurality of nodes into a predetermined linked list of the plurality of linked lists of the data structure of the skip list in the available memory; promoting the first node to one or more other linked lists based on a first set of criteria; and generating the skip list by inserting at least a second node of the plurality of nodes into the data structure and promoting the second node based on a second set of criteria, said second set of criteria being different from the first set of criteria.

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Номер записи: 13
21-06-2012 дата публикации

Method for converting mobile web application into native application and apparatus using the same

Номер: US20120159310A1
Автор: Chang Rak Yoon, Hak Cheol Kim, Jae Chul Kim, Ki Jung Lee, Kyung Ok Kim, Seong Ho Lee, Sung Woong SHIN, Yoon-Seop CHANG
Принадлежит: Electronics and Telecommunications Research Institute ETRI

A method for converting a mobile web application into a native application (the term “app” has the same meaning as the native application) and an apparatus using the method are disclosed. The method for converting a mobile web application into a native application may include: the steps of receiving at least one of a web implementation document that implements the mobile web application and a uniform resource locator (URL) for a local file; separating and analyzing a user interface element of the mobile web application based on the at least one of the web implementation document and the local file; and converting the mobile web application into the native application by mapping the analyzed user interface element to a native control that implements the native application.

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Номер записи: 14
21-06-2012 дата публикации

Preferred compilation

Номер: US20120159460A1
Автор: Günter Haug, Volker Hollich
Принадлежит: SAP SE

A method and system to identify code entities suitable for preferred compilation is provided. An example method comprises detecting a request to start up a computer program comprising a plurality of code entities and commence interpreting code entities of the computer program. A numeric value associated with a code entity is compared with a threshold value. The code entity is designated for compilation at a next compilation tier based on a result of the comparing.

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Номер записи: 15
28-06-2012 дата публикации

Invasion Analysis to Identify Open Types

Номер: US20120167091A1
Автор: Patrick W. Sathyanathan, Ten H. Tzen
Принадлежит: Microsoft Corp

The automated identification of open types of a multi-function input program. The automated identification of open types is performed without annotations in the input program, but rather by identifying a set of invading types of the program, with each of the invading types being an open type. The identification of invading types may be performed iteratively until the set of invading types no longer grows. The set of open types may be used for any purpose such as perhaps the de-virtualization of an input program during compilation.

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Номер записи: 16
12-07-2012 дата публикации

Flow analysis instrumentation

Номер: US20120179726A1
Автор: Andrew F. Roberts
Принадлежит: Ab Initio Original Works LLC, Ab Initio Software LLC, Ab Initio Technology LLC

Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for flow analysis. In one aspect, a method includes modifying a dataflow graph, the dataflow graph including a plurality of paths connecting at least one entry point and at least one exit point, including adding components to the dataflow graph that add flow units to data records and remove flow units from data records, each flow unit identifying a segment of a path traversed by the data record. The method also includes identifying execution paths based on flow units obtained by processing a plurality of data records using the modified dataflow graph. The method also includes determining a subset of the plurality of data records, wherein a selected set of execution paths are represented by the subset.

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Номер записи: 17
12-07-2012 дата публикации

Using ephemeral stores for fine-grained conflict detection in a hardware accelerated stm

Номер: US20120179875A1
Автор: Ali-Reza Adl-Tabatabai, Bratin Saha, Gad Sheaffer, Quinn Jacobson
Принадлежит: Individual

A method and apparatus for fine-grained filtering in a hardware accelerated software transactional memory system is herein described. A data object, which may have an arbitrary size, is associated with a filter word. The filter word is in a first default state when no access, such as a read, from the data object has occurred during a pendancy of a transaction. Upon encountering a first access, such as a first read, from the data object, access barrier operations including an ephemeral/private store operation to set the filter word to a second state are performed. Upon a subsequent/redundant access, such as a second read, the access barrier operations are elided to accelerate the subsequent access, based on the filter word being set to the second state to indicate a previous access occurred.

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Номер записи: 18
12-07-2012 дата публикации

Techniques for modifying a processor code sequence

Номер: US20120179897A1
Автор: Neil A. Campbell
Принадлежит: International Business Machines Corp

A technique of modifying a code sequence for a processor includes identifying a set of one or more target instructions in the code sequence. A replacement instruction is selected that includes a set of replacement instruction parts. A length of each of the replacement instruction parts corresponds to a minimum instruction length for an instruction set of the processor. The replacement instruction parts include a first instruction type and one or more second instruction types that are each configured as exception instructions if processed in isolation from the first instruction type. The replacement instruction is then substituted for the set of one or more target instructions in the code sequence for processing by the processor.

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Номер записи: 19
19-07-2012 дата публикации

Web browsing apparatus and method through storing and optimizing javascript® code

Номер: US20120185822A1
Автор: Gangwon Jo, Honggyu Kim, Hongjune Kim, Jaejin Lee, Jeongho Nah, Joo-Hwan Lee, Seung-Mo Cho, Yong-Jun Lee
Принадлежит: SAMSUNG ELECTRONICS CO LTD, SNU R&DB FOUNDATION

A web browsing method and apparatus for enhancing a user's convenience in web browsing is provided in a system that uses a multi-core processor. The web browsing method and apparatus is applicable in a system, such as a smart phone that has a low computing power or that has a storage device like a flash memory operating in a rapid manner. Optimized machine codes are stored in files and incremental optimization is achieved, so the JAVASCRIPT® program of the web application has a small compilation overhead and achieves fast execution.

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Номер записи: 20
16-08-2012 дата публикации

Running unary operation instructions for processing vectors

Номер: US20120210099A1
Автор: Jeffry E. Gonion
Принадлежит: Apple Inc

During operation, a processor generates a result vector. In particular, the processor records a value from an element at a key element position in an input vector into a base value. Next, for each active element in the result vector to the right of the key element position, the processor generates a result vector by setting the element in the result vector equal to a result of performing a unary operation on the base value a number of times equal to a number of relevant elements. The number of relevant elements is determined from the key element position to and including a predetermined element in the result vector, where the predetermined element in the result vector may be one of: a first element to the left of the element in the result vector; or the element in the result vector.

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Номер записи: 21
16-08-2012 дата публикации

Asynchronous programming execution

Номер: US20120210332A1
Автор: Fengbin Jiang, Sridhar Srinivasan, Xiang Zhou, Xiaoxuan Zhao
Принадлежит: Microsoft Corp

One or more techniques and/or systems are disclosed for improving asynchronous programming execution at runtime. Asynchronous programming code can comprise more than one level of hierarchy, such as in an execution plan. Respective aggregation operations in a portion of the asynchronous programming code are unrolled, to create a single level iterative execution, by combining elements of the multi-level iterative execution of the asynchronous programming code. In this way, the aggregation operations are concatenated to local logic code for the aggregation operations. Thread context switching in the unrolled portion of asynchronous programming code is performed merely at an asynchronous operation, thereby mitigating unnecessary switches. Exceptions thrown during programming code can be propagated up to a top of a virtual callstack for the execution.

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Номер записи: 22
30-08-2012 дата публикации

Method and System for presenting and analyzing software source code through intermediate representation

Номер: US20120222021A1
Автор: Kan Zhao
Принадлежит: Individual

The present invention provides a method and system for producing intermediate representation of source code listings with possibly mixed syntaxes to assist software development applications in presenting and analyzing the source code listings through reading the intermediate representation. A source code processor calls Application Programming Interfaces (APIs) to preserve source code information, which includes intermediate representation data sets and is preferably stored in a file-based repository. The source code processor is of a compiler, a preprocessor, a parser, or a comment document processor. The data sets capture lexical, syntax and semantic information of source code construct elements, and comprise of location, processor identification, construct category, and attribute data. A software development environment through a source code search engine is able to present source code construct elements, outlines, and symbol references from software packages over a plurality of distributed servers in a network such as the Internet.

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Номер записи: 23
30-08-2012 дата публикации

Instantiating an Interface or Abstract Class in Application Code

Номер: US20120222022A1
Автор: Geoffrey M. Hambrick, Kulvir S. Bhogal, Robert R. Peterson, Roland Barcia
Принадлежит: International Business Machines Corp

Mechanisms for instantiating an interface or abstract class in application code are provided. An object-oriented programming language is extended such that interfaces and abstract classes can be instantiated in application code without a concrete class specified. Metadata is defined which maps each interface or abstract class instantiation in the application code to a concrete class to be used either by the compiler at build time, or the virtual machine at runtime. Once the appropriate concrete class is determined from the metadata, the class is instantiated with a conventional class loader. The metadata may be provided, for example, as a separate file, such as a markup language file, defined with a virtual machine switch, as annotations in the application code, or the like.

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Номер записи: 24
13-09-2012 дата публикации

Efficient model checking technique for finding software defects

Номер: US20120233599A1
Автор: Cristina N. Cifuentes, Manuel Javier Valdiviezo Basauri
Принадлежит: Oracle International Corp

A method for detecting defects in a computer program. The method steps include obtaining source code and a potential defect definition; identifying, based on the potential defect definition, a set of program objects associated with a potential defect in the source code; extracting an executable program slice having the potential defect from the source code; generating, by a processor, an abstracted model of the program slice by: modeling, using data abstraction, the set of program objects as data-abstracted variables, identifying, within the program slice, a set of control statements including predicates necessary for evaluating the set of control statements, modeling, using predicate abstraction, the predicates as predicate-abstracted Boolean variables, and creating, based on the data-abstracted variables and the predicate-abstracted Boolean variables, a finite state machine (FSM) model of the program slice; and identifying an error state of the FSM indicating an occurrence of the potential defect within the program slice.

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Номер записи: 25
04-10-2012 дата публикации

Method of generating code executable by processor

Номер: US20120254551A1
Автор: Hironori Kasahara, Keiji Kimura, Masayoshi Mase
Принадлежит: WASEDA UNIVERSITY

It is provided a method of generating a code by a compiler, including the steps of: analyzing a program executed by a processor; analyzing data necessary to execute respective tasks included in a program; determining whether a boundary of the data used by divided tasks is consistent with a management unit of a cache memory based on results of the analyzing; and generating a code for providing a non-cacheable area from which the data to be stored in the management unit including the boundary is not temporarily stored into the cache memory and a code for storing an arithmetic processing result stored in the management unit including the boundary into a non-cacheable area in a case where it is determined that the boundary of the data used by the divided tasks is not consistent with the management unit of the cache memory.

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Номер записи: 26
22-11-2012 дата публикации

Methods for generating code for an architecture encoding an extended register specification

Номер: US20120297373A1
Автор: Brett Olsson, John-David Wellman, Michael K. Gschwind, Robert Kevin Montoye
Принадлежит: International Business Machines Corp

There are provided methods and computer program products for generating code for an architecture encoding an extended register specification. A method for generating code for a fixed-width instruction set includes identifying a non-contiguous register specifier. The method further includes generating a fixed-width instruction word that includes the non-contiguous register specifier.

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Номер записи: 27
29-11-2012 дата публикации

Points-to analysis as value flow

Номер: US20120304158A1
Автор: Cristina N. Cifuentes, Lian Li, Nathan Robert Albert Keynes
Принадлежит: Oracle International Corp

In general, in one aspect, the invention relates to a method for performing points-to analysis by generating a value flow graph for source code. The method steps include: initializing the value flow graph including a set of memory objects and a set of edges based on Base and Assignment instructions, where the set of edges represents inclusion constraints between the set of memory objects and a set of pointer variables; determining a pointed-to-by set including at least one pointer variable of the set of pointer variables; updating the value flow graph by introducing a flow edge based on an indirect reference, where the flow edge is related to a memory object of the set of memory objects that is added to a working list; updating the pointed-to-by set based on the memory object in the working list; and analyzing the source code using the pointed-to-by set.

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Номер записи: 28
29-11-2012 дата публикации

Hardware support for hashtables in dynamic languages

Номер: US20120304159A1
Автор: Luis Ceze, Mohammad H. Reshadi, Thomas Sartorius
Принадлежит: Qualcomm Inc

The aspects enable a computing device to execute traditionally software-based JavaScript® operations in hardware. Each JavaScript® object is hashed into a master hashtable that may be stored in the software. A portion of the software hashtable may be pushed to a hardware hashtable using special instruction set registers dedicated to hashtable processing. Each time a software process requests a hashtable operation (e.g., lookup) the hardware hashtable is checked to determine if the value exists in hardware. If the requested value is in the hardware hashtable, the requested value is accessed in a single operation step. If the requested value is not in the hardware hashtable, the requested value is extracted from the master hashtable in the software and a portion of the master hashtable containing the extracted value is pushed to the hardware using special instruction set registers.

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Номер записи: 29
29-11-2012 дата публикации

Systems and Methods for Run-Time Interception of Software Methods

Номер: US20120304160A1
Автор: Derek A. Soeder
Принадлежит: Ridgeway Internet Security LLC

The present disclosure involves systems and computer-implemented methods for installing software hooks. One process includes identifying a target method and a hook code, where the hook code is to execute instead of at least a portion of the target method, and wherein the target method and the hook code are executed within a managed code environment. A compiled version of the target method and a compiled version of the hook code are located in memory, where the compiled versions of the target method and the hook code are compiled in native code. Then, the compiled version of the target method is modified to direct execution of at least a portion of the compiled version of the target method to the compiled version of the hook code. The non-compiled version of the target method may be originally stored as bytecode. The managed code environment may comprise a managed .NET environment.

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Номер записи: 30
06-12-2012 дата публикации

Electronic device and method for updating coordinate systems during editing of a measuremnt program

Номер: US20120310577A1
Автор: Chih-Kuang Chang, Xin-Yuan Wu
Принадлежит: Hon Hai Precision Industry Co Ltd, Hongfujin Precision Industry Shenzhen Co Ltd

In a method for updating coordinate systems in editing a measurement program, the method imports a data array including measurement elements of a workpiece, and creates a program template. By inserting the program template in the data array that is after a measurement element, the method creates a coordinate system and calculates a coordinate matrix for the coordinate system. After the measurement elements in a position of the data array that are after the program template are updated using the coordinate matrix, a measurement program is generated and displayed on a display screen.

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Номер записи: 31
13-12-2012 дата публикации

Obtaining Profile Data for Use in Optimizing Computer Programming Code

Номер: US20120317553A1
Автор: William Jon Schmidt
Принадлежит: International Business Machines Corp

Program execution profile data is collected by direct measurement of some code paths, and by inferring data for unmeasured paths. The data collection process may cause errors, which are propagated by the inferencing process. The profile data thus constructed is further enhanced by detecting certain data mismatches, and adjusting inferred data to reduce the scope of errors propagated during the inferencing process. Preferably, a control flow graph of the program being measured is constructed. Mismatches in the total weights of input arcs versus output arcs are detected. For certain specific types of mismatches, it can be known or guessed which count is incorrect, and this count is accordingly corrected. Correction of arc counts proceeds recursively until it is no longer possible to correct mismatches. Additionally, certain other conditions are adjusted as presumed inaccuracies.

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Номер записи: 32
20-12-2012 дата публикации

Dynamic Loading of Kernel Extensions

Номер: US20120324484A1
Автор: Eric Philip Fried, Stephen Bailey Peckham
Принадлежит: International Business Machines Corp

An approach is provided in preparing a dynamically loaded kernel extension. The approach includes compiling a kernel extension program that includes a symbol, such as a function. The symbol is exported from the kernel extension program and a symbol broker that references the exported symbol is compiled. A kernel extension loader library is created with a defined callable symbol that corresponds to the exported symbol. The kernel extension loader library is linked by an external program after compilation of the external program resulting in a compiled external program. The kernel extension loader library dynamically loads the compiled kernel extension program, the compiled symbol broker, and the exported symbol when the defined callable symbol is referenced by during execution of the compiled external program.

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Номер записи: 33
27-12-2012 дата публикации

System and method for compiling machine-executable code generated from a sequentially ordered plurality of processor instructions

Номер: US20120331451A1
Автор: Robert Keith Mykland
Принадлежит: Robert Keith Mykland

A method and system are provided for deriving a resultant software program from an originating software program having overlapping branches, wherein the resultant software project has either no overlapping branches or fewer overlapping branches than the originating software program. A preferred embodiment of the invented method generates a resultant software program that has no overlapping branches. The resultant software is more easily converted into programming reconfigurable logic than the originating software program. Separate and individually applicable aspects of the invented method are used to eliminate all four possible states of two overlapping branches, i.e., forward branch overlapping forward branch, back branch overlapping back branch, and each of the two possible and distinguishable states of forward branch and back branch overlap. One or more elements of each aspect of the invention may be performed by one or more computers or processors, or by means of a computer or a communications network.

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Номер записи: 34
03-01-2013 дата публикации

Method and Programming System for Programming an Automation Component

Номер: US20130006398A1
Автор: Rudolf MÖSSNER
Принадлежит: SIEMENS AG

A method and programming system for programming an automation component of an industrial automation arrangement, the automation component being provided with at least one special main memory, such as a cache or a tightly coupled memory, with faster access, wherein a user is provided with an input option for assigning priority values to individual tasks of the automation program when creating the program, all of those program parts which are called when executing at least the task with the highest priority assigned by the user are automatically identified, and the identified program parts being permanently storable in the special main memory such that important program parts and routines are executable in a reproducible manner at high execution speed and with a short latency time.

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Номер записи: 35
03-01-2013 дата публикации

Processing vectors using wrapping add and subtract instructions in the macroscalar architecture

Номер: US20130007422A1
Автор: Jeffry E. Gonion
Принадлежит: Apple Inc

Embodiments of a system and a method in which a processor may execute instructions that cause the processor to receive an input vector and a control vector are disclosed. The executed instructions may also cause the processor to perform a sum or difference operation on another input vector dependent upon the input vector and the control vector.

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Номер записи: 36
03-01-2013 дата публикации

Debugging in a multiple address space environment

Номер: US20130007712A1
Автор: Amit Kumar Agarwal, Weirong Zhu, Yongkang Zhu, Yosseff Levanoni
Принадлежит: Microsoft Corp

The present invention extends to methods, systems, and computer program products for debugging in a multiple address space environment. Embodiments of the invention include techniques for recording debug information used for translating between an abstract unified address space and multiple address spaces at a target system (e.g., a co-processor, such as, a GPU or other accelerator). A table is stored in the recorded debug information. The table includes one or more entries mapping compiler assigned IDs to address spaces. During debugging within a symbolic debugger, the recorded debug information can be used for viewing program data across multiple address spaces in a live debugging session.

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Номер записи: 37
17-01-2013 дата публикации

Program Generating Apparatus, Method of Generating Program, and Medium

Номер: US20130019230A1
Автор: Shunsuke Sasaki, Takahiro Tokuyoshi, Toshiki Kizu, Yu Nakanishi
Принадлежит: Toshiba Corp

According to an embodiment, a program generating apparatus includes a cross-compiling unit, a processing time calculating unit, a source code converting unit, and a self-compiling unit. The cross-compiling unit generates sin instruction string for each basic block based on a source code and specifies instructions performing a memory access. The processing time calculating unit calculates a processing time of the instruction string for each basic block. The source code converting unit inserts a first code, which adds the processing time of the basic block to an accumulated processing time variable of an executed thread of the basic block, and a second code, which calculates the processing time for the specified memory access and adds the calculated processing time to the accumulated processing time variable, into the source code. The self-compiling unit generates a performance estimating program outputting the accumulated processing time variable of the thread executed.

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Номер записи: 38
24-01-2013 дата публикации

Relaxation of synchronization for iterative convergent computations

Номер: US20130024662A1
Автор: Lakshminarayanan Renganarayana, Vijayalakshmi Srinivasan
Принадлежит: International Business Machines Corp

Systems and methods are disclosed that allow atomic updates to global data to be at least partially eliminated to reduce synchronization overhead in parallel computing. A compiler analyzes the data to be processed to selectively permit unsynchronized data transfer for at least one type of data. A programmer may provide a hint to expressly identify the type of data that are candidates for unsynchronized data transfer. In one embodiment, the synchronization overhead is reducible by generating an application program that selectively substitutes codes for unsynchronized data transfer for a subset of codes for synchronized data transfer. In another embodiment, the synchronization overhead is reducible by employing a combination of software and hardware by using relaxation data registers and decoders that collectively convert a subset of commands for synchronized data transfer into commands for unsynchronized data transfer.

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Номер записи: 39
31-01-2013 дата публикации

Data processing apparatus, data processing system, and data processing method

Номер: US20130028260A1
Автор: Mitsuru Mushano
Принадлежит: Mush A Co Ltd

A data-processing apparatus includes a plurality of processing units having frequency bands different from one another set thereto, the plurality of processing units to process packets each including data and processing information added to the data, the processing information including instruction information indicating one or more processing instructions to the data, each processing unit in the processing units including: an input/output unit to obtain, in the packets, only a packet whose address indicates the processing unit in the processing units, the address determined in accordance with the processing information; and an operation unit to execute the processing instruction in the packet obtained by the input/output unit, the input/output unit including a receiving unit to receive only an electromagnetic wave having a frequency band set to the processing unit and obtain the packet.

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Номер записи: 40
31-01-2013 дата публикации

Processing table of content access overflow in an application

Номер: US20130031535A1
Автор: Jian Jiang, Jin Song Ji, Si Yuan Zhang
Принадлежит: International Business Machines Corp

The present disclosure provides a method and system for processing table of content (TOC) access overflow in an application. The method may determine whether there occurs a TOC access overflow within an object file during linking the object file that may be generated from the compiling. If the TOC access overflow occurs within the object file, then the source file corresponding to the object file may be re-compiled so as to generate an object file having no TOC access overflow, and the object file may be re-linked to generate an executable file of the application. The present disclosure may adopt two-pass compiling and a dual-instruction TOC access in a form of two pieces of instructions that may be generated for TOC entries within which TOC overflows generally occur.

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Номер записи: 41
28-02-2013 дата публикации

Demand-driven analysis of pointers for software program analysis and debugging

Номер: US20130055207A1
Автор: Marcus Peinado, Weidong Cui, Zhilei Xu
Принадлежит: Microsoft Corp

A “Demand-Driven Pointer Analyzer” (DDPA) provides a “demand-driven” field-sensitive pointer analysis process. This process rapidly and accurately identifies alias sets for selected pointers in software modules or programs of any size, including large-scale C/C++ programs such as a complete operating system (OS). The DDPA formulates the pointer analysis task as a Context-Free Language (CFL) reachability problem that operates using a Program Expression Graph (PEG) automatically constructed from the program code. The PEG provides a node and edge-based graph representation of all expressions and assignments in the program and allows the DDPA to rapidly identify aliases for pointers in the program by traversing the graph as a CFL reachability problem to determine pointer alias sets. In various embodiments, the DDPA is also context-sensitive.

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Номер записи: 42
28-02-2013 дата публикации

Compiler for x86-based many-core coprocessors

Номер: US20130055225A1
Автор: Nishkam Ravi, Ozcan Ozturk, Srimat Chakradhar, Tao Bao
Принадлежит: NEC Laboratories America Inc

A system and method for compiling includes, for a parallelizable code portion of an application stored on a computer readable storage medium, determining one or more variables that are to be transferred to and/or from a coprocessor if the parallelizable code portion were to be offloaded. A start location and an end location are determined for at least one of the one or more variables as a size in memory. The parallelizable code portion is transformed by inserting an offload construct around the parallelizable code portion and passing the one or more variables and the size as arguments of the offload construct such that the parallelizable code portion is offloaded to a coprocessor at runtime.

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Номер записи: 43
07-03-2013 дата публикации

Compiler for providing intrinsic supports for vliw pac processors with distributed register files and method thereof

Номер: US20130061022A1
Автор: Chi Bang Kuan, Jenq Kuen Lee
Принадлежит: National Tsing Hua University NTHU

A method for providing intrinsic supports for a VLIW DSP processor with distributed register files comprises the steps of: generating a program representation with cluster information on instructions of the DSP processor, wherein the cluster information is provided by a program with cluster intrinsic coding; identifying data stream operations indicating parallel instruction sequences applied on different data sets in the program representation; identifying data sharing relations indicating data shared by the data stream operations in the program representation; identifying data aggregation relations indicating results aggregated from the data stream operations in the program representation; and performing register allocation for the DSP processor according to the identified data stream operations, the data sharing relations and the data aggregation relations.

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Номер записи: 44
14-03-2013 дата публикации

Determination of Function Purity for Memoization

Номер: US20130067445A1
Автор: Alexander G. Gounares, Charles D. Garrett, Michael D. Noakes, Ying Li
Принадлежит: Concurix Corp

The purity of a function may be determined after examining the performance history of a function and analyzing the conditions under which the function behaves as pure. In some cases, a function may be classified as pure when any side effects are de minimis or are otherwise considered trivial. A control flow graph may also be traversed to identify conditions in which a side effect may occur as well as to classify the side effects as trivial or non-trivial. The function purity may be used to identify functions for memoization. In some embodiments, the purity analysis may be performed by a remote server and communicated to a client device, where the client device may memoize the function.

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Номер записи: 45
21-03-2013 дата публикации

Integrating compiler warnings into a debug session

Номер: US20130074045A1
Автор: Cary L. Bates
Принадлежит: International Business Machines Corp

Integrating compiler warnings into a debug session including: receiving, by a debugger for a debug session of a debuggee from a compiler, compiled source code for execution and compiler warning data describing one or more compiler warnings generated at compile time of the debuggee, each compiler warning resulting from a source code variable statement in the debuggee source code; receiving, by the debugger, a request to evaluate a variable; determining, from the compiler warning data, whether evaluating the variable is dependent upon a source code variable statement resulting in a compiler warning; and, if evaluating the variable is dependent upon a source code variable statement resulting in a compiler warning, returning, by the debugger responsive to the request along with a result of the evaluation, a compiler warning indicator.

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Номер записи: 46
21-03-2013 дата публикации

Method and system for syntax error repair in proframming languages

Номер: US20130074054A1
Автор: Stephen Curtis JOHNSON
Принадлежит: MathWorks Inc

The described embodiments present techniques for recovering from syntax errors. These techniques correct potential errors while preserving the shape of the parse tree, and the specific implementation of the techniques can be automatically generated from the grammar. These techniques may operate by looking back at states associated with previously-received tokens to determine pair matching status, when a synchronizing symbol is received. The techniques can respond to the pair matching status determination by potentially adding a synthesized token or by deleting a token that has already been received. The techniques may use a structure referred to herein as a tuple to assist with the evaluation of the pair matching status. Some of the techniques utilize indentation information to evaluate the pair matching status, while other techniques ignore such information. The described embodiments also include a technique for automatically generating the tuples from a set of grammar rules associated with the parser.

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Номер записи: 47
21-03-2013 дата публикации

Memoizing with Read Only Side Effects

Номер: US20130074056A1
Автор: Garrett Charles D., Gounares Alexander G., LI Ying, Noakes Michael D.
Принадлежит: CONCURIX CORPORATION

A function may be memoized when a side effect is a read only side effect. Provided that the read only side effect does not mutate a memory object, the side effect may be considered as an input to a function for purity and memoization analysis. When a read only side effect may be encountered during memoization analysis, the read only side effect may be treated as an input to a function for memoization analysis. In some cases, such side effects may enable an impure function to behave as a pure function for the purposes of memoization. 1. A method performed by at least one processor , said method comprising:receiving operational results for an application comprising a first function, said operational results comprising inputs to said first function, results returned from said first function, and a state associated with said inputs to said first function;determining that said first side effect comprises reading a first memory object, said state comprising values for said first memory object;determining that said first side effect does not comprise mutating said first memory object;determining that said first function returns a first value given a first condition, said first condition comprising a first set of input parameter values and a first value for said first memory object;causing said first function to be memoized under said first condition.2. The method of further comprising:analyzing said operational results and determining that said first function under said first condition returns a consistent result.3. The method of claim 2 , said consistent result being determined within a statistical certainty.4. The method of claim 2 , said plurality of results being captured during executing an application comprising said first impure function.5. The method of claim 4 , said application being executed under simulated loads.6. The method of claim 4 , said application being executed under actual loads.7. The method of further comprising:determining that said first function ...

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Номер записи: 48
21-03-2013 дата публикации

Selecting Functions for Memoization Analysis

Номер: US20130074057A1
Автор: Garrett Charles D., Gounares Alexander G., LI Ying, Noakes Michael D.
Принадлежит: CONCURIX CORPORATION

A function may be selected for memoization when the function indicates that memoization may result in a performance improvement. Impure functions may be identified and ranked based on operational data, which may include length of execution. A function may be selected from a ranked list and analyzed for memoization. The memoization analysis may include side effect analysis and consistency analysis. In some cases, the optimization process may perform optimization on one function at a time so as to not overburden a running system. 1. A method performed by at least one computer processor , said method comprising:receiving an application, said application comprising a plurality of functions; executing said application and during said executing, collecting initial operational data comprising length of execution for each of said functions;', 'selecting a first function for detailed analysis at least in part based on said operational data;, 'performing an initial analysis of said application, said initial analysis comprising 'receiving additional operational data comprising input parameters and return values;', 'performing a detailed analysis on said first function, said detailed analysis comprisingevaluating said first function to determine said first function is memoizable; andcausing said first function to be memoized.2. The method of claim 1 , said initial operational data comprising call frequency.3. The method of claim 2 , said initial analysis further comprising:creating an execution representation for said application, said execution representation comprising links between functions;4. The method of claim 3 , said selecting said first function further being determined in part based on said execution representation.5. The method of claim 4 , said initial analysis further comprising:applying a score to each of said plurality of functions, said score being determined in part based on said operational data and said execution representation.6. The method of claim 5 , ...

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Номер записи: 49
28-03-2013 дата публикации

Easy creation of mobile payment code

Номер: US20130080324A1
Автор: Ken Reddy, Saulius Zukauskas
Принадлежит: eBay Inc

A user is presented with a first display with parties to a payment transaction and a second display on the same screen, where the user can drag and drop the parties on the first screen to the second screen to create a desired payment flow. A service provider, such as a payment provider, builds code based on the payment flow and zips it into a downloadable file. The user can then easily implement the zipped code into a mobile app that will allow a customer to make a purchase through the app using the payment provider. The zipped code uses a library of payment options offered by the payment provider and allows the user to input custom variables into these options. Code is automatically generated for the user to use based on the user input.

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Номер записи: 50
28-03-2013 дата публикации

APPLICATION PROGRAMMING INTERFACES FOR DATA PARALLEL COMPUTING ON MULTIPLE PROCESSORS

Номер: US20130081066A1
Автор: Begeman Nathaniel, Munshi Aaftab A.
Принадлежит:

A method and an apparatus for a parallel computing program calling APIs (application programming interfaces) in a host processor to perform a data processing task in parallel among compute units are described. The compute units are coupled to the host processor including central processing units (CPUs) and graphic processing units (GPUs). A program object corresponding to a source code for the data processing task is generated in a memory coupled to the host processor according to the API calls. Executable codes for the compute units are generated from the program object according to the API calls to be loaded for concurrent execution among the compute units to perform the data processing task. 1. A parallel computing system comprising:a host processor; 'coupled to the host processor;', 'one or more compute units'} generating a program object corresponding to a source code for a data processing task;', 'generating executable codes from the program object for the one or more compute units; and', 'loading the executable codes to be executed concurrently among the one or more compute units to perform the data processing task., 'a memory coupled to at least one of the host processor and the one or more compute units, wherein a parallel computing program is stored in the memory, the parallel computing program including calls to one or more APIs (application programming interface) for the host processor to perform2. The system of claim 1 , wherein the program object includes a binary code compiled from the source code claim 1 , wherein the binary code includes descriptions of at least one of the one or more compute units.3. The system of claim 2 , wherein the generation of the program object comprises:retrieving the binary code from a precompiled library, wherein the binary codes include the executable codes.4. The system of claim 2 , wherein the generation of the executable codes comprises:compiling the source code into the binary code according to one or more ...

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Номер записи: 51
04-04-2013 дата публикации

Generating compiled code that indicates register liveness

Номер: US20130086548A1
Автор: Michael K. Gschwind, Valentina Salapura
Принадлежит: International Business Machines Corp

Object code is generated from an internal representation that includes a plurality of source operands. The generating includes performing for each source operand in the internal representation determining whether a last use has occurred for the source operand. The determining includes accessing a data flow graph to determine whether all uses of a live range have been emitted. If it is determined that a last use has occurred for the source operand, an architected resource associated with the source operand is marked for last-use indication. A last-use indication is then generated for the architected resource. Instructions and the last-use indications are emitted into the object code.

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Номер записи: 52
04-04-2013 дата публикации

METHODS AND SYSTEMS FOR OPTIMIZING EXECUTION OF A PROGRAM IN AN ENVIRONMENT HAVING SIMULTANEOUSLY PARALLEL AND SERIAL PROCESSING CAPABILITY

Номер: US20130086564A1
Автор: FELCH Andrew C.
Принадлежит: COGNITIVE ELECTRONICS, INC.

An automated method of optimizing execution of a program in a parallel processing environment is disclosed. The program has a plurality of threads and is executable in parallel and serial hardware. The method includes receiving the program at an optimizer and compiling the program to execute in parallel hardware. The execution of the program is observed by the optimizer to identify a subset of memory operations that execute more efficiently on serial hardware than parallel hardware. A subset of memory operations that execute more efficiently on parallel hardware than serial hardware are identified. The program is recompiled so that threads that include memory operations that execute more efficiently on serial hardware than parallel hardware are compiled for serial hardware, and threads that include memory operations that execute more efficiently on parallel hardware than serial hardware are compiled for parallel hardware. Subsequent execution of the program occurs using the recompiled program. 1. An automated method of optimizing execution of a program in a parallel processing environment , the program having a plurality of threads and being executable in parallel and serial hardware , the method comprising:(a) receiving, at an optimizer, the program;(b) compiling the program to execute in parallel hardware upon instruction by the optimizer;(c) executing the program on the parallel hardware upon instruction by the optimizer;(d) the optimizer observing the execution of the program and identifying a subset of memory operations that execute more efficiently on serial hardware than parallel hardware;(e) the optimizer observing the execution of the program and identifying a subset of memory operations that execute more efficiently on parallel hardware than serial hardware; and(f) the optimizer recompiling the program so that threads that include memory operations that execute more efficiently on serial hardware than parallel hardware are compiled for serial hardware, and ...

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Номер записи: 53
11-04-2013 дата публикации

OPTIMIZING JUST-IN-TIME COMPILING FOR A JAVA APPLICATION EXECUTING ON A COMPUTE NODE

Номер: US20130091496A1
Автор: Barsness Eric L., Darrington David L., Randles Amanda, Santosuosso John M.
Принадлежит: INTERNATIONAL BUSINESS MACHINES CORPORATION

Methods, systems, and products are disclosed for optimizing just-in-time (‘JIT’) compiling for a Java application executing on a compute node, the compute node having installed upon it a Java Virtual Machine (‘JVM’) capable of supporting the Java application, that include: identifying, by an application manager, a particular portion of the Java application; assigning, by the application manager, a JIT level to the particular portion of the Java application; and jitting, by the JVM installed on the compute node, the particular portion of the Java application in dependence upon the JIT level assigned to that particular portion of the Java application. 1. A method of optimizing just-in-time (‘JIT’) compiling for a software application executing on a compute node , the compute node having installed upon it a software Virtual Machine (‘VM’) capable of supporting the software application , the method comprising:identifying, by an application manager, a particular portion of the software application; 'establishing the JIT level for the particular portion of the software application in dependence upon a historic JIT profile for the particular portion of the software application and previous execution performance of the particular portion of the software application, wherein the previous execution performance for the particular portion includes a previous performance value and a number of times the particular portion was invoked, wherein the historic JIT profile specifies JIT levels previously used when jitting various portions of the software application; and', 'assigning, by the application manager, a JIT level to the particular portion of the software application, includingjitting, by the VM installed on the compute node, the particular portion of the software application in dependence upon the JIT level assigned to that particular portion of the software application.2. The method of wherein the particular portion of the software application further comprises a generic ...

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Номер записи: 54
18-04-2013 дата публикации

Data prefetching method for distributed hash table dht storage system, node, and system

Номер: US20130097402A1
Автор: Deping Yang, Dong Bao
Принадлежит: Huawei Technologies Co Ltd

Embodiments of the present disclosure provide a data prefetching method, a node, and a system. The method includes: a first storage node receives a read request sent by a client, determines a to-be-prefetched data block and a second storage node where the to-be-prefetched data block resides according to a read data block and a set to-be-prefetched data block threshold, and sends a prefetching request to the second storage node, the prefetching request includes identification information of the to-be-prefetched data block, and the identification information is used to identify the to-be-prefetched data block; and the second storage node reads the to-be-prefetched data block from a disk according to the prefetching request, and stores the to-be-prefetched data block in a local buffer, so that the client reads the to-be-prefetched data block from the local buffer of the second storage node.

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Номер записи: 55
18-04-2013 дата публикации

Computer-Guided Holistic Optimization of MapReduce Applications

Номер: US20130097593A1
Автор: Chakradhar Srimat T., Liu Jun, Ravi Nishkam
Принадлежит: NEC Laboratories America, Inc.

A method for compiler-guided optimization of MapReduce type applications that includes applying transformations and optimizations to Java bytecode of an original application by an instrumenter which carries out static analysis to determine application properties depending on the optimization being performed and provides an output of optimized Java bytecode, and executing the application and analyzing generated trace and feeds information back into the instrumenter by a trace analyzer, the trace analyzer and instrumenter invoking each other iteratively and exchanging information through files. 2. The method of claim 1 , wherein said transformation comprises:making use of a close function in Hadoop, which is invoked once at the end of every map task, said map task invoking a map function multiple times once for each key/value pair in an input data set;{'b': 2', '2, 'moving a body of an original map function to map, a new map function map, that only stores the incoming key/value pairs in a list;'}{'b': '2', 'introducing a new method called map_wrapper which invokes said map on the key/value pairs stored in the list iteratively;'}introducing a loop in said close function, which invokes said map_wrapper and reduce inside a loop;defining a new class called MyOutputCollector, which inherits from a Hadoop's OutputCollector and mimics its behavior by defining a hashtable for storing the key/value pairs; andpassing an object of MyOutputCollector as a parameter to reduce inside said loop, instead of passing an object of OutputCollector as a parameter to reduce inside said loop.3. The method of claim 1 , wherein said automatic compiler transformation accumulates an input data set and then applies a map function to multiple key/value pairs at a time claim 1 , said MapReduce data tiling optimization working correctly when multiple data elements are processed per map-reduce in the inner loop so that intermediate results obtained from data points in said data set are robust.4. The ...

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Номер записи: 56
25-04-2013 дата публикации

THERMAL-AWARE SOURCE CODE COMPILATION

Номер: US20130104110A1
Автор: BATES CARY L., JOHNSON Nicholas P., KING Justin K.
Принадлежит: INTERNATIONAL BUSINESS MACHINES CORPORATION

Thermal-aware source code compilation including: receiving, by a compiler, an identification of a target computing system, the identification of the target computing system specifying temperature sensors that measure temperature of a memory module; compiling the source code into an executable application including inserting in the executable application computer program instructions for thermal-aware execution, the computer program instructions, when executed on the target computing system, carry out the steps of: retrieving temperature measurements of one or more of the target computing system's temperature sensors; determining, in real-time in dependence upon the temperature measurements, whether a memory module is overheated; if a memory module is overheated, entering a thermal-aware execution state including, for each memory allocation in the executable application, allocating memory on a different memory module than the overheated memory module; and upon the temperature sensors indicating the memory module is no longer overheated, exiting the thermal-aware execution state. 1. A method of thermal-aware source code compilation , the method comprising:receiving, by a compiler during compilation of source code, an identification of a target computing system for which the source code is to be compiled, the identification of the target computing system specifying a plurality of temperature sensors, each temperature sensor configured to measure temperature of a memory module of the target computing system;compiling the source code into an executable application including inserting in the executable application computer program instructions for thermal-aware execution, the computer program instructions, when executed on the target computing system, carry out the steps of:retrieving temperature measurements of one or more of the target computing system's temperature sensors;determining, in real-time in dependence upon the temperature measurements, whether a memory ...

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Номер записи: 57
25-04-2013 дата публикации

REAL-TIME TEMPERATURE SENSITIVE MACHINE LEVEL CODE COMPILATION AND EXECUTION

Номер: US20130104111A1
Автор: BATES CARY L., JOHNSON Nicholas P., KING Justin K.
Принадлежит: INTERNATIONAL BUSINESS MACHINES CORPORATION

Methods, apparatuses, and computer program products for real-time temperature sensitive machine level code compilation and execution are provided. Embodiments include compiling and executing, by a just-in-time (JIT) compiler, machine level code; during execution of the machine level code, determining, by the JIT compiler, an execution temperature for the machine level code, including reading temperature measurements from one or more processor temperature sensors; based on the determined execution temperature, identifying, by the JIT compiler, a portion of the machine level code that, when executed, caused temperature measurements of one or more processor temperature sensors to exceed a predetermined threshold temperature; recompiling, by the JIT compiler, the machine level code including modifying the identified portion to generate a new execution temperature that is lower than the previously determined execution temperature; and executing, by the JIT compiler, the recompiled machine level code. 1. A method of real-time temperature sensitive machine level code compilation and execution , the method comprising:compiling and executing, by a just-in-time (JIT) compiler, machine level code;during execution of the machine level code, determining, by the JIT compiler, an execution temperature for the machine level code, including reading temperature measurements from one or more processor temperature sensors;based on the determined execution temperature, identifying, by the JIT compiler, a portion of the machine level code that, when executed, caused temperature measurements of one or more processor temperature sensors to exceed a predetermined threshold temperature;recompiling, by the JIT compiler, the machine level code including modifying the identified portion to generate a new execution temperature that is lower than the previously determined execution temperature; andexecuting, by the JIT compiler, the recompiled machine level code.2. The method of wherein modifying ...

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Номер записи: 58
02-05-2013 дата публикации

Running shift for divide instructions for processing vectors

Номер: US20130111193A1
Автор: Jeffry E. Gonion
Принадлежит: Apple Inc

In the described embodiments, a processor generates a result vector when executing a RunningShiftForDivide1P or RunningShiftForDivide2P instruction. In these embodiments, upon executing a RunningShiftForDivide1P/2P instruction, the processor receives a first input vector and a second input vector. The processor then records a base value from an element at a key element position in the first input vector. Next, when generating the result vector, for each active element in the result vector to the right of the key element position, the processor generates a shifted base value using shift values from the second input vector. The processor then corrects the shifted base value when a predetermined condition is met. Next, the processor sets the element of the result vector equal to the shifted base value.

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Номер записи: 59
02-05-2013 дата публикации

Logical repartitioning in design compiler

Номер: US20130111424A1
Автор: Hani Hasan Mustafa Saleh, Robert D. Kenney, Sreevathsa Ramachandra
Принадлежит: Apple Inc

During a pop phase of hierarchical repartitioning of an IC design, all cells within a current hierarchy may be identified, the list of cells may be ungrouped to dissolve the current hierarchy, one or more specified cells may be removed from the list of cells, where the specified one or more cells are to be moved to a different hierarchy, and the new list of cells without the specified one or more cells may be re-grouped, to re-form the previously dissolved hierarchy. During a push phase of the hierarchical repartitioning, all cells within the next lower-level hierarchy may be identified, the identified list of cells may be ungrouped to dissolve that hierarchy, the specified one or more cells may be added to the identified list of cells, and the new list of cells that includes the specified one or more cells may be grouped to reform the previously dissolved hierarchy.

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Номер записи: 60
02-05-2013 дата публикации

Reducing object size by class type encoding of data

Номер: US20130111435A1
Автор: Thomas W. Rudwick, III
Принадлежит: Apple Inc

A system and method for representing a state of an object by the object's type. A method includes receiving a request to change a state of an object. In various embodiments, the object may correspond to an instance of a class. Responsive to the request, the method includes changing the type of the object from a first type that corresponds to the first state to a second type that corresponds to the second state. There is no explicit representation of the state of the object included in the object. Rather, the object type is used to represent its state. Changing an object's type includes creation of a new object that corresponds to the second type, and storing the new object at the same location in memory wherein the original object was stored. A memory allocation is not performed as part of the creation of the new object.

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Номер записи: 61
02-05-2013 дата публикации

Memory management for closures

Номер: US20130111446A1
Автор: Christopher Arthur Lattner, Fariborz Jahanian, Gerald Blaine Garst, JR., William Bumgarner
Принадлежит: Apple Inc

Methods, software media, compilers and programming techniques are described for creating copyable stack-based closures, such as a block, for languages which allocate automatic or local variables on a stack memory structure. In one exemplary method, a data structure of the block is first written to the stack memory structure, and this may be the automatic default operation, at run-time, for the block; then, a block copy instruction, added explicitly (in one embodiment) by a programmer during creation of the block, is executed to copy the block to a heap memory structure. The block includes a function pointer that references a function which uses data in the block.

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Номер записи: 62
02-05-2013 дата публикации

MODULAR AND OPEN PLATFORM IMAGE CAPTURE DEVICES AND RELATED METHODS

Номер: US20130111464A1
Автор: Markas Tassos, McNamer Michael, Seltmann Heinz
Принадлежит: 3DMedia Corporation

Disclosed herein are modular and open platform systems and related methods. In accordance with an aspect, a system may comprise multiple hardware subsystems configured to be selectively and operatively connected together. The system may include a main software module comprising multiple software sub-modules that each corresponds to one of the hardware subsystems. Each hardware subsystem may be configured to implement a target function. The system may also include one or more processors and memory configured to detect operative connection of one of the hardware subsystems. Further, the processor and memory may dynamically load the software sub-module that corresponds to the connected hardware subsystem into the main software module, and integrate the main software module with the loaded software sub-module for performing the target function associated with the corresponding hardware subsystem in response to detection of the operative connection. 1. A system comprising a plurality of hardware subsystems configured to be selectively and operatively connected together , the system comprising:a main software module comprising a plurality of software sub-modules that each corresponds to one of the hardware subsystems, wherein each hardware subsystem is configured to implement a target function; and detect operative connection of one of the hardware subsystems; and', dynamically load the software sub-module that corresponds to the connected hardware subsystem into the main software module; and', 'integrate the main software module with the loaded software sub-module for performing the target function associated with the corresponding hardware subsystem., 'in response to detection of the operative connection], 'at least a processor and memory configured to2. The system of claim 1 , wherein each hardware subsystem is configured to be interchanged by a different one of the hardware subsystems for modifying one or more functions of the system.3. The system of claim 1 , wherein ...

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Номер записи: 63
09-05-2013 дата публикации

Automatic solver selection

Номер: US20130116988A1
Автор: Fu Zhang, Murali K. Yeddanapudi, Pieter J. Mosterman, Zhi HAN
Принадлежит: MathWorks Inc

A method, performed by a computer device, may include receiving a request to automatically select a solver for a simulation of an executable graphical model, determining a Jacobian matrix for the executable graphical model, calculating a stiffness of the executable graphical model based on the determined Jacobian matrix, and determining whether the calculated stiffness is greater than a stiffness threshold. The method may further include automatically selecting an implicit solver as the solver for the simulation, in response to determining that the calculated stiffness is greater than the stiffness threshold, automatically selecting an explicit solver as the solver for the simulation, in response to determining that the calculated stiffness is not greater than the stiffness threshold, and performing the simulation using the selected solver.

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Номер записи: 64
09-05-2013 дата публикации

Reconfigurable instruction encoding method and processor architecture

Номер: US20130117536A1
Автор: Ching-Hsiang Chuang, Huang-Lun Lin, Shui-An Wen
Принадлежит: Industrial Technology Research Institute ITRI

A reconfigurable instruction encoding method includes the followings. An instruction distribution of an application is counted, and multiple instruction pairs with higher utilization rates are accordingly found. Multiple instructions of the instruction pairs are duplicately encoded according to multiple reserved sections of an original instruction table, so that the instructions have corresponding reconfigured codes and a reconfigured instruction table extended from the original instruction table and including the reconfigured codes is obtained. A compiler is utilized to generate multiple machine codes according to the reconfigured instruction table and consecutive execution instructions. Hamming distance of the machine codes corresponding to the reconfigured instruction table and the execution instructions are not longer than Hamming distance of the machine codes generated according to the original instruction table and the execution instructions.

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Номер записи: 65
09-05-2013 дата публикации

Simultaneously targeting multiple homogeneous and heterogeneous runtime environments

Номер: US20130117733A1
Автор: Donald F. Box, Fabian O. Winternitz, Haroon Ahmed, Sadik Gokhan Caglar
Принадлежит: Microsoft Corp

A single software project in an integrated development environment (IDE) may be built for multiple target environments in a single build episode. Multiple different output artifacts may be generated by the build process for each of the target environments. The output artifacts are then deployed to the target environments, which may be homogeneous or heterogeneous environments. The same source project may be used to generate multiple output artifacts for the same target environment.

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Номер записи: 66
16-05-2013 дата публикации

Method For Estimating Resource Consumption In The Generation Of A Control Device Program Code

Номер: US20130125087A1
Автор: Wolfgang Trautmann
Принадлежит: Individual

A method for estimating a resource consumption of storage space and/or of required runtime of a control device program code to be generated for a control program, whereby the functionality of the control program is given in an executable model. The model has a function with first functional magnitudes and first information associated with the first functional magnitudes and optimization parameters for optimizing a code generator. A program code representation is generated for part of the model comprising the function by the code generator taking into account first values of the optimization parameters. An estimation unit comprises a resource model with hardware parameters. An estimated value for the storage space requirement is determined for the control device program code and/or a runtime estimated value is determined for the control device program code by the estimation unit taking into account the hardware parameters and based on the program code representation.

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Номер записи: 67
23-05-2013 дата публикации

APPLICATON INTERFACE ON MULTIPLE PROCESSORS

Номер: US20130132934A1
Автор: Munshi Aaftab AbdulLatif, Sandmel Jeremy
Принадлежит: Apple Inc.

A method and an apparatus that execute a parallel computing program in a programming language for a parallel computing architecture are described. The parallel computing program is stored in memory in a system with parallel processors. The parallel computing program is stored in a memory to allocate threads between a host processor and a GPU. The programming language includes an API to allow an application to make calls using the API to allocate execution of the threads between the host processor and the GPU. The programming language includes host function data tokens for host functions performed in the host processor and kernel function data tokens for compute kernel functions performed in one or more compute processors, e.g. GPUs or CPUs, separate from the host processor. 1. A programming language system for a parallel computing architecture , the programming language system implemented by a parallel computing program stored in memory in a system having parallel processors , the system comprising:a host processor;a graphics processing unit (GPU) coupled to the host processor;a memory coupled to at least one of the host processor and the GPU, the parallel computing program being stored in the memory to allocate threads between the host processor and the GPU and wherein the programming language includes an API to allow an application to make calls using the API to allocate execution of the threads between the host processor and the GPU.2. The programming language system of claim 1 , wherein the API is called by the application asynchronously.3. The programming language system of wherein the GPU comprises graphics texture mapping hardware to map texture maps onto surfaces to be displayed on a display device.4. The programming language system of claim 1 , further comprising:a central processing unit (CPU) coupled to the host processor, wherein the threads are allocated to be executed in the CPU if the GPU is busy executing graphics processing threads.5. The ...

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Номер записи: 68
30-05-2013 дата публикации

OPTIMIZATION METHOD FOR COMPILER, OPTIMIZER FOR A COMPILER AND STORAGE MEDIUM STORING OPTIMIZING CODE

Номер: US20130139135A1
Автор: Badea Dragos, Ditu Bogdan F.
Принадлежит: Freescale Semiconductor ,Inc.

The invention pertains to an optimization method for a compiler, comprising providing a model of inter-operand constraints of physical registers of a target-platform of a compilation; and a) providing an intermediate representation of a source code using virtual registers; b) grouping the virtual registers of the intermediate representation based on the model of inter-operand constraints into two or more groups, each group comprising at least one virtual register; c) if for at least one group at least one interference of virtual registers within the group occurs, amending the intermediate representation to resolve at least one interference and jumping to step b); otherwise d) providing a representation of a group interference graph of interferences between the groups; and e) allocating virtual registers to physical registers using a coloring scheme on the representation of the group interference graph. The invention also refers to a corresponding optimizer for a compiler and a computer-readable storage medium storing optimizing code. 1. An optimization method for a compiler , comprising:providing a model of inter-operand constraints of physical registers of a target-platform of a compilation; anda) providing an intermediate representation of a source code using virtual registers;b) grouping the virtual registers of the intermediate representation based on the model of inter-operand constraints into two or more groups, each group comprising at least one virtual register;c) if for at least one group at least one interference of virtual registers within the group occurs, amending the intermediate representation to resolve at least one interference and jumping to step b); otherwised) providing a representation of a group interference graph of interferences between the groups; ande) allocating virtual registers to physical registers using a coloring scheme on the representation of the group interference graph.2. The optimization method of claim 1 , wherein b) further ...

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Номер записи: 69
06-06-2013 дата публикации

Systems and methods for hardware-assisted type checking

Номер: US20130145216A1
Автор: Emily Fortuna, Luis Ceze, Owen Anderson, Susan J. Eggers
Принадлежит: University of Washington Center for Commercialization

Devices and methods of providing hardware support for dynamic type checking are provided. In some embodiments, a processor includes a type check register and support for one or more checked load instructions. In some embodiments, normal load instructions are replaced by a compiler with the checked load instructions. In some embodiments, to perform a checked load, an error handler instruction location is stored in the type check register, and a type tag operand is compared to a type tag stored in the loaded memory location. If the comparison succeeds, execution may proceed normally. If the comparison fails, execution may be transferred to the error handler instruction. In some embodiments, type prediction is performed to determine whether a checked load instruction is likely to fail.

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Номер записи: 70
06-06-2013 дата публикации

FIRMWARE EXTENSION METHOD AND FIRMWARE BUILDER

Номер: US20130145353A1
Автор: TSAI Chien-Liang, TSAI Chung-Yen, YAU Wei-Guan
Принадлежит: MEDIATEK INC.

A firmware extension method is provided, particularly adaptable for an embedded system. Firstly, a baseline firmware image is provided with a header file. Secondly, an extension firmware image is generated based on the header file, comprising one or more extended functions. Thereafter, a callback table is generated, comprising pointers pointing to entries of the extended functions in the extension firmware image. Further, memory allocation parameters are provided. The memory allocation parameters comprise a base address where the extension firmware image starts. The baseline firmware image, the extension firmware image and the callback table are then merged to generate a merged firmware image based on the memory allocation parameters. 1. A firmware extension method executed by a processor in an embedded system , comprising:providing a baseline firmware image and a header file associated with the baseline firmware image;generating an extension firmware image based on the header file, comprising one or more extended functions;generating a callback table comprising pointers pointing to entries of the extended functions in the extension firmware image; andproviding memory allocation parameters comprising a base address where the extension firmware image starts; andmerging the baseline firmware image, the extension firmware image and the callback table to generate a merged firmware image based on the memory allocation parameters.2. The firmware extension method as claimed in claim 1 , wherein the step of merging comprises storing the entry of the callback table into an extension pointer.3. The firmware extension method as claimed in claim 2 , wherein:the callback table comprises an enablement flag indicating whether the extended functions are enabled; andthe baseline firmware image is programmed to conditionally load and execute the extended functions through the callback table based on the extension pointer and the enablement flag.4. The firmware extension method as ...

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Номер записи: 71
06-06-2013 дата публикации

SHARING AND PERSISTING CODE CACHES

Номер: US20130145354A1
Автор: BRUENING Derek, KIRIANSKY Vladimir L.
Принадлежит: VMWARE, INC.

Computer code from an application program comprising a plurality of modules that each comprise a separately loadable file is code cached in a shared and persistent caching system. A shared code caching engine receives native code comprising at least a portion of a single module of the application program, and stores runtime data corresponding to the native code in a cache data file in the non-volatile memory. The engine then converts cache data file into a code cache file and enables the code cache file to be pre-loaded as a runtime code cache. These steps are repeated to store a plurality of separate code cache files at different locations in non-volatile memory. 1. An apparatus for caching computer code from an application program comprising a plurality of modules that each comprise a separately loadable file , the apparatus comprising:(a) a volatile memory;(b) a non-volatile memory coupled to the volatile memory via a first bus;(c) a processor coupled to the non-volatile memory via a second bus;(d) an address bus connecting the processor and the non-volatile memory for delivering code request signals from the processor to the non-volatile memory;(e) means responsive to the code request signals for transferring requested code from the non-volatile memory to the processor if the requested code is stored in cache code files in the non-volatile memory;(f) means responsive to the code request signal for transferring the requested code from the volatile memory to the processor via the non-volatile memory if the requested code is not stored in cache code files in non-volatile memory;(g) a shared code caching engine coupled to receive executed native code output from the volatile memory via the first bus, the executed native code comprising at least a portion of a module of the application program, and the shared code caching engine comprising code instruction sets for:(i) storing data corresponding to the native code in a plurality of cache data files at different ...

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Номер записи: 72
13-06-2013 дата публикации

Securing microprocessors against information leakage and physical tampering

Номер: US20130151865A1
Автор: Csaba Andras Moritz, Kristopher Carver, Saurabh Chheda
Принадлежит: BlueRISC Inc

A processor system comprising: performing a compilation process on a computer program; encoding an instruction with a selected encoding; encoding the security mutation information in an instruction set architecture of a processor; and executing a compiled computer program in the processor using an added mutation instruction, wherein executing comprises executing a mutation instruction to enable decoding another instruction. A processor system with a random instruction encoding and randomized execution, providing effective defense against offline and runtime security attacks including software and hardware reverse engineering, invasive microprobing, fault injection, and high-order differential and electromagnetic power analysis.

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Номер записи: 73
13-06-2013 дата публикации

Warning of register and storage area assignment errors

Номер: US20130152049A1
Автор: Andrew Wright, Brenda Hawkins, Daniel J. Rivett, Stephen J. Burghard
Принадлежит: International Business Machines Corp

A system for tracking register and/or storage area assignments and warning a programmer of potential assignment errors. More specifically, the system tracks programmer assignments to registers and storage areas and determines if a register or storage area has been modified prior to a call to a program or process external to the source code being examined. The system notes whether a modified register or storage area is restored to its original value subsequent to the external call. If the register or storage area has not been restored, the system displays a warning of a possible assignment error.

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Номер записи: 74
13-06-2013 дата публикации

Method for Translating a Control Program in an Automation Language into an Intermediate Language

Номер: US20130152058A1
Автор: Axel Schmuck
Принадлежит: SIEMENS AG

A method for translating a control program in an automation language into an intermediate language, wherein the control program comprises a plurality of basic operations that are each mapped to a respective sequence of instructions in the intermediate language, where a specification database comprising a respective transformation rule for at least a multiplicity of basic operations in the automation language is utilizable in a control program is accessed to translate the control program into the intermediate language, the transformation rule allows an input parameter list to be processed, and if the transformation rule is called with an input parameter list having a plurality of input parameters, unlimited in the transformation rule, the transformation rule defines the inclusion of a further transformation rule. The further transformation rule defines a recursive inclusion of the further transformation rule according to a number of the input parameters.

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Номер записи: 75
13-06-2013 дата публикации

DUAL MODE EVALUATION FOR PROGRAMS CONTAINING RECURSIVE COMPUTATION

Номер: US20130152060A1
Автор: SWEENEY Timothy Dean
Принадлежит: EPIC GAMES, INC.

A dual evaluation mode method for use with computer software that includes the acts of determining, for certain functions and expressions within input computer code, whether each function and expression may have any recursive dependencies, generating eager evaluation mode executable code for one or more elements of the input computer code based on the act of determining and providing both eager evaluation mode executable code and non-eager evaluation mode executable code to runtime software that supports both eager and non-eager evaluation modes. 1. A dual evaluation mode method comprising:determining, for certain functions and expressions within input computer code, whether each function and expression may have any recursive dependencies;generating, using one or more computer processors, eager evaluation mode executable code for one or more elements of the input computer code based on the act of determining; andproviding both eager evaluation mode executable code and non-eager evaluation mode executable code to runtime software that supports both eager and non-eager evaluation modes.2. The method of further comprising:generating non-eager evaluation mode executable code for one or more of the one or more elements of the input computer code.3. The method of wherein non-eager evaluation mode executable code is generated for every function in the input computer code.4. The method of wherein the runtime software invokes the eager evaluation executable code for one or more of the elements rather than non-eager evaluation mode executable code.5. The method of wherein the runtime software invokes the eager evaluation executable code based on a determination that doing so will generate observably equivalent results to the non-eager evaluation executable code for the element.6. The method of further comprising generating versions of executable code using different combinations of thunks and values in its parameters and program environment.7. The method of further comprising ...

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Номер записи: 76
13-06-2013 дата публикации

SOFTWARE ANALYSIS FRAMEWORK

Номер: US20130152062A1
Автор: Rioux Christien
Принадлежит: Veracode, Inc.

Presently described is a decompilation method of operation and system for parsing executable code, identifying and recursively modeling data flows, identifying and recursively modeling control flow, and iteratively refining these models to provide a complete model at the nanocode level. The nanocode decompiler may be used to determine if flaws, security vulnerabilities, or general quality issues exist in the code. The nanocode decompiler outputs in a standardized, human-readable intermediate representation (IR) designed for automated or scripted analysis and reporting. Reports may take the form of a computer annotated and/or partially human annotated nanocode listing in the above-described IR. Annotations may include plain English statements regarding flaws and pointers to badly constructed data structures, unchecked buffers, malicious embedded code or “trap doors,” and the like. Annotations may be generated through a scripted analysis process or by means of an expert-enhanced, quasi-autonomous system. 140-. (canceled)41. A system for facilitating the analysis of software code , the system comprising: means for separating the executable software code into a code section and a data section;', 'means for generating one or more signature files; and', 'means for comparing the code section of the executable software code to the one or more signature files; and, 'a decompiler and analysis subsystem operating on a processor, the decompiler and analysis subsystem comprising;'}a graphical user interface rendered on a display device, the graphical user interface for (i) accepting user commands related to the modeling and analysis of the executable software code and (ii) displaying results of the comparison on the display device.42. The system of wherein the decompiler and analysis subsystem further comprises means for creating an intermediate representation of the executable software code comprising a complete model of the executable software code based on a data section and ...

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Номер записи: 77
13-06-2013 дата публикации

Interactive analysis of a security specification

Номер: US20130152205A1
Автор: Marco Pistoia, Omer Tripp, Takaaki Tateishi
Принадлежит: International Business Machines Corp

Analyzing a security specification. An embodiment can include identifying a downgrader in a computer program under test. Via a processor, testing on the downgrader can be performed in a first level of analysis. Responsive to the downgrader not passing the testing performed in the first level of analysis, a counter example for the downgrader can be automatically synthesized. Further, a test unit can be created for the downgrader using the counter example as an input parameter to the downgrader. The test unit can be executed to perform testing on the downgrader in a second level of analysis. Responsive to the downgrader passing the testing performed in the second level of analysis, a user can be prompted to simplify a model of the downgrader.

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Номер записи: 78
20-06-2013 дата публикации

Language Translation Using Preprocessor Macros

Номер: US20130159982A1
Автор: Apostolos Lerios
Принадлежит: Individual

A method is provided for providing consistent logical code across specific programming languages. The method incorporates preprocessor macros in a source computer program code to generate a program control flow. The preprocessor macros can be used to describe program control flow in the source programming language for execution in the source computer program code. The preprocessor macros can also be used to generate control flow objects representing the control flow, which converts the source computer program code into a general language representation. The general language representation when executed is used to output computer programming code in specific programming languages representing the same logical code as that of the source computer program code.

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Номер записи: 79
27-06-2013 дата публикации

SYSTEM, APPARATUS, AND METHOD FOR DISTRIBUTED COMPILATION OF APPLICATIONS

Номер: US20130167127A1
Автор: CHANG Kyung-ah, GU Bon-Cheol, Jung Eun-Sung
Принадлежит: SAMSUNG ELECTRONICS CO., LTD.

Provided is a system for distributed multi-stage compilation of application programs in a cloud environment. The system includes a source apparatus to generate a compilation order in which source representation of an application program is compiled, and a destination apparatus to receive a compiled representation created by compiling at least a portion of the source representation according to the compilation order. 1. A distributed compilation system for an application program , the distributed compilation system comprising:a source apparatus configured to generate a compilation order in which a source representation of the application program is to be compiled; anda destination apparatus configured to receive a compiled representation created by compiling at least a portion of the source representation according to the compilation order, and to install the application program based on the compiled representation.2. The distributed compilation system of claim 1 , wherein the compiled representation comprises a compilation group of the source representation allocated to the source apparatus and compiled by the source apparatus according to the compilation order.3. The distributed compilation system of claim 1 , further comprising at least one intermediate apparatus configured to compile a compilation group allocated to the intermediate apparatus according to the compilation order claim 1 , and to transmit the result of the compilation to a next apparatus claim 1 ,wherein the compiled representation comprises the result of compilation by the intermediate apparatus.4. The distributed compilation system of claim 1 , wherein the source apparatus creates metadata comprising profile information of the destination apparatus claim 1 , the profile information comprising at least one of CPU information claim 1 , OS information claim 1 , memory information claim 1 , and library information claim 1 , of the destination apparatus.5. The distributed compilation system of claim 4 ...

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Номер записи: 80
27-06-2013 дата публикации

Systems and methods for demarcating information related to one or more blocks in an application

Номер: US20130167129A1
Автор: Balkrishna Prasad, Murali Krishna Emani, Sudeep MALLICK
Принадлежит: Infosys Ltd

The invention relates to a system and method for demarcating information related to one or more blocks in an application source code. This invention provides a means to annotate block information in the source code. It parses the application source code to generate an abstract syntax tree and instruments the source code to capture information related to the one or more blocks generated at the time of dynamic analysis of the application. The information related to the one or more blocks are stored in Hash Map and based on this information the abstract syntax tree is modified to add the information related to the one or more blocks and inserting this information in the application source code.

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Номер записи: 81
04-07-2013 дата публикации

Control flow analysis

Номер: US20130174127A1
Автор: Feng Liu, Hong Chang Lin, Qi Liang, Qin Yue Chen
Принадлежит: International Business Machines Corp

A method for control flow analysis according to an embodiment of the present invention includes: acquiring an original function call tree of a program, wherein nodes of the original function call tree represent functions and a parent/child relation between the nodes represents a calling relation; generating a corresponding function dominator tree from the calling relation, wherein nodes of the function dominator tree represent the functions and a parent/child relation between the nodes represents a dominator relation, wherein a first function dominates a second function if all the invocations to the second function are originated by the first function; and simplifying the original function call tree according to the function dominator tree so as to obtain a simplified function call tree. According to an embodiment of the present invention, the function call tree for control flow analysis can be simplified.

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Номер записи: 82
04-07-2013 дата публикации

Systems and methods for data brick creation and use

Номер: US20130174132A1
Автор: Arnold S. Santos, Joe M. Fenicle, Krishna K. Lingamneni, Martin D. Lantry, Ron Sexton
Принадлежит: American Express Travel Related Services Co Inc

Data Brick is a state of the art solution to access the data through high speed data access mechanism that is exceptionally fast and is associated with low CPU consumption cost. The Data Brick stores relatively static reference data in the form of a programming language Load Module. The Load module contains the data can be launched into the application program memory and this data can be accessed very efficiently in a programming language program. Static application data that is accessed by multiple applications in a mainframe Batch environment is a prime candidate for the Data Brick.

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Номер записи: 83
04-07-2013 дата публикации

System and Method for Stability Guarantees in Concurrent Software

Номер: US20130174134A1
Автор: Farrar Daniel James
Принадлежит:

A flexible, extensible and efficient compile-time mechanism that leverages native high-level application programming language constructs (e.g., the template and macro features of C++), thus minimizing any programmer or a software developer learning curve and eliminating the need for programming tool (e.g., compiler) changes, to identify and control aspects of shared resource access in concurrent software at the time of source code compilation. 1. A computer-implemented method for ensuring , during compilation , that a body of multi-threaded application source code is not susceptible to deadlock , the method comprising:identifying a plurality of shared resources within the body of multi-threaded application source code;identifying a plurality of access control mechanisms for managing access to the plurality of shared resources;tracking, on a detection of an object entering scope, one or more invocations of the plurality of access control mechanisms, yielding a shared resource acquisition pattern;tracking, on a detection of the object leaving scope, one or more invocations of the plurality of access control mechanisms, yielding a shared resource release pattern; andgenerating an alert when the shared resource acquisition pattern differs, beyond a predetermined threshold, from the shared resource release pattern.2. The method of claim 1 , wherein the plurality of access control mechanisms encompass operation of one or more of a lock claim 1 , a mutex claim 1 , a semaphore claim 1 , a monitor claim 1 , and a latch.3. The method of claim 1 , wherein the tracking steps and the generating step employ a type system of a programming language of the multi-threaded application source code.4. The method of claim 1 , wherein the tracking steps and the generating step employ one or more of a template and a macro.5. The method of claim 1 , wherein the tracking steps and the generating step are realized through a conventional application source code development facility.6. The ...

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Номер записи: 84
11-07-2013 дата публикации

Adaptive Diversity for Compressible Return Oriented Programs

Номер: US20130179869A1
Автор: Little Michael W., VAN DEN BERG Eric
Принадлежит: TELCORDIA TECHNOLOGIES, INC.

A method of transforming return oriented programming executables into functionally equivalent yet different forms with specific structural and/or functional characteristics that can assist in the use of such executables. A method automatically biases the structural and/or functional diversity of the return oriented programming software executables to achieve specific program representation objectives while preserving the programmatic capabilities of the original executable. 1. A method of transforming return oriented programming executables into functionally equivalent forms comprising:providing a target runtime environment;creating a return oriented program instruction library comprising a collection of code fragments which end in a ‘return’ instruction from the target runtime environment;searching different code fragments in the target runtime environment until a predetermined quantity of instruction sequences are found;diversifying an input program and/or an output of a return oriented mapper to provide an intermediate program or a result program;mapping the input program by the mapper resulting in an intermediate program or a result program encoded for a consumer; andestablishing an entropy model representing the consumer usage of the result program to be interpreted by the mapper to guide mapping.2. The method of further comprising performing a quality test on the intermediate program.3. The method of claim 2 , where if the quality test is successful claim 2 , the intermediate program becomes the result program.4. The method of claim 2 , where if the quality test is unsuccessful claim 2 , performing subsequent quality tests taking into account the results of the prior quality test.5. The method of claim 1 , whereby the entropy model is a random model.6. The method of claim 1 , whereby the mapper is a random function.7. The method of claim 1 , whereby the intermediate program is used as a context by the entropy model.8. The method of claim 1 , whereby the ...

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Номер записи: 85
18-07-2013 дата публикации

SYSTEMS AND METHODS FOR SOFTWARE INSTRUCTION TRANSLATION FROM A HIGH-LEVEL LANGUAGE TO A SPECIALIZED INSTRUCTION SET

Номер: US20130185703A1
Автор: Davis Alan L., HUNG Ching-Yu, Jayaraj Ajay, NAGURNE James, Phipps Mel Alan, SANKARAN Jadadeesh
Принадлежит: TEXAS INSTRUMENTS INCORPORATED

A computer system includes a processor and program storage coupled to the processor. The program storage stores a software instruction translator that, when executed by the processor, is configured to receive source code and translate the source code to a low-level language. The source code is restricted to a subset of a high-level language and the low-level language is a specialized instruction set. Each statement of the subset of the high-level language directly maps to an instruction of the low-level language. 1. A computer system comprising:a processor; andprogram storage coupled to said processor;wherein the program storage stores a software instruction translator that, when executed by the processor, is configured to receive source code, the source code restricted to a subset of a high-level language, and translate the source code to a low-level language;wherein the low-level language comprises a specialized instruction set; andwherein each statement of the subset of the high-level language directly maps to an instruction of the low-level language.2. The computer system of wherein the subset of the high-level language comprises a definition of a type that is not built into the standard high-level language claim 1 , but that adheres to the semantics of the high-level language.3. The computer system of wherein the type corresponds to a vector data type on which the specialized instruction set operates.4. The computer system of wherein the definition of the type overloads an operator of the high-level language.5. The computer system of wherein the definition of the type corresponds to an addressing scheme of the specialized instruction set.6. The computer system of wherein the software instruction translator requires that the source code follow a nested-loop control structure.7. The computer system of wherein the software instruction translator is configured to generate an error message in response to an attempt to translate an otherwise-valid statement of the ...

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Номер записи: 86
18-07-2013 дата публикации

PROVIDING PERFORMANCE TUNED VERSIONS OF COMPILED CODE TO A CPU IN A SYSTEM OF HETEROGENEOUS CORES

Номер: US20130185704A1
Автор: Kuesel Jamie R., Kupferschmidt Mark G., Schardt Paul E., Shearer Robert A.
Принадлежит: INTERNATIONAL BUSINESS MACHINES CORPORATION

A compiler may optimize source code and any referenced libraries to execute on a plurality of different processor architecture implementations. For example, if a compute node has three different types of processors with three different architecture implementations, the compiler may compile the source code and generate three versions of object code where each version is optimized for one of the three different processor types. After compiling the source code, the resultant executable code may contain the necessary information for selecting between the three versions. For example, when a program loader assigns the executable code to the processor, the system determines the processor's type and ensures only the optimized version that corresponds to that type is executed. Thus, the operating system is free to assign the executable code to any processor based on, for example, the current status of the processor (i.e., whether its CPU is being fully utilized) and still enjoy the benefits of executing code that is optimized for whichever processor is assigned the executable code. 1. A method of selecting optimized code to be executed in a computing system comprising a first processor and a second processor , comprising:loading executable code to be executed by one of the first and second processors, wherein the executable code is based on source code,wherein at least a portion of the source code is optimized by a compiler to generate both a first compiled code portion based on an architecture implementation of the first processor and a second compiled code portion based on an architecture implementation of the second processor, wherein the respective architecture implementations of the first and second processors are different;upon determining that the executable code is assigned to the first processor, executing the first compiled code portion and not the second compiled code portion on the first processor; andupon determining that the executable code is assigned to the ...

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Номер записи: 87
25-07-2013 дата публикации

Preventing classification of object contextual information

Номер: US20130188828A1
Автор: Shay Bushinsky, Shmuel Ur
Принадлежит: EMPIRE TECHNOLOGY DEVELOPMENT LLC

Technology is disclosed for preventing classification of objects, e.g., in an augmented reality system. The technology can identify a set of objects to be classified, determine whether context information for one or more objects in the identified set of objects to be classified is identified as not to be employed during classifiation, and during classification of two different objects, include context information for one object but not the other.

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Номер записи: 88
25-07-2013 дата публикации

Optimisation of loops and data flow sections

Номер: US20130191817A1
Автор: Vorbach Martin
Принадлежит: HYPERION CORE, INC.

The present invention relates to a method for compiling code for a multi-core processor, comprising: detecting and optimizing a loop, partitioning the loop into partitions executable and mappable on physical hardware with optimal instruction level parallelism, optimizing the loop iterations and/or loop counter for ideal mapping on hardware, chaining the loop partitions generating a list representing the execution sequence of the partitions. 1. A method for compiling code for a multi-core processor , comprising:detecting and optimizing a loop,partitioning the loop into partitions executable and mappable on physical hardware with optimal instruction level parallelism,optimizing the loop iterations and/or loop counter for ideal mapping on hardware,chaining the loop partitionsgenerating a list representing the execution sequence of the partitions.2. A method for compiling code for a multi-core processor , comprising:detecting and optimizing dataflow sections of the code,partitioning the dataflow sections into partitions executable and mappable on physical hardware with optimal instruction level parallelism,optimizing the outer control structure of the dataflow sections for ideal mapping on hardware,chaining the dataflow partitionsgenerating a list representing the execution sequence of the partitions.3. A method for operating a processor comprising:scheduling by a first scheduler the available processing hardware resource,providing a thread and/or microthread a list of respectively allocated hardware resources,scheduling and mapping partitioned dataflow code onto the allocated hardware resources, andconfiguring the interconnection between the hardware resources. The present invention relates to data processing in general and to data processing architecture in particular.Energy efficient, high speed data processing is desirable for any processing device. This holds for all devices wherein data are processed such as cell phones, cameras, hand held computers, laptops, ...

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Номер записи: 89
01-08-2013 дата публикации

MAPPING AND FORMATTING INPUT COMMANDS TO A THIRD PARTY PROTOCOL

Номер: US20130198726A1
Автор: Smith Marjorie Lynne, Smith Mark Ethard
Принадлежит: AMX, LLC

A method and apparatus of translating and mapping received commands between operating system languages and/or protocol-based languages. One example method may provide receiving an action initiated by an external source, such as a person or automated action selection operation. The method may also include identifying the action as a predetermined command of a first computer operating language stored in a memory and mapping the predetermined command to a corresponding protocol command of a different computer operating language, and executing the corresponding protocol command after the mapping operation. 1. A method of performing a computer language conversion , the method comprising:receiving at least one action initiated by an external source;identifying via a processor the at least one action as a predetermined command of a first computer operating language stored in a memory;mapping the predetermined command of the first computer operating language to a corresponding protocol command of a different computer operating language; andexecuting the corresponding protocol command.2. The method of claim 1 , wherein the at least one action provided by the external source is at least one of a power-on input action and a power-off input action performed on a device corresponding to the external source.3. The method of claim 1 , wherein the mapping the predetermined command of the first computer operating language to a corresponding protocol command of a different computer operating language comprises:retrieving a translation table from a database,matching the at least one action to the predetermined command stored in the translation table,parsing at least one character string from the at least one action, andextracting a numeric value of the at least one character string based on the parsing operation.4. The method of claim 3 , wherein the parsing the at least one character string of the at least one action comprises parsing the numeric value and identifying the numeric ...

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Номер записи: 90
08-08-2013 дата публикации

Any-To-Any System For Doing Computing

Номер: US20130205283A1
Автор: Peter D. Warren
Принадлежит: Individual

Methods for constructing an Any-to-Any data machine (consisting of Any-to-Any data components and their environmental requirements) and an Any-to-Any code machine (consisting of Any-to-Any code components and their environmental requirements) and relating them together so that they harmoniously interact and so that the data Any-to-Any machine controls and is also acted upon by the code Any-to-Any machine so as to produce an Any-to-Any system that transforms data in a manner that is useful and which is analogous to the harmonious interaction of the Any-Any binary code and Any-to-Any transistor systems, and which handles data and transforms it in a sufficiently similar manner to the manner in which the human handles and transforms data that the human finds it easy and intuitive to operate, all supported by methods that enable data to be stored in a single logical grid structure that can accept and correctly relate, transmit and receive any data, together examples of methods to derive benefits from these inventions.

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Номер записи: 91
08-08-2013 дата публикации

METHODS AND APPARATUSES FOR AUTOMATIC TYPE CHECKING VIA POISONED POINTERS

Номер: US20130205285A1
Автор: Pizlo Filip J.
Принадлежит: Apple Inc.

A method and an apparatus that modify pointer values pointing to typed data with type information are described. The type information can be automatically checked against the typed data leveraging hardware based safety check mechanisms when performing memory access operations to the typed data via the modified pointer values. As a result, hardware built in logic can be used for a broad class of programming language safety check when executing software codes using modified pointers that are subject to the safety check without executing compare and branch instructions in the software codes. 1. A machine-readable non-transitory storage medium having instructions therein , which when executed by a machine , cause the machine to perform a method , the method comprising:loading a pointer for a data structured according to a type, the structured data addressable in a memory via an address, the pointer specifying both the address and the type of the structured data;updating the pointer via arithmetic operations on the pointer with an identifier identifying a known type for determining if the type matches the known type without compare and branch operations; andloading data addressed by the updated pointer, wherein the structured data is loaded if the type matches the known type, and wherein a hardware trap handler is activated if the type does not match the known type.2. The medium of claim 1 , wherein the pointer is loaded to a hardware register to access a unit of data in a memory addressed by the pointer atomically via a hardware processor.3. The medium of claim 1 , wherein a plurality of types of structured data are created dynamically during runtime claim 1 , the types including the known type claim 1 , wherein the pointer includes a plurality of bits claim 1 , a portion of the bits corresponding to the identifier identifying the known type claim 1 , and wherein the portion of the bits capable of representing the plurality of types of structured data.4. The medium of ...

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Номер записи: 92
08-08-2013 дата публикации

RUNTIME OPTIMIZATION USING META DATA FOR DYNAMIC PROGRAMMING LANGUAGES

Номер: US20130205286A1
Автор: Barraclough Gavin, Pizlo Filip J.
Принадлежит: Apple Inc.

A method and an apparatus that optimize operations for a key among a collection of key indexed data structures using meta data describing properties of the key with respect to the collection of data structures are described. The meta data may correspond to a cache dynamically updated to indicate invariants which are true for the key in a current state of the collection of data structures. Expensive calculations to search through the collection of data structures for the key may be avoided. For example, costly lookup operations over a collection of data structures may not be required at all if a key is known to always (or to never) reference certain specific values, or for these values to have certain meta-properties, in any of the collection of data structure globally throughout a system at a current state. 1. A machine-readable non-transitory storage medium having instructions therein , which when executed by a machine , cause the machine to perform a method , the method comprising:inspecting meta data of a key to determine whether to perform lookup operations among currently allocated data objects to access a property of a data object during runtime executing a code, the property indexed by the key, the runtime having a runtime state with the currently allocated data objects including the data object, the meta data of the key including global information related to the key consistent with each data object of the runtime state;performing access operations directly for the property of the data object without performing the lookup operations if the meta data of the key satisfies certain conditions; andupdating the meta data of the key to maintain consistency with the runtime state updated with the access operations performed for the property of the data object.2. The medium of claim 1 , wherein the meta data includes multi-bit structure claim 1 , each bit having binary value indicating whether an assertion associated with the bit about the key is globally true with ...

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Номер записи: 93
15-08-2013 дата публикации

PARALLELIZATION METHOD, SYSTEM AND PROGRAM

Номер: US20130212554A1
Автор: MAEDA KUMIKO, SHIMIZU Shuichi, Yoshizawa Takeo
Принадлежит: INTERNATIONAL BUSINESS MACHINES CORPORATION

A method, system, and article of manufacture for solving ordinary differential equations described in a graphical model with nodes as blocks and dependencies as links using the processing of a computer with a plurality of processors. The method includes: generating segments of block with or without duplication for each block with an internal state and for each block without any output by traversing the graphical model from each block with an internal state to each block without any output; merging the segment to reduce duplication; compiling and converting each segment from the merged results in an executable code; and individually allocating the executable code for each segment to a plurality of processors for parallel execution. 1. A method for solving ordinary differential equations described in a graphical model with nodes as blocks and dependencies as links using the processing of a computer with a plurality of processors , said method comprising the steps of:generating segments of blocks with or without duplication for each block with an internal state and for each block without any output by traversing said graphical model from each said block with an internal state to each said block without any output;merging said segments to reduce duplication;compiling and converting each segment from said merged results into an executable code; andindividually allocating said executable code for each segment to the plurality of processors for parallel execution.2. The method of claim 1 , wherein said step for generating segments has a step for adding a block to a segment claim 1 , wherein said added block to said segment follows a parent block claim 1 , which is not comprised of a dependency claim 1 , and wherein said dependency does not exist within a single time step including an input to said block with an internal state.3. The method of claim 1 , wherein said step for merging segments to reduce duplication comprises the steps of:(a) extracting a segment s having the ...

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Номер записи: 94
22-08-2013 дата публикации

Vectorization of shaders

Номер: US20130219378A1
Автор: Andy Glaister, Blaise Pascal Tine, Blake Pelton, Derek Sessions, Mikhail Lyapunov, Yuri Dotsenko
Принадлежит: Microsoft Corp

Intermediate representation (IR) code is received as compiled from a shader in the form of shader language source code. The input IR code is first analyzed during an analysis pass, during which operations, scopes, parts of scopes, and if-statement scopes are annotated for predication, mask usage, and branch protection and predication. This analysis outputs vectorization information that is then used by various sets of vectorization transformation rules to vectorize the input IR code, thus producing vectorized output IR code.

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Номер записи: 95
22-08-2013 дата публикации

Optimization of an application to reduce local memory usage

Номер: US20130219379A1
Автор: Andrew D. Naumann, Curtis E. Hrischuk, David Brauneis, Jeffrey E. Care
Принадлежит: International Business Machines Corp

A method of optimizing an application to reduce local memory usage. The method can include instrumenting at least one executable class file of the application with analysis code, the executable class file including bytecode. The method also can include executing the class file on a virtual machine, wherein during execution the analysis code generates data related to the application's use of local memory. The method further can include, via a processor, analyzing the data related to the application's use of the local memory to generate a memory profile analysis. The method further can include, based on the memory profile analysis, automatically revising at least one portion of the bytecode to reduce an amount of the local memory used by the application.

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Номер записи: 96
29-08-2013 дата публикации

APPLICATION GENERATION SYSTEM AND METHOD FOR GENERATING AN APPLICATION

Номер: US20130227532A1
Автор: CHOI Sung Chul
Принадлежит: Pantech Co., Ltd.

The application generation system includes: a first managing unit to extract at least one execution component from at least one application; and a second management unit to generate an extracted execution component into a container application. The system provides the ability to generate an application configured by extracting operations among the operations of applications stored in a terminal. 1. An application generation system of a terminal , comprising:a first management unit to extract an execution component from an application of the terminal, the execution component being a portion of the application; anda second management unit to generate a container application including the execution component.2. The system of claim 1 , wherein the first management unit comprises:an input/output unit to receive an input;a data extraction unit to extract the execution component;a control unit to control the data extraction unit to extract the execution component according to the input; anda transmission unit to transmit the execution component.3. The system of claim 2 , wherein the second management unit comprises:a transmission unit to receive the execution component from the first management unit; anda file input/output unit to generate the container application including the execution component4. The system of claim 2 , wherein the first management unit receives a container application list from the second management unit and the control unit determines whether to generate the container application including the container application list.5. The system of claim 4 , wherein the container application list is a list of container applications stored in the terminal.6. The system of claim 2 , wherein the control unit determines if the execution component may be displayed on the terminal and the control unit determines the location on a terminal screen at which to display the execution component.7. The system of claim 1 , wherein the execution component comprises at least ...

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Номер записи: 97
29-08-2013 дата публикации

SIMULATION APPARATUS, METHOD AND MEDIUM

Номер: US20130227534A1
Автор: IKE Atsushi, THACH David
Принадлежит: FUJITSU LIMITED

A code converter of a simulation apparatus detects, during the execution of a program in a target CPU, an externally dependent instruction affected by the external environment in each of divided blocks, predicts the execution result of the externally dependent instruction, simulates the instruction execution in the predicted result, and generates a host code in which a code for performance simulation is embedded based on the simulation result. A simulation executor performs performance simulation about instruction execution in the prediction result of the program using the host code, and when the execution result of the externally dependent instruction is different from the setting of the prediction result during the execution, corrects the execution time of the instruction in the prediction result using the execution time of instructions executed before and after the instruction, and the like. A simulation information collector collects and outputs performance simulation information. 1. A simulation apparatus that executes a simulation of instruction execution of a program for a target processor that controls a pipeline process , comprising:a processor configured to realize functions ofa code converter configured to perform a process to divide a code of the program into prescribed blocks, and to set an execution result of an externally dependent instruction that is an instruction among instructions included in the blocks whose execution process depends on an external environment as a prediction result; a process to performs a function simulation of instruction execution assuming the prediction result, and to obtain timing information representing an execution timing of an instruction included in the block, and to calculate an execution time of the externally dependent instruction in the prediction result, based on a result of the function simulation and the timing information; and a process to generate, based on the result of the function simulation, a host code to ...

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Номер записи: 98
29-08-2013 дата публикации

Increasing Performance at Runtime from Trace Data

Номер: US20130227536A1
Автор: Garrett Charles D., Gounares Alexander G., Krajec Russell S., LI Ying
Принадлежит:

An analysis system may perform network analysis on data gathered from an executing application. The analysis system may identify relationships between code elements and use tracer data to quantify and classify various code elements. In some cases, the analysis system may operate with only data gathered while tracing an application, while other cases may combine static analysis data with tracing data. The network analysis may identify groups of related code elements through cluster analysis, as well as identify bottlenecks from one to many and many to one relationships. The analysis system may generate visualizations showing the interconnections or relationships within the executing code, along with highlighted elements that may be limiting performance. 1. A method performed by a computer processor , said method comprising:tracing an application and gathering performance data for a plurality of code elements related to said application;analyzing said performance data and generating a set of processor settings as causing performance effects on said application; andtransmitting said processor settings to a client device, said client device that uses said set of processor settings when executing said application.2. The method of claim 1 , said set of processor settings comprising a first set of settings for a first code element and a second set of settings for a second code element.3. The method of claim 2 , said set of processor settings comprising a first set of settings for a first instance of a first code element and a second set of settings for a second instance of said first code element.4. The method of claim 3 , said first instance of said first code element being defined by a first set of input parameters and said second instance of said first code element being defined by a second set of input parameters.5. The method of claim 3 , said first instance of said first code element being defined by a first set of parameters claim 3 , said first set of parameters ...

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Номер записи: 99
29-08-2013 дата публикации

CONTROL STRUCTURE REFINEMENT OF LOOPS USING STATIC ANALYSIS

Номер: US20130227537A1
Автор: BALAKRISHNAN GOGUL, Gupta Aarti, SANKARANARAYANAN SRIRAM
Принадлежит: NEC Laboratories America, Inc.

A system and method for discovering a set of possible iteration sequences for a given loop in a software program is described, to transform the loop representation. In a program containing a loop, the loop is partitioned into a plurality of portions based on splitting criteria. Labels are associated with the portions, and an initial loop automaton is constructed that represents the loop iterations as a regular language over the labels corresponding to the portions in the program. Subsequences of the labels are analyzed to determine infeasibility of the subsequences permitted in the automaton. The automaton is refined by removing all infeasible subsequences to discover a set of possible iteration sequences in the loop. The resulting loop automaton is used in a subsequent program verification or analysis technique to find violations of correctness properties in programs. 1. A method for discovering a set of possible iterative sequences for a given loop in a program , the method comprising:partitioning the loop into a plurality of portions based on control flow in the loop, each of the plurality of portions representing multiple paths in the control flow;associating labels with the portions, loop iterations being abstracted as a finite state automaton over the labels;constructing an initial loop automaton in memory storage that represents the loop iterations as a regular language over the labels corresponding to the portions in the program;analyzing subsequences of the labels to determine infeasibility of the subsequences permitted in the automaton; andrefining the loop automaton by removing all infeasible subsequences to discover a set of possible iteration sequences.2. The method as recited in claim 1 ,wherein partitioning the loop into a plurality of portions includes partitioning the loop using splitting criteria including one or more of outcome of branches in the loop, back edges traversed by an iteration, and induction variable updates.3. The method as recited in ...

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Номер записи: 100