КОМАНДА НА НЕТРАНЗАКЦИОННОЕ СОХРАНЕНИЕ

FIELD: physics, computer engineering. SUBSTANCE: invention relates to transactional processing within a multiprocessor computing environment. The invention provides a method of executing an instruction within a computing environment, as well as computer-readable data medium and a computer system with which said method is carried out. The method includes obtaining, by a processor, a machine instruction for execution, the machine instruction being defined for computer execution according to a computer architecture, the machine instruction comprising: an operation code to specify a non-transactional store operation; a first operand and a second operand to designate a location for the first operand; and executing, by the processor, the machine instruction, the execution comprising: non-transactional placing of the first operand at the location specified by the second operand, wherein information stored at the second operand is retained despite an abort of a transaction associated with the machine instruction, and wherein the non-transactional placing is delayed until an end of transactional execution mode of the processor. According to the invention, a non-transactional store instruction, executed in transactional execution mode, performs stores that are retained, even if a transaction associated with the instruction aborts. EFFECT: high efficiency of debugging an aborted transaction. 20 cl, 23 dwg РОССИЙСКАЯ ФЕДЕРАЦИЯ (19) RU (11) (51) МПК G06F 9/46 (13) 2 568 324 C2 (2006.01) ФЕДЕРАЛЬНАЯ СЛУЖБА ПО ИНТЕЛЛЕКТУАЛЬНОЙ СОБСТВЕННОСТИ (12) ОПИСАНИЕ (21)(22) Заявка: ИЗОБРЕТЕНИЯ К ПАТЕНТУ 2012148587/08, 15.11.2012 (24) Дата начала отсчета срока действия патента: 15.11.2012 Приоритет(ы): (30) Конвенционный приоритет: (72) Автор(ы): Дан Ф. ГРЕЙНЕР (US), Кристиан ЯКОБИ (DE), Тимоти Дж. СЛИДЖЛ (US) 15.06.2012 US 13/524,887 (43) Дата публикации заявки: 20.05.2014 Бюл. № 14 R U (73) Патентообладатель(и): ИНТЕРНЭШНЛ БИЗНЕС МАШИНЗ КОРПОРЕЙШН (US) (45) Опубликовано: 20.11.2015 Бюл. № ...

Pipeline-Rechner mit Anzeigetafel

Preload instruction control

Managing a register cache based on an architected computer instruction set

Method and apparatus for branch instruction processing in a processor

Register renaming

Vector processor

A data processor has a plurality of vector registers capable of reading and writing in parallel; a plurality of ALU's; a plurality of sending circuits, one for each of said vector registers, each for updating a read address for the corresponding vector register requested by a succeeding instruction within such a limit that said read address does not pass a write address for said corresponding vector register requested by a preceding instruction and sending out a read data together with a data valid signal for each updating; circuits for sending the data and the data valid signals from said plurality of sending circuits to the ALU's requested by the corresponding instructions; and circuits, one for each of said ALU's, each for controlling the corresponding ALU such that when the data valid signals have been received from all of the vector registers necessary to execute the instruction which uses the corresponding ALU, the corresponding ALU operates on the data supplied with said data valid ...

Epoch-based determination of completion of barrier termination command

An apparatus comprises transaction handling circuitry to issue memory access transactions, each memory access transaction specifying an epoch identifier indicative of a current epoch in which the memory access transaction is issued; transaction tracking circuitry to track, for each of at least two epochs, a number of outstanding memory access transactions issued in that epoch; barrier termination circuitry to signal completion of a barrier termination command when the transaction tracking circuitry indicates that there are no outstanding memory access transactions remaining which were issued in one or more epochs preceding a barrier point, and epoch changing circuitry to change the current epoch to a next epoch, in response to a barrier point signal representing said barrier point. This helps to reduce the circuit area overhead for tracking completion of memory access transactions preceding a barrier point.

DIGITAL SIGNAL PROCESSOR DEVICE

MULTIPROCESSOR SYSTEM WITH REPEATED COMMAND SOURCES

INFORMATION PROCESSING SYSTEM

루프의 프롤로그 또는 에필로그의 비유효 연산을 처리하는 장치 및 방법

... 소프트웨어 파이프라인된 루프의 프롤로그 또는 에필로그에서 비유효 연산(invalid operation)을 처리하는 장치에 관한 것이다. 일 실시예에 따른 비유효 연산 처리 장치는 데이터의 유효 상태를 저장하는 제1 영역과 그 데이터를 저장하는 제2 영역을 포함하는 레지스터 파일 및 그 레지스터 파일로부터 입력되는 하나 이상의 입력 소스의 제1 영역 값에 기초하여 연산의 비유효(invalid) 여부를 판단하고 제1 영역의 대응값을 포함하는 데스티네이션(destination)을 출력하는 하나 이상의 기능 유닛(functional unit)을 포함할 수 있다. 본 실시예에 따르면 비유효 연산의 가딩을 위해 프리디케이트를 사용하지 않기 때문에 컴파일러의 성능을 향상시킬 수 있다.

Systems, apparatuses, and methods for data speculation execution

Systems, methods, and apparatuses for data speculation execution (DSX) are described. In some embodiments, a hardware apparatus for performing DSX comprises a hardware decoder to decode an instruction, the instruction to include an opcode and an operand to store a portion of a fallback address and an operand to store a stride value, execution hardware to execute the decoded instruction to initiate a data speculative execution (DSX) region by activating DSX tracking hardware to track speculative memory accesses and detect ordering violations in the DSX region, and storing the fallback address.

PIPELINED INSTRUCTION PROCESSOR WITH DATA BYPASSING

An instruction processing device has a of pipe-line stage with a functional unit for executing a command from an instruction. A first register unit is coupled to the functional unit for storing a result of execution of the command when the command has reached a first one of the pipeline stages, and for supplying bypass operand data to the functional unit. A register file is coupled to the functional unit for storing the result when the command has reached a second one of the pipeline stages, downstream from the first one of the pipeline stages, and for supplying operand data to the functional unit. A disable circuit is coupled to selectively disable storing of the results in the register file under control of the instructions.

SYSTEM AND METHOD TO PREVENT IN-FLIGHT INSTANCES OF OPERATIONS FROM DISRUPTING OPERATION REPLAY WITHIN A DATA-SPECULATIVE MICROPROCESSOR

A microprocessor (100) may include one or more functional units (126) configured to execute operations, a scheduler (118) configured to issue operations to the functional units (126) for execution, and at least one replay detection unit. The scheduler (118) may be configured to maintain state information (606) for each operation. Such state information (606) may, among other things, indicate whether an associated operation has completed execution. The replay detection unit may be configured to detect that one of the operations in the scheduler (118) should be replayed. If an instance of that operation is currently being executed by one of the functional units (126) when operation is detected as needing to be replayed, the replay detection unit is configured to inhibit an update to the state information (606) for that operation in response to execution of the in-flight instance of the operation. Various embodiments of computer systems (900) may include such a microprocessor (100).

Hybrid Branch Prediction Scheme

A method and apparatus for executing a branch instruction is provided. In one embodiment, the method includes determining if a predictability value for the branch instruction is below a threshold value. Upon determining that the predictability value is above or equal to the threshold value, branch prediction information for the branch instruction is used to predict the outcome of the branch instruction. Upon determining that the predictability value for the branch instruction is below the threshold value for predictability, an alternate method of executing the branch instruction is selected. The alternate method comprises at least one of preresolving the branch instruction, simultaneously issuing first instructions from a first path of the branch instruction and second instructions from a second path of the branch instruction, and buffering the first instructions from the first path of the branch instruction and the second instructions from the second path of the branch instruction.

SECURE SPECULATIVE INSTRUCTION EXECUTION IN A DATA PROCESSING SYSTEM

A data processing system includes a processor, a cache memory, a speculative cache memory, and a control circuit. The processor is for executing instructions. The cache memory is coupled to the processor and is for storing the instructions and related data. A speculative cache is coupled to the processor and is for storing only speculative instructions and related data. The control circuit is coupled to the processor, to the cache memory, and to the speculative cache. The control circuit is for causing speculative instructions to be stored in the speculative cache in response to receiving an indication from the processor. Also, a method is provided for speculative execution in the data processing system.

System and Method for Prioritizing Branch Instructions

The present invention provides a system and method for prioritizing branch instructions in a cascaded pipeline. The system includes a cascaded delayed execution pipeline unit having a plurality of execution pipelines that execute instructions in a common issue group in a delayed manner relative to each other. The system further includes circuitry configured to: (1) receive an issue group of instructions; (2) determine if at least one branch instruction is in the issue group, if so scheduling the least one branch instruction in a one of the plurality of execution pipelines based upon a first prioritization scheme; (3) determine if there is an issue conflict for one of the plurality of execution pipelines and resolving the issue conflict by scheduling the at least one branch instruction in a different execution pipeline; (4) schedule execution of the issue group of instructions in the cascaded delayed execution pipeline unit.

Information processing unit, and exception processing method for specific application-purpose operation instruction

In the control section, an operation instruction not prescribing a functional specification, and a unit for processing the specific application-purpose operation instruction is provided within the processor core. The structure of this unit can be changed based on a flexible pipeline structure, and is separately designed for each application field. A register that prescribes a latency from when an instruction of the above unit is issued till when a result can be utilized is also provided in the processor core so as to prevent contention of an output port. Another register that prescribes a latency relating to a constraint of an interval of issuing an instruction of the above unit is also provided in the processor core so as to prevent contention of a resource with the preceding instructions.

COMBINING INSTRUCTIONS FROM DIFFERENT BRANCHES FOR EXECUTION IN A SINGLE N-WAY VLIW PROCESSING ELEMENT OF A MULTITHREADED PROCESSOR

A data processing system includes a processor operable to execute a program partitioned into a number of discrete instructions, the processor having multiple processing elements each capable of executing more than one instruction per cycle, and an interface configured to read a first program and, on detecting a branch operation by that program creating m number of branches each having a different sequence of instructions, combine an instruction from one of the branches with an instruction from at least one of the other branches so as to cause a processing element to execute the combined instructions during a single cycle. 1. A data processing system comprising:a first processor operable to execute a program partitioned into a plurality of discrete instructions, the first processor comprising a plurality of processing elements, each processing element capable of executing n instructions per cycle, wherein n is an integer greater than 1; andan interface configured to, on detecting a branch operation by a program creating m number of branches each having a different sequence of instructions, wherein m is an integer greater than 1, cause a compiler to compile the sequence of instructions from each branch so as to be suitable for processing elements that are only capable of executing one instruction per cycle, and combine an instruction from one of the branches with an instruction from at least one of the other branches to form a combined instruction so as to cause at least one processing element to execute the combined instruction during a single cycle.2. The data processing system as claimed in claim 1 , wherein m is less than n.3. The data processing system as claimed in claim 1 , wherein m and n are equal.4. The data processing system as claimed in claim 1 , wherein instructions from each of the branches are combined so as to cause each processing element to execute at least one instruction from each branch per cycle.5. The data processing system as claimed in claim ...

DYNAMIC DETECTION AND PREDICTION FOR STORE-DEPENDENT BRANCHES

One embodiment provides an apparatus. The apparatus includes a store direct dependent (SDD) branch prediction circuitry and an SDD management circuitry. The store direct dependent (SDD) branch prediction circuitry is to store an SDD branch table. The SDD branch table is to store at least one record. Each record includes a branch instruction pointer (IP) field, a load IP field, a store IP field, a comparison info field and at least one of a store value field and/or a predicted outcome field. The SDD management circuitry is to populate the SDD branch table at runtime and to override a baseline branch prediction associated with an incoming branch IP with an SDD branch prediction, if the SDD branch table contains a first record populated with the incoming branch IP and at least one of a store value and/or an SDD predicted outcome. 1. An apparatus comprising:a store direct dependent (SDD) branch prediction circuitry to store an SDD branch table, the SDD branch table to store at least one record, each record comprising a branch instruction pointer (IP) field, a load IP field, a store IP field, a comparison info field and at least one of a store value field and/or a predicted outcome field; andan SDD management circuitry to populate the SDD branch table at runtime and to override a baseline branch prediction associated with an incoming branch IP with an SDD branch prediction, if the SDD branch table contains a first record populated with the incoming branch IP and at least one of a store value and/or an SDD predicted outcome.2. The apparatus of claim 1 , wherein the first record is populated with a store IP and the SDD management circuitry is to determine the SDD branch prediction based claim 1 , at least in part claim 1 , on a store value associated with the store IP.3. The apparatus of claim 1 , wherein the populating the SDD branch table comprises querying a memory renaming (MRN) circuitry using a load IP of a load instruction to determine a store IP of a store ...

METHOD AND APPARATUS FOR RESTORING DATA TO A REGISTER FILE OF A PROCESSING UNIT

Method and system for restoring data to a register file of a processing unit are provided. A history buffer entry (HBE) is marked for restoration to a register file entry. Result data and control information is sent from the HBE to an Issue Queue (ISQ). The ISQ issues an instruction for loading the result data into the register file entry based on the control information. A write back operation is performed to restore the result data to the register file entry, in response to issuing of the instruction.

Split-level history buffer in a computer processing unit

A split level history buffer in a central processing unit is provided. A first instruction and a second instruction are fetched, tagged, and the first instruction is stored an entry of a register file. The first instruction is evicted from the entry and the second instruction is stored in the entry. If the first instruction is evicted, then the first instruction is stored in a first portion of a history buffer. If a result for the first instruction is generated, then the first instruction is moved to a second portion of the history buffer and the result is stored with the first instruction in the second portion of the history buffer. If it is determined that a third instruction evicts the second instruction from the entry, then the second instruction is stored in the first portion of the history buffer.

GRAPHICS ENGINE RESET AND RECOVERY IN A MULTIPLE GRAPHICS CONTEXT EXECUTION ENVIRONMENT

Methods, systems and apparatuses may provide for technology that triggers an idle state in a first command streamer in response to a request to reset a second command streamer that shares graphics hardware with the first command streamer. The technology may also determine an event type associated with the request and conduct the request based on the event type.

КОМАНДА НЕТРАНЗАКЦИОННОЕ СОХРАНЕНИЕ

... 1. Компьютерный программный продукт для выполнения команды внутри вычислительной среды, указанный компьютерный программный продукт содержит:считываемую компьютером запоминающую среду, считываемую обрабатывающим устройством и хранящую команды для выполнения обрабатывающим устройством для выполнения метода, содержащего:получение процессором машинной команды для выполнения, причем указанная машинная команда определяется для выполнения компьютером в соответствии с архитектурой компьютера, указанная машинная команда включает:код операции для определения нетранзакционной операции сохранения;первый операнд ивторой операнд для указания позиции для первого операнда; ивыполнение процессором машинной команды, причем указанное выполнение включает:нетранзакционное размещение первого операнда в позиции, указанной вторым операндом, причем информация, хранящаяся во втором операнде, остается, несмотря на сброс транзакции, связанной с машинной командой, и в котором нетранзакционное размещение удерживается ...

СОХРАНЕНИЕ/ВОССТАНОВЛЕНИЕ ВЫБРАННЫХ РЕГИСТРОВ ПРИ ТРАНЗАКЦИОННОЙ ОБРАБОТКЕ

... 1. Компьютерный программный продукт для облегчения обработки транзакций внутри вычислительной среды, причем компьютерный программный продукт содержит:считываемую компьютером запоминающую среду, считываемую обрабатывающим устройством и хранящую команды для выполнения обрабатывающим устройством для выполнения метода, содержащего:определение процессором из информации, предоставленной командой, одного или более выбранных регистров, которые необходимо сохранить при транзакционной обработке, команды начать обработку транзакции, причем транзакция эффективно задерживает фиксацию транзакционных сохранений в главной памяти до тех пор, пока не завершится выбранная транзакция, и один или более выбранных регистров составляют меньше, чем все регистры, используемые транзакцией при выполнении транзакции; исохранение содержимого одного или более выбранных регистров, основанное на выполнении команды.2. Компьютерный программный продукт по п.1, в котором метод дополнительно включает:определение того, что транзакция ...

Vorrichtung und Rechnerprogrammprodukt zur Ausführung von Verzweigungsbefehlen

Combining paths

Method and apparatus for scheduling in a non-uniform compute device

A data processing apparatus, and method of operation thereof, for executing instructions. The apparatus includes one or more host processors, each having a first processing unit, and a multi-level memory system. One or more levels of the memory system are tightly coupled to a corresponding second processing unit. At least one of the host processors includes an instruction scheduler that routes instructions selectively to at least one of the first and second processing units, dependent upon the availability of the processing units and the location, within the memory system, of data to be used when executing the instructions.

Managing a register cache based on an architected computer instruction set

VECTOR PROCESSOR

Coherence protocol augmentation to indicate transaction status

Embodiments relate to implementing a coherence protocol. An aspect includes sending a request for data to a remote processor and receiving by a processor a response from the remote processor. The response has a transaction status of a remote transaction on the remote processor. The processor adds the transaction status of the remote transaction on the remote processor in a local transaction interference tracking table.

NONTRANSACTIONAL STORE INSTRUCTION

A NONTRANSACTIONAL STORE instruction, executed in transactional execution mode, performs stores that are retained, even if a transaction associated with the instruction aborts. The stores include user-specified information that may facilitate debugging of an aborted transaction.

PROCESSOR WITH A COPROCESSOR HAVING EARLY ACCESS TO NOT-YET ISSUED INSTRUCTIONS

Configurable co-processor interface

A configurable coprocessor interface between a central processing unit (CPU) and a coprocessor is provided. The coprocessor interface has an instruction transfer signal group for transferring different instruction types from the CPU to the coprocessor, sequentially or in parallel, a busy signal group, for allowing the coprocessor to signal the CPU that it cannot receive a transfer of one or more of the different instruction types, and an instruction order signal group for indicating to the coprocessor a relative execution order for multiple instructions that are transferred in parallel. In addition, the coprocessor interface includes separate data transfer signal groups for data being transferred from the CPU to the coprocessor, and for data being transferred from the coprocessor to the CPU, along with a data order signal group for indicating a relative order of data (if transferred out-of-order). The interface further includes signal designations which allow for multiple issue groups between ...

Early Conditional Branch Resolution

A method and apparatus for executing branch instructions is provided. In one embodiment, In one embodiment, the method includes receiving the branch instruction to be executed in a program order and, before execution of the branch instruction in the program order, issuing the branch instruction to an execution unit to determine a predicted outcome of the branch instruction. The method further includes using the predicted outcome of the branch instruction to schedule execution of one or more instructions succeeding the branch instruction in the program order.

Hybrid hardware and software implementation of transactional memory access

Embodiments of the invention relate a hybrid hardware and software implementation of transactional memory accesses in a computer system. A processor including a transactional cache and a regular cache is utilized in a computer system that includes a policy manager to select one of a first mode (a hardware mode) or a second mode (a software mode) to implement transactional memory accesses. In the hardware mode the transactional cache is utilized to perform read and write memory operations and in the software mode the regular cache is utilized to perform read and write memory operations.

BLOCK-BASED PROCESSOR CORE TOPOLOGY REGISTER

Systems, apparatuses, and methods related to a block-based processor core topology register are disclosed. In one example of the disclosed technology, a processor can include a plurality of block-based processor cores for executing a program including a plurality of instruction blocks. A respective block-based processor core can include a sharable resource and a programmable composition topology register. The programmable composition topology register can be used to assign a group of the physical processor cores that share the sharable resource.

Determining of validity of speculative load data after a predetermined period of time in a multi-slice processor

Operation of a multi-slice processor that includes a plurality of execution slices and a plurality of load/store slices coupled via a results bus includes: retrieving, from the results bus into an entry of a register file of an execution slice, speculative result data of a load instruction generated by a load/store slice; and determining, from the load/store slice after expiration of a predetermined period of time, whether the result data is valid.

Efficient arithimetic logic units

A processor may include a conditional arithmetic logic unit and a main arithmetic logic unit. The conditional arithmetic logic unit may perform a first arithmetic logic operation to generate a first result, and output the result. The main arithmetic logic unit may select input buses among a plurality of data buses that carry the first result from the conditional arithmetic logic unit, perform a second arithmetic logic operation on data provided by the selected input buses to generate a second result, and write the second result in a storage component.

Electronic computer which executes squash branching

An electronic computer according to this invention is capable of executing a plurality of instructions simultaneously. It is characterized by comprising a flag adding section for judging whether or not each of a plurality of instruction is either a delayed branch instruction or a squash branch instruction, and based on the results, adding a flag indicating an abort condition to each instruction, and a command execute abort section for aborting execution of each instruction on the basis of whether or not the flag added to each instruction to indicate the abort condition and each branch instruction hold true.

Saving/restoring selected registers in transactional processing

A TRANSACTION BEGIN instruction begins execution of a transaction and includes a general register save mask having bits, that when set, indicate registers to be saved in the event the transaction is aborted. At the beginning of the transaction, contents of the registers are saved in memory not accessible to the program, and if the transaction is aborted, the saved contents are copied to the registers.

Transactional memory in out-of-order processors

Methods and apparatus to provide transactional memory execution in out-of-order processors are described. In one embodiment, a stored value corresponds to the number of transactional memory access requests that are uncommitted. The stored value may be used to provide nested recovery in case of an error, fault, etc. in accordance with a described embodiment.

System, apparatus and method to suppress redundant store operations in a processor

In one embodiment, a processor has a core including at least one execution circuit, a retirement circuit, a first cache memory, and a first cache controller to control the first cache memory, where the first cache controller, in response to a store request to store a first value to a memory coupled to the processor, is to suppress the store operation when the first value matches a stored value of a cache line associated with the store operation. Other embodiments are described and claimed.

LOCAL AND GLOBAL BRANCH PREDICTION INFORMATION STORAGE

DATA PROCESSOR WITH PARALLEL DECODING AND EXECUTION OF DATA AND ADDRESS INSTRUCTIONS

The present invention relates to a data processor which comprises a first pipeline for decoding and executing data instructions, a second pipeline for decoding and executing address instructions, a unit for issuing multiple instructions to said pipelines, a first set of registers being coupled with said first pipeline, and a second set of registers being coupled with said second pipeline, wherein first and second pipeline process data in parallel.

Erzeugen von kompiliertem Code, der Registeraktivität angibt

Objektcode wird aus einer internen Darstellung erzeugt, die eine Vielzahl von Quellenoperanden enthält. Das Erzeugen enthält für jeden Quellenoperanden in der internen Darstellung ein Ausführen einer Ermittlung, ob eine Zuletztverwendung für den Quellenoperanden stattgefunden hat. Die Ermittlung enthält ein Zugreifen auf einen Datenflussgraphen, um zu ermitteln, ob alle Verwendungen eines aktiven Bereichs ausgegeben worden sind. Wenn ermittelt wird, dass eine Zuletztverwendung für den Quellenoperanden stattgefunden hat, wird eine in einer Architektur angeordnete Ressource, die dem Quellenoperanden zugehörig ist, für eine Zuletztverwendungsangabe gekennzeichnet. Dann wird für die in einer Architektur angeordnete Ressource eine Zuletztverwendungsangabe erzeugt. Anweisungen und die Zuletztverwendungsangaben werden in den Objektcode ausgegeben.

HYBRIDATOMARITÄTSUNTERSTÜTZUNG FÜR EINEN BINÄRÜBERSETZUNGSBASIERTEN MIKROPROZESSOR

Eine Verarbeitungsvorrichtung, die umfasst: ein erstes Schattenregister, ein zweites Schattenregister und eine Befehlsausführungsschaltung, die kommunikationstechnisch mit dem ersten Schattenregister und dem zweiten Schattenregister gekoppelt ist und zu Folgendem ausgelegt ist: Empfangen einer Sequenz von Befehlen, die einen ersten lokalen Festschreibungsmerker, einen ersten globalen Festschreibungsmerker und einen ersten Registerzugriffsbefehl, der auf ein Architekturregister verweist, umfasst, spekulatives Ausführen des ersten Registerzugriffsbefehls, um einen spekulativen Registerzustandswert zu erzeugen, der einem physischen Register zugeordnet ist, als Antwort auf das Identifizieren der ersten lokalen Festschreibungsmerkers, Speichern des spekulativen Registerzustandswerts in dem ersten Schattenregister, und, als Antwort auf das Identifizieren des ersten globalen Festschreibungsmerkers, Speichern des spekulativen Registerzustandswerts in dem zweiten Schattenregister.

TECHNIKEN ZUR IDENTIFIZIERUNG UNRICHTIGER INFORMATIONEN IN AUFRUFSTAPELN

Es werden Ausführungsformen offenbart zum Erhalten eines Aufrufstapels für Binärdateien, wobei der Aufrufstapel eine Sequenz von Rahmen aufweist und jeder Rahmen eine „von“-Adresse und eine „zu“-Adresse für einen Aufrufbefehl aufweist, und zum Bestimmen von Basisbefehlsblöcken für die Binärdateien, wobei jeder Basisbefehlsblock einen oder mehrere Befehle aufweist. Ferner weisen die Ausführungsformen das Durchlaufen des Aufrufstapels zum Validieren von von/zu-Adressenpaaren aufeinanderfolgender Rahmen basierend auf Kontrollflusswegen auf, die zwischen „von“-Adressen und „zu“-Adressen der von/zu-Adressenpaare existieren, wobei jedes von/zu-Adressenpaar eine „von“-Adresse eines Rahmens und eine „zu“-Adresse eines unmittelbar vorhergehenden Rahmens auf dem Aufrufstapel aufweist.

System and method for operation replay within a data-speculative microprocessor

A microprocessor (100) may include one or more functional units (126) configured to execute operations, a scheduler (118) configured to issue operations to the functional units (126) for execution, and at least one replay detection unit. The scheduler (118) may be configured to maintain state information (606) for each operation. Such state information (606) may, among other things, indicate whether an associated operation has completed execution. The replay detection unit may be configured to detect that one of the operations in the scheduler (118) should be replayed. If an instance of that operation is currently being executed by one of the functional units (126) when operation is detected as needing to be replayed, the replay detection unit is configured to inhibit an update to the state information (606) for that operation in response to execution of the in-flight instance of the operation. Various embodiments of computer systems (900) may include such a microprocessor (100).

Managing a register cache based on an architected computer instruction set

Exploiting an architected last-use operand indication in a computer system operand resource pool

Debugging data processing transactions

A target transaction comprises a plurality of program instructions that execute to generate speculative updates to architectural state data. Upon detecting 200 a trigger condition the trigger condition corresponding to direct execution 202 of the transaction by processing hardware software emulation 204 of the target transaction is initiated. Preferably, the emulation permits single-stepping of the transaction instructions. Any conflict with the target transaction is detected 208, e.g. access to memory used by the transaction. If the target transaction completes without conflict then the software emulation stores data representing speculative updates generated during emulation of execution of the target transaction, i.e. the speculative updates are committed 214. The claimed invention finds typical application in debugging hardware transactions, e.g. transactional memory access. Also disclosed is an arrangement in which a memory access request is issued, receipt of a non-standard response ...

Apparatus with shared transactional processing resource and data processing method

An apparatus 2 with multiple processing elements 4, 6, 8 has shared transactional processing resources such as a dedicated transaction processing element 10, a transaction processing element (50, figure 2) which also has general purpose processing capability or separate transactional processing resources (75, figure 3). The transactional processing resources may include speculative result storage 40, restoration data storage 32 or conflict detection circuitry 34 for supporting processing of transactions performed speculatively following a transaction start event whose results are committed following a transaction end event. The transactional processing resources may also include instruction decoding capability to decode transaction start/end instructions. Sharing transactional processing resources between the processing elements helps reduce energy consumption and circuit area.

Computer instructions indicating last-use for deactivating architectural registers

An ISA includes instructions for selectively indicating last-use of architected operands, such as a register or cache lines, having values that will not be accessed again. The instruction may be an operand deactivating instruction including an opcode field indicating a function to be performed 503 on an associated operand and an indication 501 of the last-use of that operand. Alternatively a prefix (or suffix) instruction indicating last-use of an operand in an associated instruction may be provided. The instruction(s) are executed 500, 506, a determination of last use is made 502, the function performed using the operand 503 before the operand is deactivated such as by setting a tag 507 for the operand 509 in register mapper 508 to a deactivate state and returning 505 the physical register to a free register pool 510. Reading a deactivated operand may return a default value; writing to a deactivated operand may activate the operand assigning a physical register from the pool.

Computer instructions for activating and deactivating operands

INDICATING PANEL MECHANISM IN A PIPELINE WITH RECEXECUTION AND FORWARDING OF INSTRUCTIONS

Nontransactional store instruction

A NONTRANSACTIONAL STORE instruction, executed in transactional execution mode, performs stores that are retained, even if a transaction associated with the instruction aborts. The stores include user-specified information that may facilitate debugging of an aborted transaction.

Coherence protocol augmentation to indicate transaction status

Embodiments relate to implementing a coherence protocol. An aspect includes sending a request for data to a remote processor and receiving by a processor a response from the remote processor. The response has a transaction status of a remote transaction on the remote processor. The processor adds the transaction status of the remote transaction on the remote processor in a local transaction interference tracking table.

BIDIRECTIONAL BRANCH PREDICTION AND OPTIMIZATION

A method and apparatus are described for conditional branching within a central processing unit of a digital computer. The central processing unit has a pipelined architecture where the fetch and execute cycles are overlapped to optimize the efficient execution of instructions. This novel conditional branching method and apparatus optimizes the use of instructions fetched into the pipeline by maximizing the use of the delay slot instruction thereby eliminating the need to interlock the pipeline or otherwise delay execution of instructions.

MULTIPROCESSOR SYSTEM WITH MULTIPLE INSTRUCTION SOURCES

Digital multiprocessor methods and apparatus comprise a plurality of processors, including a first processor for normally processing an instruction stream including instructions from a first instruction source. At least one of the processors can transmit inserted-instructions to the first processor. Inserted-instructions are executed by the first processor in the same manner as, and without affecting the sequence of, instructions from the first instruction source. The first instruction source can be a memory element, including an instruction cache element for storing digital values representative of instructions and program steps, or an execution unit (CEU) which asserts signals to the instruction cache element to cause instructions to be transmitted to the CEU. The processors include input/output (I/O) processors having direct memory access (DMA) insert elements, which respond to a peripheral device to generate DMA inserted-instructions. These DMA inserted-instructions are executable by ...

Data processing apparatus and method for performing speculative vector access operations

APPARATUS AND METHOD FOR NON-BLOCKING EXECUTION OF A STATIC SCHEDULED PROCESSOR

정적 스케쥴 프로세서의 논블로킹 실행 장치 및 방법에 관한 것으로서, 전달되는 입력 데이터를 이용하여 적어도 하나 이상의 연산을 처리하는 프로세서, 및 상기 입력 데이터를 상기 프로세서에 전달하고, 상기 적어도 하나 이상의 연산에 대한 처리 결과를 저장하는 입력 버퍼를 포함하고, 상기 프로세서는 상기 적어도 하나 이상의 연산을 각각 수행하는 적어도 하나 이상의 연산 유닛을 포함하고, 상기 적어도 하나 이상의 연산 유닛은 상기 전달되는 입력 데이터를 레귤러 레이턴시의 연산 및 이레귤러 레이턴시의 연산 중에서 적어도 하나의 연산을 이용하여 처리할 수 있다. An apparatus and method for non-blocking execution of a static schedule processor, comprising: a processor for processing at least one or more operations by using input data to be transmitted, and a result of processing the input data to the processor and processing the at least one or more operations And an input buffer configured to store an input buffer, wherein the processor includes at least one calculation unit configured to perform the at least one calculation operation, and the at least one calculation unit is configured to perform regular latency calculation and regularity on the transferred input data. Processing may be performed using at least one of the operations of the latency.

A DATA PROCESSING APPARATUS AND METHOD FOR PERFORMING SPECULATIVE VECTOR ACCESS OPERATIONS

SAVING/RESTORING SELECTED REGISTERS IN TRANSACTIONAL PROCESSING

Cache metadata for implementing bounded transactional memory

Various technologies and techniques are disclosed for providing a bounded transactional memory application that accesses cache metadata in a cache of a central processing unit. When performing a transactional read from the bounded transactional memory application, a cache line metadata transaction-read bit is set. When performing a transactional write from the bounded transactional memory application, a cache line metadata transaction-write bit is set and a conditional store is performed. At commit time, if any lines marked with the transaction-read bit or the transaction-write bit were evicted or invalidated, all speculatively written lines are discarded. The application can also interrogate a cache line metadata eviction summary to determine whether a transaction is doomed and then take an appropriate action.

METHODS AND APPARATUS FOR INITIATING AND RESYNCHRONIZING MULTI-CYCLE SIMD INSTRUCTIONS

L'invention porte sur des techniques visant à ajouter plusieurs instructions complexes et leurs unités d'exécution attenantes à plusieurs cycles, dotées d'une structure de traitement de mots d'instruction très longs d'un flux SIMD. Selon une réalisation, un mécanisme de déclenchement agit également comme mécanisme de resynchronisation pour lire les résultats de l'exécution à plusieurs cycles. Ce mécanisme polyvalent fonctionne avec une sortie à mot d'instruction court de l'instruction multicycle, dans un processeur de séquences seul, avec un mot d'instruction très long, et parmi tous les éléments de traitement pris individuellement ou sous forme d'un ensemble. L'invention porte également sur un nombre d'instructions à virgule flottante.

SEQUENTIAL PROCESSOR COMPRISING AN ALU ARRAY

The present invention discloses a single chip sequential processor comprising at least one ALU-Block wherein said sequential processor is capable of maintaining its opcodes while processing data such as to overcome the necessity of requiring a new instruction in every clock cycle.

Block-based processor core composition register

Systems, apparatuses, and methods related to a block-based processor core composition register are disclosed. In one example of the disclosed technology, a processor can include a plurality of block-based processor cores for executing a program including a plurality of instruction blocks. A respective block-based processor core can include one or more sharable resources and a programmable composition control register. The programmable composition control register can be used to configure which resources of the one or more sharable resources are shared with other processor cores of the plurality of processor cores.

MANAGEMENT OF STORE QUEUE BASED ON RESTORATION OPERATION

Management of a store queue based on a restoration operation. A determination is made as to whether a restoration operation to perform a bulk restore of a set of architected registers has completed. Based on determining that the restoration operation has completed, one or more store queue entries corresponding to the restoration operation are invalidated.

Runtime Extraction of Data Parallelism

Mechanisms for extracting data dependencies during runtime are provided. The mechanisms execute a portion of code having a loop and generate, for the loop, a first parallel execution group comprising a subset of iterations of the loop less than a total number of iterations of the loop. The mechanisms further execute the first parallel execution group and determining, for each iteration in the subset of iterations, whether the iteration has a data dependence. Moreover, the mechanisms commit store data to system memory only for stores performed by iterations in the subset of iterations for which no data dependence is determined. Store data of stores performed by iterations in the subset of iterations for which a data dependence is determined is not committed to the system memory.

Indicating nearing the completion of a transaction

In a multi-processor transaction execution environment, a transaction executes a hint instruction indicating proximity to completion of the transaction. Pending aborts of the transaction due to memory conflicts are suppressed based on the proximity of the transaction to completion.

Unified store buffer

Techniques are disclosed relating to speculative execution of store instructions. In various embodiments, an integrated circuit includes an execution pipeline having a load store circuit. The load store circuit is configured to receive a first store instruction executable to store a first value in a memory accessible to the integrated circuit. Prior to the first store instruction committing, the load store circuit stores the first value in a store buffer. In response to the first store instruction committing, the load store circuit stores, in the store buffer, an indication that the first store instruction has committed. In various embodiments, the integrated circuit reads the stored indication to determine whether the first store instruction has committed and, responsive to the read indication, provides the first value for storage in the memory.

ARITHMETIC PROCESSING DEVICE AND METHOD OF CONTROLLING ARITHMETIC PROCESSING DEVICE

An arithmetic processing device includes: a first register configured to hold data to be used to execute an instruction; a second register configured to hold a portion of the data held in the first register; a computing circuit configured to execute computation using the data held in the second register; a first error detector configured to detect whether or not an error is included in the data to be transferred by the first register to the second register; a controller configured to interrupt the execution of the instruction if the first error detector detects the error in the data; and an error corrector configured to correct the error in the data held in the first register if the first error detector detects the error in the data.

IMPLICIT PROGRAM ORDER

Apparatus and methods are disclosed for controlling execution of memory access instructions in a block-based processor architecture using a hardware structure that generates a relative ordering of memory access instruction in an instruction block. In one example of the disclosed technology, a method of executing an instruction block having a plurality of memory load and/or memory store instructions includes decoding an instruction block encoding a plurality of memory access instructions and generating data indicating a relative order for executing the memory access instructions in the instruction block and scheduling operation of a portion of the instruction block based at least in part on the relative order data. In some examples, a store vector data register can store the generated relative ordering data for use in subsequent instances of the instruction block.

DETECTING AND RECOVERING FROM TIMING VIOLATIONS OF A PROCESSOR

A system for detecting and correcting invalid calculation results due to a timing violation. A processor compares results of an instruction simultaneously executed by a first arithmetic pipeline and a second arithmetic pipeline of the processor. In the second arithmetic pipeline, the critical stage of the first arithmetic pipeline is divided to multiple stages. A first result calculated by the first arithmetic pipeline is speculatively executed within the processor. The second arithmetic pipeline calculates a second result. The processor compares the second result to the first result. When the results are identical, the first result is assigned as the final result with a complete status. When the results do not match, the processor replaces the first result with the second result. The processor may then cancel the speculatively executed instruction and issue the second result as a final result. The processor may then restart subsequent instructions using the second result.

Intra-instructional transaction abort handling

Embodiments relate to intra-instructional transaction abort handling. An aspect includes using an emulation routine to execute an instruction within a transaction. The instruction includes at least one unit of operation. The transaction effectively delays committing stores to memory until the transaction has completed successfully. After receiving an abort indication, emulation of the instruction is terminated prior to completing the execution of the instruction. The instruction is terminated after the emulation routine completes any previously initiated unit of operation of the instruction.

OPERATION OF A MULTI-SLICE PROCESSOR WITH SPECULATIVE DATA LOADING

Operation of a multi-slice processor that includes a plurality of execution slices and a plurality of load/store slices coupled via a results bus includes: retrieving, from the results bus into an entry of a register file of an execution slice, speculative result data of a load instruction generated by a load/store slice; and determining, from the load/store slice after expiration of a predetermined period of time, whether the result data is valid.

SYSTEMS, METHODS, AND APPARATUSES FOR HETEROGENEOUS COMPUTING

The present disclosure provides a method and an apparatus comprising a decoder to decode an enqueue command instruction, execution circuitry, where execution of the enqueue command instruction causes the execution circuitry to: generate a work descriptor based, at least in part, on data from a source operand of the enqueue command instruction, the work descriptor comprising a plurality of fields including an operation field to specify one or more operations to be performed, a flag to indicate whether the work descriptor can be processed in parallel with one or more other work descriptors, and an address field associated with the one or more operations and to store the work descriptor to a work queue.

Kennzeichnung von Befehlsergebnissen im Prozessor mit Gegenflusspipeline

MIKROBEFEHLGESTEUERTE ARITHMETISCHE STEUEREINHEIT

ABLAUFSTEUERUNG ZUM AUSGEBEN UND WIEDERAUSGEBEN VON KETTEN ABHÄNGIGER BEFEHLE

Managing a multi-level cache hierarchy for architectural registers in a multithreaded processor

A multi-level register hierarchy comprises a first level pool of registers 507 for caching registers of a second level pool of registers 506 in a system wherein programs can dynamically release and re-enable architected registers such that released architected registers need not be maintained by the processor, the processor accessing operands through the first level pool of registers. The registers are assigned to each pool by associating with an entry 502 in one of the register pools. Where a last-use instruction is identified as having a last use of an architected register, that register is unassigned from both first and second level pools once the instruction is executed, allowing the entry to be reassigned to another register. The first level pool may hold recently accessed, or frequently accessed, registers.

Executing Groups of Instructions Atomically

Epoch-based determination of completion of barrier termination command

SAVING/RESTORING SELECTED REGISTERS IN TRANSACTIONAL PROCESSING

A transaction begin instruction begins execution of a transaction and includes a general register save mask having bits, that when set, indicate registers to be saved in the event the transaction is aborted. At the beginning of the transaction, contents of the registers are saved in memory not accessible to the program, and if the transaction is aborted, the saved contents are copied to the registers.

INSTRUCTION RESULT LABELING IN A COUNTERFLOW PIPELINE PROCESSOR

The present invention provides an efficient streamlined pipeline for a counterflow pipeline processor with a renaming table. The counterflow pipeline includes an execution pipe having multiple instruction stages forming an instruction pipe, a plurality of result stages forming a result pipe, and a corresponding plurality of comparator/inserters. Each comparator/inserter couples an instruction stage to a corresponding result stages. The counterflow pipeline also includes a register exam stage with the renaming table. The renaming table has entries for associating each register value of an instruction with a unique renamed register number (RRN), thereby eliminating the need for arbitration and housekeeping (killing of stale register values), as instructions and their respective register values counterflow in the streamlined counterflow pipeline. An RRN counter, such as a modulo counter, is coupled to the renaming table and provides unique RRNs for assignment to new register values. In accordance with one embodiment of the invention, instructions are decoded and unique RRNs assigned to the source and destination operand registers. If there is no previous RRN assigned to a register operand, its register value is retrieved from a register file and inserted into the top of the result pipe. In addition, when an instruction execution produces a register result value in the execution pipe, the associated RRN and register value are inserted laterally into the result pipe. The register values and RRNs, in the form of result packages, are garnered by younger (later in program order) instructions counterflowing up the instruction pipe.

Intelligent context management

Method and apparatus for delaying a load miss flush until issuing the dependent instruction

METHODS AND APPARATUS FOR INITIATING AND RESYNCHRONIZING MULTI-CYCLE SIMD INSTRUCTIONS

L'invention porte sur des techniques visant à ajouter plusieurs instructions complexes et leurs unités d'exécution attenantes à plusieurs cycles, dotées d'une structure de traitement de mots d'instruction très longs d'un flux SIMD. Selon une réalisation, un mécanisme de déclenchement agit également comme mécanisme de resynchronisation pour lire les résultats de l'exécution à plusieurs cycles. Ce mécanisme polyvalent fonctionne avec une sortie à mot d'instruction court de l'instruction multicycle, dans un processeur de séquences seul, avec un mot d'instruction très long, et parmi tous les éléments de traitement pris individuellement ou sous forme d'un ensemble. L'invention porte également sur un nombre d'instructions à virgule flottante.

Efficient and consistent software transactional memory

A method and apparatus for efficient and consistent validation/conflict detection in a Software Transactional Memory (STM) system is herein described. A version check barrier is inserted after a load to compare versions of loaded values before and after the load. In addition, a global timestamp (GTS) is utilized to track a latest committed transaction. Each transaction is associated with a local timestamp (LTS) initialized to the GTS value at the start of a transaction. As a transaction commits it updates the GTS to a new value and sets versions of modified locations to the new value. Pending transactions compare versions determined in read barriers to their LTS. If the version is greater than their LTS indicating another transaction has committed after the pending transaction started and initialized the LTS, then the pending transaction validates its read set to maintain efficient and consistent transactional execution.

Pre-arbitrated bypasssing in a speculative execution microprocessor

A pre-arbitrated bypassing system in a speculative execution microprocessor is provided. The bypassing system provides execution units enhanced to include a comparator and an enabled driver. The comparator compares a bypass address that is broadcast upon instruction decode with the destination address within each execution unit. If there is a match, then the result data is driven onto the bypass bus. Additionally, a suppress signal and validation scheme/apparatus are included to ensure that valid data is being driven onto the bypass bus. A bypass bus and associated apparatus may be included for every potential source operand.

Scheduler which retries load/store hit situations

A scheduler issues memory operations without regard to whether or not resources are available to handle each possible execution outcome of that memory operation. The scheduler also retains the memory operation after issuance. If a condition occurs which prevents correct execution of the memory operation, the memory operation is retried. The scheduler subsequently reschedules and reissues the memory operation in response to the retry. Additionally, the scheduler may receive a retry type indicating the reason for retry. Certain retry types may indicate a delayed reissuance of the memory operation until the occurrence of a subsequent event. In response to such retry types, the scheduler monitors for the subsequent event and delays reissuance until the event is detected. The scheduler may include a physical address buffer to detect a load memory operation which incorrectly issued prior to an older store memory operation upon which it is dependent for the memory operation. The scheduler may ...

Hybrid tracking of transaction read and write sets

Embodiments of the invention relate to tracking processor transactional read and write sets, thereby eliminating speculative mispredictions. Both non-speculative read set and write set indications are maintained for a transaction. The indications are stored in cache. In addition, load and write queues of addresses are maintained. The load queue of addresses relates to speculative members of a read set and the write queue of addresses relates to speculating member of a write set. For a received read request, a transaction resolution process takes place, and a resolution is performed if an address match in the write queue is detected. Similarly, for a receive write request the transaction interference additionally checks the load queue and the non-speculative read set for the pending address.

Vector instructions composed from scalar instructions

A processing system includes left and right data path processors configured to execute instructions issued from an instruction cache. A vector instruction includes a first word configured for execution by the left data path processor and a second word configured for execution by the right data path processor. The first and second words are issued in the same clock cycle from the instruction cache, and are interlocked to jointly specify a single vector instruction. The first and second words include code for vector operation and code for vector control. The first and second words are concurrently executed to complete the vector operation, free-of any other instructions issued from the instruction cache.

ISSUING INSTRUCTIONS TO MULTIPLE EXECUTION UNITS

A single chip sequential processor comprising at least one ALU-Block, where said sequential processor is capable of maintaining its op-codes while processing data such as to overcome the necessity of requiring a new instruction in every clock cycle. 1. A microprocessor comprising:an arrangement of a plurality of data processing units;a plurality of data load units operative to load data from data memory;an instruction fetch unit operative to fetch instructions from instruction memory;an instruction decode unit operative to decode the fetched instructions for execution on the microprocessor; andan instruction issue unit operative to issue the decoded instructions, in instruction order of source code, to the data processing units,one or more of the data processing units operative to process the issued instructions upon arrival, at the one or more data processing units, of operand data of the data via a bus from a data load unit of the plurality of data load units or from a different data processing unit of the plurality of data processing units.2. The microprocessor of wherein the instruction issue unit is operative to issue instructions by linearly advancing through a two-dimensional array of the plurality of data processing units in a row-wise and column-wise order in which one or more opcodes are issued to a first row of the two-dimensional array of the plurality of data processing units in successive columns and then one or more successive opcodes are issued to a next row of the two-dimensional array of the plurality of data processing units in the successive columns.3. The microprocessor of wherein the one or more opcodes are issued to the first row of the two-dimensional array of the plurality of data processing units until the first row is completed or a termination is detected claim 2 , and then the one or more successive opcodes are issued to the next row of the two-dimensional array of the plurality of data processing units.4. The microprocessor of wherein ...

Dynamic prediction of hardware transaction resource requirements

A transactional memory system dynamically predicts the resource requirements of hardware transactions. A processor of the transactional memory system predicts resource requirements of a first hardware transaction to be executed based on a resource hint, a type of hardware transaction that is associated with a given hardware transaction, and a previous execution of a prior hardware transaction that is associated with the type of hardware transaction. The processor allocates resources for the given hardware transaction based on the predicted resource requirements. The processor initiates execution of the first hardware transaction using at least a portion of the allocated resources.

Digital signal processing apparatus

The present invention relates to a digital signal processing apparatus comprising a plurality of available hardware resource means and a first instruction set means having access to said available hardware resource means, so that at least a part of said hardware resource means execute operations under control of said first instruction set means, and further comprising a second instruction set means having access to only a predetermined limited subset of said plurality of available hardware resource means, so that at least a part of said predetermined limited subset of said hardware resource means execute operations under control of said second instruction set means. Further, the present invention relates to a method for processing digital signals in a digital signal processing apparatus comprising a plurality of available hardware resource means, wherein at least a part of said hardware resource means execute operations under control of a first instruction set, and wherein at least a part ...

Dual Path Issue for Conditional Branch Instructions

A method and apparatus for executing branch instructions is provided. In one embodiment, the method includes receiving a branch instruction and issuing one or more instructions from a first path of the branch instruction and one or more instructions from a second path of the branch instruction. If the first path of the branch instruction is followed by the branch instruction, the one or more instructions from the second path of the branch instruction are invalidated. If the second path of the branch instruction is followed by the branch instruction, the one or more instructions from the first path of the branch instruction are invalidated.

INSTRUCTIONS FOR REMOTE ATOMIC OPERATIONS

Disclosed embodiments relate to atomic memory operations. In one example, a method of executing an instruction atomically and with weak order includes: fetching, by fetch circuitry, the instruction from code storage, the instruction including an opcode, a source identifier, and a destination identifier, decoding, by decode circuitry, the fetched instruction, selecting, by a scheduling circuit, an execution circuit among multiple circuits in a system, scheduling, by the scheduling circuit, execution of the decoded instruction out of order with respect to other instructions, with an order selected to optimize at least one of latency, throughput, power, and performance, and executing the decoded instruction, by the execution circuit, to: atomically read a datum from a location identified by the destination identifier, perform an operation on the datum as specified by the opcode, the operation to use a source operand identified by the source identifier, and write a result back to the location. 1. A processor to execute an instruction atomically and with weak order , the processor comprising:fetch circuitry to fetch the instruction from a code storage, the instruction comprising an opcode, a source identifier, and a destination identifier;decode circuitry to decode the fetched instruction; anda scheduling circuit to select an execution circuit among multiple circuits in the system to execute the instruction, the scheduling circuit further to schedule execution of the decoded instruction out of order with respect to other instructions, with an order selected to optimize at least one of latency, throughput, power, and performance;wherein the execution circuit is to execute the decoded instruction out of order with respect to other instructions, with an order selected to optimize at least one of latency, throughput, power, and performance, wherein the executing comprises atomically reading a datum from a location identified by the destination identifier, performing an ...

REGULATING HARDWARE SPECULATIVE PROCESSING AROUND A TRANSACTION

A transaction is detected. The transaction has a begin-transaction indication and an end-transaction indication. If it is determined that the begin-transaction indication is not a no-speculation indication, then the transaction is processed. 1. A method comprising:determining, by one or more computer processors, that instructions preceding a transaction have not completed;prohibiting, by one or more computer processors, the transaction from being processed until a determination is made that indicates that all pending outside instructions are not, or are no longer, being processed in a speculative manner; anddetermining, by one or more computer processors, that an end-transaction indication associated with the transaction indicates an end to a period of no-speculation transaction processing.2. The method of claim 1 , wherein the transaction comprises two or more instructions to be processed atomically on a data structure in a memory.3. The method of claim 1 , the method comprising:determining, by one or more computer processors, that a begin-transaction indication associated with a transaction is a no-speculation indication, wherein the begin-transaction indication is selected from the group consisting of: a new instruction, a new prefix instruction, or a variant of an instruction in a current instruction set architecture.4. The method of claim 1 , the method comprising:determining, by one or more computer processors, that the instructions preceding the transaction have completed; andresponsive to determining that the instructions preceding the transaction have completed, processing, by one or more computer processors, the transaction.5. The method of claim 4 , the method comprising:responsive to processing the transaction, determining, by one or more computer processors, whether an end-transaction indication associated with the transaction is a no-speculation indication; andresponsive to determining that the end-transaction indication is the no-speculation ...

TECHNIQUES TO IDENTIFY IMPROPER INFORMATION IN CALL STACKS

Embodiments are disclosed for obtaining a call stack for binaries, where the call stack includes a sequence of frames, and each frame has a “from” address and a “to” address for a call instruction, and for determining basic blocks of instructions for the binaries, where each basic block of instruction has one or more instructions. Further, the embodiments include traversing the call stack to validate from/to address pairs of sequential frames based on control flow routes existing between “from” addresses and “to” addresses of the from/to address pairs, where each from/to address pair has a “from” address of a frame and a “to” address of an immediate previous frame on the call stack. 1. An apparatus , comprising:memory to store executable computer program instructions; and obtain a call stack for binaries of data associated with one or more call instructions, the call stack comprising a sequence of frames, each frame comprising a “from” address and a “to” address for a call instruction;', 'determine basic blocks of instructions for the binaries, each basic block of instructions comprising one or more instructions; and', 'traverse the call stack to validate from/to address pairs of sequential frames based on control flow routes existing between “from” addresses and “to” addresses of the from/to address pairs associated with the basic blocks of instructions, each from/to address pair comprising a “from” address of a frame and a “to” address of an immediate previous frame on the call stack., 'processing circuitry coupled with the memory, the processing circuitry operable to execute the instructions, that when executed, enable the processing circuitry to2. The apparatus of claim 1 , the processing circuitry is further to:trace a control flow route from a “to” address to a “from” address of an from/to address pair associated with the basic blocks of instruction;validate the frame having the “to” address responsive to at least one control flow route that can be traced; ...

Computer Processor Employing Operand Data With Associated Meta-Data

A computer processor is provided that employs a plurality of operand storage elements that store operand data values and associated meta-data as unitary operand data elements as well as at least one functional unit that performs operations that produce and access the unitary operand data elements stored in the plurality of operand storage elements. The meta-data associated with a given operand data value as part of a unitary operand data element can specify type of the unitary operand data element (e.g., vector or scalar), elemental width and floating-point error flags. The meta-data can also be used to define special operand data values (e.g., Not-a-Result and None). The meta-data is useful in optimizing execution, such as in speculation and vectorized SIMD operations. The computer processor can also support a number of particular vector operations that are useful in optimizing execution of vectorized SIMD operations. 1. A computer processing method comprising:providing a memory system that includes cache and main memory, and at least one processor core that is operably coupled to the memory system, wherein the processor core includes at least one functional unit and a plurality of operand storage elements separate from the memory system, wherein the plurality of operand storage elements store operand data values and associated meta-data as unitary operand data elements, and wherein the at least one functional unit performs operations that access the respective unitary operand data elements stored in the plurality of operand storage elements;in response to a load operation that specifies a memory address for loading at least one operand data value, operating the processor core to construct a given unitary operand data element by generating meta-data corresponding to the load operation, using the memory address to load the at least one operand data value from the memory system to the processor core, and combining the meta-data generated by the processor core with at ...

PREFETCH INSENSITIVE TRANSACTIONAL MEMORY

Processing prefetch memory operations and transactions. A local processor receives a write prefetch request from a remote processor. Prior to execution of a write prefetch request received from a remote processor, determining whether a priority of the write prefetch request is greater than a priority of a pending transaction of a local processor. The write prefetch request is executed in response to a determination that the priority of the write prefetch request is greater than the priority of a pending transaction. Prefetch data produced by execution of the write prefetch request is provided to the remote processor. 1. A method of processing prefetch memory operations and transactions , the method comprising: prior to execution of a write prefetch request received from a remote processor, determining, by one or more processors, whether a priority of the write prefetch request is greater than a priority of a pending transaction of a local processor;', 'executing, by the one or more processors, the write prefetch request in response to a determination that the priority of the write prefetch request is greater than the priority of the pending transaction; and', 'providing, by the one or more processors, a prefetch data associated with the executed write prefetch request to the remote processor., 'during a first time period2. The method of claim 1 , the method further comprising:prior to execution of the write prefetch request, determining, by the group of one or more processors, that the write prefetch request conflicts with the pending transaction of the local processor based on a comparison of memory addresses that are accessed by the write prefetch request to memory addresses that are accessed by the pending transaction.3. The method of claim 1 , wherein the write prefetch request includes program instructions to move data from a first memory to a second memory based on an anticipated access of the data by the remote processor claim 1 , wherein the second memory ...

METHOD AND APPARATUS FOR FLUSHING INSTRUCTIONS FROM RESERVATION STATIONS

A processor may include a reorder buffer, reservation stations, and execution units. The reorder buffer may be a circular buffer with a head pointer and a tail pointer, configured to assign indexes to instructions. Reservation stations may be configured to host instructions with the assigned indexes, while waiting to be issued to the execution units. Responsive to exception event, reservation stations may be configured to flush instructions that are younger, in program order, than the instruction executed with exception. Execution units may provide the reorder buffer index EX of the instruction executed with exception. The reorder buffer may provide the reorder buffer index TP stored in the tail pointer. Reservation stations may be configured to flush instructions with assigned indexes in the wrapped-around increasing interval from the index EX to the index TP. 1. A method comprising:allocating entries of a circular buffer, wherein each circular buffer entry is identified with an index from an interval of consecutive integers;maintaining a pointer, wherein the pointer may point to a not allocated circular buffer entry, or to a circular buffer entry allocated before other allocated circular buffer entries, or to a circular buffer entry allocated after other allocated circular buffer entries;comparing a first index of a first allocated circular buffer entry with a second index of a second allocated circular buffer entry;comparing the pointer with the first index;comparing the pointer with the second index; 'determining that the first allocated entry was allocated before the second allocated entry,', 'if the first index is smaller than the second index and the pointer is smaller than or equal to both the first index and the second index, or the first index is smaller than the second index and the pointer is larger than or equal to both the first index and the second index, or the first index is larger than the second index and the pointer is smaller than or equal to ...

PREFETCH INSENSITIVE TRANSACTIONAL MEMORY

Processing prefetch memory operations and transactions. A local processor receives a prefetch request from a remote processor. Prior to execution of the prefetch request, determining whether a priority of the remote processor is greater than a priority of a local processor. The write prefetch request is executed in response to a to a determination that the priority of the remote processor is greater than the priority of the local processor. Prefetch data produced by execution of the prefetch request is provided to the remote processor. 1. A method of processing prefetch memory operations and transactions , the method comprising: prior to execution of a prefetch request received from a remote processor, determining whether a priority of the remote processor is greater than a priority of a local processor;', 'executing the prefetch request in response to a determination that the priority of the remote processor is greater than the priority of the local processor; and', 'providing a prefetch data associated with the executed prefetch request to the remote processor., 'during a first time period2. The method of claim 1 , the method further comprising:prior to execution of the prefetch request, determining, by the group of one or more processors, whether the prefetch request conflicts with a transaction of the local processor based on a comparison of (i) reads and writes of the prefetch request to (ii) reads and writes of the transaction.3. The method of claim 1 , wherein the prefetch request is at least one of (i) a read prefetch request and (ii) a write prefetch request that includes program instructions to move data from a first memory to a second memory based on an anticipated access of the data by the remote processor claim 1 , wherein the second memory has a lower memory level relative to the remote processor when compared with a memory level of the first memory relative to the remote processor.4. The method of claim 1 , the method further comprising: 'responsive ...

GRAPHICS ENGINE RESET AND RECOVERY IN A MULTIPLE GRAPHICS CONTEXT EXECUTION ENVIRONMENT

Methods, systems and apparatuses may provide for technology that triggers an idle state in a first command streamer in response to a request to reset a second command streamer that shares graphics hardware with the first command streamer. The technology may also determine an event type associated with the request and conduct the request based on the event type. 1. A computing system comprising:a memory device;a host processor coupled to the memory device; and trigger an idle state in a first command streamer in response to a request to reset a second command streamer that shares the graphics hardware with the first command streamer,', 'determine an event type associated with the request, and', 'conduct the reset based on the event type., 'a graphics processor including graphics hardware and logic to2. The computing system of claim 1 , wherein the logic is to invalidate one or more contexts in the graphics hardware based on the event type.3. The computing system of claim 2 , wherein a proxy context and a direct context are invalidated if the event type is a host reset request.4. The computing system of claim 2 , wherein a hung context is invalidated if the event type is an expiry reset request.5. The computing system of claim 1 , wherein the reset includes a media reset flow if the event media type is a media reset request.6. The computing system of claim 1 , wherein the logic is to send a reset completion message to a host processor claim 1 , and wherein the memory device includes instructions claim 1 , which when executed by the host processor claim 1 , cause the host processor to acknowledge the reset completion message with a special work item.7. A semiconductor apparatus comprising:one or more substrates; andlogic coupled to the one or more substrates, wherein the logic is implemented at least partly in one or more of configurable logic or fixed-functionality hardware logic, the logic coupled to the one or more substrates to:trigger an idle state in a first ...

TRANSACTION BEGIN/END INSTRUCTIONS

A TRANSACTION BEGIN instruction and a TRANSACTION END instruction are provided. The TRANSACTION BEGIN instruction causes either a constrained or nonconstrained transaction to be initiated, depending on a field of the instruction. The TRANSACTION END instruction ends the transaction started by the TRANSACTION BEGIN instruction. 1. A computer program product for executing a machine instruction in a computing environment , said computer program product comprising: [ an operation code to specify a transaction begin operation; and', 'one or more fields to specify a first operand address; and, 'obtaining a machine instruction for operation, the machine instruction being defined for computer execution according to a computer architecture, the machine instruction comprising, determining, using a field of the machine instruction, whether a transaction to be initiated by the machine instruction is a constrained transaction or a nonconstrained transaction;', 'based on the field being one value, initiating a constrained transaction, the constrained transaction having one or more restrictions associated therewith, and setting a condition code to indicate successful execution of the machine instruction; and', 'based on the field being another value: initiating a nonconstrained transaction; using the first operand address to designate a location of a transaction diagnostic block to store diagnostic information based on the nonconstrained transaction being aborted; and setting a condition code to indicate successful execution of the machine instruction., 'executing the machine instruction, the executing comprising], 'a computer readable storage medium readable by a processing circuit and storing instructions for performing a method comprising2. The computer program product of claim 1 , wherein the field comprises the operation code.3. The computer program product of claim 1 , wherein the machine instruction further comprises a control field claim 1 , the control field comprising a ...

MANAGING HISTORY INFORMATION FOR BRANCH PREDICTION

Branch history information characterizes results of branch instructions previously executed by a processor. A count is stored of a number of consecutive branch instructions previously executed by the processor whose results all indicate a not taken branch. In a first pipeline stage, a predicted branch result is provided based on at least a portion of the branch history information, and one or more of the branch history information, and the count, is updated based on the predicted branch result. In a second pipeline stage an actual branch result is provided based on an executed branch instruction, and the branch history information is updated based on the actual branch result. If the predicted branch result indicates a taken branch, the branch history information is updated based on the count, and if the predicted branch result indicates a not taken branch, the count is updated but not the branch history information. 1. An apparatus comprising:at least one processor executing instructions in a pipeline, the instructions including branch instructions;first storage for branch history information characterizing results of branch instructions previously executed by the processor;second storage for a count of a number of consecutive branch instructions previously executed by the processor whose results all indicate a not taken branch;first circuitry, in a first stage of the pipeline, configured to provide a predicted branch result based on at least a portion of the branch history information, and to update one or more of the branch history information, and the count, based on the predicted branch result; andsecond circuitry, in a second stage of the pipeline occurring later in the pipeline than the first stage, configured to provide an actual branch result based on an executed branch instruction, and to update the branch history information based on the actual branch result, if the predicted branch result indicates a taken branch, updating the branch history information ...

EMPLOYING A STACK ACCELERATOR FOR STACK-TYPE ACCESSES

A stack accelerator is employed for stack-type accesses. An instruction stream is scanned for stack-type accesses. These stack-type accesses may include push and pop stack operations. Based on identifying a stack-type access in the instruction stream, memory operations are replaced with one or more operations that access a stack in a stack accelerator. 1. A computer program product for facilitating processing within a computing environment , the computer program product comprising: identifying a stack-type access to perform an operation on a stack, the stack located in a stack accelerator of a processor; and', 'replacing, based on determining the stack-type access, one or more memory operations to perform the operation with one or more operations to perform the operation directly on the stack located in the stack accelerator., 'a computer readable storage medium readable by a processing circuit and storing instructions for performing a method comprising2. The computer program product of claim 1 , wherein the stack accelerator comprises a plurality of in-processor storage locations accessed based on relative position within the stack and absent use of an address.3. The computer program product of claim 2 , wherein the relative position is top of stack claim 2 , and wherein a particular in-processor location of the stack accelerator is accessed based on that particular location being associated with the top of stack.4. The computer program product of claim 1 , wherein the identifying comprises detecting one or more particular operations indicative of the stack-type access or detecting successive accesses to memory indicative of the stack-type access.5. The computer program product of claim 1 , wherein the stack-type access comprises a push-type operation to place a value on the stack claim 1 , and the replacing comprises replacing a store to memory operation with a write operation.6. The computer program product of claim 5 , wherein the replacing further comprises ...

ISSUING INSTRUCTIONS TO MULTIPLE EXECUTION UNITS

A single chip sequential processor comprising at least one ALU-Block, where said sequential processor is capable of maintaining its op-codes while processing data such as to overcome the necessity of requiring a new instruction in every clock cycle. 1. A processor comprising:a field of execution units arranged in at least a two-dimensional pattern, wherein the execution units receive a plurality of data words from a memory for processing, wherein an operation of each respective execution unit of the field of execution units is controlled by a respective instruction issued to the respective execution unit, the plurality of data words including the respective instruction,the processor having at least one operation mode in which one or more of the instructions remain valid for multiple clock cycles of the processor, wherein multiple data words of the plurality of data words are processed by the respective execution units during the multiple clock cycles,wherein result data produced by a first set of execution units of the field of execution units are transmitted via an interconnect structure to at least one execution unit of a second set of execution units of the field of execution units, andwherein, in the at least one operation mode, data transmission to and from the field of execution units is monitored and synchronized with the field of execution units outside the field of execution units by one or more synchronization units in communication with the field of execution units, and data processing in the field of execution units is performed such that no synchronization of the data processing is required between execution units inside the field of execution units.2. The processor according to claim 1 , wherein the one or more synchronization units include:a state machine, wherein in response to data not being available to the field of execution units, the state machine is configured to generate wait states for the field of execution units, andfirst-in-first-out units ...

Asynchronous flush and restore of distributed history buffer

Techniques are disclosed for performing a flush and restore of a history buffer (HB) in a processing unit. One technique inludes identifying one or more entries of the HB to restore to a register file in the processing unit. For each of the one or more HB entries, a determination is made whether to send the HB entry to the register file via a first restore bus or via a second restore bus, different from the first restore bus, based on contents of the HB entry. Each of the one or more HB entries is then sent to the register file via one of the first restore bus or the second restore bus, based on the determination.

DATA PROCESSING APPARATUS AND OPERATING METHOD THEREOF

A data processing apparatus includes a master device configured to transmit commands for destinations, a slave device including a plurality of command processing regions respectively corresponding to the destinations, and a controller configured to relay communication between the master device and the slave device. The controller assigns time stamp value to the commands as an initial value when the commands was received by the controller and increment the time stamp value every command arbitration cycle, selects a command having a largest time stamp value among the commands in a tournament manner by comparing commands having different destinations every command arbitration cycle, stores a command selection history of each comparison of commands, selects the command based on a command selection history corresponding to the compared commands when respective time stamp values of the compared commands are the same or substantially the same as each other. 1. A data processing apparatus , comprising:a master device configured to transmit commands for each destination which is a slave device to process a command;the slave device including a plurality of command processing regions respectively corresponding to the destinations; anda controller configured to relay communication between the master device and the slave device,wherein the controller assigns time stamp value to the commands as an initial value when the commands was received by the controller and increment the time stamp value every command arbitration cycle,selects a command having a largest time stamp value among the commands by comparing commands having different destinations every command arbitration cycle, stores a command selection history of each comparison of commands, selects the command based on a command selection history corresponding to the compared commands when respective time stamp values of the compared commands are the same or substantially the same as each other.2. The data processing apparatus ...

Content-Addressable Memory Filtering based on Microarchitectural State

Techniques are disclosed relating to filtering access to a content-addressable memory (CAM). In some embodiments, a processor monitors for certain microarchitectural states and filters access to the CAM in states where there cannot be a match in the CAM or where matching entries will not be used even if there is a match. In some embodiments, toggle control circuitry prevents toggling of input lines when filtering CAM access, which may reduce dynamic power consumption. In some example embodiments, the CAM is used to access a load queue to validate that out-of-order execution for a set of instructions matches in-order execution, and situations where ordering should be checked are relatively rare.

CONDITIONAL TRANSACTION END INSTRUCTION

A Conditional Transaction End (CTEND) instruction is provided that allows a program executing in a nonconstrained transactional execution mode to inspect a storage location that is modified by either another central processing unit or the Input/Output subsystem. Based on the inspected data, transactional execution may be ended or aborted, or the decision to end/abort may be delayed, e.g., until a predefined event occurs. For instance, when the instruction executes, the processor is in a nonconstrained transaction execution mode, and the transaction nesting depth is one at the beginning of the instruction, a second operand of the instruction is inspected, and based on the inspected data, transaction execution may be ended or aborted, or the decision to end/abort may be delayed, e.g., until a predefined event occurs, such as the value of the second operand becomes a prespecified value or a time interval is exceeded. 1. A computer program product for executing an instruction in a computing environment , said computer program product comprising: obtaining the instruction for execution, the instruction having associated therewith an operation code to specify a conditional transaction end operation; and', fetching an operand from a location specified by the instruction;', 'based on the operand comprising one value, ending a transaction associated with the instruction; and', 'based on the operand comprising another value, delaying completion of the instruction until a predefined action occurs., 'executing, by a processor, the instruction, the executing comprising], 'a computer readable storage medium readable by a processing circuit and storing instructions for performing a method comprising2. The computer program product of claim 1 , wherein based on the operand comprising a further value claim 1 , transactional execution of the transaction is aborted.3. The computer program product of claim 2 , wherein the further value comprises a negative value claim 2 , the one value ...

PREFETCH INSENSITIVE TRANSACTIONAL MEMORY

Prevention of a prefetch memory operation from causing a transaction to abort. A local processor receives a prefetch request from a remote processor. Prior to execution of the prefetch request, a processor determines whether the prefetch request conflicts with a transaction of the local processor. A processor responds to a determination that the priority of the prefetch request is greater than priority of the transaction, by (i) aborting the transaction (ii) executing the prefetch request, and (iii) providing requested prefetch data to the remote processor. 1. A method for controlling abort operations during processing of prefetch memory operations and transactions , the method comprising: receiving, by a local processor of a group of one or more processors, a prefetch request from a remote processor;', 'prior to execution of the prefetch request, determining, by the group of one or more processors, whether the prefetch request conflicts with a transaction of the local processor based on (i) a comparison of memory addresses that are accessed by the prefetch request to memory addresses that are accessed by the transaction and (ii) a comparison of a priority of the prefetch request with a priority of the transaction; and', 'responsive to a determination that the priority of the prefetch request is greater than priority of the transaction by (i) aborting the transaction (ii) executing the prefetch request, and (iii) providing requested prefetch data to the remote processor., 'during a first time period2. The method of claim 1 , wherein the prefetch request is at least one of (i) a read prefetch request and (ii) a write prefetch request that includes program instructions to move data from a first memory to a second memory based on an anticipated access of the data by the remote processor claim 1 , wherein the second memory has a lower memory level relative to the remote processor when compared with a memory level of the first memory relative to the remote processor.3. ...

PREFETCH INSENSITIVE TRANSACTIONAL MEMORY

Prevention of a prefetch memory operation from causing a transaction to abort. A local processor receives a prefetch request from a remote processor. Prior to execution of the prefetch request, a processor determines whether the prefetch request conflicts with a transaction of the local processor. A processor responds to a determination that the priority of the remote processor is greater than priority of the local processor by (i) aborting the transaction (ii) executing the prefetch request, and (iii) providing requested prefetch data to the remote processor. 1. A method for controlling abort operations during processing of prefetch memory operations and transactions , the method comprising: receiving, by a local processor of a group of one or more processors, a prefetch request from a remote processor;', 'prior to execution of the prefetch request, determining, by the group of one or more processors, whether the prefetch request conflicts with a transaction of the local processor based on (i) a comparison of reads and writes of the prefetch request to reads and writes of the transaction and (ii) a comparison of a priority of the local processor with a priority of the remote processor;', 'responsive to a determination that the priority of the remote processor is greater than priority of the local processor by (i) aborting the transaction (ii) executing the prefetch request, and (iii) providing requested prefetch data to the remote processor., 'during a first time period2. The method of claim 1 , wherein the prefetch request is at least one of (i) a read prefetch request and (ii) a write prefetch request that includes program instructions to move data from a first memory to a second memory based on an anticipated access of the data by the remote processor claim 1 , wherein the second memory has a lower memory level relative to the remote processor when compared with a memory level of the first memory relative to the remote processor.3. The method of claim 1 , the ...

CONDITIONAL TRANSACTION END INSTRUCTION

A Conditional Transaction End (CTEND) instruction is provided that allows a program executing in a nonconstrained transactional execution mode to inspect a storage location that is modified by either another central processing unit or the Input/Output subsystem. Based on the inspected data, transactional execution may be ended or aborted, or the decision to end/abort may be delayed, e.g., until a predefined event occurs. For instance, when the instruction executes, the processor is in a nonconstrained transaction execution mode, and the transaction nesting depth is one at the beginning of the instruction, a second operand of the instruction is inspected, and based on the inspected data, transaction execution may be ended or aborted, or the decision to end/abort may be delayed, e.g., until a predefined event occurs, such as the value of the second operand becomes a prespecified value or a time interval is exceeded. 1. A computer program product for executing an instruction in a computing environment , said computer program product comprising: obtaining the instruction for execution, the instruction having associated therewith an operation code to specify a conditional transaction end operation; and', fetching an operand from a location specified by the instruction;', 'based on the operand comprising one value, ending a transaction associated with the instruction; and', 'based on the operand comprising another value, delaying completion of the instruction until a predefined action occurs., 'executing, by a processor, the instruction, the executing comprising], 'a computer readable storage medium readable by a processing circuit and storing instructions for performing a method comprising2. The computer program product of claim 1 , wherein based on the operand comprising a further value claim 1 , transactional execution of the transaction is aborted.3. The computer program product of claim 2 , wherein the further value comprises a negative value claim 2 , the one value ...

Multi-nullification

Apparatus and methods are disclosed for nullifying memory store instructions and one or more registers identified in a target field of a nullification instruction. In some examples of the disclosed technology, an apparatus can include memory and one or more block-based processor cores configured to fetch and execute a plurality of instruction blocks. One of the cores can include a control unit configured, based at least in part on receiving a nullification instruction, to obtain an instruction identification for a memory access instruction of a plurality of memory access instructions and a register identification of at least one of a plurality of registers, based on a first and second target fields of the nullification instruction. The at least one register and the memory access instruction associated with the instruction identification are nullified. Based on the nullified memory access instruction, a subsequent memory access instruction is executed.

Rule-Based Monitoring Engine With Tracing Capabilities for Multi-Threaded Logging

A system and method embodied in a monitoring engine configured to create plug-ins to define functionality including rule-based configuration syntax adapted to intuitively and automatically launch the plug-ins as necessary in a software-based infrastructure or environment. The monitoring engine also includes a capability for tracing multi-threaded asynchronous logging onto a single file, by assigning a unique identification to each thread or rule initiated and facilitating each log according to a specific format and to formulate a combination of all the different thread identifications into a master unique identification that is easily traceable through an entire log file. 1. A system comprising:a processor; and execute an application program interface to operate a monitoring engine configured to monitor a particular functionality within a software-based infrastructure based on a rule-based configuration;', 'define, by the monitoring engine, three separate categories of plug-ins to formulate the plug-ins in rules, the plug-ins including a checker plug-in to return a value output after a checking operation, a validator plug-in to receive the value output and compare the value output to a threshold standard and return a status of a validation operation performed by the validator plug-in, and an action plug-in configured to perform a task after the validation operation indicates action is required; and', 'selectively launch the checker plug-in, the validator plug-in, and the action plug-in into the software-based infrastructure., 'memory storing instructions that, when executed, cause the processor to2. The system of claim 1 , wherein the monitoring engine comprises a plug-ins module adapted to use at least the same checker plug-in once for defining multiple rules.3. The system of claim 1 , wherein the plug-ins module comprises a checker module for adding the checker plug-in claim 1 , a validator module for adding the validation plug-in claim 1 , and an action module ...

SAVING AND RESTORING BRANCH PREDICTION STATE

A branch predictor is provided with a branch state buffer, branch prediction save circuitry responsive to a branch prediction save event associated with a given execution context to save at least a portion of the active branch prediction state associated with the given execution context to a branch state buffer; and branch prediction restore circuitry responsive to a branch prediction restore event associated with the given execution context to restore active branch prediction state based on previously saved branch prediction state stored in the branch state buffer for the given execution context. This is useful for reducing the performance impact of mitigating against speculative side-channel attacks. 1. An apparatus comprising:a processing element to process instructions of a plurality of execution contexts;a branch predictor to predict outcomes of branch instructions processed by the processing element based on active branch prediction state stored in a branch prediction store;branch prediction control circuitry responsive to an execution context switch from a first execution context to a second execution context to prevent the branch predictor predicting outcomes of branch instructions of the second execution context based on branch prediction state trained based on outcomes of previous branch instructions of the first execution context;branch prediction save circuitry responsive to a branch prediction save event associated with a given execution context to save at least a portion of the active branch prediction state associated with the given execution context to a branch state buffer; andbranch prediction restore circuitry responsive to a branch prediction restore event associated with the given execution context to restore active branch prediction state based on previously saved branch prediction state stored in the branch state buffer for the given execution context.2. The apparatus according to claim 1 , in which the branch prediction save circuitry is ...

Execution of instructions based on processor and data availability

A processor including an instruction fetcher to fetch instructions, a decoder to decode the instructions, at least one load unit adapted to load data, at least one execution unit adapted to perform arithmetic computations on the data by executing the fetched and decoded instructions, a register file adapted to store results of the arithmetic computations, and a multiplexer arrangement provided such that one or more units of the execution unit selectively obtain operands from one of: the register file or a unit used for arithmetic computation of a preceding instruction. The processor is adapted to process and execute the instructions such that processing of the instructions is started under the following conditions: the execution unit is ready for instruction execution, and data from the at least one load unit is available to the at least one execution unit.

Multi-Thread Synchronization Method and Electronic Device

A multi-thread synchronization method includes that a first thread requests to obtain a target lock. Then, the first thread checks the lock thread identifier field. The first thread checks the blocked thread quantity field when checking that the lock thread identifier field is a valid thread and is not the first thread. The first thread performs spin wait when checking that the blocked thread quantity field is less than a first threshold. When a quantity of times for spin wait reaches a second threshold and when it is checked that the lock thread identifier field is the valid thread and is not the first thread, the first thread performs an operation of adding 1 to the blocked thread quantity field, and suspends to enter a blocked state. 1. A method implemented by a first thread executed by an electronic device , wherein the method comprises:obtaining a first lockword of a target lock, wherein the first lockword comprises a lock thread identifier field indicating a second thread holding the target lock and a blocked thread quantity field indicating a quantity of third threads in a blocked state for the target lock;checking the lock thread identifier field;checking the blocked thread quantity field when the lock thread identifier field is a valid thread and is not the first thread;performing spin wait when the blocked thread quantity field is less than a first threshold; and performing a first operation of adding 1 to the blocked thread quantity field; and', 'suspending to enter the blocked state., 'when a quantity of times that the first thread performs spin wait reaches a second threshold and when the lock thread identifier field is the valid thread and is not the first thread2. The method of claim 1 , wherein after checking the blocked thread quantity field claim 1 , the method further comprises:identifying that the blocked thread quantity field is greater than or equal to the first threshold; and performing the first operation; and', 'suspending to enter the ...

APPARATUS AND METHOD FOR SEGMENTING A DATA STREAM OF A PHYSICAL LAYER

The invention introduces an apparatus for segmenting a data stream, installed in a physical layer, to include a host interface, a data register and a boundary detector. The data register is arranged to operably store data received from the host side through the host interface. The boundary detector is arranged to operably detect the content of a data register. When the data register includes a special symbol, the boundary detector outputs a starting address that the special symbol is stored in the data register to an offset register to update a value stored in the offset register, thereby enabling a stream splitter to divide data bits of the data register according to the updated value of the offset register. 1. An apparatus for segmenting a data stream , installed in a physical layer , comprising:a host interface, coupled to a host side;a data register, coupled to the host interface, arranged to operably store data received from the host side through the host interface; anda boundary detector, coupled to the data register, arranged to operably detect content of the data register; and output a starting address that a special symbol is stored in the data register to an offset register to update a value stored in the offset register when the data register comprises the special symbol, thereby enabling a stream splitter to divide data bits of the data register according to an updated value of the offset register,wherein the special symbol is not originally used to determine boundaries of each segment.2. The apparatus of claim 1 , wherein the physical layer is configured to an 8b/10b Serializer/Deserializer environment and the special symbol is a K.28.1 symbol that is sent by the host side during idle periods.3. The apparatus of claim 2 , wherein the boundary detector comprises:a plurality of output circuits, coupled to the offset register, each arranged to operably output a specific value to the offset register when being driven; anda plurality of comparators, arranged ...

Mechanism for detecting and handling a starvation of a thread in a multithreading processor environment

A method and multithread processor for detecting and handling the starvation of a thread. A counter associated with a first thread may be set with a pre-selected value. The counter may be updated in response to receiving a notification. The notification may indicate which, if any, group of instructions has been completed for the first and second threads. The counter may be updated in response to receiving the notification by decrementing a current value stored in the counter if the group of instructions is completed for the second thread and not for the first thread. If the value of the counter reaches a predetermined value, then a thread starvation condition may be detected for the first thread. That is, if the value of the counter reaches the predetermined value, then the first thread may be starved.

Backup device

Universal history buffer to support multiple register types

An approach is provided in which a mapper control unit receives first dispatch information corresponding to a first instruction that identifies a first register and a first register type. The mapper control unit dynamically configures a first history buffer entry to support the first register type and, in turn, stores content from the first register into the first history buffer entry. The mapper control unit then receives second dispatch information corresponding to a second instruction that identifies a second register and a second register type, which is different than the first register type. The mapper control unit dynamically configures a second history buffer entry to support the second register type and, in turn, stores content from the second register into the second history buffer entry.

History buffer with hybrid entry support for multiple-field registers

An approach is provided in which a mapper control unit receives dispatch information corresponding to an instruction that targets a first field in a first register and a second field in a second register, the first register being a first register type and the second register being a second register type. As such, the mapper control unit selects a history buffer entry in a history buffer that is adapted to concurrently store content corresponding to the first register type and the second register type. In turn, the mapper control unit stores first content from the first register's targeted first fields and second content from the second register's targeted second fields into the selected history buffer entry.

Pipelined microprocessor without interruption due to branching and its operating method

Saving/reset of selected registers at transaction processing

FIELD: physics, computation hardware. SUBSTANCE: invention relates to multiprocessor computation media, particularly, to transaction processing inside such computation media. Instruction "start the transaction" initiation of transaction execution and initiates the mask of saving of general purpose registers containing bits which if set specify the registers to be saved in the case of transaction reset. At the start of transaction content of registers is saved in the memory not accessible for the program and is said transaction is reset, saved content is copied into registers. EFFECT: higher rate of execution of transaction start instruction owing to the content of those registers specified directly by said saving mask. 14 cl, 21 dwg РОССИЙСКАЯ ФЕДЕРАЦИЯ (19) RU (11) (51) МПК G06F 17/00 (13) 2 562 424 C2 (2006.01) ФЕДЕРАЛЬНАЯ СЛУЖБА ПО ИНТЕЛЛЕКТУАЛЬНОЙ СОБСТВЕННОСТИ (12) ОПИСАНИЕ (21)(22) Заявка: ИЗОБРЕТЕНИЯ К ПАТЕНТУ 2012148585/08, 15.11.2012 (24) Дата начала отсчета срока действия патента: 15.11.2012 Приоритет(ы): (30) Конвенционный приоритет: (72) Автор(ы): Дан Ф. ГРЕЙНЕР (US), Кристиан ЯКОБИ (DE), Тимоти Дж. СЛИДЖЛ (US) 15.06.2012 US 13/524,882 (43) Дата публикации заявки: 20.05.2014 Бюл. № 14 R U (73) Патентообладатель(и): ИНТЕРНЭШНЛ БИЗНЕС МАШИНЗ КОРПОРЕЙШН (US) (45) Опубликовано: 10.09.2015 Бюл. № 25 2 5 6 2 4 2 4 R U (54) СОХРАНЕНИЕ/ВОССТАНОВЛЕНИЕ ВЫБРАННЫХ РЕГИСТРОВ ПРИ ТРАНЗАКЦИОННОЙ ОБРАБОТКЕ (57) Реферат: Изобретение относится к многопроцессорным и включает маску сохранения регистров общего вычислительным средам, а именно к назначения, имеющую биты, которые если транзакционной обработке внутри таких установлены, указывают регистры, которые вычислительных сред. Техническим результатом необходимо сохранить в случае сброса является повышение скорости выполнения транзакции. В начале транзакции содержимое команды начать транзакцию благодаря регистров сохраняется в памяти, не доступной сохранению содержимого только тех регистров, для программы, и если ...

Microprecessor operation protecting circuit from error instruction

내용 없음. No content.

Processor and information processing apparatus

본 발명은 컨디션 코드의 수에 의한 제한을 받지 않고 조건부 스토어 명령을 실행할 수 있는 프로세서를 제공하는 것을 목적으로 한다. An object of the present invention is to provide a processor capable of executing conditional store instructions without being limited by the number of condition codes. 조건 데이터를 부동 소수점 레지스터에 저장하고, 그 조건 데이터에 기초하여 스토어 데이터를 캐시에 스토어할지 아닐지를 판정하는 조건부 부동 소수점 스토어 명령을 연산부가 실행한다. The operation unit executes a conditional floating point store instruction that stores the condition data in a floating point register and determines whether to store the store data in the cache based on the condition data.

Method and apparatus for efficient utilization for prescient instruction prefetch

Embodiments of an apparatus, system and method enhance the efficiency of processor resource utilization during instruction prefetching via one or more speculative threads. Renamer logic and a map table are utilized to perform filtering of instructions in a speculative thread instruction stream. The map table includes a yes-a-thing bit to indicate whether the associated physical register's content reflects the value that would be computed by the main thread. A thread progress beacon table is utilized to track relative progress of a main thread and a speculative helper thread. Based upon information in the thread progress beacon table, the main thread may effect termination of a helper thread that is not likely to provide a performance benefit for the main thread.

Coherence protocol augmentation to indicate transaction status

Embodiments relate to implementing a coherence protocol. An aspect includes sending a request for data to a remote processor and receiving by a processor a response from the remote processor. The response has a transaction status of a remote transaction on the remote processor. The processor adds the transaction status of the remote transaction on the remote processor in a local transaction interference tracking table.

Speculative Region: Hardware Support for Selective Transactional Memory Access Annotation Using Instruction Prefix

A computer system and method is disclosed for executing selectively annotated transactional regions. The system is configured to determine whether an instruction within a plurality of instructions in a transactional region includes a given prefix. The prefix indicates that one or more memory operations performed by the processor to complete the instruction are to be executed as part of an atomic transaction. The atomic transaction can include one or more other memory operations performed by the processor to complete one or more others of the plurality of instructions in the transactional region.

Prefetch insensitive transactional memory

Prevention of a prefetch memory operation from causing a transaction to abort. A local processor receives a prefetch request from a remote processor. A processor determines whether the prefetch request conflicts with a transaction of the local processor. A processor responds to at least one of i) a determination that the local processor has no transaction, and ii) a determination that the prefetch request does not conflict with a transaction by providing a requested prefetch data by providing a requested prefetch data. A processor responds to a determination that the prefetch request conflicts with a transaction by suppressing a processing of the prefetch request.

Methods and apparatus for initiating and resynchronizing multi-cycle SIMD instructions

Techniques for adding more complex instructions and their attendant multi-cycle execution units with a single instruction multiple data, stream (SIMD) very long instruction word (VLIW) processing framework are described. In one aspect, an initiation mechanism also acts as a resynchronization mechanism to read the results of multi-cycle execution. This multi-purpose mechanism operates with a short instruction word (SIW) issue of the multi-cycle instruction, in a sequence processor (SP) alone, with a VLIW, and across all processing elements (PEs) individually or as an array of PEs. A number of advantageous floating point instructions are also described.

Enhanced coherence protocol to indicate transaction status

Unified functional operations scheduler for OUT-OF-ORDER execution in superscaler processors

Configurable co-processor interface

A configurable coprocessor interface between a central processing unit (CPU) and a coprocessor is provided. The coprocessor interface has an instruction transfer signal group for transferring different instruction types from the CPU to the coprocessor, sequentially or in parallel, a busy signal group, for allowing the coprocessor to signal the CPU that it cannot receive a transfer of one or more of the different instruction types, and an instruction order signal group for indicating to the coprocessor a relative execution order for multiple instructions that are transferred in parallel. In addition, the coprocessor interface includes separate data transfer signal groups for data being transferred from the CPU to the coprocessor, and for data being transferred from the coprocessor to the CPU, along with a data order signal group for indicating a relative order of data (if transferred out-of-order). The interface further includes signal designations which allow for multiple issue groups between the CPU and one or more coprocessors.

INCREASE OF COHERENCE PROTOCOL TO INDICATE THE STATUS OF THE TRANSACTION

AUMENTO DE PROTOCOLO DE COERÊNCIA PARA INDICAR O ESTADO DA TRANSAÇÃO. Concretizações referem-se à implementação de um protocolo de coerência. Um aspecto inclui o envio de um pedido de dados a um processador remoto e receber, por um processador, uma resposta do processador remoto. A resposta tem um estado de transação de uma transação remota no processador remoto. O processador adiciona o estado de transação da transação remota no processador remoto em uma tabela de rastreamento de interferência de transação local. INCREASE THE COHERENCE PROTOCOL TO INDICATE THE STATUS OF THE TRANSACTION. Achievements refer to the implementation of a coherence protocol. One aspect includes sending a request for data to a remote processor and receiving, by a processor, a response from the remote processor. The response has a transaction state of a remote transaction on the remote processor. The processor adds the transaction state of the remote transaction on the remote processor to a local transaction interference tracking table.

Register file backup queue

A register file backup system for use with a computer which processes instructions to generate results which thereby change the visual state of the computer. The computer has a register file with a plurality of addressable locations for storing data. The backup system is adapted to return the visual state of the computer to a previous state if an instruction generates an exception. The backup system utilizes less overhead so as to provide easier register file backup than a comparable software or hardware device. The backup system comprises first means for sequentially storing in program order, address information corresponding to destination locations in the register file where instruction results are to be stored. The first means has first and second outputs for transferring the address information stored therein: the first output being coupled to the register file for transferring a first portion of the address information to the register file, and the second output is used for transferring a second portion of address information for backup storage of the register file contents. The backup system also has a second means coupled to (1) the second output of the first means, for receiving and storing the second portion of the address information, and (2) the register file, for receiving and backup storing further information corresponding to the contents of one or more destination locations in the register file before that destination location is changed according to second portion of the address information. A third means is used for transferring the further information from the second means back to the register file locations according to the second portion of the address information stored in the second means after an instruction generates an exception.

Systems, methods and equipment for heterogeneous computing

Distinct system registers for logical processors

Distinct system registers for logical processors are disclosed. In one example of the disclosed technology, a processor includes a plurality of block-based physical processor cores for executing a program comprising a plurality of instruction blocks. The processor also includes a thread scheduler configured to schedule a thread of the program for execution, the thread using the one or more instruction blocks. The processor further includes at least one system register. The at least one system register stores data indicating a number and placement of the plurality of physical processor cores to form a logical processor. The logical processor executes the scheduled thread. The logical processor is configured to execute the thread in a continuous instruction window.

Computer instructions for activating and deactivating operands

An instruction set architecture (ISA) includes instructions for selectively indicating last-use architected operands having values that will not be accessed again, wherein architected operands are made active or inactive after an instruction specified last-use by an instruction, wherein the architected operands are made active by performing a write operation to an inactive operand, wherein the activation/deactivation may be performed by the instruction having the last-use of the operand or another (prefix) instruction.

Transactional memory operations with write-only atomicity

Execution of a transaction mode setting instruction causes a computer processor to be in an atomic write-only mode ignoring conflicts to certain read-sets of a transaction during transactional execution. Write-set conflicts may still cause a transactional abort. Absent any aborting, the transaction's execution may complete, by committing transactional stores to memory and updating architecture states.

Scheduler capable of issuing and reissuing dependency chains

A scheduler issues instruction operations for execution, but also retains the instruction operations. If a particular instruction operation is subsequently found to be incorrectly executed, the particular instruction operation may be reissued from the scheduler. The penalty for incorrect scheduling of instruction operations may be reduced as compared to purging the particular instruction operation and younger instruction operations from the pipeline and refetching the particular instruction operation. Furthermore, the scheduler may employ a more aggressive scheduling mechanism since the penalty for incorrect execution is reduced. Additionally, the scheduler maintains the dependency indications for each instruction operation which has been issued. If the particular instruction operation is reissued, the instruction operations which are dependent on the particular instruction operation (directly or indirectly) may be identified via the dependency indications. The scheduler reissues the dependent instruction operations as well. Instruction operations which are subsequent to the particular instruction operation in program order but which are not dependent on the particular instruction operation are not reissued. Accordingly, the penalty for incorrect scheduling of instruction operations may be further decreased over the purging of the particular instruction and all younger instruction operations and refetching the particular instruction operation.

Method and apparatus for clearing hazards using jump instructions

A method and apparatus for overlaying hazard clearing with a jump instruction within a pipeline microprocessor is described. The apparatus includes hazard logic to detect when a jump instruction specifies that hazards are to be cleared as part of a jump operation. If hazards are to be cleared, the hazard logic disables branch prediction for the jump instruction, thereby causing the jump instruction to proceed down the pipeline until it is finally resolved, and flushing the pipeline behind the jump instruction. Disabling of branch prediction for the jump instruction effectively clears all execution and/or instruction hazards that preceded the jump instruction. Alternatively, hazard logic causes issue control logic to stall the jump instruction for n-cycles until all hazards are cleared. State tracking logic may be provided to determine whether any instructions are executing in the pipeline that create hazards. If so, hazard logic performs normally. If not, state tracking logic disables the effect of the hazard logic.

Interrupt processing in a data processing system

The present invention relates generally to interrupt processing. One embodiment relates to a method for executing an interrupt in a data processing system including fetching a conditional store instruction that is conditional upon a reservation, receiving notice that an interrupt is pending, invalidating a reservation in response to receiving the notice, and processing the interrupt. Invalidating the reservation allows the conditional store instruction to finish in a predetermined amount of time and properly update an architectural state of the processor. Therefore, interrupt latencies (the amount of time between receiving and processing an interrupt) corresponding to the conditional store instruction can be bounded. The method may be used in a single processor or multi-processor data processing system, wherein each processor includes a reservation register. Furthermore, each processor may include both a completion unit for storing instructions in the order they are issued and a store queue within a load/store unit.

Transactional memory system supporting unbroken suspended execution

Mechanisms are provided, in a data processing system having a processor and a transactional memory, for executing a transaction in the data processing system. These mechanisms execute a transaction comprising one or more instructions that modify at least a portion of the transactional memory. The transaction is suspended in response to a transaction suspend instruction being executed by the processor. A suspended block of code is executed in a non-transactional manner while the transaction is suspended. A determination is made as to whether an interrupt occurs while the transaction is suspended. In response to an interrupt occurring while the transaction is suspended, a transaction abort operation is delayed until after the transaction suspension is discontinued.

A processor with apparatus for verifying instruction parallelism

A processing engine 10 for executing instructions in parallel comprises an instruction buffer 600 for holding at least two instructions, with the first instruction 602 in a first position and the second instruction 604 in a second position. A first decoder 612 provides decoding of the first instruction and generates first control signals. The first control signals include first resource control signals, first address generation control signals, and a first validity signal indicative of the validity of the first instruction in the first position. A second decoder 614 provides decoding of the second instruction and generates second control signals. The second control signals include second resource control signals, second address generation control signals, and a second validity signal indicative of the validity of the second instruction in the second position. Arbitration and merge logic 628, 630 is provided for arbitrating between the first and second control signals and for merging the first and second control signals for controlling power of execution of the instructions in accordance with a set of parallelism rules. A conditional execution unit 634 is responsive to false condition signals from the arbitration and merge logic to inhibit or modify the effect of the control signals. The parallelism rules provide for efficient instruction execution, and the avoidance of resource conflicts.

Processor with support for nested speculative sections with different transactional modes

A system and method are disclosed wherein a processor of a plurality of processors coupled to shared memory, is configured to initiate execution of a section of code according to a first transactional mode of the processor. The processor is configured to execute a plurality of protected memory access operations to the shared memory within the section of code as a single atomic transaction with respect to the plurality of processors. The processor is further configured to initiate, within the section of code, execution of a subsection of the section of code according to a second transactional mode of the processor, wherein the first and second transactional modes are each associated with respective recovery actions that the processor is configured to perform in response to detecting an abort condition.

Computer instructions for activating and deactivating operands

An instruction set architecture (ISA) includes instructions for selectively indicating last-use architected operands having values that will not be accessed again, wherein architected operands are made active or inactive after an instruction specified last-use by an instruction, wherein the architected operands are made active by performing a write operation to an inactive operand, wherein the activation/deactivation may be performed by the instruction having the last-use of the operand or another (prefix) instruction.

Non Transactional Storage Instruction

Un producto de programa informático que comprende un medio de almacenamiento legible por ordenador que almacena instrucciones que se ejecutan sobre un sistema informático que comprende una memoria (5002) y un procesador (5001) para llevar a cabo un método que comprende: obtener, mediante el procesador, una instrucción de máquina para la ejecución, siendo definida la instrucción de máquina para ejecución por ordenador de acuerdo con una arquitectura informática, comprendiendo la instrucción de máquina (700): un código de operación (702a) para especificar una operación de almacenamiento no transaccional; un campo (704) para especificar un registro, en donde los contenidos del registro son un primer operando; y al menos un campo (706, 708, 710, 712) para especificar un dirección del segundo operando, sirviendo la dirección del segundo operando para designar una ubicación en la memoria; y ejecutar, mediante el procesador, la instrucción de máquina, comprendiendo la ejecución: almacenar de manera no transaccional el primer operando en la ubicación especificada por la dirección del segundo operando, en donde el primer operando almacenado en la ubicación es retenido a pesar de una anulación de una transacción asociada con la instrucción de máquina, y caracterizado por que el almacenamiento no transaccional es retrasado hasta un final del modo de ejecución transaccional del procesador. A computer program product comprising a computer readable storage medium that stores instructions that are executed on a computer system comprising a memory (5002) and a processor (5001) to carry out a method comprising: obtaining, by means of the processor, a machine instruction for execution, the machine instruction for computer execution being defined according to a computer architecture, the machine instruction (700) comprising: an operation code (702a) to specify a non-storage operation transactional; a field (704) to specify a record, where the contents of the record are a first operand ...

Dynamic generation of null instructions

Apparatus and methods are disclosed for dynamic nullification of memory access instructions, such as memory store instructions. In some examples of the disclosed technology, an apparatus can include memory and one or more block-based processor cores. One of the cores can include an execution unit configured to execute memory access instructions comprising a plurality of memory load and/or memory store instructions contained in an instruction block. The core can also include a hardware structure storing data for at least one predicate instruction in the instruction block, the data identifying whether one or more of the memory store instructions will issue if a condition of the predicate instruction is satisfied. The core may further include a control unit configured to control issuing of the memory access instructions to the execution unit based at least in a part on the hardware structure data.

Transactional memory operations with read-only atomicity

Execution of a transaction mode setting instruction causes a computer processor to be in an atomic read-only mode ignoring conflicts to certain write-sets of a transaction during transactional execution. Read-set conflicts may still cause a transactional abort. Absent any aborting, the transaction's execution may complete, by committing transactional stores to memory and updating architecture states.

Information processing system.

An information processing system (10) including an arithmetic unit (13) in which an item of data is processed according to one instruction, another arithmetic unit (14) in which plural items of data are processed according to one instruction, an instruction control unit (15) for distributing corresponding instruction groups to respective ones of the arithmetic units (13, 14), and a main memory (12) for exchanging data with the instruction control unit (15) and with both arithmetic units (13, 14). In the information processing system (10), a group of instructions among the above-mentioned groups of instructions, which group is restricted by the order of priority as to the execution sequence thereof, is synchronized by specially inserting a synchronization instruction (WAIT). It is also possible to divide the above-mentioned groups of instructions into a group of instructions to be serial-processed and a group of instructions capable of being parallel-processed, as to the execution sequence thereof, by inserting a serialization-start instruction (POST) and a serialization-release instruction (SUB - WAIT).

Mechanism for load block on store address generation and universal dependency vector

A processor employs ordering dependencies for load instruction operations upon store address instruction operations. The processor divides store operations into store address instruction operations and store data instruction operations. The store address instruction operations generate the address of the store, and the store data instruction operations route the corresponding data to the load/store unit. The processor maintains a store address dependency vector indicating each of the outstanding store addresses and records ordering dependencies upon the store address instruction operations for each load instruction operation. Accordingly, the load instruction operation is not scheduled until each prior store address instruction operation has been scheduled. Store addresses are available for dependency checking against the load address upon execution of the load instruction operation. If a memory dependency exists, it may be detected upon execution of the load instruction operation. The processor may also employ an instruction queue and dependency vectors therein which allow a flexible dependency recording structure. The dependency vector includes a dependency indication for each instruction queue entry, which may provide a universal mechanism for scheduling instruction operations. An arbitrary number of dependencies may be recorded for a given instruction operation, up to a depdendency upon each other instruction operation. Since the dependency vector is configured to record an arbitrary number of dependencies, a given instruction operation can be ordered with respect to any other instruction operation. Accordingly, any architectural or microarchitectural restrictions upon concurrent execution or upon order of particular instruction operations in execution may be enforced. The instruction queues evaluate the dependency vectors and request scheduling for each instruction operation for which the recorded dependencies have been satisfied.

Merging level cache and data cache units having indicator bits related to speculative execution

Systems, methods, and apparatuses for decomposing a sequential program into multiple threads, executing these threads, and reconstructing the sequential execution of the threads are described. A plurality of data cache units (DCUs) store locally retired instructions of speculatively executed threads. A merging level cache (MLC) merges data from the lines of the DCUs. An inter-core memory coherency module (ICMC) globally retires instructions of the speculatively executed threads in the MLC.

Instruction stream modification for memory transaction protection

Execution of a set of instructions within a transaction is prevented. A processor identifies a first set of instructions in an instruction stream of a transaction. The first set of instructions incurs a first memory access that is not visible to the transaction and will cause the transaction to abort. The processor generates a second set of instructions that incurs a second memory access that is visible to the transaction. The second set of instructions is generated based on the first memory access and first set of instructions. The processor executes, within the transaction, the second set of instructions instead of the first set of instructions.

Generating compiled code that indicates register liveness

Object code is generated from an internal representation that includes a plurality of source operands. The generating includes performing for each source operand in the internal representation determining whether a last use has occurred for the source operand. The determining includes accessing a data flow graph to determine whether all uses of a live range have been emitted. If it is determined that a last use has occurred for the source operand, an architected resource associated with the source operand is marked for last-use indication. A last-use indication is then generated for the architected resource. Instructions and the last-use indications are emitted into the object code.

Transactional-execution facility instructions: nontransactional store

Memory Subsystem having a Multipurpose Cache for a Stream Graphics Multiprocessor

A method and a computing system are provided. The computing system may include a system memory configured to store data in a first data format. The computing system may also include a computational core comprising a plurality of execution units (EU). The computational core may be configured to request data from the system memory and to process data in a second data format. Each of the plurality of EU may include an execution control and datapath and a specialized L1 cache pool. The computing system may include a multipurpose L2 cache in communication with the each of the plurality of EU and the system memory. The multipurpose L2 cache may be configured to store data in the first data format and the second data format. The computing system may also include an orthogonal data converter in communication with at least one of the plurality of EU and the system memory.

Reducing pipeline restart penalty

Techniques are disclosed relating to reducing the latency of restarting a pipeline in a processor that implements scouting. In one embodiment, the processor may reduce pipeline restart latency using two instruction fetch units that are configured to fetch and re-fetch instructions in parallel with one another. In some embodiments, the processor may reduce pipeline restart latency by initiating re-fetching instructions in response to determining that a commit operation is to be attempted with respect to one or more deferred instructions. In other embodiments, the processor may reduce pipeline restart latency by initiating re-fetching instructions in response to receiving an indication that a request for a set of data has been received by a cache, where the indication is sent by the cache before determining whether the data is present in the cache or not.

System and method for managing the execution of instruction groups having multiple executable instructions

A group completion table (GCT) that manages the execution of instruction groups having more than one executable instruction is disclosed. The GCT includes a plurality of table entries, wherein each of the table entries is associated with a respective instruction group. Each table entry in the GCT includes a plurality of instruction completion identifiers, wherein each of the instruction completion identifiers corresponds to a specific instruction in the associated instruction group. The table entry also includes a trouble identifier that is utilized to flag the occurrence of any exception condition encountered in the execution of any instruction in the instruction group. In a related embodiment, the trouble identifier utilized in the table entry is a single bit.

Processor and method for execution of a conditional floating-point store instruction

Multiple instruction dispatch system for pipelined microprocessor without branch breaks

Method and apparatus for early load retirement in a processor system

A technique known as checkpointed early load retirement, combines register checkpointing load-value prediction to manage long-latency loads. When a long-latency load reaches the retirement stage unresolved, the processor enters Clear mode by (1) taking a Checkpoint of the architectural registers, (2) supplying a load-value prediction to consumers, and (3) early-retiring the long-latency load. This unclogs retirement, thereby “clearing the way” for subsequent instructions to retire, and also allowing instructions dependent on the long-latency load to execute sooner. When the actual value returns from memory, it is compared against the prediction. A misprediction causes the processor to roll back to the checkpoint, discarding all subsequent computation.

Hardware mitigation for Spectre and meltdown-like attacks

Aspects include circuitry that includes a first global generation counter (GGC) that is increased upon decoding of a branch instruction and a second GGC that is increased upon a completion of the branch instruction. Upon a triggered rollback, the first GGC is reset. The circuitry also includes a generation tag memory associated with a register that receives loads during a side-channel attacks which is set to the first GGC upon a first load, and a determination unit to determine, for a second load from an address depending on the register of the first load, a generation tag value associated with the register of the second load as a function of the first GGC, the second GGC, and the generation tag value associated with the register of the first load. A wait queue is configured to block the second load, if the generation tag is larger than the second GGC.

Method of and apparatus for nullifying an instruction

Forwarding data in a processor

A method and apparatus for forwarding data in a processor is provided. The method includes providing at least one cascaded delayed execution pipeline unit having a first pipeline and a second pipeline, wherein the second pipeline executes instructions in a common issue group in a delayed manner relative to the first pipeline. The method further includes determining if a first instruction being executed in the first pipeline modifies data in a data register which is accessed by a second instruction being executed in the second pipeline. If the first instruction being executed in the first pipeline modifies data in the data register which is accessed by the second instruction being executed in the second pipeline, the modified data is forwarded from the first pipeline to the second pipeline. Also provided is a design structure embodied in a machine readable storage medium for designing, manufacturing, and/or testing a design for forwarding data in a processor is provided. The design structure includes a processor. The processor includes at least one cascaded delayed execution pipeline unit having a first and second pipeline, wherein the second pipeline is configured to execute instructions in a common issue group in a delayed manner relative to the first pipeline, and circuitry. The circuitry is configured to determine if a first instruction being executed in the first pipeline modifies data in a data register which is accessed by a second instruction being executed in the second pipeline, and if the first instruction being executed in the first pipeline modifies data in the data register which is accessed by the second instruction being executed in the second pipeline, forward the modified data from the first pipeline to the second pipeline.

Management of store queue based on restoration operation

Management of a store queue based on a restoration operation. A determination is made as to whether a restoration operation to perform a bulk restore of a set of architected registers has completed. Based on determining that the restoration operation has completed, one or more store queue entries corresponding to the restoration operation are invalidated.

System and method for operation replay within a data-speculative microprocessor

Microcomputer and dividing circuit

Herein disclosed is a microcomputer MCU adopting the general purpose register method. The microcomputer is enabled to have a small program capacity or a high program memory using efficiency and a low system cost, while enjoying the advantage of simplification of the instruction decoding as in the RISC machine having a fixed length instruction format of the prior art, by adopting a fixed length instruction format having a power of 2 but a smaller bit number than that of the maximum data word length fed to instruction execution means. And, the control of the coded division is executed by noting the code bits.

Run-time selection of feed-back connections in a multiple-instruction word processor

처리 장치가 다중-명령어 워드를 실행하기 위해 배열되고, 각 다중-명령어 워드는 복수의 명령어를 가진다. 상기 처리 장치는 복수의 명령어의 병렬 실행을 위해 배열된 복수의 이슈 슬롯(IS1, IS2); 복수의 이슈 슬롯에 의해 액세스 가능한 레지스터 파일(RF1, RF2); 및 상기 복수의 이슈 슬롯과 상기 레지스터 파일을 연결하기 위한 통신 네트워크(CN)를 포함한다. 상기 처리 장치는 제1 이슈 슬롯(IS1)에 의해 생성된 제1 결과 데이터(RD1)의 유효성에 관한 제1 식별자(OV1)와 제2 이슈 슬롯(IS2)에 의해 생성된 제2 결과 데이터(RD2)의 유효성에 관한 제2 식별자(OV2)를 생성하기 위해 더 배열된다. 상기 통신 네트워크는 제1 식별자와 제2 식별자를 사용함으로서 단일 프로세서 사이클 내에 제1 결과 데이터 또는 제2 결과 데이터의 상기 레지스터 파일의 레지스터로의 전송을 동적으로 제어하기 위해 배열된 적어도 하나의 선택 회로(SC1)를 포함한다. The processing device is arranged for executing a multi-instruction word, each multi-instruction word having a plurality of instructions. The processing apparatus includes a plurality of issue slots IS1 and IS2 arranged for parallel execution of a plurality of instructions; Register files RF1 and RF2 accessible by a plurality of issue slots; And a communication network CN for connecting the plurality of issue slots and the register file. The processing apparatus may generate a first identifier OV1 regarding the validity of the first result data RD1 generated by the first issue slot IS1 and a second result data RD2 generated by the second issue slot IS2. It is further arranged to generate a second identifier OV2 regarding the validity of. The communication network uses at least one selection circuit arranged to dynamically control transfer of first result data or second result data to a register in a register within a single processor cycle by using a first identifier and a second identifier. SC1).

Processor with support for nested speculative sections with different transactional modes

A system and method are disclosed wherein a processor of a plurality of processors coupled to shared memory, is configured to initiate execution of a section of code according to a first transactional mode of the processor. The processor is configured to execute a plurality of protected memory access operations to the shared memory within the section of code as a single atomic transaction with respect to the plurality of processors. The processor is further configured to initiate, within the section of code, execution of a subsection of the section of code according to a second transactional mode of the processor, wherein the first and second transactional modes are each associated with respective recovery actions that the processor is configured to perform in response to detecting an abort condition.

Block-based architecture with parallel execution of successive blocks.

<p>SISTEMA DE COMPUTACIÓN BASADO EN BLOQUES QUE COMPRENDE UNA PLURALIDAD DE NÚCLEOS DE PROCESAMIENTO QUE COMPRENDEN UN PRIMER NÚCLEO DE PROCESAMIENTO PARA EJECUTAR LAS INSTRUCCIONES DE UN PRIMER BLOQUE DE INSTRUCCIONES Y GENEREA UNA DIRECCIÓN OBJETIVO DE UN SEGUNDO BLOQUE DE INSTRUCCIONES ANTES DE QUE SE HAYA COMPROMETIDO EL PRIMER BLOQUE DE INSTRUCCIONES, Y LA LÓGICA DE CONTROL PARA RECIBIR LA DIRECCIÓN OBJETIVO DEL SEGUNDO BLOQUE DE INSTRUCCIONES Y PARA INICIAR LA EJECUCIÓN NO ESPECULATIVA DEL SEGUNDO BLOQUE DE INSTRUCCIONES ANTES DE QUE SE HAYA COMPROMETIDO EL PRIMER BLOQUE DE INSTRUCCIONES; MÉTODO; DISPOSITIVO DE ALMACENAMIENTO LEGIBLE POR COMPUTADORA O UNA MEMORIA QUE TIENE INSTRUCCIONES EN LA MISMA.</p> <p> COMPUTER SYSTEM BASED ON BLOCKS THAT INCLUDES A PLURALITY OF PROCESSING CORES THAT INCLUDE A FIRST PROCESSING CORE TO EXECUTE THE INSTRUCTIONS OF A FIRST BLOCK OF INSTRUCTIONS AND GENERATE AN OBJECTIVE ADDRESS OF A SECOND BLOCK OF INSTRUCTIONS COMMITTED TO THE FIRST INSTRUCTION BLOCK, AND CONTROL LOGIC TO RECEIVE THE OBJECTIVE ADDRESS OF THE SECOND INSTRUCTION BLOCK AND TO START THE NON-SPECULATIVE EXECUTION OF THE SECOND INSTRUCTION BLOCK BEFORE THE FIRST INSTRUCTION BLOCK HAS BEEN COMMITTED; METHOD; LEGIBLE STORAGE DEVICE BY COMPUTER OR A MEMORY THAT HAS INSTRUCTIONS IN THE SAME. </p>

Register file backup queue

A register file backup system for use with a computer which processes instructions to generate results which thereby change the visual state of the computer. The computer has a register file with a plurality of addressable locations for storing data. The backup system is adapted to return the visual state of the computer to a previous state if an instruction generates an exception. The backup system utilizes less overhead so as to provide easier register file backup than a comparable software or hardware device. The backup system comprises first means for sequentially storing in program order, address information corresponding to destination locations in the register file where instruction results are to be stored. The first means has first and second outputs for transferring the address information stored therein: the first output being coupled to the register file for transferring a first portion of the address information to the register file, and the second output is used for transferring a second portion of address information for backup storage of the register file contents. The backup system also has a second means coupled to (1) the second output of the first means, for receiving and storing the second portion of the address information, and (2) the register file, for receiving and backup storing further information corresponding to the contents of one or more destination locations in the register file before that destination location is changed according to second portion of the address information. A third means is used for transferring the further information from the second means back to the register file locations according to the second portion of the address information stored in the second means after an instruction generates an exception.

Low power consumption semiconductor integrated circuit device and microprocessor

In semiconductor integrated circuit device and microprocessor including at least one functional circuit block, the start of operation of the functional circuit block is detected prior to the start of operation, the functional circuit block for which the start of operation has been detected is activated prior to the start of operation and inactivated after the termination of operation.

Scoreboarding mechanism in a pipeline that includes replays and redirects

Virtualizable advanced synchronization facility

A system and method for executing a transaction in a transactional memory system is disclosed. The system includes a processor of a plurality of processors coupled to shared memory, wherein the processor is configured to execute a section of code, including a plurality of memory access operations to the shared memory, as an atomic transaction relative to the execution of the plurality of processors. According to embodiments, the processor is configured to determine whether the memory access operations include any of a set of disallowed instructions, wherein the set includes one or more instructions that operate differently in a virtualized computing environment than in a native computing environment. If any of the memory access operations are ones of the disallowed instructions, then the processor aborts the transaction.

Microcomputer and dividing circuit

Herein disclosed is a microcomputer MCU adopting the general purpose register method. The microcomputer is enabled to have a small program capacity or a high program memory using efficiency and a low system cost, while enjoying the advantage of simplification of the instruction decoding as in the RISC machine having a fixed length instruction format of the prior art, by adopting a fixed length instruction format having a power of 2 but a smaller bit number than that of the maximum data word length fed to instruction execution means. And, the control of the coded division is executed by noting the code bits.

Block-based architecture with parallel execution of successive blocks

Persistent store fence processors, methods, systems, and instructions

한 양태의 프로세서는, 영구적 저장 펜스 명령어를 디코딩하는 디코드 유닛을 포함한다. 프로세서는 또한, 디코드 유닛과 커플링되는 메모리 서브시스템 모듈을 포함한다. 메모리 서브시스템 모듈은, 영구적 저장 펜스 명령어에 응답하여, 모든 후속하는 저장 명령어의 데이터가 영구적 스토리지에 영구적으로 저장되기 이전에, 영구적 저장 펜스 명령어에 대응하는 주어진 데이터가 영구적 스토리지에 영구적으로 저장되는 것을 보장한다. 후속하는 저장 명령어는, 원래의 프로그램 순서에서 영구적 저장 펜스 명령어 뒤에 발생한다. 다른 프로세서, 방법, 시스템, 및 제조 물품이 또한 개시된다. A processor of an aspect includes a decode unit that decodes a permanently stored fence instruction. The processor also includes a memory subsystem module coupled with the decode unit. The memory subsystem module is configured, in response to a persistent store fence command, to ensure that given data corresponding to the persistent store fence command is permanently stored in the persistent storage before data of all subsequent store commands are permanently stored in the persistent storage. guarantee Subsequent store instructions occur after the persistent store fence instruction in the original program sequence. Other processors, methods, systems, and articles of manufacture are also disclosed.

Coherence protocol augmentation to indicate transaction status

본 발명의 실시 예들은 일관성 프로토콜을 구현하는 것에 관한 것이다. 한 실시 예는 데이터에 대한 요청을 리모트 프로세서에 내보내는 단계 및 프로세서에 의해, 상기 리모트 프로세서로부터의 응답을 수신하는 단계를 포함한다. 상기 프로세서는 상기 리모트 프로세서 상의 상기 리모트 트랜잭션의 트랜잭션 상태를 로컬 트랜잭션 간섭 추적 테이블(a local transaction interference tracking table)에 추가한다. Embodiments of the invention relate to implementing a coherency protocol. One embodiment includes exporting a request for data to a remote processor and receiving a response from the remote processor by the processor. The processor adds the transaction state of the remote transaction on the remote processor to a local transaction interference tracking table.

Data processing systems

Epoch-based determination of completion of barrier termination command

An apparatus comprises transaction handling circuitry to issue memory access transactions, each memory access transaction specifying an epoch identifier indicative of a current epoch in which the memory access transaction is issued; transaction tracking circuitry to track, for each of at least two epochs, a number of outstanding memory access transactions issued in that epoch; barrier termination circuitry to signal completion of a barrier termination command when the transaction tracking circuitry indicates that there are no outstanding memory access transactions remaining which were issued in one or more epochs preceding a barrier point; and epoch changing circuitry to change the current epoch to a next epoch, in response to a barrier point signal representing said barrier point. This helps to reduce the circuit area overhead for tracking completion of memory access transactions preceding a barrier point.

Generating compiled code that indicates register liveness

Retiring early-completion instructions to improve computer operation throughput

The present invention, in various embodiments, provides techniques for retiring instructions that typically complete early as compared to most instructions. In a first embodiment, at each stage of the various processing stages, each instruction capable of early retirement is processed in accordance with that stage. At a particular stage, if the instruction meets the criteria for early retirement, then the instruction is terminated, e.g., “retired,” and the system is updated to reflect that the instruction has been terminated. However, if, at that particular stage, the instruction does not meet the criteria for early retirement, then the instruction is processed to the next stage, and it is determined again whether the instruction meets the criteria for early retirement. If the instruction meets the criteria, then the instruction is terminated, or if the instruction does not meet the criteria, then the instruction is processed to the next stage, and so on, until the instruction is retired. In a second embodiment, it is predetermined that early-completion instructions are to be retired at a particular stage. Consequently, all instructions are processed normally and early-completion instructions are retired when they reach that particular stage. For example, early-completion instructions are retired out-of-order after they reach a particular stage in an instruction queue, even though they meet the early-retirement criteria prior to entering the queue. In a third embodiment, early-completion instructions are retired out-of-order when an instruction queue is full. As a result, all instructions are processed normally until the instruction queue is full. At that time, the system is frozen, e.g., all units stop processing instructions. For each instruction in the instruction queue, if the instruction meets the criteria for early retirement, then the instruction is terminated and the system is updated to reflect that the instruction has been terminated. The system is then ...

Method and apparatus for releasing memory locations during transactional execution

One embodiment of the present invention provides a system for releasing a memory location from transactional program execution. The system operates by executing a sequence of instructions during transactional program execution, wherein memory locations involved in the transactional program execution are monitored to detect interfering accesses from other threads, and wherein changes made during transactional execution are not committed until transactional execution completes without encountering an interfering data access from another thread. Upon encountering a release instruction for a memory location during the transactional program execution, the system modifies state information within the processor to release the memory location from monitoring. The system also executes a commit-and-start-new-transaction instruction, wherein the commit-and-start-new-transaction instruction atomically commits the transaction's stores, thereby removing them from the transaction's write set while the transaction's read set remains unaffected.

Store nullification in the target field

Apparatus and methods are disclosed for nullifying memory store instructions identified in a target field of a nullification instruction. In some examples of the disclosed technology, an apparatus can include memory and one or more block-based processor cores configured to fetch and execute a plurality of instruction blocks. One of the cores can include a control unit configured, based at least in part on receiving a nullification instruction, to obtain an instruction identification for a memory access instruction of a plurality of memory access instructions, based on a target field of the nullification instruction. The memory access instruction associated with the instruction identification is nullified. The memory access instruction is in a first instruction block of the plurality of instruction blocks. Based on the nullified memory access instruction, a subsequent memory access instruction from the first instruction block is executed.

Systems, apparatuses, and methods for data speculation execution

Systems, methods, and apparatuses for data speculation execution (DSX) are described. In some embodiments, a hardware apparatus for performing DSX comprises a hardware decoder to decode an instruction, the instruction to include an opcode and an operand to store a portion of a fallback address and an operand to store a stride value, execution hardware to execute the decoded instruction to initiate a data speculative execution (DSX) region by activating DSX tracking hardware to track speculative memory accesses and detect ordering violations in the DSX region, and storing the fallback address.

Enabling end of transaction detection using speculative look ahead

A transaction within a computer program or computer application comprises program instructions performing multiple store operations that appear to run and complete as a single, atomic operation. The program instructions forming a current transaction comprise a transaction begin indicator, a plurality of instructions (e.g., store operations), and a transaction end indicator. A near-end of transaction indicator is triggered based on a speculative look ahead operation such that an interfering transaction requiring a halt operation may be delayed to allow the current transaction to end. A halt operation, also referred to as an abort operation, as used herein refers to an operation responsive to a condition where two transactions have been detected to interfere where at least one transaction must be aborted and the state of the processor is reset to the state at the beginning of the aborted transaction by performing a rollback.