Three-Dimensional Array of Re-Programmable Non-Volatile Memory Elements Having Vertical Bit Lines and a Single-Sided Word Line Architecture

A three-dimensional array especially adapted for memory elements that reversibly change a level of electrical conductance in response to a voltage difference being applied across them. Memory elements are formed across a plurality of planes positioned different distances above a semiconductor substrate. A two-dimensional array of bit lines to which the memory elements of all planes are connected is oriented vertically from the substrate and through the plurality of planes. A single-sided word line architecture provides a word line exclusively for each row of memory elements instead of sharing one word line between two rows of memory elements thereby avoids linking the memory element across the array across the word lines. While the row of memory elements is also being accessed by a corresponding row of local bit lines, there is no extension of coupling between adjacent rows of local bit lines and therefore leakage currents beyond the word line.

Memory devices with local and global devices at substantially the same level above stacked tiers of memory cells and methods

In an embodiment, a memory device includes a stack of tiers of memory cells, a tier of local devices at a level above the stack of tiers of memory cells, and a tier of global devices at substantially a same level as the tier of local devices. A local device may provide selective access to a data line. A global device may provide selective access to a global access line. A tier of memory cells may be selectively coupled to a global access line by the global device of the tier of global devices.

MULTIPLE PLATE LINE ARCHITECTURE FOR MULTIDECK MEMORY ARRAY

Methods, systems, and devices for multiple plate line architecture for multideck memory arrays are described. A memory device may include two or more three-dimensional arrays of ferroelectric memory cells overlying a substrate layer that includes various components of support circuitry, such as decoders and sense amplifiers. Each memory cell of the array may have a ferroelectric container and a selector device. Multiple plate lines or other access lines may be routed through the various decks of the device to support access to memory cells within those decks. Plate lines or other access lines may be coupled between support circuitry and memory cells through on pitch via (OPV) structures. OPV structures may include selector devices to provide an additional degree of freedom in multideck selectivity. Various number of plate lines and access lines may be employed to accommodate different configurations and orientations of the ferroelectric containers. 1. An electronic memory device , comprising:a first array of memory cells configured in a cross point architecture, the first array comprising a plurality of sections, each cell of the first array comprising a ferroelectric memory cell coupled with an access line oriented in a first direction and an access line oriented in a second direction that is substantially orthogonal to the first direction;a first plate line oriented in the first direction and coupled with ferroelectric memory cells in two or more sections of the first array;a second array of memory cells configured in the cross point architecture, the second array comprising a plurality of sections, wherein the first array overlies the second array, each cell of the second array comprising a ferroelectric memory cell coupled with an access line oriented in the first direction and an access line oriented in the second direction;a plurality of second plate lines oriented in the first direction, each of the second plate lines coupled with the first plate line and ...

Magnetic random access memory

Patent FR2017540A1

Memory, operating on the principle of coincidence

Address memory corresponding to a stored program

Memory detector device

Electronic device for data processing

Improvements to magnetic recording systems

3-D ferrite core memory matrix manufacturing system for computers - has cores prestacked in Y plane and are arranged to X-Y matrices then ZY, matrices

Matrix memory with magnetic cores subdivided into memory domains

Pulse generator circuit for memory device

Improvements to magnetic recording systems

Improvements to object detection devices.

Improvements to magnetic recording systems

Patent FR2266938B1

Improvements to magnetic recording systems

High speed core memory system

A magnetic core memory system is disclosed comprising a rectangular array of magnetic cores. A first plurality of independent wires thread cores along one axis and a second plurality of dependent wires thread cores along the other axis for coincident-current selection of cores to be switched. The second plurality of wires are current dependent in that the current through a selected wire is returned in the opposite direction through unselected wires in parallel. In that manner, a selected core may be overdriven with more than half-select current Ih in one of the first plurality of wires and half-select current Ih in one of the second plurality of wires. The unselected cores threaded by the overdriven wire receive a net current of Ih due to return current through unselected ones of the second plurality of wires.

Arrangement for control of selection of digitlines

Three-Wire Coincident Current Core Store.

1,176,682. Magnetic storage matrices. INTERNATIONAL COMPUTERS Ltd. 10 Jan., 1967 [12 July, 1966], No. 1243/67. Heading H3B. In order to suppress noise in a magnetic core matrix, the common, sense-inhibit lines D11, D12 ... and the word group lines WG1, WG2 ... are arranged as shown in the Figure. For reading, e.g. cores 10 to 13, half select read currents WG 1 and Y 1 are applied to lines WG1 and Y1 respectively, these cores forming a word. The reading of core 10 for example, induces a sense pulse S on line D11 which appears across the left-hand half of the primary of transformer 26 and is coupled through the secondary S to a sense amplifier. The current in word group line WG1 produces noise pulses in the cores to which it is coupled and the cores to which both word line WG1 and line D11 are coupled induce cumulative noise pulse N 1 on line D11. Similarly cores coupled to line WG1 and line D21 induce cumulative noise N 2 on sense line D21. Since the sense-inhibit lines are arranged in pairs, with each pair coupled to the transformer 26 and there are the same number of cores coupling line WG1 to lines D11, D21 of the pair being considered noise pulses N 1 , N 2 cancel out. Drive current in row line Y1 which is coupled to the cores in all the planes P1, P2 of row 1 induces a cumulative noise N 3 in sense line D11 which is coupled to line Y1 once in each plane. Similarly, a noise pulse N 4 is induced in line D21 which noise pulse cancels out noise N 3 at transformer 26. For writing currents Y1 and WG1 are reversed and inhibit current source I is selectively energized in accordance with information to be written. If a " 0 " is to be written, an inhibit current pulse I is supplied to transformer 25 to give half-select inhibit lines on both lines D11, D21 simultaneously which are everywhere in opposition to currents WG1 and Y1.

So-called conductive devices

Electronic stores

1355504 Magnetic storage systems PHILIPS ELECTRONIC & ASSOCIATED INDUSTRIES Ltd 19 July 1971 [22 July 1970] 33714/71 Heading H3B In a multi-plane word organized core store an additional plane of cores is provided lacking inhibit wires, this latter plane being used to provide signals to trigger a reading strobe pulse for the remaining planes. Fig. 3 shows planes each with conventional row and column drive lines, and each having a sense conductor; the first 18 planes have inhibit lines, and have sense amplifiers V 1 -V 18 which can be strobed. The sense line of the additional plane 19 is connected to a device AG which gives a strobe pulse output to the sense amplifiers V 1 -V 18 a fixed time after receiving an output on the sense line. In planes 1-18, which have inhibit wires, there are inevitably several remanent states in which cores may be set by single and coincident half read and write signals, and reading noise in their sense conductors cannot be cancelled by the usual folding techniques. In the additional plane however such cancellation is possible since there is no inhibit wire, and the signal which is fed to the pulse device AG is thus largely noise free. This enables an accurately set strobe pulse to be generated, independent of parasitic capacitances in the planes. The configuration of sense conductors used is shown in Fig. 6a for the first eighteen planes, the arrangement being such that each plane has four sense conductors of which two Pa<SP>1</SP> and Pa<SP>11</SP> are shown each covering two quadrants of the plane and threading the cores in opposite directions. Such a pattern ensures that the output on the sense wires, while not noise free, occurs at much the same time as associated noise wherever the core is located in the plane. This allows the time of the strobe pulse to be accurately set. Because in large planes the amplitudes of the sensed signals vary according to the core location, the sense line in the additional ...

Patent DE2513518C3

Method for the reading-in and the reading-out of informations contained in a ferrite-core storage matrix

Conductive devices known as printed circuits

Memory drive

Three-dimensional array of re-programmable non-volatile memory elements having vertical bit lines and a single-sided word line architecture

Piston provided with an annular groove open on its side wall

Thin film magnetic core memory and method of making same

Data storage device

Reading system for magnetic memory

Linear selection magnetic memory

Magnetic switching devices

753,025. Circuits employing bi-stable magnetic elements. RADIO CORPORATION OF AMERICA. Feb. 5, 1954 [Feb. 20, 1953; April 1, 1953], No. 3497/54. Class 40(4). [Also in Groups XIX and XL (c)] In a magnetic switch of the kind used for setting information in a matrix magnetic memory and comprising a number of saturable cores associated with windings which reverse the magnetic polarity of a single core from " N " to " P " when selectively energized, partial demagnetization of unselected cores which occurs as a result of ineffective " P " magnetizing current in an associated winding is reduced by biasing all the cores in an " N polarizing direction over a common D.C. or pulse-energized winding. The bias may in addition effect automatic restoration of a selected core to an " N " polarity when the selecting currents terminate. Saturable cores are also employed in the magnetic memory which has column and row windings connected to individual output coils of the cores of a pair of magnetic switches. A pulse is induced in an output coil each time a selected core in a switch reverses-its polarity, the coincidence of pulses in a row and column causing the polarity of a single core in the matrix to reverse. Memory arrangements of this kind are described in the publication R.C.A. Review Volume XIII, June 1952. When it is required to reset the memory the two switches are restored simultaneously. This induces coincident pulses in the output coils of the selected cores which restore the appropriate memory core to the normal " N " condition. If information is to be retained in the memory the induced pulses are made non- coincident by restoring one switch after the other. A magnetic switch is shown in Fig. 1 and comprises cores 10 having selecting coils 14, 16 arranged in series to form column and row windings C1-C4, R1-R4. each core also including an individual output coil 18 and a bias coil 28 forming part of a common bias winding 26. To ...

Magnetic memory

minnick

Memory for a coherent pulse doppler radar

1,132,284. Data storage. INTERNATIONAL STANDARD ELECTRIC CORP. 17 Feb., 1966 [17 Feb., 1965], No. 6970/66. Heading G4C. [Also in Division H4] The Specification describes a multiple matrix storage unit comprising, Fig. 1, p planes, each N having N = 2<SP>r</SP> lines - columns (where r is a 2 positive integer greater than zero), each said plane being divided notionally into two substores P and Q of N/2 lines each according to the parity (even or odd respectively) of the lines, and having an individual storage element at each cross-point of a line and a column, whereby p-digit binary signals may be stored, one digit to a plane; a separate access selector 6 and 5 for the lines of each sub-store, and a single access selector 7 for the columns of each plane; clock pulse generator means H (not shown) and O to provide selection signals PL, Pi and QL, Qi and A, B for driving the said access selectors to enable a specific storage element to be selected for storage of a signal digit therein or reading of a signal digit therefrom, and also to provide a controlling pulse T defining a repetition period for the operation of said storage unit; means 1, 2 for writing digits into the storage elements of each said sub-store, line-by-line, independently for each sub-store, means 3, 4 for reading destructively digits stored in the storage elements of said storage plane column-by-column; a control circuit 8 for each said storage plane under the control of said clock pulse generator and said controlling pulse for controlling the storage of incoming signal digits into said planes, and the reading of stored signal digits from said planes in alternative phases of operation during each repetition period, and including also control means (acting on gates 43, 44 with signal W) for effecting rewriting of a specified group of signal digits read out from the storage elements into those elements during a specified portion of the reading phase of the repetition period, whereby storage, ...

Write and read circuit for a magnetic core memory

Planar core memory stack

Patent FR2104796A1

Conductive devices known as printed circuits

Bit-organized sense line arrangement

Advanced memory device

Drive current generator for memory arrays

789,096. Electric digital-data-storage apparatus. INTERNATIONAL BUSINESS MACHINES CORPORATION. July 1, 1955 [July 2, 1954], No. 19065/55. Class 106 (1). [Also in Group XXXIX] In an arrangement permitting repetitive readout of information stored in a magnetic core memory matrix, Fig. 2, binary information from decoding units 11X, 11Y, for example crystal diode matrixes, is transmitted to the memory through driver units 12X, 12Y, Fig. 3, which function as temporary registers and comprise groups of bi-stable magnetic cores 30 each controlled in opposite respects by input and write windings 32, 33 and provided with output windings 34. Read-out of recorded information in the memory is effected by selectively pulse-energizing an input winding 32 in each driver unit over a valve or transistor 38 which has its cathode potential stabilized by a diode 40 and resistor 41. As a result, the magnetic condition of the associated core 30 is reversed from state b to state a and coincident induced pulses in the output windings of the two driver units drive the selected memory core 10 to binary zero state b. If a binary one is stored in core 10, reversal of its magnetic state induces a pulse in a read-out winding 20 which extends through all the memory cores in such a way as to minimise spurious induced voltages, and the write windings 33 in each driver unit are pulses simultaneously over valves 36. The selected cores 30 change over from state a to state band produce coincident output pulses which restore the memory core to the binary one condition. If, however, a binary zero is stored in core 10, the absence of a voltage in the read-out winding causes the write windings of the two driver units to be pulsed non-coincidently. In this case cores 30 are restored to state b without effect on the memory core which remains in the binary zero condition. To record new information, the memory is interrogated as previously described but the control circuit between the read-out winding 20 and ...

Magnetic memory system

Matrix selection circuit

Pulse doppler radars

Magnetic core memory with a circuit card and a method for attaching an electronic component to the circuit card

Improvements in or relating to storage arrangements

1,111,353. Circuits employing bi-stable magrietic elements. SIEMENS A.G. 21 June, 1966 [22 June, 1965], No. 27571/66. Heading H3B. Pairs of column or row conductors of a random access storage matrix are connected together in parallel. In a multi-planar matrix the row conductor pairs of adjacent planes are connected in series (Fig. 2) and corresponding column conductors in each plane are connected to a common source. Magnetic cores in the rows of a pair are differently orientated so that, for a particular direction of current flow in a column conductor and a pair of row conductors, the fluxes induced add in one core but not in the other. In this arrangement the particular core is selected by choice of the direction of the row current, whereas in Fig. 1 (not shown), the column current is reversed to select the core. Switches S1 S2 determine whether a " 1 " or a " 0 " is stored. For read-out the column current is reversed and the appropriate row current is supplied. The signals induced on the lines of a pair of row conductors affect a transformer core differentially to generate an output on line L1, L2. In Fig. 3 (not shown), the column conductors are connected in pairs and the row conductors are not The first and third column conductors of a plane are connected, by way of diodes, to one transformer winding and the second and fourth to the other winding. In this case a single transformer suffices for each matrix plane. All the column conductors of a plane are also connected by way of rectifiers to a transistor switch. In Fig. 4 (not shown), the binary digit to be stored is determined by inhibit lines which thread cores in the first and third rows and in the second and fourth rows in a matrix plane of the type shown in Fig. 2.

Memory systems

Data storage read out network

Method for reading out information in a magnetic memory

Magnetic-core storage matrix

Transistor scanning amplifier

Magnetic storage mechanism

Magnetic device for extracting information from a magnetic storage element

Intermediate magnetic core storage

749,796. Circuits employing bi-stable magnetic elements. INTERNATIONAL BUSINESS MACHINES CORPORATION. Dec. 30, 1953 [Jan. 2, 1953], No. 36171/53. Class 40 (4). [Also in Group XIX] In a storage device comprising a magnetic core matrix having sets of row and column windings, read-in is effected by successively energizing the row windings and selectively energizing the column windings and read-out by successively energizing the row windings in a direction contrary to that for read-in, arrangements being provided for detecting the changing of state of a core in response to the contrary energization of said row windings and for enabling information to be repeatedly readout. The wiring of a column of the matrix is shown in Fig. 5, each column winding 12 consisting of several turns common to all the cores 10 in the column, and each row winding 11 consisting of single turns, one per core of the row. Before reading in " each core is set to a " zero " state by passing a large current through each of the row windings. Information is then transferred from a punched card to the matrix by successively energizing the rows of the matrix via a commutator 32, Figs. 1, 2, in synchronism with the sensing of rows of the card, and energizing columns of the matrix by the sensing of holes in the card, each sensing brush being in series with one column winding of the matrix. For " read-out " a commutator 48, by successively firing a set of 12 thyratrons 53, causes successive pulsing of the rows of the matrix. These pulses are sufficiently large to cause any core storing information to return to its " zero " state and to induce a pulse in its column winding which fires one of a set of 80 thyratrons 69, thus energizing one of a set of 80 electromagnets 40, whose differentially timed energizations therefore represent the content of the store. The current flow through the earthed winding 11, wire 64, resistor 63, tube 53, anode load 61 to a positive H.T. supply 500, ...

Patent FR2156054B1

Memory operating on the principle of coincidence

Three-wire coincidence current core memory

Memory matrix having interleaved bit wires

Patent JPS5528144B2

Circuit arrangement for operating matrix memories

Magnetic core storage system

Patent FR1572951A

Core memory with improved sense inhibit recovery time

Abstract of the Disclosure A three wire 3D core memory which utilizes the same balanced pairs of sense-inhibit conductors to conduct both high energy common mode inhibit currents and low energy differential mode core switching signals includes pairs of antiparallel Schottky diodes interconnecting the conductor pairs at symmetrical positions therealong intermediate the cores of each memory mat. As high energy common mode inhibit currents are generated small deviations from perfect symmetry of electrical characteristics along the sense-inhibit conductors results in the appearance of differential voltages which are substantial in comparison to switching signal voltages. The sense-inhibit recovery time required for dissipation of these spurious differential voltage signals before a memory read cycle can proceed consumes a sub-stantial portion of a memory cycle for large stacks. The Schottky diodes substantially reduce this recovery time to greatly improve memory cycle time by limiting the differential voltages to the low threshold forward conduction voltage thereof and by appearing as transmission line discontinuities to break up differential voltage signals which remain after termination of an inhibit current into higher frequency harmonic components which are more rapidly attenuated. The Schottky diodes have no substantial effect upon the sensed output switching signals because the threshold forward bias voltage of the Schottky diodes is greater than the peak switching signal voltage.

Assembly for telecommunications systems including telephony, time division multiplex

Transistor gating circuit

Memory selection apparatus

ELECTRONIC SELECTION CIRCUITS FOR OPERATING COINCIDENT-CURRENT MAGNETIC MEMORIES, AND LIKE APPARATUS, ARE PROVIDED FOR CONSTRUCTION ESSENTIALLY ENTIRELY AS INTEGRATED CIRCUITS, EVEN THE OUTPUT DRIVE STAGES. THE CIRCUITS ARE ARRANGED TO TRANSFORM GROUND-REFERENCED INPUT SIGNALS TO OUTPUT SIGNALS FOR DRIVING FLOATING REACTANCES WITHOUT THE TRANSFORMERS REQUIRED IN THE PRIOR ART FOR VOLTAGE ISOLATION. FURTHER, THE NEW CIRCUITS DRIVE THESE REACTIVE LOADS WITHOUT EXCESSIVE POWER DISSIPATION OR EXCESSIVE TRANSIENT VOLTAGES.

Patent JPS5522868B2

Radar device with a memory arrangement made of magnetic cores

Coincidence Current Storage

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Magnetic core memory providing both non-alterable and electrically alterable locations

Coincident current core memory fabrication

Differential matrix driver

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Una memoria magnetica.

Matrixspeicher

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Verfahren und Einrichtung zum Betrieb einer Schaltung mit zwei oder mehreren magnetisierbaren Elementen

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Matrice de mémoire de données

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1,266,847. Magnetic storage arrangements. PHILIPS ELECTRONIC & ASSOCIATED INDUSTRIES Ltd. 28 Oct., 1970 [31 Oct., 1969], No. 51160/70. Heading H3B. In a three co-ordinate store in which writing is effected by simultaneously energizing with ¢- write currents an x and a y conductor common to the store planes, and writing in a particular plane is prevented by energizing a z inhibit conductor individual to the plane, all the z inhibit conductors required to be effective during a writing operation are connected in series with the x and y conductors so that the inhibit current is equal to the ¢ write current. Storage planes 1, 2 ... P are shown in Fig. 1, a selected x and a selected y conductor being series energized from a ¢-write current source It when a switch Sx and a switch Sy are selectively closed. Writing takes place when ganged switches Sw 1 , Sw 2 are in the position shown, the switch Sw 1 connecting the selected x and y conductors in series with the inhibit circuit in which either a plane inhibit conductor Z 1 , Z 2 ... Z p or an individual R, L shunt impedance Dz 1 , Dz 2 ... Dz p is connected in series in each plane, depending on the position of plane selection switches Sz 1 , Sz 2 ... Sz p . The position of switches Sw 1 , Sw 2 is reversed for reading, the inhibit circuit being then disconnected. Two current sources are used in Fig. 2 (not shown) each current source being operative in half the planes of the store. In a modification, Fig. 3, the shunt impedances are omitted, and the z conductors in a plane are divided into four sections Z 11 ... Z 14 , Z 21 ... Z 24 , Zp 1 .. Zp 4 , each set of four sections being connected to a respective group of switches Sz 11 ... Sz 13 , Sz 21 ... Sz 23 and Sz p1 ... Sz p3 so that any selected two out of four sections in each plane are always in series with the x and y conductors for writing. Fig. 4 shows a modification of Fig. 3 in which capacitive noise is reduced by the use of transformer couplings T R1 , T R2 , T ...

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Memoria magnetica de acesso aleatorio com sistema detector de digitos silencioso

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Dispositifs électriques, tels que dispositifs à mémoire comportant des élémentsmagnétiques

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Dreidimensionale Speichervorrichtung mit magnetischen Speicherelementen

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Driedemensionale geheugeninrichting met magnetische ge- heugenelementen.

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