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Небесная энциклопедия

Космические корабли и станции, автоматические КА и методы их проектирования, бортовые комплексы управления, системы и средства жизнеобеспечения, особенности технологии производства ракетно-космических систем

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Мониторинг СМИ

Мониторинг СМИ и социальных сетей. Сканирование интернета, новостных сайтов, специализированных контентных площадок на базе мессенджеров. Гибкие настройки фильтров и первоначальных источников.

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Поддерживает ввод нескольких поисковых фраз (по одной на строку). При поиске обеспечивает поддержку морфологии русского и английского языка
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Применить Всего найдено 1941. Отображено 100.
05-01-2012 дата публикации

Memory Bit Redundant Vias

Номер: US20120002471A1
Автор: Mark A. Dexter, Sarma S. GUNTURI
Принадлежит: Texas Instruments Inc

An integrated circuit containing a memory array with memory bits and a differential sense amplifier for reading the logic state of the memory bits. The integrated circuit also contains redundant vias which are in the via path that couples a bitline to Vss. Moreover, an integrated circuit containing a FLASH memory bit with redundant vias in the via path from the bitline to Vss.

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Номер записи: 1
09-02-2012 дата публикации

Semiconductor device and method for driving semiconductor device

Номер: US20120033486A1
Автор: Hiroki Inoue, Kiyoshi Kato, Shuhei Nagatsuka, Takanori Matsuzaki
Принадлежит: Semiconductor Energy Laboratory Co Ltd

It is an object to provide a semiconductor device with a novel structure in which stored data can be held even when power is not supplied, and does not have a limitation on the number of writing operations. A semiconductor device includes a plurality of memory cells each including a transistor including a first semiconductor material, a transistor including a second semiconductor material that is different from the first semiconductor material, and a capacitor, and a potential switching circuit having a function of supplying a power supply potential to a source line in a writing period. Thus, power consumption of the semiconductor device can be sufficiently suppressed.

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Номер записи: 2
01-03-2012 дата публикации

Memory device having three-dimensional gate structure

Номер: US20120051129A1
Автор: Jeong-Min Choi, Nam-Kyeong Kim
Принадлежит: Numonyx BV Amsterdam Rolle Branch

Subject matter disclosed herein relates to a memory device, and more particularly to a nonvolatile memory device having a recess structure and methods of fabricating same.

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Номер записи: 3
24-05-2012 дата публикации

Memory instruction including parameter to affect operating condition of memory

Номер: US20120127807A1
Автор: Federico Pio
Принадлежит: Micron Technology Inc

Subject matter disclosed herein relates to techniques to operate memory.

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Номер записи: 4
05-07-2012 дата публикации

Nonvolatile memory device and nonvolatile memory system employing same

Номер: US20120170370A1
Автор: Dae-Seok Byeon, Hyun-Chul Ha, Seung-jae Lee
Принадлежит: SAMSUNG ELECTRONICS CO LTD

A nonvolatile memory device comprises a memory cell array, a row selection circuit and a voltage generator. The memory cell array comprises a first dummy memory cell, a second dummy memory cell, and a NAND string comprising a plurality of memory cells coupled in series between a string selection transistor and a ground selection transistor through the first dummy memory cell and the second dummy memory cell. During a read-out operation mode, a dummy read-out voltage is applied to a first dummy wordline coupled to the first dummy memory cell, and to a second dummy wordline coupled to the second dummy memory cell. The dummy read-out voltage has a lower magnitude than a read-out voltage applied to an unselected memory cell during the read-out operation mode.

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Номер записи: 5
02-05-2013 дата публикации

Methods and apparatuses including a select transistor having a body region including monocrystalline semiconductor material and/or at least a portion of its gate located in a substrate

Номер: US20130107620A1
Автор: Toru Tanzawa
Принадлежит: Individual

Some embodiments include apparatuses and methods having a memory cell string including memory cells located in different levels of the apparatuses and a select transistor coupled to the memory cell string. In at least one of such apparatuses, the select transistor can include a body region including a monocrystalline semiconductor material. Other embodiments including additional apparatuses and methods are described.

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Номер записи: 6
23-05-2013 дата публикации

METHOD OF OPERATING INTEGRATED CIRCUIT EMBEDDED WITH NON-VOLATILE PROGRAMMABLE MEMORY HAVING VARIABLE COUPLING RELATED APPLICATION DATA

Номер: US20130128674A1
Автор: GROSS JOHN NICHOLAS, Liu David K.Y.
Принадлежит: INVENSAS CORPORATION

A programmable non-volatile device is operated with a floating gate that functions as a FET gate that overlaps a portion of a source/drain region and allows for variable coupling through geometry and/or biasing conditions. This allows a programming voltage for the device to be imparted to the floating gate through variable capacitive coupling, thus changing the state of the device. Multi-state embodiments are also possible. The invention can be used in environments such as data encryption, reference trimming, manufacturing ID, security ID, and many other applications. 1. A method of operating a non-volatile programmable (NVP) device situated on a substrate comprising:providing a floating gate, which floating gate is comprised of a layer and material that is shared by gates of at least some other non-NVP devices on said substrate;programming the NVP device to a first state with channel hot electrons that alter a voltage threshold of a floating gate;wherein said channel hot electrons are provided by one of a variable number of drain regions and/or a variable program voltage which can be coupled to said floating gate;reading the first state in the OTP device using a bias current to detect said voltage threshold; anderasing the NVP device with band-band tunneling hot hole injection.2. A method of operating a programmable non-volatile device comprising: providing a floating gate;wherein said floating gate is comprised of a material that is also used as a gate for a transistor device also situated on the substrate and associated with a logic gate and/or a volatile memory;providing a source region; andproviding a drain region including at least a first drain region and a second separate drain region; andcapacitively coupling a variable portion of said gate to said drain based on selectively coupling either or both of said first drain region and said second separate drain region;providing a programming voltage to said drain region, wherein a substantial portion of said ...

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Номер записи: 7
27-06-2013 дата публикации

Method of using memory instruction including parameter to affect operating condition of memory

Номер: US20130167251A1
Автор: Federico Pio
Принадлежит: Micron Technology Inc

Subject matter disclosed herein relates to techniques to use a memory device. A method includes receiving a memory instruction comprising at least one parameter representative of at least one threshold voltage value and a read command to read at least one cell of the memory device. The method further includes detecting at least one voltage value from the at least one cell. The method further includes comparing the at least one voltage value to the at least one threshold voltage value. The method further includes determining at least one logical value of the at least one cell in response to the comparison of the at least one voltage value to the at least one threshold voltage value.

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Номер записи: 8
04-07-2013 дата публикации

NONVOLATILE SEMICONDUCTOR MEMORY DEVICE

Номер: US20130170300A1
Автор: Futatsuyama Takuya
Принадлежит:

A nonvolatile semiconductor memory device comprises a cell unit including a first and a second selection gate transistor and a memory string provided between the first and second selection gate transistors and composed of a plurality of serially connected electrically erasable programmable memory cells operative to store effective data; and a data write circuit operative to write data into the memory cell, wherein the number of program stages for at least one of memory cells on both ends of the memory string is lower than the number of program stages for other memory cells, and the data write circuit executes the first stage program to the memory cell having the number of program stages lower than the number of program stages for the other memory cells after the first stage program to the other memory cells. 2. The nonvolatile semiconductor memory device according to claim 1 , wherein the number of program stages for at least one of memory cells on both ends of said memory string and the number of program stages for other memory cells have a difference of 2 or more.3. The nonvolatile semiconductor memory device according to claim 1 , wherein said memory cells on both ends of said memory string store 1 bit claim 1 , and other memory cells store 3 bits.4. The nonvolatile semiconductor memory device according to claim 1 , wherein said cell unit includes a dummy cell having a structure same as said memory cell between said first selection gate transistor and said memory string and/or between said second selection gate transistor and said memory string.5. The nonvolatile semiconductor memory device according to claim 1 , whereinthe number of program stages for the first memory cell is 1, and the number of program stages for other memory cells is 3,said data write circuit executes the first stage program to the first memory cell after execution of the second stage program to the second memory cell, and{'sub': 2', '2', '2, 'said data write circuit executes the m-th stage ( ...

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Номер записи: 9
01-08-2013 дата публикации

Asymmetric Dense Floating Gate Nonvolatile Memory with Decoupled Capacitor

Номер: US20130193501A1
Автор: Andrew E. Horch
Принадлежит: Synopsys Inc

A nonvolatile memory (“NVM”) bitcell with one or more active regions capacitively coupled to the floating gate but that are separated from both the source and the drain. The inclusion of capacitors separated from the source and drain allows for improved control over the voltage of the floating gate. This in turn allows CHEI (or IHEI) to be performed with much higher efficiency than in existing bitcells, thereby the need for a charge pump to provide current to the bitcell, ultimately decreasing the total size of the bitcell. The bitcells may be constructed in pairs, further reducing the space requirements of the each bitcell, thereby mitigating the space requirements of the separate capacitor/s. The bitcell may also be operated by CHEI (or IHEI) and separately by BTBT depending upon the voltages applied at the source, drain, and capacitor/s.

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Номер записи: 10
08-08-2013 дата публикации

NONVOLATILE SEMICONDUCTOR MEMORY DEVICE

Номер: US20130201762A1
Автор: IZUMI Tatsuo
Принадлежит: KABUSHIKI KAISHA TOSHIBA

According to one embodiment, a control circuit of a memory cell array is configured to write data to a memory cell array by applying a first write pass voltage, which is lower than the program voltage, to a first group of nonselective word lines adjacent to a selective word line. The control circuit is further configured to apply a second write pass voltage, which is higher than the first write pass voltage, to a second group of second nonselective word lines, the second group not including the word lines of the first group. 1. A nonvolatile semiconductor memory device , comprising:a memory cell array including a plurality of memory cells connected in series to form a memory string;a plurality of word lines, each word line connected to a control gate of a respective memory cell in the memory string; anda control circuit configured to control a data write to the memory cell array, wherein a program voltage to a selected word line,', 'a first write pass voltage, which is lower than the program voltage, to a first group of non-selected word lines, the first group comprising word lines adjacent to the selected word line, and', 'a second write pass voltage, which is higher than the first write pass voltage, to a second group of non-selected word lines, the second group not including the first group; and, 'the control circuit appliesthe control circuit sets the first write pass voltage to a first level when the selected word line is connected to a memory cell at an end of the memory string and to a second level when the selected word line is not connected to a memory cell at either end of the memory string, the first level not equal to the second level.2. The nonvolatile semiconductor memory device according to claim 1 , wherein the first level of the first write pass voltage is higher than the second level of the first write pass voltage.3. The nonvolatile semiconductor memory device according to claim 1 , wherein the first level of the first write pass voltage is lower ...

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Номер записи: 11
12-09-2013 дата публикации

METHOD FOR PROGRAMMING A FLOATING GATE

Номер: US20130235658A1
Автор: Blackall Erick, Chen Wayne T., Smith Brett, Teggatz Ross E.
Принадлежит: TRIUNE IP LLC

The present invention provides circuits, systems, and methods for programming a floating gate. As described herein, a floating gate tunneling device is used with an analog comparison device in a circuit having a floating reference node and an offset-mitigating feedback loop for iteratively programming a floating gate or multiple floating gates. 1. A circuit configured to place a selected charge on a floating gate of a tunneling device , said circuit comprising:an analog comparison device operatively coupled to said tunneling device; anda reference node operatively coupled to said tunneling device.2. The circuit according to further comprising a feedback loop configured to couple an output of said analog comparison device to an input of said analog comparison device.3. The circuit according to further comprising a voltage level shifting device selectably coupled to said tunneling device claim 1 , wherein said voltage level shifting device is configured to receive input from said analog comparison device.4. The circuit according to wherein said analog comparison device has an input configured to receive a reference signal.5. The circuit according to wherein said selected charge is provided by said reference signal.6. The circuit according to further comprising one or more additional tunneling devices operatively coupled to said analog comparison device.7. The circuit according to further comprising at least one power supply operatively coupled to said analog comparison device and said tunneling device.8. The circuit according to wherein said analog comparison device comprises an op amp.9. The circuit according to wherein said analog comparison device comprises a comparator.10. The circuit according to wherein said analog comparison device comprises an analog to digital converter.11. The circuit according to wherein said tunneling device comprises a Fowler-Nordheim tunneling device.12. The circuit according to wherein said tunneling device comprises a Channel-Hot- ...

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Номер записи: 12
19-09-2013 дата публикации

MEMORY DEVICES INCLUDING VERTICAL PILLARS AND METHODS OF MANUFACTURING AND OPERATING THE SAME

Номер: US20130242654A1
Автор: Choi Jung-Dal, Sim Jae-Sung
Принадлежит:

In a semiconductor device and a method of forming such a device, the semiconductor device comprises a substrate of semiconductor material extending in a horizontal direction. A plurality of interlayer dielectric layers is provided on the substrate. A plurality of gate patterns is provided, each gate pattern between a neighboring lower interlayer dielectric layer and a neighboring upper interlayer dielectric layer. A vertical channel of semiconductor material extends in a vertical direction through the plurality of interlayer dielectric layers and the plurality of gate patterns, a gate insulating layer between each gate pattern and the vertical channel that insulates the gate pattern from the vertical channel, the vertical channel being in contact with the substrate at a contact region that comprises a semiconducting region. 1. A method of fabricating a semiconductor device comprising:providing a substrate of semiconductor material extending in a horizontal direction;providing a plurality of interlayer dielectric layers on the substrate;providing a plurality of gate patterns, each gate pattern between a neighboring lower interlayer dielectric layer and a neighboring upper interlayer dielectric layer;providing a vertical channel of semiconductor material extending in a vertical direction through the plurality of interlayer dielectric layers and the plurality of gate patterns; andproviding a gate insulating layer between each gate pattern and the vertical channel that insulates the gate pattern from the vertical channel,wherein the vertical channel is in contact with the substrate at a contact region that comprises a semiconducting region.2. The method of wherein the contact region comprises an upper surface of the substrate and a lower portion of the vertical channel claim 1 , and wherein the upper surface of the substrate and at least sidewalls of the lower portion of the vertical channel comprise a semiconducting region.3. The method of wherein the contact region is ...

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Номер записи: 13
19-09-2013 дата публикации

USE OF EMERGING NON-VOLATILE MEMORY ELEMENTS WITH FLASH MEMORY

Номер: US20130242657A1
Автор: Ghodsi Ramin
Принадлежит: MICRON TECHNOLOGY, INC.

Memory devices and methods of operating memory devices are provided, such as those that involve a memory architecture that replaces typical static and/or dynamic components with emerging non-volatile memory (NV) elements. The emerging NV memory elements can replace conventional latches, can serve as a high speed interface between a flash memory array and external devices and can also be used as high performance cache memory for a flash memory array. 1. A memory device comprising:a plurality of transistor-based non-volatile memory elements arranged in a first plurality of memory blocks;a plurality of emerging non-volatile memory elements arranged in at least one second memory block which is configured to operate as a redundant memory block for a bad memory block of the first plurality of memory blocks.2. A memory device as in claim 1 , wherein the memory device maps a bad block of the first plurality of memory blocks to the at least one redundant memory block.3. A memory device as in claim 2 , wherein the memory device includes an associated bad block management function for performing the mapping.4. A memory device as in claim 1 , wherein the plurality of emerging non-volatile memory elements are arranged into a plurality of second memory blocks and wherein at least some of the second plurality of memory blocks are configured to operate as redundant memory blocks for bad memory blocks of the first plurality of memory blocks.5. A memory device as in claim 4 , wherein the device is configured such that data to be stored in a first memory block of the first plurality of memory blocks is first stored in a memory block of the second plurality of memory blocks and if the first memory block of the first plurality of memory blocks is bad the data is stored in a redundant memory block of the second plurality of memory blocks.6. A memory device as in claim 1 , wherein the memory device is configured as part of a plug-in memory.7. A memory device comprising:a plurality of ...

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Номер записи: 14
26-09-2013 дата публикации

Semiconductor Memory Having Both Volatile and Non-Volatile Functionality and Method of Operating

Номер: US20130250685A1
Автор: Yuniarto Widjaja
Принадлежит: Zeno Semiconductor Inc

Semiconductor memory having both volatile and non-volatile modes and methods of operation. A semiconductor storage device includes a plurality of memory cells each having a floating body for storing, reading and writing data as volatile memory. The device includes a floating gate or trapping layer for storing data as non-volatile memory, the device operating as volatile memory when power is applied to the device, and the device storing data from the volatile memory as non-volatile memory when power to the device is interrupted.

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Номер записи: 15
26-09-2013 дата публикации

Method for erasing memory cells in a flash memory device using a positive well bias voltage and a negative word line voltage

Номер: US20130250695A1
Автор: Chung-Shan Kuo, Chung-Zen Chen, Yang-Chieh Lin
Принадлежит: Mosaid Technologies Inc

A memory device of the non-volatile type including a memory array having a plurality of memory cells organized as sectors, each sector having a main word line associated with a plurality of local word lines, each local word line coupled to the main word line by a respective local word line driver circuit, each of the local word line driver circuits consisting of a first MOS transistor coupled between the respective main word line and a respective local word line and a second MOS transistor coupled between the respective local word line and a first biasing terminal.

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Номер записи: 16
24-10-2013 дата публикации

NOVEL SHIELDING 2-CYCLE HALF-PAGE READ AND PROGRAM SCHEMES FOR ADVANCED NAND FLASH DESIGN

Номер: US20130279251A1
Автор: Lee Peter Wung
Принадлежит:

The present invention provides a two-cycle half-page read scheme by dividing whole NAND array bit lines (BLs) into an odd-BL group and an even-BL group. During the half-plane reading of NAND cells in the odd(even)-BL group, the half-plane even(odd)-BL group acts as the shielding BLs to protect over the odd(even)-BL string reading so that each half-page read operation is substantially reliable and free from BL coupling noise effect. Additionally, each half-page read operation is preferably divided into 3 periods: the first being a bias-condition setup period of the selected WL and remaining control signals; the second being a pre-charge period for all BLs; and the third being a half-page flash data sensing period. 1. A NAND memory block circuit for two-cycle half-page read operation , the NAND memory block circuit comprising:a NAND cell array comprising a plurality of memory cells built in a common P-well region and arranged as multiple pages in rows in x-direction and multiple strings in columns in y-direction, each page of memory cells being associated with a word line in the x-direction and each string of memory cells being associated with a bit line in the y-direction, the x-direction being perpendicular to the y-direction;a first string decoder located at one end of the multiple strings, the first string decoder comprising a row of 1-poly NMOS select-gate transistors having a first common gate input and respectively connecting drain nodes to the bit lines of corresponding strings; anda second string decoder located at another end of the multiple strings, the second string decoder comprising a first half-row of odd-column 1-poly NMOS select-gate transistors plus a first extra 1-poly NMOS select-gate transistor and a second half-row of even-column 1-poly NMOS select-gate transistors plus a second extra 1-poly NMOS select-gate transistor, the first/second half-row of odd/even-column 1-poly NMOS select-gate transistors being respectively gated by a second/third ...

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Номер записи: 17
07-11-2013 дата публикации

NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE

Номер: US20130294168A1
Автор: SHIRAKAWA Masanobu
Принадлежит:

According to one embodiment, a non-volatile semiconductor memory device comprises a memory cell array and a memory region. The memory cell array has a plurality of physical blocks. Each of the plurality of physical blocks includes a plurality of string units. Each string unit has a plurality of NAND strings that shares a plurality of word lines connected to a plurality of memory cells, respectively. The memory region is disposed to one of the plurality of physical blocks. Each of the plurality of string units configures a first logical block, and when the first logical block is failed, information of the first failed logical block is stored in a first region of the memory region.

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Номер записи: 18
14-11-2013 дата публикации

SEMICONDUCTOR MEMORY DEVICE AND METHOD OF DRIVING SEMICONDUCTOR MEMORY DEVICE

Номер: US20130301363A1
Автор: OGAWA Hiroyuki
Принадлежит: FUJITSU SEMICONDUCTOR LIMITED

Upon programming a semiconductor memory device including a first and a second n-wells, a first and a second p-channel memory transistors respectively formed in the first and the second n-wells, and a bit line connected to a drain of the first p-channel transistor and a drain of the second p-channel memory transistor, a first voltage is applied to the first bit line, a second voltage is applied to the first n-well, and a third voltage lower than the second voltage is applied to the second n-well. 1. A semiconductor memory device comprising:a first n-well formed in a semiconductor substrate;a second n-well formed in the semiconductor substrate and electrically isolated from the first n-well;a first p-channel memory transistor formed in the first n-well;a second p-channel memory transistor formed in the second n-well;a first word line connected to a control gate of the first p-channel memory transistor;a second word line connected to a control gate of the second p-channel memory transistor;a first bit line connected to a drain of the first p-channel transistor and a drain of the second p-channel memory transistor; anda control circuit which, upon programming in the first p-channel memory transistor, applies a first voltage to the first bit line, a second voltage to the first n-well and a third voltage lower than the second voltage to the second n-well.2. The semiconductor memory device according to claim 1 , whereina potential difference between the first voltage and the third voltage is not more than 3 V.3. The semiconductor memory device according to claim 1 , further comprising:a third p-channel memory transistor formed in the first n-well and having a drain connected to the first bit line; anda third word line connected to a control gate of the third p-channel memory transistor,wherein the control circuit applies, upon programming in the first p-channel memory transistor, a fourth voltage lower than the second voltage to the third word line.4. The semiconductor ...

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Номер записи: 19
21-11-2013 дата публикации

Memory structure

Номер: US20130307051A1
Автор: Chin-Fu Chen
Принадлежит: United Microelectronics Corp

A memory structure includes a substrate, a source region, a drain region, a gate insulating layer, a floating gate and a control gate. The substrate has a surface and a well extended from the surface to the interior of the substrate. The source region and the drain region are formed in the well and a channel region is formed between the source region and the drain region. The gate insulating layer is formed on the surface of the substrate between the source region and the drain region and covers the channel region. The floating gate disposed on the gate insulating layer to store a bit data. The control gate is disposed near lateral sides of the floating gate.

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Номер записи: 20
21-11-2013 дата публикации

NON-VOLATILE MEMORY DEVICE

Номер: US20130308382A1
Автор: Lee Yong-Kyu, Seo Bo-Young, Yu Tea-Kwang
Принадлежит: SAMSUNG ELECTRONICS CO., LTD.

A non-volatile memory device includes a first sector including a first sector selection transistor and a first plurality of pages connected to the first sector selection transistor, and a second sector including a second sector selection transistor and a second plurality of pages connected to the second sector selection transistor. Each of the first and second plurality of pages includes a memory transistor and a selection transistor, and a number of pages in the first plurality of pages is greater than a number of pages in the second plurality of pages. 1. (canceled)2. A non-volatile memory device comprising:a first sector including a first sector selection transistor and a first plurality of pages connected to the first sector selection transistor;a second sector including a second sector selection transistor and a second plurality pages connected to the second sector selection transistor; anda control unit configured to apply an enable signal to each of the first and second pluralities of pages through word lines,wherein the control unit is configured to apply the enable signal to only some of the second plurality pages through the word lines.3. The non-volatile memory device of claim 2 , wherein a number of pages of the first plurality of pages is equal to a number of pages of the second plurality of pages.4. The non-volatile memory device of claim 2 , wherein the first sector is a sector storing code data claim 2 , and the second sector is a sector storing operation data.5. The non-volatile memory device of claim 2 , wherein a number of pages of the first plurality of pages is greater than a number of pages of the second plurality of pages.6. The non-volatile memory device of claim 2 , wherein the first sector and the second sector are formed in a first well.7. The non-volatile memory device of claim 2 , wherein the first sector is formed in a first well claim 2 , and the second sector is formed in a second well different from the first well. This application ...

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Номер записи: 21
21-11-2013 дата публикации

Apparatuses and methods for coupling load current to a common source

Номер: US20130308385A1
Автор: Toru Tanzawa
Принадлежит: Individual

Apparatuses and methods are disclosed, including an apparatus with a string of charge storage devices coupled to a common source, a first switch coupled between the string of charge storage devices and a load current source, and a second switch coupled between the load current source and the common source. Additional apparatuses and methods are described.

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Номер записи: 22
12-12-2013 дата публикации

Memory cell string based on gated-diode cell and memory array using the same

Номер: US20130329499A1
Автор: Jong-ho Lee
Принадлежит: SEOUL NATIONAL UNIVERSITY R&DB FOUNDATION

The present invention provides a nonvolatile memory cell string and a memory array using the same. According to the present invention, a wall type semiconductor separated into twin fins and a memory cell string formed with memory cells having a gated diode structure along each fin are enabled to increase the degree of integration and basically prevent the interferences between adjacent cells. And a first semiconductor layer and a depletion region of a PN junction wrapped up by a gate electrode are enabled to remove GSL and CSL by GIDL memory operation and significantly increase the degree of integration for applying to a neuromorphic technology.

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Номер записи: 23
12-12-2013 дата публикации

SEMICONDUCTOR DEVICE WITH FLOATING GATE AND ELECTRICALLY FLOATING BODY

Номер: US20130329501A1
Автор: OKHONIN Serguei
Принадлежит: MICRON TECHNOLOGY, INC.

Techniques for providing floating body memory devices are disclosed. In one particular exemplary embodiment, the techniques may be realized as a semiconductor device comprising a floating gate, a control gate disposed over the floating gate, a body region that is electrically floating, wherein the body region is configured so that material forming the body region is contained under at least one lateral boundary of the floating gate, and a source region and a drain region adjacent the body region. 1. A semiconductor device comprising:a body region, wherein the body region is electrically floating;a gate disposed over a first portion of the body region, wherein the gate is electrically floating;a source region adjoining the first portion of the body region; anda drain region adjoining a second portion of the body region, the second portion adjacent the first portion and separating the drain region from the first portion.2. The device of claim 1 , wherein the floating gate is separated from the body region by a dielectric.3. The device of claim 2 , further comprising a control gate disposed over the floating gate.4. The device of claim 3 , wherein the control gate is separated from the floating gate by a dielectric.5. The device of claim 4 , further comprising circuitry to apply a first signal set including a first potential difference coupled between the source region and the drain region and a first gate signal coupled to the control gate claim 4 , wherein the first signal set programs a first logic state in the floating gate.6. The device of claim 5 , further comprising circuitry to apply a second signal set including a second potential difference coupled between the source region and the drain region and a second gate signal coupled to the control gate claim 5 , wherein the second signal set programs a second logic state in the floating gate.7. The device of claim 6 , further comprising circuitry to apply a third signal set including a third potential difference ...

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Номер записи: 24
19-12-2013 дата публикации

Random telegraph signal noise reduction scheme for semiconductor memories

Номер: US20130336068A1
Автор: Toru Tanzawa
Принадлежит: MICRON TECHNOLOGY, INC.

Embodiments are provided that include a method including providing a first pulsed gate signal to a selected memory cell, wherein the pulsed gate signal alternates between a first voltage level and a second voltage level during a time period and sensing a data line response to determine data stored on the selected memory of cells. Further embodiments provide a system including a memory device, having a regulator circuit coupled to a plurality of access lines of a NAND memory cell, and a switching circuit configured to sequentially bias at least one of the plurality of the access lines between a first voltage level and a second voltage level based on an input signal.

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Номер записи: 25
26-12-2013 дата публикации

Nonvolatile semiconductor memory device and method of manufacturing

Номер: US20130341698A1
Автор: Motoyuki Sato
Принадлежит: Toshiba Corp

According to one embodiment, a nonvolatile semiconductor memory device includes a first insulating layer on a semiconductor layer, a charge storage layer on the first insulating layer, a second insulating layer on the charge storage layer, and a control gate electrode on the second insulating layer. The charge storage layer includes a floating gate layer on the first insulating layer, an interface insulating layer on the floating gate layer, and a charge trap layer on the interface insulating layer, and a lower end of a conduction band of the interface insulating layer is higher than a trap level of the charge trap layer and is lower than a lower end of a conduction band of the charge trap layer.

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Номер записи: 26
23-01-2014 дата публикации

Memory System with Unverified Program Step

Номер: US20140022841A1
Автор: Changyuan Chen, Hao Thai Nguyen, Jongmin Park, Man Lung Mui, Seungpil Lee, Vamsi Krishna Sakhamuri, Yee Lih Koh
Принадлежит: SanDisk Technologies LLC

In a programming operation that includes repeated bitscan, program, and verify steps, the bitscan steps may be hidden by performing bitscan in parallel with program preparation and program steps. The effect of a program step may be predicted from previous observation so that when a bitscan indicates that the memory cells are close to being programmed, a last programming step may be completed without subsequent verification or bitscan steps.

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Номер записи: 27
27-02-2014 дата публикации

SEMICONDUCTOR DEVICE

Номер: US20140056071A1
Автор: CHOI Eun Seok
Принадлежит: SK HYNIX INC.

A semiconductor device includes a first memory block configured to include first active areas extended parallel in a first direction, a second memory block adjacent to the first memory block and configured to include second active areas extended parallel in the first direction, the second active areas being staggered from the first active areas, first bit lines disposed on the first active areas, and second bit lines disposed on the second active areas. 1. A semiconductor device comprising:a first memory block configured to include first active areas extended parallel in a first direction;a second memory block adjacent to the first memory block, and configured to include second active areas extended parallel in the first direction, the second active areas being staggered from the first active areas;first bit lines disposed on the first active areas; andsecond bit lines disposed on the second active areas.2. The semiconductor device of claim 1 , further comprising:first contact plugs configured to couple the first active areas with the first bit lines, respectively; andsecond contact plugs configured to couple the second active areas with the second bit lines, respectively.3. The semiconductor device of claim 2 , wherein the first contact plugs and the second contact plugs are disposed staggered to each other.4. The semiconductor device of claim 1 , further comprising:a common source line located between the first memory block and the second memory block, and extended in a second direction crossing the first direction.5. The semiconductor device of claim 1 , wherein the first memory block and the second memory block are operated in a same manner when a program operation claim 1 , a read operation or an erase operation is performed.6. The semiconductor device of claim 1 , wherein the first memory block and the second memory block are independently driven when a program operation claim 1 , a read operation or an erase operation is performed.7. The semiconductor device ...

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Номер записи: 28
27-02-2014 дата публикации

NON-VOLATILE MEMORY DEVICE, METHOD OF OPERATING THE SAME AND METHOD OF FABRICATING THE SAME

Номер: US20140056080A1
Автор: LEE Jun Hyuk, OH Seul Ki
Принадлежит: SK HYNIX INC.

A non-volatile memory device includes a semiconductor substrate having active regions formed of a p-type semiconductor, first and second vertical strings disposed on the active regions, channels extending vertical to the semiconductor substrate, and a plurality of memory cells stacked along the channels, wherein the active regions are directly connected to the channels of the first and second vertical strings. 1. A non-volatile memory device comprising:a semiconductor substrate having active regions formed of a p-type semiconductor; andfirst and second vertical strings disposed on the active regions, and including channels vertical to the semiconductor substrate and a plurality of memory cells stacked along the channels, wherein the active regions are directly connected to the channels of the first and second vertical strings.2. The device of claim 1 , further comprising a plurality of ion implantation regions in the active regions claim 1 , wherein the ion implantation regions connect the first and second vertical strings to the channels.3. The device of claim 2 , wherein the channels of the first and second vertical strings are formed at a boundary between the active regions and the ion implantation regions claim 2 , so that they are directly connected to both the active regions and the ion implantation regions.4. The device of claim 2 , wherein the first and second vertical strings are electrically connected to each other by the ion implantation regions during program and reading operations.5. A non-volatile memory device comprising:a conductive layer for applying an erase voltage formed on a semiconductor substrate; andfirst and second vertical strings formed on the conductive layer for applying an erase voltage and including channels vertical to the semiconductor substrate, and a plurality of memory cells stacked along the channels, wherein the conductive layer for applying an erase voltage is directly connected to the channels of the first and second vertical ...

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Номер записи: 29
13-03-2014 дата публикации

MULTI-CHIP PACKAGED INTEGRATED CIRCUIT WITH FLASH MEMORY

Номер: US20140071755A1
Автор: Ganapathy Kumar, Karamcheti Vijay
Принадлежит:

In one embodiment of the invention, a memory module is disclosed including a printed circuit board with an edge connector; an address controller coupled to the printed circuit board; and a plurality of memory slices. Each of the plurality of memory slices of the memory module includes one or more memory integrated circuits coupled to the printed circuit board, and a slave memory controller coupled to the printed circuit board and the one or more memory integrated circuits. The slave memory controller receives memory access requests for the memory module from the address controller. The slave memory controller selectively activates one or more of the one or more memory integrated circuits in the respective memory slice in response to the address received from the address controller to read data from or write data into selected memory locations in the memory integrated circuits. 159-. (canceled)60. A multi-chip packaged integrated circuit part to mount to a printed circuit board of a memory module , the multi-chip packaged integrated circuit part comprising: one or more pairs of', 'a spacer under the slave memory controller die, and', 'a flash memory die under the spacer,', 'wherein the flash memory die is larger than the spacer to provide an opening into a perimeter of the flash memory die to which electrical connections may be made., 'a slave memory controller (SMC) die, and'}, 'an integrated circuit package including'}61. The multi-chip packaged integrated circuit part of claim 60 , wherein the integrated circuit package is a multi-chip module integrated circuit package.62. The multi-chip packaged integrated circuit part of claim 60 , further comprising:a first plurality of conductors to electrically coupled the slave memory controller die to one or more independent pads of a pin-out of the integrated circuit package;a second plurality of conductors to electrically couple the slave memory controller die to one or more joint pads of the pin-out; anda third plurality ...

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Номер записи: 30
13-03-2014 дата публикации

THREE DIMENSIONAL STACKED NONVOLATILE SEMICONDUCTOR MEMORY

Номер: US20140071758A1
Автор: MAEJIMA Hiroshi
Принадлежит: KABUSHIKI KAISHA TOSHIBA

A three dimensional stacked nonvolatile semiconductor memory according to an example of the present invention includes a memory cell array comprised of first and second blocks disposed side by side in a first direction, and a driver disposed on one end of the memory cell array in a second direction orthogonal to the first direction. First select gate lines in the first block and first select gate lines in the second block are connected to the driver after they are commonly connected in one end in the second direction of the memory cell array in a relation of one to one. 1. A nonvolatile semiconductor memory comprising:a first memory cell array comprised of plurality of first blocks disposed on the semiconductor substrate, and each of plurality of blocks arranged in a first direction;a second memory cell array comprised of plurality of second blocks disposed on the semiconductor substrate, and each of plurality of blocks arranged in a first direction;a first driver disposed on the semiconductor substrate; anda second driver disposed on the semiconductor substrate,wherein each of the plurality of first blocks and the plurality of second blocks is comprised of at least three conductive layers stacked on the semiconductor substrate by being insulated from each other, and columnar semiconductors passing through the at least three conductive layers,wherein an uppermost layer of the at least three conductive layers is comprised of first select gate lines extending in a second direction orthogonal to the first direction, a lowermost layer of the at least three conductive layers is a second select gate line, remaining conductive layers excluding the uppermost layer and the lowermost layer of the at least three conductive layers are a word line,wherein select gate transistors are comprised of the first select gate lines and the columnar semiconductors, and the second select gate line and the columnar semiconductors, respectively, and memory cells are comprised of the word ...

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Номер записи: 31
13-03-2014 дата публикации

NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME

Номер: US20140071762A1
Автор: INOUE Satoshi
Принадлежит: KABUSHIKI KAISHA TOSHIBA

According to one embodiment, a nonvolatile semiconductor memory device includes a memory cell and a select gate transistor formed on a semiconductor substrate. The memory cell includes a first gate insulating film, a first charge storage layer, a first intergate insulating film, and a first control gate. The first gate insulating film, the first charge storage layer, the first intergate insulating film, and the first control gate are formed on the semiconductor substrate in order. The select gate transistor includes a second gate insulating film, a first gate electrode, a second intergate insulating film, and a second control gate. The second gate insulating film, the first gate electrode, the second intergate insulating film, and the second control gate are formed on the semiconductor substrate in order. The second intergate insulating film different first and second thicknesses. 1. A nonvolatile semiconductor memory device comprising: a first gate insulating film formed on the semiconductor substrate,', 'a first charge storage layer formed on the first gate insulating film,', 'a first intergate insulating film formed on the first charge storage layer, and', 'a first control gate formed on the first intergate insulating film; and, 'a memory cell formed on a semiconductor substrate, the memory cell comprising'} a second gate insulating film formed on the semiconductor substrate,', 'a first gate electrode formed on the second gate insulating film,', 'a second intergate insulating film formed on the first gate electrode and having different first and second thicknesses, and', 'a second control gate formed on the second intergate insulating film., 'a select gate transistor formed on the semiconductor substrate, the select gate transistor comprising'}2. The device according to claim 1 , whereinthe first thickness is the same as the thickness of the first intergate insulating film, and the second thickness is smaller than the first thickness.3. The device according to ...

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Номер записи: 32
20-03-2014 дата публикации

SEMICONDUCTOR DEVICE

Номер: US20140082345A1
Автор: ASANO Shigehiro, Kanno Shinichi, YANO Junji
Принадлежит: KABUSHIKI KAISHA TOSHIBA

On a single semiconductor package PK, m semiconductor chips CP to CPm are mounted, and the semiconductor package PK has external terminals T shared by m pad electrodes PD to PDm of the m semiconductor chips CP to CPm. An electrostatic protection circuit CD is mounted on only one CPm of the m semiconductor chips CP to CPm. 119-. (canceled)20. A semiconductor device comprising a semiconductor package:the semiconductor package comprising,a first chip comprising a first pad and a first circuit connected to the first pad via a first resistor,a second chip comprising a second pad and a second circuit connected to the second pad via a second resistor and an electrostatic protection circuit, the first chip and the second chip being overlapped with each other, andan external terminal electrically connected to the first pad and the second pad.21. The semiconductor device according to claim 20 , wherein the electrostatic protection circuit comprises a diode formed on the second chip.22. The semiconductor device according to claim 21 , wherein the first circuit and the second circuit comprise NAND flash memories.23. The semiconductor device according to claim 22 , wherein the first chip and the second chip are mounted on the semiconductor package.24. The semiconductor device according to claim 23 , wherein the semiconductor package mounting the first chip and the second chip comprises a NAND memory.25. The semiconductor device according to claim 24 , whereinthe first chip and the second chip include address terminals, data terminals, read/write terminals, and chip select terminals,the address terminals, the data terminals, and the read/write terminals are respectively connected to common external terminals of the semiconductor package via bonding wires, andeach of the chip select terminals is individually connected to an external terminal of the semiconductor package via a bonding wire.26. The semiconductor device according to claim 25 , further comprising:a controller that ...

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Номер записи: 33
27-03-2014 дата публикации

NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND CONTROL METHOD THEREOF

Номер: US20140085983A1
Автор: Hosono Koji
Принадлежит: KABUSHIKI KAISHA TOSHIBA

A nonvolatile semiconductor memory device includes a memory cell array having first and second groups of memory strings, each memory string including first and second memory cells connected between select transistors. The nonvolatile semiconductor memory device further includes a first word line connected to the first memory cells of the memory strings, a second word line connected to the second memory cells of the memory strings, and a control unit configured to control application of control voltages to the select transistors and the word lines, such that a select line voltage is applied to the first word line and a non-select line voltage is applied to the second word line and not discharged while select transistors of the first group of memory strings are turned off and select transistors of the second group of memory strings are turned on. 1. A nonvolatile semiconductor memory device , comprising:a memory cell array including at least first and second groups of memory strings, each of the memory strings including at least first and second memory cells serially connected between first and second select transistors;a plurality of word lines including a first word line commonly connected to the first memory cells of the memory strings and a second word line commonly connected to the second memory cells of the memory strings;a plurality of bit lines each connected to a different memory string in each of the groups of memory strings; anda control unit configured to control application of control voltages to the select transistors, the word lines, and the bit lines, whereina select line voltage is applied to the first word line and a non-select line voltage is applied to the other word lines while the first and second select transistors of the first group of memory strings are turned on, and the non-select line voltage remains applied to the other word lines while the first and second select transistors of the first group of memory strings are turned off and the ...

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Номер записи: 34
03-04-2014 дата публикации

Vertically-integrated nonvolatile memory devices having laterally-integrated ground select transistors

Номер: US20140092686A1
Автор: Jaehoon Jang, Jaehun Jeong, Kihyun Kim, Sunil Shim
Принадлежит: SAMSUNG ELECTRONICS CO LTD

Nonvolatile memory devices utilize vertically-stacked strings of nonvolatile memory cells (e.g., NAND-type strings) that can be selectively coupled to common source lines within a substrate. This selective coupling may be provided by lateral ground select transistors having different threshold voltages that account for different lateral spacings between the vertically-stacked strings of nonvolatile memory cells and the common source lines.

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Номер записи: 35
01-01-2015 дата публикации

SEMICONDUCTOR DEVICE AND OPERATION METHOD THEREOF

Номер: US20150003150A1
Автор: ARITOME Seiichi
Принадлежит: SK HYNIX INC.

A semiconductor device and a method of operating the same. The semiconductor device may include a plurality of memory blocks. Each of the plurality of memory blocks may include a plurality of cell strings extending substantially perpendicular to a semiconductor substrate, the plurality of cell strings sharing a plurality of bit lines, and a plurality of source lines respectively connected to the cell strings and word lines. Page buffers, connected to the bit lines, may store data. A selection switch portion may selectively transmit a voltage corresponding to data stored in the page buffers, and voltages supplied from an external source, to the bit lines and the source lines during the program operation, the read operation and the erase operation. A control circuit may control the page buffers and the selection switch portion. 1. A semiconductor device , comprising: a plurality of cell strings extending substantially perpendicular to a semiconductor substrate, the plurality of cell strings sharing a plurality of bit lines, and', 'a plurality of source lines respectively connected to the cell strings and word lines;, 'a plurality of memory blocks comprisingpage buffers, connected to the bit lines, suitable for storing data;a selection switch portion configured to selectively transmit a voltage corresponding to data stored in the page buffers, and voltages supplied from an external source, to the bit lines and the source lines during the program operation, the read operation and the erase operation; anda control circuit configured to control the page buffers and the selection switch portion.2. The semiconductor device of claim 1 , wherein the selection switch portion comprises: selectively transmit a first voltage, of the voltages, to the source lines, or', 'selectively transmit a voltage output from the page buffers to the source lines; and, 'a first selection circuit configured to selectively transmit a second voltage, of the voltages to the bit lines, or', ' ...

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Номер записи: 36
01-01-2015 дата публикации

SEMICONDUCTOR MEMORY DEVICE

Номер: US20150003157A1
Автор: ARITOME Seiichi
Принадлежит: SK HYNIX INC.

A semiconductor memory device includes a memory array including memory blocks stacked in a plurality of layers over a substrate and an operation circuit suitable for performing a read operation and a program loop to memory cells included in the memory blocks, wherein word lines of the memory blocks are coupled to each other and a pair of the memory blocks are arranged vertically adjacent to each other and share bit lines. 1. A semiconductor memory device , comprising:a memory array including memory blocks stacked in a plurality of layers over a substrate; andan operation circuit suitable for performing a read operation and a program loop to memory cells included in the memory blocks,wherein word lines of the memory blocks are coupled to each other, andwherein a pair of the memory blocks are arranged vertically adjacent to each other and share bit lines.2. The semiconductor memory device of claim 1 , wherein selection lines of the memory blocks in an odd-numbered layer are coupled to each other claim 1 , andwherein selection lines of the memory blocks in an even-numbered layer are coupled to each other.3. The semiconductor memory device of claim 2 , wherein the selection lines of the memory blocks sharing the bit lines and arranged vertically adjacent to each other are separated from each other.4. The semiconductor memory device of claim 1 , wherein selection lines of the memory blocks are separated from each other.5. The semiconductor memory device of claim 1 , wherein the memory blocks in an odd-numbered layer share the bit lines with an upper memory block and share a common source line with a lower memory block claim 1 , andwherein the memory blocks in an even-numbered layer share the common source line with an upper memory block and share the bit lines with a lower memory block.6. The semiconductor memory device of claim 1 , wherein the memory blocks in an even-numbered layer and the memory blocks in an odd-numbered layer are stacked with a vertical symmetry.7. ...

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Номер записи: 37
01-01-2015 дата публикации

SEMICONDUCTOR MEMORY DEVICE

Номер: US20150003158A1
Автор: ARITOME Seiichi
Принадлежит: SK HYNIX INC.

A semiconductor memory device includes a memory array including memory blocks stacked in a plurality of layers on a substrate, first vertical lines suitable for coupling bit lines, and second vertical lines suitable for coupling word lines of the memory blocks vertically stacked, wherein the memory blocks include selection lines vertically stacked and separated from each other, and the bit lines are coupled to the memory blocks and arranged in a plurality of layers. 1. A semiconductor memory device , comprising:a memory array including memory blocks stacked in a plurality of layers on a substrate;first vertical lines suitable for coupling bit lines; andsecond vertical lines suitable for coupling word lines of the memory blocks that are vertically stacked,wherein the memory blocks include selection lines vertically stacked and separated from each other, andwherein the bit lines are coupled to the memory blocks and arranged in the plurality of layers.2. The semiconductor memory device of claim 1 , wherein word lines of the memory blocks that are arranged in the same layer are separated from each other.3. The semiconductor memory device of claim 1 , wherein the memory block claim 1 , arranged in an odd-numbered layer claim 1 , shares the bit lines with the memory block claim 1 , arranged in an even-numbered layer arranged on the odd-numbered layer and shares common source line with the memory block claim 1 , arranged in an even-numbered layer arranged under the odd-numbered layer.4. The semiconductor memory device of claim 3 , wherein the bit lines and the common source lines are arranged in a direction crossing each other.5. The semiconductor memory device of claim 3 , wherein the memory block claim 3 , arranged in the even-numbered layer claim 3 , and the memory block claim 3 , arranged in the odd-numbered claim 3 , are stacked with vertical symmetry.6. The semiconductor memory device of claim 3 , wherein the common source lines of the memory blocks arranged in ...

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Номер записи: 38
01-01-2015 дата публикации

Semiconductor memory circuit and device

Номер: US20150003165A1
Автор: Yoshimitsu Yamauchi
Принадлежит: Sharp Corp

Provided is a semiconductor memory circuit including an oxide semiconductor insulated gate FET enabling advanced performance without being affected by a variation in threshold voltage. A semiconductor memory circuit MC includes a first transistor element T 1 composed of an insulated gate FET having a gate electrode connected to a memory node N 1 , a drain electrode connected to an intermediate node N 2 , and a source electrode connected to a data I/O terminal DIO; a second transistor element T 2 composed of an oxide semiconductor insulated gate FET having a gate electrode connected to a first control terminal CIN 1 , a drain electrode connected to the intermediate node N 2 , and a source electrode connected to the memory node N 1 ; a capacitive element C 1 having one end connected to a first voltage terminal VIN 1 and the other end connected to the memory node N 1 ; and a switching element S 1 for controlling a conducting state between a second control terminal CIN 2 or a second voltage terminal VIN 2 or the first voltage terminal VIN 1 , and the intermediate node N 2 , based on a voltage level of at least the second control terminal CIN 2.

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Номер записи: 39
05-01-2017 дата публикации

CONTROLLER FOR A SOLID-STATE DRIVE, AND RELATED SOLID-STATE DRIVE

Номер: US20170004039A1
Автор: Maffeis Margherita
Принадлежит:

A controller for a solid state drive is proposed. The solid state drive comprises a plurality of memory cells, wherein each memory cell comprises a floating gate transistor for storing a symbol when programmed with a threshold voltage associated with that symbol, and wherein each threshold voltage is variable over the memory cells of the plurality of memory cells thereby defining a corresponding threshold voltage distribution. The controller comprises: 1. A controller for a solid state drive , the solid state drive comprising a plurality of memory cells , wherein each memory cell comprises a floating gate transistor for storing a symbol when programmed with a threshold voltage associated with that symbol , and wherein each threshold voltage is variable over the memory cells of the plurality of memory cells thereby defining a corresponding threshold voltage distribution , the controller comprising:an encoding unit for encoding information bits into encoded bits;a mapping unit for mapping the encoded bits into symbols to be stored, each one for being stored into a respective target memory cell, said mapping unit mapping the encoded bits by associating the symbols to be stored with the target memory cells in such a way that the threshold voltage distributions associated with said symbols to be stored define overlapping regions smaller than a predetermined overlapping region indicative of an admitted bit error rate;a demapping unit for demapping read symbols read from the target memory cells and providing metrics indicative of a distance between the threshold voltage distributions associated with said read symbols,a conversion unit for converting said metrics into an indication of the reliability of the read symbols, anda soft decoding unit for soft decoding the read symbols according to said indication of the reliability of the read symbols thereby obtaining said information bits.2. The controller according to claim 1 , wherein said mapping unit further maps the ...

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Номер записи: 40
05-01-2017 дата публикации

CONTROLLER FOR A SOLID-STATE DRIVE, AND RELATED SOLID-STATE DRIVE

Номер: US20170004059A1
Автор: Maffeis Margherita
Принадлежит:

A controller for a solid state drive is proposed. The solid state drive comprises a plurality of memory cells. Each memory cell can store a symbol among a plurality of possible symbols the memory cell is designed to store, wherein each bit of each symbol is associated with a respective memory page. The memory cells are programmed and read simultaneously at memory page level. The controller comprises: 1. A controller for a solid state drive comprising a plurality of memory cells , wherein each memory cell can store a symbol among a plurality of possible symbols the memory cell is designed to store , wherein each bit of each symbol is associated with a respective memory page , the memory cells being programmed and read simultaneously at memory page level , and wherein the controller comprises: mark a memory page whose bit error rate overruns an admitted bit error rate as a failed memory page, each memory page other than a failed memory page defining an unfailed memory page, and', 'for a first group of memory cells which are associated with the failed memory page, determine first allowed symbols that are allowed to be stored in the first group of memory cells, said first allowed symbols being a subset of the plurality of the possible symbols such that the bits of the first allowed symbols associated with the unfailed memory pages include all possible bit combinations, and, 'a spreading unit configured toa writing unit configured to write information bits into the first group of memory cells according to the first allowed symbols.2. The controller according to claim 1 , wherein each memory cell comprises a floating gate transistor for storing a symbol when programmed with a threshold voltage associated with that symbol claim 1 , and wherein each threshold voltage is variable over the memory cells of the plurality of memory cells thereby defining a corresponding threshold voltage distribution claim 1 , said first allowed symbols being further selected according to a ...

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Номер записи: 41
13-01-2022 дата публикации

METHODS AND DEVICES FOR WEAR LEVELING

Номер: US20220011943A1
Автор: "Di Martino Alberto Jose", Grasso Rosario Roberto, Lo Giudice Gianbattista, MATRANGA Giovanni
Принадлежит:

A method of operating a non-volatile memory including having a first set of non-volatile memory cells and a second set of non-volatile memory cells. The first set of non-volatile memory cells and second set of non-volatile memory cells are associated with host addresses. Voltage levels are determined to erase the first and second sets of non-volatile memory cells. The first and second sets of non-volatile memory cells are disassociated from the host addresses. And, the first set of non-volatile memory cells is associated to another address based on the voltage level effective to erase the non-volatile memory cells. 1. A method of operating a non-volatile memory , the method comprising:having the non-volatile memory comprising a first set of non-volatile memory cells and a second set of non-volatile memory cells, the first set of non-volatile memory cells being associated with a first host address and the second set of non-volatile memory cells being associated with a second host address;determining a first voltage level effective to erase the first set of non-volatile memory cells;determining a second voltage level effective to erase the second set of non-volatile memory cells;disassociating the first set of non-volatile memory cells from the first host address;disassociating the second set of non-volatile memory cells from the second host address; andassociating the first set of non-volatile memory cells to the second host address based on the first voltage level effective to erase the first set of non-volatile memory cells.2. The method of wherein associating the first set of non-volatile memory cells to the second host address comprises determining the first voltage level is higher than the second voltage level.3. The method of further comprising:cycling the first set of non-volatile memory cells; anddetermining the first voltage level is no longer effective to erase the first set of non-volatile memory cells.4. The method of further comprising:associating the ...

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Номер записи: 42
07-01-2016 дата публикации

Semiconductor Device Having Features to Prevent Reverse Engineering

Номер: US20160005485A1
Автор: III William Eli, Thacker
Принадлежит:

A ROM circuit includes a first N channel transistor having an output and having device geometry and device characteristics adapted to bias the output at a predetermined level when a P channel circuit is connected to the first N channel transistor; a pass transistor connected between the output and a data bus, the pass transistor connected to a word line, the word line adapted to turn ON the pass transistor when the word line is asserted; and the P channel circuit connected to the data bus and adapted to provide leakage current to charge a gate in the first N channel transistor when pass transistor is turned ON. 1. A ROM circuit comprising:a first transistor having an output and having device geometry and device characteristics adapted to bias the output at a predetermined level indicating a binary 1 or a binary 0 when a circuit is connected to the first transistor through a pass transistor;the pass transistor connected between the output and a data bus, the pass transistor connected to a word line, the word line adapted to turn ON the pass transistor when the word line is asserted; andthe circuit connected to the data bus and adapted to provide leakage current to charge a gate in the first transistor when pass transistor is turned ON.2. The ROM circuit of wherein the gate of the first transistor is a floating gate.3. The ROM circuit of wherein the gate of the first transistor is connected to a gate of a second transistor.4. The ROM circuit of wherein the second transistor includes a second output and has device geometry and device characteristics adapted to bias the second output at a predetermined level when the circuit is connected to the second transistor.5. The ROM circuit of further comprising a read amplifier connected to the data bus.76. The ROM circuit of claim further comprising a security shield disposed over a surface of the ROM circuit.8. The ROM circuit of wherein the security shield comprises a metal trace extending over a portion of the surface of the ...

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Номер записи: 43
07-01-2021 дата публикации

NONVOLATILE MEMORY DEVICES AND OPERATING METHODS THEREOF

Номер: US20210005261A1
Автор: KIM Ji-Sung, Shin Hoyoung, Shin Hyun-Jin
Принадлежит:

A nonvolatile memory device includes a memory cell array including a main memory area and a dummy memory area, a row decoder, a bit line selection circuit, a data input/output circuit, a control circuit, and a voltage generator. The bit line selection circuit is configured to select a first main bit line during a program time and is configured to select a dummy bit line during a column address switch time. During the column address switch time, a second main bit line is selected. The voltage generator is configured to output, to the row decoder, a source line voltage to be applied to a selected source line during the program time and during the column address switch time, wherein the source line voltage is maintained at a voltage level during the program time and during the column address switch time. 1. A nonvolatile memory device comprising:a memory cell array including a main memory area and a dummy memory area, wherein the main memory area is connected to a plurality of main bit lines and the dummy memory area is connected to a dummy bit line;a row decoder connected to the memory cell array through a plurality of word lines and a plurality of source lines;a bit line selection circuit configured to select at least one main bit line of the plurality of main bit lines during a program time and configured to select the dummy bit line during a column address switch time that occurs after the program time;a data input/output circuit connected to the bit line selection circuit through a plurality of data lines;a control circuit configured to control the row decoder and the bit line selection circuit based on an address and a command; anda voltage generator configured to output, to the row decoder, a source line voltage to be applied to a source line selected from the plurality of source lines during the program time and during the column address switch time,wherein a voltage level of the source line voltage during the program time equals a voltage level of the source ...

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Номер записи: 44
04-01-2018 дата публикации

Semiconductor Structure and Method for Forming the Same

Номер: US20180006046A1
Автор: CHEN Hsin-Chi, Chuang Chiang-Ming, Chuang Kun-Tsang, Lee Chih-Ming, Liao Hung-Che, Liu Chien-Hsuan
Принадлежит:

A semiconductor structure includes a semiconductor substrate, at least one raised dummy feature, at least one memory cell, and at least one word line. The raised dummy feature is present on the semiconductor substrate and defines a cell region on the semiconductor substrate. The memory cell is present on the cell region. The word line is present adjacent to the memory cell. 1. A device comprising:a memory cell array, the memory cell array including at least one memory cell gate stack, the at least one memory cell gate stack including a first stack of first materials; anda dummy feature, the dummy feature including at least one dummy gate stack that at least partially surrounds the memory cell array, the at least one dummy gate stack including a second stack of the first materials.2. The device of claim 1 , further comprising:the first stack of first materials including a tunneling layer, a floating gate atop the tunneling layer, a blocking layer atop the floating gate, a control gate atop the blocking layer and a capping layer atop the control gate; anda sidewall spacer along a sidewall of the capping layer, the control gate and the blocking layer and wherein the floating gate extends under the sidewall spacer.3. The device of claim 1 , wherein the at least one memory cell gate stack has a first height and the at least one dummy gate stack has a second height claim 1 , the second height being equal to the first height.4. The device of claim 1 , further comprising a second dummy feature claim 1 , the second dummy feature including at least one second dummy gate stack that a least partially surrounds the dummy gate stack claim 1 , the at least one second dummy gate stack including a third stack of the first materials.5. The device of claim 1 , wherein the dummy feature encircles the memory cell array.6. The device of claim 1 , wherein the dummy feature has at least one opening communicating the memory cell array with a non-memory cell region outside of the memory cell ...

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Номер записи: 45
03-01-2019 дата публикации

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

Номер: US20190006380A1
Автор: LIU Chen-Chin, Lu Yi Hsien, Wang Yu-Hsiung, Wu Wei Cheng, YANG Juo-Li
Принадлежит:

In a method of manufacturing a semiconductor device, a memory cell structure covered by a protective layer is formed in a memory cell area of a substrate. A mask pattern is formed. The mask pattern has an opening over a first circuit area, while the memory cell area and a second circuit area are covered by the mask pattern. The substrate in the first circuit area is recessed, while the memory cell area and the second circuit area are protected. A first field effect transistor (FET) having a first gate dielectric layer is formed in the first circuit area over the recessed substrate and a second FET having a second gate dielectric layer is formed in the second circuit area over the substrate as viewed in cross section. 1. A semiconductor device including:a non-volatile memory cell formed in a memory cell area of a substrate;a first circuit formed in a first circuit area of the substrate; anda second circuit formed in a second circuit area of the substrate,wherein a first device forming surface of the substrate in the first circuit area is located at a lower level than a second device forming surface of the substrate in the second circuit area as viewed in cross section.2. The semiconductor device of claim 1 , wherein:the first circuit includes a first field effect transistor (FET) having a first gate dielectric layer,the second circuit includes a second FET having a second gate dielectric layer, anda thickness of the first gate dielectric layer is greater than a thickness of the second gate dielectric layer.3. The semiconductor device of claim 1 , wherein an operational voltage of the first circuit is higher than an operational voltage of the second circuit.4. The semiconductor device of claim 1 , wherein a memory cell forming surface of the substrate in the memory cell area is located at a lower level than the first device forming surface of the substrate in the first circuit area as viewed in cross section.5. The semiconductor device of claim 1 , further comprising ...

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Номер записи: 46
08-01-2015 дата публикации

TEMPERATURE COMPENSATION METHOD FOR HIGH-DENSITY FLOATING-GATE MEMORY

Номер: US20150008496A1
Автор: Chakrabartty Shantanu, GU Ming, Huang Chenling
Принадлежит: BOARD OF TRUSTEES OF MICHIGAN STATE UNIVERSITY

A temperature compensation technique is provided for a non-volatile memory arrangement. The memory arrangement includes: a memory circuit () having a floating gate transistor (P) operating in weak-inversion mode and a varactor (C) with a terminal electrically coupled to a gate node of the floating gate transistor; a first current reference circuit () having a floating gate transistor (PI); a second current reference circuit () having a floating gate transistor (P); and a control module () configured to selectively receive a reference current (I, I) from a drain of the floating gate transistor in each of the first and second current reference circuits. The control module operates to determine a ratio between the reference currents received from the first and second current reference circuits, generate a tuning voltage (V) in accordance with the ratio between the reference currents and apply the tuning voltage to the varactor in the memory circuit. 1. A non-volatile memory arrangement , comprising:a first memory circuit having a floating gate transistor with a gate node and operating in weak-inversion mode, and a varactor with first terminal electrically coupled to the gate node of the floating gate transistor; anda control module electrically coupled to a second terminal of the varactor and operable to tune a voltage applied to the varactor, thereby compensating for temperature changes.2. The non-volatile memory arrangement of wherein the varactor is further defined as a metal-oxide semiconductor capacitor operating in accumulation mode.3. The non-volatile memory arrangement of wherein the first memory circuit further includes a tunneling capacitor coupled electrically to the gate node of the floating gate transistor and a control-gate capacitor coupled electrically to the gate node of the floating gate transistor claim 1 , wherein the tunneling capacitor configured to receive an injection current for the first memory circuit.4. The non-volatile memory arrangement of ...

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Номер записи: 47
08-01-2015 дата публикации

SEMICONDUCTOR MEMORY DEVICE AND METHOD OF OPERATING THE SAME

Номер: US20150009758A1
Автор: Jang Yoon Soo
Принадлежит: SK HYNIX INC.

A semiconductor memory device and a method of operating the same are provided. The semiconductor memory device includes memory cells stacked on a substrate. The method includes applying a reference voltage to an unselected drain select line, applying a drain selection voltage to a selected drain select line, and applying a word line voltage to a normal word line. Before the word line voltage is applied to the normal word line, a positive voltage is applied to a dummy word line to bounce the unselected drain select line. 1. A method of operating a semiconductor memory device comprising memory cells stacked on a substrate , the method comprising:applying a reference voltage to an unselected drain select line;applying a drain selection voltage to a selected drain select line; andapplying a word line voltage to a normal word line,wherein, before the word line voltage is applied to the normal word line, a positive voltage is applied to a dummy word line.2. The method of claim 1 , wherein the positive voltage applied to the dummy word line bounces the unselected drain select line.3. The method of claim 1 , wherein the positive voltage is applied to the dummy word line during the application of the reference voltage to the unselected drain select line.4. The method of claim 1 , wherein claim 1 , before the application of the reference voltage to the unselected drain select line claim 1 , the positive voltage is applied to the dummy word line during an application of a precharge voltage to the unselected drain select line.5. The method of claim 4 , wherein the application of the precharge voltage is ended before the word line voltage is applied to the normal word line.6. The method of claim 1 , wherein claim 1 , during the application of the drain selection voltage to the selected drain select line claim 1 , the positive voltage is applied to the dummy word line.7. The method of claim 1 , wherein claim 1 , before the drain selection voltage is applied to the selected drain ...

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Номер записи: 48
12-01-2017 дата публикации

DUAL NON-VOLATILE MEMORY CELL COMPRISING AN ERASE TRANSISTOR

Номер: US20170011804A1
Автор: La Rosa Francesco, NIEL Stephan, Regnier Arnaud
Принадлежит:

The present disclosure relates to a non-volatile memory cell on a semiconductor substrate, comprising a first transistor comprising a control gate, a floating gate and a drain region, a second transistor comprising a control gate, a floating gate and a drain region, in which the floating gates of the first and second transistors are electrically coupled, and the second transistor comprises a conducting region electrically coupled to its drain region and extending opposite its floating gate through a tunnel dielectric layer. 1. A method , comprising: a first floating-gate transistor having a control gate, a floating gate, and a drain region;', 'a second floating-gate transistor having a control gate, a floating gate, and a drain region, wherein:', a tunnel dielectric layer extending along the floating gate of the second floating-gate transistor; and', 'a permanently conductive region electrically coupled to the drain region of the second floating-gate transistor and extending along an opposite side of the tunnel dielectric layer with respect to the floating gate of the second floating-gate transistor, the method comprising:, 'the floating gates of the first and second floating-gate transistors are electrically coupled to each other, and the second floating-gate transistor comprises], 'manufacturing on a semiconductor substrate a memory cell that includesforming in the substrate isolating trenches delimiting first and second strips of the substrate,making the second strip permanently conductive by doping the second strip,forming a first dielectric layer on the substrate and forming the floating gate of the first floating gate transistor on the first dielectric layer, the floating gate being arranged transversally to the two strips of substrate,forming a second dielectric layer on the floating gate of the first floating gate transistor and forming the control gate of the first floating gate transistor on the floating gate with of the first floating gate transistor, to ...

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Номер записи: 49
12-01-2017 дата публикации

Method to Reduce Program Disturbs in Non-Volatile Memory Cells

Номер: US20170011807A1
Автор: Georgescu Bogdan, HIROSE Ryan T., Kouznetsov Igor G., Prabhakar Venkatraman, Shakeri Kaveh
Принадлежит:

A non-volatile memory and methods of operating the same to reduce disturbs is provided. In one embodiment, the method includes coupling a first positive high voltage to a first global wordline in a first row of an array of memory cells, and coupling a second negative high voltage (V) to a first bitline in a first column of the array to apply a bias to a non-volatile memory transistor in a selected memory cell to program the selected memory cell. A margin voltage having a magnitude less than VNEG is coupled to a second global wordline in a second row of the array, and an inhibit voltage coupled to a second bitline in a second column of the array to reduce a bias applied to a non-volatile memory transistor in an unselected memory cell to reduce program disturb of data programmed in the unselected memory cell due to programming. 120-. (canceled)21. A circuit , comprising: 'a plurality of memory cells, each comprising at least a non-volatile memory (NVM) transistor, arranged in rows and columns, wherein gates of the NVM transistors of memory cells in a same row couple to and share a global wordline; and', 'a memory array including,'} a first voltage to a first global wordline in a first row of the memory array, and a second voltage to source-drain paths of memory cells in a first column of the memory array to apply a bias voltage to the NVM transistor in a selected memory cell to program the selected memory cell, and', 'a third voltage to source-drain paths of memory cells in a second column of the memory array., 'a programmable control circuitry coupled to the memory array, wherein the programmable control circuitry includes a voltage control circuitry configured to provide,'}22. The circuit of claim 21 , wherein each of the plurality of memory cells further includes a first end and a second end claim 21 , wherein the second ends of memory cells in a same column are coupled to and share a bitline.23. The circuit of claim 22 , wherein the first and second voltages are ...

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Номер записи: 50
12-01-2017 дата публикации

SELF-ALIGNED FLOATING GATE IN A VERTICAL MEMORY STRUCTURE

Номер: US20170011928A1
Автор: Koval Randy J.
Принадлежит: Intel Corporation

A memory device or electronic system may include a memory cell body extending from a substrate, a self-aligned floating gate separated from the memory cell body by a tunneling dielectric film, and a control gate separated from the self-aligned floating gate by a blocking dielectric film. The floating gate is flanked by the memory cell body and the control gate to form a memory cell, and the self-aligned floating gate is at least as thick as the control gate. Methods for building such a memory device are also disclosed. 1. (canceled)2. A method of manufacturing a memory device comprising:creating a stackup of at least three tier insulating layers alternating with at least two circuit layers, the circuit layers individually include a conductive layer sandwiched between sacrificial layers that are differentiated from the tier insulating layer to allow selective etching of the sacrificial layers without etching the tier insulating layers;creating a hole through the stackup;etching the conductive layers back from the hole;etching the sacrificial layers back from the hole;forming a blocking dielectric film inside at least a portion of the hole, the blocking dielectric film no thicker than an individual sacrificial layer of the sacrificial layers;creating floating gates in the cavities created by the etching of the conductive layers and the sacrificial layers, the floating gates separated from the conductive layers and the tier insulating layers by the blocking dielectric film;forming a tunneling dielectric film inside the hole; andfilling the hole with semiconductor material, the semiconductor material separated from the floating gates by the tunneling dielectric film.3. The method of claim 2 , the conductive layers claim 2 , the floating gates and the semiconductor material comprise polysilicon claim 2 , and the tier insulating layers and the sacrificial layers comprise an oxide or a nitride.4. The method of claim 2 , further comprising:creating an outer oxide film on an ...

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Номер записи: 51
10-01-2019 дата публикации

FLASH MEMORY PACKAGE AND STORAGE SYSTEM INCLUDING FLASH MEMORY PACKAGE

Номер: US20190012260A1
Автор: Arai Masahiro, Kawamura Atsushi, Okada Mitsuhiro
Принадлежит: Hitachi, Ltd.

A flash memory package has a controller and at least one memory including a flash memory. The controller stores received write data in a primary storage area, which is a partial storage area of the memory, sets the unit of storage area including the plurality of physical pages as the unit of collective transfer to perform collective transfer and, when a volume of data accumulated in the primary storage area is equal to or larger than the capacity of one unit of collective transfer of the flash memory, collectively transfers a volume of data corresponding to the capacity of at least one unit of collective transfer from the primary storage area to a secondary storage area, which is a partial storage area of the flash memory. 1. A flash memory package comprising: a controller; and at least one memory including a flash memory , whereinthe flash memory includes a plurality of physical blocks, each of the physical blocks is the unit of data erasure, the physical blocks each include a plurality of physical pages, and each of the physical pages is the unit of data write, andthe controller is configured to:store received write data in a primary storage area, which is a partial storage area of the memory;set the unit of storage area including the plurality of physical pages as the unit of collective transfer to perform collective transfer; andwhen a volume of data accumulated in the primary storage area is equal to or larger than a capacity of one unit of collective transfer of the flash memory, collectively transfer a volume of data corresponding to the capacity of at least one unit of collective transfer from the primary storage area to a secondary storage area, which is a partial storage area of the flash memory.2. The flash memory package according to claim 1 , further comprising:page management information including information indicating a relation between a position of a logical page and a logical block; andblock management information including information indicating ...

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Номер записи: 52
14-01-2016 дата публикации

THREE DIMENSIONAL MEMORY DEVICE AND DATA ERASE METHOD THEREOF

Номер: US20160012901A1
Автор: Hsu Tzu-Hsuan, Lue Hang-Ting, WU Chen-Jun
Принадлежит:

A data erase method of a three dimensional (3D) memory device comprising the following steps. First, in a first phase of an erase operation, a first voltage is applied to a first semiconductor channel of the semiconductor channels to erase data stored in the memory cells defined on the first semiconductor channel and a second voltage is applied to a second semiconductor channel of the semiconductor channels, wherein the second semiconductor channel is adjacent to the first semiconductor channel. Then, in a second phase of the erase operation, the second voltage is applied to the first semiconductor channel and the first voltage is applied to the second semiconductor channel. 1. A data erase method of a three dimensional (3D) memory device , wherein the 3D memory device comprises a plurality of word lines and a plurality of semiconductor channels , the semiconductor channels intersect with the word lines to form a plurality of memory cells , the data erase method comprises:in a first phase of an erase operation, applying a first voltage to a first semiconductor channel of the semiconductor channels to erase data stored in the memory cells defined on the first semiconductor channel and applying a second voltage to a second semiconductor channel of the semiconductor channels, wherein the second semiconductor channel is adjacent to the first semiconductor channel;in a second phase of the erase operation, applying the second voltage to the first semiconductor channel and applying the first voltage to the second semiconductor channel.2. The data erase method according to claim 1 , wherein the first and second semiconductor channels are disposed on adjacent layers of a memory stack and separated by a dielectric strip claim 1 , the word lines are disposed on the sidewall of the memory stack claim 1 , the data erase method further comprises:in the first phase, applying the first voltage on both ends of the first semiconductor channel and applying the second voltage on both ...

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Номер записи: 53
10-01-2019 дата публикации

MANAGED NAND POWER MANAGEMENT

Номер: US20190013079A1
Автор: Blodgett Greg A., Jean Sebastien Andre
Принадлежит:

Apparatus and methods are disclosed including a memory device or a memory controller configured to receive, from a host device over a host interface, a request for a device descriptor of a memory device, and to send to the host, over the host interface, the device descriptor, the device descriptor including voltage supply capability fields that are set to indicate supported voltages of the memory device, the supported voltages selected from a plurality of discrete voltages. The host device can utilize the supported voltages to supply an appropriate voltage to the memory device. Methods of operation are disclosed, as well as machine-readable medium, a host computing device, and other embodiments. 1. A memory device comprising:an array of memory cells; receiving, from a host device over a host interface, a request for a device descriptor of a memory device; and', 'sending to the host device, over the host interface, the device descriptor, the device descriptor including voltage supply capability fields that are set to indicate supported voltages of the memory device, the supported voltages selected from a plurality of discrete voltages, and wherein the host device utilizes the supported voltages to supply an appropriate voltage to the memory device., 'a memory controller, configured to perform operations comprising2. The memory device of claim 1 , wherein the voltage supply capability fields includes a VCC voltage capability field.3. The memory device of claim 1 , wherein the voltage supply capability fields includes a VCCQ voltage capability field.4. The memory device of claim 1 , wherein the voltage supply capability fields includes a VCCQ2 voltage capability field.5. The memory device of claim 1 , wherein the voltage supply capability fields indicates that the memory device is compliant with Universal Flash Storage (UFS) version 2.1 voltage levels.6. The memory device of claim 1 , wherein the voltage supply capability fields indicates that the memory device is ...

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Номер записи: 54
10-01-2019 дата публикации

MANAGED NAND PERFORMANCE THROTTLING

Номер: US20190013081A1
Автор: Blodgett Greg A., Jean Sebastien Andre
Принадлежит:

Apparatus and methods are disclosed, including a memory device or a memory controller configured to determine that a condition has occurred that indicates a performance throttling operation, implement a performance throttling responsive to the determined condition, responsive to implementing the performance throttling, set a performance throttling status indicator in an exception event status attribute, receive a command from a host device across a memory device interface, perform the command, prepare a response to the command, the response including a flag indicating that the performance throttling status indicator is set in the exception event status attribute, and send the response to the host device. Methods of operation are disclosed, as well as machine-readable medium and other embodiments. 1. A memory device comprising:a non-volatile memory array; determining that a condition has occurred that indicates a performance throttling operation;', 'implementing a performance throttling responsive to the determined condition;', 'responsive to implementing the performance throttling, setting a performance throttling status indicator in an exception event status attribute;', 'receiving a command from a host device across a memory device interface;', 'performing the command;', 'preparing a response to the command, the response including a flag indicating that the performance throttling status indicator is set in the exception event status attribute; and', 'sending the response to the host device., 'a memory controller configured to perform the operations comprising2. The memory device of claim 1 , wherein the response is formatted as a Universal Flash Storage Protocol Information Unit (UPIU) message.3. The memory device of claim 1 , wherein the host device and the memory device communicate using a Universal Flash Storage family of standards.4. The memory device of claim 1 , wherein the memory controller is further configured to perform the operations of:setting a ...

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Номер записи: 55
19-01-2017 дата публикации

METHOD FOR FABRICATING A FLASH MEMORY

Номер: US20170018649A1
Автор: Chen Chih-Jung, CHEN Tzu-Ping
Принадлежит:

A method for fabricating semiconductor device is disclosed. First, a substrate is provided, and a dielectric stack is formed on the substrate, in which the dielectric stack includes a first silicon oxide layer and a first silicon nitride layer. Next, the dielectric stack is patterned, part of the first silicon nitride layer is removed to form two recesses under two ends of the first silicon nitride layer, second silicon oxide layers are formed in the two recesses, a spacer is formed on the second silicon oxide layers, and third silicon oxide layers are formed adjacent to the second silicon oxide layers. 1. A method for fabricating semiconductor device , comprising:providing a substrate;forming a dielectric stack on the substrate, wherein the dielectric stack comprises a first silicon oxide layer and a first silicon nitride layer;patterning the dielectric stack;removing part of the first silicon nitride layer for forming two recesses under two ends of the first silicon nitride layer;forming second silicon oxide layers in the two recesses;forming a spacer on the second silicon oxide layers; andforming third silicon oxide layers adjacent to the second silicon oxide layers.2. The method of claim 1 , further comprising:forming a patterned resist on the dielectric stack;using the patterned resist as mask to pattern the dielectric stack by removing part of the first silicon nitride layer;performing a dry etching process to remove the first silicon oxide layer not covered by the first silicon nitride layer;performing a wet etching process to remove part of the silicon oxide layer under the first silicon nitride layer for forming the two recesses under two ends of the first silicon nitride layer; andstripping the patterned resist.3. The method of claim 1 , further comprising performing an n-type implantation process after forming the second silicon oxide layers for forming a buried n+ region in the substrate.4. The method of claim 1 , further comprising:forming a second ...

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Номер записи: 56
18-01-2018 дата публикации

NONVOLATILE MEMORY DEVICES AND METHODS FORMING THE SAME

Номер: US20180019258A1
Автор: LEE Changhyun, SON Byoungkeun
Принадлежит:

Provided are nonvolatile memory devices and methods of forming the same. The nonvolatile memory device includes a plurality of word lines, a ground select line, string select line, and a dummy word line. Each of distances between the dummy word line and the ground select line and between the dummy word line and the word line is greater than a distance between a pair of the word lines adjacent to each other. 18-. (canceled)9. A nonvolatile memory device comprising:a substrate;a ground select line on the substrate;a plurality of word lines vertically stacked on the ground select line;a string select line on the plurality of word lines;a first dummy word line between the ground select line and a first word line, wherein the first word line is nearest to the ground select line among the word lines; anda second dummy word line between the string select line and a second word line, wherein the second word line is nearest to the string select line among the word lines,wherein a first distance between a bottom surface of the ground select line and a bottom surface of the first dummy word line is greater than a second distance between the bottom surface of the first dummy word line and a bottom surface of the first word line, andwherein a third distance between bottom surfaces of adjacent ones of the word lines is less than the second distance.10. The nonvolatile memory device of claim 9 ,wherein a bottom surface of the second dummy word line is vertically spaced apart from a bottom surface of the second word line by a fourth distance, andwherein the fourth distance is greater than the third distance and is less than the first distance.11. The nonvolatile memory device of claim 9 ,wherein a bottom surface of the string select line is vertically spaced apart from a bottom surface of the second dummy word line by a fifth distance, andwherein the fifth distance is greater than the second distance and the third distance.12. The nonvolatile memory device of claim 9 , wherein each ...

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Номер записи: 57
17-04-2014 дата публикации

NONVOLATILE MEMORY DEVICES AND METHODS FORMING THE SAME

Номер: US20140104945A1
Автор: LEE Changhyun, SON Byoungkeun
Принадлежит: SAMSUNG ELECTRONICS CO., LTD.

Provided are nonvolatile memory devices and methods of forming the same. The nonvolatile memory device includes a plurality of word lines, a ground select line, string select line, and a dummy word line. Each of distances between the dummy word line and the ground select line and between the dummy word line and the word line is greater than a distance between a pair of the word lines adjacent to each other. 1. A method of forming a nonvolatile memory device , comprising:alternately and repeatedly forming gate patterns and insulating patterns on a semiconductor substrate;forming semiconductor patterns which penetrate the gate patterns and the insulating patterns and upwardly extend from the semiconductor substrate; andforming a data storage layer between the semiconductor patterns and the gate patterns,wherein the gate patterns include a plurality of word lines, a ground select line under the word lines, a string select line on the word lines, a first dummy word line between the ground select line and a first word line, wherein the first word line is nearest to the ground select line among the word lines, and a second dummy word line between the string select line and a second word line, wherein the second word line is nearest to the string select line among the word lines, andwherein each of a first distance between the ground select line and the first dummy word line and a second distance between the first dummy word line and the first word line is greater than a third distance between a pair of the word lines adjacent to each other.2. The method of claim 1 , wherein each of a distance between the string select line and the second dummy word line and a distance between the second dummy word line and the second word line is greater than the third distance.3. The method of claim 1 , wherein forming the gate patterns and the insulating patterns comprises:alternately and repeatedly forming first insulating layers and second insulating layers on the semiconductor ...

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Номер записи: 58
22-01-2015 дата публикации

Dynamic Regulation of Memory Array Source Line

Номер: US20150023100A1
Автор: Huynh Jonathan H., Pan Feng, Wang Sung-En
Принадлежит:

To maintain stability of memory array operations, a current source supplies a common source line of a memory. The magnitude of the regulation current from the source is dynamically determined based on the amount of current from the array itself through use of a feedback control signal provided by a current comparator circuit. The current comparison circuit can use either a digital or an analog implementation. 1. A non-volatile memory circuit , comprising:an array of non-volatile memory cells arranged along a plurality of bit lines connected to a common source line;a pull down device connected between the common source line and ground;a first op-amp having a first input connected to the common source line, a second input connected to receive a first reference level, and an output connected to control the pull down device;a variable current source connected between a first supply level and the common source line; anda current comparison circuit connected to the pull down device to perform a comparison of the amount of current flowing through the pull down device to a reference value and having an output connected to control the variable current source based upon the comparison.2. The non-volatile memory circuit of claim 1 , wherein the pull-down device includes a first transistor connected between the common source line and ground and having a gate connected to receive the output of the first op-amp.3. The non-volatile memory circuit of claim 2 , wherein the current comparison circuit includes:a current mirror connected between a second supply level and ground, having a first leg connected to ground through a second transistor having a gate connected to receive the output of the first op-amp and a second leg connected to ground through a reference current source; anda second op-amp having a first input connected to receive a second reference level, having a second input connected to a node of the second leg above the reference current source, and having an output that ...

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Номер записи: 59
16-01-2020 дата публикации

ENHANCED NVDIMM ARCHITECTURE

Номер: US20200020360A1
Автор: Kosuru Trinadhachari, McPadden Adam J., Sethuraman Saravanan, Swaminathan Janani
Принадлежит:

Aspects of the present disclosure relate to a memory module having a volatile memory, a high speed non-volatile memory, and a non-volatile memory. The memory module can allow write mirroring to the volatile memory and high speed non-volatile memory simultaneously. An I/O request is received. A determination is made whether the I/O request is a write or a read. In response to determining that the I/O request is a read, data included in the high speed non-volatile memory is transferred to the non-volatile memory. In response to determining that the I/O request is a write, at least one location to write data of the write is determined based on decoding bits of the write command. The data of the write can then be written to the at least one location. 1. A system comprising:a memory module including a volatile memory, a high speed non-volatile memory (high speed NVM), and a non-volatile memory; and receiving an I/O request;', 'determining whether the I/O request is a write or a read;', 'in response to determining that the I/O request is a read,', 'transferring data included in the high speed non-volatile memory to the non-volatile memory;', 'in response to determining that the I/O request is a write,', 'determining at least one location to write data of the write based on decoding bits of the write; and', 'writing, based on the decoded bits, the data of the write to the at least one location., 'one or more processing circuits, wherein the one or more processing circuits are configured to perform a method comprising2. The system of claim 1 , wherein the I/O request is the write claim 1 , wherein determining at least one location to write data of the write based on decoding bits of the write and writing the data of the write to the at least one location comprises:determining, based on the decoded bits, that the data of the write should be written to the volatile memory and high speed NVM simultaneously; andwriting the data of the write to the volatile memory and high speed ...

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Номер записи: 60
21-01-2021 дата публикации

SOLID STATE DRIVE ARCHITECTURES

Номер: US20210020245A1
Автор: McKenzie Robert Neil, Peddle Charles I., Snelgrove Martin, Snelgrove Xavier
Принадлежит: THSTYME BERMUDA LIMITED

A solid state drive includes DRAM logical flash and flash memory, in which system processor reads and writes only to the DRAM logical flash which minimizes writes to the flash memory. A method for operation of a solid state flash device includes writing, by a CPU, to a solid state drive by sending commands and data to DRAM logical flash using flash commands and formatting. 1. A solid state drive (SSD) comprising: DRAM memory; and', 'a DRAM controller to manage data transfers into and out of the DRAM memory;, 'Dynamic Random Access Memory (DRAM) logical flash which stores files in the same way as NAND flash and responds to flash commands, wherein the DRAM logical flash comprisesflash memory;a master SSD controller; andan interface to connect the SSD to a host having a Central Processing Unit (CPU) such that the CPU exclusively reads data from, and writes to, the DRAM logical flash, the DRAM logical flash providing principal data storage during operation of the CPU;the SSD controller to independently determine when to transfer the data from the DRAM logical flash to the flash memory;wherein the master SSD controller organizes data in the DRAM using a File Access Table (FAT) or New Technology File System (NTFS) in a same way that data is organized in the Flash memory; andwherein a majority of memory commands are handled by the master SSD controller using DRAM so as to reduce a number of writes to the Flash memory, the master controller is configured to independently determine when data should be transferred between the DRAM and the flash memory to reduce a number of write/erase cycles for the flash memory, the master SSD controller is configured to determine when to move data to or from the DRAM based on factors including lack of use of the data.2. The drive of claim 1 , further comprising an energy storage device storing enough power to move data content stored in the DRAM to the flash memory if external power to the solid state drive is interrupted.3. The drive of ...

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Номер записи: 61
21-01-2021 дата публикации

Memory structure for self-erasing secret storage

Номер: US20210020775A1
Автор: Elad Peer, Elena Sidorov, Rami Sudai, Reuven Elbaum, Steve J. Brown, Uri Bear
Принадлежит: Intel Corp

In one embodiment, memory cell includes a control gate, a floating gate, a substrate comprising a source region and a drain region, a first isolator between the control gate and floating gate, and a second isolator between the floating gate and the substrate. The memory cell is configured to have a retention time that is within a statistical window around a selected lifespan. The selected lifespan may be less than ten years, such as, for example, less than one year, less than one month, or less than one week.

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Номер записи: 62
28-01-2016 дата публикации

Pulse Control For Non-Volatile Memory

Номер: US20160027515A1
Автор: Bronner Gary B., Donnelly Kevin, Haukness Brent Steven, Kellam Mark D.
Принадлежит:

A nonvolatile memory device that uses pulsed control and rest periods to mitigate the formation of defect precursors. A first embodiment uses pulsed bitline control, where the coupling between a memory cell channel and a reference voltage is pulsed when it is desired to change state in the associated memory cell. Each pulse may be chosen to be less than about 20 nanoseconds, while a “rest period” between pulses can be on the order of about a hundred nanoseconds or greater. Because bitline control is used, very short rise times can be enabled, enabling generation of pulse durations of 50 nanoseconds or less. In other embodiments, these methods may also be more generally applied to other conductors (e.g., wordline or substrate well, for program or erase operations); segmented wordlines or bitlines may also be used, to minimize RC loading and enable sufficiently short rise times to make pulses robust. 1. A method of changing state in memory cells of a nonvolatile memory device , where each memory cell has a floating gate , a first conductor and a second conductor , where each memory cell is to store charge on the floating gate according to a potential difference between the first conductor and the second conductor , to indicate a first state in the respective memory cell , and where data is to be programmed or erased in each memory cell using multiple program-verify cycles , each program-verify cycle comprising a program portion and a verify portion , the method comprising:during the program portion of each program-verify cycle, repeatedly pulsing application of the potential difference between the first conductor and the second conductor, dependent on state of a corresponding bit line, to provide for a pulsed voltage drop across the memory cell dependent on the state of the corresponding bit line; andfor each memory cell to which the pulsed voltage drop is to be provided, between each application of the potential difference, providing for a rest period.2. The method ...

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Номер записи: 63
10-02-2022 дата публикации

METHOD AND APPARATUS FOR CONVOLUTIONAL COMPUTATION BASED ON FLOATING GATE NVM ARRAY

Номер: US20220043885A1
Автор: Conte Antonino, La Rosa Francesco
Принадлежит:

In an embodiment a method programming floating gate transistors belonging to non-volatile memory cells to multilevel threshold voltages respectively corresponding to the weight factors, performing a sensing operation of the programmed floating gate transistors with a control signal adapted to make the corresponding memory cells become conductive at an instant determined by a respective programmed threshold voltage, performing the convolutional computation by using the input values during an elapsed time for each memory cell to become conductive and outputting output values resulting from the convolutional computation. 1. A method for convolutional computing input values with weight factors of a convolutional matrix operator , the method comprising:programming floating gate transistors belonging to non-volatile memory cells to multilevel threshold voltages respectively corresponding to the weight factors;performing a sensing operation of the programmed floating gate transistors with a control signal adapted to make the corresponding memory cells become conductive at an instant determined by a respective programmed threshold voltage;performing the convolutional computation by using the input values during an elapsed time for each memory cell to become conductive; andoutputting output values resulting from the convolutional computation.2. The method according to claim 1 , wherein performing the convolutional computation comprises:performing a multiply and accumulate sequence on all input values for each output value, andobtaining product values of the multiplication operations of one input value by a respective weight factor from the elapsed time for the respective memory cell to become conductive in response to the control signal, andwherein all the product values are provided in parallel and accumulated together during the sensing operation.3. The method according to any of claim 1 , wherein the control signal is a voltage ramp control signal applied on control gates ...

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Номер записи: 64
25-01-2018 дата публикации

SYSTEMS AND METHODS FOR PROGRAMMING DATA TO STORAGE DEVICES

Номер: US20180025782A1
Автор: Bandic Zvonimir, Qin Minghai, Song Seung-Hwan, Sun Chao
Принадлежит:

Receiving one or more first write commands to write a first set of data to a storage device. The first set of data is programmed in a plurality of memory cells in the storage device using a first plurality of program levels available in the plurality of memory cells. One or more second write commands to write a second set of data to the storage device is received. The second set of data is programmed in the plurality of memory cells with which the first set of data is programmed. The second set of data is programmed using a second plurality of program levels available in the plurality of memory cells different from the first plurality of program levels. Each program level of the first and second pluralities of program levels is mapped to a respective bit pattern comprising three bits. 1. A method comprising:receiving one or more first write commands to write a first set of data to a storage device;programming the first set of data in a plurality of memory cells in the storage device using a first plurality of program levels available in the plurality of memory cells, wherein each of the plurality of memory cells is programmed with two bits of data from the first set of data;receiving one or more second write commands to write a second set of data to the storage device; andprogramming the second set of data in the plurality of memory cells programmed with the first set of data, wherein the second set of data is programmed using a second plurality of program levels available in the plurality of memory cells, each of the second plurality of program levels is different from each of the first plurality of program levels, and each of the plurality of memory cells is programmed with two bits of data from the second set of data,wherein each program level of the first and second pluralities of program levels is mapped to a respective bit pattern comprising three bits,wherein first and second bit pairs of the bit patterns mapped to the first plurality of program levels are ...

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Номер записи: 65
10-02-2022 дата публикации

Integrated Assemblies and Methods of Forming Integrated Assemblies

Номер: US20220045075A1
Автор: Chary Indra V., Chen Jiewei, Fang Jun, Greenlee Jordan D., Hopkins John D., Klein Rita J., Li Xiao, Lomeli Nancy M., Luo Kaiming, Samara Vladimir, Shamanna Vinayak
Принадлежит: MICRON TECHNOLOGY, INC.

Some embodiments include an integrated assembly having a source structure, and having a stack of alternating conductive levels and insulative levels over the source structure. Cell-material-pillars pass through the stack. The cell-material-pillars are arranged within a configuration which includes a first memory-block-region and a second memory-block-region. The cell-material-pillars include channel material which is electrically coupled with the source structure. Memory cells are along the conductive levels and include regions of the cell-material-pillars. A panel is between the first and second memory-block-regions. The panel has a first material configured as a container shape. The container shape defines opposing sides and a bottom of a cavity. The panel has a second material within the cavity. The second material is compositionally different from the first material. Some embodiments include methods of forming integrated assemblies. 1. An integrated assembly , comprising:a source structure;a stack of alternating conductive levels and insulative levels over the source structure;cell-material-pillars passing through the stack; the cell-material-pillars being arranged within a configuration which includes a first memory-block-region and a second memory-block-region; the cell-material-pillars including channel material; the channel material being electrically coupled with the source structure;memory cells along the conductive levels and comprising regions of the cell-material-pillars; anda panel between the first and second memory-block-regions; the panel having a first material configured as a container shape; the container shape, along a cross-section, defining opposing sides and a bottom of an interior cavity; the panel having a second material within the interior cavity, with the second material being compositionally different from the first material.2. The integrated assembly of wherein the first material comprises conductive material.3. The integrated assembly ...

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Номер записи: 66
24-01-2019 дата публикации

Random telegraph signal noise reduction scheme for semiconductor memories

Номер: US20190027222A1
Автор: Toru Tanzawa
Принадлежит: Micron Technology Inc

Embodiments are provided that include a memory device having a memory array including a plurality of access lines and data lines. The memory device further includes a circuit coupled to the plurality of access lines and configured to provide consecutive pulses to a selected one of the plurality of access lines. Each pulse of the consecutive pulses includes a first voltage and a second voltage. The first voltage is greater in magnitude than the second voltage, and the first voltage is applied for a shorter duration than the second voltage.

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Номер записи: 67
23-01-2020 дата публикации

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

Номер: US20200027889A1
Автор: LIU Chen-Chin, Lu Yi Hsien, Wang Yu-Hsiung, Wu Wei Cheng, YANG Juo-Li
Принадлежит:

In a method of manufacturing a semiconductor device, a memory cell structure covered by a protective layer is formed in a memory cell area of a substrate. A mask pattern is formed. The mask pattern has an opening over a first circuit area, while the memory cell area and a second circuit area are covered by the mask pattern. The substrate in the first circuit area is recessed, while the memory cell area and the second circuit area are protected. A first field effect transistor (FET) having a first gate dielectric layer is formed in the first circuit area over the recessed substrate and a second FET having a second gate dielectric layer is formed in the second circuit area over the substrate as viewed in cross section. 1. A semiconductor device including:a non-volatile memory cell formed in a memory cell area of a substrate;a first circuit formed in a first circuit area of the substrate; anda second circuit formed in a second circuit area of the substrate,wherein a first device forming surface of the substrate in the first circuit area is located at a lower level than a second device forming surface of the substrate in the second circuit area as viewed in cross section.2. The semiconductor device of claim 1 , wherein:the first circuit includes a first field effect transistor (FET) having a first gate dielectric layer,the second circuit includes a second FET having a second gate dielectric layer, anda thickness of the first gate dielectric layer is greater than a thickness of the second gate dielectric layer.3. The semiconductor device of claim 1 , wherein an operational voltage of the first circuit is higher than an operational voltage of the second circuit.4. The semiconductor device of claim 1 , wherein a memory cell forming surface of the substrate in the memory cell area is located at a lower level than the first device forming surface of the substrate in the first circuit area as viewed in cross section.5. The semiconductor device of claim 1 , further comprising ...

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Номер записи: 68
31-01-2019 дата публикации

MEMORY DEVICE AND OPERATING METHOD THEREOF

Номер: US20190035468A1
Автор: IN Eun Kyu, KIM Byung Ryul, Park Jae Woo, PARK Seok Won
Принадлежит:

A memory device prevents generation of an abnormal column address. The memory device includes: a memory cell array; and a column address controller configured to generate a column address of the memory cell array in response to a column address control signal, wherein the column address controller enables the column address control signal when an address signal is input, and wherein the address signal includes a column address signal corresponding to the column address. 1. A memory device comprising:a memory cell array; anda column address controller configured to generate a column address of the memory cell array in response to a column address control signal,wherein the column address controller enables the column address control signal when an address signal is input, andwherein the address signal includes a column address signal corresponding to the column address.2. The memory device of claim 1 , wherein the address signal is input during five cycles of a reference clock of the memory device.3. The memory device of claim 2 , wherein the column address signal includes a first column address signal input during a first cycle among the five cycles and a second column address signal input during a second cycle among the five cycles.4. The memory device of claim 3 , wherein the column address controller includes:an address control signal generator configured to generate an address control signal indicating one among the five cycles corresponding to a currently input address signal of the address signal;a column address control signal generator configured to generate the column address control signal; anda column address generator configured to generate the column address by using the first column address signal and the second column address signal,wherein the column address control signal generator enables the column address control signal during the second cycle, andwherein the column address generator generates the column address when the column address control ...

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Номер записи: 69
30-01-2020 дата публикации

Semiconductor Memory Having Both Volatile and Non-Volatile Functionality and Method of Operating

Номер: US20200035301A1
Автор: Widjaja Yuniarto
Принадлежит:

Semiconductor memory having both volatile and non-volatile modes and methods of operation. A semiconductor storage device includes a plurality of memory cells each having a floating body for storing, reading and writing data as volatile memory. The device includes a floating gate or trapping layer for storing data as non-volatile memory, the device operating as volatile memory when power is applied to the device, and the device storing data from the volatile memory as non-volatile memory when power to the device is interrupted.

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Номер записи: 70
30-01-2020 дата публикации

NON-VOLATILE MEMORY WITH DOUBLE CAPA IMPLANT

Номер: US20200035304A1
Автор: SIMOLA Roberto, Tailliet François
Принадлежит: STMICROELECTRONICS (ROUSSET) SAS

An EEPROM includes a floating gate transistor having a source region, a channel region and a drain region. A first capa implant zone on a drain-side of the floating gate transistor has a first dopant concentration level. A second capa implant zone in the first capa implant zone adjacent the drain region has a second dopant concentration level that is greater than the first dopant concentration level. A gate oxide region insulates the floating gate electrode from the channel region, first capa implant zone and second capa implant zone. A thickness of the gate oxide region is thinner at the second capa implant zone than at the channel region and first capa implant zone. 1. An electrically erasable and programmable nonvolatile memory including a memory cell , wherein the memory cell comprises a floating gate transistor comprising:a source region disposed in a semiconductor layer;a drain region disposed in the semiconductor layer;a first capa implant zone disposed in the semiconductor layer adjacent the drain region;a channel region disposed in the semiconductor layer between the source region and the first capa implant zone;a second capa implant zone disposed in the first capa implant zone adjacent the drain region;wherein a dopant concentration level of the second capa implant zone is greater than a dopant concentration level of the first capa implant zone;a control gate electrode;a floating gate electrode, wherein the floating gate electrode is insulated from the control gate electrode; anda gate oxide region insulating the floating gate electrode from the channel region, the first capa implant zone and the second capa implant zone, wherein the gate oxide region has a first thickness over the channel region and a second thickness, less than the first thickness, over the second capa implant zone.2. The electrically erasable and programmable nonvolatile memory of claim 1 , wherein an edge of the first capa implant zone is laterally offset claim 1 , in a direction ...

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Номер записи: 71
12-02-2015 дата публикации

SEMICONDUCTOR MEMORY DEVICE

Номер: US20150043279A1
Автор: Yamauchi Yoshimitsu
Принадлежит:

Provided is a semiconductor memory device including an oxide semiconductor insulated gate FET and having a capability to implement advanced performance without being affected by a variation in threshold voltage. A memory cell MC includes a memory node Nm formed at a connection point of a gate of a first transistor element T, a source of a second transistor element T, and one end of a capacitive element Cm, and a control node Nc formed at a connection point of a drain of the first transistor element T and a drain of the second transistor element T. Each memory cell MC arranged in the same column includes the control node Nc connected to a shared first control line CL extending in a column direction, the first transistor element T having a source connected to a shared data signal line DL extending in the column direction, the second transistor element T having a gate connected to an individual first selection line WL, and the capacitive element Cm having the other end connected to an individual second selection line GL, and a switching element SE having one end connected to the first control line CL, and the other end connected to a voltage supply line VL is provided with respect to each first control line CL. 1. A semiconductor memory device comprising a memory cell array in which a plurality of memory cells each having a first transistor element composed of an insulated gate FET , a second transistor element composed of an oxide semiconductor insulated gate FET , and a capacitive element are arranged at least in a column direction , whereineach of the memory cells includes a memory node formed at a connection point of a gate electrode of the first transistor element, a source electrode of the second transistor element, and one end of the capacitive element, and a control node formed at a connection point of a drain electrode of the first transistor element and a drain electrode of the second transistor element,each of the memory cells arranged in respective rows ...

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Номер записи: 72
09-02-2017 дата публикации

MULTIPLE-TIME PROGRAMMABLE MEMORY

Номер: US20170040063A1
Автор: Chen Chung-Chieh, CHEN Hsu-Shun, CHIH Yu-Der, KUO Cheng-Hsiung, LI Gu-Huan
Принадлежит:

A multiple-time programmable (MTP) structure is provided that can operate using a power supply with a supply voltage of 1.5 V to 5.5 V. When the supply voltage is above a first voltage, a first circuit is configured to induce a second constant voltage at a drain of a second transistor, and to induce the second constant voltage on a terminal in a third circuit. In some embodiments, the third circuit provides a third constant voltage on a gate of a third transistor. When the supply voltage is below the first voltage, a fifth circuit is configured to induce a fourth constant voltage on a terminal in the third circuit. The fourth constant voltage is substantially equal to the second constant voltage. 1. A method , comprising: activating a first transistor having a first source/drain region coupled to a digital-output node;', 'wherein the digital-output node is pulled to a first voltage while the first transistor and the floating gate transistor are activated; and', 'activating a floating gate transistor having a gate coupled to a word line, a first source/drain region coupled to a voltage source, and a second source/drain region coupled to the digital-output node,'}, wherein the digital-output node is pulled to a second voltage while the first transistor is deactivated and the floating gate transistor is activated when the floating gate transistor is in a first logic state, and', 'wherein the digital-output node is pulled to a third voltage while the first transistor is deactivated and the floating gate transistor is activated when the floating gate transistor is in a second logic state., 'deactivating the first transistor while the floating gate transistor remains activated,'}], 'during a read operation2. The method of claim 1 , wherein the second voltage is less than the third voltage.3. The method of claim 1 , wherein the second voltage is less than the first voltage.4. The method of claim 1 , wherein the third voltage is greater than the first voltage.5. The method ...

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Номер записи: 73
09-02-2017 дата публикации

SEMICONDUCTOR STORAGE DEVICE AND DATA READ METHOD

Номер: US20170040064A1
Автор: TORII Satoshi
Принадлежит:

A semiconductor storage device including plural bit lines, plural select gate lines that intersect with the plural bit lines, and plural memory cells that each include a p-channel memory transistor. The semiconductor storage device includes plural p-channel charging transistors that are respectively connected to the plural bit lines, and a charging line that is connected to each of the plurality of charging transistors. A controller that ON/OFF controls the charging transistors places each of the charging transistors in an ON state prior to read current flowing in a read target bit line, and that places the charging transistor connected to the read target bit line in an OFF state when read current flows in the read target bit line. 1. A semiconductor storage device , comprising:a plurality of bit lines;a plurality of select gate lines that intersect with the plurality of bit lines;a plurality of memory cells that each include a p-channel memory transistor, with the plurality of memory cells each disposed so as to correspond to respective portions of intersection between the plurality of bit lines and the plurality of select gate lines;a source line that is connected to each of the memory transistors, and that is applied with a first specific potential when reading data stored in the memory cells;a plurality of p-channel charging transistors that are respectively connected to the plurality of bit lines;a charging line that is connected to each of the plurality of charging transistors, and that is applied with a second specific potential when reading data stored in the memory anda controller that places each of the charging transistors in an ON state prior to current, corresponding to data stored in a read target memory cell of the plurality of memory cells on which data reading is to be performed, flowing in a read target bit line that is one of the plurality of bit lines and that corresponds to the read target memory cell, the controller placing a charging ...

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Номер записи: 74
12-02-2015 дата публикации

SOLID STATE DRIVE ARCHITECTURES

Номер: US20150046625A1
Автор: McKenzie Robert Neil, Peddle Charles I., Snelgrove Martin, Snelgrove Xavier
Принадлежит: THSTYME BERMUDA LIMITED

A solid state drive includes DRAM logical flash and flash memory, in which system processor reads and writes only to the DRAM logical flash which minimizes writes to the flash memory. A method for operation of a solid state flash device includes writing, by a CPU, to a solid state drive by sending commands and data to DRAM logical flash using flash commands and formatting. 1. A solid state drive comprising:DRAM logical flash; andflash memory;in which a system bus reads and writes to the DRAM logical flash but not the flash memory.2. The drive of claim 1 , in which not all flash writes to the drive are written through to the flash memory.3. The drive of claim 1 , in which the solid state drive writes data from the DRAM logical flash to the flash memory at predetermined points that are independent from commands issued by the system processor.4. The drive of claim 1 , in which the DRAM logical flash simulates flash memory by storing files in the same way as NAND flash and responds to flash commands.5. The drive of claim 4 , in which the DRAM logical flash simulates flash memory by using a FAT table claim 4 , updating logical records claim 4 , combining files claim 4 , and directly connecting to a SATA bus.6. The drive of claim 1 , further comprising an energy storage device storing enough power to move the data content stored in the DRAM logical flash to flash memory if external power to the solid state drive is interrupted.7. The drive of claim 1 , in which the DRAM logical flash implements all flash commands full interface speed.8. The drive of claim 1 , in which the DRAM logical flash stores program trace points and operation snapshots and minimizes writes to the flash memory.9. The drive of claim 1 , in which the solid state drive is configured to provide a full recovery of a last state of an attached computing device for any power down.10. The drive of claim 1 , in which pages of the NAND flash are individually identified as having errors and eliminated from a ...

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Номер записи: 75
06-02-2020 дата публикации

SOLID STATE STORAGE DEVICE AND READ RETRY METHOD THEREOF

Номер: US20200042237A1
Автор: FU Jen-Chien, LU Tsu-Han, YEN Hsiao-Chang, ZENG Shih-Jia
Принадлежит:

A solid state storage device includes a control circuit and a non-volatile memory. The control circuit includes a retry table. In addition, plural retry read-voltage sets are recorded in the retry table, and the retry table is divided into plural retry sub-tables. The plural retry read-voltage sets are classified into plural groups. The plural retry read-voltage sets are recorded into the corresponding retry sub-tables. The non-volatile memory is connected with the control circuit. During a read retry process of a read cycle, the control circuit performs a hard decoding process according to a retry sub-table of the plural retry sub-tables. If the hard decoding process fails, the control circuit performs a soft decoding process according to another retry sub-table of the plural retry sub-tables. 1. A solid state storage device , comprising:a control circuit comprising a retry table, wherein plural retry read-voltage sets are recorded in the retry table, and the retry table is divided into plural retry sub-tables, wherein the plural retry read-voltage sets are classified into plural groups, and the plural retry read-voltage sets are recorded into the corresponding retry sub-tables; anda non-volatile memory connected with the control circuit,wherein during a read retry process of a read cycle, the control circuit performs a hard decoding process according to a retry sub-table of the plural retry sub-tables, wherein if the hard decoding process fails, the control circuit performs a soft decoding process according to another retry sub-table of the plural retry sub-tables.2. The solid state storage device as claimed in claim 1 , wherein the plural retry read-voltage sets are classified into a first group and a second group according to the hard decoding process and the soft decoding process claim 1 , wherein the retry read-voltage sets of the first group and the retry read-voltage sets of the second group are respectively recorded into a first retry sub-table and a second ...

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Номер записи: 76
07-02-2019 дата публикации

METHOD AND SYSTEM FOR COMPENSATING FOR FLOATING GATE-TO-FLOATING GATE (FG-FG) INTERFERENCE IN FLASH MEMORY CELL READ OPERATIONS

Номер: US20190043565A1
Автор: Goda Akira, Miccoli Carmine
Принадлежит: Intel Corporation

Embodiments of the present disclosure provide methods, devices, modules, and systems for compensating for floating gate to floating gate (fg-fg) interference in flash memory cell read operations. Compensating for fg-fg interference effects can reduce or prevent read errors. Embodiments of the present disclosure can compensate for fg-fg interference by determining the programmed state of aggressor (or influencing) memory cells that are programmed after a target memory cell. If the aggressor memory cell is in the erased state of Level 0 or is in a programmed state of Level 2-15, the target memory cell is identified as undisturbed. If the aggressor memory cell is programmed to a Level 1 (instead of Level 0 or Levels 2-15), the target memory cell is identified as disturbed. If the target memory cell is disturbed, sensing parameters may be adjusted to compensate for the disruption. 1. A memory controller , comprising: receive a request to read data stored in a first memory cell of a multi-level non-volatile memory array, wherein the data includes at least 4 bits, wherein the first memory cell is in a first wordline;', 'perform a read operation on a second memory cell of the flash memory array to determine if the second memory cell is programmed to a first programming level that is between an erased programming level and at least 14 other programming levels, the second memory cell being adjacent to the first memory cell on a memory cell string, wherein the second memory cell is operated with a second wordline that is adjacent to the first wordline, in response to the request; and', 'read the data stored in the first memory cell, in response to the request, with a compensated sensing parameter if the first memory cell is in a disturbed condition; and, 'memory controller logic toerror-correcting code logic to determine that the first memory cell is in the disturbed condition when the second memory cell is programmed to the first programming level.2. The memory controller of ...

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Номер записи: 77
07-02-2019 дата публикации

FLASH MEMORY COMPONENTS AND METHODS

Номер: US20190043875A1
Автор: Fastow Richard, Parat Krishna
Принадлежит:

Flash memory technology is disclosed. In one example, a flash memory component can include a plurality of conductive layers vertically spaced apart from one another and separated by voids, each of the plurality of conductive layers forming a word line. The memory component can also include a vertically oriented conductive channel extending through the plurality of conductive layers. In addition, the flash memory component can include a plurality of memory cells coupling the plurality of conductive layers to the conductive channel. Each word line can be associated with one of the plurality of memory cells. Associated devices, systems, and methods are also disclosed. 1. A flash memory component , comprising:a plurality of conductive layers vertically spaced apart from one another and separated by voids, each of the plurality of conductive layers forming a word line;a vertically oriented conductive channel extending through the plurality of conductive layers; anda plurality of memory cells coupling the plurality of conductive layers to the conductive channel, wherein each word line is associated with one of the plurality of memory cells.2. The flash memory component of claim 1 , wherein the voids are filled with a gas.3. The flash memory component of claim 2 , wherein the gas comprises air claim 2 , argon claim 2 , nitrogen claim 2 , or a combination thereof.4. The flash memory component of claim 1 , wherein the conductive layers are vertically spaced apart from one another by a distance of from about 5 nm to about 50 nm.5. The flash memory component of claim 1 , wherein each of the conductive layers has a thickness of from about 10 nm to about 40 nm.6. The flash memory component of claim 1 , wherein the plurality of conductive layers comprises polysilicon.7. The flash memory component of claim 6 , wherein at least one of the plurality of conductive layers has a SiGe residue on a top surface claim 6 , a bottom surface claim 6 , or both.8. The flash memory component of ...

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Номер записи: 78
07-02-2019 дата публикации

SELECTIVE DEPOSITION OF SiN ON HORIZONTAL SURFACES

Номер: US20190043876A1
Автор: GUPTA Awnish, Park Jason Daejin, van Cleemput Patrick A., van Schravendijk Bart J.
Принадлежит:

Methods and apparatuses for selectively depositing silicon nitride (SiN) via high-density plasma chemical vapor deposition (HDP CVD) to form a SiN pad on an exposed flat surface of a nitride layer in a 3D NAND staircase structure with alternating oxide and nitride layers are provided. In some embodiments, selective etching is performed to remove undesirable buildup of SiN on sidewalls of the oxide layers of the staircase structure. Nitride layers of the staircase structure are replaced with tungsten (W) to form tungsten wordlines, while the SiN pads are replaced with tungsten to from landing pads, which prevent punchthrough of the tungsten wordlines on the staircase structure by interconnects extending thereto. 1. A method of processing a semiconductor substrate for fabricating a 3D NAND structure , the method comprising:providing a substrate having alternating oxide layers and nitride layers arranged in a staircase pattern, wherein the each of the nitride layers has an exposed horizontal surface; andprior to depositing an oxide filler over the staircase pattern, depositing silicon nitride (SiN) via high-density plasma chemical vapor deposition (HDP CVD) over both the oxide layers and nitride layers, wherein the SiN is deposited selectively relative to oxide sidewall surfaces on the exposed horizontal surfaces of the nitride layers at each layer to form SiN pads.2. The method of claim 1 , wherein the deposition of SiN via HDP CVD comprises:simultaneously depositing SiN on the exposed horizontal surfaces of the nitride layers to form the SiN pads and selectively etching SiN deposited on sidewalls of the oxide layers of the staircase pattern relative to the SiN pads.3. The method of claim 1 , further comprising:exposing the exposed horizontal surfaces of the nitride layers at each layer to deposition chemistry to form the SiN pads; andexposing sidewalls of the oxide layers of the staircase pattern to an etchant to selectively etch SiN deposited thereon relative to the ...

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Номер записи: 79
19-02-2015 дата публикации

NON-VOLATILE MEMORY DEVICE AND OPERATION AND FABRICATING METHODS THEREOF

Номер: US20150049557A1
Автор: Watanabe Hiroshi
Принадлежит: PHISON ELECTRONICS CORP.

Provided is a non-volatile memory device having a zigzag body wiring. First word lines and second word lines are disposed on a substrate, arranged periodically and extended along a first direction. First inter-poly dielectric films are disposed on the substrate and respectively beneath the first word lines. Second inter-poly dielectric films are disposed on the substrate and respectively beneath the second word lines, wherein the first inter-poly dielectric films are thinner than the second inter-poly dielectric films. A floating gate is disposed between the substrate and each of the first and second inter-poly dielectric films. A tunnel oxide film is disposed between the substrate and each of the floating gates. Bit lines are disposed above the first and second word lines and extended along a second direction different from the first direction. 1. A non-volatile memory device , comprising:a well, disposed in a substrate;a plurality of first word lines and a plurality of second word lines, disposed on the substrate, arranged periodically and extending in a first direction;a plurality of inter-poly dielectric films, disposed on the substrate and respectively beneath the plurality of first word lines and the plurality of second word lines;a plurality of floating gates, disposed between the well and the plurality of inter-poly dielectric films; anda plurality of tunnel oxide films, disposed between the well and the plurality of floating gates,wherein a first distance from the first word lines to the substrate is smaller than a second distance from the second word lines to the substrate.2. The non-volatile memory device of claim 1 , wherein a third distance from a top of the first word lines to the substrate is smaller than or equal to a fourth distance from a bottom of the second word lines to the substrate.3. The non-volatile memory device of claim 1 , wherein the plurality of inter-poly dielectric films comprise:a plurality of first inter-poly dielectric films, ...

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Номер записи: 80
06-02-2020 дата публикации

MANAGED NAND PERFORMANCE THROTTLING

Номер: US20200043559A1
Автор: Blodgett Greg A., Jean Sebastien Andre
Принадлежит:

Apparatus and methods are disclosed, including a memory device or a memory controller configured to determine that a condition has occurred that indicates a performance throttling operation, implement a performance throttling responsive to the determined condition, responsive to implementing the performance throttling, set a performance throttling status indicator in an exception event status attribute, receive a command from a host device across a memory device interface, perform the command, prepare a response to the command, the response including a flag indicating that the performance throttling status indicator is set in the exception event status attribute, and send the response to the host device. Methods of operation are disclosed, as well as machine-readable medium and other embodiments. 1. (canceled)2. A method implemented on a host , the method comprising:sending by an initiator executing on the host, over a host interface to a memory device, an access request for a protected memory region of a non-volatile memory array, the access request including an identifier of the initiator, the protected memory region requiring a secret value derived from a key and a write counter to access the protected memory region;receiving a result from the memory device through the host interface; anddetermining that the result includes a second identifier different from the identifier of the initiator; andresponsive to determining that the result includes the second identifier, determining that the result is not responsive to the access request and sending a second access request for the protected memory region.3. The method of claim 2 , wherein the result includes a write counter status and an operation status.4. The method of claim 3 , wherein the write counter status is located in a first region of the result claim 3 , the operation status is located in a second region of the result claim 3 , and the identifier of the initiator is located in a third region of the result.5 ...

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Номер записи: 81
18-02-2021 дата публикации

Semiconductor Memory Having Both Volatile and Non-Volatile Functionality and Method of Operating

Номер: US20210050059A1
Автор: Widjaja Yuniarto
Принадлежит:

Semiconductor memory having both volatile and non-volatile modes and methods of operation. A semiconductor storage device includes a plurality of memory cells each having a floating body for storing, reading and writing data as volatile memory. The device includes a floating gate or trapping layer for storing data as non-volatile memory, the device operating as volatile memory when power is applied to the device, and the device storing data from the volatile memory as non-volatile memory when power to the device is interrupted. 122-. (canceled)23. A semiconductor memory device comprising a string of memory cells connected in series , each said memory cell having:a floating body region configured to be charged to a level indicative of a state of said memory cell to store the state as volatile memory;a first region in electrical contact with said floating body region;a second region in electrical contact with said floating body region and spaced apart from said first region;a floating gate or trapping layer positioned between said first and second regions and configured to receive transfer of data stored as said volatile memory and store said data as non-volatile memory indicative of said state of the memory cell; anda control gate positioned above said floating gate or trapping layer;wherein said charge stored in said floating body region determines a charge stored in said floating gate or trapping layer upon interruption of power to said semiconductor memory device; andwherein said transfer of data to said floating gate or trapping layer occurs to at least two of said memory cells.24. The semiconductor memory device of claim 23 , wherein said floating body region has a first conductivity type selected from a p-type conductivity type and an n-type conductivity type;said first region has a second conductivity type selected from said p-type and n-type conductivity types, said second conductivity type being different from said first conductivity type; andsaid second ...

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Номер записи: 82
18-02-2016 дата публикации

SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME

Номер: US20160049413A1
Автор: Chen Chih-Jung, CHEN Tzu-Ping
Принадлежит:

A semiconductor device is disclosed. The semiconductor device includes: a substrate; a floating gate on the substrate; a first silicon oxide layer between the floating gate and the substrate; a first tunnel oxide layer and a second tunnel oxide layer adjacent to two sides of the first silicon oxide layer; and a control gate on the floating gate. Preferably, the thickness of the first tunnel oxide layer and the second tunnel oxide layer is less than the thickness of the first silicon oxide layer. 1. A semiconductor device , comprising:a substrate;a floating gate on the substrate;a first silicon oxide layer between the floating gate and the substrate, wherein art of the bottom surface of the floating gate is lower than the to surface of the first silicon oxide layer;a first tunnel oxide layer and a second tunnel oxide layer adjacent to two sides of the first silicon oxide layer, wherein the thickness of the first tunnel oxide layer and the second tunnel oxide layer is less than the thickness of the first silicon oxide layer; anda control gate on the floating gate.2. The semiconductor device of claim 1 , further comprising an oxide-nitride-oxide (ONO) stack between the floating gate and the control gate.3. The semiconductor device of claim 1 , further comprising a plurality of second silicon oxide layers adjacent to the first tunnel oxide layer and the second tunnel oxide layer.4. The semiconductor device of claim 1 , wherein the thickness of the second silicon oxide layers is greater than the thickness of the first tunnel oxide layer and the second tunnel oxide layer.5. A method for operating memory cell claim 1 , wherein the memory cell comprises a floating gate on a substrate claim 1 , a patterned oxide-nitride-oxide (ONO) stack on the floating gate claim 1 , a control gate on the ONO stack claim 1 , a first tunnel oxide layer and a second tunnel oxide layer between the floating gate and the substrate claim 1 , a select gate adjacent to the first tunnel oxide layer ...

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Номер записи: 83
18-02-2016 дата публикации

DUAL CHANNEL MEMORY

Номер: US20160049507A1
Автор: Luo Zhijiong
Принадлежит:

Technologies are generally described related to a dual channel memory device, system and method of manufacture. Various described devices include utilization of both a front channel and a back channel through a substrate formed underneath a dual gate structure of a semiconductor device. Using two pairs of contacts on opposing sides of the gate structure, where the contact pairs are formed on differently doped layers of the semiconductor device, multiple bits may be stored in the semiconductor device acting as a single memory cell. Memorization may be realized by storing different amount or types of charges on the floating gate, where the charges may impact a conduction status of the channels of the device. By detecting the conduction status of the channels, such as open circuit, close circuit, or high resistance, low resistance, data stored on the device (“0” or “1”) may be detected. 1. A semiconductor device comprising:a first substrate;an insulator layer positioned over the first substrate;a second substrate positioned over the insulator layer; a tunnel oxide layer positioned over a first portion of the second substrate;', 'a floating gate layer positioned over the tunnel oxide layer;', 'a control oxide layer positioned over the floating gate layer;', 'a control gate layer positioned over the control oxide layer, and, 'a gate structure comprisinga third substrate positioned over a second portion of the second substrate, wherein the second portion of the second substrate includes dopants of a first type and the third substrate includes dopants of a second type.2. The semiconductor device of claim 1 , further comprising:a first pair of contacts configured to contact the third substrate on opposite sides of the gate structure; anda second pair of contacts configured to contact the second portion of the second substrate on opposite sides of the gate structure.3. The semiconductor device of claim 2 , wherein the third substrate is positioned around the first portion of ...

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Номер записи: 84
16-02-2017 дата публикации

Method for Reading Data Stored in a Flash Memory According to a Threshold Voltage Distribution and Memory Controller and System Thereof

Номер: US20170047122A1
Автор: Yang Tsung-Chieh
Принадлежит:

A method for reading data stored in a flash memory is disclosed. The flash memory comprises a plurality of memory cells and each memory cell has a particular threshold voltage The method includes: obtaining a first threshold voltage distribution representing threshold voltages of a first group of the memory cells; obtaining a second threshold voltage distribution representing threshold voltages of a second group of the memory cells, wherein the second threshold voltage distribution is different from the first threshold voltage distribution, and the first group of the memory cells comprises at least a part of the second group of the memory cells; and controlling the flash memory to perform at least one read operation upon the first group of the memory cells according to the second threshold voltage distribution. 1. A method for reading data stored in a flash memory , wherein the flash memory comprises a first set of memory cells and a second set of memory cells , and each memory cell corresponds to a particular threshold voltage , the method comprising:measuring a first voltage characteristic of the first set of the memory cells;measuring a second voltage characteristic of the second set of the memory cells; andreading the first set of the flash memory by using the second voltage characteristic.2. The method as claimed in claim 1 , wherein the first voltage characteristic is different from the second voltage characteristic claim 1 , and the first set of memory cells comprises at least a part of the memory cells of the second set.3. A memory controller for reading data stored in a flash memory claim 1 , wherein the flash memory comprises a first set of memory cells and a second set of memory cells claim 1 , and each memory cell corresponds to a particular threshold voltage claim 1 , the memory controller comprising:a control logic, measuring a first voltage characteristic of the first set of the memory cells, measuring a second voltage characteristic of the second set ...

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Номер записи: 85
25-02-2021 дата публикации

SUPPORTING RESPONSES FOR MEMORY TYPES WITH NON-UNIFORM LATENCIES ON SAME CHANNEL

Номер: US20210056027A1
Автор: Balakrishnan Kedarnath, Magro James Raymond
Принадлежит:

Systems, apparatuses, and methods for identifying response data arriving out-of-order from two different memory types are disclosed. A computing system includes one or more clients for processing applications. A memory channel transfers memory traffic between a memory controller and a memory bus connected to each of a first memory and a second memory different from the first memory. The memory controller determines a given point in time when read data is to be scheduled to arrive on the memory bus from memory. The memory controller associates a unique identifier with the given point in time. The memory controller identifies a given command associated with the arriving read data based on the given point in time. 120-. (canceled)21. A memory controller comprising:a memory channel configured to communicate with a first memory device and a second memory device via a shared data bus; and identify one or more commands that are pending for issuance to at least one of the first memory device and the second memory device; and', 'send a command of the one or more commands via the memory channel responsive to a determination that sending the command will not cause a collision on the shared data bus., 'a control unit configured to22. The memory controller as recited in claim 21 , wherein to determine whether sending the command will cause a collision on the shared data bus claim 21 , the control unit is configured to determine when a previous command was sent to at least one of the first memory device and the second memory device.23. The memory controller as recited in claim 22 , wherein an access latency of the first memory device is deterministic claim 22 , and an access latency of the second memory device is not deterministic.24. The memory controller as recited in claim 23 , wherein an access latency corresponds to a latency of receiving valid read data in response to a read command.25. The memory controller as recited in claim 24 , wherein a latency of a response to a ...

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Номер записи: 86
25-02-2016 дата публикации

Integrated Circuit Comprising an Input Transistor Including a Charge Storage Structure

Номер: US20160055909A1
Автор: Barrenscheen Jens, Mauder Anton
Принадлежит:

An electronic circuit comprises an input insulated gate field effect transistor. The input insulated gate field effect transistor comprises first and second load terminals and a control terminal. The control terminal is electrically coupled to an input signal terminal of the electronic circuit. The electronic circuit further comprises a control circuit. An input terminal of the control circuit is electrically coupled to the second load terminal. The control terminal is electrically connected to a control structure comprising a control electrode and charge storage structure. 1. An electronic circuit , comprising:an input insulated gate field effect transistor comprising first and second load terminals and a control terminal, the control terminal being electrically coupled to an input signal terminal of the electronic circuit;a control circuit, wherein an input terminal of the control circuit is electrically coupled to the second load terminal; and whereinthe control terminal is electrically connected to a control structure comprising a control electrode and charge storage structure.2. The electronic circuit of claim 1 , wherein the electronic circuit is configured to perform active current-free voltage detection by applying an input voltage signal to the control terminal of the insulated gate field effect transistor.3. The electronic circuit of claim 1 , wherein the input insulated gate field effect transistor is a normally off n-type channel insulated gate field effect transistor.4. The electronic circuit of claim 1 , wherein a threshold voltage of the input insulated gate field effect transistor is at least 10 times greater than a threshold voltage of an insulated gate field effect transistor of the control circuit.5. The electronic circuit of claim 1 , wherein the input insulated gate field effect transistor and the control circuit are monolithically integrated.6. The electronic circuit of claim 1 , wherein a threshold voltage Vth of the input insulated gate field ...

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Номер записи: 87
14-02-2019 дата публикации

DETERMINING READ VOLTAGES FOR A STORAGE DEVICE

Номер: US20190051360A1
Автор: Goss Ryan James, Lien Nicholas Odin
Принадлежит:

Systems and methods presented herein provide for computing read voltages for a storage device. In one embodiment, a controller is controller is operable to soft read data from a portion of the storage device, and to iteratively test the soft read data a predetermined number of times. For example, the controller may test the soft read data a number of times by applying a different probability weight to the soft read data each time the soft read data is tested. The controller may then decode the soft read data based on the probability weight, and determine an error metric of the decoded soft read data. Then, the controller determines a read voltage for the portion of the storage device based on the probability weight and the error metric. 1. A storage system , comprising:a storage device; anda controller operable to soft read data from a portion of the storage device, to decode the soft read data a plurality of times using a plurality of probability weights, to compare each decoded soft read data to hard read data from the portion of the storage device, to generate a plurality of error metrics based on the comparisons, and to determine a read voltage based on the error metrics.2. The storage system of claim 1 , wherein:the controller is further operable to decode the soft read data using a low density parity check (LDPC).3. The storage system of claim 1 , wherein:the storage device is a NAND flash memory device, a magnetoresistive random-access memory device, or a combination thereof.4. The storage system of claim 1 , wherein:the controller is further operable to statistically track the read voltage to determine a longevity of the portion of the storage device.5. The storage system of claim 4 , wherein:the controller is further operable to retire the portion of the storage device when the portion of the storage device has passed its longevity.6. The storage system of claim 1 , wherein:the probability weight is a log likelihood ratio (LLR) weight.7. The storage system ...

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Номер записи: 88
22-02-2018 дата публикации

NONVOLATILE MEMORY DEVICE, STORAGE DEVICE INCLUDING NONVOLATILE MEMORY DEVICE AND READING METHOD OF NONVOLATILE MEMORY DEVICE

Номер: US20180053554A1
Автор: BYEON Daeseok, NAM Sang-Wan, YOON Chiweon
Принадлежит:

A nonvolatile memory device includes a memory cell array and a row decoder circuit. The row decoder circuit turns on memory cells of a plurality of cell strings of a selected memory block after applying a first prepulse to a first dummy word line connected to first dummy memory cells after applying a second prepulse to a second dummy word line connected to second dummy memory cells. 1. A nonvolatile memory device , comprising:at least one memory block, including at least a first memory block comprising a plurality of cell strings arranged in rows and columns stacked perpendicular to a substrate, wherein the cell strings include: string select transistors (SSTs) connected to string select lines (SSLs), ground select transistors (GSTs) connected to ground select lines (GSLs), a plurality of nonvolatile memory cells connected to word lines, and first and second dummy memory cells connected to first and second dummy word lines; and applying a string line select voltage to a selected SSL for selected cell strings to turn on the SSTs of the selected cell strings,', 'applying a ground line select voltage to a selected GSL for selected cell strings to turn on the GSTs of the selected cell strings,', 'applying a read pass voltage to unselected word lines of unselected nonvolatile memory cells to turn on the unselected nonvolatile memory cells of the selected cell strings,', 'applying a read select voltage to a selected word line of selected nonvolatile memory cells to read data from the selected nonvolatile memory cells,', 'applying a SSL prepulse to SSLs of unselected cell strings, and then applying an unselected SSL voltage to turn off the SSTs of the unselected cell strings;', 'applying a GSL prepulse to GSLs of unselected cell strings, and then applying an unselected GSL voltage to turn off the GSTs of the unselected cell strings;', 'applying a first dummy word line prepulse to the first dummy word line such that the first dummy memory cells are turned on and then turned ...

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Номер записи: 89
13-02-2020 дата публикации

BIAS SCHEME FOR WORD PROGRAMMING IN NON-VOLATILE MEMORY AND INHIBIT DISTURB REDUCTION

Номер: US20200051642A1
Автор: Keshavarzi Ali, MENEZES Gary, Prabhakar Venkatraman, Ramkumar Krishnaswamy
Принадлежит:

A memory device that includes a non-volatile memory (NVM) array, divided into a flash memory portion and an electrically erasable programmable read-only memory (EEPROM) portion. The NVM array includes charge-trapping memory cells arranged in rows and columns, in which each memory cell has a memory transistor including an angled lightly doped drain (LDD) implant, and a select transistor including a shared source region with a halo implant. The flash memory portion and the EEPROM portion are disposed within one single semiconductor die. Other embodiments are also disclosed. 1 a memory transistor including an implant in source and drain regions, wherein the implant extends at least partly under an oxide-nitride-oxide stack of the memory transistor; and', 'a select transistor including a shared source region, wherein the shared source region is shared between two adjacent memory cells of a same row of the non-volatile memory array;, 'a non-volatile memory array divided into a flash memory portion and an electrically erasable programmable read-only memory portion, the non-volatile memory array including memory cells arranged in rows and columns, wherein each memory cell includeswherein the flash memory portion and the electrically erasable programmable read-only memory portion are disposed within one single semiconductor die.. A memory device, comprising: The present application claims the priority and benefit under 35 U.S.C. § 119(e) of U.S. Provisional Application No. 62/585,739, filed on Nov. 14, 2017, and U.S. Provisional Application No. 62/591,048, filed on Nov. 27, 2017, which are both incorporated by reference herein in each of its entirety.The present disclosure relates generally to non-volatile memory devices, and more particularly to biasing scheme for word/byte programming and methods to reduce inhibit disturb.Non-volatile memories are widely used for storing data in computer systems, and typically include a memory array with a large number of memory cells ...

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Номер записи: 90
05-03-2015 дата публикации

MEMORY CELL, MEMORY ARRAY AND OPERATION METHOD THEREOF

Номер: US20150063038A1
Автор: King Ya-Chin, Lin Chrong-Jung
Принадлежит:

A memory cell, a memory array and an operation method are disclosed herein. The memory cell includes a substrate with a first conductivity type, a first doped region with a second conductivity type, a second doped region with the second conductivity type, a first floating gate, a second floating gate and a word gate. The first and the second doped region are disposed in the substrate. The first floating gate is disposed on the substrate and electrically coupled to the first doped region. The second floating gate is disposed on the substrate and electrically coupled to the second doped region. The word line gate is disposed on the substrate and between the first and second doped region, wherein the word gate includes a first part extending over the first floating gate and a second part extending over the second floating gate. 1. A memory cell , comprising:a substrate having a first conductivity type;a first doped region having a second conductivity type disposed in the substrate;a second doped region having the second conductivity type disposed in the substrate;a first floating gate disposed on the substrate and electrically coupled to the first doped region;a second floating gate disposed on the substrate and electrically coupled to the second doped region; anda word gate disposed on the substrate and between the first doped region and the second doped region, the word gate comprising a first part extending over the first floating gate and a second part extending over the second floating gate.2. The memory cell of claim 1 , wherein the first part and the word gate substantially form a first recess claim 1 , and the second part and the word gate substantially form a second recess claim 1 , wherein the first floating gate comprises a first tip edge extending to the first recess claim 1 , and the second floating gate comprises a second tip edge extending to the second recess.3. The memory cell of claim 1 , wherein a sidewall of the first part is substantially aligned ...

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Номер записи: 91
10-03-2022 дата публикации

Semiconductor memory

Номер: US20220077170A1
Автор: Atsushi Fukumoto, Fumiki Aiso, Keisuke SUDA, Yoshiaki Fukuzumi
Принадлежит: Toshiba Memory Corp

A semiconductor memory includes a substrate, a source line layer above the substrate in a memory region and a peripheral region of the substrate, a first insulating layer above the source line layer, a first conductive layer on the first insulating layer in the memory and peripheral regions, an alternating stack of a plurality of second insulating layers and a plurality of second conductive layers on the first conductive layer in the memory region, and a plurality of pillars extending through the alternating stack of the second insulating layers and the second conductive layers, the first conductive layer, and the first insulating layer in the memory region. A bottom end of each of the pillars is in the source line layer in a thickness direction. A carrier density of the source line layer is higher in the memory region than in the peripheral region.

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Номер записи: 92
21-02-2019 дата публикации

HIGH COUPLING RATIO SPLIT GATE MEMORY CELL

Номер: US20190057970A1
Автор: SUN YUAN, Tan Shyue Seng, Toh Eng Huat
Принадлежит:

A split gate non-volatile memory (NVM) cell formed on a crystalline-on-insulator (COI) substrate, such as a fully or partially depleted silicon-on-insulator (SOI) substrate is disclosed. The split gate memory cell includes a split gate disposed on a surface substrate of the SOI substrate between source/drain (S/D) regions. The split gate includes a storage gate with a control gate (CG) over a floating gate (FG), and a select gate (SG). A back gate is provided on the bulk substrate below a buried oxide (BOX). The back gate may be doped with the same polarity type dopants as the S/D regions. The back gate is coupled to the CG to increase CG coupling ratio, improving programming performance. Alternatively, the back gate may be doped with the opposite polarity type dopants as the S/D regions. The back gate is coupled to a negative bias during program and erase operations. The negative bias increases the gate threshold voltages of the SG and CG, resulting in higher electron generation efficiency to improve programming speed as well as a higher electric field to increase erase speed. 1. A non-volatile memory (NVM) cell comprises:a substrate, the substrate includes a surface substrate and a bulk substrate separated by an insulator layer;a split gate transistor disposed on the substrate, the split gate transistor includes a first gate and a second gate separated by an integrate dielectric; and{'sub': 'BG', 'a back gate in a surface portion of the bulk substrate adjacent to the insulator layer, the back gate serves as a back gate terminal of the NVM cell and coupled to back gate bias voltage (V).'}2. The device of claim 1 , wherein the insulator layer is an ultra-thin buried oxide (UTBOX).3. The device of claim 2 , wherein the first gate serves as a storage gate and includes a first storage gate disposed underneath a second storage gate.4. The device of claim 3 , wherein the first storage gate is a floating gate (FG) and the second storage gate is a control gate (CG) claim 3 ...

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Номер записи: 93
03-03-2016 дата публикации

PAGE OR WORD-ERASABLE COMPOSITE NON-VOLATILE MEMORY

Номер: US20160064089A1
Автор: La Rosa Francesco
Принадлежит:

A non-volatile memory includes bit lines, a first page-erasable sector including memory cells of a first type, and a second word-erasable or bit-erasable sector including memory cells of a second type. The memory cells of the first type comprise a single floating-gate transistor and the memory cells of the second type comprise a first floating-gate transistor and a second floating-gate transistor the floating gates of which are electrically coupled, the second floating-gate transistor of a memory cell of the second type enabling the memory cell to be individually erased. 1. A non-volatile memory on a semiconductor substrate , comprising:bit lines,first memory cells of a first type each including a single floating-gate transistor, the floating-gate transistor of each of the first memory cells including a drain region electrically coupled to a first bit line of the bit lines,second memory cells of the first type each including a single floating-gate transistor, the floating-gate transistor of each of the second memory cells including a drain region electrically coupled to a second bit line of the bit lines, and a first floating-gate transistor including a floating gate and a drain region electrically coupled to the first bit line, and', 'a second floating-gate transistor including a floating gate and a drain region electrically coupled to the second bit line, wherein, 'memory cells of a second type each includingthe floating gate of the first floating-gate transistor is electrically coupled to the floating gate of the second floating-gate transistor, andthe second floating-gate transistor comprises a tunnel dielectric layer and a permanently conductive region extending on an opposite side of the tunnel dielectric layer with respect to the floating gate of the second floating-gate transistor.2. The memory according to claim 1 , comprising a first page-erasable or sector-erasable first sector claim 1 , including memory cells of the first type claim 1 , and a word- ...

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Номер записи: 94
20-02-2020 дата публикации

Floating Boosted Pre-Charge Scheme for Sense Amplifiers

Номер: US20200058360A1
Автор: CHIARAMONTE Loredana, Conte Antonino, Lipani Anna Rita Maria
Принадлежит:

A sense structure includes: a sense amplifier core configured to compare a measurement current with a reference current; a cascode transistor coupled to the sense amplifier core and configured to be coupled to a load; a switch coupled between a bias voltage node and a control terminal of the cascode transistor; a local capacitor having a first terminal coupled to the control terminal of the cascode transistor; a first transistor coupled between a second terminal of the local capacitor and a reference terminal; and a control circuit coupled to a control terminal of the first transistor, the control circuit configured to disconnect the local capacitor from the reference terminal to produce a voltage overshoot in the control terminal of the cascode transistor, and after disconnecting the local capacitor from the reference terminal, limit or reduce the voltage overshoot by adjusting a voltage of the control terminal of the first transistor. 1. A sense structure comprising:a sense amplifier core configured to compare a measurement current with a reference current;a cascode transistor coupled to the sense amplifier core and configured to be coupled to a load;a switch coupled between a bias voltage node and a control terminal of the cascode transistor;a local capacitor having a first terminal coupled to the control terminal of the cascode transistor;a first transistor coupled between a second terminal of the local capacitor and a reference terminal; anda control circuit coupled to a control terminal of the first transistor, the control circuit configured to disconnect the local capacitor from the reference terminal to produce a voltage overshoot in the control terminal of the cascode transistor, and after disconnecting the local capacitor from the reference terminal, limit or reduce the voltage overshoot by adjusting a voltage of the control terminal of the first transistor.2. The sense structure of claim 1 , wherein the control circuit is configured to adjust the voltage ...

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Номер записи: 95
22-05-2014 дата публикации

Read margin measurement in a read-only memory

Номер: US20140140141A1
Автор: David Alexander Grant
Принадлежит: Texas Instruments Inc

Read margin measurement circuitry for measuring the read margin of floating-gate programmable non-volatile memory cells. In some embodiments, the read margin of a cell with a floating-gate transistor in a non-conductive state is measured by periodically clocking a counter following initiation of a read cycle; a latch stores the counter contents upon the cell under test making a transition due to leakage of the floating-gate transistor. Logic for testing a group of cells in parallel is disclosed. In some embodiments, the read margin of a cell in which the floating-gate transistor is set to a conductive state is measured by repeatedly reading the cell, with the output developing a voltage corresponding to the duty cycle of the output of the read circuit.

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Номер записи: 96
02-03-2017 дата публикации

NON-VOLATILE MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME

Номер: US20170062450A1
Автор: SAKAMOTO Wataru, Suzuki Ryota
Принадлежит: KABUSHIKI KAISHA TOSHIBA

A non-volatile memory device comprises a first semiconductor layer extending in a first direction, a first electrode extending over the first semiconductor layer in a second direction crossing the first direction, a second electrode extending over the first semiconductor layer in the second direction, the second electrode being adjacent to the first electrode, a first insulating layer covering the first electrode and the second electrode, and a first interconnection provided on the first insulating layer and electrically connected to the first semiconductor layer. A first insulating layer includes a first portion extending between the first electrode and the second electrode; and the first interconnection has a first opening provided above a first part of the first semiconductor layer located below the first portion of the first insulating layer. 1. A non-volatile memory device comprising:a first semiconductor layer extending in a first direction;a first electrode extending over the first semiconductor layer in a second direction crossing the first direction;a second electrode extending over the first semiconductor layer in the second direction, the second electrode being adjacent to the first electrode;a first insulating layer covering the first electrode and the second electrode and including a first portion extending between the first electrode and the second electrode; anda first interconnection provided on the first insulating layer and electrically connected to the first semiconductor layer,the first interconnection having a first opening provided above a first part of the first semiconductor layer located below the first portion of the first insulating layer.2. The device according to claim 1 , wherein the first interconnection further includes a second opening; and the first opening and the second opening are arranged in the second direction.3. The device according to claim 1 , further comprising:a conductor adjacent to the second electrode, the conductor ...

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Номер записи: 97
02-03-2017 дата публикации

APPARATUS INCLUDING GETTERING AGENTS IN MEMORY CHARGE STORAGE STRUCTURES

Номер: US20170062577A1
Автор: Brewer Rhett T., Ramaswamy Durai V.
Принадлежит: MICRON TECHNOLOGY, INC.

Apparatus having a processor and a memory device in communication with the processor, the memory device including an array of memory cells and a control logic to control access of the array of memory cells, wherein the array of memory cells includes a memory cell having a first dielectric adjacent a semiconductor, a control gate, a second dielectric between the control gate and the first dielectric, and a charge storage structure between the first dielectric and the second dielectric, and wherein the charge storage structure includes a charge-storage material and a gettering agent. 1. An apparatus , comprising:a processor; and an array of memory cells; and', a first dielectric adjacent a semiconductor;', 'a control gate;', 'a second dielectric between the control gate and the first dielectric; and', 'a charge storage structure between the first dielectric and the second dielectric;', 'wherein the charge storage structure comprises a charge-storage material and a gettering agent; and', 'wherein at least a portion of the charge storage structure comprises a ratio of the gettering agent to the charge-storage material that is greater than a stoichiometric amount., 'a control logic to control access of the array of memory cells, wherein the array of memory cells comprises a memory cell comprising], 'a memory device in communication with the processor, the memory device comprising2. The apparatus of claim 1 , wherein claim 1 , in the memory cell claim 1 , the charge-storage material is a silicon-containing material.3. The apparatus of claim 1 , wherein claim 1 , in the memory cell claim 1 , the gettering agent comprises a plurality of gettering agents.4. The apparatus of claim 1 , wherein claim 1 , in the memory cell claim 1 , the gettering agent comprises an element or compound meeting at least one criteria claim 1 , under process conditions experienced by the charge-storage material claim 1 , selected from a group consisting of preferentially reacting with unreacted ...

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Номер записи: 98
29-05-2014 дата публикации

OPERATING METHOD OF MEMORY HAVING REDUNDANCY CIRCUITRY

Номер: US20140146613A1
Автор: CHIH Yue-Der, LIU Shang-Hsuan, YANG Tien-Chun
Принадлежит: TAIWAN SEMICONDUCTOR MANUGACTURING COMPANY, LTD.

In a method of operating a memory circuit, which includes a plurality of memory arrays each coupled with a corresponding input/output (IO) interface and a redundancy memory page a failing address of a failing bit cell is determined. The failing address is located in a memory page of one of the memory arrays. The method further includes repairing the failing bit cell by replacing the memory page with the redundancy memory page. 1. A method of operating a memory circuit , a plurality of memory arrays each coupled with a corresponding input/output (IO) interface; and', 'a redundancy memory page;, 'the memory circuit comprising determining a failing address of a failing bit cell, wherein the failing address is located in a memory page of one of the memory arrays; and', 'repairing the failing bit cell by replacing the memory page with the redundancy memory page., 'the method comprising2. The method of claim 1 , further comprising:registering bits of the failing address in at least one information row, wherein the at least one information row includes a plurality of word lines.3. The method of claim 2 , further comprising:configuring at least two of the word lines to register the bits of the failing address.4. The method of claim 2 , further comprising:downloading the failing address from the at least one information row by a multiple read process.5. A method of operating a memory circuit claim 2 , the method comprising:determining a first failing address of a first failing bit cell located in a first group of memory arrays, wherein the first group of memory arrays includes a first memory array coupled with a first input/output (IO) interface and a second memory array coupled with a second IO interface; andrepairing the first failing bit cell;wherein the repairing the first failing bit cell comprises using a redundancy memory page, wherein the redundancy memory page is configured to selectively repair any memory page of the first and second memory arrays of the first ...

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Номер записи: 99
29-05-2014 дата публикации

Memory device having three-dimensional gate structure

Номер: US20140146614A1
Автор: Jeong-Min Choi, Nam-Kyeong Kim
Принадлежит: Micron Technology Inc

Subject matter disclosed herein relates to a memory device, and more particularly to a nonvolatile memory device having a recess structure and methods of fabricating same.

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Номер записи: 100