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Небесная энциклопедия

Космические корабли и станции, автоматические КА и методы их проектирования, бортовые комплексы управления, системы и средства жизнеобеспечения, особенности технологии производства ракетно-космических систем

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Мониторинг СМИ

Мониторинг СМИ и социальных сетей. Сканирование интернета, новостных сайтов, специализированных контентных площадок на базе мессенджеров. Гибкие настройки фильтров и первоначальных источников.

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Применить Всего найдено 8217. Отображено 100.
05-01-2012 дата публикации

Methods, structures, and devices for reducing operational energy in phase change memory

Номер: US20120002465A1
Автор: Roy E. Meade
Принадлежит: Micron Technology Inc

Methods of forming and operating phase change memory devices include adjusting an activation energy barrier between a metastable phase and a stable phase of a phase change material in a memory cell. In some embodiments, the activation energy barrier is adjusted by applying stress to the phase change material in the memory cell. Memory devices include a phase change memory cell and a material, structure, or device for applying stress to the phase change material in the memory cell. In some embodiments, a piezoelectric device may be used to apply stress to the phase change material. In additional embodiments, a material having a thermal expansion coefficient greater than that of the phase change material may be positioned to apply stress to the phase change material.

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Номер записи: 1
26-01-2012 дата публикации

Non-Volatile Memory Element And Memory Device Including The Same

Номер: US20120018695A1
Автор: Chang-Bum Lee, Chang-Jung Kim, Dong-Soo Lee, Ji-hyun Hur, Man Chang, Myoung-Jae Lee, Seung-Ryul Lee, Young-Bae Kim
Принадлежит: SAMSUNG ELECTRONICS CO LTD

Example embodiments, relate to a non-volatile memory element and a memory device including the same. The non-volatile memory element may include a memory layer having a multi-layered structure between two electrodes. The memory layer may include first and second material layers and may show a resistance change characteristic due to movement of ionic species therebetween. The first material layer may be an oxygen-supplying layer. The second material layer may be an oxide layer having a multi-trap level.

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Номер записи: 2
02-02-2012 дата публикации

Memory resistor having plural different active materials

Номер: US20120026776A1
Автор: Jianhua Yang, Minxian Max Zhang, R. Stanley Williams
Принадлежит: Hewlett Packard Development Co LP

Methods and means related to memory resistors are provided. A memristor includes at least two different active materials disposed between a pair of electrodes. The active materials are selected to exhibit respective and opposite changes in electrical resistance in response to changes in oxygen ion content. The active materials are subject to oxygen ion reconfiguration under the influence of an applied electric field. An electrical resistance of the memristor is thus adjustable by way of applied programming voltages and is non-volatile between programming events.

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Номер записи: 3
16-02-2012 дата публикации

Semiconductor memory device

Номер: US20120039110A1
Автор: Hiroshi Maejima, Koji Hosono
Принадлежит: Toshiba Corp

A memory-cell array that includes a first line, a second line intersecting the first line, and a memory cell including a variable resistive element provided in the intersection of the first and the second lines; a data-write unit configured to apply a voltage pulse to the memory cell through the first and the second lines, the voltage pulse to set and/or reset data; and a detector unit configured to compare a cell current that flows through the memory cell by the voltage pulse at the time of setting and/or resetting the data with a reference current generated from the initial value of the cell current, and to control the data-write unit in accordance with a result of comparison.

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Номер записи: 4
23-02-2012 дата публикации

Memory devices using a plurality of diodes as program selectors for memory cells

Номер: US20120044736A1
Автор: Shine C. Chung
Принадлежит: Chung Shine C

At least one junction diode fabricated in standard CMOS logic processes can be used as program selectors for the memory cells that can be programmed based on the directions of current flow. These memory cells are MRAM, RRAM, CBRAM, or other memory cells that have a resistive element coupled to the P terminal of the first diode and to the N terminal of a second diode. The diodes can be constructed by P+ and N+ active regions on an N well as the P and N terminals of the diodes. By applying a high voltage to a resistive element and switching the N terminal of the first diode to a low voltage while disabling the second diode, a current flows through the memory cell can change the resistance into one state. Similarly, by applying a low voltage to a resistive element and switching the P terminal of the second diode to a high voltage while disabling the first diode, a current flows through the memory cell can change the resistance into another state. The P+ active region of the diode can be isolated from the N+ active region in an N well by using dummy MOS gate, SBL, or STI isolations.

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Номер записи: 5
23-02-2012 дата публикации

One-time programmable memories using polysilicon diodes as program selectors

Номер: US20120044738A1
Автор: Shine C. Chung
Принадлежит: Chung Shine C

Polysilicon diodes fabricated in standard CMOS logic processes can be used as program selectors for One-Time Programmable (OTP) devices, using electrical fuse, contact/via fuse, contact/via anti-fuse, or gate-oxide breakdown anti-fuse etc. as OTP element The diode can be constructed by P+/N+ implants on a polysilicon as a program selector. The OTP device has an OTP element coupled to a polysilicon diode. The OTP devices can be used to construct a two-dimensional OTP memory with the N-terminals of the diodes in a row connected as a wordline and the OTP elements in a column connected as a bitline. By applying a high voltage between a selected bitline and a selected wordline to turn on a diode in a selected cell for suitable duration of time, a current flows through an OTP element may change the resistance state. The cell data in the OTP memory can also be read by turning on a selected wordline and to couple a selected bitline to a sense amplifier. The wordlines may have high-resistivity local wordlines coupled to low-resistivity global wordlines through conductive contact(s) or via(s).

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Номер записи: 6
23-02-2012 дата публикации

Reversible resistive memory using diodes formed in cmos processes as program selectors

Номер: US20120044747A1
Автор: Shine C. Chung
Принадлежит: Chung Shine C

Junction diodes fabricated in standard CMOS logic processes can be used as program selectors for reversible resistive memory cells that can be programmed based on magnitude, duration, voltage-limit, or current-limit of a supply voltage or current. These cells are PCM, RRAM, CBRAM, or other memory cells that have a reversible resistive element coupled to a diode. The diode can be constructed by P+ and N+ active regions on an N well as the P and N terminals of the diode. The memory cells can be used to construct a two-dimensional memory array with the N terminals of the diodes in a row connected as a wordline and the reversible resistive elements in a column connected as a bitline. By applying a voltage or a current to a selected bitline and to a selected wordline to turn on the diode, a selected cell can be programmed into different states reversibly based on magnitude, duration, voltage-limit, or current-limit. The data in the reversible resistive memory can also be read by turning on a selected wordline to couple a selected bitline to a sense amplifier. The wordlines may have high-resistivity local wordlines coupled to low-resistive global wordlines through conductive contact(s) or via(s).

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Номер записи: 7
23-02-2012 дата публикации

Programmably reversible resistive device cells using cmos logic processes

Номер: US20120044753A1
Автор: Shine C. Chung
Принадлежит: Chung Shine C

Junction diodes fabricated in standard CMOS logic processes can be used as program selectors for reversible resistive devices, such as PCM, RRAM, CBRAM, or other memory cells. The reversible resistive devices have a reversible resistive element coupled to a diode. The diode can be constructed by P+ and N+ active regions on an N well as the P and N terminals of the diode. By applying a voltage or a current between a reversible resistive element and the N terminal of a diode, the reversible resistive device can be programmed into different states based on magnitude, duration, voltage-limit, or current-limit in a reversible manner. The P+ active region of the diode can be isolated from the N+ active region in the N well by using dummy MOS gate, SBL, or STI/LOCOS isolations.

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Номер записи: 8
08-03-2012 дата публикации

Semiconductor memory apparatus and method for controlling programming current pulse

Номер: US20120057417A1
Автор: Yong Bok An
Принадлежит: Hynix Semiconductor Inc

A semiconductor memory apparatus includes a write control code generation unit configured to generate a write control code which is updated at each pulsing timing of an external test pulse signal applied through a pad; and a data write unit configured to output a programming current pulse which has a magnitude corresponding to the code value of the write control code.

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Номер записи: 9
15-03-2012 дата публикации

Multi-level resistance change memory

Номер: US20120063193A1
Автор: Reika Ichihara
Принадлежит: Individual

According to one embodiment, a multi-level resistance change memory includes a memory cell includes first and second resistance change films connected in series, and a capacitor connected in parallel to the first resistance change film, a voltage pulse generating circuit generating a first voltage pulse with a first pulse width to divide a voltage of the first voltage pulse into the first and second resistance change films based on a resistance ratio thereof, and generating a second voltage pulse with a second pulse width shorter than the first pulse width to apply a voltage of the second voltage pulse to the second resistance change film by a transient response of the capacitor, and a control circuit which is stored multi-level data to the memory cell by using the first and second voltage pulses in a writing.

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Номер записи: 10
22-03-2012 дата публикации

Nonvolatile semiconductor memory device

Номер: US20120069627A1
Автор: Hiroshi Kanno, Mitsuru Sato, Natsuki Kikuchi, Takafumi SHIMOTORI, Takayuki Tsukamoto, Yoichi MINEMURA
Принадлежит: Toshiba Corp

A nonvolatile semiconductor memory device includes: a memory cell array including plural first lines, plural second lines, and plural memory cells each including a variable resistance element; a first decoder connected to at least one ends of the plurality of first lines and configured to select at least one of the first lines; at least one pair of second decoders connected to both ends of the plurality of second lines and configured such that one of the pair of second decoders is selected for selecting the second lines according to a distance between the one of the first lines selected by the first decoder and the both ends of the second lines; and a voltage application circuit configured to apply a certain voltage between the first line and the second line selected by the first decoder and the second decoder.

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Номер записи: 11
29-03-2012 дата публикации

Resistive Random Access Memory and Verifying Method Thereof

Номер: US20120075908A1
Автор: Chih-He Lin, Pei-Chia Chiang, Shyh-Shyuan Sheu, Wen-Pin Lin
Принадлежит: Industrial Technology Research Institute ITRI

A resistive random access memory (RRAM) and a verifying method thereof are provided. The RRAM comprises at least one resistive memory cell. The resistive memory cell comprises a resistive memory element and a transistor, wherein one terminal of the resistive memory element is coupled to a first terminal of the transistor. The verifying method comprises the following steps: Whether the resistive memory cell passes verification is determined. During a first time period and under the circumstance that the resistive memory cell fails to pass verification, a reference voltage is applied to the other terminal of the resistive memory element and a voltage pulse is applied to a second terminal of the transistor according to a voltage signal to write a reverse voltage to the resistive memory cell.

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Номер записи: 12
19-04-2012 дата публикации

Resistive Memory Element and Use Thereof

Номер: US20120092920A1
Автор: Sakyo Hirose
Принадлежит: Murata Manufacturing Co Ltd

A resistive memory element that includes an element body and at least a pair of electrodes opposed to each other with at least a portion of the element body interposed therebetween. The element body is made of an oxide semiconductor which has a composition represented by the general formula: (Ba 1-x Sr x )Ti 1-y M y O 3 (wherein M is at least one from among Mn, Fe, and Co; 0≦x≦1.0; and 0.005≦y≦0.05). The first electrode of the pair of electrodes is made of a material which can form a Schottky barrier which can develop a rectifying property and resistance change characteristics in an interface region between the first electrode and the element body. The second electrode is made of a material which provides a more ohmic junction to the element body as compared with the first electrode.

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Номер записи: 13
26-04-2012 дата публикации

Cross point variable resistance nonvolatile memory device

Номер: US20120099367A1
Автор: Kazuhiko Shimakawa, Ryotaro Azuma
Принадлежит: Panasonic Corp

A cross point variable resistance nonvolatile memory device includes memory cells having the same orientation for stable characteristics of all layers. Each memory cell ( 51 ) is placed at a different one of cross points of bit lines ( 53 ) in an X direction and word lines ( 52 ) in a Y direction formed in layers. In a multilayer cross point structure where vertical array planes sharing the word lines are aligned in the Y direction each for a group of bit lines aligned in a Z direction, even and odd layer bit line selection switch elements ( 57, 58 ) switch electrical connection and disconnection between a global bit line ( 56 ) and commonly-connected even layer bit lines and commonly-connected odd layer bit lines, respectively. A bidirectional current limiting circuit ( 92 ) having parallel-connected P-type current limiting element ( 91 ) and N-type current limiting element ( 90 ) is provided between the global bit line and the switch elements.

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Номер записи: 14
03-05-2012 дата публикации

Phase-change memory device

Номер: US20120106244A1
Автор: Ki-won Lim, Won-ryul Chung, Young-Ran Kim
Принадлежит: SAMSUNG ELECTRONICS CO LTD

A phase-change memory device and its firing method are provided. The firing method of the phase-change memory device includes applying a writing current to phase-change memory cells, identifying a state of the phase-change memory cells after applying the writing current, and applying a firing current, in which an additional current is added to the writing current, to the phase-change memory cells in accordance with the state.

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Номер записи: 15
17-05-2012 дата публикации

Phase change memory device

Номер: US20120120724A1
Автор: Hyuck-Soo Yoon
Принадлежит: Individual

A phase change memory device includes a signal generator configured to generate first and second sensing and amplifying enable signals which are sequentially activated during an activation period of a word line selection signal and each of which has a certain activation period length, a resistance sensor configured to sense a resistance value by applying a certain operation current to a phase change memory cell corresponding to the word line selection signal during an activation period of the first sensing and amplifying enable signal and a voltage level amplifier configured to logically determine a voltage level of the resistance sensing signal based on a voltage level of a logic reference signal during an activation period of the second sensing.

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Номер записи: 16
24-05-2012 дата публикации

Memory resistor adjustment using feedback control

Номер: US20120127780A1
Автор: Gilberto Ribeiro, Jianhua Yang, John Paul Strachan, Julien Borghetti, Matthew D. Pickett
Принадлежит: Hewlett Packard Development Co LP

Apparatus and methods related to memory resistors are provided. A feedback controller applies adjustment signals to a memristor. A non-volatile electrical resistance of the memristor is sensed by the feedback controller during the adjustment. The memristor is adjusted to particular values lying between first and second limiting values with minimal overshoot. Increased memristor service life, faster operation, lower power consumption, and higher operational integrity are achieved by the present teachings.

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Номер записи: 17
14-06-2012 дата публикации

Programming reversible resistance switching elements

Номер: US20120147657A1
Автор: Deepak C. Sekar, Klaus Schuegraf, Roy Scheuerlein
Принадлежит: SanDisk 3D LLC

A storage system and method for operating the storage system that uses reversible resistance-switching elements is described. Techniques are disclosed herein for varying programming conditions to account for different resistances that memory cells have. These techniques can program memory cells in fewer attempts, which can save time and/or power. Techniques are disclosed herein for achieving a high programming bandwidth while reducing the worst case current and/or power consumption.

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Номер записи: 18
19-07-2012 дата публикации

Memory unit and method of operating the same

Номер: US20120182785A1
Автор: Wataru Otsuka
Принадлежит: Sony Corp

A memory unit includes memory cells each having a memory element and a transistor, word lines and first and second bit lines, and a drive section. In performing setting operation for a first memory element located on one word line and in performing resetting operation for a second memory element located on the one word line, the drive section applies a given word line electric potential to the one word line, and sets an electric potential of a bit line on a lower electric potential side out of the first and the second bit lines corresponding to the first memory element to a value higher than a value of an electric potential of a bit line on the lower electric potential side corresponding to the second memory element by an amount of given electric potential difference.

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Номер записи: 19
23-08-2012 дата публикации

Memory apparatus

Номер: US20120212994A1
Автор: Chieko Nakashima, Hiroshi Yoshihara, Kentaro Ogata, Makoto Kitagawa, Tomohito Tsushima, Tsunenori Shiimoto
Принадлежит: Sony Corp

A memory apparatus includes: a plurality of memory cells which includes a first resistance change element; and a read-out circuit which determines the size of a resistance value of the first resistance change element by comparing the resistance state of a memory cell selected among the plurality of memory cells to the resistance state of a reference memory cell, wherein the reference memory cell includes a second resistance change element, a resistance value of the second resistance change element with respect to an applied voltage is smaller than that in a high resistance state of the first resistance change element, and the second resistance change element shows the same resistance change characteristic as the first resistance change element.

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Номер записи: 20
30-08-2012 дата публикации

Write bandwidth in a memory characterized by a variable write time

Номер: US20120218814A1
Автор: John A. Bivens, Luis A. Lastras-Montano, Michele M. Franceschini
Принадлежит: International Business Machines Corp

A memory system that includes a plurality of memory arrays having memory cells characterized by a variable write time. The memory system also includes a memory bus configured to receive write commands, and a plurality of data buffers configured to communicate with the memory arrays. The memory system further includes an address buffer configured to communicate with the memory arrays to store the write addresses. A mechanism configured to receive a write command and to split a data line received with the write command into a number of parts is also included in the memory system. The parts of the data line are stored in different data buffers and the writing of the parts of the data line to memory arrays at the write address is initiated. The write command is completed when write completion signals specifying the write address have been received from all of the memory arrays.

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Номер записи: 21
20-09-2012 дата публикации

Program cycle skip

Номер: US20120236663A1
Автор: Gopinath Balakrishnan, Luca Fasoli, Tz-yi Liu, Yan Li, Yuheng Zhang
Принадлежит: SanDisk 3D LLC

A non-volatile storage system includes technology for skipping programming cycles while programming a page (or other unit) of data. While programming a current subset of the page (or other unit) of data, the system will evaluate whether the next subsets of the page (or other unit) of data should be programmed into non-volatile storage elements or skipped. Subsets of the page (or other unit) of data that should not be skipped are programmed into non-volatile storage elements. Some embodiments include transferring the appropriate data to temporary latches/registers, in preparation for programming, concurrently with the evaluation of whether to program or skip the programming.

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Номер записи: 22
27-09-2012 дата публикации

Method and apparatus providing a cross-point memory array using a variable resistance memory cell and capacitance

Номер: US20120243298A1
Автор: Glen Hush
Принадлежит: Individual

The invention relates to a method and apparatus providing a memory cell array in which each resistance memory cell is connected in series to a capacitive element. Access transistors are not necessary to perform read and write operations on the memory cell. In one exemplary embodiment, the capacitive element is a capacitor.

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Номер записи: 23
27-09-2012 дата публикации

Control Method for Memory Cell

Номер: US20120243346A1
Автор: Ching-Chih HSU, Frederick T. Chen, Heng-Yuan Lee, Pang-Shiu Chen, Yen-Ya Hsu, Yu-Sheng Chen
Принадлежит: Industrial Technology Research Institute ITRI

A control method for at least one memory cell. The memory cell includes a transistor and a resistor. The resistor is connected to the transistor in series between a first node and a second node. In a programming mode, the memory cell is programmed. When it is determined that the memory cell has been successfully programmed, impedance of the memory cell is in a first state. When it is determined that the memory cell has not been successfully programmed, a specific action is executed to reset the memory cell. The impedance of the memory cell is in a second state after the step resetting the memory cell. The impedance of the memory cell in the second state is higher than that of the memory cell in the first state.

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Номер записи: 24
04-10-2012 дата публикации

Semiconductor memory device and controlling method thereof

Номер: US20120250393A1
Автор: Masanobu Shirakawa
Принадлежит: Individual

According to one embodiment, a semiconductor memory device includes a memory cell array in which memory cells each including at least a rectification element and a variable resistance element, which are connected in series, a peripheral circuit, a sense amplifier configured to sense the memory cells via the peripheral circuit, and a control circuit configured to control operations of the memory cell array and the sense amplifier. The control circuit is configured to boost a potential of a selected bit line, which is one of a first even bit line and a first odd bit line of a first side, by charge sharing of a second even bit line and a second odd bit line which are nonselected bit lines and physically neighbor the first even bit line or the first odd bit line of the first side, which is connected to a selected one of the memory cells.

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Номер записи: 25
11-10-2012 дата публикации

Semiconductor device

Номер: US20120257437A1
Автор: Akiyoshi Seko, Tatsuya Matano
Принадлежит: Elpida Memory Inc

A semiconductor device includes first and second interconnects, a variable resistance element that may assume a first resistance value or a second resistance value in response to the current flowing therein, and second transistors connected between the first and second interconnects in series with each other on both sides of the variable resistance element, and a power supply circuit unit that delivers the power supply to a control electrode of the first transistor. The power supply circuit unit supplies the power of a first power supply when the variable resistance element is to make transition to the first resistance value and the power supply circuit unit supplies the power of a second power supply when the variable resistance element is to make transition to the second resistance value, thereby allowing transitioning of the resistance values of the variable resistance element

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Номер записи: 26
18-10-2012 дата публикации

Semiconductor memory device

Номер: US20120266043A1
Автор: Kazuya Ishihara, Mitsuru Nakura, Nobuyoshi Awaya
Принадлежит: Individual

The invention realizes a semiconductor memory device that can efficiently execute a detection of a data error that might possibly occur in a continuous reading action, and a correction of the error data. The semiconductor memory device uses a variable resistive element made of a metal oxide for storing information. During a reading action of coded data with an ECC in the semiconductor memory device, when a data error is detected by an ECC circuit, a writing voltage pulse having a polarity opposite to a polarity of a reading voltage pulse is applied to all memory cells from which the error is detected so as to correct bits from which the error is detected, on an assumption that an erroneous writing has occurred due to the application of the writing voltage pulse having the polarity same as the polarity of the applied reading voltage pulse.

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Номер записи: 27
08-11-2012 дата публикации

Nonvolatile latch circuit and nonvolatile flip-flop circuit

Номер: US20120280713A1
Автор: Yoshikazu Katoh
Принадлежит: Panasonic Corp

A nonvolatile latch circuit of the invention includes a variable resistance element which is formed by interposing an oxide layer between electrodes, and changes to a low resistance state by applying a voltage to cause current flow in the direction from the first to the second electrode, and changes to a high resistance state by applying a voltage to cause current flow in the reverse direction, wherein a first terminal of a transistor, a first terminal of other transistor, an output terminal of an inverter circuit, and an output terminal of other inverter circuit are respectively connected to one electrode, the other electrode, a second terminal of the transistor, and a second terminal of the other transistor, and a current flowing through the variable resistance element when changed to a low resistance state is smaller in absolute value than a current therethrough when changed to a high resistance state.

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Номер записи: 28
06-12-2012 дата публикации

Nitrogen Doped Aluminum Oxide Resistive Random Access Memory

Номер: US20120305881A1
Автор: Siu-Weng S. Wong, Sung Il Park, Wanki Kim, Zhiping Zhang
Принадлежит: Leland Stanford Junior University

A resistive random access memory (RRAM) device is provided that includes a first electrode, a second electrode, and a resistance-change film disposed between the first electrode and the second electrode, where the resistance-change film includes an atomic ratio of aluminum, oxygen and nitrogen.

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Номер записи: 29
20-12-2012 дата публикации

Resistance-change memory device and method of operating the same

Номер: US20120320659A1
Автор: Makoto Kitagawa
Принадлежит: Sony Corp

Disclosed herein is a resistance-change memory device including a bit line; a voltage supplying layer; a memory element connected between the bit line and the voltage supplying layer, a resistance value of the memory element being changed in accordance with an applied voltage; and a drive controlling circuit causing a first current to flow through the bit line and causing a second current smaller than the first current to flow through the bit line, thereby controlling a resistance decreasing operation in which the memory element is made to transit from a high resistance state to a low resistance state by using the second current.

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Номер записи: 30
27-12-2012 дата публикации

Programming of phase-change memory cells

Номер: US20120327709A1
Автор: Abu Sebastian, Angeliki Pantazi, Charalampos Pozidis, Nikolaos Papandreou, Urs Frey
Принадлежит: International Business Machines Corp

A method and apparatus for programming a phase-change memory cell. A bias voltage signal (V BL ) is applied to the cell. A measurement portion (m) of this bias voltage signal has a profile which varies with time. A measurement (T M ), which is dependent on a predetermined condition being satisfied, is then made. The predetermined condition is dependent on cell current during the measurement portion (m) of the bias voltage signal. A programming signal is generated in dependence on the measurement (T M ), and the programming signal is applied to program the cell.

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Номер записи: 31
10-01-2013 дата публикации

Memory system with data line switching scheme

Номер: US20130010523A1
Автор: Luca Fasoli, Tianhong Yan
Принадлежит: SanDisk 3D LLC

A storage system includes a three-dimensional memory array that has multiple layers of non-volatile storage elements grouped into blocks. Each block includes a subset of first selection circuits for selectively coupling a subset of array lines (e.g. bit lines) of a first type to respective local data lines. Each block includes a subset of second selection circuits for selectively coupling a subset of the respective local data lines to global data lines that are connected to control circuitry. To increase the performance of memory operations, the second selection circuits can change their selections independently of each other.

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Номер записи: 32
10-01-2013 дата публикации

Descending set verify for phase change memory

Номер: US20130010533A1
Автор: Ferdinando Bedeschi
Принадлежит: Micron Technology Inc

Subject matter disclosed herein relates to a memory device, and more particularly to write performance of a phase change memory.

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Номер записи: 33
24-01-2013 дата публикации

Resistive ram, method for fabricating the same, and method for driving the same

Номер: US20130021835A1
Автор: Hyun-Sang Hwang, Myoung-Woo Son, Xinjun Liu
Принадлежит: Individual

A resistive random access memory (ReRAM) includes a first electrode, a threshold switching layer formed over the first electrode and configured to perform a switching operation according to an applied voltage, a resistance change layer formed over the threshold switching layer, and configured to perform a resistance change operation, and a second electrode formed over the resistance change layer, wherein the threshold switching layer comprises a stoichiometric transition oxide while the resistance change layer comprises a non-stoichiometric transition metal oxide.

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Номер записи: 34
24-01-2013 дата публикации

Programming at least one multi-level phase change memory cell

Номер: US20130021845A1
Автор: Abu Sebastian, Angeliki Pantazi, Evangelos S. Eleftheriou, Haris Pozidis, Nikolaos Papandreou
Принадлежит: International Business Machines Corp

A method is provided that comprises a step of programming the PCM cell to have a respective definite cell state by at least one current pulse flowing to the PCM cell, said respective definite cell state being defined at least by a respective definite resistance level, a step of controlling said respective current pulse by a respective bitline pulse and a respective wordline pulse, and a step of controlling said respective bitline pulse and said respective wordline pulse dependent on an actual resistance value of the PCM cell and a respective reference resistance value being defined for the definite resistance level.

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Номер записи: 35
21-02-2013 дата публикации

Programming at least one multi-level phase change memory cell

Номер: US20130044540A1
Автор: Abu Sebastian, Angeliki Pantazi, Evangelos S. Eleftheriou, Haris Pozidis, Nikolaos Papandreou
Принадлежит: International Business Machines Corp

An apparatus for programming at least one multi-level Phase Change Memory (PCM) cell having a first terminal and a second terminal A programmable control device controls the PCM cell to have a respective cell state by applying at least one current pulse to the PCM cell, the control device controlling the at least one current pulse by applying a respective first pulse to the first terminal and a respective second pulse applied to the second terminal of the PCM cell. The respective cell state is defined by a respective resistance level. The control device receives a reference resistance value defining a target resistance level for the cell, and further receives an actual resistance value of said PCM cell such that the applying the respective first pulse and said respective second pulse is based on said actual resistance value of the PCM cell and said received reference resistance value.

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Номер записи: 36
28-02-2013 дата публикации

Methods, apparatuses, and circuits for programming a memory device

Номер: US20130051136A1
Автор: Agostino Pirovano, Andrea Redaelli, Umberto M. Meotto
Принадлежит: Micron Technology Inc

Subject matter described pertains to methods, apparatuses, and circuits for programming a memory device.

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Номер записи: 37
07-03-2013 дата публикации

Device fabrication

Номер: US20130059436A1
Автор: Darrell Rinerson, Robin Cheung
Принадлежит: Individual

Device fabrication is disclosed, including forming a first part of a device at a first fabrication facility as part of a front-end-of-the-line (FEOL) process, the first part of the device comprising a base wafer formed by FEOL processing, and subsequently performing one or more back-end-of-the-line (BEOL) processes at a second fabrication facility to form an IC, the one or more BEOL processes comprising finishing the forming of the device (e.g., an IC including memory) by depositing one or more memory layers on the base wafer. FEOL processing can be used to form active circuitry die (e.g., CMOS circuitry on a Si wafer) and BEOL processing can be used to form on top of each active circuitry die, one or more layers of cross-point memory arrays formed by thin film processing technologies that may or may not be compatible with or identical to some or all of the FEOL processes.

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Номер записи: 38
23-05-2013 дата публикации

Systems and methods for modeling binary synapses

Номер: US20130132314A1
Автор: Gregory Stuart Snider
Принадлежит: Hewlett Packard Development Co LP

Methods and system for modeling the behavior of binary synapses are provided. In one aspect, a method of modeling synaptic behavior includes receiving an analog input signal and transforming the analog input signal into an N-bit codeword, wherein each bit of the N-bit codeword is represented by an electronic pulse ( 1001 ). The method includes loading the N-bit codeword into a circular shift register ( 1002 ) and sending each bit of the N-bit codeword through one of N switches. Each switch applies a corresponding weight to the bit to produce a weighted bit. A signal corresponding to a summation of the weighted bits is output and represents a synaptic transfer function characterization of a binary synapse ( 1009 ).

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Номер записи: 39
30-05-2013 дата публикации

Selector Device for Memory Applications

Номер: US20130134382A1
Автор: Iuliana Radu, Koen Martens, Pieter Blomme, Stefan Cosemans
Принадлежит: Interuniversitair Microelektronica Centrum vzw IMEC, KU Leuven Research and Development

The present disclosure is related to a selector device for memory applications. The selector device for selecting a memory element in a memory array comprises an MIT element and a decoupled heater, thermally linked to the MIT element. The MIT element comprises a MIT material component and a barrier component and is switchable from a high to a low resistance state by heating the MIT element above a transition temperature with the decoupled heater. The barrier component is provided to increase the resistance of the MIT element in the high resistance state.

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Номер записи: 40
27-06-2013 дата публикации

Method of programming variable resistance element, method of initializing variable resistance element, and nonvolatile storage device

Номер: US20130163308A1
Автор: Mitsuteru Iijima, Takeshi Takagi
Принадлежит: Panasonic Corp

Programming a variable resistance element includes: a writing step of applying a writing voltage pulse to transition metal oxide comprising two stacked metal oxide layers to decrease resistance of the metal oxide, each metal oxide layer having different oxygen deficiency; and an erasing step of applying an erasing voltage pulse, of different polarity than the writing pulse, to the metal oxide to increase resistance of the metal oxide. |Vw 1 |>|Vw 2 |. Vw 1 represents writing voltage for first to N-th steps, Vw 2 represents writing voltage for (N+1)-th and subsequent steps, where N≧1, |Ve 1 |>|Ve 2 |. Ve 1 represents erasing voltage for first to M-th steps. Vet represents erasing voltage for M+1-th and subsequent steps. tw 1 <te 1 . tw 1 represents writing pulse width for first to N-th steps. te 1 represents erasing pulse width for first to M-th steps. M≧1. The (N+1)-th writing step follows the M-th erasing step.

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Номер записи: 41
27-06-2013 дата публикации

Parallel programming scheme in multi-bit phase change memory

Номер: US20130163322A1
Автор: Chung H. Lam, Jing Li
Принадлежит: International Business Machines Corp

A system, a method for parallel programming multiple bits of a phase change memory array for high bandwidth. The system and method includes parallel programming scheme wherein a common wordline (WL) is driven with a first pulse of one of: gradually increasing (RESET) or decreasing (SET) amplitudes which control current flow through one or more phase change memory cells associated with the WL. Simultaneously therewith, one or more bitlines (BLs) are driven with one or more second pulses, each second pulse more narrow than that of the first pulse applied to the WL. The starting time of the one or more second pulses may vary with each bitline driven at a time later than, but within the window of the wordline pulse to achieve a programming current suitable for achieving the corresponding memory cell state.

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Номер записи: 42
04-07-2013 дата публикации

Variable resistance memory device

Номер: US20130170282A1
Автор: Jae-Yun YI
Принадлежит: Individual

A variable resistance memory device includes: first and second structures that each include a first electrode, a second electrode, and a variable resistance material layer interposed between the first and second electrodes and configured to switch between different resistance states depending on a voltage applied across the variable resistance material layer; and a material layer interposed between the first and second structures and configured to pass a bidirectional current according to a voltage applied across the material layer. The first and second structures are symmetrical with respect to the material layer.

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Номер записи: 43
25-07-2013 дата публикации

Variable resistance nonvolatile memory element writing method and variable resistance nonvolatile memory device

Номер: US20130188414A1
Автор: Kazuhiko Shimakawa, Ken Kawai, Yoshikazu Katoh
Принадлежит: Panasonic Corp

A variable resistance nonvolatile memory element writing method of, by applying a voltage pulse to a memory cell including a variable resistance element, reversibly changing the variable resistance element between a first resistance state and a second resistance state according to a polarity of the applied voltage pulse is provided. The variable resistance nonvolatile memory element writing method includes applying a first preliminary voltage pulse and subsequently applying the first voltage pulse to the variable resistance element to change the variable resistance element from the second resistance state to the first resistance state, the first preliminary voltage pulse being smaller in voltage absolute value than the second threshold voltage and different in polarity from the first voltage pulse.

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Номер записи: 44
29-08-2013 дата публикации

Memory Device Having An Integrated Two-Terminal Current Limiting Resistor

Номер: US20130221314A1
Автор: Dipankar Pramanik, Mankoo Lee, Tony P. Chiang
Принадлежит: Intermolecular Inc

A resistor structure incorporated into a resistive switching memory cell or device to form memory devices with improved device performance and lifetime is provided. The resistor structure may be a two-terminal structure designed to reduce the maximum current flowing through a memory device. A method is also provided for making such memory device. The method includes depositing a resistor structure and depositing a variable resistance layer of a resistive switching memory cell of the memory device, where the resistor structure is disposed in series with the variable resistance layer to limit the switching current of the memory device. The incorporation of the resistor structure is very useful in obtaining desirable levels of device switching currents that meet the switching specification of various types of memory devices. The memory devices may be formed as part of a high-capacity nonvolatile memory integrated circuit, which can be used in various electronic devices.

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Номер записи: 45
29-08-2013 дата публикации

Circuit and method for reading a resistive switching device in an array

Номер: US20130223132A1
Автор: Frederick Perner
Принадлежит: Hewlett Packard Development Co LP

A read circuit for sensing a resistive state of a resistive switching device in a crosspoint array has an equipotential preamplifier connected to a selected column line of the resistive switching device in the array to deliver a read current while maintaining the selected column line at a reference voltage near a biasing voltage applied to unselected row lines of the array. The read circuit includes a reference voltage generation component for generating the reference voltage for the equipotential preamplifier. The reference voltage generation component samples the biasing voltage via the selected column line and adds a small increment to a sampled biasing voltage to form the reference voltage.

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Номер записи: 46
29-08-2013 дата публикации

Method and circuit for switching a memristive device in an array

Номер: US20130223134A1
Автор: Frederick Perner, Muhammad Chakeel Qureshi, Richard Carter, Wei Yi
Принадлежит: Hewlett Packard Development Co LP

A method of switching a memristive device in a two-dimensional array senses a leakage current through the two-dimensional array when a voltage of half of a switching voltage is applied to a row line of the memristive device. A leakage compensation current is generated according to the sensed leakage current, and a switching current ramp is also generated. The leakage compensation current and the switching current ramp are combined to form a combined switching current, which is applied to the row line of the memristive device. When a resistance of the memristive device reaches a target value, the combined switching current is removed from the row line.

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Номер записи: 47
26-09-2013 дата публикации

Phase-change random access memory device having multi-levels and method of manufacturing the same

Номер: US20130248805A1
Автор: Min Seok Son
Принадлежит: Individual

A phase-change random access memory (PCRAM) device and a method of manufacturing the same. The PCRAM includes a heating electrode having an upper surface protruding in a stepped shape and a phase-change material layer formed in a phase-change space on the heating electrode, the phase-change material layer having a plurality of portions having thicknesses corresponding to the stepped shape of the heating electrode.

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Номер записи: 48
03-10-2013 дата публикации

Method of changing reflectance or resistance of a region in an optoelectronic memory device

Номер: US20130258765A1
Автор: Christopher David Muzzy, Fen Chen, Richard Steven Kontra, Theodore M. Levin, Timothy Dooling Sullivan, Tom C. Lee
Принадлежит: International Business Machines Corp

A method for changing reflectance or resistance of a region in an optoelectronic memory device. Changing the reflectance of the region includes sending an electric current through the region to cause a reflectance change in the region. Changing the resistance of the region includes: projecting a laser beam at a first beam intensity on the region, resulting in the region changing from a first to a second different resistance value; electrically reading the second resistance value during which an optical signal carried by the laser beam has a first digital value; after electrically reading the second resistance value, the laser beam is projected at a second beam intensity on the region resulting in the region changing from the second to the first resistance value; and electrically reading the first resistance value of the region while the laser beam is being projected on the region at the second beam intensity.

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Номер записи: 49
03-10-2013 дата публикации

Reliable set operation for phase-change memory cell

Номер: US20130258768A1
Автор: Ferdinando Bedeschi
Принадлежит: Micron Technology Inc

A Phase-Change Memory (PCM) device and a method of writing data to the PCM device are described. The PCM device includes a multi-phase data storage cell having at least a Set state and a Reset state that may be established using a heater configured to heat the data storage cell. A memory interface may be coupled with the heater configured to write data to the data storage cell, the data being represented by the Set or the Reset states. A write Reset pulse is used to place the data storage cell in the Reset state corresponding to a read value that is less than a read threshold. A write Set pulse that is a predetermined function of the write Reset pulse is used to place the data storage cell in the Set state. The PCM device may include additional intermediate states that enable each data storage cell to store two or more bits of information. Other embodiments may be described and claimed.

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Номер записи: 50
21-11-2013 дата публикации

Semiconductor memory device

Номер: US20130308368A1
Автор: Hiroyuki Nagashima, Naoya Tokiwa
Принадлежит: KABUSHIKI KAISHA TOSHIBA

A semiconductor memory device comprises a plurality of memory layers arranged in multilayer, each memory layer including a cell array, the cell array containing a plurality of first parallel lines, a plurality of second parallel lines arranged crossing the first lines, and a plurality of memory cells connected at intersections of the first lines and the second lines; a pulse generator operative to generate pulses required for data access to the memory cell; and a control means operative to control the pulse generator such that the pulse output from the pulse generator has energy in accordance with the memory layer to which the access target memory cell belongs.

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Номер записи: 51
21-11-2013 дата публикации

Write control device

Номер: US20130308400A1
Автор: Byoung Chan Oh, Yoon Jae Shin
Принадлежит: SK hynix Inc

A write control device includes a switching unit configured to selectively supply a write current in response to a driving control signal, a driving unit configured to supply a driving current to a memory cell corresponding to the write current applied through the switching unit, and an over-driving control unit coupled to an output node of the driving unit and configured to over-drive the output node in response to the driving control signal.

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Номер записи: 52
21-11-2013 дата публикации

Phase change material cell with piezoelectric or ferroelectric stress inducer liner

Номер: US20130309782A1
Автор: Alejandro G. Schrott, Bipin Rajendran, Catherine A. Dubourdieu, Martin M. Frank
Принадлежит: CENTRE NATIONAL DE LA RECHERCHE SCIENTIFIQUE CNRS, International Business Machines Corp

An example embodiment disclosed is a process for fabricating a phase change memory cell. The method includes forming a bottom electrode, creating a pore in an insulating layer above the bottom electrode, depositing piezoelectric material in the pore, depositing phase change material in the pore proximate the piezoelectric material, and forming a top electrode over the phase change material. Depositing the piezoelectric material in the pore may include conforming the piezoelectric material to at least one wall defining the pore such that the piezoelectric material is deposited between the phase change material and the wall. The conformal deposition may be achieved by chemical vapor deposition (CVD) or by atomic layer deposition (ALD).

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Номер записи: 53
28-11-2013 дата публикации

Method for programming nonvolatile memory element, method for initializing nonvolatile memory element, and nonvolatile memory device

Номер: US20130314975A1
Автор: Koji Katayama, Takeshi Takagi
Принадлежит: Panasonic Corp

A method for programming a nonvolatile memory element includes: decreasing a resistance value of a variable resistance element in an initial state, by applying an initialization voltage pulse to a series circuit in which a load resistor having a first resistance value is connected in series with the variable resistance element and a MSM diode; applying, after the decreasing, a write voltage pulse to the series circuit after the resistance value of the variable resistance element is changed to a second resistance value lower than the first resistance value; and applying, after the decreasing, an erase voltage pulse to the series circuit after the resistance value of the variable resistance element is changed to a third resistance value lower than the first resistance value.

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Номер записи: 54
05-12-2013 дата публикации

Sense amplifier circuitry for resistive type memory

Номер: US20130322154A1
Автор: Adrian E. Ong, Chan-kyung Kim, Sooho Cha, YongSik Youn
Принадлежит: SAMSUNG ELECTRONICS CO LTD

Example embodiments include a resistive type memory current sense amplifier circuit including differential output terminals, first and second input terminals, pre-charge transistors, and current modulating transistors coupled directly to the pre-charge transistors. The pre-charge configuration provides high peak currents to charge the bit line and reference line during a “ready” or “pre-charge” stage of operation of the current sense amplifier circuit. The current modulating transistors are configured to operate in a saturation region mode during at least a “set” or “amplification” stage. The current modulating transistors continuously average a bit line current and a reference line current during the “set” or “amplification” stage, thereby improving noise immunity of the circuit. During a “go” or “latch” stage of operation, a logical value “0” or “1” is latched at the differential output terminals based on positive feedback of a latch circuit.

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Номер записи: 55
05-12-2013 дата публикации

Semiconductor memory device

Номер: US20130322163A1
Автор: Yoshihiro Ueda
Принадлежит: Toshiba Corp

According to one embodiment, a semiconductor memory device includes a first cell array includes memory cells and reference cells, a second cell array located adjacent to the first cell array in a first direction, a third cell array located adjacent to the first cell array in a second direction crossing the first direction, a fourth cell array located adjacent to the second cell array in the second direction, and a sense amplifier connected to the first to fourth cell array and configured to compare a current through a memory cell with a current through a reference cell to determine the data of the memory cell. A reference cell is selected from a cell array which is diagonally opposite to a cell array as a read target.

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Номер записи: 56
12-12-2013 дата публикации

Filamentary memory devices and methods

Номер: US20130329483A1
Автор: Beth R. Cook, Durai Vishak Nirmal Ramaswamy, Lei Bi, Marko Milojevic
Принадлежит: Individual

Apparatus, devices, systems, and methods are described that include filamentary memory cells. Mechanisms to substantially remove the filaments in the devices are described, so that the logical state of a memory cell that includes the that includes the removable filament can be detected. Additional apparatus, systems, and methods are described.

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Номер записи: 57
19-12-2013 дата публикации

Semiconductor memory device

Номер: US20130336044A1
Автор: Keiichi Kushida
Принадлежит: Toshiba Corp

According to one embodiment, there is provided a semiconductor memory device including a memory cell. The memory cell includes a first driving transistor, a first load transistor, a first read transfer transistor, a first write transfer transistor, a second driving transistor, a second load transistor, a second read transfer transistor, a second write transfer transistor, and one or more variable resistance elements. The one or more variable resistance elements has resistance that changes depending on a direction of a bias applied to both terminals. The one or more variable resistance elements are arranged in at least one of a portion between a first storage node and a first write transfer transistor and a portion between a second storage node and a second write transfer transistor.

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Номер записи: 58
19-12-2013 дата публикации

Nonvolatile Memory Device Using a Tunnel Nitride As A Current Limiter Element

Номер: US20130337606A1
Автор: Mihir Tendulkar, Takeshi Yamaguchi, Tim Minvielle, Yun Wang
Принадлежит: Intermolecular Inc, SanDisk 3D LLC, Toshiba Corp

Embodiments of the invention generally include a method of forming a nonvolatile memory device that contains a resistive switching memory element that has an improved device switching performance and lifetime, due to the addition of a current limiting component disposed therein. In one embodiment, the current limiting component comprises a resistive material that is configured to improve the switching performance and lifetime of the resistive switching memory element. The electrical properties of the current limiting layer are configured to lower the current flow through the variable resistance layer during the logic state programming steps (i.e., “set” and “reset” steps) by adding a fixed series resistance in the resistive switching memory element found in the nonvolatile memory device. In one embodiment, the current limiting component comprises a tunnel nitride that is a current limiting material that is disposed within a resistive switching memory element in a nonvolatile resistive switching memory device.

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Номер записи: 59
02-01-2014 дата публикации

Semiconductor memory apparatus and method of operating using the same

Номер: US20140003129A1
Автор: Kwang Myoung Rho
Принадлежит: SK hynix Inc

A semiconductor memory apparatus includes a resistive memory cell coupled between a bit line and a bit line bar; a control unit configured to couple the bit line to a first node and apply a reference voltage to a second node in response to a first sense amplifier enable signal and a second sense amplifier enable signal; a data output sense amplifier configured to sense and amplify a voltage of the first node and a voltage of the second node; a data transfer unit configured to couple the first and second nodes to a data line and a data line bar in response to a column select signal; and a data input unit configured to drive the bit line and the bit line bar according to voltage levels of the first and second nodes in response to a write enable signal.

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Номер записи: 60
30-01-2014 дата публикации

Method for driving nonvolatile memory element, and nonvolatile memory device

Номер: US20140029330A1
Автор: Satoru Mitani, Shunsaku Muraoka, Takeshi Takagi
Принадлежит: Panasonic Corp

A method for driving a nonvolatile memory element includes: a writing step of changing a variable resistance layer to a low resistance state, by applying a writing voltage pulse having a first polarity; and an erasing step of changing the variable resistance layer to a high resistance state, by applying an erasing voltage pulse having a second polarity different from the first polarity, wherein in the writing step, a first input and output terminal of a field effect transistor is a source terminal of the transistor, and when a pulse width of the writing voltage pulse is PWLR and a pulse width of the erasing voltage pulse is PWHR, PWLR and PWHR satisfy a relationship of PWLR<PWHR.

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Номер записи: 61
06-02-2014 дата публикации

Operating method for memory device and memory array and operating method for the same

Номер: US20140036570A1
Автор: Feng-Min Lee, Ming-Hsiu Lee, Yu-Yu Lin
Принадлежит: Macronix International Co Ltd

An operating method for a memory device and a memory array and an operating method for the same are provided. The operating method for the memory device comprises following steps. A memory device is made being in a set state. A method for making the memory device being in the set state comprises applying a first bias voltage to the memory device. The memory device in the set state is read. A method for reading the memory device in the set state comprises applying a second bias voltage to the memory device. A recovering bias voltage is applied to the memory device. The step for applying the recovering bias voltage is performed after the step for applying the first bias voltage or the step for applying the second bias voltage.

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Номер записи: 62
06-03-2014 дата публикации

Non-volatile memory device and method for manufacturing the same

Номер: US20140063913A1
Автор: Yoshio Kawashima, Yukio Hayakawa
Принадлежит: Panasonic Corp

A non-volatile memory device includes: a memory cell array including a plurality of memory cells each including a variable resistance element and a first current steering element; and a current steering element parameter generation circuit. The current steering element parameter generation circuit includes: a third line placed between a substrate and a second interlayer dielectric; a fourth line placed above the second interlayer dielectric; and a second current steering element which is connected between the third line and the fourth line without the variable resistance element being interposed therebetween when the variable resistance element is removed between the third line and the fourth line and has the same non-linear current steering characteristics as the first current steering element.

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Номер записи: 63
03-04-2014 дата публикации

Non-volatile resistive memory devices and methods for biasing resistive memory structures thereof

Номер: US20140092670A1
Автор: Stefan Cosemans
Принадлежит: Interuniversitair Microelektronica Centrum vzw IMEC

The disclosed technology relates to a non-volatile resistive memory device and a method of using the same. In one aspect, the memory device comprises a plurality of memory cells interconnected by a plurality of bit lines, a plurality of word lines, a plurality of source lines and a plurality of form lines. The memory device further comprises a memory controller connected to and configured to apply voltages to the bit lines, the word lines, the source lines and the form lines. In addition, each of the memory cells comprises a cell selecting transistor and a resistive memory element serially connected to a drain-source path of the cell selecting transistor. Furthermore, each of the memory cells comprises a boosting capacitor configured to provide a boosting a voltage to an internal node formed at a connection point between the resistive memory element and the cell selecting transistor.

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Номер записи: 64
03-04-2014 дата публикации

Memory device and writing method thereof

Номер: US20140092679A1
Автор: Kenji Mae, Kiyoshi Nakai, Koji Sato
Принадлежит: Elpida Memory Inc

A write amplifier for driving a bit line connected to a selected phase change memory cell drives the bit line with a first current driving capability and then drives the bit line with a second current driving capability lower than the first current driving capability.

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Номер записи: 65
06-01-2022 дата публикации

REDUCING CURRENT IN CROSSBAR ARRAY CIRCUITS WITH LARGE OUTPUT RESISTANCE

Номер: US20220005526A1
Автор: GE NING, Hu Miao
Принадлежит: TETRAMEM INC.

Methods of using large output resistance with adjusted conductance mapping value to reduce the current in crossbar array circuit are disclosed. An example method of simulating a crossbar array circuit having a crossbar array, includes steps of: S1. testing the crossbar array; S2. calibrating a simulation model; S3. simulating the crossbar array with the simulation model, wherein a simulation result is generated after the S3; S4. determining a fixed ratio of ideal current from the simulation result; S5. adjusting conductance mapping value to let the crossbar array pass the fixed ratio of ideal current and generating a conductance matrix; S6. programming the conductance matrix to the crossbar array; S7. passing an input signal to the crossbar array and generating a computing result; and S8. checking the quality of computing results. 1. A method of simulating a crossbar array circuit having a crossbar array , comprising steps of:S1. testing the crossbar array;S2. calibrating a simulation model;S3. simulating the crossbar array with the simulation model, wherein a simulation result is generated after the S3;S4. determining a fixed ratio of ideal current from the simulation result;S5. adjusting conductance mapping value to let the crossbar array pass the fixed ratio of ideal current and generating a conductance matrix;S6. programming the conductance matrix to the crossbar array;S7. passing an input signal to the crossbar array and generating a computing result; andS8. checking the quality of computing results; if the computing results are qualified, transmitting the computing results; if the computing results are not qualified, adjusting the conductance mapping value with consideration of programming errors and defects, and returning to S5.2. The method as claimed in claim 1 , wherein the crossbar array circuit further comprises:one or many of cross-point devices;{'sub': 'out', 'an output resistance Rconnected to the crossbar array; and'}an ADC configured to receive ...

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Номер записи: 66
01-01-2015 дата публикации

One-time programmable devices using junction diode as program selector for electrical fuses with extended area

Номер: US20150003143A1
Автор: Shine C. Chung
Принадлежит: Individual

Junction diodes fabricated in standard CMOS logic processes can be used as program selectors for One-Time Programmable (OTP) devices, such as electrical fuses. At least one portion of the electrical fuse can have at least one extended area to accelerate programming. An extended area is an extension of the fuse element beyond contact or via longer than required by design rules. The extended area also has reduced or substantially no current flowing through. The program selector can be at least one MOS. The OTP device can have the at least one OTP element coupled to at least one diode in a memory cell.

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Номер записи: 67
01-01-2015 дата публикации

MIXED MODE PROGRAMMING FOR PHASE CHANGE MEMORY

Номер: US20150003149A1
Автор: Bedeschi Ferdinando
Принадлежит:

Subject matter disclosed herein relates to a memory device, and more particularly to write performance of a phase change memory. 1. (canceled)2. A method , comprising:applying a voltage-regulated bias pulse to a phase change memory (PCM) cell for programming the PCM cell to a resistive state; andapplying a current-regulated bias pulse to the PCM cell for programming the PCM cell to the resistive state,wherein the PCM cell transitions to the resistive state after applying both the voltage-regulated bias pulse and the current-regulated bias pulse to the PCM cell.3. The method of claim 2 , wherein the voltage-regulated bias pulse is one of a plurality of voltage-regulated bias pulses claim 2 , further comprising applying the plurality of voltage-regulated bias pulses before applying the current-regulated bias pulse.4. The method of claim 3 , wherein applying the plurality of voltage-regulated bias pulses comprises increasing an amplitude of the voltage-regulated bias pulses during applying the plurality of voltage-regulated bias pulses.5. The method of claim 4 , further comprising applying the current-regulated bias pulse to the PCM cell in response to the voltage-regulated bias pulse reaching or exceeding a particular value.6. The method of claim 3 , wherein the current-regulated bias pulse is one of a plurality of current-regulated bias pulses claim 3 , further comprising applying the plurality of current-regulated bias pulses to transition the PCM cell to the resistive state.7. The method of claim 6 , wherein applying the plurality of current-regulated bias pulses comprises increasing an amplitude of the current-regulated bias pulses during applying the plurality of current-regulated bias pulses.8. The method of claim 2 , wherein the voltage-regulated bias pulse has a negative slope after reaching a peak amplitude.9. The method of claim 2 , wherein the current bias pulse has a negative slope after reaching a peak amplitude.10. The method of claim 2 , wherein ...

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Номер записи: 68
07-01-2021 дата публикации

NEURAL NETWORK MEMORY

Номер: US20210004174A1
Автор: Boniardi Mattia, Tortorelli Innocenzo
Принадлежит:

An example apparatus can include a memory array and a memory controller. The memory array can include a first portion including a first plurality of memory cells. The memory array can further include a second portion including a second plurality of memory cells. The memory controller can be coupled to the first portion and the second portion. The memory controller can be configured to operate the first plurality of memory cells for short-term memory operations. The memory controller can be further configured to operate the second plurality of memory cells for long-term memory operations. 1. An apparatus , comprising: a first portion comprising a first plurality of variable resistance memory cells; and', 'a second portion comprising a second plurality of variable resistance memory cells that have been degraded through forced write cycling; and, 'a memory array comprising operate the first portion for short-term memory operations; and', 'operate the second portion for long-term memory operations., 'a memory controller coupled to the first portion and the second portion, wherein the memory controller is configured to2. The apparatus of claim 1 , wherein the controller is configured to operate the first portion for short-term memory operations by applying a RESET read disturb pulse to change a conductance of any of the first plurality of variable resistance memory cells to which the RESET read disturb is applied claim 1 , wherein the conductance represents a synaptic weight or a portion of a synaptic weight.3. The apparatus of claim 1 , wherein the controller is configured to operate the first portion for short-term memory operations by performing a short SET pulse to change a conductance of any of the first plurality of variable resistance memory cells to which the short SET pulse is applied;wherein the conductance represents a synaptic weight or a portion of a synaptic weight.4. The apparatus of claim 1 , wherein the memory controller is configured to operate the ...

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Номер записи: 69
05-01-2017 дата публикации

WRITING MULTIPLE LEVELS IN A PHASE CHANGE MEMORY

Номер: US20170004884A1
Автор: Lam Chung H., LEWIS Scott C., MAFFITT Thomas M., MORRISH Jack
Принадлежит:

Structures and methods for a multi-bit phase change memory are disclosed herein. A method includes establishing a write-reference voltage that incrementally ramps over a write period. The increments of the write-reference voltage correspond to discrete resistance states of a storage cell of the multi-bit phase change memory. 1. A phase change memory system comprising:a write head controller configured to determine a time interval of a write-reference voltage which triggers a write head; anda read head controller configured to determine a value stored at a storage cell based upon a time interval of a read-reference voltage which triggers a read head, the read head retrieves information stored in the storage cell using the read-reference voltage, and', 'the write head stores information in the storage cell using the write-reference voltage., 'wherein'}2. The system of claim 1 , wherein the read head comprises:a digital-to-analog converter that establishes the read-reference voltage; anda comparator that compares the read-reference voltage to a voltage across the storage cell.3. The system of claim 1 , wherein the write head comprises:a digital-to-analog converter that establishes the write-reference voltage; anda circuit that generates a write current based on the write-reference voltage.4. The system of claim 1 , wherein the read head and the write head are devoid of an analog-to-digital converter.5. The system of claim 1 , wherein the read head includes a sense comparator having multiple inputs and an output.6. The system of claim 5 , wherein the sense comparator is configured to change logic states from a high logic state to a low logic state when a first input and a second input are a same value or substantially the same value.7. The system of claim 6 , wherein the first input of the sense comparator receives a read-reference voltage that is ramped over a predetermined read period claim 6 , the read-reference voltage is generated by a controllable current source.8 ...

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Номер записи: 70
07-01-2016 дата публикации

Sensing a non-volatile memory device utilizing selector device holding characteristics

Номер: US20160005461A1
Автор: Hagop Nazarian, Lin Shih Liu, Sung Hyun Jo
Принадлежит: Crossbar Inc

Providing for improved sensing of non-volatile resistive memory to achieve higher sensing margins, is described herein. The sensing can leverage current-voltage characteristics of a volatile selector device within the resistive memory. A disclosed sensing process can comprise activating the selector device with an activation voltage, and then lowering the activation voltage to a holding voltage at which the selector device deactivates for an off-state memory cell, but remains active for an on-state memory cell. Accordingly, very high on-off ratio characteristics of the selector device can be employed for sensing the resistive memory, providing sensing margins not previously achievable for non-volatile memory.

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Номер записи: 71
13-01-2022 дата публикации

APPARATUSES AND METHODS INCLUDING MEMORY AND OPERATION OF SAME

Номер: US20220013173A1
Автор: Papagianni Christina, Tang Stephen, Tortorelli Innocenzo
Принадлежит: MICRON TECHNOLOGY, INC.

Disclosed herein is a memory cell. The memory cell may act both as a combined selector device and memory element. The memory cell may be programmed by applying write pulses having different polarities. Different polarities of the write pulses may program different logic states into the memory cell. The memory cell may be read by read pulses all having the same polarity. The logic state of the memory cell may be detected by observing different threshold voltages when the read pulses are applied. The different threshold voltages may be responsive to the different polarities of the write pulses. 1. A method comprising:applying a write pulse having a first polarity or a second polarity to a memory cell comprising a layer configured to act as a selector device and a memory element, wherein a first state is written to the memory cell when the write pulse has the first polarity and a second state is written to the memory cell when the write pulse has the second polarity; andapplying a read pulse having the first polarity to the memory cell, wherein a magnitude of the read pulse is between a first threshold voltage of the memory cell in the first state and a second threshold voltage of the memory cell in the second state.2. The method of claim 1 , further comprising sensing a current through the memory cell.3. The method of claim 2 , further comprising determining that the memory cell is in the first state or the second state based on a magnitude of the current sensed.4. The method of claim 3 , wherein the memory cell is determined to be in the second state if the magnitude is below a threshold current and the memory cell is determined to be in the first logic state when the magnitude through the memory cell is equal to or above the threshold current.5. The method of claim 1 , wherein the read pulse has a magnitude less than a magnitude of the write pulse.6. The method of claim 5 , wherein the magnitudes of the read pulse and the write pulse are voltage magnitudes.7. The ...

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Номер записи: 72
07-01-2021 дата публикации

NONVOLATILE MEMORY DEVICE INCLUDING TEMPERATURE COMPENSATION CIRCUIT

Номер: US20210005253A1
Автор: JANJUA BILAL AHMAD, LIM JI-HOON
Принадлежит:

A nonvolatile memory device includes a differential current driver that receives a first differential signal and a second differential signal, which are based on a temperature, and generates a first compensation current and a second compensation current corresponding to a difference value between the first and second differential signals. A current mirror circuit copies a first current, which is a sum of a reference current and the first compensation current, to generate a second current having a same value as a value of the first current and regulates the reference current depending on a difference value of the second current and the second compensation current. A trimming circuit generates a program current or a read current based on the regulated reference current. 1. A nonvolatile memory device comprising:a differential current driver configured to receive a first differential signal and a second differential signal, which are based on a temperature, and to generate a first compensation current and a second compensation current corresponding to a difference value between the first and second differential signals;a current mirror circuit configured to copy a first current, which is a sum of a reference current and the first compensation current, to generate a second current having a same value as a value of the first current and to regulate the reference current depending on a difference value of the second current and the second compensation current; anda trimming circuit configured to generate a program current or a read current based on the regulated reference current.2. The nonvolatile memory device of claim 1 , further comprising a control logic circuit configured to generate a temperature compensation magnitude signal for regulating a maximum compensation current value that is a sum of the first compensation current and the second compensation current.3. The nonvolatile memory device of claim 2 , wherein:in response to the temperature compensation magnitude ...

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Номер записи: 73
07-01-2021 дата публикации

TECHNIQUES FOR APPLYING MULTIPLE VOLTAGE PULSES TO SELECT A MEMORY CELL

Номер: US20210005254A1
Автор: Chen Jessica, Cui Mingdong, Hamada Josephine T., McCrate Joseph M., Sarpatwari Karthik
Принадлежит:

Methods, systems, and devices for memory cell selection to enable a memory device to select a targeted memory cell during a write operation are described. The memory device may apply a first pulse to a selected bit line of the targeted memory cell while applying a voltage to deselected word lines to prevent current leakage. If the targeted memory is not selected after the first pulse, the memory device may apply a second pulse to the selected bit line while applying a voltage to the deselected word lines. If the targeted memory cell is not selected following the second pulse, the memory device may apply a third pulse to the selected bit line while applying the voltage to the deselected word lines. The memory device may detect a snapback event after any of the pulses if the targeted memory cell is selected. 1. A method , comprising:applying, to a memory cell comprising a chalcogenide material, a first pulse during a selection procedure of a write operation, the first pulse having a first voltage;reducing a voltage applied to the memory cell from the first voltage to a third voltage after applying the first pulse;applying, to the memory cell based at least in part on applying the first pulse, a second pulse having a second voltage higher than the first voltage;reducing the voltage applied to the memory cell from the second voltage to the third voltage after applying the second pulse;determining that the memory cell is unselected after applying the second pulse and based at least in part on the third voltage;applying, to the memory cell based at least in part on determining that the memory cell is unselected after applying the second pulse, a third pulse having the second voltage; andselecting the memory cell for the write operation based at least in part on applying the first pulse, the second pulse, and the third pulse to the memory cell.2. The method of claim 1 , wherein determining that the memory cell is unselected further comprises:determining whether a snap back ...

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Номер записи: 74
07-01-2021 дата публикации

RESISTIVE MEMORY APPARATUS AND METHOD FOR WRITING DATA THEREOF

Номер: US20210005255A1
Автор: Chao He-Hsuan, Hattori Norio, Hung Chih-Hua, Lim Seow Fong, Wang Ping-Kun, Wu Chien-Min
Принадлежит: WINBOND ELECTRONICS CORP.

A resistive memory and a method for writing data thereof are provided. The method for writing data includes: receiving a write-in data and generating an inverted write-in data; reading a current data in a plurality of selected memory cells; comparing the current data with the write-in data and the inverted write-in data; selecting the write-in data or the inverted write-in data to generate a final data according to a comparison result; and writing the final data into the selected memory cells. 1. A method for writing data of a resistive memory , comprising:receiving a write-in data and generating an inverted write-in data;reading a current data in a plurality of selected memory cells;comparing the current data with the write-in data and the inverted write-in data;selecting the write-in data Or the inverted write-in data to generate a final data according to a comparison result;generating the final data by setting a special data flag to a third logic value when the write-in data is a first special data or a second special data or when the resistive memory receives an erase command; andwriting the final data into the selected memory cells.2. The method for writing data according to claim 1 , further comprising:setting a data inverting flag to a first logic value when the write-in data is selected as the final data; andselecting the data inverting flag to a second logic value when the inverted write-in data is selected as the final data.3. (canceled)4. The method for writing data according to claim 2 , comprising:generating the final data by setting the data inverting flag to the first logic value and setting a special data flag to a third logic value when the write-in data is a first special data; andgenerating the final data by setting the data inverting flag to the second logic value and setting the special data flag to the third logic value when the write-in data is a second special data.5. The method for writing data according to claim 2 , wherein the step of ...

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Номер записи: 75
07-01-2021 дата публикации

METAL FILAMENT RERAM CELL WITH CURRENT LIMITING DURING PROGRAM AND ERASE

Номер: US20210005256A1
Автор: McCollum John L., Xue Fengliang
Принадлежит: Microchip Technology Inc.

A ReRAM memory cell includes a ReRAM element, a programming circuit coupled to the ReRAM element and defining a programming circuit path in the ReRAM memory cell, and an erase circuit coupled to the ReRAM element and defining an erase circuit path in the ReRAM memory cell. The programming circuit path is separate from the erase circuit path. 1. A ReRAM memory cell for use in a memory array , the ReRAM memory cell comprising:a ReRAM element having a first terminal and a second terminal, the first terminal connected to an ion-source electrode in the ReRAM element and coupled to a row power line in a row of the memory array;a programming circuit coupled to the ReRAM element and defining a programming circuit path in the ReRAM memory cell, the programming circuit including an n-channel transistor coupled between the second terminal of the ReRAM element and a first column bit line in a column of the memory array, the n-channel transistor having a gate coupled to an n-word line in the row of the memory array; andan erase circuit coupled to the ReRAM element and defining an erase circuit path in the ReRAM memory cell, the erase circuit including a p-channel transistor coupled between the second terminal of the ReRAM element and a second column bit line in the column in the memory array, the p-channel transistor having a gate coupled to a p-word line in the row of the memory array.2. (canceled)3. (canceled)4. A ReRAM memory cell for use in a memory array , the ReRAM memory cell comprising:a ReRAM element having a first terminal and a second terminal, the first terminal connected to an ion-source electrode in the ReRAM element;a programming circuit coupled to the ReRAM element and defining a programming circuit path in the ReRAM memory cell, the programming circuit including a p-channel programming transistor coupled between the first terminal of the ReRAM element and a first column bit line in a column of the memory array, the p-channel programming transistor having a gate ...

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Номер записи: 76
07-01-2021 дата публикации

Techniques for programming a memory cell

Номер: US20210005257A1
Автор: Agostino Pirovano, Fabio Pellizzer, Hernan A. Castro, Innocenzo Tortorelli
Принадлежит: Micron Technology Inc

Techniques are provided for programming a self-selecting memory cell that stores a first logic state. To program the memory cell, a pulse having a first polarity may be applied to the cell, which may result in the memory cell having a reduced threshold voltage. During a duration in which the threshold voltage of the memory cell may be reduced (e.g., during a selection time), a second pulse having a second polarity (e.g., a different polarity) may be applied to the memory cell. Applying the second pulse to the memory cell may result in the memory cell storing a second logic state different than the first logic state.

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Номер записи: 77
07-01-2021 дата публикации

Memory Cells, Memory Cell Programming Methods, Memory Cell Reading Methods, Memory Cell Operating Methods, and Memory Devices

Номер: US20210005259A1
Автор: Liu Jun
Принадлежит: MICRON TECHNOLOGY, INC.

Embodiments disclosed include memory cell operating methods, memory cell programming methods, memory cell reading methods, memory cells, and memory devices. In one embodiment, a memory cell includes a wordline, a first bitline, a second bitline, and a memory element. The memory element is electrically connected to the wordline and selectively electrically connected to the first bitline and the second bitline. The memory element stores information via a resistive state of the memory element. The memory cell is configured to convey the resistive state of the memory element via either a first current flowing from the first bitline through the memory element to the wordline or a second current flowing from the wordline through the memory element to the second bitline. 1. A memory cell comprising:a wordline;a first bitline;a second bitline; anda memory element electrically connected to the wordline and selectively electrically connected to the first bitline and to the second bitline, the memory element storing information via a resistive state of the memory element;wherein the memory cell is configured to convey the resistive state of the memory element via either a first current flowing from the first bitline through the memory element to the wordline or a second current flowing from the wordline through the memory element to the second bitline.2. The memory cell of wherein:the memory cell further comprises a first diode and a second diode;the memory element comprises a first electrode connected to the first bitline via the first diode and to the second bitline via the second diode and a second electrode connected to the wordline; andthe memory element is electrically connected to the first bitline via the first diode when the first diode is forward biased and is electrically disconnected from the first bitline when the first diode is not forward biased; andthe memory element is electrically connected to the second bitline via the second diode when the second diode is ...

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Номер записи: 78
07-01-2021 дата публикации

Operations on memory cells

Номер: US20210005263A1
Автор: Hernan A. Castro
Принадлежит: Micron Technology Inc

In an example, a plurality of signal pulses is applied across a plurality of memory cells concurrently until each respective memory cell reaches a desired state. Each respective memory cell is commonly coupled to a first signal line and is coupled to a different respective second signal line. Each signal pulse causes each respective memory cell to move toward the desired state by causing each respective memory cell to snap back. Current to a respective second signal line is turned off in response to each time the respective memory cell coupled thereto snaps back.

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Номер записи: 79
04-01-2018 дата публикации

Methods for Error Correction with Resistive Change Element Arrays

Номер: US20180005706A1
Автор: Sheyang NING
Принадлежит: Nantero Inc

Error correction methods for arrays of resistive change elements are disclosed. An array of resistive change elements is organized into a plurality of subsections. Each subsection includes at least one flag bit and a plurality of data bits. At the start of a write operation, all bits in a subsection are initialized. If any data bits fail to initialize, the pattern of errors is compared to the input data pattern. The flag cells are then activated to indicate the appropriate encoding pattern to apply to the input data to match the errors. The input data is then encoded according to this encoding pattern before being written to the array. A second error correction algorithm can be used to correct remaining errors. During a read operation, the encoding pattern indicated by the flag bits is used to decode the read data and retrieve the original input data.

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Номер записи: 80
02-01-2020 дата публикации

Phase change memory device with reduced read disturb and method of making the same

Номер: US20200005863A1
Автор: Michael Grobis, Ward Parkinson, Zhaoqiang BAI
Принадлежит: SanDisk Technologies LLC

A method of operating a phase change memory device includes flowing a write current of a first polarity through a phase change memory element of a selected phase change memory cell, and flowing a read current of a second polarity opposite to the first polarity through the phase change memory element of the selected phase change memory cell. A first junction between the phase change memory element and a first electrode and a second junction between the phase change memory element and a second electrode exhibit asymmetric thermoelectric heat generation during the step of flowing the write current.

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Номер записи: 81
02-01-2020 дата публикации

Memory devices and operation methods thereof

Номер: US20200005864A1
Автор: Ji-Hoon Lim, Venkataramana Gangasani
Принадлежит: SAMSUNG ELECTRONICS CO LTD

A memory device may include a memory cell array including a plurality of memory cells and a compensation resistor electrically connected to the memory cell array. The compensation resistor may generate a cell current compensating for a voltage drop generated in a parasitic resistor of a signal line connected to at least one memory cell of the plurality of memory cells. The compensation circuit may control a magnitude of resistance of a compensation resistor upon receiving an address corresponding to the memory cell. The compensation circuit may increase a magnitude of the cell current based on adjusting the magnitude of resistance of the compensation resistor to be substantially equal to a resistance value of the parasitic resistor.

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Номер записи: 82
02-01-2020 дата публикации

METHOD FOR PROGRAMMING A RESISTIVE RANDOM ACCESS MEMORY

Номер: US20200005867A1
Автор: Molas Gabriel, SASSINE Gilbert
Принадлежит:

A method for programming a resistive random access memory including a matrix of memory cells. This method includes a programming procedure that includes applying a programming voltage ramp to the memory cells of a part at least of the matrix, the programming voltage ramp starting at a first non-zero voltage value, called start voltage, and ending at a second voltage value, called stop voltage, greater in absolute value than the first voltage value. The stop voltage is determined such that each memory cell of said at least one part of the matrix has a first probability between 1/(10N) and 1/N of having a programming voltage greater in absolute value than the stop voltage (V), N being the number of memory cells in the at least one part of the matrix. 1. Method for programming a resistive random access memory comprising a matrix of memory cells , comprising a programming step that includes applying a programming voltage ramp to the memory cells of a part at least of the matrix , the programming voltage ramp starting at a start voltage having a first non-zero voltage value and ending at a stop voltage having a second voltage value greater in absolute value than the first voltage value , wherein the stop voltage is determined such that each memory cell of said at least one part of the matrix has a first probability comprised between 1/(10N) and 1/N of having a programming voltage greater in absolute value than the stop voltage , N being the number of memory cells in said at least one part of the matrix.2. The method according to claim 1 , wherein the stop voltage is determined from a distribution of programming voltages of a sample of memory cells claim 1 , said distribution obeying a normal law.3. The method according to claim 1 , wherein the start voltage is determined such that each memory cell of said at least one part of the matrix has a second probability comprised between 1/(10N) and 1/N of having a programming voltage less in absolute value than the start voltage ...

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Номер записи: 83
04-01-2018 дата публикации

ELECTRONIC COMPONENT

Номер: US20180006253A1
Автор: BORA Achyut, KIRSCH Peer, RUHL Andreas, TONG Qiong, TORNOW Marc
Принадлежит: Merck Patent GmBH

An electronic component () comprising a plurality of switching elements () which comprise, in this sequence, 1101. Electronic component () comprising a plurality of switching elements () which comprise , in this sequence ,{'b': '16', 'a first electrode (),'}{'b': '18', 'a molecular layer () bonded to a substrate, and'}{'b': '20', 'a second electrode (),'}where the molecular layer essentially consists of molecules (M) which contain a connecting group (V) and an end group (E) having a polar or ionic function.2. Electronic component according to claim 1 , where the connecting group (V) is of flexible conformation and the molecules (M) have a conformation-flexible molecular dipole moment.310. Electronic component () according to claim 1 , where the connecting group (V) is a C-C-alkylene group claim 1 , which may contain one or more functional groups and/or one or more 3-6-membered claim 1 , saturated or partially unsaturated claim 1 , alicyclic or heterocyclic rings in the chain and in which one or more H atoms may be replaced by halogen.410. Electronic component () according to claim 3 , where the connecting group (V) is a linear or branched C-C-alkylene group claim 3 , in which one or more non-adjacent CHgroups may each be replaced by —C═C— claim 3 , —CH═CH— claim 3 , —NR′— claim 3 , —O— claim 3 , —S— claim 3 , —CO— claim 3 , —CO—O— claim 3 , —O—CO— claim 3 , —O—CO—O— or a 3-6-membered claim 3 , saturated or partially unsaturated claim 3 , alicyclic or heterocyclic ring claim 3 , where N claim 3 , O and/or S are not bonded directly to one another claim 3 , in which one or more tertiary carbon atoms (CH groups) may be replaced by N and in which one or more hydrogen atoms may be replaced by halogen claim 3 , where R′ in each case claim 3 , independently of one another claim 3 , denotes H or C-C-alkyl.510. Electronic component () according to claim 4 , where the connecting group (V) is a linear or branched C-C-alkylene group claim 4 , in which one or more non-adjacent ...

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Номер записи: 84
02-01-2020 дата публикации

METHODS AND APPARATUS FOR THREE-DIMENSIONAL NON-VOLATILE MEMORY

Номер: US20200006432A1
Автор: Grobis Michael K., Stewart Derek, Terris Bruce D.
Принадлежит: SanDisk Technologies LLC

An apparatus is provided that includes a bit line above a substrate, a word line above the substrate, and a non-volatile memory cell between the bit line and the word line. The non-volatile memory cell includes a reversible resistance-switching memory element coupled in series with an isolation element. The isolation element includes a first selector element coupled in series with a second selector element. The first selector element includes a first snapback current, and the second selector element includes a second snapback current lower than the first snapback current. 1. Apparatus comprising:a bit line above a substrate;a word line above the substrate; anda non-volatile memory cell between the bit line and the word line, the non-volatile memory cell comprising a reversible resistance-switching memory element coupled in series with an isolation element, the isolation element comprises a first selector element coupled in series with a second selector element; and', 'the first selector element comprises a first snapback current, the second selector element comprises a second snapback current lower than the first snapback current., 'wherein2. The apparatus of claim 1 , wherein the first selector element comprises a first selector leakage current claim 1 , the second selector element comprises a second selector leakage current claim 1 , and the first selector leakage current is less than second selector leakage current.3. The apparatus of claim 1 , wherein the first selector element comprises a first selector leakage current claim 1 , the second selector element comprises a second selector leakage current claim 1 , the reversible resistance-switching memory element comprises a memory element leakage current claim 1 , and one of the first selector leakage current and the second selector leakage current substantially equals the memory element leakage current.4. The apparatus of claim 1 , wherein the first selector element comprises a first threshold voltage claim 1 , ...

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Номер записи: 85
03-01-2019 дата публикации

SELECT DEVICE FOR MEMORY CELL APPLICATIONS

Номер: US20190006420A1
Автор: Cardon Christopher D., Onal Caner, Wells David H.
Принадлежит:

The present disclosure includes select devices and methods of using select device for memory cell applications. An example select device includes a first electrode having a particular geometry, a semiconductor material formed on the first electrode and a second electrode having the particular geometry with formed on the semiconductor material, wherein the select device is configured to snap between resistive states in response to signals that are applied to the select device. 1. A memory cell , comprising: a first electrode having a particular geometry;', 'a first heater formed on the first electrode;', 'a semiconductor material formed on the first heater;', 'a second heater formed on the semiconductor material; and', 'a second electrode having the particular geometry formed on the second heater; and, 'a select device includinga storage element coupled in series to the select device.2. The memory cell of claim 1 , wherein a width of the semiconductor material is less than approximately 20 nanometers.3. The memory cell of claim 1 , wherein a width of the particular geometry is based on an operating voltage associated with the memory cell.4. The memory cell of claim 1 , wherein a composition of the semiconductor material is based on an operating voltage associated with the memory cell.5. The memory cell of claim 1 , wherein the select device is configured to support bi-directional current flow therethrough.6. The memory cell of claim 1 , wherein the particular geometry is a circular geometry.7. The memory cell of claim 1 , wherein the particular geometry is a quasi-square geometry.8. A memory cell claim 1 , comprising: a first heater;', 'a first electrode on the first heater;', 'a semiconductor material on the first electrode;', 'a second electrode on the semiconductor material; and', 'a second heater on the second electrode; and, 'a select device includinga storage element coupled in series to the select device.9. The memory cell of claim 8 , wherein a vacuum is ...

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Номер записи: 86
03-01-2019 дата публикации

VARIABLE RESISTANCE MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME

Номер: US20190006422A1
Автор: PARK Jong-Chul
Принадлежит: SAMSUNG ELECTRONICS CO., LTD.

A variable resistance memory device including a first conductive line extending in a first direction on a substrate, a second conductive line on the first conductive line and extending in a second direction crossing the first direction, and a memory cell pillar connected to the first conductive line and the second conductive line at a crossing point therebetween and including a heating electrode layer and a variable resistance layer in contact with the heating electrode layer such that both sidewalls of the heating electrode layer are aligned with both sidewalls of the first conductive line in the first direction. 1. A variable resistance memory device comprising:a first conductive line on a substrate, the first conductive line extending in a first direction;a second conductive line on the first conductive line, the second conductive line extending in a second direction, the second direction being a direction crossing the first direction; anda memory cell pillar connected to the first conductive line and the second conductive line at an intersection point therebetween, the memory cell pillar including a heating electrode layer and a variable resistance layer, the variable resistance layer in contact with the heating electrode layer, two opposite sidewalls of the heating electrode layer aligned with two opposite sidewalls of the first conductive line in the first direction, respectively.2. The variable resistance memory device of claim 1 , wherein the heating electrode layer is in contact with a portion of a bottom surface of the variable resistance layer in the first direction claim 1 , and is in contact with an entirety of the bottom surface of the variable resistance layer in the second direction.3. The variable resistance memory device of claim 1 , wherein the substrate includes a substrate recess portion claim 1 , the substrate recess portion being a recess formed in the substrate in a self-aligned manner with respect to the two opposite sidewalls of the first ...

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Номер записи: 87
08-01-2015 дата публикации

HIGH OPERATING SPEED RESISTIVE RANDOM ACCESS MEMORY

Номер: US20150009745A1
Автор: Nazarian Hagop, Nguyen Sang
Принадлежит:

Providing for resistive random access memory (RRAM) having high read speeds is described herein. By way of example, a RRAM memory can be powered at one terminal by a bitline, and connected at another terminal to a gate of a transistor having a low gate capacitance (relative to a capacitance of the bitline). With this arrangement, a signal applied at the bitline can quickly switch the transistor gate, in response to the RRAM memory being in a conductive state. A sensing circuit configured to measure the transistor can detect a change in current, voltage, etc., of the transistor and determine a state of the RRAM memory from the measurement. Moreover, this measurement can occur very quickly due to the low capacitance of the transistor gate, greatly improving the read speed of RRAM. 120-. (canceled)21. A method , comprising:receiving an instruction related to selection of a two-terminal memory cell of a memory device for a read operation;selecting a wordline of the memory device that is associated with the selected two-terminal memory cell;applying a read signal to a bitline of the memory device, wherein the bitline is connected to a first terminal of the two-terminal memory cell; anddetermining a state of a sensing circuit in response to applying the read signal, wherein the sensing circuit comprises a read transistor having a gate selectively connected to or disconnected from a second terminal of the two-terminal memory cell, and further wherein the state of the sensing circuit is determinative of a program or erase state of the two-terminal memory cell.22. The method of claim 21 , further comprising applying a precharge signal to the bitline during a precharge phase of the read operation claim 21 , and wherein applying the read signal further comprises applying a transitory read pulse to the bitline during an operation phase of the read operation that follows the precharge phase.23. The method of claim 21 , wherein determining the state of the sensing circuit ...

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Номер записи: 88
27-01-2022 дата публикации

Phase-change memory device having reversed phase-change characteristics and phase-change memory having highly integrated three-dimensional architecture using same

Номер: US20220029094A1
Автор: Yun Heub Song
Принадлежит: SAMSUNG ELECTRONICS CO LTD

According to an embodiment, a phase-change memory device comprises: an upper electrode and a lower electrode; a phase-change layer in which a crystal state thereof is changed by heat supplied by the upper electrode and the lower electrode; and a selector which selectively switches the heat supplied by the upper electrode and the lower electrode to the phase-change layer, wherein the selector is formed of a compound which includes a transition metal in the phase-change material so as to have a high resistance when the crystalline state of the selector is crystalline and so as to have a low resistance when the crystalline state of the selector is non-crystalline.

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Номер записи: 89
12-01-2017 дата публикации

Nonvolatile memory device and method for sensing the same

Номер: US20170011796A1
Автор: Mu-hui Park
Принадлежит: SAMSUNG ELECTRONICS CO LTD

A nonvolatile memory device includes a first resistive memory cell connected to a first word line, a second resistive memory cell connected to a second word line that is different from the first word line, a clamping unit connected between a sensing node and a reference current supplying unit connected to the second resistive memory cell to supply a reference current, and a sense amplifier connected to the sensing node to sense a level change of the sensing node, wherein when the first word line is enabled, the second word line is disabled.

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Номер записи: 90
14-01-2016 дата публикации

ENHANCING NUCLEATION IN PHASE-CHANGE MEMORY CELLS

Номер: US20160012888A1
Автор: Conti Anna Maria, Fugazza Davide, Kalb Johannes A., Pellizzer Fabio, Pirovano Agostino
Принадлежит:

Various embodiments disclosed herein comprise methods and apparatuses for placing phase-change memory (PCM) cells of a memory array into a temperature regime where nucleation probability of the PCM cells is enhanced prior to applying a subsequent SET programming signal. In one embodiment, the method includes applying a nucleation signal to the PCM cells to form nucleation sites within the memory array where the nucleation signal has a non-zero rising-edge. A programming signal is subsequently applied to achieve a desired level of crystallinity within selected ones of the plurality of PCM cells. Additional methods and apparatuses are also described. 1. A method of programming a plurality of phase-change memory (PCM) cells within a memory array , the method comprising:applying a nucleation signal to the PCM cells to form nucleation sites within the memory array, the nucleation signal having a non-zero rising-edge, the non-zero rising-edge of the nucleation signal occurring over a time period longer than 10 nanoseconds; andsubsequently applying a programming signal to achieve a desired level of crystallinity within selected ones of the plurality of PCM cells.2. The method of claim 1 , wherein the nucleation signal and the programming signal are portions of the same signal with a programming signal portion having a larger amplitude than a nucleation portion of the signal.3. The method of claim 1 , wherein the nucleation signal and the programming signal are portions of the same signal with a programming signal portion having a substantially equal amplitude as a nucleation portion of the signal.4. The method of claim 1 , wherein the nucleation signal and the programming signal are separate signals.5. The method of claim 1 , further comprising adding a time-period between application of the nucleation signal and application of the programming signal.6. The method of claim 1 , wherein the non-zero rising-edge of the nucleation signal is a step-wise incremental signal.7. ...

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Номер записи: 91
14-01-2016 дата публикации

Multiple bit per cell dual-alloy gst memory elements

Номер: US20160012889A1
Автор: Daniel R. Shepard, Mac D. Apodaca
Принадлежит: HGST Inc, HGST NETHERLANDS BV

In various embodiments, a memory cell for storing two or more bits of information includes two series-connected memory storage elements composed of programmable materials having different melting points, enabling independent programming of the storage elements via different current pulses.

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Номер записи: 92
11-01-2018 дата публикации

Sense amplifier

Номер: US20180012639A1
Автор: Bal S. Sandhu, Cezary Pietrzyk, George McNeil Lattimore, Robert Campbell Aitken
Принадлежит: ARM LTD

Broadly speaking, embodiments of the present techniques provide an amplification circuit comprising a sense amplifier and at least one Correlated Electron Switch (CES) configured to provide a signal to the sense amplifier. The sense amplifier outputs an amplified version of the input signal depending on the signal provided by the CES element. The signal provided by the CES element depends on the state of the CES material. The CES element provides a stable impedance to the sense amplifier, which may improve the reliability of reading data from the bit line, and reduce the number of errors introduced during the reading.

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Номер записи: 93
11-01-2018 дата публикации

Semiconductor storage device

Номер: US20180012640A1
Автор: Kosuke Hatsuda, Yoshiaki Osada
Принадлежит: Toshiba Memory Corp

According to one embodiment, a semiconductor storage device includes a memory cell, a bit line connected to the memory cell, and a sense circuit connected to the bit line, wherein the sense circuit includes a first transistor with a first end connected to the bit line, a second transistor with a first end connected to a second end of the first transistor, a third transistor with a first end connected to the bit line, a fourth transistor with a first end connected to a second end of the third transistor, and an amplifier connected to a second end of the second transistor and to a second end of the fourth transistor.

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Номер записи: 94
11-01-2018 дата публикации

Memory cell selector and method of operating memory cell

Номер: US20180012652A1
Автор: Fei Li, Hongxin Yang, Minghua Li, Wei He, Yu Jiang
Принадлежит: Agency for Science Technology and Research Singapore

Embodiments provide a selector device for selecting a memory cell. The selector device includes a first electrode; a second electrode; and a switching layer sandwiched between the first electrode and the second electrode. The switching layer includes at least one metal rich layer and at least one chalcogenide rich layer. The metal rich layer includes at least one of a metal or a metal compound, wherein metal content of the metal rich layer is greater than 50 at. %. The chalcogenide content of the chalcogenide rich layer is greater than 50 at. %.

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Номер записи: 95
11-01-2018 дата публикации

SEMICONDUCTOR MEMORY DEVICES INCLUDING A MEMORY ARRAY AND RELATED METHOD INCORPORATING DIFFERENT BIASING SCHEMES

Номер: US20180012656A1
Автор: Liu Jun, Wells David H.
Принадлежит:

Memory devices provide a plurality of memory cells, each memory cell including a memory element and a selection device. A plurality of first (e.g., row) address lines can be adjacent (e.g., under) a first side of at least some cells of the plurality. A plurality of second (e.g., column) address lines extend across the plurality of row address lines, each column address line being adjacent (e.g., over) a second, opposing side of at least some of the cells. Control circuitry can be configured to selectively apply a read voltage or a write voltage substantially simultaneously to the address lines. Systems including such memory devices and methods of accessing a plurality of cells at least substantially simultaneously are also provided. 1. A semiconductor memory device including a memory array , comprising:address lines including a first row address line, a second row address line, a third row address line, and a fourth row address line;column address lines including a first column address line and a second column address line;a first memory cell coupled between the first column address line and the first row address line;a second memory cell coupled between the first column address line and the second row address line;a third memory cell coupled between the second column address line and the third row address line;a fourth memory cell coupled between the second column address line and the fourth row address line; anda voltage biasing system operably coupled with the row address lines and the column address lines, and configured to selectively apply voltages to the row address lines and the column address lines according to a bias scheme that causes either the first memory cell or the second memory cell to be accessed within a same clock cycle as either the third memory cell or the fourth memory cell.2. The semiconductor memory device of claim 1 , wherein each memory cell is configured as at least one of a magnetoresistive random access memory (MRAM) cell claim 1 , a ...

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Номер записи: 96
11-01-2018 дата публикации

MEMORY DEVICE

Номер: US20180013061A1
Автор: Fukumizu Hiroyuki, YAMAGUCHI Takeshi
Принадлежит: Toshiba Memory Corporation

According to one embodiment, a memory device includes a stacked body. The stacked body includes first and second electrodes, and an oxide layer provided between the first and second electrodes. The second electrode includes a semiconductor layer, and a metal-containing region including at least one of first or second metallic element and being provided between at least a portion of the semiconductor layer and at least a portion of the oxide layer. The first metallic element includes at least one selected from Pt, Pd, Ir, Ru, Re, and Os. The second metallic element includes at least one selected Ti, W, Mo, and Ta. The stacked body has first and second states. The first state is obtained by causing a current to flow in the stacked body from the second toward first electrode. The second state is obtained by causing a current to flow from the first toward second electrode. 1. A memory device , comprising: a first electrode,', 'a second electrode, and', 'an oxide layer provided between the first electrode and the second electrode,, 'a stacked body including'} a semiconductor layer of an n-type, and', 'a metal-containing region including at least one of a first metallic element or a second metallic element and being provided between at least a portion of the semiconductor layer and at least a portion of the oxide layer,, 'the second electrode including'}the first metallic element including at least one selected from the group consisting of Pt, Pd, Ir, Ru, Re, and Os,the second metallic element including at least one selected from the group consisting of Ti, W, Mo, and Ta,the stacked body having a first state and a second state, the first state being obtained by causing a first current to flow in the stacked body from the second electrode toward the first electrode, the second state being obtained by causing a second current to flow in the stacked body from the first electrode toward the second electrode,a first resistance of the stacked body in the first state being lower ...

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Номер записи: 97
11-01-2018 дата публикации

Two-Terminal Switching Devices Comprising Coated Nanotube Elements

Номер: US20180013084A1
Автор: Ghenciu Eliodor G., Kocab J. Thomas, Rueckes Thomas, Yao Thierry
Принадлежит:

An improved switching material for forming a composite article over a substrate is disclosed. A first volume of nanotubes is combined with a second volume of nanoscopic particles in a predefined ration relative to the first volume of nanotubes to form a mixture. This mixture can then be deposited over a substrate as a relatively thick composite article via a spin coating process. The composite article may possess improved switching properties over that of a nanotube-only switching article. A method for forming substantially uniform nanoscopic particles of carbon, which contains one or more allotropes of carbon, is also disclosed. 1. A two-terminal switching device comprising:a first electrode;a second electrode; anda switching composite article disposed between and in constant electrical communication with each of said first electrode and said second electrode of said two terminal switching device, wherein said composite article is comprised of comprises a plurality of nanotube elements and a volume of nanoscopic particles;wherein said volume of nanoscopic particles is miscible with said plurality of nanotube elements and forms a continuous material around at least one of said nanotube elements.2. The two-terminal switching device of wherein substantially all of said nanotube elements are coated in a continuous material formed from said nanoscopic particles.3. The two-terminal switching device of wherein said continuous material coating increases the distance between said nanotube elements within said composite article.4. The two-terminal switching device of wherein said continuous material coating improves the switching functionality of said two-terminal switching device.5. The two-terminal switching device of wherein said volume of nanoscopic particles includes silicon oxide particles.6. The two-terminal switching device of wherein said volume of nanoscopic particles includes silicon nitride particles.7. The two-terminal switching device of wherein said nanotube ...

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Номер записи: 98
10-01-2019 дата публикации

Transient Sensing of Memory Cells

Номер: US20190013056A1
Автор: Nobunaga Dean K.
Принадлежит:

The present invention is directed to a method for sensing the resistance state of a memory cell, which includes a memory element and a selection transistor coupled in series between first and second conductive lines. The method includes the steps of precharging the first conductive line; allowing the voltage of the first conductive line to decay toward zero by discharging through the second conductive line; measuring the voltage of the first conductive line after a discharge period to determine the resistance state of the memory cell; concluding that the memory cell is in the high resistance state if the measured voltage is greater than a reference level; and concluding that the memory cell is in the low resistance state if the measured voltage is less than the reference level. The discharge period is shorter than a time period required for the voltage of the first conductive line to reach zero. 1. A method for sensing a resistance state of a memory cell , which includes a memory element and a transistor coupled in series between first and second conductive lines , the method comprising the steps of:precharging at least the first conductive line to a first voltage;allowing a voltage of the first conductive line to decay by discharging through the second conductive line;measuring the voltage of the first conductive line after a discharge period to determine the resistance state of the memory cell;concluding that the memory cell is in a high resistance state if the measured voltage is greater than a reference level; andconcluding that the memory cell is in a low resistance state if the measured voltage is less than the reference level,wherein the discharge period is shorter than a time period required for the voltage of the first conductive line to reach zero when the memory cell is in the high resistance state.2. The method of claim 1 , wherein the first conductive line has a higher precharged potential than the second conductive line.3. The method of claim 1 , ...

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Номер записи: 99
10-01-2019 дата публикации

Apparatuses, devices and methods for sensing a snapback event in a circuit

Номер: US20190013067A1
Автор: Hernan A. Castro, Jeremy Miles Hirst, Stephen Tang
Принадлежит: Micron Technology Inc

Example subject matter disclosed herein relates to apparatuses and/or devices, and/or various methods for use therein, in which an application of an electric potential to a circuit may be initiated and subsequently changed in response to a determination that a snapback event has occurred in a circuit. For example, a circuit may comprise a memory cell that may experience a snapback event as a result of an applied electric potential. In certain example implementations, a sense circuit may be provided which is responsive to a snapback event occurring in a memory cell to generate a feed back signal to initiate a change in an electric potential applied to the memory cell.

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Номер записи: 100