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Небесная энциклопедия

Космические корабли и станции, автоматические КА и методы их проектирования, бортовые комплексы управления, системы и средства жизнеобеспечения, особенности технологии производства ракетно-космических систем

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Мониторинг СМИ

Мониторинг СМИ и социальных сетей. Сканирование интернета, новостных сайтов, специализированных контентных площадок на базе мессенджеров. Гибкие настройки фильтров и первоначальных источников.

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Применить Всего найдено 10445. Отображено 100.
19-01-2012 дата публикации

Semiconductor memory device and test method thereof

Номер: US20120014189A1
Автор: Chan-sub Jun, Hyong-yong Lee
Принадлежит: Individual

Example embodiments disclose a semiconductor memory device and a test method thereof. The semiconductor memory device includes a memory cell array that provides first and second data groups at a first data rate and an output circuit, in a normal mode of operation, serially outputs the first and second data groups at a first data rate on an external terminal. In a test mode of operation, the output circuit outputs the first data group or the second data group at a second data rate on the external terminal in response to control signals, without switching the test mode. The second data rate may be lower than the first data rate.

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Номер записи: 1
16-02-2012 дата публикации

Semiconductor integrated circuit with multi test

Номер: US20120039137A1
Автор: Jong Won Lee, Shin Ho Chu
Принадлежит: Hynix Semiconductor Inc

A semiconductor integrated circuit includes a multi-mode control signal generating unit configured to control an activation of a up/down mat I/O switch control signal, which controls I/O switches in a up/down mat, according to a multi-test mode signal and a read/write discriminating signal, a multi-mode decoder configured to output multi-mat select signals to simultaneously activate a plurality of mats according to a multi-test mode active write signal, and a mat controller configured to enable word lines and the I/O switches according to the up/down mat I/O switch control signal and the multi-mat select signals.

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Номер записи: 2
22-03-2012 дата публикации

On-Chip Memory Testing

Номер: US20120072790A1
Автор: Daniel Robert Burggraf, III, Hari Pendurty
Принадлежит: Texas Instruments Inc

An integrated circuit is described that has a substrate with a memory array with dedicated support hardware formed on the substrate. An access wrapper circuit is coupled to address and data lines of the memory array and to control lines of the dedicated support hardware. The wrapper circuit is configured to provide an access port to the memory array. A test controller is formed on the substrate and coupled in parallel with the access wrapper circuit to the address and data lines of the memory array and to the control lines of the dedicated support hardware, wherein the test controller is operable to perform a test of the memory array by manipulating control signals to the support hardware in addition to those required to write data patterns into the memory array and to read the contents of the memory array.

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Номер записи: 3
19-04-2012 дата публикации

Apparatus and methods for tuning a memory interface

Номер: US20120096218A1
Автор: Dan Shimizu, Eric Scott, Joe Macri, Sagheer Ahmad
Принадлежит: ATI TECHNOLOGIES ULC

The disclosure relates to an integrated circuit including programmable control logic configured to generate at least one data pattern sequence from a number of stored data patterns and using the generated at least one data pattern sequence to at least one of read from and write to at least one memory device. A method includes generating at least one data pattern sequence from a number of stored data patterns and writing and reading the data pattern sequence from and to a memory device.

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Номер записи: 4
10-05-2012 дата публикации

Memory card

Номер: US20120117430A1
Автор: Kui-Hyun RO, Sung-Eun YUN, Young-Jae Jung, Yun-Bo Yang
Принадлежит: SAMSUNG ELECTRONICS CO LTD

A memory card includes a memory cell, a connector, a controller, and firmware. The memory cell can switch between a plurality of states. The connector can be connected to an external device and exchange signals including commands and data with the external device. The controller exchanges signals with the connector, analyzes a received signal, and accesses the memory cell to record, retrieve or modify data based on the analysis result. The firmware is located within the controller, controls the operation of the controller, and can be set to a test mode or a user mode. When the firmware receives a test command from the external device and the firmware is set to the test mode, the firmware performs a defect test on the memory cell and transmits the result of the defect test to the external device through the connector.

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Номер записи: 5
05-07-2012 дата публикации

Semiconductor memory device, test circuit, and test operation method thereof

Номер: US20120173942A1
Автор: Bok-Moon Kang, Chang-Ho Do, Tae-Hyung Jung, Yeon-Woo Kim
Принадлежит: Hynix Semiconductor Inc

A semiconductor memory device includes a plurality of banks, each including a plurality of first memory cells and a plurality of second memory cells; a first input/output unit configured to transfer first data between the first memory cells and a plurality of first data pads; a second input/output unit configured to transfer second data between the second memory cells and a plurality of second data pads; a path selection unit configured to transfer the first data, which are input through the first data pads, to both the first and second memory cells during a test mode; and a test mode control unit configured to compare the first data of the first and second memory cells, and to control at least one of the first data pads to denote a fail status based on a comparison result, during the test mode.

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Номер записи: 6
02-08-2012 дата публикации

Locally synchronous shared bist architecture for testing embedded memories with asynchronous interfaces

Номер: US20120198291A1
Автор: Akhil Garg, Prashant Dubey, Sravan Kumar Bhaskarani
Принадлежит: STMICROELECTRONICS PVT LTD

A system and method of sharing testing components for multiple embedded memories and the memory system incorporating the same. The memory system includes multiple test controllers, multiple interface devices, a main controller, and a serial interface. The main controller is used for initializing testing of each of the dissimilar memory groups using a serial interface and local test controllers. The memory system results in reduced routing congestion and faster testing of plurality of dissimilar memories. The present disclosure further provides a programmable shared built in self testing (BIST) architecture utilizing globally asynchronous and locally synchronous (GALS) methodology for testing multiple memories. The built in self test (BIST) architecture includes a programmable master controller, multiple memory wrappers, and an interface. The interface can be a globally asynchronous and locally synchronous (GALS) interface.

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Номер записи: 7
30-08-2012 дата публикации

Test circuit, semiconductor memory apparatus using the same, and test method of the semiconductor memory apparatus

Номер: US20120218846A1
Автор: Yong Gu Kang
Принадлежит: SK hynix Inc

A test circuit of a semiconductor memory apparatus includes: a test control signal generating unit configured to enable a control signal if an active signal is enabled after a test signal is enabled, and substantially maintain the control signal in an enable state until a precharge timing signal is enabled; and a precharge control unit configured to invert the control signal to output the inverted signal as a bit line precharge signal when a preliminary bit line precharge signal is in a disable state.

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Номер записи: 8
30-08-2012 дата публикации

Embedded processor

Номер: US20120221911A1
Автор: Joe M. Jeddeloh
Принадлежит: Individual

Electronic apparatus, systems, and methods of operating and constructing the electronic apparatus and/or systems include an embedded processor disposed in a logic chip to direct, among other functions, self-testing of an electronic device structure in conjunction with a pattern buffer disposed in the logic chip, when the electronic device structure is coupled to the logic chip. Additional apparatus, systems, and methods are disclosed.

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Номер записи: 9
06-12-2012 дата публикации

Resistive memory devices and memory systems having the same

Номер: US20120307547A1
Автор: Joon Min PARK, Kwang Jin Lee
Принадлежит: SAMSUNG ELECTRONICS CO LTD

A nonvolatile memory device includes an array of resistive memory cells and a write driver, which is configured to drive a selected bit line in the array with a reset current pulse, which is responsive to a first external voltage input through a first terminal/pad of the memory device during a memory cell reset operation. The write driver is further configured to drive the selected bit line in sequence with a first set current pulse, which is responsive to the first external voltage, and a second set current pulse, which is responsive to a second external voltage input through a second terminal/pad of the memory device during a memory cell set operation.

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Номер записи: 10
13-12-2012 дата публикации

Device and method for testing semiconductor device

Номер: US20120317449A1
Автор: Jung Rae Kim
Принадлежит: SAMSUNG ELECTRONICS CO LTD

A device for testing a semiconductor memory device, the device including a code table that is configured to store at least a first received code and a second received code received via a host interface, a pattern generation engine that is configured to determine a third code based on at least one of the first and the second received codes stored in the code table and to output the third code, in response to a request to perform a test operation, received via the host interface, and a signal generation unit that is configured to generate control signals for testing the semiconductor memory device, based on the third code received from the pattern generation engine.

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Номер записи: 11
17-01-2013 дата публикации

Detecting random telegraph noise induced failures in an electronic memory

Номер: US20130019132A1
Автор: Alex Shubat, Gurgen Harutyunyan, Hayk Grigoryan, Karen Amirkhanyan, Samvel Shoukourian, Tatevik Melkumyan, Valery Vardanian, Yervant Zorian
Принадлежит: Synopsys Inc

A method and system for testing an electronic memory. The method includes subjecting the electronic memory to a first test condition of a predetermined set of test conditions. The method also includes testing functionality of the electronic memory, a first plurality of times, for the first test condition using a predetermined test algorithm. The method further includes checking availability of a second test condition from the predetermined set of test conditions if the functionality of the electronic memory is satisfactory. Further, the method includes testing the functionality of the electronic memory, a second plurality of times, for the second test condition using the predetermined test algorithm if the second test condition is available. Moreover, the method includes accepting the electronic memory for use in a product if the functionality of the electronic memory is satisfactory.

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Номер записи: 12
07-02-2013 дата публикации

Disguising test pads in a semiconductor package

Номер: US20130033284A1
Автор: Arie Frenklakh
Принадлежит: SanDisk Technologies LLC

A method of forming a semiconductor package is disclosed including disguising the test pads. Test pads are defined in the conductive pattern of the semiconductor package for allowing electrical test of the completed package. The test pads are formed in shapes such as letters or objects so that they are less recognizable as test pads.

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Номер записи: 13
07-02-2013 дата публикации

System-in package including semiconductor memory device and method for determining input/output pins of system-in package

Номер: US20130033942A1
Автор: Bok Rim KO
Принадлежит: Hynix Semiconductor Inc

A semiconductor memory device includes an internal clock generation unit configured to generate an internal clock including periodic pulses during a period of a test mode; a DQ information signal generation block configured to generate DQ information signals which are sequentially enabled, in response to the internal clock; and a data output block configured to output the DQ information signals to DQ pads during a period of the test mode.

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Номер записи: 14
28-03-2013 дата публикации

Memory apparatus

Номер: US20130077414A1
Автор: Jason Varricchione, Stephen Potvin
Принадлежит: Nanya Technology Corp

A memory apparatus includes a mimic redundant device comparator, a reference delay signal generator, and a signal comparison controller. The mimic redundant device comparator is configured to receive an input signal and to delay the input signal according to a mimic delay, so as to generate a comparison signal. The reference delay signal generator is configured to receive the input signal and to delay the input signal according to a plurality of reference delays, so as to generate a plurality of reference delay signals. The signal comparison controller is configured to receive the reference delay signals and the comparison signal. According to a time difference between the comparison signal and the reference delay signals, the signal comparison controller is configured to generate a selected signal and to generate a delay control signal according to the selected signal.

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Номер записи: 15
04-04-2013 дата публикации

Method of fabricating a memory card using sip/smt hybrid technology

Номер: US20130084677A1
Автор: Andre McKenzie, Cheemen Yu, Hem Takiar, Ning Ye, Robert C. Miller
Принадлежит: SanDisk Technologies LLC

A portable memory card formed from a multi-die assembly, and methods of fabricating same, are disclosed. One such multi-die assembly includes an LGA SiP semiconductor package and a leadframe-based SMT package both affixed to a PCB. The multi-die assembly thus formed may be encased within a standard lid to form a completed portable memory card, such as a standard SDTM card. Test pads on the LGA SiP package, used for testing operation of the package after it is fabricated, may also be used for physically and electrically coupling the LGA SiP package to the PCB.

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Номер записи: 16
04-04-2013 дата публикации

GENERIC MARCH ELEMENT BASED MEMORY BUILT-IN SELF TEST

Номер: US20130086440A1
Автор: Al-Ars Zaid, Gaydadjiev Georgi Nedeltchev, Hamdioui Said, Van de Goor Adrianus
Принадлежит: Technische Universiteit Delft

Method for testing a memory under test () including a plurality of memory cells and a Memory Built-In Self-Test Engine () connectable to a memory under test. The MBIST engine () is arranged to generate appropriate addressing and read and/or write operations to the memory under test (). The MBIST engine () is connected to a March Element Stress register (MESR) (), a generic march element register (GMER) (), and a Command Memory (). The GMER () specifies one of a set of Generic March Elements (GME), and the MESR () specifies the stress conditions to be applied. Only a few GMEs are required in order to specify most industrial algorithms. The architecture is orthogonal and modular, and all speed related information is contained in the GME. In addition, only little memory is required for the specification of the test, providing a low implementation cost, yet with a high flexibility. 114-. (canceled)15. A method for testing a memory under test comprising a plurality of memory cells , the method comprising:reading a set of GME-MBIST commands from a Command Memory, executing the set of GME-MBIST commands, which includes a test having a finite sequence of Generic March Elements (GME's), each GME being a march element comprising a finite sequence of operations applied to a memory cell in the memory under test before progressing to the next memory cell and specifying operations and generic data values of the march element, wherein the GME-MBIST commands are executed by operations on a Generic March Element Register (GMER) and a March Element Stress Register (MESR), 'the MESR specifying the stress conditions to be applied, and performing the associated GME specified by the GMER and MESR to memory cells of the memory under test,', "the GMER specifying one of a set of Generic March Elements (GME's), and"}the set of GME-MBIST commands defining a specific test comprises the commands:INIT, comprising an Opcode field, and fields for initializing the values of the parameters ...

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Номер записи: 17
25-04-2013 дата публикации

ASYNCHRONOUS MEMORY ELEMENT FOR SCANNING

Номер: US20130103993A1
Автор: Inoue Michiko, IWATA Hiroshi, Ohtake Satoshi
Принадлежит: NATIONAL UNIVERSITY CORPORATION NARA INSTITUTE OF SCIENCE AND TECHNOLOGY

A scan asynchronous memory element includes: an asynchronous memory element configured to receive an n-input; and a scan control logic circuit configured to generate an n-bit signal input and the n-input to the asynchronous memory element from a scan input. The scan control logic circuit outputs the signal input when a control signal supplied to the scan control logic circuit has a first bit pattern, the scan control logic circuit outputs the scan input when the control signal has a second bit pattern, and the scan control logic circuit outputs a bit pattern allowing the asynchronous memory element to hold a previous value when the control signal has a bit pattern other than the first and second bit patterns. 1. A scan asynchronous memory element comprising:an asynchronous memory element configured to receive an n-input, where n is an integer greater than or equal to 2; anda scan control logic circuit configured to generate the n-input to the asynchronous memory element from an n-bit signal input and a scan input, wherein the scan control logic circuit outputs the signal input when a control signal supplied to the scan control logic circuit has a first bit pattern,', 'the scan control logic circuit outputs the scan input when the control signal has a second bit pattern, and', 'the scan control logic circuit outputs a bit pattern allowing the asynchronous memory element to hold a current state when the control signal has a bit pattern other than the first and second bit patterns., 'as the n input to the asynchronous memory element,'}2. The scan asynchronous memory element of claim 1 , whereinthe asynchronous memory element includes a Muller's C-element.3. The scan asynchronous memory element of claim 2 , whereinthe control signal includes an n-bit signal, and a combinational logic circuit configured to output the control signal when the control signal has a pattern other than the first and second bit patterns, and output the scan input as an n-bit scan input when the ...

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Номер записи: 18
06-06-2013 дата публикации

Latch Based Memory Device

Номер: US20130141987A1
Автор: Aunis Julie, Kamp Winfried, Koeppe Siegmar
Принадлежит: INFINEON TECHNOLOGIES AG

A method of testing a latch based memory device is disclosed. The latch based memory device includes a number of latches, electrical connections and a circuit environment of the latches. A storage functionality of the latches can be tested during a first test phase while a functionality of the electrical connections and the circuit environment of the latches can be tested during a second test phase. 1. A method of testing a latch based memory device , the latch based memory device comprising a plurality of latches , electrical connections and a circuit environment of the latches , the method comprising:testing a storage functionality of the latches during a first test phase, andtesting a functionality of the electrical connections and the circuit environment of the latches during a second test phase.2. The method according to claim 1 , further comprising:connecting, in the first test phase, at least two pairs of the latches with each other so as to form a shift register chain, wherein the shift register chain is a master slave register chain in which the at least two pairs of the latches are controlled by complementary clock signals in the first test phase.3. The method according to claim 1 , further comprisingconfiguring in the second test phase at least part of the plurality of latches to a transparent state.4. The method according to claim 3 , further comprisingperforming, in the second test phase, a scan test for evaluating the correctness of the electrical connections and the circuit environment of the latches in terms of structure of the circuit.5. The method according to claim 1 , further comprisingproviding at least one test signal for controlling and performing the first or second test phase, wherein the test signal is on a constant predefined potential during the first or second test phase, respectively.6. The method according to claim 1 , wherein the latch based memory device comprises:the plurality latches, which include a first set of latches and a ...

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Номер записи: 19
04-07-2013 дата публикации

Boundary scan chain for stacked memory

Номер: US20130173971A1
Автор: David J. Zimmerman
Принадлежит: Individual

A boundary scan chain for stacked memory. An embodiment of a memory device includes a system element and a memory stack including one or more memory die layers, each memory die layer including input-output (I/O) cells and a boundary scan chain for the I/O cells. A boundary scan chain of a memory die layer includes a scan chain portion for each of the I/O cells, the scan chain portion for an I/O cell including a first scan logic multiplexer a scan logic latch, an input of the scan logic latch being coupled with an output of the first scan logic multiplexer, and a decoder to provide command signals to the boundary scan chain.

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Номер записи: 20
04-07-2013 дата публикации

COMPUTER MEMORY TEST STRUCTURE

Номер: US20130173974A1
Автор: Kim Sungjoon, Sul Chinsong
Принадлежит: SILICON IMAGE, INC.

A method and apparatus for a computer memory test structure. An embodiment of a method for testing of a memory board includes testing a memory of the memory board, where testing the memory including use of a built-in self-test structure to provide a first test pattern for the memory. The method further includes testing an IO (input output) interface of the memory with a host, where testing of the IO interface includes use of the built-in self-test structure to provide a second test pattern for the IO interface. 1. A method of testing a memory board comprising:testing a memory of the memory board, testing of the memory including use of a built-in self-test structure to provide a first test pattern for the memory; andtesting an IO (input output) interface of the memory with a host, testing of the IO interface including use of the built-in self-test structure to provide a second test pattern for the IO interface.2. The method of claim 1 , wherein the first test pattern complies with a protocol for the memory claim 1 , and further comprising:performing error checking for the testing of the memory by enabling detection of legal commands for the memory.3. The method of claim 2 , wherein the second test pattern does not comply with the protocol for the memory.4. The method of claim 1 , further comprising encoding a test property into the second test pattern.5. The method of claim 1 , wherein at least a portion of the built-in self-test structure is included in the memory and in the host.6. The method of claim 1 , further comprising examining a received test pattern to determine if one or more errors have occurred in the memory or the IO interface.7. The method of claim 1 , further comprising testing of memories based on checking an extracted test property of the first test pattern.8. The method of claim 1 , wherein providing the first test pattern and the second test pattern includes either: generation of test signals claim 1 , or receipt of test signals from an external ...

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Номер записи: 21
11-07-2013 дата публикации

Electrical Screening of Static Random Access Memories at Varying Locations in a Large-Scale Integrated Circuit

Номер: US20130176772A1
Автор: Wah Kit Loh, Xiaowei Deng, Yang Yi
Принадлежит: Texas Instruments Inc

A method of testing large-scale integrated circuits including multiple instances of memory arrays, and an integrated circuit structure for assisting such testing, are disclosed. In one embodiment, voltage drops due to parasitic resistance in array bias conductors are determined by extracting layout parameters, and subsequent circuit simulation that derives the voltage drops in those conductors during operation of each memory array. In another embodiment, sense lines from each memory array are selectively connected to a test sense terminal of the integrated circuit, at which the array bias voltage at each memory array is externally measured. Feedback control of the applied voltage to arrive at the desired array bias voltage can be performed.

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Номер записи: 22
01-08-2013 дата публикации

BUILT-IN SELF-TEST CIRCUIT APPLIED TO HIGH SPEED I/O PORT

Номер: US20130194876A1
Автор: Chen Chung-Ching, Chen Yu-Lin, Liu Hsian-Feng
Принадлежит: MStar Semiconductor, Inc.

A built-in self-test circuit (BIST) applied to a high speed I/O port is provided. The BIST circuit includes a detecting unit, a flag unit and a selecting unit. The detecting unit has a first input terminal for receiving a serial output signal, a second input terminal for receiving a serial enable signal, and an output terminal for generating a detection signal. The flag unit receives the detection signal and generates a flag signal. The selecting unit receives the serial output signal, the serial enable signal and the flag signal. When a reset signal is at a first level, the selecting unit transmits the serial output signal and the serial enable signal to the I/O port. When the reset signal is at a second level, the serial output signal and the serial enable signal possesses a predetermined relationship. 1. A built-in self-test (BIST) circuit for a memory controller , the memory controller comprising a core circuit and an I/O port , the core circuit outputting a reset signal , a serial output signal and a serial enable signal , the I/O port comprising an output driver , the BIST circuit comprising:a detecting unit, having a first input terminal for receiving the serial output signal, a second input terminal for receiving the serial enable signal, and an output terminal for generating a detection signala flag unit, for receiving the detection signal to generate a flag signal; anda selecting unit, for receiving the serial output signal, the serial enable signal and the flag signal;wherein, when the reset signal is at a first level, the selecting unit transmits the serial output signal and the serial enable signal to an input terminal and an enable terminal of the output driver, respectively; when the reset signal is at a second level, the serial output signal and the serial enable signal possesses a predetermined relationship, and the selecting unit transmits the flag signal to the input terminal of the output driver.2. The BIST circuit according to claim 1 , wherein ...

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Номер записи: 23
22-08-2013 дата публикации

MEMORY SYSTEM AND TEST METHOD THEREOF

Номер: US20130219235A1
Автор: OHBA Hiroyuki, Ono Nobuhiro
Принадлежит: KABUSHIKI KAISHA TOSHIBA

According to one embodiment, two memory systems each including a memory and a controller are connected via a communication line. The controller includes a testing unit that performs a self-test process on the memory, a communication unit that communicates with the counterpart controller, and a status output unit. The communication unit performs a startup synchronization process which is performed before the self-test process and a termination synchronization process which is performed after the self-test process. The testing unit obtains a comprehensive test result from the test results of the two memory systems, and the status output unit of one memory system outputs the comprehensive test result. 1. A memory system in which two storage devices each comprising a storage unit and a controller that transmits data between a host device and the storage unit are connected via a communication line so that bidirectional communication can be performed , wherein a testing unit that performs a self-test process on the storage unit connected to a subject controller;', 'a communication unit that performs communication with a counterpart controller via the communication line; and', 'a test result output unit that outputs test results of the two storage devices obtained by the testing unit,, 'the controller includesthe communication unit performs a first synchronization process making the testing unit of each of the two storage devices execute the self-test process at a predetermined point, and a second synchronization process in which a termination synchronization frame including a test result of a subject storage device is transmitted to the counterpart storage device via the communication line after the self-test process is terminated and the termination of the self-test process is synchronized between the two storage devices,the testing unit performs a comprehensive test result determination process of obtaining a comprehensive test result from the test result of the subject ...

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Номер записи: 24
29-08-2013 дата публикации

Oscillator based on a 6T SRAM for measuring the Bias Temperature Instability

Номер: US20130222071A1
Автор: Ching-Te Chuang, Hao-I Yang, Kuen-Di Lee, Ming-Chien Tsai, Ming-Hsien Tu, Nan-Chun Lien, Shyh-Jye Jou, Wei Hwang, Wei-Chiang Shih, Yi-Wei Lin
Принадлежит: National Chiao Tung University NCTU

The present invention provides an oscillator which is based on a 6T SRAM for measuring the Bias Temperature Instability. The oscillator includes a first control unit, a first inverter, a second control unit, and a second inverter. The first control unit is coupled with the first inverter. The second control unit is coupled with the second inverter. The first control unit and the second control unit is used to control the first inverter and the second inverter being selected, biased, and connected respectively, so that the NBTI and the PBTI of the SRAM can be measured separately, and the real time stability of the SRAM can be monitored immediately.

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Номер записи: 25
29-08-2013 дата публикации

Deeply pipelined integrated memory built-in self-test (bist) system and method

Номер: US20130223168A1
Автор: Gary L. Taylor, Rosalee D. Gunderson
Принадлежит: Avago Technologies Enterprise IP Singapore Pte Ltd

A memory system with integrated memory built-in self-test (BIST) circuitry has one or more pipeline registers interposed between combinational logic elements. These combinational logic elements can include write data decoding logic, memory control signal decoding logic, address counter logic, address comparison logic, data comparison logic, and next state decoding logic. Features can be included that compensate for the delay inherent in the pipeline registers.

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Номер записи: 26
19-09-2013 дата публикации

Semiconductor memory device for controlling write recovery time

Номер: US20130242679A1
Автор: Jae-Hyuk Im, Woon-Bok Lee
Принадлежит: 658868 N B Inc

A semiconductor memory device includes a CAS latency mode detecting means for outputting a CAS latency control signal in response to a CAS latency mode; and an auto-precharge control means for controlling timing of an auto-precharge operation in response to the CAS latency control signal.

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Номер записи: 27
10-10-2013 дата публикации

Semiconductor device having plural data input/output terminals

Номер: US20130265831A1
Автор: Teppei MIYAJI, Yoshinori Matsui
Принадлежит: Elpida Memory Inc

Disclosed herein is a device that includes a plurality of first terminals; a first circuit including a plurality of first nodes; a buffer circuit including a plurality of second nodes connected to the first terminals through a plurality of first interconnection lines, respectively, and a plurality of third nodes connected to the first nodes of the first circuit through a plurality of second interconnection lines, respectively; and a second circuit configured to perform at least one of first and second operations. The first operation is such that a plurality of first signals, that appear respectively on the first interconnection lines, are outputted in series, and the second operation is such that a plurality of second signals, that are supplied in series, are transferred respectively to the first interconnection lines.

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Номер записи: 28
17-10-2013 дата публикации

Read only memory (rom) with redundancy

Номер: US20130275821A1
Автор: Albert M. Chu, Daryl M. Seitzer, George M. Braceras, Kevin W. Gorman, Michael R. Ouellette, Rohit Shetty, Ronald A. Piro, Thomas W. Wyckoff
Принадлежит: International Business Machines Corp

A read only memory (ROM) with redundancy and methods of use are provided. The ROM with redundancy includes a programmable array coupled to a repair circuit having one or more redundant repairs. The one or more redundant repairs include a word address match logic block, a data I/O address, and a tri-state buffer. The word address match logic block is provided to the tri-state buffer as a control input and the data I/O address is provided to the tri-state buffer as an input. An output of the tri-state buffer of each redundant repair is provided as a first input to one or more logic devices. One or more data outputs of a ROM bit cell array is provided as a second input to a respective one of the one or more logic devices.

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Номер записи: 29
24-10-2013 дата публикации

Controller to detect malfunctioning address of memory device

Номер: US20130283110A1
Автор: Adrian E. Ong, Fan Ho
Принадлежит: RAMBUS INC

A controller including a non-volatile memory to store a repair address, and a memory control unit operatively coupled with the non-volatile memory. The memory control unit comprising a memory test function configured to detect a malfunctioning address of primary data storage elements within a memory device. The memory device being another semiconductor device separate from the controller. The memory test function configured to store the repair address in the non-volatile memory, the repair address indicating the malfunctioning address of the primary data storage element.

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Номер записи: 30
31-10-2013 дата публикации

Redundancy control circuit and memory device including the same

Номер: US20130286758A1
Автор: Byung-Chul Kim
Принадлежит: SAMSUNG ELECTRONICS CO LTD

A redundancy control circuit includes an address fuse circuit and a first circuit. The address fuse circuit includes a plurality of first fuses. Each of the first fuses is configured to be cut based on a result of comparing a number of bits of a defective input address having a first logic level with a number of bits of the defective input address having a second logic level. The address fuse circuit is configured to generate a first address using the first fuses based on a cutting operation that depends on the result of comparing. The first circuit is configured to output either the first address or a second address that is an inverted address of the first address as a repair address, wherein a logic level of each of bits of the repair address is the same as that of the defective input address.

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Номер записи: 31
14-11-2013 дата публикации

Threshold voltage measurement device

Номер: US20130301343A1
Автор: Ching-Te Chuang, Geng-Cing Lin, Jyun-Kai Chu, Kuen-Di Lee, Ming-Chien Tsai, Nan-Chun Lien, Shao-cheng WANG, Shyh-Jye Jou, Wei-Chiang Shih, Yi-Wei Lin
Принадлежит: Individual

A threshold voltage measurement device is disclosed. The device is coupled to a 6T SRAM. The SRAM comprises two inverters each coupled to a FET. Power terminals of one inverter are in a floating state; the drain and source of the FET coupled to the inverter are short-circuited. Two voltage selectors, a resistor, an amplifier and the SRAM are connected in a negative feedback way. Different bias voltages are applied to the SRAM for measuring threshold voltages of two FETs of the other inverter and the FET coupled to the other inverter. The present invention uses a single circuit to measure the threshold voltages of the three FETs without changing the physical structure of the SRAM. Thereby is accelerated the measurement and decreased the cost of the fabrication process and measurement instruments.

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Номер записи: 32
28-11-2013 дата публикации

Test mode signal generation circuit

Номер: US20130318407A1
Автор: Min su Park, Yu Ri LIM
Принадлежит: SK hynix Inc

A test mode signal generation circuit includes a pre-decoder block configured to output first and second control signals and test address signals in response to first and second address signals, and a signal generation block configured to decode the test address signals in response to the first control signal and generate first and second test mode group signals each including a plurality of test mode signals.

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Номер записи: 33
05-12-2013 дата публикации

On-chip memory testing

Номер: US20130322176A1
Автор: Daniel R. Burggraf, III, Hari Pendurty
Принадлежит: Texas Instruments Inc

An integrated circuit is described that has a substrate with a memory array with dedicated support hardware formed on the substrate. An access wrapper circuit is coupled to address and data lines of the memory array and to control lines of the dedicated support hardware. The wrapper circuit is configured to provide an access port to the memory array. A test controller is formed on the substrate and coupled in parallel with the access wrapper circuit to the address and data lines of the memory array and to the control lines of the dedicated support hardware, wherein the test controller is operable to perform a test of the memory array by manipulating control signals to the support hardware in addition to those required to write data patterns into the memory array and to read the contents of the memory array.

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Номер записи: 34
12-12-2013 дата публикации

TESTING OF NON STUCK-AT FAULTS IN MEMORY

Номер: US20130332785A1
Автор: PRAKASH SURAJ
Принадлежит: STMICROELECTRONICS INTERNATIONAL N.V.

A method for identifying non stuck-at faults in a read-only memory (ROM) includes generating a golden value of a victim cell, providing a fault-specific pattern through an aggressor cell, generating a test reading of the victim cell in response to the provided fault-specific pattern, and determining whether the ROM has at least one non stuck-at fault. The determination is based on a comparison of the golden value and the test reading of the victim cell. 1. A method for testing a read-only memory (ROM) for at least one non stuck-at fault , the method comprising:generating a golden value read from a victim cell, wherein the golden value corresponds to an uncorrupted data value of the victim cell;providing a fault-specific pattern through an aggressor cell, wherein the aggressor cell is associated with a plurality of victim cells;generating a test reading of the victim cell in response to the provided fault-specific pattern; anddetermining whether the ROM has at least one non stuck-at fault based on a comparison of the golden value and the test reading of the victim cell.2. The method as claimed in claim 1 , wherein the non stuck-at fault is at least one of an address decoder open fault claim 1 , an address decoder delay fault claim 1 , and a multiple read fault.3. The method as claimed in further comprising receiving a test signal for testing the ROM for address decoder open faults.4. The method as claimed in claim 3 , wherein the generating the golden value further comprises:obtaining a second refreshing address from a previous read sequence;generating a first refreshing address for a current read sequence based at least on the second refreshing address of the previous read sequence; andreading the victim cell of the current read sequence, wherein the victim cell is at a pre-determined distance from the aggressor cell.5. The method as claimed in claim 3 , wherein the providing comprises reading the aggressor cell.6. The method as claimed in claim 3 , wherein the ...

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Номер записи: 35
26-12-2013 дата публикации

MEMORY TESTING SUPPORT METHOD AND MEMORY TESTING SUPPORT APPARATUS

Номер: US20130346813A1
Автор: INOUE TAMORU
Принадлежит: FUJITSU LIMITED

A memory testing support method includes executing a procedure using a plurality of test patterns on a memory to be tested; recording an observation result of a current value flowing in the memory during the execution of the procedure using each of the test patterns into a storing section; and determining superiority or inferiority of the test patterns in terms of effectiveness of testing the memory based on the observation results of the test patterns recorded in the storing section. 1. A memory testing support method comprising:executing a procedure using a plurality of test patterns on a memory to be tested;recording an observation result of a current value flowing in the memory during the execution of the procedure using each of the test patterns into a storing section; anddetermining superiority or inferiority of the test patterns in terms of effectiveness of testing the memory based on the observation results of the test patterns recorded in the storing section.2. The memory testing support method as claimed in claim 1 , further comprising:selecting one of the test patterns to be used for the testing of the memory based on the determination result of superiority or inferiority; andexecuting the procedure using the selected test pattern.3. The memory testing support method as claimed in claim 1 , wherein the determining determines superiority or inferiority based on a maximum value of the current value obtained for each of the test patterns.4. The memory testing support method as claimed in claim 1 , wherein the determining determines superiority or inferiority based on magnitude of change of the current value within a predetermined time claim 1 , obtained for each of the test patterns.5. The memory testing support method as claimed in claim 1 , wherein the determining determines superiority or inferiority based on a duration during which the current value exceeds a predetermined threshold value claim 1 , obtained for each of the test patterns.6. A memory ...

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Номер записи: 36
02-01-2014 дата публикации

TEST CIRCUIT OF SEMICONDUCTOR MEMORY APPARATUS AND SEMICONDUCTOR MEMORY SYSTEM INCLUDING THE SAME

Номер: US20140006863A1
Автор: KWON Yong Kee, LEE Hyung Dong, MOON Young Suk, YANG Hyung Gyun
Принадлежит: SK HYNIX INC.

A semiconductor memory apparatus includes a test circuit configured to receive a plurality of sequentially-changing test input patterns, compress the received test input patterns at each clock signal, and output the compressed patterns as variable test data. 1. A semiconductor memory apparatus comprising a test circuit configured to receive a plurality of sequentially-changing test input patterns , compress the received test input patterns at each clock signal , and output the compressed patterns as variable test data.2. The semiconductor memory apparatus according to claim 1 , wherein claim 1 , when receiving the plurality of test input patterns claim 1 , the test circuit determines whether or not the test data set in response to the test input patterns are outputted claim 1 , thereby deciding whether or not an input path has a defect.3. The semiconductor memory apparatus according to claim 1 , wherein the test circuit comprises an input unit configured to determine whether to enable the test circuit and enter a test mode based on a received test mode signal.4. A test circuit of a semiconductor memory apparatus claim 1 , comprising:a plurality of input units configured to receive a plurality of sequentially-changing test input patterns, respectively, during a test mode; anda compression unit comprising a plurality of XOR gates configured to receive the respective test input patterns received by the input units and a plurality of registers alternately connected to the XOR gates and forming a chain structure, and configured to finally output an output signal of the register positioned at the last stage as test data.5. The test circuit according to claim 4 , wherein the input unit is configured to enable the test circuit and enter a test mode when an activated test mode signal is received.6. The test circuit according to claim 4 , wherein each of the XOR gates performs a logic operation on the received test input pattern and an output signal of the register positioned ...

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Номер записи: 37
02-01-2014 дата публикации

MEMORY AND METHOD FOR TESTING THE SAME

Номер: US20140006886A1
Автор: SONG Choung-Ki
Принадлежит: SK HYNIX INC.

A memory includes a bank including a plurality of memory cells a command decoder configured to operate in synchronization with a clock signal and activate at least one of a plurality of commands including an active command, a write command, a calibration command, and an MRS command in response to a plurality of command signals, a test decoder configured to set the memory as a test mode in response to a plurality of address signals and the MRS command, and a test controller configured to activate at least one internal test command for test operating the bank at a time point that is decided based on counting information obtained by counting a test clock signal having a higher frequency than the clock signal, when the memory is set in the test mode. 1. A memory comprising:a bank comprising a plurality of memory cells;a command decoder configured to operate in synchronization with a clock signal and activate at least one of a plurality of commands including an active command, a write command, a calibration command, and an MRS command in response to a plurality of command signals;a test decoder configured to set the memory as a test mode in response to a plurality of address signals and the MRS command; anda test controller configured to activate at least one internal test command for test operating the bank at a time point that is decided based on counting information obtained by counting a test clock signal having a higher frequency than the clock signal, when the memory is set in the test mode.2. The memory of claim 1 , wherein the at least one internal test command configured to include a test active command for activating the bank claim 1 , a test precharge command for precharging the bank and a test write command for writing data into the bank.3. The memory of claim 2 , wherein the test decoder generates at least one test time information for deciding a time point when the at least one internal test command are activated.4. The memory of claim 3 , wherein the at ...

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Номер записи: 38
09-01-2014 дата публикации

COMPUTER SYSTEM HAVING FUNCTION OF DETECTING WORKING STATE OF MEMORY BANK

Номер: US20140013044A1
Автор: TIAN BO, WU KANG
Принадлежит: HON HAI PRECISION INDUSTRY CO., LTD.

A memory bank of a computer system includes a detection unit for detecting working state of a storage chip and a register chip of the memory bank. The detection unit detects whether the storage chip and the register chip work normally and outputs detection signals to a motherboard of the computer system according to the detection of the storage chip and the register chip. The motherboard performs predetermined operations according to the detection signals, thus indicating the working state of the storage chip and the register chip. 2. The computer system according to claim 1 , wherein the detection unit comprises two detection ports claim 1 , one of the two detection ports is electronically connected to each of the data I/O ports claim 1 , and another of the two detection ports is electronically connected to the SDA port.3. The computer system according to claim 1 , wherein when the detected logic voltage of each of the data I/O ports continuously changes between a logic high level voltage and a logic low level voltage claim 1 , the detection unit determines that the storage chip works normally and outputs a first detection signal; and when the detected logic voltage of any of the data I/O ports does not change within a first predetermined period of time claim 1 , the detection module determines that the storage chip does not work normally and outputs a second detection signal.4. The computer system according to claim 1 , wherein when the detected logic voltage of the SDA port of the register chip continuously changes between a logic high level voltage and a logic low level voltage claim 1 , the detection unit determines that the register chip works normally and outputs a third detection signal to the motherboard; and when the detected logic voltage of the SDA port does not change within a second predetermined period of time claim 1 , the detection unit determines that the register chip does not work normally and outputs a fourth detection signal to the motherboard. ...

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Номер записи: 39
09-01-2014 дата публикации

GENERIC ADDRESS SCRAMBLER FOR MEMORY CIRCUIT TEST ENGINE

Номер: US20140013169A1
Автор: JOHNSON JOHN C., Kobla Darshan, Natarajan Vimal K., Zimmerman David
Принадлежит:

A generic data scrambler for a memory circuit test engine. An embodiment of a memory device includes a memory; a memory controller for the memory; a built-in self-test (BIST) circuit for the testing of the memory; and a generic data scrambler for scrambling of data according to a scrambling algorithm for the memory, where each algorithm is based on values of an address for data. The generic data scrambler includes a programmable lookup table to hold values for each possible outcome of the algorithm, the lookup table to generate a set of data factors, and a logic for combining the data with the data factors to generate scrambled data. 1. A memory device comprising:a memory;a memory controller for the memory;a built-in self-test (BIST) circuit for the testing of the memory; and a programmable lookup table to hold values for each possible outcome of the algorithm, the lookup table to generate a set of data factors, and', 'a logic for combining the data with the data factors to generate scrambled data., 'a generic data scrambler for scrambling of data according to a scrambling algorithm for the memory, each algorithm being based at least in part on values of an address for data, wherein the generic data scrambler includes2. The memory device of claim 1 , wherein the lookup table includes a register file claim 1 , values of the register file being selected based on the value of at least a portion of bits of the address.3. The memory device of claim 3 , wherein the lookup table includes a multiplexer claim 3 , the multiplexer to choose one of a plurality of sets of values of the register file based on one or more bits of the address.4. The memory device of claim 1 , wherein the algorithm is a function of the address.5. The memory device of claim 1 , wherein the BIST circuit and the generic data scrambler may be utilized with a plurality of different scrambling algorithms.6. The memory device of claim 1 , wherein the memory device is a stacked memory device includes a ...

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Номер записи: 40
16-01-2014 дата публикации

SEMICONDUCTOR MEMORY DEVICE AND METHOD OF TESTING THE SAME

Номер: US20140016416A1
Автор: KIM Kwang-Hyun
Принадлежит: SK HYNIX INC.

Provided is a semiconductor memory device in which a plurality of first and second data lines coupled to a memory cell array are alternately arranged. The semiconductor memory device includes a first write driving circuit configured to load a plurality of first write data transmitted through a plurality of third data lines into the plurality of first data lines in response to a first write enable signal; a second write driving circuit configured to load a plurality of second write data transmitted through a plurality of fourth data lines into the plurality of second data lines in response to a second write enable signal; and a column control circuit configured to activate at least one of the first and second write enable signals during a given period, in response to a plurality of data width option modes, during a parallel test mode. 1. A semiconductor memory device comprising:a plurality of first and second data lines configured to be coupled to a memory cell array, both lines are alternately arranged;a first write driving circuit configured to load a plurality of first write data transmitted through a plurality of third data lines into the plurality of first data lines in response to a first write enable signal;a second write driving circuit configured to load a plurality of second write data transmitted through a plurality of fourth data lines into the plurality of second data lines in response to a second write enable signal; anda column control circuit configured to activate at least one of the first and second write enable signals during a given period, in response to a plurality of data width option modes, during a parallel test mode.2. The semiconductor memory device of claim 1 , wherein the column control circuit comprises:an option mode determination unit configured to generate an option mode determination signal in response to a write mode signal, a test-mode data width option mode signal, a normal-mode data width option mode signal, and a parallel test ...

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Номер записи: 41
23-01-2014 дата публикации

SEMICONDUCTOR MEMORY DEVICE HAVING RESISTIVE MEMORY CELLS AND METHOD OF TESTING THE SAME

Номер: US20140022836A1
Автор: KANG DONG-SEOK, Kang Sang-beom, Kim Hye-jin, Lee Yun-Sang, Oh Hyung-rok, PARK Chul-woo, Sohn Dong-Hyun
Принадлежит:

A semiconductor memory device includes a memory cell array, a mode register set and a test circuit. The memory cell array includes a plurality of wordlines, a plurality of bitlines, and a plurality of spin-transfer torque magneto-resistive random access memory (STT-MRAM) cells, and each STT-MRAM cell disposed in a cross area of each wordline and bitline, and the STT-MRAM cell includes a magnetic tunnel junction (MTJ) element and a cell transistor. The MTJ element includes a free layer, a barrier layer and a pinned layer. A gate of the cell transistor is coupled to a wordline, a first electrode of the cell transistor is coupled to a bitline via the MTJ element, and a second electrode of the cell transistor is coupled to a source line. The mode register set is configured to set a test mode, and the test circuit is configured to perform a test operation by using the mode register set. 1. A semiconductor memory device comprising:a memory cell array including a plurality of wordlines, a plurality of bitlines, and a plurality of spin-transfer torque magneto-resistive random access memory (STT-MRAM) cells, each STT-MRAM cell disposed in a cross area of each wordline and bitline, and the STT-MRAM cell including a magnetic tunnel junction (MTJ) element and a cell transistor, the MTJ element including a free layer, a barrier layer and a pinned layer, a gate of the cell transistor coupled to a wordline, a first electrode of the cell transistor coupled to a bitline via the MTJ element, a second electrode of the cell transistor coupled to a source line;a mode register set configured to set a test mode; anda test circuit configured to perform a test operation by using the mode register set.2. The semiconductor memory device of claim 1 , wherein the test mode includes at least one of a read leveling test mode for adjusting a skew between a clock signal and a data strobe signal claim 1 , a parallel bit test mode for detecting failed cells among the STT-MRAM cells claim 1 , and a ...

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Номер записи: 42
23-01-2014 дата публикации

MACRO AND COMMAND EXECUTION FROM MEMORY ARRAY

Номер: US20140026005A1
Автор: Louie Benjamin, Roohparvar Frankie F.
Принадлежит: MICRON TECHNOLOGY, INC.

Methods and apparatus for executing internal operations of memory devices utilizing instructions stored in the memory array of the memory device are disclosed. Decode blocks adapted to interpret instructions and data stored in the memory device are also disclosed. Methods can be used to perform internal self-test operations of the memory device by executing test procedures stored in the memory array of the memory device performing a self-test operation. 1. A method of performing an internal diagnostic for a NAND configured memory device comprising:storing data in a data cache coupled to an array of memory cells arranged in a NAND configuration, wherein the data stored in the data cache corresponds to at least one diagnostic function;performing a decode operation on the data stored in the data cache, wherein the decode operation generates a diagnostic function command for testing internal functions of the NAND configured memory device; andproviding the decoded diagnostic function command to a state machine of the NAND configured memory device adapted to perform the decoded diagnostic function command.2. The method of claim 1 , wherein the diagnostic function command comprises an instruction and an associated macro.3. The method of claim 1 , wherein storing data in the data cache comprises claim 1 , in response to a first received command signal claim 1 , performing a read operation of data corresponding to at least one internal operation function previously stored in an array of memory cells of the memory device.4. The method of claim 3 , wherein storing data in the data cache comprises loading data from input ports of the memory device in response to a second received command signal.5. The method of claim 3 , wherein the decode operation occurs in response to an end of array read signal generated by the state machine claim 3 , wherein the end of array read signal is generated upon completion of the read operation.6. The method of claim 3 , wherein performing a read ...

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Номер записи: 43
23-01-2014 дата публикации

MULTI-SITE TESTING OF COMPUTER MEMORY DEVICES AND SERIAL IO PORTS

Номер: US20140026006A1
Автор: Sul Chinsong
Принадлежит: SILICON IMAGE, INC.

A method and apparatus for multi-site testing of computer memory devices. An embodiment of a method of testing computer memory devices includes coupling multiple memory devices, each memory device having a serializer output and a deserializer input, wherein the serializer output of a first memory device is coupled with a deserializer input of one or more of the memory devices of the plurality of memory devices. The method further includes producing test signal patterns using a test generator of each memory device, serializing the test signal pattern at each memory device, and transmitting the serialized test pattern for testing of the memory devices, wherein testing of the memory devices includes a first test mode and a second test mode. 1. A memory testing apparatus comprising:an input to receive data from one or more memory devices of a plurality of memory devices, each memory device of the plurality of memory devices having a differential serializer output having first and second complementary serializer nodes and a differential deserializer input having first and second complementary deserializer nodes, wherein the first serializer node and the first deserializer node share a same sense, and the second serializer node and the second deserializer node share the same sense complementary to the first serializer and deserializer nodes, wherein the first serializer node of a first memory device is to be coupled with the first deserializer node of the first memory device, the second serializer node of the first memory device is to be coupled with the second deserializer input node of a second memory device, the first serializer node of the second memory device is to be coupled with the first deserializer node of the second memory device, and the second serializer node of the second memory device is to be coupled with the second deserializer node of the first memory device; andan error checker to check the data from the one or more memory devices for errors, the error ...

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Номер записи: 44
30-01-2014 дата публикации

Memory module and a memory test system for testing the same

Номер: US20140032984A1
Автор: Hyun-Soo Kim, Jung-Kuk Lee, Sang-Seok Kang, Woo-seop Kim
Принадлежит: SAMSUNG ELECTRONICS CO LTD

A memory module includes a first rank, a second rank and a test control unit. The first rank includes a plurality of semiconductor memory devices configured to operate in response to a first chip selection signal. The second rank includes a plurality of semiconductor memory devices configured to operate in response to a second chip selection signal. The test control unit is configured to simultaneously enable the first and second chip selection signals to test the first and second ranks in a test mode.

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Номер записи: 45
06-02-2014 дата публикации

TESTING METHOD AND SEMICONDUCTOR INTEGRATED CIRCUIT TO WHICH THE SAME METHOD IS APPLIED

Номер: US20140040686A1
Автор: Yanagida Masahiro
Принадлежит: FUJITSU LIMITED

A method includes: writing testing data to a testing target area of the memory; reading the written data; writing the readout data to a result storage area of the memory with a first data layout; and acquiring a first comparison result by reading the data written to the result storage area and comparing the readout data with check data; rewriting the data read from the testing target area of the memory to the result storage area of the memory while changing a writing destination with a second data layout different from the first data layout within the result storage area of the memory by the testing circuit; and acquiring a second comparison result by reading the rewritten data and comparing the readout data with the check data; and specifying a defective position of the memory in accordance with the first comparison result and the second comparison result. 1. A testing method by which a testing apparatus tests a memory mounted on a semiconductor integrated circuit including a testing circuit , the method comprising:writing testing data to a testing target area of the memory by the testing circuit;reading the written data from the testing target area of the memory by the testing circuit;writing the data read from the testing target area of the memory to a result storage area of the memory with a first data layout by the testing circuit;acquiring a first comparison result by reading the data written to the result storage area of the memory and comparing the readout data with check data;rewriting the data read from the testing target area of the memory to the result storage area of the memory in a way that changes a writing destination with a second data layout different from the first data layout within the result storage area of the memory by the testing circuit;acquiring a second comparison result by reading the data rewritten to the result storage area of the memory and comparing the readout data with the check data; andspecifying a defective position of the ...

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Номер записи: 46
13-02-2014 дата публикации

Semiconductor apparatus

Номер: US20140043884A1
Автор: Sang Hoon Shin, Young Ju Kim
Принадлежит: SK hynix Inc

A semiconductor apparatus includes a memory chip which includes: a memory area; a data input/output block configured to communicate with the memory area; and a data transmission/reception block configured to connect one of a plurality of channels and a pad to the data input/output block, wherein the plurality of channels are configured to input and output normal data to and from another chip, and the pad is configured to input and output test data.

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Номер записи: 47
13-02-2014 дата публикации

Solid state drive tester

Номер: US20140047286A1
Автор: Eui Won LEE, Hyo Jin Oh
Принадлежит: UniTest Inc

Disclosed is a solid state drive tester which reduces the size of the tester and easily changes a function without changing hardware (H/W) by implementing a plurality of devices for testing an SSD as one chip using a Field Programmable Gate Array (FPGA). The solid state drive tester includes: a host terminal receiving a test condition for testing a storage from a user; and a test control unit generating a test pattern corresponding to the test condition, adaptively selecting an interface according to an interface type of the storage to be tested to test the storage using the test pattern, and storing fail data generated during the test in an internal memory. The test control unit is implemented by an FPGA to reduce the size of the tester and easily change a function without hardware.

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Номер записи: 48
13-02-2014 дата публикации

SOLID STATE DRIVE TESTER

Номер: US20140047287A1
Автор: LEE Eui Won, OH Hyo Jin
Принадлежит:

Disclosed is a solid state drive tester which divides the functions of generating and comparing test pattern data and Frame Information Structure (FIS) data with each other into each other to implement the functions as separate logics, so that entire test time is decreased by reducing load of a processor. The solid state drive tester includes a host terminal for receiving a test condition for testing a storage from a user, and a test control unit creating a test pattern corresponding to the test condition, and adaptively selecting an interface according to an interface type of the storage to be tested to test the storage using the test pattern, wherein the test control unit is divided into a control module for controlling the test of the storage and a test execution module for practically executing the test in hardware to test a plurality of storages in real time. 1. A solid state drive tester comprising:a host terminal for receiving a test condition for testing a storage from a user; anda test control unit generating a test pattern corresponding to the test condition, and adaptively selecting an interface according to an interface type of the storage to be tested to test the storage using the test pattern,wherein the test control unit is divided into a control module for controlling the test of the storage and a test execution module for practically executing the test in hardware to test a plurality of storages in real time.2. The solid state drive tester of claim 1 , wherein the test control unit comprises:an embedded processor for controlling the test of the storage; anda test executing unit for generating a test pattern to test the storage, transmitting the test pattern to the storage, and determining whether a fail occurs by comparing the generated test pattern with a test pattern read out from the storage in cooperation with the embedded processor.3. The solid state drive tester of claim 2 , wherein the test control unit comprises:a communication interface ...

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Номер записи: 49
13-02-2014 дата публикации

STORAGE INTERFACE APPARATUS FOR SOLID STATE DRIVE TESTER

Номер: US20140047288A1
Автор: LEE Eui Won, OH Hyo Jin
Принадлежит:

Disclosed is a storage interface apparatus for a solid state drive (SSD) tester which allows a plurality of interfaces to share a single protocol in parts where the protocol is commonly used in a multiple interface for interfacing a storage. The storage interface apparatus for the solid state driver tester includes: a host terminal for receiving a test condition for testing a storage from a user; and a test control unit for generating a test pattern corresponding to the test condition to test the storage. The test control unit includes a storage interface unit for interfacing the storage, and the storage interface unit includes a plurality of interfaces that share a protocol in parts where the protocol is commonly used. 1. A storage interface apparatus for a solid state driver tester , the storage interface apparatus comprising:a host terminal for receiving a test condition for testing a storage from a user; anda test control unit for generating a test pattern corresponding to the test condition to test the storage,wherein the test control unit includes a storage interface unit for interfacing the storage, the storage interface unit includes a plurality of interfaces, and the interfaces share a protocol in parts where the protocol is commonly used.2. The storage interface apparatus of claim 1 , wherein the storage interface unit includes a plurality of complex interfaces to simultaneously test a plurality of storages.3. The storage interface apparatus of claim 2 , wherein each of the complex interfaces includes a serial-ATA (SATA) interface claim 2 , a serial attached SCSI (SAS) interface claim 2 , and a PCI express (PCIe) interface claim 2 , and the SATA interface claim 2 , the SAS interface claim 2 , and the PCIe interface share a link layer protocol.4. The storage interface apparatus of claim 2 , wherein each of the complex interfaces includes a serial-ATA (SATA) interface claim 2 , a serial attached SCSI (SAS) interface claim 2 , and a PCI express (PCIe) ...

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Номер записи: 50
13-02-2014 дата публикации

FAILURE DETECTION APPARATUS FOR SOLID STATE DRIVE TESTER

Номер: US20140047289A1
Автор: LEE Eui Won
Принадлежит:

Disclosed is a failure detection apparatus for a solid state driver tester, the failure detection apparatus including: a host terminal for receiving a test condition for testing a storage from a user; and a test control unit for creating a test pattern according to the test condition or creating a test pattern at random, and adaptively selecting an interface according to a type of the storage to be tested to test the storage with the test pattern. The test control unit includes a plurality of buffer memories for storing readout data of the storage, stores the readout data in the buffer memories in an interleaving manner, and endows comparison of the created test pattern and the readout data stored in the buffer memories with continuity to test the storage in real time. 1. A failure detection apparatus for a solid state driver tester , the failure detection apparatus comprising:a host terminal for receiving a test condition for testing a storage from a user; anda test control unit for creating a test pattern according to the test condition or creating a test pattern at random, and adaptively selecting an interface according to a type of the storage to be tested to test the storage with the test pattern,wherein the test control unit includes a plurality of buffer memories for storing readout data of the storage, stores the readout data in the buffer memories in an interleaving manner, and endows comparison of the created test pattern and the readout data stored in the buffer memories with continuity to test the storage in real time.2. The failure detection apparatus of claim 1 , wherein the test control unit includes:an embedded processor for controlling a test of the storage; anda test executing unit for creating a test pattern for a test of the storage in association with the embedded processor to transmit the test pattern to the storage, and reading out the test pattern stored in the storage to compare the readout test pattern with the created test pattern in real ...

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Номер записи: 51
13-02-2014 дата публикации

Error generating apparatus for solid state drive tester

Номер: US20140047290A1
Автор: Eui Won LEE, Hyo Jin Oh
Принадлежит: UniTest Inc

Disclosed is an error generating apparatus of a solid state drive tester. The error processing operation of the storage is tested by inserting errors into a specific instruction to be transmitted to the storage, and detecting the results of the error processing operation of the storage when testing the storage. The error generating apparatus includes a host terminal for receiving a test condition for a test of a storage from a user, and a test control unit for generating a test pattern according to the test condition or generating a test pattern randomly, generating error data used to test an error characteristic of the storage, and testing the storage based on the test pattern and a normal instruction or an error instruction which is formed by inserting the error data into the normal instruction.

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Номер записи: 52
20-02-2014 дата публикации

PROGRAMMING ERROR CORRECTION CODE INTO A SOLID STATE MEMORY DEVICE WITH VARYING BITS PER CELL

Номер: US20140053033A1
Автор: Hoei Jung S., Roohparvar Frankie F., SARIN Vishal
Принадлежит: MICRON TECHNOLOGY, INC.

Memory devices that, in a particular embodiment, receive and transmit analog data signals representative of bit patterns of two or more bits such as to facilitate increases in data transfer rates relative to devices communicating data signals indicative of individual bits. Programming error correction code (ECC) and metadata into such memory devices includes storing the ECC and metadata at different bit levels per cell based on an actual error rate of the cells. The ECC and metadata can be stored with the data block at a different bit level than the data block. If the area of memory in which the block of data is stored does not support the desired reliability for the ECC and metadata at a particular bit level, the ECC and metadata can be stored in other areas of the memory array at different bit levels. 1. An electronic system , comprising:a host processor;a communication bus coupled to the host processor;a bulk storage device having a bus interface for communication with the communication bus; and an array of memory cells; and', 'control circuitry coupled to the array of memory cells wherein the control circuitry is configured to calibrate a controller to a reliability of an area of the array of memory cells and change a bit level of ECC data and/or metadata programmed into the area of the array of memory cells based on the calibration and a desired level of reliability., 'a memory device, comprising2. The system of claim 1 , wherein the control circuitry is further configured to control calibration of the controller by controlling writing a first voltage to a center memory cell of the array of memory cells claim 1 , writing a second voltage to memory cells surrounding the center memory cell claim 1 , reading the center memory cell at a first time claim 1 , varying threshold voltages of the surrounding memory cells claim 1 , reading the center memory cell at a second time claim 1 , and generating a table comprising an indication of an ability of the center memory ...

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Номер записи: 53
06-03-2014 дата публикации

SYSTEMS AND METHODS FOR TESTING MEMORY

Номер: US20140068360A1
Автор: Cao Xiaoyi, Chang Sunny Lai-Ming, Chiu Eric Sin Kwok, Lai Bosco Chun Sang, ZHANG LEI, Zhou Shaodong
Принадлежит: KINGTIGER TECHNOLOGY (CANADA) INC.

Embodiments of systems and methods for testing memory are disclosed, where memory errors are detected, and, in at least one embodiment, memory units containing errors are prevented from being accessed by applications on a computing system. 1. A method of testing a memory device within a computing system , wherein a plurality of applications are executable by at least one processor of the computing system , the method comprising:performing a first memory test on the memory device;detecting, from the first memory test, at least one error in a memory unit of the memory device; preventing at least one of the plurality of applications from accessing the memory unit;', 'performing a second memory test on the memory unit;', 'determining, from the second memory test, whether the at least one error is successfully verified; and', 'if the at least one error is successfully verified, identifying the memory unit as defective., 'in response to the detecting, performing acts to verify the at least one error comprising2. The method of claim 1 , wherein the identifying comprises recording an identification of the memory unit in a persistent memory.3. The method of claim 2 , further comprising:if the at least one error is successfully verified, recording, in association with the identification of the memory unit in the persistent memory, an indication of a number of errors detected in the memory unit.4. The method of claim 1 , wherein the memory unit comprises one of:a single memory cell of the memory device; ora memory block consisting of a plurality of memory cells of the memory device.5. The method of claim 1 , wherein performing the first memory test comprises applying a first number of test patterns claim 1 , and wherein performing the second memory test on the memory unit comprises applying a second number of test patterns claim 1 , the second number being substantially greater than the first number.6. The method of claim 1 , further comprising: 'wherein the at least one error ...

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Номер записи: 54
13-03-2014 дата публикации

CHIP CAPABLE OF IMPROVING TEST COVERAGE OF PADS AND RELATED METHOD THEREOF

Номер: US20140075251A1
Автор: Liang Ming-Cheng, Ting Kuo-Cheng, Wang Shih-Hsing
Принадлежит: ETRON TECHNOLOGY, INC.

A method capable of improving test coverage of chip pads, where the chip includes a control unit, a plurality of pads, and a storage unit, is disclosed. The storage unit includes a plurality of blocks. The method includes writing test data to a first predetermined block through a predetermined pad of the plurality of pads, controlling a first pad to read and store a predetermined datum of the test data from the first predetermined block, controlling the first pad to write the predetermined datum to a second predetermined block, reading the predetermined datum stored in the second predetermined block through the predetermined pad, and determining whether the first pad is passed. 1. A chip capable of improving test coverage of chip pads , the chip comprising:a control unit;a plurality of pads, wherein a predetermined pad of the plurality of pads is used for coupling to a probe of a probe card, and the probe card is coupled to a test machine; anda storage unit comprising a plurality of blocks;wherein the control unit controls a first pad of the plurality of pads to read and store a predetermined datum of test data from a first predetermined block, the control unit controls the first pad to write the predetermined datum to a second predetermined block of the plurality of blocks, the test machine controls the probe to read the predetermined datum stored in the second predetermined block through the predetermined pad, and the test machine determines whether the first pad is passed according to a read result.2. The chip of claim 1 , wherein the test machine further determines a leakage condition of the first pad according to the read result.3. The chip of claim 1 , wherein the storage unit is a memory array.4. The chip of claim 1 , further comprising:a plurality of off-chip units, wherein each off-chip unit is coupled to one pad of the plurality of pads; anda plurality of data path units, wherein each data path unit is coupled between one off-chip unit of the plurality of ...

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Номер записи: 55
27-03-2014 дата публикации

Method, system and apparatus for evaluation of input/output buffer circuitry

Номер: US20140089752A1
Автор: Christopher J. Nelson, David J. Zimmerman, Pete D. Vogt, Tak M. Mak
Принадлежит: Intel Corp

Techniques and mechanisms for evaluating I/O buffer circuits. In an embodiment, test rounds are performed for a device including the I/O buffer circuits, each of the test rounds comprising a respective loop-back test for each of the I/O buffer circuits. Each of the test rounds corresponds to a different respective delay between a transmit clock signal and a receive clock signal. In another embodiment, a first test round indicates a failure condition for at least one I/O buffer circuit and a second test round indicates the failure condition for each of the I/O buffer circuits. Evaluation of the I/O buffer circuits determines whether the device satisfies a test condition, where the determining is based on a difference between the delay corresponding to the first test round and the delay corresponding to the second test round.

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Номер записи: 56
03-04-2014 дата публикации

MEMORY TESTING IN A DATA PROCESSING SYSTEM

Номер: US20140095948A1
Автор: Kochar Sumeet, LI HAI QIANG, LI XIANG N., XU CHAO C.
Принадлежит: INTERNATIONAL BUSINESS MACHINES CORPORATION

In a method of memory testing in a data processing system, in response to receiving a request for a hardware memory test during boot process of the data processing system, a controller accesses a stored past memory test result. The past memory test result includes at least a first number of test loops used in a past memory test, an identification of a first test pattern, and an error that occurred in the past memory test. The controller adjusts a second number of test loops and a second test pattern to be used in the hardware memory test according to the past memory test result. The controller then performs the hardware memory test according to the adjusted second number of test loops and the second test pattern. 1. A method of memory testing in a data processing system , the method comprising:in response to receiving a request for a hardware memory test during boot process of the data processing system, a controller accessing a stored past memory test result, wherein the past memory test result includes at least a first number of test loops used in a past memory test, an identification of a first test pattern, and any error that occurred in the past memory test;the controller adjusting a second number of test loops and a second test pattern to be used in the hardware memory test according to the past memory test result ; andthe controller performing the hardware memory test according to the adjusted second number of test loops and the second test pattern.2. The method according to claim 1 , wherein the past memory test result comprises at least one of a past hardware memory test result claim 1 , a past software memory test result claim 1 , and a past runtime memory error.3. The method according to claim 1 , wherein:the adjusting includes in response to no error being present in the stored past memory test result, setting the second number of test loops for the hardware memory test to zero; andthe performing includes in response to the second number of test loops ...

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Номер записи: 57
03-04-2014 дата публикации

Method and apparatus for diagnosing a fault of a memory using interim time after execution of an application

Номер: US20140095949A1
Автор: Hiroshi Nakatani, Makoto Toko, Naoya OHNISHI, Satoru Amaki, Yoshito Sameda
Принадлежит: Toshiba Corp

An area of a memory has a diagnosis area and a non diagnosis area, with the diagnosis area divided into a plurality of Row areas which do not overlap each other, and each of the Row areas is divided into a plurality of Cell areas which do not overlap each other. A memory fault diagnostic method has a diagnostic step in a Row area to diagnose between Cell areas with respect to all the combinations of a set of Cell areas in the Row area, and a diagnostic step between Row areas to diagnose between Row areas with respect to all the combinations of a set of Row areas in the diagnosis area. A Row area size is determined to be a size in which a time of the diagnosis in a Row area becomes equal to a time of the diagnosis between Row areas.

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Номер записи: 58
10-04-2014 дата публикации

Encoding and Decoding Redundant Bits to Accommodate Memory Cells Having Stuck-At Faults

Номер: US20140101517A1
Автор: Cyril Guyot, Hessam Mahdavifar, Luiz Franca-Neto, Qingbo Wang, Robert Eugeniu Mateescu, Zvonimir Bandic
Принадлежит: HGST NETHERLANDS BV

A data storage system has a memory circuit that comprises memory cells and a control circuit that receives data bits provided for storage in the memory cells. The control circuit encodes the data bits to generate a first set of redundant bits and encoded data bits, such that the encoded data bits selected for storage in a first subset of the memory cells with first stuck-at faults have digital values of corresponding ones of the first stuck-at faults. The control circuit encodes the first set of redundant bits to generate a second set of redundant bits. The control circuit performs logic functions on the second set of redundant bits and the encoded data bits to generate a third set of redundant bits, such that redundant bits in the third set of redundant bits selected for storage in a second subset of the memory cells with second stuck-at faults have digital values of corresponding ones of the second stuck-at faults.

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Номер записи: 59
06-01-2022 дата публикации

MEMORY SYSTEM

Номер: US20220005537A1
Автор: KUROSE Kengo, SHIRAKAWA Masanobu, TOKUTOMI Tsukasa, Watanabe Kiwamu
Принадлежит: Toshiba Memory Corporation

A memory system according to an embodiment includes a semiconductor memory, and a memory controller. The semiconductor memory comprises memory cells and word lines. Each of the word lines is connected to the memory cells. The memory controller executes a patrol operation including a read operation of the semiconductor memory. The word lines are classified into one of first and second groups. The memory controller executes patrol operations in which the word lines are respectively selected in a first patrol period and, in a second patrol period subsequent to the first patrol period, executes a patrol operation in which the word line included in the first group is selected and omits a patrol operation in which the word line included in the second group is selected. 1. A memory system comprising:a semiconductor memory comprising a plurality of memory cells connected in series and a plurality of word lines, each of the plurality of word lines being connected to each of the memory cells; anda memory controller that executes a patrol operation including a read operation of the semiconductor memory,wherein the word lines are classified into one of a first group and a second group based on an address of the word line, andthe memory controller executes a plurality of patrol operations in which the word lines are respectively selected in a first patrol period and, in a second patrol period subsequent to the first patrol period, executes a patrol operation in which the word line included in the first group is selected and omits a patrol operation in which the word line included in the second group is selected.2. The memory system of claim 1 , wherein the semiconductor memory further comprises a plurality of first conductor layers stacked with an insulating layer interposed therebetween and respectively used as the word lines and a pillar penetrating through the first conductor layers claim 1 , the pillar includes a first columnar portion and a second columnar portion above the ...

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Номер записи: 60
07-01-2021 дата публикации

MEMORY SYSTEM AND METHOD OF OPERATING MEMORY SYSTEM

Номер: US20210004282A1
Автор: Kim Jong Wook
Принадлежит: SK HYNIX INC.

The present technology relates to a memory system and a method of operating the memory system. The memory system includes a memory device including a plurality of semiconductor memories, and a controller for controlling the memory device to perform a test program operation and a threshold voltage distribution monitoring operation on each of the plurality of semiconductor memories during an operation. The controller sets operation performance parameters of each of the semiconductor memories based on monitoring information obtained as a result of the threshold voltage distribution monitoring operation. 1. A memory system comprising:a memory device including a plurality of semiconductor memories; anda controller for controlling the memory device to perform a test program operation and a first threshold voltage distribution monitoring operation on each of the plurality of semiconductor memories during an operation,wherein the controller sets operation performance parameters of each of the semiconductor memories based on first monitoring information obtained as a result of the first threshold voltage distribution monitoring operation.2. The memory system of claim 1 , wherein the controller controls the memory device to perform a test erase operation and a second threshold voltage distribution monitoring operation on each of the plurality of semiconductor memories after performing the first threshold voltage distribution monitoring operation during the operation claim 1 , and sets the operation performance parameters based on second monitoring information obtained as a result of the second threshold voltage distribution monitoring operation and the first monitoring information.3. The memory system of claim 2 , wherein each of the plurality of semiconductor memories includes a plurality of memory blocks claim 2 , andeach of the plurality of semiconductor memories programs the plurality of memory blocks to a solid program state during the test program operation.4. The ...

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Номер записи: 61
07-01-2016 дата публикации

Semiconductor memory device and method of testing the same

Номер: US20160005445A1
Автор: Chun-Seok Jeong
Принадлежит: SK hynix Inc

A semiconductor memory device includes a row input section suitable for receiving a first row signal including a first row command and a first row address, corresponding to an active command, during a test operation of the active command, a column input section suitable for receiving a second row signal including a second row address corresponding to the active command during the test operation of the active command, and a signal control section suitable for generating an internal row signal for an operation of the active command by transforming the first row signal and the second row signal outputted from the row input section and the column input section.

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Номер записи: 62
07-01-2016 дата публикации

METHODS AND APPARATUS FOR TESTING AND REPAIRING DIGITAL MEMORY CIRCUITS

Номер: US20160005493A1
Автор: Iyer Sundar, Joshi Sanjeev, Nazar Shadab
Принадлежит:

An ActiveTest solution for memory is disclosed which can search for memory errors during the operation of a product containing digital memory. The ActiveTest system tests memory banks that are not being accessed by normal memory users in order to continually test the memory system in the background. When there is a conflict between the ActiveTest system and a memory user, the memory user is generally given priority. 1. A memory test system comprising:a set of memory banks;a pointer configured to point to a next memory bank in the set of memory banks to be tested such that said next memory bank is skipped when a memory access is currently blocking access said next memory bank;a first deficit bank pointer configured to identify a first deficit memory bank among the set of memory banks that has been skipped due to a blocking memory access; anda first deficit counter associated with said first deficit bank pointer, said first deficit counter configured to store a count of a number of times that said first deficit memory bank has been skipped for testing;wherein said first deficit memory bank identified by said first deficit bank pointer is given priority for testing over said next memory bank pointed to by said pointer when said first deficit counter is not zero.2. The memory test system as set forth in claim 1 , further comprising a memory row pointer for each memory bank in said set of memory banks.3. The memory test system as set forth in claim 1 , wherein said first deficit bank counter is decremented upon testing said first deficit memory bank identified by said first deficit bank pointer.4. The memory test system as set forth in claim 1 , wherein said pointer is incremented upon testing said next memory bank identified by said pointer.5. The memory test system as set forth in claim 1 , further comprising:a second deficit bank pointer configured to identify a second deficit memory bank that has been blocked from a recent testing attempt; anda second deficit counter ...

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Номер записи: 63
13-01-2022 дата публикации

Low latency decoder for error correcting codes

Номер: US20220013187A1
Автор: Venugopal Santhanam
Принадлежит: Synopsys Inc

A method for error correction comprises receiving data at a first device, and decoding, by decoder circuitry of the first device, the data. Decoding the data comprises determining a first error location within the data, and determining a first error magnitude within the data in parallel with determining the first error location. Decoding the data further comprises performing error correction to generate the decoded data based on the first error location and the first error magnitude. The method further comprises transmitting the decoded data to a second device.

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Номер записи: 64
13-01-2022 дата публикации

MEMORY DEVICE

Номер: US20220013188A1
Автор: Kim Sang Hwan
Принадлежит: SK HYNIX INC.

A memory device includes a first pad, a second pad, and a double data rate (DDR) test controller. The first pad may receive a write enable signal. The second pad may receive a data strobe signal. The DDR test controller is connected to the first pad and the second pad and outputs an internal write enable signal and an internal data strobe signal. The DDR test controller generates the internal data strobe signal based on the write enable signal received through the first pad, in at least a portion of a DDR test operation of the memory device. 1. A memory device comprising:a first pad capable of receiving a write enable signal;a second pad capable of receiving a data strobe signal; anda double data rate (DDR) test controller connected to the first pad and the second pad and configured to output an internal write enable signal and an internal data strobe signal,wherein the DDR test controller generates the internal data strobe signal based on the write enable signal received through the first pad, in at least a portion of a DDR test operation of the memory device.2. The memory device of claim 1 , wherein the DDR test controller outputs the write enable signal received through the first pad as the internal write enable signal claim 1 , and outputs the data strobe signal received through the second pad as the internal data strobe signal claim 1 , during a normal operation of the memory device.3. The memory device of claim 1 , wherein the DDR test controller outputs the write enable signal received through the first pad as the internal write enable signal in a period in which a command or an address is input during the DDR test operation.4. The memory device of claim 1 , wherein the DDR test controller outputs the write enable signal received through the first pad as the internal data strobe signal in a period in which data is input during the DDR test operation.5. The memory device of claim 1 , wherein the DDR test controller comprises:a multiplexer connected to the ...

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Номер записи: 65
02-01-2020 дата публикации

Efficient post programming verification in a nonvolatile memory

Номер: US20200005873A1
Автор: Dalal Meir, Sagron Itay, Shappir Assaf, Yazovitsky Eli
Принадлежит:

A storage device includes storage circuitry and multiple memory cells. The memory cells are organized in multiple memory blocks of a nonvolatile memory. The storage circuitry is configured to define a partial verification scheme that specifies testing only a data portion of the data programmed to the memory blocks, to program data to a memory block, calculate redundancy data over the data, and save the calculated redundancy data in a dedicated memory, to verify that the data portion specified for the memory block in the partial verification scheme has been programmed successfully, to check a predefined condition for conditionally performing full verification to the memory block, when the predefined condition is fulfilled, to verify that data programmed to the memory block and not tested using the partial verification scheme has been programmed successfully, and to recover, using the redundancy data, at least part of the data programmed that failed verification. 1. A storage device , comprising:multiple memory cells organized in multiple memory blocks of a nonvolatile memory; and define a partial verification scheme that specifies testing only a data portion of the data programmed to the memory blocks;', 'program data to a memory block, calculate redundancy data over the data, and save the calculated redundancy data in a dedicated memory;', 'verify that the data portion specified for the memory block in the partial verification scheme has been programmed successfully;', 'check a predefined condition for conditionally performing full verification to the memory block;', 'when the predefined condition is fulfilled, verify that data programmed to the memory block and not tested using the partial verification scheme has been programmed successfully; and', 'recover, using the redundancy data, at least part of the data programmed that failed verification., 'storage circuitry, configured to2. The storage device according to claim 1 , wherein the storage circuitry is ...

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Номер записи: 66
02-01-2020 дата публикации

Recovering from failure in programming a nonvolatile memory

Номер: US20200005874A1
Автор: Baum Barak, Ben-Yehuda Guy, Guy Roman, Mouler Stas, Sagron Itay, Shappir Assaf
Принадлежит:

A controller includes an interface and a processor. The interface is configured to communicate with a nonvolatile memory including multiple memory cells organized in multiple memory blocks that each includes multiple Word Lines (WLs). The processor is configured to store first data in one or more WLs of a memory block, the first data occupies less than a maximal number of WLs available in the memory block, to calculate redundancy data over the first data and store the redundancy data in a dedicated memory, to program second data to a selected WL of the memory block that was not programmed with the first data, to check a programming status resulting from the programming of the selected WL, and in response to identifying that programming the second data to the selected WL has corrupted at least part of the first data, to recover the first data using the redundancy data. 1. A controller , comprising:an interface, which is configured to communicate with a nonvolatile memory comprising multiple memory cells organized in multiple memory blocks, wherein each memory block comprises multiple Word Lines (WLs) of the memory cells; and receive first data, and store the first data in one or more WLs of a given memory block, wherein the first data occupies less than a maximal number of WLs available in the given memory block;', 'calculate redundancy data over the first data, and store the redundancy data in a dedicated memory;', 'receive second data and program the second data to a selected WL of the given memory block that was not programmed with the first data;', 'check a programming status resulting from the programming of the selected WL; and', 'in response to identifying that programming the second data to the selected WL has corrupted at least part of the first data, recover the first data using the redundancy data., 'a processor, configured to2. The controller according to claim 1 , wherein in response to identifying that the second data has been programmed successfully ...

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Номер записи: 67
02-01-2020 дата публикации

SIMULTANEOUS SCAN CHAIN INITIALIZATION WITH DISPARATE LATCHES

Номер: US20200005883A1
Автор: Agrawal Mitesh, GEUKES BENEDIKT, MONDAL Krishnendu
Принадлежит:

Provided is an integrated circuit that includes a reset electrically connected to a select line of a multiplexer and an OR gate. The multiplexer receives data from a power source. The multiplexer and the OR gate comprise a circuit. A clock is electrically connected to the OR gate. The OR gate is electrically connected to a clock input of a latch. The latch includes the clock input, a scan enable input, a data input, and a data output. A regular logic data path is electrically connected to the multiplexer, and the multiplexer is further electrically connected to the data port of the latch. 1. A method , comprising:determining that an integrated circuit is in a test mode, the integrated circuit including an initialization circuit and two or more disparate latches, the initialization circuit comprising a multiplexor and an OR gate, wherein:a reset is electrically connected to a select line of the multiplexer and a first input of the OR gate,a clock is electrically connected to a second input of the OR gate,an output of the OR gate is electrically connected to a clock input of a first latch,a logic data path is electrically connected to a first input of the multiplexer, andan output of the multiplexer is connected to a data input of the first latch;enabling, in response to determining that the integrated circuit is in the test mode, a data stream to be shifted from one latch of the two or more latches to another latch of the two or more latches;setting a reset pin; andinitializing the two or more latches.2. The method of claim 1 , wherein a data output of the first latch is electrically connected to the logic data path.3. The method of claim 1 , wherein the integrated circuit is included in a clock domain.4. The method of claim 1 , wherein the multiplexor receives data from a power source5. The method of claim 1 , wherein the two or more latches are selected from the group consisting of a high-performance claim 1 , high-efficiency claim 1 , set-reset claim 1 , positive ...

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Номер записи: 68
02-01-2020 дата публикации

SYSTEM AND METHOD FOR COUNTING FAIL BIT AND READING OUT THE SAME

Номер: US20200005885A1
Автор: Benitez C. Omar, Mohr Christian N., Montierth Dennis G., Wieduwilt Christopher G., Wolff Gregg D.
Принадлежит: MICRON TECHNOLOGY, INC.

An apparatus may include a memory array, a test circuit coupled to the memory array, a counter circuit coupled to the test circuit and an input/output (I/O) circuit coupled to the counter circuit. During a test operation, the test circuit may receive blocks of data from the memory array and compare the data to detect errors in the blocks of data. The counter circuit may increment a count value in response to detection of an error by the test circuit, and the I/O circuit may provide the count value to an output. The test circuit may also provide test comparison data based on the received blocks of data, and the I/O circuit may provide one of the count value and the test comparison data to the output. 1. An apparatus comprising:a memory array;a test circuit coupled to the memory array, wherein, during a test operation, the test circuit is configured to receive blocks of data from the memory array and to detect one or more errors in the received blocks of data;a counter circuit coupled to the test circuit, wherein, during the test operation, the counter circuit is configured to update a count value in response to detection of an error by the test circuit; andan input/output (I/O) circuit coupled to the counter circuit, wherein the I/O circuit comprises a multiplexing circuit configured to provide the count value of the counter circuit to an output.2. The apparatus of claim 1 , wherein:the test-circuit is further configured to provide test comparison data based on the received blocks of data; andthe I/O-circuit is further coupled to the test circuit, wherein the multiplexing-circuit is further configured to provide at least one of the count value of the counter circuit or at least a portion of the test comparison data to the output.3. (canceled)4. The apparatus of claim 2 , wherein the I/O circuit is configured to provide the count value and the portion of the test comparison data to a test device.5. The apparatus of further comprising a data path comprising a multi- ...

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Номер записи: 69
03-01-2019 дата публикации

APPARATUS FOR MEMORY DEVICE TESTING AND FIELD APPLICATIONS

Номер: US20190006022A1
Автор: NIU Baohua, YING Ji-Feng
Принадлежит: Taiwan Semiconductor Manufacturing Co, Ltd.

A memory test system is disclosed that includes a memory integrated circuit (IC) and a memory functional tester. The memory IC includes a plurality of memory banks, where each memory bank includes a plurality of memory cells. The memory functional tester includes an adjustable voltage generator circuit, a read current measurement circuit, and a controller. The memory functional tester performs a write/read functional test on the memory bank over a number of write control voltages to determine a preferred write control voltage, where the preferred write control voltage is designated for use during subsequent write operations to the memory bank during an operational mode. 1. A memory functional tester to perform a write/read functional test on a plurality of memory cells , the memory functional tester , comprising:an adjustable voltage generator circuit configured to generate each write control voltage of a plurality of write control voltages to store first and second logic states in the plurality of memory cells during respective first and second write cycles of the write/read functional test; 'measure first and second sets of read currents that define first and second sets of read current distributions associated with the each write control voltage of the plurality of write control voltages, wherein the first read current distribution represents the first logic state stored in the plurality of memory cells during the first write cycle, and the second read current distribution represents the second logic state stored in the plurality of memory cells during the second write cycle;', 'a read current measurement circuit configured to determine a number error currents that fall outside the first and second read current distributions associated with the each write control voltage of the plurality of write control voltages;', 'determine an error rate associated with the each write control voltage based on the corresponding number of error currents associated with the each ...

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Номер записи: 70
03-01-2019 дата публикации

SEMICONDUCTOR DEVICE, SEMICONDUCTOR MEMORY AND METHOD FOR TESTING RELIABILITY OF SEMICONDUCTOR DEVICE

Номер: US20190006023A1
Автор: Sugahara Takahiko
Принадлежит: MegaChips Corporation

A memory controller performs a reliability test only on a memory array out of the memory array and a random number generator on receipt of a memory test command from a testing device while performing a reliability test only on the random number generator out of the memory array and the random number generator on receipt of a random number test command from the testing device. 1. A semiconductor device comprising:random number generator circuitry that generates a random number; andmemory controller circuitry connected to the random number generator circuitry, the memory controller circuitry including a self-test circuit that performs a reliability test of the random number generator circuitry,wherein the self-test circuit:inputs a predetermined control signal to the random number generator circuitry to cause the random number generator circuitry to generate a random number value, andchecks irreproducibility of random number values, which are generated by the random number generator circuitry.2. The semiconductor device according to claim 1 , further comprising:a storage, whereinthe self-test circuit stores the random number value generated by the random number generator circuitry in the storage, and checks irreproducibility of the random number values generated by the random number generator circuitry based on the random number value read from the storage.3. The semiconductor device according to claim 2 , whereina test command received from an external device by the semiconductor device contains count information for specifying a number of counts to cause the random number generator circuitry to generate the random number values, andthe self-test circuit extracts the count information from the test command and causes the random number generator circuitry to sequentially generate a plurality of random number values based on the count information.4. The semiconductor device according to claim 3 , whereinthe self-test circuit (i) starts checking of the random number ...

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Номер записи: 71
03-01-2019 дата публикации

Memory device comprising an electrically floating body transistor and methods of operating

Номер: US20190006516A1
Автор: Dinesh Maheshwari, Jin-Woo Han, Yuniarto Widjaja
Принадлежит: Zeno Semiconductor Inc

A semiconductor memory cell comprising an electrically floating body having two stable states is disclosed. A method of operating the memory cell is disclosed.

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Номер записи: 72
20-01-2022 дата публикации

CIRCUIT FOR DETECTING ANTI-FUSE MEMORY CELL STATE AND MEMORY

Номер: US20220020442A1
Автор: JI Rumin
Принадлежит: CHANGXIN MEMORY TECHNOLOGIES, INC.

A circuit for detecting an anti-fuse memory cell state includes a current providing module connected to a first node and used to provide constant current; an anti-fuse memory cell array connected to the first node and including at least one bit line, the at least one bit line is connected to a plurality of anti-fuse memory cells and the first node; and a comparator, a first input end of the comparator is connected to the first node and a second input end of the comparator is connected to a first reference voltage, and used to detect a storage state of an anti-fuse memory cell to be tested in the anti-fuse memory cell array. 1. A circuit for detecting an anti-fuse memory cell state , comprising:a current providing module connected to a first node and used to provide constant current;an anti-fuse memory cell array connected to the first node and comprising at least one bit line, the at least one bit line being connected to a plurality of anti-fuse memory cells and the first node; anda comparator, wherein a first input end of the comparator is connected to the first node, a second input end of the comparator is connected to a first reference voltage, and the comparator is used to detect a storage state of an anti-fuse memory cell to be tested in the anti-fuse memory cell array.2. The circuit for detecting the anti-fuse memory cell state of claim 1 , wherein the current providing module comprises:an amplifier, wherein a first input end of the amplifier is connected to a second reference voltage, a second input end of the amplifier is connected to a second node, and an output end of the amplifier is connected to a third node;a first switching element, wherein a first end of the first switching element is connected to a power voltage, a second end of the first switching element is connected to the second node, and a control end of the first switching element is connected to the third node;a reference resistor, wherein a first end of the reference resistor is connected to ...

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Номер записи: 73
27-01-2022 дата публикации

INTEGRATED CIRCUIT SELF-REPAIR METHOD AND INTEGRATED CIRCUIT THEREOF

Номер: US20220026489A1
Автор: Lin Yu-Pin, Sung Lien-Hsiang
Принадлежит: Realtek Semiconductor Corp.

An integrated circuit self-repair method and an integrated circuit thereof are provided. The integrated circuit self-repair method includes: transmitting, by a main register, a predetermined logic state to at least three registers, and setting the at least three registers to the predetermined logic state; outputting, according to the predetermined logic state in the at least three registers, the predetermined logic state to drive a controlled circuit to perform a function; and when a minority of the at least three registers are changed to an opposite logic state due to an emergency occurring at an input power source, outputting the predetermined logic state according to the predetermined logic state of the remaining registers, and transmitting the predetermined logic state back to the register that is in the opposite logic state, to correct the opposite logic state to the predetermined logic state. 1. An integrated circuit self-repair method , comprising:transmitting, by a main register, a predetermined logic state to at least three registers, and setting the at least three registers to the predetermined logic state;outputting, according to the predetermined logic state in the at least three registers, the predetermined logic state to drive a controlled circuit to perform a function; andwhen a minority of the at least three registers are changed to an opposite logic state due to an emergency occurring at an input power source, outputting the predetermined logic state according to the predetermined logic state of the remaining registers, and transmitting the predetermined logic state back to the register that is in the opposite logic state, to correct the opposite logic state to the predetermined logic state.2. The integrated circuit self-repair method according to claim 1 , wherein the predetermined logic state is generated by a setting circuit claim 1 , the setting circuit transmits a transmission protocol with the predetermined logic state to the main register ...

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Номер записи: 74
12-01-2017 дата публикации

SEMICONDUCTOR DEVICE PACKAGE HAVING AN OSCILLATOR AND AN APPARATUS HAVING THE SAME

Номер: US20170010639A1
Автор: KARAKANE Yuji, MATSUMOTO Manabu, MURAKAMI Katsuya, Ozawa Isao, Shimazaki Tadashi, Tanimoto Akira
Принадлежит:

A semiconductor device package includes a substrate including, on an edge thereof, a connector that is connectable to a host, a nonvolatile semiconductor memory device disposed on a surface of the substrate, a memory controller disposed on the surface of the substrate, an oscillator disposed on the surface of the substrate and electrically connected to the memory controller, and a seal member sealing the nonvolatile semiconductor memory device, the memory controller, and the oscillator on the surface of the substrate. 1. A semiconductor device package , comprising:a substrate including, on an edge thereof, a connector that is connectable to a host;a nonvolatile semiconductor memory device disposed on a surface of the substrate;a memory controller disposed on the surface of the substrate;an oscillator disposed on the surface of the substrate and electrically connected to the memory controller; anda seal member sealing the nonvolatile semiconductor memory device, the memory controller, and the oscillator on the surface of the substrate.2. The semiconductor device package according to claim 1 , whereinthe oscillator is positioned farther from the connector than the memory controller is.3. The semiconductor device package according to claim 1 , whereinthe oscillator is disposed in a region of the substrate defined by an edge of the nonvolatile semiconductor memory device, an edge of the memory controller, and edges of the seal member.4. The semiconductor device package according to claim 1 , further comprising:a volatile semiconductor memory device disposed on the surface of the substrate, whereina region of the substrate covered by the seal member includes first and second regions that are diagonal to each other, andthe oscillator is disposed in the first region, and the volatile semiconductor memory device is disposed in the second region.5. The semiconductor device package according to claim 4 , whereina height of the volatile semiconductor memory device is greater ...

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Номер записи: 75
27-01-2022 дата публикации

METHOD AND DEVICE FOR PROCESSING DATA STORED IN A MEMORY UNIT

Номер: US20220028472A1
Автор: Jauss Manuel, Kartal Mustafa
Принадлежит:

A method for processing data stored in a memory unit. The method includes the following steps: ascertaining a randomly or pseudo-randomly formed test pattern, which characterizes at least one first subarea of a memory area of the memory unit, forming, as a function of the test pattern, a test variable associated with data stored in the at least one first subarea. 116-. (canceled)17. A method for processing data stored in a memory unit , comprising the following steps:ascertaining a randomly or pseudo-randomly formed test pattern, which characterizes at least one first subarea of a memory area of the memory unit; andforming, as a function of the test pattern, a test variable associated with data stored in the at least one first subarea.18. The method as recited in claim 17 , further comprising:a) storing at least temporarily the test variable; and/orb) comparing the test variable with a reference test variable for the at least one first subarea.19. The method as recited in claim 17 , wherein the ascertainment of the test pattern includes at least one of the following: (a) random or pseudo-random formation of the test pattern claim 17 , b) receiving the test pattern from an external unit claim 17 , c) reading out the test pattern from the memory unit and/or from a further memory unit claim 17 , d) deriving the test pattern from a test pattern base data.20. The method as recited in claim 19 , wherein the formation of the test pattern includes the following steps: providing a random or pseudo-random sequence of numbers claim 19 , ascertaining the at least one first subarea as a function of at least one first part of the sequence of numbers claim 19 , a start address of the first subarea in the memory area being formed as a function of the first part of the sequence of numbers.21. The method as recited in claim 17 , wherein the test pattern characterizes claim 17 , in addition to the first subarea claim 17 , at least one second subarea claim 17 , the at least one further ...

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Номер записи: 76
27-01-2022 дата публикации

METHOD FOR THE SECURED STORING OF A DATA ELEMENT OF A PREDEFINED DATA TYPE TO BE STORED BY A COMPUTER PROGRAM IN AN EXTERNAL MEMORY

Номер: US20220028474A1
Автор: Assel Martin, Aue Axel, SCHREIBER Matthias
Принадлежит:

A method for the secured storing of a data element of a predefined data type to be stored by a computer program in an external memory, which is connected to a microcontroller, an error correction value of one error correction value data type being used. The method includes, when creating the computer program: defining a composite data element that includes one element of the data type and one element of the error correction value data type, in the computer program; and when executing the computer program: calculating the error correction value for the data element to be stored; forming an error correction data element as the composite data element, which contains the data element to be stored and the associated error correction value, which has been calculated for the data element; and writing the error correction data element to a memory address for the error correction data element. 1. A method for secured storing of a data element of a predefined data type to be stored by a computer program in an external memory , which is connected to a microcontroller , an error correction value of an error correction value data type being used , the method comprising:defining, when creating the computer program, a composite data element, which includes one element of the predefined data type and one element of the error correction value data type, in the computer program; and calculating the error correction value for the data element to be stored,', 'forming an error correction data element as the composite data element, which contains the data element to be stored and the error correction value which has been calculated for the data element, and', 'writing the error correction data element to a memory address for the error correction data element., 'when executing the computer program2. The method as recited in claim 1 , further comprising a read operation of the data element claim 1 , the read operation including:reading the error correction data element stored at the ...

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Номер записи: 77
27-01-2022 дата публикации

ON-CHIP-COPY FOR INTEGRATED MEMORY ASSEMBLY

Номер: US20220028475A1
Автор: ALROD IDAN, SHARON ERAN
Принадлежит: WESTERN DIGITAL TECHNOLOGIES, INC.

A non-volatile memory system comprises an integrated memory assembly in communication with a memory controller. The integrated memory assembly includes a memory die bonded to a control die. The control die includes one or more control circuits for controlling the operation of the memory die. The control circuits are configured to receive a request to copy data on the memory die, read codewords on the memory die in response to the request, decode the codewords to identify errors in the codewords, correcting the errors in the codewords, and program the codewords back into the memory die. In one embodiment, the codewords read are stored in the memory die as single bit per memory cell data and the codewords programmed back into the memory die after correcting errors are programmed as multiple bit per memory cell data. 1. A method , comprising:transferring codewords that are stored in non-volatile memory cells on a memory die to a control die bonded to the memory die, the codewords are stored in the non-volatile memory cells on the memory die as single bit per memory cell data;on the control die, decoding the transferred codewords to identify one or more errors;on the control die, fixing the identified errors in the codewords; andafter fixing the identified errors in the codewords, programming the codewords to the memory die as multiple bit per memory cell data such that multiple non-volatile memory cells of the memory die store data from multiple codewords.2. The method of claim 1 , wherein:the programming the codewords comprises programming using a multi-pass programming process;the multi-pass programming process comprises programming a first subset of the codewords during a first pass of the multi-pass programming process and programming a second subset of the codewords during a later pass of the multi-pass programming process that is subsequent to the first pass; andthe decoding the transferred codewords comprises decoding the second subset of the codewords on the ...

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Номер записи: 78
27-01-2022 дата публикации

REPAIR ANALYSIS CIRCUIT AND MEMORY INCLUDING THE SAME

Номер: US20220028477A1
Автор: CHO Hosung
Принадлежит:

A memory may include a first repair analysis circuit suitable for storing an input fail address when the input fail address is different from a fail address which is already stored in the first repair analysis circuit, and outputting the input fail address as a first transfer fail address when a storage capacity of the first repair analysis circuit is full; and a second repair analysis circuit suitable for storing the first transfer fail address when the first transfer fail address is different from a fail address which is already stored in the second repair analysis circuit. 1. A repair analysis circuit comprising:{'sup': 'th', 'first to Xrepair address registers each suitable for storing a fail address therein where X is an integer equal to or greater than 2; and'}{'sup': 'th', 'a redundancy check circuit suitable for receiving an input address set including one or more addresses and input fail information indicating whether the input address set is a fail, and checking whether a fail address within the input address set is same as one of fail addresses already stored in the first to Xrepair address registers,'}{'sup': th', 'th, 'wherein when it is determined that the fail address within the input address set is different from one of the fail addresses already stored in the first to Xrepair address registers, the corresponding fail address is stored in an empty repair address register among the first to Xrepair address registers.'}2. The repair analysis circuit of claim wherein the redundancy check circuit checks whether fail addresses within the input address set are same as one another.3. The repair analysis circuit of claim 1 , wherein when it is determined that the fail address within the input address set is different from one of the fail addresses already stored in the first to Xrepair address registers claim 1 , the corresponding fail address is stored in a repair address register having the lowest number among empty repair address registers of the first to ...

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Номер записи: 79
27-01-2022 дата публикации

Retention Voltage Management for a Volatile Memory

Номер: US20220028479A1
Автор: Abu-Rahma Mohamed H., Barn Amrinder S., Nazar Shahzad
Принадлежит:

An apparatus includes a memory circuit that includes a plurality of sub-arrays. The memory circuit is configured to implement a retention mode according to test information indicating voltage sensitivities for the plurality of sub-arrays. The apparatus also includes a voltage control circuit coupled to a power supply node. The voltage control circuit is configured, in response to activation of the retention mode for the plurality of sub-arrays, to generate, based on the test information, at least two different retention voltage levels for different ones of the plurality of sub-arrays. The at least two different retention voltage levels are lower than a power supply voltage level of the power supply node. 120-. (canceled)21. An apparatus , comprising:a memory circuit including a plurality of sub-arrays, wherein the memory circuit is configured to implement a retention mode according to stored information indicating voltage sensitivities for the plurality of sub-arrays; and generate, based on the stored information, a first retention voltage level for a first subset of the plurality of sub-arrays; and', 'generate, based on the stored information, a second retention voltage level, higher than the first retention voltage level, for a second subset of the plurality of sub-arrays; and', 'wherein the first and second retention voltage levels are lower than a power supply voltage level of the power supply node, and wherein the second subset includes one or more voltage sensitive data storage cells that fail to retain data at the first retention voltage level., 'a voltage control circuit coupled to a power supply node, wherein during the retention mode for the plurality of sub-arrays, the voltage control circuit is configured to22. The apparatus of claim 21 , wherein the stored information includes test information generated from a test procedure that indicates that one or more voltage sensitive data storage cells are included in the second subset of the plurality of sub- ...

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Номер записи: 80
27-01-2022 дата публикации

TSV Check Circuit With Replica Path

Номер: US20220028749A1
Автор: Harutaka Makabe
Принадлежит: Micron Technology Inc

Disclosed herein is an apparatus that includes a first semiconductor chip, first and second TSVs penetrating the first semiconductor chip, a first path including the first TSV, a second path including the second TSV, a first charge circuit configured to charge the first path, a second charge circuit configured to charge the second path, a first discharge circuit configured to discharge the first path, a second discharge circuit configured to discharge the second path, and a comparator circuit configured to compare a potential of the first path with a potential of the second path.

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Номер записи: 81
08-01-2015 дата публикации

OPTIMIZING fuseROM USAGE FOR MEMORY REPAIR

Номер: US20150012786A1
Автор: Ellur Harsharaj, Varadarajan Devanathan
Принадлежит: TEXAS INSTRUMENTS INCORPORATED

A memory repair system in an integrated circuit (IC) that optimizes the fuseROM used for memory repair. The IC includes a plurality of memory wrappers. Each memory wrapper includes a memory block with a fuse register and a bypass register. The bypass register have a bypass data that indicates a defective memory wrapper of the plurality of memory wrappers. A fuseROM controller is coupled to the plurality of memory wrappers. A memory bypass chain links the bypass registers in the plurality of memory wrappers with the fuseROM controller. The fuseROM controller loads the bypass data in the memory bypass chain. A memory data chain links the fuse registers in the plurality of memory wrappers with the fuseROM controller. The memory data chain is re-configured to link the fuse registers in a set of defective memory wrappers of the plurality of memory wrappers responsive to the bypass data loaded in the memory bypass chain. 1. An integrated circuit comprising:a plurality of memory wrappers, each memory wrapper comprising a memory block with a fuse register and a bypass register, the bypass register having a bypass data that is configured to indicate a defective memory wrapper of the plurality of memory wrappers;a fuseROM controller coupled to the plurality of memory wrappers;a memory bypass chain configured to link the bypass registers in the plurality of memory wrappers with the fuseROM controller, wherein the fuseROM controller is configured to load the bypass data in the memory bypass chain; anda memory data chain configured to link the fuse registers in the plurality of memory wrappers with the fuseROM controller, wherein the memory data chain is re-configured to link the fuse registers in a set of defective memory wrappers of the plurality of memory wrappers responsive to the bypass data loaded in the memory bypass chain.2. The integrated circuit of further comprising a fuseROM coupled to the fuseROM controller claim 1 , wherein the fuseROM comprises a memory data ...

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Номер записи: 82
11-01-2018 дата публикации

SEMICONDUCTOR APPARATUS, MEMORY SYSTEM AND REPAIR METHOD THEREOF

Номер: US20180011645A1
Автор: KIM Dae Suk, KU Young Jun
Принадлежит: SK HYNIX INC.

A semiconductor apparatus may include a fuse cell array, an address generation circuit, a control circuit, and a command generation circuit. The fuse cell array may store a fail address. The address generation circuit may generate a copy address according to test information containing the fail address. The control circuit may control a repair operation including enabling a copy start signal according to the test information and storing the fail address in the fuse cell array according to a copy done signal. The command io generation circuit may generate an address and a plurality of commands for a data copy operation according to the copy start signal and enable the copy done signal when the data copy operation is completed. 1. A semiconductor apparatus comprising:a fuse cell array configured to store a fail address;an address generation circuit configured to generate a copy address according to test information containing the fail address;a control circuit configured to control a repair operation including enabling a copy start signal according to the test information and storing the fail address in the fuse cell array according to a copy done signal; anda command generation circuit configured to generate an address and a plurality of commands for a data copy operation according to the copy start signal and enable the copy done signal when the data copy operation is completed.2. The semiconductor apparatus according to claim 1 , wherein the copy address comprises an address of memory cells coupled to signal lines corresponding to the fail address.3. The semiconductor apparatus according to claim 1 , wherein the data copy operation comprises copying data stored in the normal memory cells corresponding to the copy address into redundant memory cells selected to store the data stored in to the normal memory cells.4. The semiconductor apparatus according to claim 1 , further comprising a BIST (Built-in Self Test) circuit configured to generate the test information by ...

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Номер записи: 83
14-01-2016 дата публикации

Determination of Word Line to Local Source Line Shorts

Номер: US20160012914A1
Автор: Magia Sagar, Sabde Jagdish
Принадлежит:

A number of techniques for determining defects in non-volatile memory arrays are presented, which are particularly applicable to 3D NAND memory, such as that of the BiCS type. Word line to word shorts within a memory block are determined by application of an AC stress mode, followed by a defect detection operation. An inter-block stress and detection operation can be used determine word line to word line leaks between different blocks. Select gate leak line leakage, both the word lines and other select lines, is consider, as are shorts from word lines and select lines to local source lines. In addition to word line and select line defects, techniques for determining shorts between bit lines and low voltage circuitry, as in the sense amplifiers, are presented. 1. A method of determining whether one or more blocks of a semi-conductor memory device are defective , the memory device comprising a plurality of blocks , each formed of a plurality of NAND strings having multiple memory cells connected in series between one or more source select gates and one or more drain select gates , the memory cells being connected along word lines and the source and drain select gates being respectively connected along source and drain select lines , where each of a block's NAND strings are connected though the corresponding source select gates to a local source line , the method comprising: applying a high voltage to the local source line; and', 'concurrently setting the word lines, source select lines and drain select lines to a low voltage;, 'performing a stress operation on a selected block, comprising performing a write operation on the selected blocks; and', 'determining whether the write operation was successful., 'subsequently performing a defect determination operation, including2. The method of claim 1 , wherein determining whether the write operation was successful comprises determining that the number of cells along a word line that fail to verify exceeds a predetermined ...

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Номер записи: 84
14-01-2016 дата публикации

Determination of Bit Line to Low Voltage Signal Shorts

Номер: US20160012915A1
Автор: Magia Sagar, Sabde Jagdish
Принадлежит:

A number of techniques for determining defects in non-volatile memory arrays are presented, which are particularly applicable to 3D NAND memory, such as that of the BiCS type. Word line to word shorts within a memory block are determined by application of an AC stress mode, followed by a defect detection operation. An inter-block stress and detection operation can be used determine word line to word line leaks between different blocks. Select gate leak line leakage, both the word lines and other select lines, is consider, as are shorts from word lines and select lines to local source lines. In addition to word line and select line defects, techniques for determining shorts between bit lines and low voltage circuitry, as in the sense amplifiers, are presented. 1. A method of determining defects in a non-volatile memory circuit , the method comprising: applying a high voltage level to the first set of bit lines; and', 'setting the sense amplifiers associated with the second set of bit lines to a sense amplifier operating level,', 'wherein at least one bit line of the first set of bit lines is adjacent to at least one of the sense amplifiers associated with the second set of bit lines; and, 'for a first set of one or more bit lines and a second set of one or more bit lines, while the switches corresponding to the first and second sets of bit lines are off, concurrently, 'performing a stress operation on a non-volatile memory circuit having a plurality of memory cells, where each of the memory cells is connectable by one of a plurality of bit lines to one of a plurality of sense amplifiers, and where each of the bit lines is connectable to an associated one of the sense amplifiers by a corresponding switch, the stress operation including with the corresponding switches for the first and second sets of bit lines off and the sense amplifiers associated with of the second set of bit lines set to the sense amplifier operating level, supplying the first set of bit lines from ...

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Номер записи: 85
10-01-2019 дата публикации

APPARATUSES AND METHODS FOR CONTROLLING REFRESH OPERATIONS

Номер: US20190013059A1
Автор: Akamatsu Hiroshi
Принадлежит: MICRON TECHNOLOGY, INC.

An apparatus includes, a first word line, a second word line and a control. The second word line is contiguous to the first word line. The control circuit includes a first defective address storing circuit and a fast detection circuit. The first defective address storing circuit stores first enable information along with first defective address. The first enable information indicates whether or not the second word line is functional. The first detection circuit provides a first signal when the first word line is accessed. The first signal indicates whether or not the second word line is functional. The control circuit activates the second word line when the first signal indicates that the second word line is functional and does not activate the second word line when the first signal indicates that the second word line is not functional. 1. A method comprising:receiving a first command to enter a target-row refresh mode;receiving a second command and a third command during the target-row refresh mode, wherein the second command is accompanied by first address information designating a first word line of a plurality of word lines in a memory array, wherein the third command is accompanied by the first address information designating the first word line, and wherein the plurality of word lines further includes a second word line that is proximate to the first word line; and responsive to the second command, activating the first word line; and', 'responsive to the third command, activating the second word line if the second word line is functional and not activating the second word line if the second word line is not functional., 'performing, responsive to the second command and the third command, a refresh operation on the memory array by2. The method of claim 1 , further comprising:before entering the target-row refresh mode, storing detective address information, 'responsive, at least in part, to the first address information accompanying the third command, providing ...

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Номер записи: 86
10-01-2019 дата публикации

MEMORY TESTING METHOD AND MEMORY APPARATUS THEREFOR

Номер: US20190013084A1
Автор: Chan Johnny
Принадлежит: WINBOND ELECTRONICS CORP.

A memory testing method for testing a memory apparatus configured with an auxiliary testing circuit is provided. The memory testing method includes: reading a test data from a memory array of the memory; and encoding the test data into an encoded data by the auxiliary testing circuit, wherein the encoded data comprises a first piece data and a second piece data. The encoded data is encoded to include a first piece data and a second piece data, where the first piece data indicates a number of a binary state in the read test data, and the second piece data indicates an error bit in the read test data. In addition, a memory apparatus for the memory testing method is also provided. 1. A memory testing method for testing a memory apparatus configured with an auxiliary testing circuit , the memory testing method comprising:reading a test data from a memory array of the memory apparatus; andencoding the test data into an encoded data by the auxiliary testing circuit, wherein the encoded data comprises a first piece data and a second piece data,wherein the first piece data indicates a number of a binary state in the read test data, and the second piece data indicates an error bit in the read test data.2. The memory testing method as claimed in claim 1 , wherein the memory apparatus is an ECC memory apparatus.3. The memory testing method as claimed in claim 1 , wherein before the step of reading the test data from the memory array of the memory apparatus claim 1 , the memory testing method further comprises:writing the test data of one of a target pattern into the memory array.4. The memory testing method as claimed in claim 3 , wherein the target pattern comprises at least one of an all-one pattern claim 3 , an all-zero pattern claim 3 , a checkerboard pattern claim 3 , and an inverse checkerboard pattern.5. The memory testing method as claimed in claim 3 , wherein the step of encoding the test data into the encode data comprises:calculating the number of the binary state ...

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Номер записи: 87
14-01-2021 дата публикации

Memory device and memory system comprising the same

Номер: US20210012831A1
Автор: Byoungjik Kim, Jihyuk Oh, Kiseok Park, Youngjin Park
Принадлежит: SAMSUNG ELECTRONICS CO LTD

A memory device includes a plurality of memory chips for writing and reading data in response to a control command and an address signal, and a control logic circuit for transferring the control command and the address signal to the plurality of the memory chips, and receiving a first command from a memory controller to perform a first operation, different from a refresh operation, on at least one of a plurality of the memory chips. The control logic circuit, in response to a refresh command, transmits the first command to at least one of a plurality of the memory chips and performs the first operation during a pre-determined refresh time interval without carrying out the refresh operation.

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Номер записи: 88
14-01-2021 дата публикации

SEMICONDUCTOR MEMORY DEVICES AND METHODS OF OPERATING SEMICONDUCTOR MEMORY DEVICES

Номер: US20210012849A1
Автор: Kim Kyungryun, Lee Jaeho, Oh Yoonna, Shin Hohyun
Принадлежит:

A semiconductor memory device comprises a memory cell array including segments disposed at corresponding intersections of row and column blocks, each row block including dynamic memory cells coupled to word-lines and bit-lines, a row decoder that activates a first word-line of a first row block in response to a row address, determines whether the first row block is a master block based on a first fuse information and a second row block is mapped as a slave to the master block, activates a second word-line of the second row block, and outputs a row block information signal, and a column decoder accessing a portion of first memory cells coupled to the first word-line or a portion of second memory cells coupled to the second word-line based on a column address, the row block information signal and a second fuse information. 1. A semiconductor memory device comprising:a memory cell array including a plurality of row blocks arranged in a first direction, a plurality of column blocks arranged in a second direction different from the first direction and a plurality of segments each of which is disposed at a corresponding intersection of the plurality of row blocks and the plurality of column blocks, each of the plurality of row blocks including a plurality of dynamic memory cells coupled to word-lines and bit-lines;a row decoder configured to:receive a row address,activate a first word-line of a first row block of the plurality of row blocks in response to the row address, wherein the first row block is identified with at least one block address bit of the row address,determine whether the first row block is a master block based on a first fuse information indicating that the first row block is the master block and a second row block of the plurality of row blocks is mapped as a slave to the master block,activate, in response to the determining of whether the first row block is the master block, a second word-line of the second row block of the plurality of row blocks, ...

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Номер записи: 89
14-01-2021 дата публикации

Uncorrectable ecc

Номер: US20210012851A1
Автор: Deping He, Harish Reddy Singidi, Jianmin Huang, John Zhang, Kulache Tanpairoj, Ting Luo, Xiangang Luo
Принадлежит: Micron Technology Inc

Disclosed in some examples are NAND devices, firmware, systems, methods, and devices that apply smart algorithms to process ECC errors by taking advantage of excess overprovisioning. In some examples, when the amount of overprovisioned blocks are above a predetermined threshold, a first ECC block error handling mode may be implemented and when the overprovisioned blocks are equal or less than the predetermined threshold, a second mode of ECC block error handling may be utilized.

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Номер записи: 90
14-01-2021 дата публикации

SEMICONDUCTOR MEMORY DEVICE, MEMORY CONTROLLER, AND ERROR NOTIFICATION METHOD

Номер: US20210012852A1
Автор: Maeda Masaki, TANAKA Kazuhito
Принадлежит: Panasonic Intellectual Property Management Co., Ltd.

A semiconductor memory device includes a data bus terminal group for outputting read data to an external device or inputting write data from an external device, a first terminal from or into which 1-bit data is output or input, a DBI circuit that executes a Data Bus Inversion (DBI) function, an error detection circuit that detects an internal error, and an information superimposing circuit that superimposes predetermined output information onto the 1-bit data to be output from the first terminal and the read data to be output from the data bus terminal group. The predetermined output information includes first output information indicating whether or not an output bit pattern of the data bus terminal group is inverted, and second output information indicating whether or not an internal error has been detected by the error detection circuit. 1. A semiconductor memory device , comprising:a data bus terminal group for outputting read data to an external device or inputting write data from an external device;a first terminal from or into which 1-bit data is output or input;a DBI circuit that executes a Data Bus Inversion (DBI) function;an error detection circuit that detects an internal error; andan information superimposing circuit that superimposes predetermined output information onto the 1-bit data to be output from the first terminal and the read data to be output from the data bus terminal group,wherein the predetermined output information includes:first output information indicating whether or not an output bit pattern of the data bus terminal group is inverted; andsecond output information indicating whether or not an internal error has been detected by the error detection circuit.2. The semiconductor memory device according to claim 1 ,wherein the information superimposing circuit further extracts predetermined input information from the 1-bit data input to the first terminal and an input bit pattern serving as the write data input to the data bus terminal ...

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Номер записи: 91
14-01-2021 дата публикации

Storage control circuit, storage apparatus, imaging apparatus, and storage control method

Номер: US20210012853A1
Автор: Masaki Murozuka
Принадлежит: Sony Semiconductor Solutions Corp

It is aimed to detect an error of an address abnormality in a memory. An address error detection information generating unit generates address error detection information for detecting an error relating to an access address for a memory. A control part stores the address error detection information generated by the address error detection information generating unit in the memory at a time of write access. An error detecting part compares the address error detection information generated by the address error detection information generating unit with the address error detection information stored in the memory to detect an error at a time of read access.

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Номер записи: 92
14-01-2021 дата публикации

Non-volatile semiconductor memory device and method for driving the same

Номер: US20210012854A1
Автор: Daisuke Uchida
Принадлежит: Kioxia Corp

The non-volatile semiconductor memory device comprises a non-volatile semiconductor memory, a controller for controlling the non-volatile semiconductor memory, the controller includes a reset terminal capable of receiving a reset signal from a host, an interface circuit capable of receiving a sleep command, and a data storing circuit, when the reset signal is received in a state which the interface circuit is being supplied with power, the data storing circuit is reset, when a sleep command is received in a state which the interface circuit is being supplied with power, the data necessary for communication with the host or the non-volatile semiconductor memory device is stored into the data storing circuit and power to the interface circuit is interrupted and when the reset signal is received in a state which power to the interface circuit is interrupted, the data is read from the data storing circuit.

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Номер записи: 93
14-01-2021 дата публикации

Method and Apparatus for enabling Multiple Return Material Authorizations (RMAs) on an Integrated Circuit Device

Номер: US20210012855A1
Автор: Chen Kenneth, Draper Andrew Martyn, Lau Wei Chun, Lu Ting, Menon Sankaran M.
Принадлежит:

An integrated circuit (IC) device configured for multiple return material authorizations (RMAs) is provided. The IC device includes an asset and a return material authorization (RMA) counter fuse including a first fuse, a second fuse, and a third fuse. The IC device enters an RMA state in response to blowing the first fuse, a second state in response to blowing the second fuse, and the RMA state in response to blowing the third fuse. 1. An integrated circuit (IC) device configured for multiple return material authorizations (RMAs) , the IC device comprising:an asset disposed on the IC device; anda return material authorization (RMA) counter fuse comprising a first fuse, a second fuse, and a third fuse, wherein the IC device enters an RMA state that disables access to the asset in response to blowing the first fuse, wherein the IC device enters a second state in response to blowing the second fuse, and wherein the IC device re-enters the RMA state in response to blowing the third fuse.2. The IC device of claim 1 , wherein the asset comprises circuitry claim 1 , nonvolatile code claim 1 , or a field programmable gate array circuit design claim 1 , or a combination thereof.3. The IC device of claim 1 , wherein the IC device blows the second fuse during a time period beginning after the first fuse is blown and wherein the IC device blows the third fuse during a time period beginning after the second fuse is blown.4. The IC device of claim 1 , wherein the IC device enables access to the asset in response to the IC device leaving the RMA state.5. The IC device of claim 1 , wherein the third fuse is blown during a time period beginning after the first fuse is blown.6. The IC device of claim 1 , wherein a status of a fuse on the RMA counter fuse indicates a state of the IC device.7. The IC device of claim 1 , wherein the IC device indicates an amount of times that the IC device has been in the RMA state based on a status of at least one of the first fuse claim 1 , the ...

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Номер записи: 94
09-01-2020 дата публикации

TEST CONTROL CIRCUIT, SEMICONDUCTOR MEMORY APPARATUS AND SEMICONDUCTOR SYSTEM USING THE TEST CONTROL CIRCUIT

Номер: US20200013475A1
Автор: CHAE Haeng Seon
Принадлежит: SK HYNIX INC.

A test control circuit includes a test mode generation circuit. The test mode generation circuit may be configured to generate, while in a fast access mode, a fast test mode signal based on information included in one of a plurality of mode signals and a fast set signal. The test mode generation circuit may be configured to generate, while in a normal mode, a normal test mode signal based on information included in two or more mode signals from the plurality of mode signals and a normal set signal. 1. A test control circuit comprising:a control signal generation circuit configured to generate a normal set signal and a fast set signal based on a test command signal, a command pulse, and a fast access signal;a decoding circuit configured to generate a plurality of mode signals based on a plurality of the test command signals; anda test mode generation circuit configured to generate a normal test mode signal based on two or more mode signals and the normal set signal, and generate a fast test mode signal based on one mode signal and the fast set signal.2. The test control circuit of claim 1 , wherein the control signal generation circuit includes:an encoder configured to generate a pre-decoding signal by encoding the test command signal;a normal set signal generator configured to generate the normal set signal based on the pre-decoding signal, the command pulse, and the fast access signal; anda fast set signal generator configured to generate the fast set signal based on the normal set signal and the fast access signal.3. The test control circuit of claim 2 , wherein the normal set signal generator is configured to generate the normal set signal based on the pre-decoding signal and the command pulse claim 2 , or based on the command pulse and the fast access signal.4. The test control circuit of claim 2 , wherein the control signal generation circuit is configured to further generate a latch reset signal by delaying the normal set signal claim 2 , and further generate ...

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Номер записи: 95
09-01-2020 дата публикации

MEMORY SYSTEM WITH DIAGNOSE COMMAND AND OPERATING METHOD THEREOF

Номер: US20200013477A1
Автор: JIN Young Tack
Принадлежит:

A memory system and an operating method thereof include: at least a CPU configured to generate a special command; at least a PCIe link coupled with the CPU, wherein the PCIe link includes at least a PCIe switch; and a plurality of memory devices connected with the PCIe switch, wherein each of the plurality of memory devices includes a memory controller, an operational mode switch, and a plurality of memory components, and the operational mode switch is configured to perform a loopback from the memory controller corresponding to the special command at loopback operational mode. 1at least a CPU configured to generate a special command;at least a PCIe link coupled with the CPU, wherein the PCIe link includes at least a PCIe switch; anda plurality of memory devices connected with the PCIe switch,wherein each of the plurality of memory devices includes a memory controller, an operational mode switch, and a plurality of memory components, and the operational mode switch is configured to perform a loopback from the memory controller corresponding to the special command at loopback operational mode.. A memory system comprising: This application is a continuation of U.S. patent application Ser. No. 15/812,472 filed on Nov. 14, 2017, which claims benefits of priority of U.S. Provisional Patent Application No. 62/477,319 filed on Mar. 27, 2017. The disclosure of each of the foregoing application is incorporated herein by reference in its entirety.Exemplary embodiments of the present invention relate to an apparatus of semiconductor memory storage system, and more particularly to diagnose SSD and an operation method thereof.The computer environment paradigm has shifted to ubiquitous computing systems that can be used anytime and anywhere. Due to this fact, the use of portable electronic devices s as mobile phones, digital cameras, and notebook computers has rapidly increased. These portable electronic devices generally use a memory system having memory devices, that is, a data ...

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Номер записи: 96
18-01-2018 дата публикации

Configurable Vertical Integration

Номер: US20180017614A1
Автор: Leedy Glenn J
Принадлежит:

The Configurable Vertical Integration [CVI] invention pertains to methods and apparatus for the enhancement of yields of 3D or stacked integrated circuits and herein referred to as a CVI Integrated Circuit [CVI IC]. The CVI methods require no testing of circuit layer components prior to their fabrication as part of a 3D integrated circuit. The CVI invention uses active circuitry to configure the CVI IC as a means to isolate or prevent the use of defective circuitry. CVI circuit configuration method can be predominately described as a large grain method. 1. A method of integrated circuit testing of a stacked integrated circuit comprising a plurality of information busing and processing circuit portions , the method comprising:one or more circuit portions for enabling and disabling the operation of one or more information processing circuit portions and one or more bus circuit portions;disabling a plurality of processing circuit portions;testing at least one enabled processing circuit portion at a time.2. A method of information processing using a stacked integrated circuit comprising a plurality of information busing and processing circuit portions , the method comprising:one or more circuit portions for enabling and disabling the operation of one or more information processing circuit portions and one or more bus circuit portions;performing information processing between at least two of the processing circuit portions while at least one of the processing circuit portions is disabled as a result from one of the one or more circuit portions.3. A method of information processing using a stacked integrated circuit comprising a plurality of information busing and processing circuit portions , the method comprising:one or more circuit portions for enabling and disabling the operation of one or more information processing circuit portions and one or more bus circuit portions;performing information processing with a plurality of the processing circuit portions and at least ...

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Номер записи: 97
15-01-2015 дата публикации

Manufacturing testing for ldpc codes

Номер: US20150019926A1
Автор: Lingqi Zeng, Yu Kou
Принадлежит: SK Hynix Memory Solutions America Inc

An amount of time and an error rate function are received, where the error rate function defines a relationship between a number of iterations associated with iterative decoding and an error rate. A testing error rate is determined based at least in part on the amount of time. The number of iterations which corresponds to the testing error rate in the error rate function is selected to be a testing number of iterations; the testing error rate and the testing number of iterations are associated with testing storage media using iterative decoding.

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Номер записи: 98
21-01-2016 дата публикации

ELECTRONIC DEVICE

Номер: US20160019980A1
Автор: Jeong Hoe-Gwon
Принадлежит:

An electronic device comprising a semiconductor memory unit that may include a variable resistance element configured to be changed in a resistance value thereof in response to current flowing through both ends thereof, a toggle data generation unit configured to generate toggle data of which logic value toggles with a predetermined cycle, in a first mode for testing reliability of the variable resistance element, a data transfer line configured to transfer data inputted from an outside, and a driving unit configured to flow current which is changed in its direction with the predetermined cycle, through the variable resistance element in response to the toggle data in the first mode, and flow current through the variable resistance element in a direction determined in response to the data of the data transfer line, in a second mode in writing date into or reading data from the variable resistance element.

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Номер записи: 99
21-01-2016 дата публикации

Memory test with in-line error correction code logic

Номер: US20160019981A1
Автор: Kevin W. Gorman, Michael R. Ouellette, Patrick E. Perry
Принадлежит: International Business Machines Corp

Systems and methods are provided for reusing existing test structures and techniques used to test memory data to also test error correction code logic surrounding the memories. A method includes testing a memory of a computing system with an error code correction (ECC) logic block bypassed and a first data pattern applied. The method further includes testing the memory with the ECC logic block enabled and a second data pattern applied. The method also includes testing the memory with the ECC logic block enabled and the first data pattern applied.

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Номер записи: 100