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Небесная энциклопедия

Космические корабли и станции, автоматические КА и методы их проектирования, бортовые комплексы управления, системы и средства жизнеобеспечения, особенности технологии производства ракетно-космических систем

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Мониторинг СМИ

Мониторинг СМИ и социальных сетей. Сканирование интернета, новостных сайтов, специализированных контентных площадок на базе мессенджеров. Гибкие настройки фильтров и первоначальных источников.

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Применить Всего найдено 4293. Отображено 100.
05-01-2012 дата публикации

Nonvolatile memory apparatus

Номер: US20120002480A1
Автор: In Suk YUN
Принадлежит: Hynix Semiconductor Inc

A nonvolatile memory device includes: a data transmission line configured to transmit internal configuration data; a data path control unit configured to control a data transmission path direction of the data transmission line according to control of a test signal; and a configuration data latch unit configured to latch a signal transmitted through the data transmission line or drive a latched signal to the data transmission line, according to control of the test signal.

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Номер записи: 1
19-01-2012 дата публикации

Semiconductor memory device and test method thereof

Номер: US20120014189A1
Автор: Chan-sub Jun, Hyong-yong Lee
Принадлежит: Individual

Example embodiments disclose a semiconductor memory device and a test method thereof. The semiconductor memory device includes a memory cell array that provides first and second data groups at a first data rate and an output circuit, in a normal mode of operation, serially outputs the first and second data groups at a first data rate on an external terminal. In a test mode of operation, the output circuit outputs the first data group or the second data group at a second data rate on the external terminal in response to control signals, without switching the test mode. The second data rate may be lower than the first data rate.

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Номер записи: 2
19-04-2012 дата публикации

Apparatus and methods for tuning a memory interface

Номер: US20120096218A1
Автор: Dan Shimizu, Eric Scott, Joe Macri, Sagheer Ahmad
Принадлежит: ATI TECHNOLOGIES ULC

The disclosure relates to an integrated circuit including programmable control logic configured to generate at least one data pattern sequence from a number of stored data patterns and using the generated at least one data pattern sequence to at least one of read from and write to at least one memory device. A method includes generating at least one data pattern sequence from a number of stored data patterns and writing and reading the data pattern sequence from and to a memory device.

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Номер записи: 3
02-08-2012 дата публикации

Locally synchronous shared bist architecture for testing embedded memories with asynchronous interfaces

Номер: US20120198291A1
Автор: Akhil Garg, Prashant Dubey, Sravan Kumar Bhaskarani
Принадлежит: STMICROELECTRONICS PVT LTD

A system and method of sharing testing components for multiple embedded memories and the memory system incorporating the same. The memory system includes multiple test controllers, multiple interface devices, a main controller, and a serial interface. The main controller is used for initializing testing of each of the dissimilar memory groups using a serial interface and local test controllers. The memory system results in reduced routing congestion and faster testing of plurality of dissimilar memories. The present disclosure further provides a programmable shared built in self testing (BIST) architecture utilizing globally asynchronous and locally synchronous (GALS) methodology for testing multiple memories. The built in self test (BIST) architecture includes a programmable master controller, multiple memory wrappers, and an interface. The interface can be a globally asynchronous and locally synchronous (GALS) interface.

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Номер записи: 4
30-08-2012 дата публикации

Embedded processor

Номер: US20120221911A1
Автор: Joe M. Jeddeloh
Принадлежит: Individual

Electronic apparatus, systems, and methods of operating and constructing the electronic apparatus and/or systems include an embedded processor disposed in a logic chip to direct, among other functions, self-testing of an electronic device structure in conjunction with a pattern buffer disposed in the logic chip, when the electronic device structure is coupled to the logic chip. Additional apparatus, systems, and methods are disclosed.

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Номер записи: 5
18-10-2012 дата публикации

Semiconductor memory device and test method thereof

Номер: US20120266034A1
Автор: Sang-Hoon Shin
Принадлежит: Hynix Semiconductor Inc

A semiconductor memory device includes a plurality of memory cells; a data comparison section configured to compare input data to be stored in the memory cells with output data outputted from the memory cells in a test operation, an address storage section configured to store addresses corresponding to defected memory cells of the memory cells in response to a comparison result of the data comparison section, and a comparison period control section configured to generate a period control signal for controlling an activation period of the data comparison section.

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Номер записи: 6
09-05-2013 дата публикации

Apparatuses and methods for operating a memory device

Номер: US20130117604A1
Автор: Chang Wan Ha
Принадлежит: Micron Technology Inc

Subject matter described pertains to apparatuses and methods for operating a memory device.

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Номер записи: 7
04-07-2013 дата публикации

Boundary scan chain for stacked memory

Номер: US20130173971A1
Автор: David J. Zimmerman
Принадлежит: Individual

A boundary scan chain for stacked memory. An embodiment of a memory device includes a system element and a memory stack including one or more memory die layers, each memory die layer including input-output (I/O) cells and a boundary scan chain for the I/O cells. A boundary scan chain of a memory die layer includes a scan chain portion for each of the I/O cells, the scan chain portion for an I/O cell including a first scan logic multiplexer a scan logic latch, an input of the scan logic latch being coupled with an output of the first scan logic multiplexer, and a decoder to provide command signals to the boundary scan chain.

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Номер записи: 8
08-08-2013 дата публикации

Built-in test circuit and method

Номер: US20130201776A1
Автор: Fang Jao, Hung-jen Liao, Tzu-Kuei LIN, Yen-Huei Chen
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

A method of testing a semiconductor memory includes performing a first test of a first type prior to packaging the semiconductor memory. The first test of the first type includes generating a first plurality of addresses, decoding the first plurality of addresses to generate a second plurality of decoded addresses at a first decoder, and activating one of a plurality of rows or a plurality of columns of the semiconductor memory based on the second plurality of decoded addresses. The semiconductor memory is packaged after performing the first test of the first type.

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Номер записи: 9
08-08-2013 дата публикации

INTEGRATED CIRCUIT WITH MEMORY BUILT-IN SELF TEST (MBIST) CIRCUITRY HAVING ENHANCED FEATURES AND METHODS

Номер: US20130205179A1
Автор: Badgett Kevin, Chen Wei-yu, Hesse Kay
Принадлежит: Advanced Micro Devices, Inc.

Integrated circuits with memory built-in self test (MBIST) circuitry and methods are disclosed that employ enhanced features. In one aspect of the invention, an integrated circuit is provided having MIBST circuitry configured to serially test multiple arrays of memory elements within a component of the integrated circuit and to also conduct parallel initialization of the serially tested arrays. In another aspect of the invention, the MBST circuitry is used set the memory elements of the arrays to a first state and then to an inverse state during a burn-in operation to maintain each of the two opposing states for a desired time in order to either force a failure of the integrated circuit component or produce a pre-stressed component beyond an infancy stage. 1. A method of initializing an integrated circuit (IC) , the method comprising:providing the IC with a plurality of functional units, each functional unit including a plurality of arrays of memory elements each associated with one or more of a plurality of memory built-in self test (MBIST) slave circuits, wherein the plurality of memory MBIST circuits are configured to communicate with a MBIST master circuit;the MBIST master circuit sending a global initialization command to the plurality of MBIST slave circuits to commence the parallel initialization of the plurality of arrays of the plurality of functional units; andthe plurality of MBIST slave circuits providing initialization data to the plurality of arrays of the plurality of functional units in parallel to set the memory elements of the plurality of arrays of the plurality of functional units to an initialization state.2. The method of claim 1 , wherein the plurality of functional units includes a unified L2 Cache claim 1 , an Instruction Cache claim 1 , a Decoder unit claim 1 , a Branch Predication unit claim 1 , a Floating Point unit claim 1 , an Execution unit and a Load/Store unit claim 1 , and wherein the method further comprises: providing the IC with ...

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Номер записи: 10
05-09-2013 дата публикации

Latency Detection in a Memory Built-In Self-Test by Using a Ping Signal

Номер: US20130232385A1
Автор: Hesse Kay, Periyacheri Suresh
Принадлежит: Advanced Micro Devices, Inc.

In a complex semiconductor device including embedded memories, the round trip latency may be determined during a memory self-test by applying a ping signal having the same latency as control and failure signals used during the self-test. The ping signal may be used for controlling an operation counter in order to obtain a reliable correspondence between the counter value and a memory operation causing a specified memory failure. 111.-. (canceled)12. A method of performing a memory self-test of a memory portion of a semiconductor device , the method comprising:determining a round trip latency of control signals and a failure signal exchanged between said memory portion and a memory built-in self-test (MBIST) circuit prior to a first run of a test algorithm, said test algorithm causing said MBIST circuit to perform a plurality of memory operations and compare a result data of said plurality of memory operations with a reference data to determine a plurality of memory failures, wherein determining said round trip latency comprises generating a ping signal and conveying said ping signal on one or more signal lines used for conveying said control and failure signal; andobtaining a failure bitmap of said memory portion for a selected one of said plurality of memory failures on the basis of said round trip latency by performing a second run of said test algorithm.13. (canceled)14. The method of claim 12 , wherein generating said ping signal comprises generating a control signal combination not used for performing said first and second runs of said test algorithm.15. The method of claim 14 , wherein generating said ping signal further comprises decoding said control signal combination into a single signal at said memory portion so as to impart substantially the same latency to said single signal and said control signals to be transferred to said memory portion for performing said first and second runs.16. The method of claim 15 , wherein generating said ping signal further ...

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Номер записи: 11
05-09-2013 дата публикации

MEMORY DEVICES, TESTING SYSTEMS AND METHODS

Номер: US20130232386A1
Автор: Shore Michael A.
Принадлежит: MICRON TECHNOLOGY, INC.

Testing systems and methods, as well as memory devices using such testing systems and methods, may facilitate testing of memory devices using a read-modify-write test procedure. One such testing system receives a signal indicative of at least some of a plurality of bits of data read from an address differing from each other, and then masks subsequent write operations at the same address. Therefore, any address at which the bits of read data do not all have the same value may be considered to be faulty. Failure data from the test can therefore be stored in the same array of memory cells that is being tested. 1. An apparatus comprising:error detect circuitry configured to provide an error signal having a value indicating an error responsive to detecting a read data error associated with a memory cell of an array of memory cells; anda write mask circuit configured to provide a write mask signal responsive to receiving the error signal having the value indicating the error.2. The apparatus of claim 1 , wherein the error detect circuitry is further configured provide the error signal having a value indicating claim 1 , no error responsive to detecting correct read data associated with the memory cell of the array of memory cells.3. The apparatus of claim 2 , wherein the write mask circuit is further configured to inhibit provision of a write mask signal responsive to the error signal have the value indicating no error.4. The apparatus of claim 1 , wherein the write mask circuit is further configured to provide the write mask signal based on an external write mask signal.5. The apparatus of claim 1 , further comprising reset logic configured to provide a reset signal responsive to a test enable signal claim 1 , wherein the write mask circuit is configured to reset the write mask signal responsive to the reset signal.6. The apparatus of claim 1 , wherein the write mask circuit comprises a latch configured to latch an internal write mask signal having a value based on the ...

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Номер записи: 12
12-09-2013 дата публикации

DIRECT RELATIVE MEASUREMENT OF MEMORY DURABILITY

Номер: US20130235649A1
Автор: Haukness Brent Steven, Lindstadt Eric, Tringali J. James
Принадлежит: RAMBUS INC.

Disclosed is a memory including a plurality of resistive change memory cells, including at least a first group and a second group of the memory cells and a comparison circuit configured to conduct a direct relative comparison of a remaining endurance of the first group of memory cells to a remaining endurance of the second group of memory cells. 1. A method comprising:selecting a first group of memory cells in a memory;while the first group of memory cells are in a predetermined test state, measuring a first metric indicative of a remaining endurance of the first group of memory cells;selecting a second group of memory cells in the memory;while the second group of memory cells are in the predetermined test state, measuring a second metric indicative of a remaining endurance of the second group of memory cells;comparing the first and second metrics; andforming a result responsive to the comparing step.2. The method of wherein the test state is a high resistance state.3. The method of wherein the first and second metrics are measured concurrently.4. The method of wherein the first and second metrics are measured sequentially.5. The method of wherein measuring the first and second metrics comprises directly measuring at least one respective current in each of the first and second groups of memory cells.6. The method of wherein measuring at least one respective current comprises measuring bit line currents claim 2 , word line currents claim 2 , global bit line currents or source line currents in each of the first and second groups of memory cells.7. The method of wherein the result comprises a binary swap signal claim 2 , the swap signal having a first state indicating that the first group of memory cells has a relatively better remaining endurance than the second group of memory cells claim 2 , and a second state indicating that the second group of memory cells has a relatively better remaining endurance than the first group of memory cells.8. The method of and further ...

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Номер записи: 13
19-09-2013 дата публикации

Method and Apparatus for Shortened Erase Operation

Номер: US20130242665A1
Автор: Chang-Ting Chen, Chin-Hung Chang, Chun-Hsiung Hung, Ken-Hui Chen, Kuen-Long Chang, Nai-Ping Kuo
Принадлежит: Macronix International Co Ltd

A nonvolatile memory array has a multiple erase procedures of different durations. A block of memory cells of the array can be erased by one of the different erase procedures.

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Номер записи: 14
10-10-2013 дата публикации

Semiconductor device having plural data input/output terminals

Номер: US20130265831A1
Автор: Teppei MIYAJI, Yoshinori Matsui
Принадлежит: Elpida Memory Inc

Disclosed herein is a device that includes a plurality of first terminals; a first circuit including a plurality of first nodes; a buffer circuit including a plurality of second nodes connected to the first terminals through a plurality of first interconnection lines, respectively, and a plurality of third nodes connected to the first nodes of the first circuit through a plurality of second interconnection lines, respectively; and a second circuit configured to perform at least one of first and second operations. The first operation is such that a plurality of first signals, that appear respectively on the first interconnection lines, are outputted in series, and the second operation is such that a plurality of second signals, that are supplied in series, are transferred respectively to the first interconnection lines.

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Номер записи: 15
05-12-2013 дата публикации

Data processing device, microcontroller, and self-diagnosis method of data processing device

Номер: US20130325206A1
Автор: Akira HOSOTANI
Принадлежит: Renesas Electronics Corp

A data processing device according to the present invention includes a memory, an arithmetic circuit that accesses the memory by outputting an access control signal CTRL that controls access to the memory, a first data storage unit that stores first data used when a self-diagnosis is performed, a read-modify-write circuit that generates second data by replacing a part of the first data stored in the first data storage unit with modify data outputted from the arithmetic circuit, and a determination unit that diagnoses a failure of the read-modify-write circuit by comparing the second data with an expected value.

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Номер записи: 16
06-02-2014 дата публикации

System and method to perform scan testing using a pulse latch with a blocking gate

Номер: US20140035645A1
Автор: Kashyap R. Bellur, Venkatasubramanian Narayanan
Принадлежит: Qualcomm Inc

A system and method to perform scan testing using a pulse latch with a blocking gate is disclosed. In a particular embodiment, a scan latch includes a pulse latch operable to receive data while a pulse clock signal has a first logical clock value and a blocking gate coupled to an output of the pulse latch. The blocking gate is operable to propagate the data from the output of the pulse latch while the pulse clock signal has a second logical clock value.

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Номер записи: 17
06-02-2014 дата публикации

Non-Volatile Memory (NVM) with Imminent Error Prediction

Номер: US20140040687A1
Автор: Eguchi Richard K., HADAD DANIEL, He Chen, II Jon W., PROSPERI KATRINA M., Weilmann
Принадлежит:

A non-volatile memory system includes a memory array and a memory controller. The memory controller is configured to perform a first array integrity read operation of the array until an error is detected. The controller is also configured to determine that the error is not error correction code (ECC) correctable. A first word line voltage associated with the error is characterized as being a first threshold voltage. The controller is further configured to perform a second array integrity read operation of the array. The second array integrity read operation includes reading the array with a word line read voltage that is offset from the first threshold voltage and is based on a predetermined width offset reference value. Finally, the controller is configured to check a check sum value resulting from the second array integrity read operation to determine when an imminent failure in the memory array is indicated. 1. A method for determining an imminent failure of a non-volatile memory array , the method comprising:performing a first array integrity read operation of the non-volatile memory array until an error is detected;determining that the error is not error correction code (ECC) correctable, wherein a first word line voltage associated with the error is characterized as being a first threshold voltage;performing a second array integrity read operation of the non-volatile memory array, the second array integrity read operation comprising reading the array with a word line read voltage that is offset from the first threshold voltage and based on a predetermined width offset reference value; andchecking a check sum value resulting from the second array integrity read operation, wherein when the check sum value is equal to a predetermined check sum value, there is not imminent failure in the memory array, and wherein when the check sum value is not equal to the predetermined check sum value, then there is imminent failure in the non-volatile memory array.2. The method ...

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Номер записи: 18
27-03-2014 дата публикации

Method, system and apparatus for evaluation of input/output buffer circuitry

Номер: US20140089752A1
Автор: Christopher J. Nelson, David J. Zimmerman, Pete D. Vogt, Tak M. Mak
Принадлежит: Intel Corp

Techniques and mechanisms for evaluating I/O buffer circuits. In an embodiment, test rounds are performed for a device including the I/O buffer circuits, each of the test rounds comprising a respective loop-back test for each of the I/O buffer circuits. Each of the test rounds corresponds to a different respective delay between a transmit clock signal and a receive clock signal. In another embodiment, a first test round indicates a failure condition for at least one I/O buffer circuit and a second test round indicates the failure condition for each of the I/O buffer circuits. Evaluation of the I/O buffer circuits determines whether the device satisfies a test condition, where the determining is based on a difference between the delay corresponding to the first test round and the delay corresponding to the second test round.

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Номер записи: 19
06-01-2022 дата публикации

REPAIR CIRCUIT, MEMORY, AND REPAIR METHOD

Номер: US20220005544A1
Автор: Zhang Liang
Принадлежит:

The repair circuit is disposed in a memory including a normal memory area and a redundant memory area including a target repair unit immediately adjacent to the normal memory area, and the repair circuit being configured to control the target repair unit to repair an abnormal memory cell in the normal memory area. The repair circuit includes: a first control circuit, configured to receive signals at a target number of bits from low to high in a row address, process the received signals to obtain a control result, and output the control result, where the target number is associated with a number of Word Lines in the target repair unit; and a repair determination circuitry, connected to an output terminal of the first control circuit, and configured to receive the control result and output, in combination with the control result, a repair signal indicating whether to perform a repair operation. 1. A repair circuit , disposed in a memory comprising a normal memory area and a redundant memory area , wherein the redundant memory area comprises a target repair unit immediately adjacent to the normal memory area , the repair circuit is configured to control the target repair unit to repair an abnormal memory cell in the normal memory area , and the repair circuit comprises:a first control circuit, configured to receive signals at a target number of bits from low to high in a row address, process the signals at the target number of bits to obtain a control result, and output the control result, wherein the target number is associated with a number of Word Lines (WLs) in the target repair unit; anda repair determination circuitry, connected to an output terminal of the first control circuit, and configured to receive the control result and output, in combination with the control result, a repair signal indicating whether to perform a repair operation.2. The repair circuit of claim 1 , wherein the repair determination circuitry comprises:a comparison circuit, configured to ...

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Номер записи: 20
07-01-2021 дата публикации

SCALABLE INFIELD SCAN COVERAGE FOR MULTI-CHIP MODULE FOR FUCTIONAL SAFETY MISSION APPLICATION

Номер: US20210003629A1
Автор: Azam Asad, Bhaskar Rajesh, Carrieri Enrico, Srivastava Amit Kumar
Принадлежит: Intel Corporation

An apparatus of a multi-chip package (MCP) of a functional safety system, comprises a processor to be configured as a master chip in a master-slave arrangement with a slave chip in the MCP, and a memory coupled to the processor to store one or more infield test scan patterns. The processor includes a bock to couple the master chip to the slave chip via a high-speed input/output (IO) interface to retrieve the one or more infield test scan patterns from the memory via the master chip, and to provide the one or more infield test scan patterns to the slave chip via the high-speed IO interface in response to the functional safety system entering an infield test mode. 2. The apparatus of claim 1 , wherein the indication to configure I3C interface to enable multilane comprises an indication of using four serial data lanes.3. The apparatus of claim 1 , wherein the first chip is further configured to transmit error correction data using multiple lanes after the transmission of the data to the second chip using multiple lanes.4. The apparatus of claim 3 , wherein the transmitted error correction data comprises a word for cyclic redundancy check (CRC WORD) which is transmitted over the first data lane.5. The apparatus of claim 4 , wherein the first chip is further configured to transmit HDR Exit data after the word for cyclic redundancy check (CRC WORD) over the first data lane to conclude the transmission.6. The apparatus of claim 1 , wherein the first chip is further configured to transmit the data to the second chip using multiple lanes with a duration of multiples of 10 serial clocks (SCL).7. The apparatus of claim 1 , wherein the first chip is further configured to transmit the data to the second chip in double data rate (DDR).8. The apparatus of claim 1 , wherein a plurality of data packets is transmitted to the second chip after the transmission of the Clear Command Channel (CCC) command.9. The apparatus of claim 1 , wherein the first chip is a master chip and the ...

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Номер записи: 21
03-01-2019 дата публикации

REGISTER ARRAY HAVING GROUPS OF LATCHES WITH SINGLE TEST LATCH TESTABLE IN SINGLE PASS

Номер: US20190004114A1
Автор: LI Xiaoxiao, LU YINPENG, Meng Chao, SUN JIAN
Принадлежит: GLOBALFOUNDRIES INC.

A register array includes a plurality of groups of latches. Each of the groups of latches includes a first latch, a second latch, and a test latch connected to the first latch and the second latch. During functional operation the first latch and the second latch process data, in response to the same read/write clock signal supplied simultaneously to the first read/write clock input and the second read/write clock input. During test operation a skewed test clock signal of an original test clock signal is supplied at different timings to the first latch, the second latch, and the test latch, and a single scan signal is input to the first latch. The single scan signal cascades from the first latch through the test latch to the second latch, and is output by the second latch, within a single cycle of the original test clock signal. 1. A register array comprising: a first latch;', 'a second latch; and', 'a test latch connected to the first latch and the second latch,, 'a plurality of groups of latches, each of the groups of latches comprisesduring functional operation the first latch and the second latch process data, in response to the same read/write clock signal, and a skewed test clock signal of an original test clock signal is supplied at different timings to the first latch, the second latch, and the test latch;', 'a single scan signal is input to the first latch; and', 'the first latch and the second latch are connected to the test latch to cause the single scan signal to cascade from the first latch through the test latch to the second latch, and be output by the second latch, to use a single test clock and the single scan signal to test both the first latch and the second latch within a single cycle of the original test clock signal., 'during test operation2. The register array according to claim 1 , the first latch and the second latch are physically symmetrical.3. The register array according to claim 1 , the first latch and the second latch each comprise a ...

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Номер записи: 22
13-01-2022 дата публикации

Low latency decoder for error correcting codes

Номер: US20220013187A1
Автор: Venugopal Santhanam
Принадлежит: Synopsys Inc

A method for error correction comprises receiving data at a first device, and decoding, by decoder circuitry of the first device, the data. Decoding the data comprises determining a first error location within the data, and determining a first error magnitude within the data in parallel with determining the first error location. Decoding the data further comprises performing error correction to generate the decoded data based on the first error location and the first error magnitude. The method further comprises transmitting the decoded data to a second device.

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Номер записи: 23
13-01-2022 дата публикации

MEMORY DEVICE

Номер: US20220013188A1
Автор: Kim Sang Hwan
Принадлежит: SK HYNIX INC.

A memory device includes a first pad, a second pad, and a double data rate (DDR) test controller. The first pad may receive a write enable signal. The second pad may receive a data strobe signal. The DDR test controller is connected to the first pad and the second pad and outputs an internal write enable signal and an internal data strobe signal. The DDR test controller generates the internal data strobe signal based on the write enable signal received through the first pad, in at least a portion of a DDR test operation of the memory device. 1. A memory device comprising:a first pad capable of receiving a write enable signal;a second pad capable of receiving a data strobe signal; anda double data rate (DDR) test controller connected to the first pad and the second pad and configured to output an internal write enable signal and an internal data strobe signal,wherein the DDR test controller generates the internal data strobe signal based on the write enable signal received through the first pad, in at least a portion of a DDR test operation of the memory device.2. The memory device of claim 1 , wherein the DDR test controller outputs the write enable signal received through the first pad as the internal write enable signal claim 1 , and outputs the data strobe signal received through the second pad as the internal data strobe signal claim 1 , during a normal operation of the memory device.3. The memory device of claim 1 , wherein the DDR test controller outputs the write enable signal received through the first pad as the internal write enable signal in a period in which a command or an address is input during the DDR test operation.4. The memory device of claim 1 , wherein the DDR test controller outputs the write enable signal received through the first pad as the internal data strobe signal in a period in which data is input during the DDR test operation.5. The memory device of claim 1 , wherein the DDR test controller comprises:a multiplexer connected to the ...

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Номер записи: 24
07-01-2021 дата публикации

TEST MODES FOR A SEMICONDUCTOR MEMORY DEVICE WITH STACKED MEMORY CHIPS USING A CHIP IDENTIFICATION

Номер: US20210005274A1
Автор: LEE Seong Ju
Принадлежит: SK HYNIX INC.

A semiconductor system includes a first semiconductor device and a second semiconductor device. The first semiconductor device controls a test mode. The first semiconductor device outputs a chip identification and receives external data. The second semiconductor device includes a plurality of memory chips. At least one of the plurality of memory chips are activated based on the chip identification to store input data into each of the plurality of memory chips that have been activated while a write operation is performed in the test mode. At least two of the plurality of memory chips are activated based on the chip identification to output the stored input data as the external data while a read operation is performed in the test mode. 1. A semiconductor device comprising:a first group of memory chips vertically stacked, wherein one or more memory chips of the first group are activated during a write operation in a test mode to store input data into each of the memory chips that have been activated in the first group, and the input data stored in one or more of the memory chips of the first group, which is activated by a chip identification, is outputted as first external data through a first main pad during a read operation; anda second group of memory chips vertically stacked, wherein one or more memory chips of the second group are activated during the write operation in the test mode to store the input data into each of the memory chips that have been activated in the second group, and the input data stored in one or more of the memory chips of the second group, which is activated by the chip identification, is outputted as second external data through a second main pad during the read operation.2. The semiconductor device of claim 1 , wherein the first group of memory chips include:a first memory chip configured to store the input data during the write operation and configured to transmit the stored input data to a first sub-pad and to output the input data ...

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Номер записи: 25
02-01-2020 дата публикации

SIMULTANEOUS SCAN CHAIN INITIALIZATION WITH DISPARATE LATCHES

Номер: US20200005883A1
Автор: Agrawal Mitesh, GEUKES BENEDIKT, MONDAL Krishnendu
Принадлежит:

Provided is an integrated circuit that includes a reset electrically connected to a select line of a multiplexer and an OR gate. The multiplexer receives data from a power source. The multiplexer and the OR gate comprise a circuit. A clock is electrically connected to the OR gate. The OR gate is electrically connected to a clock input of a latch. The latch includes the clock input, a scan enable input, a data input, and a data output. A regular logic data path is electrically connected to the multiplexer, and the multiplexer is further electrically connected to the data port of the latch. 1. A method , comprising:determining that an integrated circuit is in a test mode, the integrated circuit including an initialization circuit and two or more disparate latches, the initialization circuit comprising a multiplexor and an OR gate, wherein:a reset is electrically connected to a select line of the multiplexer and a first input of the OR gate,a clock is electrically connected to a second input of the OR gate,an output of the OR gate is electrically connected to a clock input of a first latch,a logic data path is electrically connected to a first input of the multiplexer, andan output of the multiplexer is connected to a data input of the first latch;enabling, in response to determining that the integrated circuit is in the test mode, a data stream to be shifted from one latch of the two or more latches to another latch of the two or more latches;setting a reset pin; andinitializing the two or more latches.2. The method of claim 1 , wherein a data output of the first latch is electrically connected to the logic data path.3. The method of claim 1 , wherein the integrated circuit is included in a clock domain.4. The method of claim 1 , wherein the multiplexor receives data from a power source5. The method of claim 1 , wherein the two or more latches are selected from the group consisting of a high-performance claim 1 , high-efficiency claim 1 , set-reset claim 1 , positive ...

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Номер записи: 26
02-01-2020 дата публикации

ERASE PAGE CHECK

Номер: US20200005884A1
Автор: Batutis Devin, Luo Ting, Singidi Harish Reddy, Stoller Scott Anthony, Tanpairoj Kulachet, Thomson Preston Allen
Принадлежит:

Disclosed in some examples are methods, systems, memory devices, and machine readable mediums for performing an erase page check. For example, in response to an unexpected (e.g., an asynchronous) shutdown, the memory device may have one or more cells that did not finish programming. The memory device may detect these cells and erase them or mark them for erasure. 1identifying a NAND memory cell of the memory device to test for an incomplete programming, the memory cell configured as a multi-level cell;shifting a read voltage used to read a first portion of the memory cell a predetermined magnitude toward zero, the read voltage for the first portion having a lowest read voltage of a plurality of read voltages used to read other portions of the memory cell;reading a value in the first portion of the memory cell using the shifted read voltage;determining that the memory cell was incompletely programmed based upon the value;in response to determining that the memory cell was incompletely programmed, mark the memory cell as incompletely programmed; andwherein shifting the read voltage and reading the value is a user-mode read operation.. A method performed by a NAND memory device, the method comprising: This application is continuation of U.S. application Ser. No. 16/129,422, filed Sep. 12, 2018, which is a continuation of U.S. application Ser. No. 15/692,962, filed Aug. 31, 2017, now issued as U.S. Pat. No. 10,096,380, all of which are incorporated herein by reference in their entireties.Memory devices are typically provided as internal, semiconductor, integrated circuits in computers or other electronic devices. There are many different types of memory, including volatile and non-volatile memory.Volatile memory requires power to maintain its data, and includes random-access memory (RAM), dynamic random-access memory (DRAM), or synchronous dynamic random-access memory (SDRAM), among others.Non-volatile memory can retain stored data when not powered, and includes flash ...

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Номер записи: 27
03-01-2019 дата публикации

SEMICONDUCTOR DEVICE, SEMICONDUCTOR MEMORY AND METHOD FOR TESTING RELIABILITY OF SEMICONDUCTOR DEVICE

Номер: US20190006023A1
Автор: Sugahara Takahiko
Принадлежит: MegaChips Corporation

A memory controller performs a reliability test only on a memory array out of the memory array and a random number generator on receipt of a memory test command from a testing device while performing a reliability test only on the random number generator out of the memory array and the random number generator on receipt of a random number test command from the testing device. 1. A semiconductor device comprising:random number generator circuitry that generates a random number; andmemory controller circuitry connected to the random number generator circuitry, the memory controller circuitry including a self-test circuit that performs a reliability test of the random number generator circuitry,wherein the self-test circuit:inputs a predetermined control signal to the random number generator circuitry to cause the random number generator circuitry to generate a random number value, andchecks irreproducibility of random number values, which are generated by the random number generator circuitry.2. The semiconductor device according to claim 1 , further comprising:a storage, whereinthe self-test circuit stores the random number value generated by the random number generator circuitry in the storage, and checks irreproducibility of the random number values generated by the random number generator circuitry based on the random number value read from the storage.3. The semiconductor device according to claim 2 , whereina test command received from an external device by the semiconductor device contains count information for specifying a number of counts to cause the random number generator circuitry to generate the random number values, andthe self-test circuit extracts the count information from the test command and causes the random number generator circuitry to sequentially generate a plurality of random number values based on the count information.4. The semiconductor device according to claim 3 , whereinthe self-test circuit (i) starts checking of the random number ...

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Номер записи: 28
02-01-2020 дата публикации

AN APPARATUS AND METHOD FOR ELECTRICAL TEST PREDICTION

Номер: US20200006165A1
Автор: TUROVETS Igor
Принадлежит:

A test site and method are herein disclosed for predicting E-test structure (in-die structure) and/or device performance. The test site comprises an E-test structure and OCD-compatible multiple structures in the vicinity of the E-test structure to allow optical scatterometry (OCD) measurements. The OCD-compatible multiple structures are modified by at least one modification technique selected from (a) multiplication type modification technique, (b) dummification type modification technique, (c) special Target design type modification technique, and (d) at least one combination of (a), (b) and (c) for having a performance equivalent to the performance of the E-test structure. 1. A method for predicting E-test structure (in-die structure) and/or device performance comprising:providing an E-test structure and OCD-compatible multiple structures in the vicinity of said E-test structure to allow optical scatterometry (OCD) measurements;(ii) conducting optical scatterometric (OCD) measurements on said multiple structures;(iii) conducting electrical measurements on said E-test structure;(iv) establishing correlations between an OCD measurement data obtainable via said OCD measurements on said multiple structures and electrical parameters obtainable via said electrical measurements on said E-test structure; and(v) using said correlations for predicting the performance of said E-test structure.2. The method of comprising modifying said OCD-compatible multiple structures by applying at least one modification technique selected from:(a) multiplication type modification technique;(b) dummification type modification technique;(c) special Target design type modification technique; and(d) at least one combination of (a), (b) and (c).3. The method of claim 2 , wherein modifying said OCD-compatible multiple structures by said multiplication type modification technique comprising creating multiple structures identical to and in the vicinity of said E-test structure.4. The method of ...

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Номер записи: 29
20-01-2022 дата публикации

LEAKAGE SOURCE DETECTION

Номер: US20220020446A1
Автор: Aella Pavan Reddy K., Kamana Rajesh, Kotti Radhakrishna, Majumdar Amitava, White Patrick Daniel
Принадлежит:

Methods, systems, and devices for leakage source detection are described. In some cases, a testing device may scan a first set of access lines of a memory die that have a first length and a second set of access lines of the memory die that have a second length different than the first length. The testing device may determine a first error rate associated with the first set of access lines and a second error rate associated with the second set of access lines. The testing device may categorize a performance of the memory die based on the first and second error rates. In some cases, the testing device may determine a third error rate associated with a type of error based on the first and second error rates and may categorize the performance of the memory die based on the third error rate. 1. (canceled)2. A method , comprising:scanning, with an electron beam, a first set of conductive paths of a memory die having a first length and a second set of conductive paths of the memory die having a second length different than the first length;determining a first error rate associated with the first set of conductive paths based at least in part on scanning the first set of conductive paths; anddetermining a second error rate associated with the second set of conductive paths based at least in part on scanning the second set of conductive paths.3. The method of claim 2 , further comprising:determining a third error rate associated with a first type of error based at least in part on the first error rate of the first set of conductive paths and the second error rate of the second set of conductive paths; anddetermining a fourth error rate associated with a second type of error different than the first type of error based at least in part on the first error rate of the first set of conductive paths and the second error rate of the second set of conductive paths.4. The method of claim 3 , wherein:the first type of error comprises one or more errors that occur because of shorting ...

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Номер записи: 30
27-01-2022 дата публикации

METHOD AND DEVICE FOR PROCESSING DATA STORED IN A MEMORY UNIT

Номер: US20220028472A1
Автор: Jauss Manuel, Kartal Mustafa
Принадлежит:

A method for processing data stored in a memory unit. The method includes the following steps: ascertaining a randomly or pseudo-randomly formed test pattern, which characterizes at least one first subarea of a memory area of the memory unit, forming, as a function of the test pattern, a test variable associated with data stored in the at least one first subarea. 116-. (canceled)17. A method for processing data stored in a memory unit , comprising the following steps:ascertaining a randomly or pseudo-randomly formed test pattern, which characterizes at least one first subarea of a memory area of the memory unit; andforming, as a function of the test pattern, a test variable associated with data stored in the at least one first subarea.18. The method as recited in claim 17 , further comprising:a) storing at least temporarily the test variable; and/orb) comparing the test variable with a reference test variable for the at least one first subarea.19. The method as recited in claim 17 , wherein the ascertainment of the test pattern includes at least one of the following: (a) random or pseudo-random formation of the test pattern claim 17 , b) receiving the test pattern from an external unit claim 17 , c) reading out the test pattern from the memory unit and/or from a further memory unit claim 17 , d) deriving the test pattern from a test pattern base data.20. The method as recited in claim 19 , wherein the formation of the test pattern includes the following steps: providing a random or pseudo-random sequence of numbers claim 19 , ascertaining the at least one first subarea as a function of at least one first part of the sequence of numbers claim 19 , a start address of the first subarea in the memory area being formed as a function of the first part of the sequence of numbers.21. The method as recited in claim 17 , wherein the test pattern characterizes claim 17 , in addition to the first subarea claim 17 , at least one second subarea claim 17 , the at least one further ...

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Номер записи: 31
14-01-2016 дата публикации

Semiconductor memory device and memory system

Номер: US20160012916A1
Автор: Takuya Haga, Tokumasa Hara
Принадлежит: Toshiba Corp

According to one embodiment, a semiconductor memory device includes: transistors; NAND strings; a bit line; a source line; and string sets. The transistors are stacked above a semiconductor substrate. In one of the string sets, a first transistor in a first NAND string has a first threshold, and a first transistor in a second NAND string has a second threshold lower than the first threshold.

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Номер записи: 32
14-01-2016 дата публикации

METHOD FOR TESTING ARRAY FUSE OF SEMICONDUCTOR APPARATUS

Номер: US20160012917A1
Автор: KANG Jae Seok
Принадлежит:

Provided is a method for testing an array fuse of a semiconductor apparatus. The method may perform a series of operations for testing an array fuse block of the semiconductor apparatus as a test program is executed. The series operations may include the following steps: generating a test source file containing information for accessing the array fuse block; generating a test vector using the test source file; extracting repair confirmation information by performing a simulation using the test vector; to extracting a repair confirmation information expected value from the test source file; and determining a pass or fail by comparing the repair confirmation information to the repair confirmation information expected value. 1. A method for testing an array fuse of a semiconductor apparatus , which performs a series of operations for testing an array fuse block of the semiconductor apparatus as a test program is executed ,wherein the series operations comprise the steps:generating a test source file containing information for accessing the array fuse block;generating a test vector using the test source file;extracting repair confirmation information by performing a simulation using the test vector;extracting a repair confirmation information expected value from the test source file; anddetermining a pass or fail by comparing the repair confirmation information to the repair confirmation information expected value.2. The method according to claim 1 , wherein the test source file comprises information for accessing all unit fuses of the array fuse block.3. The method according to claim 2 , wherein the unit fuses are arranged in substantially a matrix shape.4. The method according to claim 2 , wherein the test source file includes information for accessing and rupturing all unit fuses.5. The method according to claim 2 ,wherein the unit fuses of the array fuse block are accessed through input/output pads of the semiconductor apparatus, andwherein the test source file ...

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Номер записи: 33
14-01-2021 дата публикации

RECOVERY MANAGEMENT OF RETIRED SUPER MANAGEMENT UNITS

Номер: US20210012850A1
Автор: Huang Jian, Zhou Zhenming
Принадлежит:

A system includes a memory component, and a processing device coupled with the memory component. The processing device to identify a group of management units of the memory component, wherein the group of management units is included in a set of retired groups of management units, select a management unit from the group of management units, perform a media integrity check on the management unit to determine a failed bit count of the management unit, and in response to the failed bit count of the management unit failing to satisfy a threshold criterion, remove the group of management units from the set of retired groups of management units. 1. A system comprising:a memory component; and identify a group of management units of the memory component, wherein the group of management units is included in a set of retired groups of management units;', 'select a management unit from the group of management units;', 'perform a media integrity check on the management unit to determine a failed bit count of the management unit; and', 'remove the group of management units from the set of retired groups of management units based on whether the failed bit count satisfies a threshold criterion., 'a processing device, operatively coupled with the memory component, to2. The system of claim 1 , wherein to perform the media integrity check the processing device is to:write a set of random to the management unit;read the set of random data from the management unit; anddetermine the failed bit count of the read operation, wherein the failed bit count indicates a number of bits that were not properly read from the management unit.3. The system of claim 2 , wherein to perform the media integrity check the processing device is further to:write an inverse of the set of random data to the management unit;read the inverse of the set of random data from the management unit; anddetermine the failed bit count based on the read of the set of random data and the read of the inverse of the set of ...

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Номер записи: 34
14-01-2021 дата публикации

SEMICONDUCTOR MEMORY DEVICE, MEMORY CONTROLLER, AND ERROR NOTIFICATION METHOD

Номер: US20210012852A1
Автор: Maeda Masaki, TANAKA Kazuhito
Принадлежит: Panasonic Intellectual Property Management Co., Ltd.

A semiconductor memory device includes a data bus terminal group for outputting read data to an external device or inputting write data from an external device, a first terminal from or into which 1-bit data is output or input, a DBI circuit that executes a Data Bus Inversion (DBI) function, an error detection circuit that detects an internal error, and an information superimposing circuit that superimposes predetermined output information onto the 1-bit data to be output from the first terminal and the read data to be output from the data bus terminal group. The predetermined output information includes first output information indicating whether or not an output bit pattern of the data bus terminal group is inverted, and second output information indicating whether or not an internal error has been detected by the error detection circuit. 1. A semiconductor memory device , comprising:a data bus terminal group for outputting read data to an external device or inputting write data from an external device;a first terminal from or into which 1-bit data is output or input;a DBI circuit that executes a Data Bus Inversion (DBI) function;an error detection circuit that detects an internal error; andan information superimposing circuit that superimposes predetermined output information onto the 1-bit data to be output from the first terminal and the read data to be output from the data bus terminal group,wherein the predetermined output information includes:first output information indicating whether or not an output bit pattern of the data bus terminal group is inverted; andsecond output information indicating whether or not an internal error has been detected by the error detection circuit.2. The semiconductor memory device according to claim 1 ,wherein the information superimposing circuit further extracts predetermined input information from the 1-bit data input to the first terminal and an input bit pattern serving as the write data input to the data bus terminal ...

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Номер записи: 35
14-01-2021 дата публикации

Method and Apparatus for enabling Multiple Return Material Authorizations (RMAs) on an Integrated Circuit Device

Номер: US20210012855A1
Автор: Chen Kenneth, Draper Andrew Martyn, Lau Wei Chun, Lu Ting, Menon Sankaran M.
Принадлежит:

An integrated circuit (IC) device configured for multiple return material authorizations (RMAs) is provided. The IC device includes an asset and a return material authorization (RMA) counter fuse including a first fuse, a second fuse, and a third fuse. The IC device enters an RMA state in response to blowing the first fuse, a second state in response to blowing the second fuse, and the RMA state in response to blowing the third fuse. 1. An integrated circuit (IC) device configured for multiple return material authorizations (RMAs) , the IC device comprising:an asset disposed on the IC device; anda return material authorization (RMA) counter fuse comprising a first fuse, a second fuse, and a third fuse, wherein the IC device enters an RMA state that disables access to the asset in response to blowing the first fuse, wherein the IC device enters a second state in response to blowing the second fuse, and wherein the IC device re-enters the RMA state in response to blowing the third fuse.2. The IC device of claim 1 , wherein the asset comprises circuitry claim 1 , nonvolatile code claim 1 , or a field programmable gate array circuit design claim 1 , or a combination thereof.3. The IC device of claim 1 , wherein the IC device blows the second fuse during a time period beginning after the first fuse is blown and wherein the IC device blows the third fuse during a time period beginning after the second fuse is blown.4. The IC device of claim 1 , wherein the IC device enables access to the asset in response to the IC device leaving the RMA state.5. The IC device of claim 1 , wherein the third fuse is blown during a time period beginning after the first fuse is blown.6. The IC device of claim 1 , wherein a status of a fuse on the RMA counter fuse indicates a state of the IC device.7. The IC device of claim 1 , wherein the IC device indicates an amount of times that the IC device has been in the RMA state based on a status of at least one of the first fuse claim 1 , the ...

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Номер записи: 36
09-01-2020 дата публикации

TEST CONTROL CIRCUIT, SEMICONDUCTOR MEMORY APPARATUS AND SEMICONDUCTOR SYSTEM USING THE TEST CONTROL CIRCUIT

Номер: US20200013475A1
Автор: CHAE Haeng Seon
Принадлежит: SK HYNIX INC.

A test control circuit includes a test mode generation circuit. The test mode generation circuit may be configured to generate, while in a fast access mode, a fast test mode signal based on information included in one of a plurality of mode signals and a fast set signal. The test mode generation circuit may be configured to generate, while in a normal mode, a normal test mode signal based on information included in two or more mode signals from the plurality of mode signals and a normal set signal. 1. A test control circuit comprising:a control signal generation circuit configured to generate a normal set signal and a fast set signal based on a test command signal, a command pulse, and a fast access signal;a decoding circuit configured to generate a plurality of mode signals based on a plurality of the test command signals; anda test mode generation circuit configured to generate a normal test mode signal based on two or more mode signals and the normal set signal, and generate a fast test mode signal based on one mode signal and the fast set signal.2. The test control circuit of claim 1 , wherein the control signal generation circuit includes:an encoder configured to generate a pre-decoding signal by encoding the test command signal;a normal set signal generator configured to generate the normal set signal based on the pre-decoding signal, the command pulse, and the fast access signal; anda fast set signal generator configured to generate the fast set signal based on the normal set signal and the fast access signal.3. The test control circuit of claim 2 , wherein the normal set signal generator is configured to generate the normal set signal based on the pre-decoding signal and the command pulse claim 2 , or based on the command pulse and the fast access signal.4. The test control circuit of claim 2 , wherein the control signal generation circuit is configured to further generate a latch reset signal by delaying the normal set signal claim 2 , and further generate ...

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Номер записи: 37
09-01-2020 дата публикации

REMOTE SSD DEBUG VIA HOST/SERIAL INTERFACE AND METHOD OF EXECUTING THE SAME

Номер: US20200013476A1
Автор: KONAN Andrei, PENIAZ Sergei
Принадлежит:

Memory systems and method of operating the same enable debugging of a memory system with vendor unique (VU) commands without using a physical cable connection to a debugging port on the memory system. In one aspect, a Universal Asynchronous Receiver-Transmitter (UART) protocol is serialized over a VU host protocol. In another aspect, Joint Test Action Group (JTAG) may be performed over UART or serial advanced technology attachment (SATA). 1. A method for debugging a memory system including a memory device , the method comprising:storing debugging logic in the memory device;transferring vendor unique (VU) commands from a host via a host protocol to the memory system without using a physical cable connection to a debug port on the memory system; anddebugging at least one component in the memory system in response to VU commands.2. The method of claim 1 , wherein the transferring comprises transferring the VU commands from a VU package residing in the host to core firmware in the memory system.3. The method of claim 1 , wherein the debugging comprises requesting debugging information from the debugging logic via core firmware.4. The method of claim 3 , wherein the debugging further comprises retrieving debugging information directly from the debugging logic in response to the instruction and transferring the retrieved debugging information to the host.5. The method of claim 3 , wherein the requesting of debugging information is performed from a VU package residing in the host.6. The method of claim 1 , wherein the memory system comprises a solid state drive (SSD) and the memory device comprises a NAND memory embodied in the SSD.7. The method of claim 1 , wherein the debugging logic comprises a Universal Asynchronous Receiver-Transmitter (UART) log.8. A memory system comprising:multiple firmware cores;a Universal Asynchronous Receiver-Transmitter (UART) serial hardware element in communication with each of the firmware cores;a memory device in which a UART log is stored ...

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Номер записи: 38
09-01-2020 дата публикации

MEMORY SYSTEM WITH DIAGNOSE COMMAND AND OPERATING METHOD THEREOF

Номер: US20200013477A1
Автор: JIN Young Tack
Принадлежит:

A memory system and an operating method thereof include: at least a CPU configured to generate a special command; at least a PCIe link coupled with the CPU, wherein the PCIe link includes at least a PCIe switch; and a plurality of memory devices connected with the PCIe switch, wherein each of the plurality of memory devices includes a memory controller, an operational mode switch, and a plurality of memory components, and the operational mode switch is configured to perform a loopback from the memory controller corresponding to the special command at loopback operational mode. 1at least a CPU configured to generate a special command;at least a PCIe link coupled with the CPU, wherein the PCIe link includes at least a PCIe switch; anda plurality of memory devices connected with the PCIe switch,wherein each of the plurality of memory devices includes a memory controller, an operational mode switch, and a plurality of memory components, and the operational mode switch is configured to perform a loopback from the memory controller corresponding to the special command at loopback operational mode.. A memory system comprising: This application is a continuation of U.S. patent application Ser. No. 15/812,472 filed on Nov. 14, 2017, which claims benefits of priority of U.S. Provisional Patent Application No. 62/477,319 filed on Mar. 27, 2017. The disclosure of each of the foregoing application is incorporated herein by reference in its entirety.Exemplary embodiments of the present invention relate to an apparatus of semiconductor memory storage system, and more particularly to diagnose SSD and an operation method thereof.The computer environment paradigm has shifted to ubiquitous computing systems that can be used anytime and anywhere. Due to this fact, the use of portable electronic devices s as mobile phones, digital cameras, and notebook computers has rapidly increased. These portable electronic devices generally use a memory system having memory devices, that is, a data ...

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Номер записи: 39
19-01-2017 дата публикации

NON-VOLATILE SEMICONDUCTOR STORAGE DEVICE AND METHOD OF TESTING THE SAME

Номер: US20170017543A9
Автор: MIYAGI Masanori, YAMASAKI Taro
Принадлежит:

Provided is a non-volatile semiconductor storage device which can be downsized with a simple circuit without impairing the function of an error correcting section, and a method of testing the non-volatile semiconductor storage device. An error correction circuit is configured to perform error detection and correction of merely the same number of bits as data bits, and a circuit for performing error detection and correction of check bits is omitted to downsize the circuit. A multiplexer for, in a testing state, replacing a part of the data bits read out from a storage element array with the check bits, and inputting the check bits to the error correction circuit is provided. Thus, error detection and correction of the check bits are performed to enable shipment inspection concerning the check bits as well. 1. A non-volatile semiconductor storage device , comprising:a non-volatile semiconductor storage element array for storing data bits and check bits, the non-volatile semiconductor storage element array comprising, as a basic unit, one unit including an m-data-bit storage element and an n-check-bit storage element;an error correction code generating circuit for generating an error correction code based on the data bits and the check bits of the one unit read out from the non-volatile semiconductor storage element array;a control signal generating circuit for outputting a control signal for switching between a first state and a second state;a multiplexer for inputting second state data including at least the check bits and first state data having, of the data bits, the same number of bits as the second state data, and selecting between the first state data and the second state data based on the control signal to output selected one of the first state data and the second state data; andan error correction circuit for performing error correction of merely the same number of bits as the data bits based on data of the data bits excluding the first state data, the ...

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Номер записи: 40
18-01-2018 дата публикации

PERSISTENT COMMAND PARAMETER TABLE FOR PRE-SILICON DEVICE TESTING

Номер: US20180018250A1
Автор: Bair Dean G., Gott Rebecca M., JR. Edward J., Kaminski, Lewis William J., Rayadurgam Chakrapani
Принадлежит:

Embodiments relate to pre-silicon device testing using a persistent command table. An aspect includes receiving a value for a persistent command parameter from a user. Another aspect includes determining whether the value of the persistent command parameter is greater than zero. Another aspect includes based on determining whether the value of the persistent command parameter is greater than zero, selecting a number of commands equal to the value of the persistent command parameter from a regular command table of a driver of a device under test. Another aspect includes adding the selected commands to the persistent command table of the driver. Another aspect includes performing testing of the device under test via the driver using only commands that are in the persistent command table of the driver. 1a memory; anda processor, communicatively coupled to the memory, the processor configured to perform a method comprising:executing, by the processor, testing logic for a pre-silicon device of a cache design in a virtual environment;obtaining, by the processor, a persistent command parameter and a repetitive sequence parameter having been specified for testing of a device under test, the testing of the device under test being via a single driver or multiple drivers of a same type;wherein the device under test is the pre-silicon device in the virtual environment, wherein a regular command table is defined as comprising a full set of available commands configured to test the pre-silicon device, wherein the persistent command table comprises a random subset of the available commands configured to test the pre-silicon device, wherein the persistent command parameter defines a number of the available commands to be in the persistent command table, wherein the repetitive sequence parameter defines whether the available commands in the persistent command table are to test the pre-silicon device in a repetitive manner or in a random order, wherein the available commands in the ...

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Номер записи: 41
19-01-2017 дата публикации

Built-in self-test (bist) engine

Номер: US20170018313A1
Автор: Aravindan J. BUSI, John R. Goss, Kiran K. Narayan, Krishnendu Mondal, Michael A. Ziegerhofer, Michael R. Ouellette, Paul J. Grzymkowski
Принадлежит: International Business Machines Corp

A BIST engine configured to store a per pattern based fail status during memory BIST run and related processes thereof are provided. The method includes testing a plurality of patterns in at least one memory device and determining which of the plurality of patterns has detected a fail during execution of each pattern. The method further includes storing a per pattern based fail status of each of the detected failed patterns.

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Номер записи: 42
19-01-2017 дата публикации

SEMICONDUCTOR DEVICES AND SEMICONDUCTOR SYSTEMS INCLUDING THE SAME

Номер: US20170018314A1
Автор: CHAE Haeng Seon
Принадлежит:

A semiconductor system may include a first semiconductor device and a second semiconductor device. The first semiconductor device may be configured to output command signals and setting signals. The second semiconductor device may be configured to decode the command signals, extract setting codes from the setting signals, and test a memory cell array accessed by address patterns during at least one operation section corresponding to the setting codes to confirm whether the memory cell array includes at least one failed memory cell. 1. A semiconductor system comprising:a first semiconductor device suitable for outputting command signals and setting signals; anda second semiconductor device suitable for decoding the command signals, suitable for extracting setting codes from the setting signals, and suitable for testing a memory cell array accessed by address patterns during at least one operation section corresponding to the setting codes to confirm whether the memory cell array includes at least one failed memory cell.2. The semiconductor system of claim 1 ,wherein the setting codes include a first setting code and a second setting code; andwherein the first and second setting codes are included in the setting signals outputted from the first semiconductor device.3. The semiconductor system of claim 1 ,wherein the setting codes include a first setting code and a second setting code; andwherein the first and second setting codes are sequentially outputted from the first semiconductor device through the setting signals.4. The semiconductor system of claim 1 ,wherein the setting codes include a first setting code and a second setting code; andwherein the second semiconductor device performs a write operation for writing data patterns into the memory cell array accessed by the address patterns during a first operation section corresponding to the first setting code.5. The semiconductor system of claim 4 , wherein the second semiconductor device performs a read operation ...

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Номер записи: 43
19-01-2017 дата публикации

TEST SYSTEM AND TEST METHOD

Номер: US20170018315A1
Автор: CHAE Chol Su
Принадлежит:

A test system may include a memory device suitable for reading a stored data chunk; and a test device suitable for calculating a cumulative failure probability that the data chunk will contain a s predetermined number of error bits or less and decoding for the data chunk will fail. 1. A test system comprising:a memory device suitable for reading a stored data chunk; anda test device suitable for calculating a cumulative failure probability that the data chunk will contain a predetermined number of error bits or less and decoding for the data chunk will fail.2. The test system according to claim 1 ,wherein the test device calculates an individual failure probability that the data chunk will contain error bits of respective values of the predetermined number and decoding for the data chunk containing error bits of the respective values of the predetermined number will fail, andwherein the test device calculates the cumulative failure probability by accumulating individual failure probabilities for the respective values of the predetermined number.3. The test system according to claim 2 , wherein the test device calculates the individual failure probability based on an occurrence probability that the data chunk will contain the predetermined number of error bits.4. The test system according to claim 3 , wherein the test device writes a plurality of data chunks to the memory device claim 3 , reads the plurality of data chunks from the memory device claim 3 , counts a number of error bits contained in each of the data chunks claim 3 , and calculates the occurrence probability based on a count result5. The test system according to claim 2 , wherein the test device calculates the individual failure probability based on a specific failure probability that decoding for sample data containing the predetermined number of error bits will fail.6. The test system according to claim 5 , wherein the test device decodes a plurality of sample data containing the predetermined number ...

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Номер записи: 44
21-01-2016 дата публикации

Memory test with in-line error correction code logic

Номер: US20160019981A1
Автор: Kevin W. Gorman, Michael R. Ouellette, Patrick E. Perry
Принадлежит: International Business Machines Corp

Systems and methods are provided for reusing existing test structures and techniques used to test memory data to also test error correction code logic surrounding the memories. A method includes testing a memory of a computing system with an error code correction (ECC) logic block bypassed and a first data pattern applied. The method further includes testing the memory with the ECC logic block enabled and a second data pattern applied. The method also includes testing the memory with the ECC logic block enabled and the first data pattern applied.

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Номер записи: 45
03-02-2022 дата публикации

SEMICONDUCTOR DEVICE INCLUDING DEFECT DETECTION CIRCUIT AND METHOD OF DETECTING DEFECTS IN THE SAME

Номер: US20220036958A1
Автор: SON JONGPIL
Принадлежит: SAMSUNG ELECTRONICS CO., LTD.

A semiconductor device includes a semiconductor die having a peripheral region surrounding, a defect detection circuit in the peripheral region, the defect detection circuit arranged in an open conduction loop, the defect detection circuit comprising a plurality of latch circuits and a plurality of defect detection conduction paths, each defect detection conduction path of the plurality of defect detection conduction paths connecting two adjacent latch circuits of the plurality of latch circuits, and a test control circuitry configured to perform (a) a test write operation by transferring bits of an input data pattern in a forward direction of the open conduction loop to cause the plurality of latch circuits to store the bits of the input data pattern in the plurality of latch circuits, and (b) a test read operation by transferring bits stored in the plurality of latch circuits in a backward direction of the open conduction loop. 1. A semiconductor device comprising:a semiconductor die including a central region and a peripheral region surrounding the central region;a defect detection circuit in the peripheral region, the defect detection circuit arranged in an open conduction loop, the defect detection circuit comprising a plurality of latch circuits and a plurality of defect detection conduction paths, each defect detection conduction path of the plurality of defect detection conduction paths connecting two adjacent latch circuits of the plurality of latch circuits; anda test control circuitry configured to perform (a) a test write operation by sequentially transferring bits of an input data pattern in a forward direction of the open conduction loop to cause the plurality of latch circuits to store the bits of the input data pattern in the plurality of latch circuits, and (b) a test read operation by transferring bits stored in the plurality of latch circuits in a backward direction of the open conduction loop to read out an output data pattern.2. The ...

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Номер записи: 46
18-01-2018 дата публикации

Replicating test case data into a cache and cache inhibited memory

Номер: US20180019021A1
Автор: Manoj Dusanapudi, Shakti Kapoor
Принадлежит: International Business Machines Corp

Data is replicated into a memory cache and cache inhibited memory in data segments with segment size that provides non-naturally aligned data boundaries to reduce the time needed to generate test cases for testing a processor. Placing data in the non-naturally aligned data boundaries allows replicated testing of the memory cache and cache inhibited memory while preserving double word and quad word boundaries in segments of the replicated test data. This allows test cases generated for cacheable memory to be replicated and used for cache inhibited memory. The processor can then use a single test replicated in this manner by branching back and using the next slice of the replicated test data in the memory cache and cache inhibited memory.

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Номер записи: 47
18-01-2018 дата публикации

TESTING NON-VOLATILE MEMORIES

Номер: US20180019022A1
Автор: Christensen Jeffrey W., Christensen Phillip E., MILLER Robert S., Reuter Matthew S., Sater Antoine G.
Принадлежит:

A computer-implemented method includes receiving probability distribution function (PDF) data corresponding to bit-error-rate (BER) data for each of a plurality of data blocks within a qualified set of NVRAMS, collecting non-exhaustive bit-error-rate data for each of the data blocks on a tested NVRAM to produce non-exhaustive test data for each of the data blocks, determining a plurality of stable data blocks on the tested NVRAM based on the non-exhaustive test data and the probability distribution function data for each of the data blocks, determining, from the non-exhaustive test data, an inferior data block for the stable data blocks on the tested NVRAM, collecting exhaustive bit-error-rate data on the inferior data block to produce exhaustive test data for the tested NVRAM, and routing the tested NVRAM according to the exhaustive test data. A corresponding computer program product and computer system are also disclosed herein. 1. A method , executed by one or more processors , for testing non-volatile random access memories (NVRAMS) , the method comprising:receiving probability distribution function data corresponding to bit-error-rate data for each of a plurality of data blocks within a qualified set of NVRAMS;collecting non-exhaustive bit-error-rate data for each of the plurality of data blocks on a tested NVRAM to produce non-exhaustive test data for each of the plurality of data blocks;determining a plurality of stable data blocks on the tested NVRAM based on the non-exhaustive test data and the probability distribution function data for each of the plurality of data blocks;determining, from the non-exhaustive test data, an inferior data block for the plurality of stable data blocks on the tested NVRAM;collecting exhaustive bit-error-rate data on the inferior data block to produce exhaustive test data for the tested NVRAM; andprocessing or routing the tested NVRAM according to the exhaustive test data.2. The method of claim 1 , wherein the exhaustive test ...

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Номер записи: 48
16-01-2020 дата публикации

FLASH MEMORY

Номер: US20200020394A1
Автор: HABERLA Holger, HUDYRYEV Andrey, LOHBRANDT Soeren, MICAKOVIC Predrag
Принадлежит: X-FAB Semiconductor Foundries GmbH

A flash memory comprising a first plurality of memory cells, each memory cell of the first plurality of memory cells selectively connected to a first input of a comparator. A second plurality of memory cells selectively connected to a second input of the comparator, wherein a first number of the second plurality of memory cells are in an erased state, wherein a second number of the second plurality of memory cells are in a written state, wherein each memory cell of the first plurality of memory cells and each memory cell of the second plurality of memory cells has a first cell capacitance, and wherein the sum of the first number and the second number is at least three. 1. A flash memory comprising:a first plurality of memory cells, each memory cell of the first plurality of memory cells selectively connected to a first input of a comparator;a second plurality of memory cells selectively connected to a second input of the comparator,wherein a first number of the second plurality of memory cells are in an erased state;wherein a second number of the second plurality of memory cells are in a written state;wherein each memory cell of the first plurality of memory cells and each memory cell of the second plurality of memory cells has a first cell capacitance; andwherein the sum of the first number and the second number is at least three.2. A flash memory according to claim 1 , wherein each memory cell of the first plurality of memory cells and each memory cell of the second plurality of memory cells has a first size comprising a first channel length and a first channel width.3. A flash memory according to claim 1 , wherein the first plurality of memory cells and the second plurality of memory cells are distributed in an array claim 1 , and wherein the second plurality of memory cells are in positions spread out evenly across the array.4. A flash memory according to claim 1 , wherein the second plurality of memory cells is configured to generate a reference voltage.5. A ...

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Номер записи: 49
16-01-2020 дата публикации

MULTI-LEVEL MEMORY SAFETY OF A SENSOR INTEGRATED CIRCUIT

Номер: US20200020412A1
Автор: Alpago Octavio H., Biberidis Nicolas Rafael, Rigoni Nicolas
Принадлежит: Allegro Microsystems, LLC

A method for multi-level memory safety for a sensor integrated circuit can include loading a blocking bit into a volatile memory from a non-volatile memory and providing the blocking bit to a gating circuit from the volatile memory. Further, the method may include the gating circuit determining whether to provide a default value to a functional logic based upon the provided blocking bit. 1. A method for multi-level memory safety for a sensor integrated circuit , comprising:loading, from a non-volatile memory, a blocking bit into a volatile memory;providing, from the volatile memory, the blocking bit to a gating circuit; anddetermining, via the gating circuit, whether to provide a default value to a functional logic based upon the provided blocking bit.2. The method for multi-level memory safety of claim 1 , further comprising determining whether a bit stored in the non-volatile memory is corrupted.3. The method for multi-level memory safety of claim 2 , wherein the bit stored in the non-volatile memory comprises the blocking bit.4. The method for multi-level memory safety of claim 2 , further comprising placing the functional logic in a safe state if the bit stored in the non-volatile memory is determined to be corrupted.5. The method for multi-level memory safety of claim 4 , further comprising: determining whether data stored in the non-volatile memory is corrupted; andreturning the functional logic to a functional state from the safe state when the data stored in the non-volatile memory is determined not to be corrupted.6. The method for multi-level memory safety of claim 2 , further comprising determining whether the bit stored in the non-volatile memory is correctable.7. The method for multi-level memory safety of claim 6 , further comprising placing the functional logic in a safe state if the bit stored in the non-volatile memory is determined not to be correctable.8. The method for multi-level memory safety of claim 1 , further comprising determining whether ...

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Номер записи: 50
21-01-2021 дата публикации

APPARATUSES AND METHODS FOR SOFT POST-PACKAGE REPAIR

Номер: US20210020261A1
Автор: Wilson Alan J.
Принадлежит: MICRON TECHNOLOGY, INC.

Embodiments of the disclosure are drawn to apparatuses and methods for soft post-package repair (SPPR). After packaging, it may be necessary to perform post-package repair operations on rows of the memory. During a scan mode of an SPPR operation, addresses provided by a fuse bank may be examined to determine if they are open addresses or if the bad row of memory is a redundant row of memory. The open addresses and the bad redundant addresses may be stored in volatile storage elements, such as in latch circuits. During a soft send mode of a SPPR operation, the address previously associated with the bad row of memory may be associated with the open address instead, and the address of the bad redundant row may be disabled. 1. An apparatus comprising:a row latch associated with a redundant word line of a memory array;a fuse array configured to store a first address; determine if the first address is associated with the row latch,', 'determine if the first address is associated with a bad redundant row,', 'provide the first address to the row latch if the first address is associated with the row latch and the first address is not associated with a bad redundant row, and', 'provide the second address to the row latch if the first address is not associated with the row latch., 'a fuse logic circuit comprising volatile memory elements configured to store a second address, the fuse logic circuit configured to'}2. The apparatus of claim 1 , wherein the fuse logic circuit is further configured to disable the first address if the redundant word line is a bad redundant row.3. The apparatus of claim 2 , wherein the fuse logic is configured to disable the first address by changing a state of at least one enable bit of the first address.4. The apparatus of claim 1 , wherein the fuse array is configured to store a plurality of addresses including the first address claim 1 , and wherein the fuse logic circuit is configured to provide the first address to the row latch if none of the ...

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Номер записи: 51
10-02-2022 дата публикации

Bidirectional scan cells for single-path reversible scan chains

Номер: US20220043062A1
Автор: Wu-Tung Cheng, YU HUANG
Принадлежит: Siemens Industry Software Inc

A circuit comprises a plurality of scan chains. The plurality of scan chains comprises bidirectional scan cells. Each of the bidirectional scan cells comprises two serial input-output ports serving as either a serial data input port or a serial data output port based on a control signal. Each of the plurality of scan chains is configured to perform a shift operation in either a first direction or a second direction based on the control signal. The first direction is opposite to the second direction.

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Номер записи: 52
26-01-2017 дата публикации

SYSTEM INCLUDING HIERARCHICAL MEMORY MODULES HAVING DIFFERENT TYPES OF INTEGRATED CIRCUIT MEMORY DEVICES

Номер: US20170025187A1
Автор: Hampel Craig, Horowitz Mark
Принадлежит:

Volatile memory devices may be on a first memory module that is coupled to a memory controller by a first signal path. A nonvolatile memory device may be on a second memory module that is coupled to the first memory module by a second signal path. A memory transaction for the nonvolatile memory device may be transferred from the memory controller to at least one of the volatile memory devices using the first signal path and data associated with the memory transaction is to be written from at least one of the volatile memory devices to the nonvolatile memory device using the second signal path and a control signal. A defect circuit may generate the control signal in view of a detection of a defect in the nonvolatile memory device based on a comparison of a test value read from a memory location to a stored value. 1. A system comprising:a plurality of volatile memory devices disposed on a first memory module that is coupled to a memory controller by a first signal path;a nonvolatile memory device disposed on a second memory module that is coupled to the first memory module by a second signal path, wherein a memory transaction for the nonvolatile memory device is transferred from the memory controller to at least one of the plurality of volatile memory devices using the first signal path, and wherein data associated with the memory transaction is to be written from the at least one of the plurality of volatile memory devices to the nonvolatile memory device using the second signal path and a control signal; anda defect circuit to generate the control signal in view of a detection of a defect in the nonvolatile memory device based on a comparison of a test value read from a memory location to a stored value.2. The system of claim 1 , wherein the defect circuit is further to store an address corresponding to the memory location when the defect is detected.3. The system of claim 1 , further comprising:a mapping circuit to receive the memory location and the control signal ...

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Номер записи: 53
28-01-2016 дата публикации

Semiconductor memory apparatus

Номер: US20160027530A1
Автор: Sung Ho Kim
Принадлежит: SK hynix Inc

A semiconductor memory apparatus may include a first data storage region configured to output a first data, a second data storage region configured to output a second data, a third data storage region configured to output a third data, and a fourth data storage region configured to output a fourth data. The apparatus may include a first comparison block configured to compare the first data with the second data, and generate a first comparison signal. The apparatus may include a second comparison block configured to compare the second data with the third data, and generate a second comparison signal. The apparatus may include a third comparison block configured to compare the third data with the fourth data, and generate a third comparison signal. The apparatus may include a signal combination block configured to output a result signal in response to the first to third comparison signals.

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Номер записи: 54
10-02-2022 дата публикации

METHOD FOR TUNING AN EXTERNAL MEMORY INTERFACE

Номер: US20220043760A1
Автор: BROWN Zachary John
Принадлежит:

A device and method are presented. Largest and smallest successful values of a receive clock delay and a transmit clock delay are determined. A first set of parameters for an SPI coupled to a DDR flash memory are set, including the largest successful values of the transmit clock delay and the receive clock delay, and a first value of a RD cycle. A second set of parameters for the SPI are set, including the smallest successful value of the transmit clock delay and receive clock delay, and a second value of the RD cycle. One of the first and second sets of parameters is selected based on whether the first or second set of parameters results in successfully reading from the DDR flash memory over a larger range of operating temperatures. The SPI is programmed using the selected one of the first and second sets of parameters. 1. A device , comprising:a memory storing instructions; and determine a first set of parameters for the SPI that is usable by the processor to read successfully from the DDR flash memory, the first set of parameters comprising a largest successful value of a transmit clock delay, a largest successful value of a receive clock delay, and a first value of a reference clock delay (RD) cycle;', 'determine a second set of parameters for the SPI that is usable by the processor to read successfully from the DDR flash memory, the second set of parameters comprising a smallest successful value of the transmit clock delay, a smallest successful value of the receive clock delay, and a second value of the RD cycle;', 'select one of the first and second sets of parameters based on a determination of whether the first set of parameters is usable by the processor to read successfully from the DDR flash memory over a larger range of operating temperatures of the device than the second set of parameters; and', 'program the SPI using the selected one of the first and second sets of parameters., 'a processor adapted to be coupled to a Double Data Rate (DDR) flash ...

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Номер записи: 55
25-01-2018 дата публикации

METHODS OF OPERATING BUFFERED MULTI-RANK MEMORY MODULES CONFIGURED TO SELECTIVELY LINK RANK CONTROL SIGNALS

Номер: US20180025788A1
Автор: Han YouKeun, Kim Seokil, KIM Tae-Hyung, LIM JONGHYOUNG, SHIN HUICHONG, Yun Young
Принадлежит:

A method of operating a memory module including a plurality of semiconductor memory devices organized into a multi-rank memory on a DIMM and a memory buffer included on the DIMM, operatively coupled to the multi-rank memory, can be provided by mapping an access to the DIMM from a memory controller to semiconductor memory devices included in more than one rank within the multi-rank memory based on a mode register set signal and selectively linking rank control signals during a parallel bit test operation to the more than one rank within the multi-rank memory plurality of semiconductor memory devices. 1. A memory module , comprising:a plurality of semiconductor memory devices on a substrate to provide a DIMM organized into at least two ranks; anda memory buffer configured to change states of input signals received for each rank based on a mapping table defined according to a mode register set signal and configured to control the plurality of semiconductor memory devices for each rank.2. The memory module of claim 1 , wherein the input signals include a rank control signal configured to select the semiconductor memory devices for each rank.3. The memory module of claim 1 , wherein the input signals include clock enable signals for each rank.4. The memory module of claim 1 , wherein the input signals include on-die termination signals for each rank.5. The memory module of claim 1 , wherein the semiconductor memory devices provide a stacked memory device configured to communicate data and control signals through a plurality of through-silicon lines.6. A method of operating a memory module including a plurality of semiconductor memory devices organized into a multi-rank memory on a DIMM and a memory buffer included on the DIMM claim 1 , operatively coupled to the multi-rank memory claim 1 , the method comprising:mapping an access to the DIMM from a memory controller to semiconductor memory devices included in more than one rank within the multi-rank memory based on a mode ...

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Номер записи: 56
25-01-2018 дата публикации

Shared error detection and correction memory

Номер: US20180025789A1
Автор: Chiaki Dono, Taihei SHIDO, Yuki Ebihara
Принадлежит: Micron Technology Inc

Apparatuses and methods for an interface chip that interfaces with chips are described. An example apparatus includes: first terminals; circuit groups, each of the circuit groups including circuit blocks being configured to electrically couple to the first terminals; a control circuit that selects one of the circuit groups and electrically couple the first terminals to the circuit blocks of the one of the circuit groups; terminal groups, each of the terminal groups including second terminals, each of the terminal groups being provided correspondingly to each of the circuit groups, the second terminals of each of the terminal groups being smaller in number than the circuit blocks of a corresponding one of the circuit groups; and a remapping circuit that couples the second terminals of each of the terminal groups to selected ones of the circuit blocks of the corresponding one of the circuit groups.

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Номер записи: 57
28-01-2021 дата публикации

Method and Apparatus for Creating Tests for Execution in a Storage Environment

Номер: US20210027189A1
Автор: Malak Alshawabkeh, Motasem Awwad, Samer Badran
Принадлежит: EMC IP Holding Co LLC

Testcase recommendations are generated for a testcase creator application by training a learning function using metadata of previously generated testcases by parsing the metadata into steptasks, and providing the parsed metadata to the learning function to enable the learning function to determine relationships between the steptasks of the previously generated testcases, and using, by the testcase creator application, the trained learning function to obtain a predicted subsequent steptask for a given type of testcase to be generated. Each steptask describes one of the steps of the testcase using a concatenation of a step number of the one of the steps of the testcase, a module and a submodule to be used to perform of the one of the steps of the testcase, and a function to be performed at the one of the steps of the testcase.

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Номер записи: 58
23-01-2020 дата публикации

MEMORY SYSTEM AND METHOD FOR OPTIMIZING READ THRESHOLD

Номер: US20200027519A1
Автор: CAI Yu, LU Xuanxuan, XIONG Chenrong, Zhang Fan
Принадлежит:

A memory system includes a memory device and a controller. The controller performs a test read operation on a read data set of the memory device, using multiple read threshold entries and determines which are good read threshold entries based on results of the read operation. The controller selects a best read threshold entry among the multiple read threshold entries based on a result of the test read operation, partitions the read data set into a good data set decodable by the best read threshold entry and a bad data set undecodable by the best read threshold entry, and sets the bad data set as a new read data set. 1. A memory system comprising:a memory device; anda controller suitable for:performing a test read operation on a read data set of the memory device, using multiple read threshold entries; anddetermining good read threshold entries among the multiple read threshold entries based on results of the test read operation,wherein the determining of the good read threshold entries includes:selecting a best read threshold entry among the multiple read threshold entries based on a result of the test read operation;partitioning the read data set into a good data set that includes data in the read data set that is decodable by the best read threshold entry and a bad data set that includes data in the read data set that is undecodable by the best read threshold entry; andsetting the bad data set as a new read data set.2. The memory system of claim 1 , when the performing of the test read operation includes reading data from the new read data set claim 1 , using remaining read threshold entries claim 1 , which excludes the best read threshold entry among multiple read threshold entries.3. The memory system of claim 1 , wherein the result of the test read operation includes numbers of fail bits for the read data set.4. The memory system of claim 1 , wherein the read data set corresponds to physical addresses selected from a super block of the memory device.5. The ...

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Номер записи: 59
23-01-2020 дата публикации

Run-Time Memory Device Failure Detection Enhancement

Номер: US20200027520A1
Автор: CHU Sanghoon, JINN Scott, PAVLENKO Yuriy
Принадлежит:

The subject technology provides implementations, which may be included as part of firmware of the flash memory device, that will not solely rely on a flash controller interpreted status but includes additional checks to the returned flash status byte. Each flash read, write, and erase command requires a status read command to determine the state of operation. Depending on the particular command issued, each bit of the returned status has a different meaning. The flash memory device firmware can check whether an illogical or inconsistent status is present. For example, if an overall pass/fail bit indicates a “pass” but a plane pass/fail bit indicates a “fail” then there could be an erroneous detection. Also, for every operation, the firmware can read status twice when the flash memory is ready. If the second status byte fails to match the first status byte then a die may be flagged as failing. 1. A storage system , comprising:a plurality of memory devices; and when a time interval has elapsed, providing a first check status command, wherein the time interval is associated with an operation for a memory device of the plurality of memory devices;', 'receiving a first signal;', 'determining whether the first signal indicates a ready status;', 'providing a second check status command after the first check status command;', 'receiving a second signal;', 'determining whether the second signal is different from the first signal; and', 'when the second signal is different from the first signal, providing an indication of a failure of the memory device., 'a controller configured to cause2. The storage system of claim 1 , wherein the controller is configured to cause:when the second signal matches the first signal, determining whether an illogical status is detected;when the illogical status is detected, providing the indication of the failure of the memory device; andwhen the illogical status is not detected, providing an indication of a success of the memory device.3. The ...

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Номер записи: 60
28-01-2021 дата публикации

IN-SYSTEM TEST OF A MEMORY DEVICE

Номер: US20210027853A1
Автор: Redaelli Marco
Принадлежит:

An example system includes a processing resource and a switch board coupled to a system under test (SUT) and the processing resource. The SUT includes a memory device. The switch board can be configured to provide power to the SUT, communicate a first signal from the SUT to the processing resource, and provide a second signal to the SUT that simulates an input to the SUT during operation of the SUT. The processing resource can be configured to receive a function, selected from a library of functions, to execute during a test of the memory device and cause the switch board to provide the second signal during the test of the SUT. 1. A system , comprising:a processing resource; anda switch board coupled to a system under test (SUT) and the processing resource, wherein the SUT includes a memory device, provide power to the SUT;', 'communicate a first signal from the SUT to the processing resource; and', 'provide a second signal to the SUT that simulates an input to the SUT during operation of the SUT, and, 'wherein the switch board is configured to receive a function, selected from a library of functions, to execute during a test of the memory device; and', 'cause the switch board to provide the second signal during the test of the SUT., 'wherein the processing resource is configured to2. The system of claim 1 , wherein the SUT comprises an in-vehicle infotainment (IVI) system.3. The system of claim 2 , wherein the second signal simulates startup of a vehicle including the IVI system.4. The system of claim 2 , wherein the second signal simulates connection of a battery of a vehicle including the IVI system to the IVI system.5. The system of claim 2 , wherein the second signal simulates activation of a rearview camera of a vehicle including the IVI system.6. The system of claim 2 , wherein the second signal simulates changing gears of a vehicle including the IVI system.7. The system of claim 1 , wherein the first signal is a general purpose input/output (GPIO) signal of ...

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Номер записи: 61
28-01-2021 дата публикации

Memory device test circuit and memory device test method

Номер: US20210027854A1
Автор: Sheng-Lin Lin, Shih-Chieh Lin
Принадлежит: Realtek Semiconductor Corp

A memory device test circuit and a memory device test method are provided. The memory device test circuit is configured to test a memory device and includes a storage circuit, a comparison circuit and a control circuit. The storage circuit stores a test data. The comparison circuit is coupled to the storage circuit. The control circuit is coupled to the storage circuit, the comparison circuit, and the memory device and performs the following steps to test the memory device: writing the test data to the memory device; controlling the memory device to enter a power mode; controlling the memory device to enter a function mode; and controlling the comparison circuit to compare an output data of the memory device with the test data.

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Номер записи: 62
02-02-2017 дата публикации

SEMICONDUCTOR MEMORY APPARATUS AND TEST METHOD THEREOF

Номер: US20170032850A1
Автор: EM Ho Seok, LIM Seung Kyun
Принадлежит:

A semiconductor memory apparatus includes a normal write pulse generator configured to generate a normal write pulse in a normal operation, a test write pulse generator configured to repeatedly generate a test write pulse a preset number of times in a test operation, and a selector configured to provide the normal write pulse to a memory cell in the normal operation and provide the test write pulse to the memory cell in the test operation. 1. A semiconductor memory apparatus comprising:a normal write pulse generator configured to generate a normal write pulse in a normal operation;a test write pulse generator configured to repeatedly generate a test write pulse a preset number of times in a test operation; anda selector configured to provide the normal write pulse to a memory cell in the normal operation and provide the test write pulse to the memory cell in the test operation.2. The semiconductor memory apparatus of claim 1 , wherein the test write pulse generator repeatedly generates the test write pulse a preset number of times when a test signal is enabled and stops generating the test write pulse if the test write pulses have been generated the preset number of times.3. The semiconductor memory apparatus of claim 2 , wherein the test write pulse generator includes:a latch unit configured to generate a test activation signal in response to the test signal and a reset signal;a clock generator configured to generate a clock periodically transitioning between preset voltage levels in response to the test activation signal;an output controller configured to output the test write pulse in response to the test activation signal and the clock; anda counting unit configured to generate the reset signal in response to the test activation signal and the test write pulse.4. The semiconductor memory apparatus of claim 3 , wherein the latch unit enables the test activation signal when the test signal is enabled claim 3 , and disables the test activation signal when the reset ...

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Номер записи: 63
04-02-2016 дата публикации

APPARATUSES AND METHODS FOR OPERATING A MEMORY DEVICE

Номер: US20160035436A1
Автор: Ha Chang Wan
Принадлежит:

Subject matter described pertains to apparatuses and methods for operating a memory device. 1. A method comprising;accessing a memory to determine whether a dynamic data cache includes a problematic memory cell; andtemporarily suspending communications between the dynamic data cache and a secondary data cache if the dynamic data cache includes a problematic memory cell.2. The method of claim 1 , wherein temporarily suspending communications between the dynamic data cache and the secondary data cache if the dynamic data cache includes a problematic memory cell comprises temporarily suspending communications between the dynamic data cache and the secondary data cache if the dynamic data cache includes a problematic group of memory cells.3. The method of claim 1 , wherein accessing a memory to determine whether a dynamic data cache includes a problematic memory cell comprises accessing the memory to determine whether the dynamic data cache includes a problematic column of memory cells.4. The method of claim 3 , further comprising:reestablishing communications between the dynamic data cache and the secondary data cache after accessing a memory array in place of the problematic memory cell.5. The method of claim 1 , wherein accessing a memory to determine whether a dynamic data cache includes a problematic memory cell comprises determining a status of an indicator stored with addresses of problematic memory cells.6. The method of claim 4 , wherein accessing the memory array comprises accessing a redundant column of the memory array.7. The method of claim 1 , further comprising remapping a portion of the dynamic data cache comprising the problematic memory cell to a redundant memory array portion.8. The method of claim 7 , wherein the portion of the dynamic data cache comprises a column of the dynamic data cache claim 7 , wherein the redundant memory array portion comprises a redundant memory array column claim 7 , and wherein remapping comprises remapping the column of ...

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Номер записи: 64
17-02-2022 дата публикации

RECEIVER TRAINING OF REFERENCE VOLTAGE AND EQUALIZER COEFFICIENTS

Номер: US20220051742A1
Автор: Baby Kiran, Bala Phalguni, M. Ashwin S., Mishra Navin Kumar, Shelke Anirudha, Shetty Sudhir Kumar Katla, Syed Younus
Принадлежит:

In a receiver having at least a first equalizer and a sampler, a calibration module jointly calibrates a reference voltage and one or more equalizer coefficients. For each of a set of test reference voltages, an equalizer coefficient for the first equalizer may be learned that maximizes a right eye boundary of an eye diagram of a sampler input signal to a sampler of the receiver following the equalization stage. Then, from the possible pairs of reference voltages and corresponding optimal equalizer coefficients, a pair is identified that maximizes an eye width of the eye diagram. After setting the reference voltage, the first equalizer coefficient may then be adjusted together with learning a second equalizer coefficient for the second equalizer using a similar technique. 1. A method for calibrating a receiver of a communication link , the receiver comprising at least a first equalizer to generate a sampler input signal based on a receiver input signal , and a sampler sampling the sampler input signal to generate an output signal , the method comprising:receiving, at the receiver over the communication link, a receiver input signal representing a bit pattern having AC frequency components and DC frequency components;determining, for each of a plurality of reference voltages, a corresponding first equalizer coefficient for the first equalizer and a corresponding plurality of parameters of the sampler input signal that are based on the reference voltage and the corresponding first equalizer coefficient;selecting a reference voltage from among the plurality of reference voltages and the selected reference voltage's corresponding first equalizer coefficient that have the corresponding plurality of parameters of the sampler input signal that satisfy a plurality of optimization criterion; andsetting the selected reference voltage.2. The method of claim 1 , wherein the receiver input signal comprises a bit pattern having alternating current frequency components and direct ...

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Номер записи: 65
17-02-2022 дата публикации

Recovery management of retired super management units

Номер: US20220051749A1
Автор: Jian Huang, Zhenming Zhou
Принадлежит: Micron Technology Inc

A system includes a memory component, and a processing device coupled with the memory component. The processing device to identify a group of management units of the memory component, wherein the group of management units is included in a set of retired groups of management units, select a management unit from the group of management units, perform a media integrity check on the management unit to determine a failed bit count of the management unit, and in response to the failed bit count of the management unit failing to satisfy a threshold criterion, remove the group of management units from the set of retired groups of management units.

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Номер записи: 66
31-01-2019 дата публикации

Technologies for dynamically allocating data storage capacity for different data storage types

Номер: US20190034102A1
Автор: Paul Dormitzer, Steven Miller
Принадлежит: Intel Corp

Technologies for allocating data storage capacity on a data storage sled include a plurality of data storage devices communicatively coupled to a plurality of network switches through a plurality of physical network connections and a data storage controller connected to the plurality of data storage devices. The data storage controller is to determine a target storage resource allocation to be used by one or more applications to be executed by one or more sleds in a data center, determine data storage capacity available for each of a plurality of different data storage types on the data storage sled, wherein each data storage type is associated with a different level of data redundancy, determine an amount of data storage capacity for each data storage type to be allocated to satisfy the target storage resource allocation, and adjust the amount of data storage capacity allocated to each data storage type.

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Номер записи: 67
31-01-2019 дата публикации

SEMICONDUCTOR LAYERED DEVICE WITH DATA BUS

Номер: US20190034370A1
Автор: Funahashi Akinori, Kondo Chikara
Принадлежит:

Apparatuses and methods of data communication between semiconductor chips are described. An example apparatus includes: a first die including a first switch circuit that receives a plurality of data signals, and further provides the plurality of data signals to a plurality of corresponding first ports among a plurality of first data ports and a first data redundancy port; and a second die including a second switch circuit that receives the plurality of data signals from the first die at a plurality of corresponding second ports among a plurality of second data ports and a second data redundancy port and further provides the plurality of data signals to a memory array. 1. An apparatus comprising: a plurality of first terminals configured to receive a plurality of bits of a data signal, respectively; and', 'a second terminal configured to receive a data bus inversion (DBI) signal, the DBI signal indicating whether the data signal is inverted in logic level;, 'a first set of terminals including a plurality of third terminals; and', 'a fourth terminal; and, 'a second set of terminals includinga first switch circuit coupled between the first set of terminals and the second set of terminals and supplied with first control information,wherein the first switch circuit is configured to couple the plurality of first terminals to the plurality of third terminals, respectively, and couple the second terminal to the fourth terminal when the first control information is in a first state, andwherein the first switch circuit is further configured to couple one of the plurality of first terminals to the fourth terminal and couple remaining ones of the first terminals to selected ones of the third terminals, respectively, when the first control information is in a state other than the first state.2. The apparatus of claim 1 , further comprising a plurality of first vias coupled to the third terminals claim 1 , respectively claim 1 , and a second via coupled to the fourth terminal.3. ...

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Номер записи: 68
31-01-2019 дата публикации

SEMICONDUCTOR MEMORY DEVICE AND OPERATING METHOD THEREOF

Номер: US20190035451A1
Автор: LEE Hee Youl
Принадлежит: SK HYNIX INC.

The semiconductor memory device includes a memory cell array, a peripheral circuit and a control logic. The memory cell array includes a plurality of memory cells. The peripheral circuit performs a program operation for the plurality of memory cells in the memory cell array. The control logic controls the peripheral circuit and the memory cell array such that, during the program operation for the plurality of memory cells, pre-bias voltages are applied to a plurality of word lines coupled to the plurality of memory cells to precharge channel regions of the plurality of memory cells. Furthermore, different pre-bias voltages are applied to the plurality of word lines depending on the relative positions of the word lines. 1. A semiconductor memory device comprising:a memory cell array including a plurality of word lines;a peripheral circuit configured to apply a program voltage to a selected word line among the plurality of word lines; anda control logic configured to control the peripheral circuit to apply pre-bias voltages to the plurality of word lines before the program voltage is applied to the selected word line,wherein each of the plurality of word lines includes a plurality of memory cells; andwherein the pre-bias voltages are determined based on a program sequence of the plurality of word lines.2. The semiconductor memory device according to claim 1 ,wherein the plurality of word lines are grouped into a plurality of word line groups,wherein the plurality of word lines are sequentially programmed in a direction away from a first programmed word line, andwherein the earlier a word line group among the plurality of word line groups is programmed, the lower a pre-bias voltage to be applied to word lines included in the word line group is.3. The semiconductor memory device according to claim 1 ,wherein the plurality of word lines are grouped into a plurality of word line groups,wherein the plurality of word lines are programmed in a sequence from a word line ...

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Номер записи: 69
31-01-2019 дата публикации

TECHNOLOGIES FOR MANAGING ERRORS IN A REMOTELY ACCESSIBLE MEMORY POOL

Номер: US20190035483A1
Автор: Nachimuthu Murugasamy K., Schmisseur Mark, Ziakas Dimitrios
Принадлежит:

Technologies for managing errors in a remotely accessible memory pool include a memory sled. The memory sled includes a memory pool having one or more byte-addressable memory devices and a memory pool controller coupled to the memory pool. The memory sled is to write test data to a byte-addressable memory region in the memory pool. The memory region is to be accessed by a remote compute sled. The memory sled is also to read data from the memory region to which the test data was written, compare the read data to the test data to determine whether a threshold number of errors are present in the read data, and send, in response to a determination that the threshold number of errors are present in the read data, a notification to the remote compute sled that the memory region is faulty. 1. A memory sled comprising:communication circuitry;a memory pool controller couplable to a memory pool having one or more byte-addressable memory devices, wherein the memory pool controller is to: (i) write test data to a byte-addressable memory region in the memory pool, wherein the memory region is to be accessed by a remote compute sled through a network; (ii) read data from the memory region to which the test data was written; (iii) compare the read data to the test data to determine whether a threshold number of errors are present in the read data; and (iv) send, in response to a determination that the threshold number of errors are present in the read data, a notification through the network that the memory region is faulty.2. The memory sled of claim 1 , wherein the memory pool controller is further to:receive, from an orchestrator server, an allocation request to allocate byte-addressable memory from the memory pool to the remote compute sled; andsend, in response to a determination that the threshold number of errors are present in the read data, a second notification to the orchestrator server that the memory region is faulty.3. The memory sled of claim 1 , wherein the memory ...

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Номер записи: 70
31-01-2019 дата публикации

FINFET-BASED MEMORY TESTING USING MULTIPLE READ OPERATIONS

Номер: US20190035484A1
Автор: Harutyunyan Gurgen, Shoukourian Samvel, Tshagharyan Grigor, Zorian Yervant
Принадлежит:

A test methodologies for detecting both known and potentially unknown FinFET-specific faults by way of implementing an efficient and reliable base set of March elements in which multiple sequential March-type read operations are performed immediately after logic values (i.e., logic-0 or logic-1) are written into each FinFET cell of a memory array. For example, a March-type write-1 operation is performed, followed immediately by multiple sequentially-executed March-type read-1 operations, then a March-type write-0 operation is performed followed immediately by multiple sequentially-executed March-type read-0 operations. An optional additional March-type read-0 operation is performed before the March-type write-1 operation, and an optional additional March-type read-1 operation is performed before the March-type write-0 operation. The write-1-multiple-read-1 and write-0-multiple-read-0 sequences are performed using one or both of an increasing address order and a decreasing address order. 1. A method for testing a FinFET array including a plurality of FinFET cells , each said FinFET cell having an associated array address , the FinFET array being configured such that the associated array addresses of said plurality of FinFET cells are arranged in a sequential address order , the method comprising:performing a first test pattern including performing a first March-type read operation to verify that each said FinFET cell stores a logic-0 value, performing a first March-type write operation to store a logic-1 value in each said FinFET cell, and performing a first sequence including multiple sequential March-type read-1 operations;performing a second test pattern including performing a second March-type read operation to verify that each said FinFET cell stores said logic-1 value, performing a second March-type write operation to store said logic-0 value in each said FinFET cell, and performing a second sequence including multiple sequential March-type read-0 operations; ...

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Номер записи: 71
05-02-2015 дата публикации

Apparatus and method for acquiring data of fast fail memory

Номер: US20150039951A1
Автор: Ho Sang YOU
Принадлежит: UniTest Inc

An apparatus and method for acquiring data of fast fail memory includes a pattern generator for generating a pattern to be recorded to a device under test (DUT) and receiving DUT data from the DUT; a data transmitter for sending the DUT data and the pattern generated so as to correspond thereto to a failure analyzer from the pattern generator; and a failure analyzer for analyzing the DUT data and the pattern generated so as to correspond to the DUT data, which are received from the data transmitter, thus producing failure analysis information. The data transmitter (FIFO) able to advance the failure analysis time allows failure analysis to be performed before completion of testing, thereby shortening the total failure analysis time and overcoming hardware limitations for failure analysis.

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Номер записи: 72
30-01-2020 дата публикации

System and Method for Testing Processor Errors

Номер: US20200035319A1
Автор: Dusanapudi Manoj, Kapoor Shakti, Rajaiah Nandhini, Wu Nelson
Принадлежит:

A system comprising a computer processor comprising a plurality of registers, a load-store unit configured to load data in at least one of the plurality of registers, and a memory. The memory includes a memory location mapped to a first virtual memory address and a second virtual memory address. Issuance of a load from the memory location via the first virtual memory address causes execution of a side effect. The memory also includes a computer program containing programming instructions that, when executed by the computer processor, performs an operation that includes storing a predetermined data value at the memory location, and testing the memory for errors during load operations. 1. A system comprising:a computer processor comprising a plurality of registers;a load-store unit configured to load data in at least one of the plurality of registers; and a memory location mapped to a first virtual memory address and a second virtual memory address, wherein issuance of a load from the memory location via the first virtual memory address causes execution of a side effect, and', storing a predetermined data value at the memory location, and', 'testing the memory for errors during load operations., 'a computer program containing programming instructions that, when executed by the computer processor, performs an operation, the operation comprising], 'a memory comprising2. The system of claim 1 , wherein testing the memory for errors during load operations comprises:issuing load requests to the first virtual memory address and the second virtual memory address;identifying the memory location being mapped to the first virtual memory address and the second virtual memory address;causing the load store unit to load data from the memory location to a first register and a second register; andexecuting the side effect that causes the load store unit to store a modified data value at the memory location.3. The system of claim 2 , wherein testing the memory for errors during load ...

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Номер записи: 73
30-01-2020 дата публикации

MEMORY DEVICE AND TEST CIRCUIT THEREOF

Номер: US20200035320A1
Автор: Kim Kwang-Soon, Kim Young-Hoon, Lee Sang-Kwon
Принадлежит:

A memory device includes a plurality of memory cell arrays, a plurality of data transmitters corresponding to the plurality of memory cell arrays, respectively, and suitable for transmitting data read in parallel from the corresponding memory cell arrays, and a test circuit suitable for selecting one data transmitter among the plurality of data transmitters, and sequentially outputting data transmitted in parallel from the selected data transmitter to one data input/output pad among a plurality of data input/output pads, during a test mode. 1. A memory device comprising:a plurality of memory cell arrays;a plurality of data transmitters corresponding to the plurality of memory cell arrays, respectively, and suitable for transmitting data read in parallel from the corresponding memory cell arrays; anda test circuit suitable for selecting one data transmitter among the plurality of data transmitters, and sequentially outputting data transmitted in parallel from the selected data transmitter to one data input/output pad among a plurality of data input/output pads, during a test mode.2. The memory device of claim 1 , wherein the test circuit comprises:a plurality of selection units each corresponding to the respective output lines of the data transmitters and suitable for outputting data of an output line of the selected data transmitter in response to select signals.3. The memory device of claim 2 , further comprising:a plurality of serializers corresponding to the respective data transmitters and suitable for sequentially outputting the data transmitted in parallel from the data transmitters to the data input/output pads.4. The memory device of claim 3 , wherein the test circuit comprises one serializer among the plurality of serializers claim 3 , andduring the test mode, the one serializer receives the data outputted from the selection units in parallel, and sequentially outputs the received data to the one data input/output pad among the data input/output pads.5. The ...

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Номер записи: 74
04-02-2021 дата публикации

SYSTEM INCLUDING HIERARCHICAL MEMORY MODULES HAVING DIFFERENT TYPES OF INTEGRATED CIRCUIT MEMORY DEVICES

Номер: US20210035652A1
Автор: Hampel Craig, Horowitz Mark
Принадлежит:

Volatile memory devices may be on a first memory module that is coupled to a memory controller by a first signal path. A nonvolatile memory device may be on a second memory module that is coupled to the first memory module by a second signal path. A memory transaction for the nonvolatile memory device may be transferred from the memory controller to at least one of the volatile memory devices using the first signal path and data associated with the memory transaction is to be written from at least one of the volatile memory devices to the nonvolatile memory device using the second signal path and a control signal. A durability circuit may generate the control signal based on a comparison of a number of write transactions to a particular memory location with a threshold value. 1. (canceled)2. A device comprising:circuitry to determine to write data associated with a memory transaction from at least one of a plurality of volatile memory devices to a nonvolatile memory device based on a comparison of a number of write transactions to a particular memory location and a threshold value, wherein the memory transaction is transferred from a memory controller to the at least one of the plurality of volatile memory devices using a first signal path, wherein the data associated with the memory transaction is to be written from the at least one of the plurality of volatile memory devices to the nonvolatile memory device using a second signal path.3. The device of claim 2 , wherein the circuitry further comprises a counter circuit to count the number of write transactions to the particular memory location.4. The device of claim 2 , wherein the circuitry further comprises:a counter circuit;a register to store the threshold value; anda comparison circuit to receive the number of write transactions from the counter circuit and the threshold value stored at the register and to compare the number of write transactions with the threshold value.5. The device of claim 2 , wherein the ...

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Номер записи: 75
04-02-2021 дата публикации

APPARATUS AND METHOD

Номер: US20210035653A1
Автор: BECKER Alan Jeremy, PIERRON Loïc
Принадлежит:

Apparatus comprises memory circuitry having a plurality of addressable memory entries storing respective data items and associated error protection codes; memory error protection circuitry to generate the error protection code for a data item stored to the memory circuitry, the error protection code for a given data item stored to the memory circuitry depending upon at least the given data item and a memory address defining a memory entry to which the given data item is stored, and to perform a check operation to check for consistency between a retrieved data item, the memory address defining a memory entry from which the given data item is retrieved and the error protection code associated with the retrieved data item; memory built-in self-test circuitry to test the memory and memory error protection circuitry; and access circuitry to provide an indirect access path between the memory built-in self-test circuitry a memory which accesses the memory circuitry via the memory error protection circuitry and a direct access path between the memory built-in self-test circuitry and a memory entry which bypasses the memory error protection circuitry; the memory built-in self-test circuitry being configured to execute a test operation by writing a test value to a first memory entry of the memory circuitry having a first test memory address via the indirect access path; retrieving the test value and associated error protection code from the first memory entry by the direct access path; writing the retrieved test value and associated error protection code to a second memory entry having a second test memory address via the direct access path, there being a difference in at least one bit between the first test memory address and the second test memory address; and retrieving the test value and associated error protection code from the second memory entry via the indirect access path; the memory built-in self-test circuitry comprising fault detection circuitry configured to ...

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Номер записи: 76
11-02-2016 дата публикации

SEMICONDUCTOR TEST DEVICE

Номер: US20160042808A1
Автор: Lee Wan Seob
Принадлежит:

A semiconductor test device performs a test using a high-speed internal clock. The semiconductor test device includes a clock generator suitable for generating an internal clock in response to a test mode signal during a test mode, a data generator suitable for generating internal data in response to the internal clock, and a data latch circuit suitable for latching the internal data in response to the internal clock, and outputting the latched data to an internal logic circuit. 19.-. (canceled)10. A semiconductor test device comprising:a pre-driver suitable for outputting a first output signal by driving first output data in response to a rising clock and a falling clock;a data generator suitable for generating second output data in response to the rising clock and the falling clock;an internal pre-driver suitable for driving the second output data in response to the rising clock and the falling clock and outputting a second output signal;a data comparator suitable for outputting a comparison signal by comparing the first output signal to the second output signal;a data accumulator suitable for accumulating the comparison signal in response to the rising clock and the falling clock; andan output driver suitable for driving an output signal of the data accumulator during a test mode.11. The semiconductor test device according to claim 10 , wherein the first output data is output from a page buffer of an internal logic circuit.12. The semiconductor test device according to claim 10 , further comprising:a test circuit suitable for determining a data pass status or a data failure status in response to output data of the output driver.13. The semiconductor test device according to claim 10 , wherein the rising clock is enabled by latching a rising edge of an internal reference clock for a predetermined time claim 10 , and the falling clock is enabled by latching a falling edge of an internal reference clock for a predetermined time.14. The semiconductor test device ...

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Номер записи: 77
11-02-2016 дата публикации

SEMICONDUCTOR MEMORY DEVICES AND MEMORY SYSTEMS INCLUDING THE SAME

Номер: US20160042809A1
Автор: CHUNG Hoi-ju, KIM Young-Il
Принадлежит:

A semiconductor memory device includes a memory cell array, an input/output (I/O) gating circuit, an error decision circuit and an error check and correction (ECC) circuit. The I/O gating circuit reads test pattern data to provide test result data in a test mode and reads a codeword in a normal mode. The error decision circuit determines the correctability of errors in the test result data by a first unit, based on the test pattern data and the test result data and provides a first error kind signal indicating a first determination result, in the test mode. The ECC circuit decodes the codeword including main data and parity data generated based on the main, determines correctability of errors in the codeword by a second unit and provides a second error kind signal indicating a second determination result, in the normal mode. The main data includes a plurality of unit data. 1. A semiconductor memory device comprising:a memory cell array;an input/output (I/O) gating circuit configured to read test pattern data from the memory cell array to provide test result data in a test mode, and configured to read a codeword from the memory cell array in a normal mode;an error decision circuit configured to determine correctability of errors in the test result data according to a first unit whose size is equal to or smaller than a size of the codeword, based on the test pattern data and the test result data, and the error decision circuit configured to provide a first error kind signal indicating a first determination result, in the test mode; andan error check and correction (ECC) circuit configured to decode the codeword, the codeword including main data and parity data generated from the main data, the ECC circuit configured to determine correctability of errors in the codeword according to a second unit whose size is equal to or smaller than the size of the codeword, and the ECC circuit configured to provide a second error kind signal indicating a second determination result, ...

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Номер записи: 78
11-02-2016 дата публикации

METHOD OF REPAIRING NON-VOLATILE MEMORY BASED STORAGE DEVICE AND METHOD OF OPERATING ELECTRONIC SYSTEM INCLUDING THE STORAGE DEVICE

Номер: US20160042810A1
Автор: Lee Joon Ho, Park Jong Tae
Принадлежит:

A method of repairing a storage device including a non-volatile memory includes powering on the storage device, performing a booting sequence, determining whether an error has occurred during the booting sequence or during a normal mode, writing a failure signature to a predetermined signature address in the non-volatile memory upon determining that the error has occurred, reporting a failure to a host upon writing the failure signature, entering into a repair mode upon reporting the failure, and operating in the normal mode upon determining that the error has not occurred. 1. A method of repairing a storage device including a non-volatile memory , comprising:powering on the storage device;performing a booting sequence;determining whether an error has occurred during the booting sequence or during a normal mode;writing a failure signature to a predetermined signature address in the non-volatile memory upon determining that the error has occurred;reporting a failure to a host upon writing the failure signature;entering into a repair mode upon reporting the failure; andoperating in the normal mode upon determining that the error has not occurred.2. The method of claim 1 , wherein performing the booting sequence comprises:executing a read-only memory (ROM) code that has been written to ROM;loading a firmware code from the non-volatile memory to random access memory (RAM); andreading flash translation layer (FTL) metadata from the non-volatile memory,wherein determining whether the error has occurred comprises determining whether the error is present in the FTL metadata.3. The method of claim 2 , wherein entering into the repair mode comprises:receiving an FTL format command issued by a repair application program stored in the host;initializing the FTL metadata in response to receiving the FTL format command; anderasing the failure signature from the signature address.4. The method of claim 3 , wherein initializing the FTL metadata comprises:erasing at least one block ...

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Номер записи: 79
07-02-2019 дата публикации

TECHNOLOGIES FOR STORAGE DISCOVERY AND REALLOCATION

Номер: US20190042126A1
Автор: CAIN Gamil, Chagam Reddy Anjaneya Reddy, Greer Teddy, Sen Sujoy
Принадлежит:

Technologies for storage discovery and reallocation include a compute device. The compute device is to receive, from a data storage sled, storage device data from a storage device located on the data storage sled. The storage device data includes storage device self-test data that defines a result of a self-test performed by the storage device. The compute device is also to determine, in response to the storage device self-test data, whether the storage device fails to satisfy a performance threshold. Further, the compute device is to generate, in response to a determination that the storage device fails to satisfy the performance threshold, an adjustment message for the storage device. The adjustment message instructs the storage device to adjust a performance parameter of the storage device. The compute device is also to send the adjustment message to the storage device. 1. A compute device to manage storage device performance , the compute device comprising: receive, from a data storage sled, storage device data from a storage device located on the data storage sled, wherein the storage device data includes storage device self-test data that defines a result of a self-test performed by the storage device;', 'determine, in response to the storage device self-test data, whether the storage device fails to satisfy a performance threshold;', 'generate, in response to a determination that the storage device fails to satisfy the performance threshold, an adjustment message for the storage device, wherein the adjustment message instructs the storage device to adjust a performance parameter of the storage device; and', 'send the adjustment message to the storage device., 'a compute engine to2. The compute device of claim 1 , wherein to generate the adjustment message comprises to generate an adjustment message that instructs the storage device to adjust a capacity provisioning ratio for the storage device claim 1 , wherein the capacity provisioning ratio defines a ratio ...

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Номер записи: 80
07-02-2019 дата публикации

Technologies for providing streamlined provisioning of accelerated functions in a disaggregated architecture

Номер: US20190042234A1
Автор: Francesc Guim Bernat, Kshitij DOSHI, Suraj Prabhakaran, Timothy Verrall
Принадлежит: Intel Corp

Technologies for providing streamlined provisioning of accelerated functions in a disaggregated architecture include a compute sled. The compute sled includes a network interface controller and circuitry to determine whether to accelerate a function of a workload executed by the compute sled, and send, to a memory sled and in response to a determination to accelerate the function, a data set on which the function is to operate. The circuitry is also to receive, from the memory sled, a service identifier indicative of a memory location independent handle for data associated with the function, send, to a compute device, a request to schedule acceleration of the function on the data set, receive a notification of completion of the acceleration of the function, and obtain, in response to receipt of the notification and using the service identifier, a resultant data set from the memory sled. The resultant data set was produced by an accelerator device during acceleration of the function on the data set. Other embodiments are also described and claimed.

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Номер записи: 81
24-02-2022 дата публикации

DEFECT DETECTING METHOD AND DEVICE FOR WORD LINE DRIVING CIRCUIT

Номер: US20220059176A1
Автор: CHEN Wugang, YANG LUNG
Принадлежит:

A defect detecting method for a Word Line (WL) driving circuit includes: m WLs correspondingly connected to m different WL driving circuits are selected from a memory cell array and corresponding WL driving circuit arrays to serve as m WLs to be tested, one of which is set as a first WL and the remaining m-1 ones are set as second WLs; first potential is written into memory cells correspondingly connected to the m WLs to be tested; second potential is written into memory cells correspondingly connected to the first WL; real-time potentials of the memory cells connected to respective second WLs are sequentially read, and when difference value between the real-time potential of one target memory cell and the first potential is greater than first pre-set value, it is determined that the WL driving circuit connected to the second WL corresponding to the target memory cell has a defect. 1. A defect detecting method for a Word Line (WL) driving circuit , comprising:selecting m WLs from a memory cell array and WL driving circuit arrays corresponding to the memory cell array to serve as m WLs to be tested, setting one of the m WLs to be tested as a first WL, and setting the remaining m−1 WLs to be tested as second WLs, wherein the m WLs to be tested are respectively and correspondingly connected to m different WL driving circuits, where m is an integer greater than 1;a first write operation of writing a first potential into memory cells correspondingly connected to all transistors controlled by the m WLs to be tested;a second write operation of writing a second potential into memory cells correspondingly connected to all transistors controlled by the first WL; anda read and determination operation of sequentially reading real-time potentials of memory cells correspondingly connected to all transistors controlled by respective second WLs, and when a difference value between a read real-time potential of a target memory cell and the first potential is greater than a first pre ...

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Номер записи: 82
24-02-2022 дата публикации

ENCODING TEST DATA OF MICROELECTRONIC DEVICES, AND RELATED METHODS, DEVICES, AND SYSTEMS

Номер: US20220059177A1
Автор: Johnson Jason M.
Принадлежит:

Memory devices are disclosed. A memory device may include a number of column planes, and at least one circuit. The at least one circuit may be configured to receive test result data for a column address for each column plane of the number of column planes of the memory array. The at least one circuit may also be configured to convert the test result data to a first result responsive to only one bit of a number of bits of the number of column planes failing a test for the column address. Further, the at least one circuit may be configured to convert the test result data to a second result responsive to only one column plane failing the test for the column address and more than one bit of the one column plane being defective. Methods of testing a memory device, and electronic systems are also disclosed. 1. A device , comprising:a memory array including a number of column planes; and receive test result data for a column address for each column plane of the number of column planes of the memory array;', 'convert the test result data to a first result responsive to only one bit of a number of bits of the number of column planes failing a test for the column address, the first result identifying the one bit and a column plane of the number of column planes that includes the one bit; and', 'convert the test result data to a second result responsive to only one column plane failing the test for the column address and more than one bit of the one column plane being defective, the second result identifying the one column plane., 'at least one circuit coupled to the memory array and configured to2. The device of claim 1 , wherein the at least one circuit is further configured to convert the test result data to a third result responsive to two or more column planes of the number of column planes failing the test for the column address.3. The device of claim 2 , wherein the at least one circuit is further configured to convert the test result data to a fourth result responsive ...

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Номер записи: 83
24-02-2022 дата публикации

FAIL BIT REPAIR METHOD AND DEVICE

Номер: US20220059182A1
Автор: CHEN Yui-Lang
Принадлежит: CHANGXIN MEMORY TECHNOLOGIES, INC.

A Fail Bit (FB) repair method and device can be applied to repairing an FB in a chip. The method includes: a bank to be repaired including multiple target repair banks in a chip to be repaired is determined; first repair processing is performed on a first FB in each target repair bank by using a redundant circuit; a second FB position determination step is executed to determine a bit position of a second FB, and second repair processing is performed on the second FB; unrepaired FBs in each target repair bank is determined, and the second FB position determination step is recursively executed to obtain a test repair position of each unrepaired FB to perform third repair processing on the unrepaired FB according to the test repair position. 1. A Fail Bit (FB) repair method , comprising:determining a bank to be repaired of a chip to be repaired, the bank to be repaired comprising multiple target repair banks;performing first repair processing on a first FB in each target repair bank by using a redundant circuit;after first repair processing is performed, executing a second FB position determination step to determine a bit position of a second FB in each target repair bank, and performing second repair processing on the second FB according to the bit position of the second FB; anddetermining unrepaired FBs in each target repair bank, and recursively executing the second FB position determination step to obtain a test repair position of each unrepaired FB to perform third repair processing on the unrepaired FB according to the test repair position.2. The method of claim 1 , wherein prior to the determining the bank to be repaired of the chip to be repaired claim 1 , the method further comprises:determining an initial bank to be repaired of the chip to be repaired, the initial bank to be repaired comprising initial Word Lines (WLs) and initial Bit Lines (BLs);acquiring a WL compression ratio and BL compression ratio of the initial bank to be repaired; andperforming ...

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Номер записи: 84
07-02-2019 дата публикации

SEMICONDUCTOR DEVICES

Номер: US20190043546A1
Автор: KOO Kibong
Принадлежит: SK HYNIX INC.

A semiconductor device may include a power supply circuit, a word line control circuit, and a memory circuit. The power supply circuit may drive a pre-charge voltage to a level of an external voltage based on a write initialization signal which is enabled if a command has a predetermined level combination. The word line control circuit may generates two or more word line selection signals that are sequentially counted based on the write initialization signal. The memory circuit may sequentially select a plurality of word lines based on the word line selection signals. The memory circuit may drive bit lines of memory cells connected to the selected word line to the pre-charge voltage. The memory circuit may store data, which are loaded on the bit lines to have a level of the pre-charge voltage, into the memory cells connected to the selected word line. 1. A semiconductor device comprising:a power supply circuit configured to drive a pre-charge voltage to a level of an external voltage based on a write initialization signal which is enabled if a command has a predetermined level combination;a word line control circuit configured to generate two or more word line selection signals that are sequentially counted based on the write initialization signal; anda memory circuit configured to sequentially select a plurality of word lines based on the word line selection signals, configured to drive bit lines of memory cells connected to the selected word line to the pre-charge voltage, and configured to store data, which are loaded on the bit lines to have a level of the pre-charge voltage, into the memory cells connected to the selected word line.2. The semiconductor device of claim 1 , wherein the external voltage is set to be a ground voltage.3. The semiconductor device of claim 1 , wherein the write initialization signal is a signal that activates an initialization operation for writing the data having a level of the external voltage into the memory cells.4. The ...

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Номер записи: 85
07-02-2019 дата публикации

FAILURE INDICATOR PREDICTOR (FIP)

Номер: US20190043602A1
Автор: Khatib Zadeh Amirali, Kudryavtsev Andrey, POLIAKOV Pavel, Qawami Shekoufeh
Принадлежит:

A memory controller includes a memory to store results of a reference performance test (RT) performed on a non-volatile memory (NVM) die, where the results of the RT include one or more first indicators of failure associated with one or more first read/write cycles of the NVM die before the NVM die is placed in use. The memory controller further includes an analyzer coupled with the memory to perform, in one or more second read/write cycles, one or more field tests that provide second indicators of failure associated with one or more second read/write cycles of the NVM die during the use of the NVM die, and further to predict and dynamically adjust, over one or more second read/write cycles, at least one of likelihood or expected time of failure of the NVM, based at least in part on the first and second indicators of failure. 1. A memory controller (MC) , comprising:a memory, to store results of a reference performance test (RT) performed on a non-volatile memory (NVM) die, wherein the results of the RT comprise one or more first indicators of failure associated with one or more first read and write cycles of the NVM die before the NVM die is placed in use; andan analyzer coupled with the memory, to:perform, in one or more second read/write cycles one or more field tests that provide second indicators of failure associated with one or more second read/write cycles of the NVM die during the use of the NVM die; andpredict and dynamically adjust, over the one or more second read/write cycles, at least one of likelihood or expected time of failure of the NVM, based at least in part on the first and second indicators of failure.2. The MC of claim 1 , wherein the memory is to store results of the one or more field tests that comprise the second indicators of failure.3. The MC of claim 2 , wherein the analyzer is to compare the first and second indicators of failure claim 2 , wherein the prediction is based at least in part on a result of the comparison.4. The MC of claim ...

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Номер записи: 86
01-05-2014 дата публикации

Boundary scan chain for stacked memory

Номер: US20140122952A1
Автор: David J. Zimmerman
Принадлежит: Individual

A boundary scan chain for stacked memory. An embodiment of a memory device includes a system element and a memory stack including one or more memory die layers, each memory die layer including input-output (I/O) cells and a boundary scan chain for the I/O cells. A boundary scan chain of a memory die layer includes a scan chain portion for each of the I/O cells, the scan chain portion for an I/O cell including a first scan logic multiplexer a scan logic latch, an input of the scan logic latch being coupled with an output of the first scan logic multiplexer, and a decoder to provide command signals to the boundary scan chain.

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Номер записи: 87
06-02-2020 дата публикации

STORAGE PROTOCOL MATCHING DEVICE AND METHOD

Номер: US20200043565A1
Автор: CHOI Soo Il, YUN Jong Yun
Принадлежит:

Disclosed is a storage test apparatus having a storage protocol matching device including an integrated protocol software unit and an integrated protocol hardware unit, in which, when an insertion of a storage is detected, a protocol configuration that matches a protocol of the storage is automatically set through a protocol switching, thereby enhancing the test efficiency. 1. A storage protocol matching device comprising:a control unit configured to provide a command signal for protocol matching;an integrated protocol software unit connected to the control unit and including a plurality of mutually different pieces of protocol software;an integrated protocol hardware unit connected to the integrated protocol software unit and including a plurality of mutually different pieces of protocol hardware corresponding to the plurality of mutually different pieces of protocol software;a connector serving as an interface for transmitting and receiving a test signal of a storage device, and provided with a detection pin for detecting an insertion of the storage device; anda switch unit configured to perform a protocol switching,wherein the control unit controls the switch unit to sequentially switch the plurality of mutually different pieces of protocol software and the plurality of mutually different pieces of protocol hardware in response to detecting the insertion of the storage device until the switched protocol software and the switched protocol hardware match a protocol of the storage device.2. The storage protocol matching device of claim 1 , wherein the detection pin includes a combination of a plurality of pins.3. The storage protocol matching device of claim 1 , wherein the switch unit is disposed to connect the integrated protocol hardware unit to the connector.4. The storage protocol matching device of claim 1 , wherein the storage device is a solid state drive (SSD).5. A storage test apparatus including the storage protocol matching device according to .6. The ...

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Номер записи: 88
18-02-2021 дата публикации

MEMORY CIRCUIT DEVICE AND A METHOD FOR TESTING THE SAME

Номер: US20210050069A1
Автор: NING Shu-Liang
Принадлежит:

A memory circuit device and a memory test method are disclosed. The memory circuit device includes: a memory cell array, including storage lines and redundant storage lines; and a redundant decoder control circuit, configured to receive an address of a failed storage line from a testing device and activate a corresponding redundant storage line based on the address of the failed storage line, so that the redundant storage line can replace and store data in the failed storage line, wherein the address of the failed storage line is determined while testing operation status of the storage lines in the memory cell array. Embodiments of the present invention can improve repair efficiency of the memory circuit device through activating the associated redundant storage line by the redundant decoder control circuit based on the address of the failed storage line rather than under the control of an external controller. 1. A memory circuit device , comprising:a memory cell array comprising at least one storage line and at least one redundant storage line for storing data; anda redundant decoder control circuit configured to receive an address of a failed storage line from a testing device and activate a corresponding redundant storage line based on the address of the failed storage line, wherein the corresponding redundant storage line replaces the failed storage line and stores data,wherein the address of the failed storage line is determined by the testing device while testing operation status of the at least one storage line of the memory cell array, andthe redundant decoder control circuit comprises: at least one redundant storage line control unit, each of the at least one redundant storage line control unit connected to a corresponding redundant storage line, a register unit for receiving the address of the failed storage line from the testing device and storing the address of the failed storage line;', 'an enabling unit for providing, based on an activation signal, an ...

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Номер записи: 89
16-02-2017 дата публикации

SEMICONDUCTOR MEMORY CELL MULTI-WRITE AVOIDANCE ENCODING APPARATUS, SYSTEMS AND METHODS

Номер: US20170047130A1
Автор: Bittlestone Clive, Goel Manish, Qiu Yunchen, Zhang Sai, Zhu Yuming
Принадлежит:

Data words to be written to a memory location are delta encoded in multi-write avoidance (“MWA”) code words. MWA code words result in no re-writing of single-bit storage cells containing logical “0's” to a “0” state and no re-writing of logical “1's” to cells that have already been written once to a logical “1.” Potential MWA code words stored in a look-up table (“LUT”) are indexed by a difference word DELTA_D. DELTA_D represents a bitwise difference (“delta”) between a data word currently stored at the memory location and a new data word (“NEW_D”) to be stored at the memory location. Validation and selection logic chooses an MWA code word representing NEW_D to be written if the MWA code word does not violate the principle of multi-write avoidance. Some embodiments generate the MWA code words using a pattern generator rather than indexing the MWA code words from a LUT. 1. A semiconductor memory cell multi-write avoidance (“MWA”) encoding apparatus , comprising:a memory cell reset avoidance (“MCRA”) decoder to receive an existing (2̂m)−1 bit wide MWA code word (“OLD_C”) from a subset of storage cells in a semiconductor memory array, OLD_C representing an existing m-bit data word (“OLD_D”), the MCRA decoder to decode OLD_C to determine OLD_D;a two-dimensional delta encoding look-up table (“LUT”) communicatively coupled to the MCRA decoder to be indexed by a DELTA_D, the DELTA_D an m-bit word, each set bit of the DELTA_D representing a state change at a corresponding bit position between the OLD_D and a NEW_D to be encoded as a NEW_C and stored in the subset of storage cells in the semiconductor storage array, the delta encoding LUT to store a plurality of potential difference code words DELTA_C(I) corresponding to each possible DELTA_D, each set bit of each DELTA_C(I) representing a state change at a corresponding bit position between the OLD_C and the NEW_C, at least one of the plurality of difference code words DELTA_C(I) to satisfy an MWA requirement of having no ...

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Номер записи: 90
15-02-2018 дата публикации

NON-VOLATILE MEMORY TESTING

Номер: US20180047458A1
Автор: Bucksch Thorsten
Принадлежит:

Devices, systems and methods are provided which comprise testing of a non-volatile memory concurrently during at least a part of a testing of other system parts by a processor (). 1. A device , comprising:a processor,a non-volatile memory,a test controller, andat least one further circuit part,wherein, in a test mode, the processor is configured to test the at least one further circuit part, and wherein the test controller is configured to test the non-volatile memory concurrently with at least part of the testing of the at least one further circuit part.2. The device of claim 1 , wherein the device is implemented as a System-on-Chip.3. The device of claim 1 , wherein the test controller is separate from the non-volatile memory.4. The device of claim 3 , further comprising a bus system coupling the processor claim 3 , the non-volatile memory and the at least one further circuit part claim 3 , the device further comprising a multiplexer configured to the decouple the non-volatile memory from the processor during the test mode.5. The device of claim 1 , wherein the test controller is incorporated in a memory controller of the non-volatile memory.6. The device of claim 1 , wherein the test controller is configured to be suspended in order to suspend testing of the non-volatile memory.7. The device of claim 6 , wherein the processor is configured to suspend the test controller during some phases of testing of the at least one further circuit part.8. The device of claim 7 , wherein the some phases of testing comprise operating conditions negatively influencing testing of the non-volatile memory.9. The device of claim 1 , wherein the non-volatile memory comprises a flash memory.10. A System-on-Chip claim 1 , comprising:a microcontroller,a flash memory,further circuits, anda built-in self-test controller,wherein the built-in self-test controller is configured to test the flash memory at least in part concurrently to the microcontroller testing at least some of the further ...

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Номер записи: 91
03-03-2022 дата публикации

TESTING CIRCUIT, TESTING DEVICE AND TESTING METHOD THEREOF

Номер: US20220068416A1
Автор: Zhang Liang
Принадлежит: CHANGXIN MEMORY TECHNOLOGIES, INC.

A testing circuit includes: a first sampling module configured to receive a to-be-tested pulse signal, and generate a first sampled signal according to the pulse signal; and a second sampling module configured to receive the pulse signal, and generate a second sampled signal according to the pulse signal. The second sampled signal and the first sampled signal have a phase difference, the phase difference being equal to a pulse width of the pulse signal. 1. A testing circuit , comprising:a first sampling module, configured to receive a to-be-tested pulse signal, and generate a first sampled signal according to the pulse signal; anda second sampling module, configured to receive the pulse signal, and generate a second sampled signal according to the pulse signal,wherein the second sampled signal and the first sampled signal have a phase difference, the phase difference being equal to a pulse width of the pulse signal.2. The testing circuit of claim 1 , wherein the first sampling module is configured to generate the first sampled signal in response to a falling edge of the pulse signal claim 1 , and the second sampling module is configured to generate the second sampled signal in response to a rising edge of the pulse signal.3. The testing circuit of claim 1 , wherein a first delay time of the first sampling module on a first transmission path is equal to a second delay time of the second sampling module on a second transmission path.4. The testing circuit of claim 1 , wherein the first sampling module comprises:a first temporary storage unit, configured to sample a first to-be-sampled signal in response to the pulse signal so as to generate a first temporary storage signal, wherein a triggering type of the first temporary storage unit is edge triggering, and an edge of the first temporary storage signal corresponds to a first edge of the pulse signal and corresponds to an edge of the first sampled signal.5. The testing circuit of claim 4 , wherein the first temporary ...

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Номер записи: 92
03-03-2022 дата публикации

MITIGATING SINGLE-EVENT UPSETS USING CONTAINERIZATION

Номер: US20220068421A1
Автор: Kaemmer Joseph, Ridgway Chris K., Thommana John V.
Принадлежит:

A computing system is disclosed. The computing system includes a computation unit, one or more processors, a volatile memory, and a non-volatile memory communicatively coupled to the one or more processors and having instructions stored thereon, which when executed by the one or more processors, causing the one or more processor to instantiate a container and perform at least one of a volatile memory checking procedure or a non-volatile memory checking procedure. The volatile memory checking procedure includes checking the first physical address space for errors, loading a container into volatile memory containing the first physical address space if an error is determined, rechecking the first physical address space for error, loading the container to a second physical address space and updating a memory management unit if an error in the first physical address space is determined. 1. A computing system comprising: one or more one processors;', 'the volatile memory; and, 'a computation unit on-board a low earth orbit satellite configured to resolve single-event upsets in a volatile memory, comprising instantiate a container upon the volatile memory, wherein the container is configured as a self-contained architecture that includes a parsed component of an application, and metadata, wherein the metadata contains at least one of a digests or error correction coding; and', checking a first physical address space of the volatile memory for the error, wherein the first address space is configured to store a portion of the container, wherein checking a first physical address space includes at least one of detecting the digest or a checksum based on the error correction coding;', 'loading at least one of the container or a test pattern into volatile memory that includes the first physical address space when the error is determined in the first address space;', 'rechecking the first physical address space for errors;', updating a memory management unit corresponding to the ...

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Номер записи: 93
03-03-2022 дата публикации

MANAGING BLOCK RETIREMENT FOR TEMPORARY OPERATIONAL CONDITIONS

Номер: US20220068422A1
Автор: Brandt Kevin R., Hale Christopher S., Hamilton Marc S., Muchherla Kishore Kumar, Ratnam Sampath K., Stoller Scott A., Thomson Preston A.
Принадлежит:

A processing device in a memory system detects a data loss occurrence in a block of a memory component. The processing device further designates the block as a quarantined block, performs a stress test on the block, and depending on whether the stress test on the block satisfies a testing criterion, either designates the block as usable by the memory component or retires the block of the memory component. 1. A system comprising:a memory component; anda processing device, operatively coupled with the memory component, to perform operations comprising:detecting a data loss occurrence in a block of the memory component;designating the block as a quarantined block, performing a stress test on the block of the memory component; anddepending on whether the stress test on the block of the memory component satisfies a testing criterion, either designating the block as usable by the memory component or retiring the block of the memory component.2. The system of claim 1 , wherein designating the block as the quarantined block comprises designating claim 1 , for a predetermined time period claim 1 , the block as unusable by the memory component for storing host data.3. The system of claim 1 , wherein designating the block as usable by the memory component comprises:designating the block as a healthy block; anddesignating the block as usable by the memory component for storing host data.4. The system of claim 1 , wherein the operations further comprise:identifying a behavioral criterion associated with the data loss occurrence in the block of the memory component; andincrementing a counter associated with the block in response to the identified behavioral criterion, wherein a value of the counter corresponds to a number of occurrences of a plurality of behavioral criteria causing data loss occurrences in the block,wherein the block is designated as the quarantined block responsive to determining that the value of the counter satisfies a first threshold criterion.5. The system ...

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Номер записи: 94
13-02-2020 дата публикации

COMPARATOR

Номер: US20200049763A1
Автор: Yamada Shigekazu
Принадлежит: MICRON TECHNOLOGY, INC.

A device includes a comparator, a reference signal node electrically coupled to a first input of the comparator, a plurality of test signal nodes, a plurality of first select signal nodes, a first multiplexer coupled between the plurality of test signal nodes and the comparator, a plurality of latches, a plurality of second select signal nodes, and a second multiplexer coupled between an output of the comparator and the plurality of latches. Each first select signal node corresponds to a test signal node. The first multiplexer electrically couples one of the plurality of test signal nodes to a second input of the comparator in response to a corresponding first select signal. Each latch corresponds to a test signal node. Each second select signal node corresponds to a latch. The second multiplexer electrically couples the output of the comparator to an input of one of the plurality of latches in response to a corresponding second select signal. 1. A device comprising:a comparator;a reference signal node electrically coupled to a first input of the comparator;a plurality of test signal nodes;a plurality of first select signal nodes, each first select signal node corresponding to a test signal node;a first multiplexer coupled between the plurality of test signal nodes and the comparator, the first multiplexer to electrically couple one of the plurality of test signal nodes to a second input of the comparator in response to a corresponding first select signal on one of the plurality of first select signal nodes;a plurality of latches, each latch corresponding to a test signal node;a plurality of second select signal nodes, each second select signal node corresponding to a latch; anda second multiplexer coupled between an output of the comparator and the plurality of latches, the second multiplexer to electrically couple the output of the comparator to an input of one of the plurality of latches in response to a corresponding second select signal on one of the plurality ...

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Номер записи: 95
14-02-2019 дата публикации

APPARATUSES AND METHODS FOR HIGH SPEED WRITING TEST MODE FOR MEMORIES

Номер: US20190051369A1
Автор: DIETRICH Stefan, Spirkl Wolfgang
Принадлежит: MICRON TECHNOLOGY, INC.

Apparatuses and methods are provided for a high speed writing test mode for memories. An example apparatus includes a memory core, a data terminal coupled to a data receiver, a read buffer coupled between the data terminal and the memory core, and a write buffer coupled between the data receiver and the memory core. The write buffer may include at least a first input coupled to the data receiver, and a second input. While in a test mode, the write buffer may be loaded with data from the second input instead of the first input. 1. An apparatus comprising:a memory core including a data path and a memory array;a data receiver coupled to a data terminal;a write buffer including a first input coupled to the data receiver and a second input, and an output coupled to the data path; anda test mode circuit configured to cause data to be loaded into the write buffer from the second input, in response to a test mode command.2. The apparatus of claim 1 , wherein claim 1 , in test mode claim 1 , the test mode circuit is further configured to prevent data loaded to the write buffer via the second input from being overwritten.3. The apparatus of claim 2 , wherein the test mode circuit is further configured to disable an input pointer of the write buffer.4. The apparatus of claim 1 , wherein the test mode circuit is further configured to disconnect the first input from the data receiver.5. The apparatus of claim 4 , wherein disconnecting the first input from the data receiver includes disabling the data receiver.6. The apparatus of claim 1 , wherein the second input is coupled claim 1 , via a switch claim 1 , o a read buffer claim 1 , wherein data is loaded into the read buffer via an address bus.7. The apparatus claim 1 , wherein the second input is coupled to an address bus.8. The apparatus of claim 1 , further comprising:a transmitter coupled to the data terminal; anda read buffer having an output coupled to the transmitter and having an in coupled to the data path.9. The ...

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Номер записи: 96
14-02-2019 дата публикации

METHODS, SYSTEMS AND APPARATUS FOR IN-FIELD TESTING FOR GENERIC DIAGNOSTIC COMPONENTS

Номер: US20190051370A1
Автор: Azam Asad, Chakravarty Sreejit, Chen Kaitlyn, Raja Gopal R Selvakumar
Принадлежит: Intel Corporation

The disclosed embodiments relate to method, apparatus and system for testing memory circuitry and diagnostic components designed to test the memory circuitry. The memory may be tested regularly using Memory Built-In Self-Test (MBIST) to detect memory failure. Error Correction Code (ECC)/Parity is implemented for SRAM/Register Files/ROM memory structures to protect against transient and permanent faults during runtime. ECC/Parity encoder and decoder logic detect failure on both data and address buses and are intended to catch soft error or structural fault in address decoding logic in SRAM Controller, where data may be read/written from/to different locations due to faults. ECC/parity logic on the memory structures are subject to failures. In certain exemplary embodiments, an array test controller is used to generate and transmit error vectors to thereby determine faulty diagnostic components. The test vectors may be generated randomly to test the diagnostic components during run-time for in-field testing. 1. A system to provide in-field testing to diagnose components , the system comprising:a memory circuitry;a diagnostic component in communication with the memory, the diagnostic component configured to test the memory for ECC/Parity check; generate a test vector for in-field diagnostic of one or more of the memory circuitry and the diagnostic component;', 'transmit the test vector to one or more of the diagnostic component and the memory circuitry;', 'receive a response to the test vector from one of the memory circuitry or the diagnostic component; and', 'detect an error by comparing the received response with the test vector., 'an array test controller to communicate with the memory circuit and the at least one diagnostic component, the array test controller configured to2. The system of claim 1 , wherein the array test controller is further configured to store the received response.3. The system of claim 1 , wherein the test vector is one of pseudorandom test ...

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Номер записи: 97
14-02-2019 дата публикации

REPAIR DEVICE AND SEMICONDUCTOR DEVICE INCLUDING THE SAME

Номер: US20190051371A1
Автор: KIM Jong Sam
Принадлежит:

A repair device and a semiconductor device including the same are disclosed, which relate to a technology for a Post Package Repair (PPR) device. The repair device includes: a clock generator configured to generate a fuse clock signal based to corresponding to an available fuse; a fuse selection circuit configured to discriminate between a first clock signal and a second clock signal in the fuse clock signal; a fuse signal generator configured to output a first repair signal corresponding to the first clock signal and a second repair signal corresponding to the second clock signal during a post package repair (PPR) mode; and an output circuit configured to output a first output signal by detecting address information of the remaining unused fuses in response to the first repair signal, or configured to output a second output signal by detecting address information of the remaining unused fuses. 1. A repair device comprising:a clock generator configured to generate a fuse clock signal corresponding to an available fuse based to a fuse signal indicating whether a fuse is used or not;a fuse selection circuit configured to discriminate between a first clock signal and a second clock signal in the fuse clock signal in response to a first signal and a second signal;a repair signal generator configured to output a first repair signal corresponding to the first clock signal and a second repair signal corresponding to the second clock signal during a post package repair (PPR) mode; andan output circuit configured to output a first output signal by detecting address information of the remaining unused fuses in response to the first repair signal, or configured to output a second output signal by detecting address information of the remaining unused fuses in response to the second repair signal.2. The repair device according to claim 1 , wherein the post package repair PPR mode is a hard—post package repair (HPPR) mode.3. The repair device according to claim 1 , wherein the ...

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Номер записи: 98
25-02-2021 дата публикации

CONCURRENT TESTING OF A LOGIC DEVICE AND A MEMORY DEVICE WITHIN A SYSTEM PACKAGE

Номер: US20210057036A1
Автор: Khan Amanulla, Kodihalli Himakiran, Nachiappan Thenappan, Sreesailam Sreekar, YANG Kelly, Zhang Lianrui
Принадлежит:

Testing packaged integrated circuit (IC) devices is difficult and time consuming. When multiple devices (dies) are packaged to produce a SiP (system in package) the devices should be tested for defects that may be introduced during the packaging process. With limited access to the inputs and outputs of the devices, test times increase compared with testing the devices before they are packaged. A CoWoS (chip on wafer on substrate) SiP includes a logic device and a memory device and has interfaces between the logic device and memory device that cannot be directly accessed at a package ball. Test programs are concurrently executed by the logic device and the memory device to reduce testing time. Each memory device includes a BIST (built-in self-test) module that is initialized and executes the memory test program while the one or more modules within the logic device are tested. 1. A computer-implemented method , comprising:initializing a memory device within a system package for testing, wherein the system package includes the memory device and a logic device, a first portion of signals between the memory device and a logic device are routed within an interposer or through silicon vias (TSVs) enclosed by the system package and a second portion of signals for the logic device are coupled to package balls of the system package;executing a first test program to test the memory device; andconcurrent with execution of the first test program, executing a second test program to test a first module within the logic device.2. The computer-implemented method of claim 1 , further comprising claim 1 , concurrent with execution of the first test program claim 1 , executing a third test program to test a second module within the logic device.3. The computer-implemented method of claim 2 , wherein the second test program and the third test program are executed concurrently.4. The computer-implemented method of claim 2 , wherein the second test program and the third test program are ...

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Номер записи: 99
22-02-2018 дата публикации

Semiconductor device, test program, and test method

Номер: US20180053546A1
Автор: Atsushi Miyanishi, Yoshisato Yokoyama, Yuichiro Ishii
Принадлежит: Renesas Electronics Corp

When a screening test at a normal temperature is performed instead of a low temperature screening test of SRAM, overkill is reduced and risk of outflow of defects due to local variation is suppressed. An SRAM including a word line, a bit line pair, a memory cell, and a drive circuit that drives the bit line pair is provided with a function that can drive one bit line of the bit line pair at a high level (VDD) potential and drive the other bit line at an intermediate potential (VSS+several tens mV to one handled and several tens mV) a little higher than a low level (VSS) potential for normal writing when writing data into the memory cell.

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Номер записи: 100