Поиск патентов

05-01-2012 дата публикации

Dynamically setting burst length of double data rate memory device by applying signal to at least one external pin during a read or write transaction

Номер: US20120005420A1

Принадлежит: Round Rock Research LLC

One or more external control pins and/or addressing pins on a memory device are used to set one or both of a burst length and burst type of the memory device.

Подробнее

Номер записи: 1

12-01-2012 дата публикации

Precharging circuit and semiconductor memory device including the same

Номер: US20120008446A1

Автор: Seung-Bong Kim

Принадлежит: Hynix Semiconductor Inc

A semiconductor memory device includes a write driver for transmitting data loaded on a global line to a local line pair, a read driver for transmitting data loaded on the local line pair to the global line, a core region for storing data loaded on the local line pair or provide stored data to the local line pair, and a precharging circuit configured to precharge the local line pair by selectively using a first voltage and a second voltage in response to a precharge control signal and an operation mode signal, wherein the second voltage is lower than the first voltage.

Подробнее

Номер записи: 2

09-02-2012 дата публикации

Level shifter for use with memory arrays

Номер: US20120033508A1

Автор: Chad A. Adams, Elizabeth L. Gerhard, Jeffrey M. Scherer, Sharon H. Cesky

Принадлежит: International Business Machines Corp

In a first aspect, a level shifter circuit for use in a memory array is provided that includes (1) a first voltage domain powered by a first voltage; (2) a second voltage domain powered by a second voltage; (3) level shifter circuitry that converts an input signal from the first voltage domain to the second voltage domain; and (4) isolation circuitry that selectively isolates the first voltage domain from the second voltage domain so as to selectively prevent current flow between the first voltage domain and the second voltage domain. Numerous other aspects are provided.

Подробнее

Номер записи: 3

16-02-2012 дата публикации

Memory systems and memory modules

Номер: US20120042204A1

Автор: Michael John Sebastian Smith, Suresh Natarajan Rajan

Принадлежит: Google LLC

One embodiment of the present invention sets forth a memory module that includes at least one memory chip, and an intelligent chip coupled to the at least one memory chip and a memory controller, where the intelligent chip is configured to implement at least a part of a RAS feature. The disclosed architecture allows one or more RAS features to be implemented locally to the memory module using one or more intelligent register chips, one or more intelligent buffer chips, or some combination thereof. Such an approach not only increases the effectiveness of certain RAS features that were available in prior art systems, but also enables the implementation of certain RAS features that were not available in prior art systems.

Подробнее

Номер записи: 4

22-03-2012 дата публикации

Different types of memory integrated in one chip by using a novel protocol

Номер: US20120072647A1

Автор: Fu-Chang Hsu, Peter Wung Lee

Принадлежит: Aplus Flash Technology Inc

A semiconductor chip contains four different memory types, EEPROM, NAND Flash, NOR Flash and SRAM, and a plurality of major serial/parallel interfaces such as I 2 C, SPI, SDI and SQI in one memory chip. The memory chip features write-while-write and read-while-write operations as well as read-while-transfer and write-while-transfer operations. The memory chip provides for eight pins of which two are for power and up to four pins have no connection for specific interfaces and uses a novel unified nonvolatile memory design that allow the integration together of the aforementioned memory types integrated together into the same semiconductor memory chip.

Подробнее

Номер записи: 5

26-04-2012 дата публикации

Memory module with memory stack and interface with enhanced capabilities

Номер: US20120102292A1

Автор: David T. Wang, Frederick Daniel Weber, Keith R. Schakel, Michael J.S. Smith, Suresh N. Rajan

Принадлежит: Google LLC

A memory module, which includes at least one memory stack, comprises a plurality of DRAM integrated circuits and an interface circuit. The interface circuit interfaces the memory stack to a host system so as to operate the memory stack as a single DRAM integrated circuit. In other embodiments, a memory module includes at least one memory stack and a buffer integrated circuit. The buffer integrated circuit, coupled to a host system, interfaces the memory stack to the host system so to operate the memory stack as at least two DRAM integrated circuits. In yet other embodiments, the buffer circuit interfaces the memory stack to the host system for transforming one or more physical parameters between the DRAM integrated circuits and the host system.

Подробнее

Номер записи: 6

10-05-2012 дата публикации

Semiconductor memory device and driving method of semiconductor memory device

Номер: US20120113707A1

Автор: Yasuhiko Takemura

Принадлежит: Semiconductor Energy Laboratory Co Ltd

A novel semiconductor memory device whose power consumption is low is provided. A source of a writing transistor WTr_n_m, a gate of a reading transistor RTr_n_m, and one electrode of a capacitor CS_n_m are connected to each other. A gate and a drain of the writing transistor WTr_n_m are connected to a writing word line WWL_n and a writing bit line WBL_m, respectively. The other electrode of the capacitor CS_n_m is connected to a reading word line RWL_n. A drain of the reading transistor RTr_n_m is connected to a reading bit line RBL_m. Here, the potential of the reading bit line RBL_m is input to an inverting amplifier circuit such as a flip-flop circuit FF_m to be inverted by the inverting amplifier circuit. This inverted potential is output to the writing bit line WBL_m.

Подробнее

Номер записи: 7

31-05-2012 дата публикации

Memory Modules and Devices Supporting Configurable Core Organizations

Номер: US20120134084A1

Автор: Craig E. Hampel, Donald C. Stark, Ely K. Tsern, Frederick A. Ware, Richard E. Perego

Принадлежит: RAMBUS INC

Described are memory apparatus organized in memory subsections and including configurable routing to support multiple data-width configurations. Relatively narrow width configurations load fewer sense amplifiers, resulting in reduced power usage for relatively narrow memory configurations. Also described are memory controllers that convey width selection information to configurable memory apparatus and support point-to-point data interfaces for multiple width configurations.

Подробнее

Номер записи: 8

21-06-2012 дата публикации

Memory Module With Reduced Access Granularity

Номер: US20120159061A1

Автор: Craig E. Hampel, Frederick A. Ware

Принадлежит: RAMBUS INC

A memory module having reduced access granularity. The memory module includes a substrate having signal lines thereon that form a control path and first and second data paths, and further includes first and second memory devices coupled in common to the control path and coupled respectively to the first and second data paths. The first and second memory devices include control circuitry to receive respective first and second memory access commands via the control path and to effect concurrent data transfer on the first and second data paths in response to the first and second memory access commands.

Подробнее

Номер записи: 9

28-06-2012 дата публикации

Auto-precharge signal generator

Номер: US20120163100A1

Автор: Sun Young Hwang, Yin Jae Lee

Принадлежит: Hynix Semiconductor Inc

An auto-precharge signal generation circuit comprises a signal generator, a set signal generator, and an auto-precharge signal generator. The signal generator is configured to generating a control signal and a precharge control signal in response to receiving a first column address strobe signal and an auto-precharge flag signal. The set signal generator is configured to generating a set signal in response to receiving the control signal and the precharge control signal. The auto-precharge signal generator is configured to generate an auto-precharge signal in response to receiving the set signal and a period set signal.

Подробнее

Номер записи: 10

09-08-2012 дата публикации

Memory System with Calibrated Data Communication

Номер: US20120204054A1

Автор: Benedict Chung-Kwong Lau, Bruno W. Garlepp, Donald C. Stark, Jared Levan Zerbe, Jun Kim, Kevin S. Donnelly, Leung Yu, Mark A. Horowitz, Roxanne Vu, Stefanos Sidiropoulos, Tsyr-Chyang Ho

Принадлежит: RAMBUS INC

An integrated circuit device includes a transmitter circuit operable to transmit a timing signal over a first wire to a DRAM. The DRAM receives a first signal having a balanced number of logical zero-to-one transitions and one-to-zero transitions and samples the first signal at a rising edge of the timing signal to produce a respective sampled value. The device further includes a receiver circuit to receive the respective sampled value from the DRAM over a plurality of wires separate from the first wire. In a first mode, the transmitter circuit repeatedly transmits incrementally offset versions of the timing signal to the DRAM until sampled values received from the DRAM change from a logical zero to a logical one or vice versa; and in a second mode, it transmits write data over the plurality of wires to the DRAM according to a write timing offset generated based on the sampled values.

Подробнее

Номер записи: 11

30-08-2012 дата публикации

Semiconductor memory apparatus

Номер: US20120218849A1

Автор: Kie Bong Ku

Принадлежит: Hynix Semiconductor Inc

A semiconductor memory apparatus includes a memory cell array including a plurality of chips, a control circuit configured to control an internal operation of the memory cell array, a power circuit configured to supply power to the control circuit, and a mode setting circuit configured to output a flag signal for power supply control based on a mode register set command and data received through a data input/output pad, in response to a clock enable signal.

Подробнее

Номер записи: 12

27-09-2012 дата публикации

Semiconductor memory device and method of setting operation environment therein

Номер: US20120243365A1

Автор: Kazushige Kanda, Toshihiro Suzuki

Принадлежит: Toshiba Corp

A semiconductor memory device comprises: a memory cell array including a plurality of memory cells; an internal circuit having a function required in a storage operation of the memory cell array; a parameter storage unit configured to store a certain parameter and to have a storage place specified by a parameter address, the certain parameter designating an operation of the internal circuit; a command register configured to store a command instructing an operation of the internal circuit; and a converting circuit configured to adjust at least one of the parameter address and the command that differ between products or between standards to the internal circuit.

Подробнее

Номер записи: 13

13-12-2012 дата публикации

Asynchronous/synchronous interface

Номер: US20120314517A1

Автор: Chih Liang Chen, Dean K. Nobunaga, June Lee

Принадлежит: Micron Technology Inc

The present disclosure includes methods, and circuits, for operating a memory device. One method embodiment for operating a memory device includes controlling data transfer through a memory interface in an asynchronous mode by writing data to the memory device at least partially in response to a write enable signal on a first interface contact, and reading data from the memory device at least partially in response to a read enable signal on a second interface contact. The method further includes controlling data transfer in a synchronous mode by transferring data at least partially in response to a clock signal on the first interface contact, and providing a bidirectional data strobe signal on an interface contact not utilized in the asynchronous mode.

Подробнее

Номер записи: 14

28-02-2013 дата публикации

High speed multiple memory interface i/o cell

Номер: US20130049799A1

Автор: Cheng-Gang Kong, Dharmesh Bhakta, Hong-Him Lim, Todd Randazzo

Принадлежит: LSI Corp

A calibration circuit includes an amplifier, a current steering digital-to-analog converter (DAC), a comparator, a slew calibration network, and an on-die termination (ODT) network. The amplifier generally has a first input, a second input, and an output. The first input generally receives a reference signal. The current steering digital-to-analog converter (DAC) generally has a first input coupled to the output of the amplifier, a first output coupled to the second input of the amplifier, and a second output coupled to a circuit node. The comparator generally has a first input receiving the reference signal, a second input coupled to the circuit node, and an output at which an output of the calibration circuit may be presented. The slew calibration network is generally coupled to the circuit node and configured to adjust a slew rate of the calibration circuit. The on-die termination (ODT) network is generally coupled to the circuit node.

Подробнее

Номер записи: 15

28-02-2013 дата публикации

Semiconductor apparatus

Номер: US20130051110A1

Автор: Kenichi Kuboyama, Muneaki Matsushige, Shuuichi Senou, Susumu Takano, Toshiharu Okamoto, Toshihiko Funaki

Принадлежит: Renesas Electronics Corp

A semiconductor apparatus according to an aspect of the present invention includes first and second bus-interface circuits, a first memory core connected to the first bus-interface circuit through a first data bus, the first memory core being connected to a first access control signal output from the first bus-interface circuit, a second memory core connected to the second bus-interface circuit through a second data bus, and a select circuit that selectively connects one of the first access control signal and a second access control signal output from the second bus-interface circuit to the second memory core.

Подробнее

Номер записи: 16

11-04-2013 дата публикации

NONVOLATILE MEMORY DEVICE AND METHOD OF OPERATING THE SAME

Номер: US20130088930A1

Автор: Cho Myung, HAH Beom Seok, KIM Ji Hwan, Lee Jung Hwan, Park Seong Je

Принадлежит: SK HYNIX INC.

A nonvolatile memory device includes a page buffer unit configured to include a plurality of page buffers coupled to the respective bit lines; a pass/fail circuit coupled to the page buffer unit and configured to perform a pass/fail check operation by comparing the amount of current, varying according to verify data stored in the plurality of page buffers, with an amount of reference current corresponding to the number of allowed error correction code bits; and a masking circuit configured to preclude the pass/fail check operation by coupling a ground terminal to sense nodes coupled to the remaining page buffers, respectively, other than page buffers corresponding to column addresses having the identical upper bits as an input column address. 1. A nonvolatile memory device , comprising:a page buffer unit configured to comprise a plurality of page buffers coupled to respective bit lines;a pass/fail circuit coupled to the page buffer unit and configured to perform a pass/fail check operation by comparing an amount of current, varying according to verify data stored in the plurality of page buffers, with an amount of reference current corresponding to a number of allowed error correction code bits; anda masking circuit configured to preclude the pass/fail check operation by coupling a ground terminal to sense nodes coupled to the remaining page buffers, respectively, other than page buffers corresponding to column addresses having identical upper bits as an input column address.2. The nonvolatile memory device of claim 1 , wherein each of the plurality of page buffers temporarily stores the verify data by sensing a program state of memory cells comprising the page buffer and controls a potential of a sense node based on the verify data.3. The nonvolatile memory device of claim 2 , wherein each of the plurality of page buffers comprises:a line coupling circuit for coupling a respective bit line and the sense node;a precharge circuit for precharging the sense node;a ...

Подробнее

Номер записи: 17

02-05-2013 дата публикации

Semiconductor system including semiconductor device

Номер: US20130107641A1

Автор: Jeong Hun Lee

Принадлежит: Hynix Semiconductor Inc

A semiconductor system includes a controller configured to apply code signals for setting levels of a reference voltage and data, and to receive output data. The semiconductor system also includes a semiconductor device configured to receive the data for the respective levels of the reference voltage set according to the code signals, to compare the reference voltages with the data to generate new data, to store the new data as internal data, and to process the stored internal data to output as the output data.

Подробнее

Номер записи: 18

02-05-2013 дата публикации

Semiconductor memory device and operating method thereof

Номер: US20130111101A1

Автор: Seok-Cheol Yoon

Принадлежит: Hynix Semiconductor Inc

A semiconductor memory device includes a path control unit configured to activate an address transmission path corresponding to a bank address, an address providing unit configured to provide a memory address to the path control unit in response to an active signal, and a plurality of memory banks each configured to receive the memory address provided through the corresponding address transmission path of the path control unit, wherein the bank address corresponds to a memory bank of the plurality of memory banks.

Подробнее

Номер записи: 19

09-05-2013 дата публикации

Semiconductor memory device and system having redundancy cells

Номер: US20130117615A1

Автор: Dae-Hyun Kim, Su-a Kim, Woo-Jin Lee

Принадлежит: Individual

In one embodiment, the memory device includes a memory cell array, to data line selection circuit and selection control logic. The memory cell array has at least a first memory cell group and a redundancy memory cell group. The first memory cell group includes a plurality of first memory cells associated with a first data line, and the redundancy memory cell group includes a plurality of redundancy memory cells associated with a redundancy data line. The selection control logic is configured to detect if a defective memory cell in the first memory cell group is being accessed, and is configured to control the data line selection circuit to replace access via the first data line with access via the redundancy data line such that a detected defective memory cell in the first memory cell group is replaced with one of the plurality of redundancy memory cells.

Подробнее

Номер записи: 20

13-06-2013 дата публикации

MEMORY SYSTEM AND DATA TRANSMISSION METHOD

Номер: US20130148448A1

Автор: MATSUI Yoshinori

Принадлежит: ELPIDA MEMORY, INC.

A memory system of a high-speed operation can be realized by reducing an influence of reflection signals etc. caused by branching and impedance mismatching in various wirings between a memory controller and a memory module, and an influence due to transmission delays of data, command/address, and clocks in the memory module. To this end, a memory system comprises a memory controller and a memory module mounted with DRAMs. A buffer is mounted on the memory module. The buffer and the memory controller are connected to each other via data wiring, command/address wiring, and clock wiring. The DRAMs and the buffer on the memory module are connected to each other via internal data wiring, internal command/address wiring, and internal cock wiring. The data wiring, the command/address wiring, and the clock wiring may be connected to buffers of other memory modules in cascade. Between the DRAMs and the buffer on the memory module, high-speed data transmission is implemented using data phase signals synchronous with clocks. 1. A memory system comprising:a substrate;a plurality of memory chips mounted over the substrate, the plurality of memory chips receiving a first signal and a second signal;a memory buffer mounted over the substrate, the memory buffer including a detection circuit which detects a skew between the first signal and the second signal, and the memory buffer including an adjustment circuit which adjusts a relationship between the first signal and the second signal based on the skew.a first wiring configured to commonly couple each of the plurality of memory chips for transferring the first signal to the each of the plurality of memory chips in common; anda plurality of second wirings corresponding with the plurality of memory chips, each first end of the plurality of second wirings configured to couple to an associated one of the plurality of memory chips independently for transferring the second signal to an associated one of the plurality of memory chips.2. ...

Подробнее

Номер записи: 21

27-06-2013 дата публикации

Configuration Context Switcher with a Latch

Номер: US20130162291A1

Автор: Jason Redgrave, Martin Voogel, Trevis Chandler

Принадлежит: Tabula Inc

Some embodiments provide an IC with configuration context switchers. The IC includes several configurable circuits, each of which configurably performs one of several operations at any given time, based on the configuration data set that it receives at that time. The IC includes several storage circuits for storing several configuration data sets for each of the configurable circuits. The IC also includes a context switching interconnect circuit for switchably connecting the configurable circuit to different sets of storage circuits to receive different sets of configuration data sets. The context switcher includes one or more stages for re-timing the data coming from the configuration storage elements. The stages can include interconnect circuitry or storage circuitry. Some embodiments build one of the stages in the configuration data storage elements. Some embodiments encode the configuration data bits and hence utilize a decoder in the context switcher to decode the encoded configuration data.

Подробнее

Номер записи: 22

22-08-2013 дата публикации

MEMORY BANK SIGNAL COUPLING BUFFER AND METHOD

Номер: US20130215699A1

Автор: CHOPRA Sumit, Shori Aidan

Принадлежит: MICRON TECHNOLOGY, INC.

A memory array contains a plurality of banks coupled to each other by a plurality of data lines. Each of the data lines is divided into a plurality of segments within the array. Respective bidirectional buffers couple read data from one of the segments to another in a first direction, and to couple write data from one of the segments to another in a second direction that is opposite the first direction. The data lines may be local data read/write lines that couple different banks of memory cells to each other and to respective data terminals, digit lines that couple memory cells in a respective column to respective sense amplifiers, word lines that activate memory cells in a respective row, or some other signal line within the array. The memory array also includes precharge circuits for precharging the segments of respective data lines to a precharge voltage. 1. An apparatus comprising:a plurality of data lines configured to provide respective signals within a plurality of memory cells, a data line of the plurality of data lines being divided into a plurality of data line segments; anda bidirectional buffer interposed in the data line and connecting two data line segments of the plurality of data line segments to each other, the bidirectional buffer configured to bi-directionally provide data between the two data line segment, wherein the bidirectional buffer is configured in a precharge mode to decouple the two data line segments from one another.2. The apparatus of claim 1 , wherein the bi-directional buffer comprises:a first transistor including a gate, a source, and a drain, the gate of the first transistor configured to be coupled to a first of the two data line segments;a second transistor including a gate, a source, and a drain, the gate of the second transistor configured to be coupled to a second of the two data line segments, and the source of the second transistor configured to be coupled to the source of the first transistor;a third transistor including ...

Подробнее

Номер записи: 23

19-09-2013 дата публикации

Semiconductor memory device for controlling write recovery time

Номер: US20130242679A1

Автор: Jae-Hyuk Im, Woon-Bok Lee

Принадлежит: 658868 N B Inc

A semiconductor memory device includes a CAS latency mode detecting means for outputting a CAS latency control signal in response to a CAS latency mode; and an auto-precharge control means for controlling timing of an auto-precharge operation in response to the CAS latency control signal.

Подробнее

Номер записи: 24

10-10-2013 дата публикации

Apparatus and method for implementing a multi-level memory hierarchy having different operating modes

Номер: US20130268728A1

Автор: Glenn J. Hinton, Raj K. Ramanujan, Rajat Agarwal

Принадлежит: Individual

A system and method are described for integrating a memory and storage hierarchy including a non-volatile memory tier within a computer system. In one embodiment, PCMS memory devices are used as one tier in the hierarchy, sometimes referred to as “far memory.” Higher performance memory devices such as DRAM placed in front of the far memory and are used to mask some of the performance limitations of the far memory. These higher performance memory devices are referred to as “near memory.” In one embodiment, the “near memory” is configured to operate in a plurality of different modes of operation including (but not limited to) a first mode in which the near memory operates as a memory cache for the far memory and a second mode in which the near memory is allocated a first address range of a system address space with the far memory being allocated a second address range of the system address space, wherein the first range and second range represent the entire system address space.

Подробнее

Номер записи: 25

19-12-2013 дата публикации

Integrated circuit chip and memory device

Номер: US20130339641A1

Автор: Hye-Young Lee, Kie-Bong Ku, Sejin YOO, Sung-Hwa OK

Принадлежит: SK hynix Inc

A memory device includes a pad that provides an interface with an exterior, a first setting unit that generates a termination setting signal for setting the pad for a purpose of termination data strobe using a first specific code of a mode register set operation, a second setting unit that generates a mask setting signal for setting the pad for a purpose of data mask using a second specific code of the mode register set operation, and a third setting unit that generates a write inversion setting signal for setting the pad for a purpose of write data bus inversion using third specific code of the mode register set operation. When a setting signal with a higher priority is activated, a setting signal with a lower priority is deactivated regardless of a value of the corresponding code.

Подробнее

Номер записи: 26

20-02-2014 дата публикации

Memory with Alternative Command Interfaces

Номер: US20140052934A1

Автор: Ian Shaeffer, Liji GOPALAKRISHNAN, Yi Lu

Принадлежит: RAMBUS INC

A memory device or module selects between alternative command ports. Memory systems with memory modules incorporating such memory devices support point-to-point connectivity and efficient interconnect usage for different numbers of modules. The memory devices and modules can be of programmable data widths. Devices on the same module can be configured select different command ports to facilitate memory threading. Modules can likewise be configured to select different command ports for the same purpose.

Подробнее

Номер записи: 27

06-03-2014 дата публикации

Signal transmission circuit having crosstalk cancellation unit

Номер: US20140062612A1

Автор: Chang-sik Yoo, Chun-Seok Jeong, Young-Hoon Kim

Принадлежит: Industry University Cooperation Foundation IUCF HYU, SK hynix Inc

A signal transmission circuit may include a main driving unit configured to drive a first signal transmission line with given driving force in response to a first input signal, and a crosstalk cancellation unit configured to differentiate a signal transferred through a second signal transmission line, which is adjacent to the first signal transmission line, and incorporate a differentiated value into the first signal transmission line.

Подробнее

Номер записи: 28

06-03-2014 дата публикации

Integrated circuit

Номер: US20140064013A1

Автор: Jae-Bum Ko, Sang-Jin Byeon

Принадлежит: SK hynix Inc

An integrated circuit includes a plurality of mode register set (MRS) setting blocks configured to generate a plurality of additive latency (AL) codes in response to an MRS signal, and a decoding unit configured to decoding the plurality of AL codes in response to a stack information signal to generate a plurality of AL setting signals.

Подробнее

Номер записи: 29

20-03-2014 дата публикации

SEMICONDUCTOR MEMORY DEVICE AND INFORMATION DATA PROCESSING APPARATUS INCLUDING THE SAME

Номер: US20140082306A1

Автор: KAJIGAYA Kazuhiko

Принадлежит:

A semiconductor memory device includes a plural number of data input/output pins, a plural number of banks, in each of which a plural number of the information data is stored, a selector and a control circuit. In a first access mode, the control circuit simultaneously accesses the multiple banks in response to a single read-out command or to a single write-in command from outside. In the first access mode, the selector coordinates a plurality of data input/output pins with the multiple banks in a predetermined relationship. 1. A method comprising: reading first data including M bits from a selected one of a plurality of memory banks each including a plurality of memory cells, M being an integer more than 1, and', 'transferring the M bits of the first data respectively to M pieces of data terminals in parallel to each other; and, 'performing a first operation in response to a data read request in a first access mode, the first operation comprising reading second data including M bits from the memory banks, respectively, each of the M bits being stored in a different one of the memory banks, and', 'transferring the M bits of the second data respectively to the data terminals in parallel to each other., 'performing a second operation in response to a data read request in a second access mode, the second operation comprising2. The method as claimed in claim 1 , further comprising: transferring third data including M bits respectively from the data terminals in parallel to each other, and', 'writing the third data into a selected one of the memory banks; and, 'performing a third operation in response to a data write request in the first access mode, the third operation comprising transferring fourth data including M bits respectively from the data terminals in parallel to each other, and', 'writing the M bits of the fourth data into the memory banks, respectively, each of the M bits of the fourth data being written into a different one of the memory banks., 'performing a ...

Подробнее

Номер записи: 30

02-01-2020 дата публикации

COMPOSITIONS AND METHODS FOR PREPARING OLIGONUCLEOTIDE SOLUTIONS

Номер: US20200002700A1

Автор: Chee Mark S., Stuelpnagel John R.

Принадлежит:

The present invention is directed to methods and compositions for generating a pool of oligonucleotides. The invention finds use in preparing a population or subpopulations of oligonucleotides in solution. The pool of oligonucleotides finds use in a variety of nucleic acid detection and/or amplification assays. 1. A method for detecting a plurality of target nucleic acids comprising: (i) providing a first substrate comprising the first oligonucleotides linked to a first substrate via a first cleavable linker, and a plurality of second oligonucleotides linked to the first substrate via a second cleavable linker, wherein the second oligonucleotides are different from the first oligonucleotides and,', '(ii) selectively cleaving the first oligonucleotides from the first substrate;, '(a) obtaining a solution comprising a plurality of first oligonucleotides, comprising(b) hybridizing the cleaved first oligonucleotides with the target nucleic acids;(c) contacting the hybridized target nucleic acid with a plurality of probes attached to a second substrate and adapted to capture target nucleic acids hybridized to the first or second oligonucleotides; and(d) detecting the captured target nucleic acids.2. The method of claim 1 , wherein selectively cleaving comprises contacting the first cleavable linkers with a first cleaving agent.3. The method of claim 2 , wherein the first cleaving agent is selected from the group consisting of an enzyme claim 2 , a chemical agent claim 2 , and a light source.4. The method of claim 1 , wherein the at least a first oligonucleotide comprises at least 50 different oligonucleotides.5. The method of claim 1 , wherein the first and second oligonucleotides together comprise at least 50 different oligonucleotides.6. The method of claim 1 , wherein the first and second oligonucleotides are linked to the first substrate at discrete sites.7. The method of claim 1 , wherein (a) comprises amplifying the first oligonucleotides.8. The method of claim 7 , ...

Подробнее

Номер записи: 31

02-01-2020 дата публикации

MEMORY WITH ALTERNATIVE COMMAND INTERFACES

Номер: US20200004714A1

Автор: Gopalakrishnan Liji, Lu Yi, Shaeffer Ian

Принадлежит:

A memory device or module selects between alternative command ports. Memory systems with memory modules incorporating such memory devices support point-to-point connectivity and efficient interconnect usage for different numbers of modules. The memory devices and modules can be of programmable data widths. Devices on the same module can be configured select different command ports to facilitate memory threading. Modules can likewise be configured to select different command ports for the same purpose. 1. (canceled)2. A memory device for storing and retrieving data responsive to memory commands , the memory device comprising:a memory core having sub-banks of memory banks;a first command port;a second command port; and in a first mode, to disable the first command port and to provide access to the sub-banks of memory banks responsive to the memory commands from the second command port; and', 'in a second mode, to disable the second command port and to provide access to the sub-banks of memory banks responsive to the memory commands from the first command port., 'control logic coupled to the memory core and selectively coupled to the first command port and the second command port, the control logic3. The memory device of claim 2 , the memory core further comprising a first data queue and a second data queue coupled to the sub-banks of memory banks.4. The memory device of claim 3 , wherein the control logic activates only one of the first data queue and the second data queue in the first mode and both of the first data queue and the second data queue in the second mode.5. The memory device of claim 2 , further comprising a mode register to store a value that sets one of the first mode and the second mode.6. The memory device of claim 2 , the control logic to access each and every one of the sub-banks of memory banks responsive to the commands received on either of the first command port and the second command port.7. The memory device of claim 2 , wherein the memory ...

Подробнее

Номер записи: 32

07-01-2021 дата публикации

SEMICONDUCTOR MEMORY APPARATUS AND METHOD FOR READING THE SAME

Номер: US20210005276A1

Автор: NAKAOKA Yuji

Принадлежит: WINBOND ELECTRONICS CORP.

A semiconductor memory apparatus including a data memory array, a parity memory array, a data read/write and correction part, a parity read/write part and a syndrome generating and decoding part is provided. The data read/write and correction part reads the data memory array and outputs a first application reading data. The parity read/write part reads the parity memory array and outputs a parity reading data. During a read cycle of an application data, the syndrome generating and decoding part generates a syndrome writing data according to the first application reading data, compares and decodes the syndrome writing data with the parity reading data to generate a verifying comparison data. In the same read cycle, the data read/write and correction part corrects the application data according to the verifying comparison data, and writes the corrected application data back to the data memory array and outputs a corresponding output data. 1. A semiconductor memory apparatus , comprising:a data memory array for storing an application data;a parity memory array for storing a parity data corresponding to the application data;a data read/write and correction part coupled to the data memory array for reading the application data of the data memory array, and outputting a corresponding first application reading data;a parity read/write part coupled to the parity memory array for reading the parity data of the parity memory array, and outputting a corresponding parity reading data; anda syndrome generating and decoding part coupled to the data read/write and correction part and the parity read/write part, wherein in a read cycle of the application data, the syndrome generating and decoding part generates a syndrome writing data according to the first application reading data, and compares and decodes the syndrome writing data and the parity reading data to generate a verifying comparison data,wherein in the same read cycle, the data read/write and correction part corrects ...

Подробнее

Номер записи: 33

04-01-2018 дата публикации

MEMORY APPARATUS AND OPERATING METHOD THEREOF

Номер: US20180005672A1

Автор: CHANG Chih-Hsiang

Принадлежит: WINBOND ELECTRONICS CORP.

A memory apparatus including a memory cell array, a register unit and a command generator is provided. The memory cell array includes a plurality of memory cells. The register unit is configured to record a plurality of user-defined information. The command generator receives a user-defined command and operates at least two memory operations on the memory cell array according to the received user-defined command and the user-defined information. The user-defined information is generated according to the at least two memory operations. Furthermore, an operating method of a memory apparatus is also provided. 1. A memory apparatus , comprising:a memory cell array, comprising a plurality of memory cells;a register unit, configured to record a plurality of user-defined information; anda command generator, coupled to the register unit and the memory cell array,wherein the command generator receives a user-defined command, and executes at least two memory operations on the memory cell array according to the received user-defined command and the user-defined information, wherein the user-defined information is generated according to the at least two memory operations.2. The memory apparatus as claimed in claim 1 , further comprising:a detection unit, configured to receive a write signal, and detecting whether the write signal corresponds to at least one of the user-defined information,wherein when the write signal corresponds to at least one of the user-defined information, the corresponding at least one user-defined information is recorded in the register unit according to the write signal.3. The memory apparatus as claimed in claim 1 , further comprising:a signal decoder, configured to receive and decode an external signal, wherein a single memory operation corresponding to the external signal is executed on the memory cell array according to a decoding result of the signal decoder.4. The memory apparatus as claimed in claim 1 , wherein the register unit is a mode ...

Подробнее

Номер записи: 34

02-01-2020 дата публикации

MEMORY CIRCUIT AND METHOD OF OPERATING SAME

Номер: US20200005841A1

Автор: LEE Cheng Hung, LU Shih-Lien Linus, TSAI Jui-Che

Принадлежит:

A memory circuit includes a first memory cell, a second memory cell, a pre-charge circuit and a sense amplifier. The pre-charge circuit is coupled to a first bit line and a second bit line. The pre-charge circuit is configured to charge the first bit line and the second bit line to a pre-charge voltage level responsive to a first signal. The sense amplifier is coupled to the first memory cell by the first bit line, and coupled to the second memory cell by the second bit line. The sense amplifier is responsive to a second signal and a third signal. The second signal and the third signal being different from the first signal. 1. A memory circuit comprising:a first memory cell coupled to a first bit line;a second memory cell coupled to a second bit line;a pre-charge circuit coupled to the first bit line and the second bit line, the pre-charge circuit configured to charge the first bit line and the second bit line to a pre-charge voltage level responsive to a first signal; anda sense amplifier coupled to the first memory cell by the first bit line, and coupled to the second memory cell by the second bit line, the sense amplifier being responsive to a second signal and a third signal, the second signal and the third signal being different from the first signal, the sense amplifier comprising:a header switch coupled to a first supply voltage, and configured to provide the first supply voltage to the sense amplifier responsive to the second signal.2. The memory circuit of claim 1 , further comprising:a latch coupled to the sense amplifier by the first bit line, and being configured to output a random set of data based on data stored in the first memory cell and the second memory cell.3. The memory circuit of claim 1 , wherein the pre-charge circuit comprises: a first terminal of the first transistor being configured to receive the first signal;', 'a second terminal of the first transistor being coupled to the first bit line; and', 'a third terminal of the first transistor ...

Подробнее

Номер записи: 35

03-01-2019 дата публикации

Methods for generating reference voltages and controllers utilizing the same

Номер: US20190005989A1

Автор: Fan Jiang, Jiajia XIA, Minglu XU

Принадлежит: Shanghai Zhaoxin Semiconductor Co Ltd

A controller includes an input/output circuit and a reference voltage generating circuit. The input/output circuit includes a plurality of receiving circuits. Each receiving circuit receives and processes one data bit and generates an output bit accordingly. The reference voltage generating circuit is coupled to the input/output circuit and includes a plurality of circuit units for providing a plurality of reference voltages. One of the circuit units is coupled to one of the receiving circuits to provide a reference voltage to the corresponding receiving circuit and the receiving circuit processes the data bit according to the received reference voltage.

Подробнее

Номер записи: 36

03-01-2019 дата публикации

SEMICONDUCTOR STORAGE DEVICE

Номер: US20190005998A1

Автор: MATSUOKA Fumiyoshi

Принадлежит: Toshiba Memory Corporation

A semiconductor storage device includes a first bank that includes a first memory cell group and writes data into the first memory cell group upon receipt of a first command, a second bank that includes a second memory cell group and writes data into the second memory cell group upon receipt of the first command, and a delay controller that issues the first command for the first bank upon receipt of a second command, and issues the first command for the second bank after an interval of at least a first period. 1a first bank that includes a first memory cell group and writes data into the first memory cell group upon receipt of a first command;a second bank that includes a second memory cell group and writes data into the second memory cell group upon receipt of the first command; anda delay controller that issues the first command for the first bank upon receipt of a second command, and issues the first command for the second bank after an interval of at least a first period.. A semiconductor storage device comprising: This application is a Continuation application of U.S. application Ser. No. 15/264,545, filed Sep. 13, 2016, which claims the benefit of U.S. Provisional Application No. 62/309,837, filed Mar. 17, 2016. The entire contents of both the above-identified applications are incorporated herein by reference.Embodiments described herein relate generally to a semiconductor storage device.A magnetic random access memory (MRAM) is a memory device employing a magnetic element having a magnetoresistive effect as a memory cell for storing information, and is receiving attention as a next-generation memory device characterized by its high-speed operation, large storage capacity, and non-volatility. Research and development have been advanced to use the MRAM as a replacement for a volatile memory, such as a dynamic random access memory (DRAM) or a static random access memory (SRAM). In order to lower the development cost and enable smooth replacement, it is desirable ...

Подробнее

Номер записи: 37

20-01-2022 дата публикации

Page buffer circuit and memory device including the same

Номер: US20220020404A1

Автор: Inho Kang, Jeunghwan Park, Jinwoo Park, Taehyo Kim, Yongsung CHO

Принадлежит: SAMSUNG ELECTRONICS CO LTD

Provided are a page buffer and a memory device including the same. A memory device includes: a memory cell array including a plurality of memory cells; and a page buffer circuit including page buffer units in a first horizontal direction, the page buffer units being connected to the memory cells via bit lines, and cache latches in the first horizontal direction, the cache latches corresponding to the page buffer units, wherein each of the page buffer units includes one or more pass transistors connected to a sensing node of each of the plurality of page buffer units, the sensing node electrically connected to a corresponding bit line. Each sensing node included in each of the page buffer units and the combined sensing node are electrically connected to each other through the pass transistors.

Подробнее

Номер записи: 38

11-01-2018 дата публикации

COMPOSITIONS AND METHODS FOR PREPARING OLIGONUCLEOTIDE SOLUTIONS

Номер: US20180010123A1

Автор: Chee Mark S., Stuelpnagel John R.

Принадлежит:

The present invention is directed to methods and compositions for generating a pool of oligonucleotides. The invention finds use in preparing a population or subpopulations of oligonucleotides in solution. The pool of oligonucleotides finds use in a variety of nucleic acid detection and/or amplification assays. 1. (canceled)2. A system for detecting a plurality of target nucleic acids comprising:(a) a solution comprising at least a first oligonucleotide capable of hybridizing to a target nucleic acid;(b) at least a second oligonucleotide linked to the first substrate via a second cleavable linker, wherein the second oligonucleotide is different from the first oligonucleotide and capable of hybridizing to a target nucleic acid;(c) a plurality of probes attached to a second substrate and adapted to capture target nucleic acids hybridized to the first or second oligonucleotide; and(d) a detector adapted to detect captured target nucleic acids.3. The system of claim 2 , wherein the first oligonucleotide is obtained by:(i) providing a first substrate and the first oligonucleotide linked to the first substrate via a first cleavable linker; and(ii) cleaving the first cleavable linker.4. The system of comprising a cleaving agent capable of cleaving the first or second cleavable linker.5. The system of claim 4 , wherein the cleaving agent is selected from the group consisting of an enzyme claim 4 , a chemical agent claim 4 , and a light source.6. The system of claim 2 , wherein the at least a first oligonucleotide comprises at least 50 different oligonucleotides.7. The system of claim 2 , wherein the first and second oligonucleotides together comprise at least 50 different oligonucleotides.8. The system of claim 2 , wherein (i) comprises providing the first and second oligonucleotides linked to the first substrate.9. The system of claim 8 , wherein the first and second oligonucleotides are linked to the first substrate at discrete sites.10. The system of claim 2 , wherein ...

Подробнее

Номер записи: 39

14-01-2016 дата публикации

FLASH MEMORY CONTROLLER WITH CALIBRATED DATA COMMUNICATION

Номер: US20160011973A1

Автор: Donnelly Kevin S., Garlepp Bruno W., Ho Tsyr-Chyang, Horowitz Mark A., Kim Jun, Lau Benedict Chung-Kwong, Sidiropoulos Stefanos, Stark Donald C., Vu Roxanne, Yu Leung, Zerbe Jared LeVan

Принадлежит:

An integrated circuit device includes a transmitter circuit operable to transmit a timing signal over a first wire to a DRAM. The DRAM receives a first signal having a balanced number of logical zero-to-one transitions and one-to-zero transitions and samples the first signal at a rising edge of the timing signal to produce a respective sampled value. The device further includes a receiver circuit to receive the respective sampled value from the DRAM over a plurality of wires separate from the first wire. In a first mode, the transmitter circuit repeatedly transmits incrementally offset versions of the timing signal to the DRAM until sampled values received from the DRAM change from a logical zero to a logical one or vice versa; and in a second mode, it transmits write data over the plurality of wires to the DRAM according to a write timing offset generated based on the sampled values. 1. A flash memory controller , comprising:a bus interface to couple to a plurality of flash memory devices, the bus interface including a circuit to send at least one signal to individually address a selected flash memory device of the plurality of flash memory devices and store a device-specific value in a reference voltage register of the selected flash memory device; anda transmitter to output a data signal to the selected flash memory devicewherein the device-specific value stored in the reference voltage register of the selected flash memory device controls a reference voltage used by a corresponding receiver circuit of the selected flash memory device, the receiver circuit to receive the data signal transmitted by the flash memory controller to the selected flash memory device.2. The flash memory controller of claim 1 , wherein the device-specific value stored in the reference voltage register of the selected flash memory device is determined during a calibration mode of operation of the selected flash memory device.3. The flash memory controller of claim 1 , wherein each of the ...

Подробнее

Номер записи: 40

14-01-2021 дата публикации

Systems and methods for performing a write pattern in memory devices

Номер: US20210011803A1

Автор: Gary L. Howe

Принадлежит: Micron Technology Inc

A semiconductor device may include a memory bank and a plurality of mode registers that communicatively couple to each of the plurality of memory banks. The plurality of mode registers may include a pattern of data stored therein. The semiconductor device may also include a bank control that receives a write pattern command that causes the bank control to write the pattern of data into the memory bank, send a signal to a multiplexer to couple the plurality of mode registers to the memory bank, and write the pattern of data to the memory bank via the plurality of mode registers.

Подробнее

Номер записи: 41

14-01-2021 дата публикации

MEMORY WITH ALTERNATIVE COMMAND INTERFACES

Номер: US20210011876A1

Автор: Gopalakrishnan Liji, Lu Yi, Shaeffer Ian

Принадлежит:

A memory device or module selects between alternative command ports. Memory systems with memory modules incorporating such memory devices support point-to-point connectivity and efficient interconnect usage for different numbers of modules. The memory devices and modules can be of programmable data widths. Devices on the same module can be configured select different command ports to facilitate memory threading. Modules can likewise be configured to select different command ports for the same purpose. 1. (canceled)2. A memory controller to control memory devices disposed on a memory module , the memory devices each having a selectable first command port and a selectable second command port , the memory controller comprising:a first data port to communicate first data;a second data port to communicate second data; the memory devices to communicate with one of the first data port and the second data port in a narrow-data mode and with both of the first data port and the second data port in a wide-data mode;', 'a first subset of the memory devices to receive first commands via first command ports at each respective memory device in the first subset of the memory devices; and', 'a second subset of the memory devices to receive second commands via second command ports at each respective memory device in the second subset of the memory devices; and, 'circuitry to configurea first command interface to connect to the first command port of each memory device of the first subset of the memory devices; anda second command interface to connect to the second command port of each memory device of the second subset of the memory devices.3. The memory controller of claim 2 , the circuitry to configure the first subset of the memory devices to receive the first commands via the first command ports at each respective memory device in the first subset of the memory devices and the second subset of the memory devices to receive the second commands via the second command ports at each ...

Подробнее

Номер записи: 42

09-01-2020 дата публикации

ERROR CODE CALCULATION ON SENSING CIRCUITRY

Номер: US20200012562A1

Автор: Finkbeiner Timothy P., Lea Perry V.

Принадлежит:

Examples of the present disclosure provide apparatuses and methods for error code calculation. The apparatus can include an array of memory cells that are coupled to sense lines. The apparatus can include a controller configured to control a sensing circuitry, that is coupled to the sense lines, to perform a number of operations without transferring data via an input/output (I/O) lines. The sensing circuitry can be controlled to calculate an error code for data stored in the array of memory cells and compare the error code with an initial error code for the data to determine whether the data has been modified. 1. An apparatus comprising:an array of memory cells that are coupled to a plurality of sense lines;a plurality of sense amplifiers coupled to the plurality of sense lines; and control a compute component, that is coupled to at least one of the plurality of sense amplifiers, to perform a number of operations to:', 'calculate an error code for data stored in the array of memory cells; and', 'compare the error code with an initial error code for the data to determine whether the data has been modified., 'a controller configured to2. The apparatus of claim 1 , wherein the controller being configured to control the compute component to calculate the error code and compare the error code comprises the controller being configured to control the compute component to perform AND operations claim 1 , OR operations claim 1 , SHIFT operations claim 1 , and INVERT operations.3. The apparatus of claim 1 , wherein a respective one of the plurality of sense amplifiers is coupled to a respective one of the plurality of sense lines.4. The apparatus of claim 1 , wherein the controller is further configured to calculate the initial error code at a first time and the error code a second time.5. The apparatus of claim 1 , wherein the data comprises at least one of user data and executable instructions.6. The apparatus of claim 5 , wherein the executable instructions comprise an ...

Подробнее

Номер записи: 43

10-01-2019 дата публикации

NONVOLATILE SRAM

Номер: US20190013063A1

Автор: Karnik Tanay, LIU Huichu, Manipatruni Sasikanth, Morris Daniel H., Mukherjee Niloy, Nikonov Dmitri E., VAIDYANATHAN Kaushik, Young Ian

Принадлежит: Intel Corporation

One embodiment provides an apparatus. The apparatus includes a pair of nonvolatile resistive random access memory (RRAM) memory cells coupled to a volatile static RAM (SRAM) memory cell. The pair of nonvolatile RRAM memory cells includes a first RRAM memory cell and a second RRAM memory cell. The first RRAM memory cell includes a first resistive memory element coupled to a first bit line, and a first selector transistor coupled between the first resistive memory element and a first output node of the volatile SRAM memory cell. The second RRAM memory cell includes a second resistive memory element coupled to a second bit line, and a second selector transistor coupled between the second resistive memory element and a second output node of the volatile SRAM memory cell. 1. An apparatus comprising:a pair of nonvolatile resistive random access memory (RRAM) memory cells coupled to a volatile static RAM (SRAM) memory cell, the pair of nonvolatile RRAM memory cells comprising a first RRAM memory cell and a second RRAM memory cell, a first resistive memory element coupled to a first bit line, and', 'a first selector transistor coupled between the first resistive memory element and a first output node of the volatile SRAM memory cell, and the second RRAM memory cell comprising:', 'a second resistive memory element coupled to a second bit line, and', 'a second selector transistor coupled between the second resistive memory element and a second output node of the volatile SRAM memory cell., 'the first RRAM memory cell comprising2. The apparatus of claim 1 , wherein the first resistive memory element comprises a first positive electrode and a first negative electrode and the second resistive memory element comprises a second positive electrode and a second negative electrode.3. The apparatus of claim 2 , wherein the first positive electrode is coupled to the first bit line and the second positive electrode is coupled to the second bit line.4. The apparatus of claim 2 , wherein ...

Подробнее

Номер записи: 44

09-01-2020 дата публикации

Semiconductor memory device

Номер: US20200013435A1

Автор: Jumpei Sato

Принадлежит: Toshiba Memory Corp

A semiconductor memory device includes n interconnect layers above a substrate; and a first interconnect region between an end of a control circuit and an end of the substrate in a direction of a first axis beside a first pad region in a direction of a second axis. The n interconnect layers are located at different levels from the substrate. Each of the n interconnect layers includes an interconnect. The first interconnect region includes no transistor, and no contact coupled to the substrate. The first interconnect region includes an interconnect extending along the second axis in m (m is a natural number equal to or larger than 3, larger than n/2, and equal to or smaller than n) interconnect layers of the n interconnect layers.

Подробнее

Номер записи: 45

09-01-2020 дата публикации

MEMORY DEVICE AND OPERATION METHOD THEREOF

Номер: US20200013451A1

Автор: SON JONGPIL

Принадлежит: SAMSUNG ELECTRONICS CO., LTD.

An operation method of a memory device which includes a plurality of memory cells connected to a plurality of word lines includes receiving a first activate command from an external device, receiving at least one operation command from the external device after the first activate command is received, receiving a precharge command after receiving the at least one operation command, and receiving a second activate command from the external device after the precharge command is received. When the at least one operation command does not include a write command, the second activate command is received after a first precharge reference time elapses from a time at which the precharge command is received. When the at least one operation command includes the write command, the second activate command is received after a second precharge reference time elapses from the time at which the precharge command is received. 1. An operation method of a memory device , the memory device including a plurality of dynamic random access memory (DRAM) cells connected to a plurality of word lines , the method comprising:receiving a first activate command from an external source;receiving at least one operation command from the external source;receiving a precharge command;determining whether the at least one operation command includes a write command; and receiving a second activate command from the external source after a first precharge reference time period elapses, the first precharge reference time period starting at a time when the precharge command is received, or', 'receiving the second activate command from the external source after a second precharge reference time period elapses, the second precharge reference time period starting at the time when the precharge command is received., 'based on results of the determining,'}2. The method of claim 1 , wherein the second precharge reference time period is longer than the first precharge reference time period.3. The method of claim 1 , ...

Подробнее

Номер записи: 46

09-01-2020 дата публикации

NON-VOLATILE MEMORY WITH POOL CAPACITOR

Номер: US20200013795A1

Автор: Dak Piyush, Dunga Mohan, Higashitani Masaaki, Kai James, Lin Luisa, Ramachandra Venkatesh P.

Принадлежит: SanDisk Technologies LLC

A non-volatile storage apparatus comprises a non-volatile memory structure and an I/O interface. A portion of the memory die is used as a pool capacitor for the I/O interface. 1. A non-volatile storage apparatus , comprising:a non-volatile memory structure;a peripheral circuit connected to the memory structure; andan I/O interface connected to the peripheral circuit, a section of the memory structure is configured to operate as a capacitor and is connected to the I/O interface.2. The non-volatile storage apparatus of claim 1 , wherein:the non-volatile memory structure is a three dimensional non-volatile memory array divided into blocks; andthe section of the memory array is a block at an edge of the memory array that is configured to operate as a capacitor and is connected to the I/O interface.3. The non-volatile storage apparatus of claim 1 , wherein:the I/O interface is a power I/O pad.4. The non-volatile storage apparatus of claim 1 , wherein:the non-volatile memory array is a three dimensional memory structure comprising alternating conductive layers and dielectric layers with vertical columns of materials extending through the conductive layers and dielectric layers;the I/O interface includes a power I/O pad and a ground I/O pad;the section of the memory structure includes multiple vertical columns, has a first set of the conductive layers connected to the power I/O pad and a second set of the conductive layers connected to ground I/O pad such that the section of the memory structure functions as a capacitor connected to the power I/O pad.5. The non-volatile storage apparatus of claim 4 , further comprising:a first switch connected to the power I/O pad, the first set of the conductive layers are connected to the first switch; anda second switch connected to the ground I/O pad, the second set of the conductive layers are connected to the second switch.6. The non-volatile storage apparatus of claim 4 , further comprising:a first switch connected to the power I/O ...

Подробнее

Номер записи: 47

09-01-2020 дата публикации

HIGH SPEED INTERLEAVER/DEINTERLEAVER DEVICE SUPPORTING LINE RATE, AND METHOD THEREOF

Номер: US20200014490A1

Автор: Bhat Sri, LIU Yanlai, Subramaniam Bala

Принадлежит: HUGHES NETWORK SYSTEMS, LLC

A deinterleaver device, a method for deinterleaving, an interleaver device, and a method for interleaving are disclosed. The method for deinterleaving includes: providing a memory and a stream count for a frame; virtually dividing the memory into equal sections, wherein a section count equals the stream count; calculating a write address for a sample of the samples based on a location of the sample in the frame and a correspondence of the location to one of the sections; receiving the sample; and writing the received sample to the write address, wherein the calculating and the write address corresponds to a correct deinterleaving location in one of the sections for the sample. 121-. (canceled)22. A method for interleaving soft decisions for a frame , the method comprising:providing a memory and a stream count selected from n-different supported stream counts;virtually dividing the memory into x-rows, y-columns and the y-columns into equal sections, wherein y is calculated as a common denominator of a majority of the n-different counts, x is at least a length of samples divided by y, and the y-columns are subdivided into equal sections wherein a section count equals the stream count;collecting soft decisions sequentially, wherein the soft decisions number less than or equal to a frame size of the frame;calculating, for each respective soft decision, a write address comprising a row of the x-rows and a column of the y-columns based on a location of the respective soft decision, wherein a next column of the y-columns is set as the column every x soft decisions; andwriting the respective soft decision to a respective write address of the memory.23. The method of claim 22 , wherein a frame length of the soft-decisions in the frame is variable.24. The method of claim 22 , wherein the frame comprises 64 claim 22 ,800 soft-decisions claim 22 , each soft decision of the soft decisions is 6-bits claim 22 , the frame is modulated using a modulation type having 1 claim 22 , 2 ...

Подробнее

Номер записи: 48

03-02-2022 дата публикации

METHOD OF PERFORMING INTERNAL PROCESSING OPERATIONS WITH PRE-DEFINED PROTOCOL INTERFACE OF MEMORY DEVICE

Номер: US20220036929A1

Автор: KIM NAMSUNG, LEE SUKHAN, O SEONGIL, SOHN KYOMIN, YU Hak-soo

Принадлежит:

A memory device includes a memory cell array, signal lines, a mode selector circuit, a command converter circuit, and an internal processor. The memory cell array includes first and second memory regions. The mode selector circuit is configured to generate a processing mode selection signal for controlling the memory device to enter an internal processing mode based on the address received together with the command. The command converter circuit is configured to convert the received command into an internal processing operation command in response to activation of the internal processing mode selection signal. The internal processor is configured to perform an internal processing operation on the first memory region in response to the internal processing operation command, in the internal processing mode. 1. A memory device comprising:a memory cell array including a first memory region and a second memory region;a processing-in-memory (PIM) engine configured to perform an internal processing operation on the first memory region;a mode selector circuit configured to activate a processing mode selection signal for controlling the memory device to enter the internal processing operation based on a PIM mode entering code, the PIM mode entering code being stored in the mode selector circuit and corresponding to a first back-to-back address sequence along with sequential write commands; anda command converter circuit configured to convert a received command into a PIM command in response to the activation of the processing mode selection signal.2. The memory device of claim 1 , wherein the mode selector circuit is further configured to receive first addresses sequentially claim 1 , compare the PIM mode entering code with the first addresses claim 1 , and activate the processing mode selection signal when the sequential first addresses coincide with the PIM mode entering code.3. The memory device of claim 1 , wherein the command converter circuit is further configured ...

Подробнее

Номер записи: 49

03-02-2022 дата публикации

Electronic device configured to perform an auto-precharge operation

Номер: US20220036930A1

Автор: Woongrae Kim

Принадлежит: SK hynix Inc

An electronic device may include: an input/output control signal generation circuit configured to generate an input control signal and a first output control signal during a write operation, and generate a second output control signal during a write operation with an auto-precharge operation; and a bank address output circuit configured to latch a bank address based on the input control signal, and output the latched bank address as a write bank address for the write operation or a precharge bank address for the auto-precharge operation, based on the first output control signal and the second output control signal.

Подробнее

Номер записи: 50

17-01-2019 дата публикации

ACTIVATION OF MEMORY CORE CIRCUITS IN AN INTEGRATED CIRCUIT

Номер: US20190019547A1

Автор: Kalla Thomas, Noack Jens, Pille Juergen, Salz Philipp

Принадлежит:

In an approach to activating at least one memory core circuit of a plurality of memory core circuits in an integrated circuit, one or more computer processors activate a clock signal of a currently selected memory core circuit. The one or more computer processors activate the clock signal of a previously selected memory core circuit to allow the previously selected memory core circuit to be set to a deselected operating mode. The one or more computer processors forward an output bit generated by a memory core circuit selected from a plurality of memory core circuits to a multiplexed bit line. 1. An apparatus for an integrated circuit associated with memory core circuits , the apparatus comprising:an integrated circuit coupled to a plurality of memory core circuits wherein at least one of the plurality of memory core circuits are coupled to one or more outputs lines for outputting at least one output bit;the at least one output bit coupled to the plurality of memory core circuits, wherein the at least one output bit is held in an inactive level; anda logic circuitry configured to forward the at least one output bit generated by one or more of the plurality of memory core circuits to a multiplexed bit line, wherein the logic circuitry comprises a clock gating circuit configured to activate a first clock gate signal associated with a currently selected memory core circuit and configured to activate a second clock signal associated with a previously selected memory core circuit to set the previously selected memory core circuit to a deselected operating mode.2. The apparatus of claim 1 , wherein:the logic circuitry is coupled to a storage element configured to store information regarding whether or not a specific memory core circuit was previously selected; andthe clock gating circuit is adapted to keep the first clock gate signal associated with the currently selected memory core circuit activated if stored data in the storage element indicated that the currently ...

Подробнее

Номер записи: 51

17-01-2019 дата публикации

ACTIVATION OF MEMORY CORE CIRCUITS IN AN INTEGRATED CIRCUIT

Номер: US20190019548A1

Автор: Kalla Thomas, Noack Jens, Pille Juergen, Salz Philipp

Принадлежит:

In an approach to activating at least one memory core circuit of a plurality of memory core circuits in an integrated circuit, one or more computer processors activate a clock signal of a currently selected memory core circuit. The one or more computer processors activate the clock signal of a previously selected memory core circuit to allow the previously selected memory core circuit to be set to a deselected operating mode. The one or more computer processors forward an output bit generated by a memory core circuit selected from a plurality of memory core circuits to a multiplexed bit line. 1. A method for activating at least one memory core circuit of a plurality of memory core circuits in an integrated circuit , the method comprising:activating, by one or more computer processors, a clock signal of a currently selected memory core circuit;activating, by the one or more computer processors, the clock signal of a previously selected memory core circuit to allow the previously selected memory core circuit to be set to a deselected operating mode; andforwarding, by the one or more computer processors, an output bit generated by a memory core circuit selected from a plurality of memory core circuits to a multiplexed bit line.2. The method of claim 1 , further comprising:storing, by the one or more computer processors, information regarding whether a specific memory core circuit was previously selected in a storage element; andmaintaining, by the one or more computer processors, an activated state of the clock signal of the specific memory core circuit based on the information stored in the storage element indicating that the specific memory core was previously activated.3. A computer program product for activating at least one memory core circuit of a plurality of memory core circuits in an integrated circuit claim 1 , the computer program product comprising:one or more computer readable storage media and program instructions stored on the one or more computer ...

Подробнее

Номер записи: 52

17-01-2019 дата публикации

ACTIVATION OF MEMORY CORE CIRCUITS IN AN INTEGRATED CIRCUIT

Номер: US20190019549A1

Автор: Kalla Thomas, Noack Jens, Pille Juergen, Salz Philipp

Принадлежит:

In an approach to activating at least one memory core circuit of a plurality of memory core circuits in an integrated circuit, one or more computer processors activate a clock signal of a currently selected memory core circuit. The one or more computer processors activate the clock signal of a previously selected memory core circuit to allow the previously selected memory core circuit to be set to a deselected operating mode. The one or more computer processors forward an output bit generated by a memory core circuit selected from a plurality of memory core circuits to a multiplexed bit line. 1 'precharge the one or more outputs during an execution of a built-in self-test, reset the one or more outputs during an execution of a built-in self-test;', 'an integrated circuit coupled to a plurality of memory core circuits wherein at least one of the plurality of memory core circuits are coupled to one or more outputs for outputting at least one output bit, wherein the plurality of memory core circuits is configured tothe at least one output bit coupled to the plurality of memory core circuits, wherein the at least one output bit is held in an inactive level, wherein the inactive level corresponds to either a logical zero or a logical one; anda logic circuitry coupled to a storage element configured to store information regarding whether or not a specific memory core circuit was previously selected, wherein the storage element is implemented as a latch, and wherein the logic circuitry is:configured as a state machine to forward the at least one output bit generated by one or more of the plurality of memory core circuits to a multiplexed bit line, precharge the one or more outputs upon a power-on phase, to reset the one or more outputs upon a power-on phase, to precharge the one or more outputs upon an exception state removal, reset the one or more outputs upon an exception state removal, precharge the one or more outputs upon an initialization of the at least one of a ...

Подробнее

Номер записи: 53

22-01-2015 дата публикации

Memory device and read operation method thereof

Номер: US20150023120A1

Автор: Chia-Jung Chen, Chin-Hung Chang, Ken-Hui Chen, Kuen-Long Chang, Su-Chueh Lo

Принадлежит: Macronix International Co Ltd

A read operation for a memory device is provided. A selected word line, first and second global bit line groups and a selected first bit line group are precharged. A first cell current flowing through the selected word line, the first and the selected first bit line groups is generated. A first reference current flowing through the second global bit line group is generated. A first half page data is read based on the first cell current and the first reference current. The selected word line, the first and the second global bit line groups are kept precharged.

Подробнее

Номер записи: 54

16-01-2020 дата публикации

MULTIPLE CONCURRENT MODULATION SCHEMES IN A MEMORY SYSTEM

Номер: US20200020367A1

Автор: Gans Dean D., Hasbun Robert Nasry, Hollis Timothy M., Wright Jeffrey P.

Принадлежит:

Methods, systems, and devices for multiple concurrent modulation schemes in a memory system are described. Techniques are provided herein to communicate data using a modulation scheme having at least three levels and using a modulation scheme having at least two levels within a common system or memory device. Such communication with multiple modulation schemes may be concurrent. The modulated data may be communicated to a memory die through distinct signal paths that may correspond to a particular modulation scheme. An example of a modulation scheme having at least three levels may be pulse amplitude modulation (PAM) and an example of a modulation scheme having at least two levels may be non-return-to-zero (NRZ). 1. (canceled)2. An apparatus , comprising:a controller configured to communicate a first data and a second data, the first data modulated using a different modulation scheme than the second data;a first signal path coupled with the controller and a memory die, the first signal path configured to communicate the first data; anda second signal path coupled with the controller and the memory die, the second signal path configured to communicate the second data.3. The apparatus of claim 2 , further comprising:a third signal path coupled with the controller and a second memory die; anda fourth signal path coupled with the controller and the second memory die, wherein the third signal path is configured to communicate the first data and the fourth signal path is configured to communicate the second data.4. The apparatus of claim 2 , further comprising:a bus coupled with the controller and the memory die, the bus configured to communicate the first data and the second data based on a timing of a system clock of the controller.5. The apparatus of claim 2 , further comprising:a first encoder coupled with the controller and configured to modulate the first data; anda second encoder coupled with the controller and configured to modulate the second data.6. The ...

Подробнее

Номер записи: 55

16-01-2020 дата публикации

Semiconductor storage device

Номер: US20200020379A1

Автор: Fumiyoshi Matsuoka

Принадлежит: Toshiba Memory Corp

A semiconductor storage device includes a first bank that includes a first memory cell group and writes data into the first memory cell group upon receipt of a first command, a second bank that includes a second memory cell group and writes data into the second memory cell group upon receipt of the first command, and a delay controller that issues the first command for the first bank upon receipt of a second command, and issues the first command for the second bank after an interval of at least a first period.

Подробнее

Номер записи: 56

16-01-2020 дата публикации

SEMICONDUCTOR MEMORY DEVICE HAVING CLOCK GENERATION SCHEME BASED ON COMMAND

Номер: US20200020380A1

Автор: DOO SU YEON, Oh Taeyoung, SHIN SEUNGJUN

Принадлежит:

A semiconductor memory device includes a command decoder configured to generate an auto-sync signal in response to a command for writing data at a memory cell or reading data from a memory cell, and an internal data clock generating circuit configured to phase synchronize a second clock, having a clock frequency higher than a clock frequency of a first clock, with the first clock in response to the auto-sync signal. 112-. (canceled)13. A memory device comprising:a command decoder configured to decode a column address strobe (CAS) command synchronized with a first clock;an internal data clock generating circuit configured to perform a synchronization between the first clock and a second clock in response to the CAS command; anda pattern generator configured to generate an error data code (EDC) hold pattern in response to the CAS command.14. The memory device of claim 13 , further comprising:an input/output control circuit configured to control data input/output based on the second clock synchronized with the first clock.15. The memory device of claim 14 , wherein the internal data clock generating circuit performs the synchronization between the first clock and the second clock during a latency of the data input/output.16. The memory device of claim 14 , wherein the internal data clock generating circuit includes:a data clock divider configured to divide the second clock into multi-phase clocks; anda phase switch configured to perform swapping of the multi-phase clocks.17. The memory device of claim 13 , wherein the second clock is toggled after the CAS command is received by the command decoder.18. The memory device of claim 14 , wherein the pattern generator is further configured to output the EDC hold pattern before read data are output by the input/output control circuit.19. The memory device of claim 18 , wherein the pattern generator is further configured to end outputting the EDC hold pattern claim 18 , when outputting the read data is completed by the input/ ...

Подробнее

Номер записи: 57

21-01-2021 дата публикации

BANK TO BANK DATA TRANSFER

Номер: US20210020207A1

Автор: Lea Perry V., Manning Troy A.

Принадлежит:

The present disclosure includes apparatuses and methods for bank to bank data transfer. An example apparatus includes a plurality of banks of memory cells, an internal bus configured to transfer data between the plurality of banks and an external bus interface, and a bank-to-bank transfer bus configured to transfer data between the plurality of banks. 1. An apparatus , comprising:a plurality of shared input/output (SIO) lines coupled to logic comprising a plurality of latches;a plurality of memory banks coupled to respective SIO lines among the plurality of SIO lines;a bank-to-bank transfer bus coupled to each SIO line among the plurality of SIO lines; anda controller coupled to the bank-to-bank transfer bus and the plurality of SIO lines and configured to cause data to be transferred to at least one memory bank among the plurality of memory banks via the bank-to-bank transfer bus in a first direction or a second direction based, at least in part, on a transfer time associated with transferring the data to the at least one memory bank.2. The apparatus of claim 1 , further comprising a plurality of control components coupled to respective SIO lines among the plurality of SIO lines claim 1 , wherein the control components are configured to compare a write address value or a read address value claim 1 , or both claim 1 , for designating addresses among the plurality of memory banks prior to the data being transferred between the memory banks.3. The apparatus of claim 1 , wherein the controller is configured to:determine that a processing in memory program is running on a particular memory bank among the plurality of memory banks; andcause the bank-to-bank transfer bus to be bifurcated such that the particular memory bank receives data transferred from other memory banks among the plurality of memory banks directly or in an optimized manner, or both.4. The apparatus of claim 1 , wherein the controller is configured to cause data to be transferred from the plurality of ...

Подробнее

Номер записи: 58

21-01-2021 дата публикации

APPARATUS AND METHOD FOR IMPROVING INPUT/OUTPUT THROUGHPUT OF MEMORY SYSTEM

Номер: US20210020208A1

Автор: PARK Jeen

Принадлежит:

A memory system includes: a plurality of memory dies, and a controller selects a second read request, including at least a portion of a plurality of first read requests, so that the memory dies interleave and output data corresponding to the first read requests, and performs a correlation operation for the selected second read request, when the second read request is selected, the controller determines whether the correlation operation is performed or not before a time at which the second read request is selected, determines whether the correlation operation is successful or not, determines a pending credit in response to an operation state of the memory dies at the time at which the second read request is selected, and determines whether to perform the correlation operation or not for the second read request that is selected at the time at which the second read request is selected based on the pending credit. 1. A memory system , comprising:a plurality of memory dies; anda controller that is coupled to the memory dies through a plurality of channels, the controller comprising circuitry that:selects a second read request, including at least a portion of a plurality of first read requests transferred from an external device, so that the memory dies interleave and output data corresponding to the first read requests through the channels, andperforms a correlation operation for the selected second read request,wherein, when the second read request is selected, the controller determines whether the correlation operation is performed or not before a time at which the second read request is selected, determines whether the correlation operation is successful or not, determines a pending credit in response to an operation state of the memory dies at the time at which the second read request is selected, and determines whether to perform the correlation operation or not for the second read request that is selected at the time at which the second read request is selected ...

Подробнее

Номер записи: 59

21-01-2021 дата публикации

NON-VOLATILE MEMORY DEVICES AND PROGRAM METHODS THEREOF

Номер: US20210020256A1

Автор: KIM Seongjin, Kim Wandong, NAM Sang-Wan, PARK Jinwoo

Принадлежит: SAMSUNG ELECTRONICS CO., LTD.

A program method of a non-volatile memory device, the non-volatile memory device including a peripheral circuit region and a memory cell region including a cell substrate and a cell string having memory cells stacked perpendicular to a surface of a cell substrate, the method includes performing a first program phase including programming a first memory cell connected to a first word line and applying a first pass voltage to other word lines above or below the first word line, and performing a second program phase including programming a second memory cell being connected to a second word line closer to the cell substrate, applying a second pass voltage to a first word line group below the second word line and applying a third pass voltage to a second word line group above the second word line, the second pass voltage being lower than the third pass voltage. 1. A program method of a non-volatile memory device , the non-volatile memory device including a peripheral circuit region and a memory cell region vertically connected to the peripheral circuit region , the peripheral circuit region including at least one first metal pad , the memory cell region including a cell substrate , a cell string , and at least one second metal pad directly connected with the at least one first metal pad , respectively , and the cell string in which a plurality of memory cells are stacked in a direction perpendicular to a surface of a cell substrate , the method comprising:performing a first program phase including programming a first memory cell among the plurality of memory cells, the first memory cell being connected to a first word line among a plurality of word lines of the cell string, the first program phase including applying a first pass voltage from the peripheral circuit region to other word lines among the plurality of word lines above or below the first word line with respect to the cell substrate; andperforming a second program phase including programming a second memory ...

Подробнее

Номер записи: 60

10-02-2022 дата публикации

Low latency memory access

Номер: US20220043758A1

Автор: Frederick A. Ware

Принадлежит: RAMBUS INC

A memory device includes receivers that use CMOS signaling levels (or other relatively large signal swing levels) on its command/address and data interfaces. The memory device also includes an asynchronous timing input that causes the reception of command and address information from the CMOS level receivers to be decoded and forwarded to the memory core (which is self-timed) without the need for a clock signal on the memory device's primary clock input. Thus, an activate row command can be received and initiated by the memory core before the memory device has finished exiting the low power state. Because the row operation is begun before the exit wait time has elapsed, the latency of one or more accesses (or other operations) following the exit from the low power state is reduced.

Подробнее

Номер записи: 61

24-01-2019 дата публикации

Error rate meter included in a semiconductor die

Номер: US20190025372A1

Автор: Grégoire Waelchli

Принадлежит: Semiconductor Components Industries LLC

An apparatus for performing an electrical test at a device is described. In one general implementation, an apparatus may include a memory, a receiver, and a processor. The receiver is configured to receive a test signal, convert the test signal into a digital test signal (bit stream) and store the digital test signal in the memory. The receiver identifies when a pre-defined number of bits of the bit stream are available in the memory. The processor is configured to perform a logic operation on the bit stream and a reference signal, generate a test result based on the logic operation, and determine whether the test result satisfies a condition. In some implementations, the processor may be configured to synchronize the digital test signal with the reference signal prior to performing of the logic operation.

Подробнее

Номер записи: 62

25-01-2018 дата публикации

Method and apparatus for serial data output in memory device

Номер: US20180025757A1

Автор: Johnny Chan, Tinwai Wong

Принадлежит: Winbond Electronics Corp

A memory device includes a memory array storing data, a sense amplifier configured to read a plurality of data bits from the memory array and output a sense data signal including the data bits read from the memory array, a data multiplexer configured to receive the sense data signal and generate a plurality of group signals, a plurality of local data registers coupled to the data multiplexer, at least one of the local data registers being configured to generate a serial data output signal according to an output mode, and a plurality of output circuits coupled to respective ones of the plurality of local data registers, at least one of the output circuits being configured to receive the serial data output signal output from the at least one of the local data registers and sequentially output the data bits included in the serial data output signal.

Подробнее

Номер записи: 63

25-01-2018 дата публикации

METHODS OF OPERATING BUFFERED MULTI-RANK MEMORY MODULES CONFIGURED TO SELECTIVELY LINK RANK CONTROL SIGNALS

Номер: US20180025788A1

Автор: Han YouKeun, Kim Seokil, KIM Tae-Hyung, LIM JONGHYOUNG, SHIN HUICHONG, Yun Young

Принадлежит:

A method of operating a memory module including a plurality of semiconductor memory devices organized into a multi-rank memory on a DIMM and a memory buffer included on the DIMM, operatively coupled to the multi-rank memory, can be provided by mapping an access to the DIMM from a memory controller to semiconductor memory devices included in more than one rank within the multi-rank memory based on a mode register set signal and selectively linking rank control signals during a parallel bit test operation to the more than one rank within the multi-rank memory plurality of semiconductor memory devices. 1. A memory module , comprising:a plurality of semiconductor memory devices on a substrate to provide a DIMM organized into at least two ranks; anda memory buffer configured to change states of input signals received for each rank based on a mapping table defined according to a mode register set signal and configured to control the plurality of semiconductor memory devices for each rank.2. The memory module of claim 1 , wherein the input signals include a rank control signal configured to select the semiconductor memory devices for each rank.3. The memory module of claim 1 , wherein the input signals include clock enable signals for each rank.4. The memory module of claim 1 , wherein the input signals include on-die termination signals for each rank.5. The memory module of claim 1 , wherein the semiconductor memory devices provide a stacked memory device configured to communicate data and control signals through a plurality of through-silicon lines.6. A method of operating a memory module including a plurality of semiconductor memory devices organized into a multi-rank memory on a DIMM and a memory buffer included on the DIMM claim 1 , operatively coupled to the multi-rank memory claim 1 , the method comprising:mapping an access to the DIMM from a memory controller to semiconductor memory devices included in more than one rank within the multi-rank memory based on a mode ...

Подробнее

Номер записи: 64

10-02-2022 дата публикации

SEMICONDUCTOR DEVICE AND READING METHOD

Номер: US20220044712A1

Автор: OKABE Sho, SENOO Makoto

Принадлежит: WINBOND ELECTRONICS CORP.

A semiconductor device capable of performing high-speed read or high-reliability read is provided. A reading method of a NAND flash memory includes: pre-charging a sensing node through a voltage-supply node; discharging the sensing node to the voltage-supply node for a prescribed operation; recharging the sensing node by the voltage-supply node after the prescribed operation; and discharging a NAND string and sensing a memory cell. 1. A reading method of a NAND flash memory , comprising:a first step, pre-charging a sensing node by a voltage from a voltage-supply node;a second step, discharging a voltage of the sensing node to the voltage-supply node to perform a prescribed operation;a third step, after the prescribed operation, recharging the sensing node by the voltage from the voltage-supply node; anda fourth step, after the third step, discharging a NAND string and performing sensing of a memory cell.2. The reading method according to claim 1 , whereinthe prescribed operation comprises resetting a latch circuit of a page buffer/sensing circuit or making a selected bit line to be in a floating state during a period until an unselected bit line finishes discharging.3. The reading method according to claim 1 , whereina driving capability of the voltage-supply node in the third step is equal to or greater than a driving capability of the voltage-supply node in the first step.4. The reading method according to claim 1 , whereinin the third step, a driving capability of the voltage-supply node changes in stages.5. The reading method according to claim 1 , further comprising a fifth step of connecting electrically a selected bit line to the sensing node after the sensing node is recharged.6. A semiconductor device claim 1 , comprising:a NAND memory cell array;a reading member, reading data from a selected page of the memory cell array; andan output member, outputting the data read by the reading member to an outside, whereinthe reading member comprises a page buffer/ ...

Подробнее

Номер записи: 65

23-01-2020 дата публикации

MULTI-LEVEL SIGNALING IN MEMORY WITH WIDE SYSTEM INTERFACE

Номер: US20200028720A1

Автор: Balb Markus, Ebert Ralf, Hollis Timothy M.

Принадлежит:

Techniques are provided herein to increase a rate of data transfer across a large number of channels in a memory device using multi-level signaling. Such multi-level signaling may be configured to increase a data transfer rate without increasing the frequency of data transfer and/or a transmit power of the communicated data. An example of multi-level signaling scheme may be pulse amplitude modulation (PAM). Each unique symbol of the multi-level signal may be configured to represent a plurality of bits of data. 1. (canceled)2. An apparatus , comprising:an array of memory cells;a controller configured to control operation of memory cells in the array of memory cells;an interposer formed of a first material and operatively coupled with the array of memory cells and the controller, wherein the interposer comprises a plurality of channels between the array of memory cells and the controller;a substrate coupled with the interposer and formed of a second material different than the first material; anda receiver configured to determine a logic state represented by a signal modulated using a first modulation scheme communicated across at least one channel of the interposer.3. The apparatus of claim 2 , further comprising:a driver configured to generate the signal to be transmitted across the at least one channel of the interposer based at least in part on a plurality of information bits.4. The apparatus of claim 2 , wherein the signal comprises a binary-level signal.5. The apparatus of claim 4 , wherein the first modulation scheme comprises a non-return-to-zero (NRZ) scheme claim 4 , a unipolar encoding scheme claim 4 , a bipolar encoding scheme claim 4 , a Manchester encoding scheme claim 4 , a two-level pulse amplitude modulation (PAM) scheme claim 4 , or a combination thereof.6. The apparatus of claim 2 , wherein the signal comprises a non-binary signal.7. The apparatus of claim 6 , wherein the first modulation scheme comprises a four-level pulse amplitude modulation (PAM ...

Подробнее

Номер записи: 66

02-02-2017 дата публикации

Flash memory controller with calibrated data communication

Номер: US20170031854A1

Автор: Benedict Chung-Kwong Lau, Bruno W. Garlepp, Donald C. Stark, Jared Levan Zerbe, Jun Kim, Kevin S. Donnelly, Leung Yu, Mark A. Horowitz, Roxanne Vu, Stefanos Sidiropoulos, Tsyr-Chyang Ho

Принадлежит: RAMBUS INC

An integrated circuit device includes a transmitter circuit operable to transmit a timing signal over a first wire to a DRAM. The DRAM receives a first signal having a balanced number of logical zero-to-one transitions and one-to-zero transitions and samples the first signal at a rising edge of the timing signal to produce a respective sampled value. The device further includes a receiver circuit to receive the respective sampled value from the DRAM over a plurality of wires separate from the first wire. In a first mode, the transmitter circuit repeatedly transmits incrementally offset versions of the timing signal to the DRAM until sampled values received from the DRAM change from a logical zero to a logical one or vice versa; and in a second mode, it transmits write data over the plurality of wires to the DRAM according to a write timing offset generated based on the sampled values.

Подробнее

Номер записи: 67

17-02-2022 дата публикации

Internal signal monitoring circuit

Номер: US20220050737A1

Автор: Yusuke Sakamoto

Принадлежит: Micron Technology Inc

Disclosed herein is an apparatus that includes a first circuit configured to measure a first time period from a first active edge of one of plurality of internal signals to a second active edge of one of the plurality of internal signals, and a second circuit configured to compare the first time period with a second time period to generate an alert signal.

Подробнее

Номер записи: 68

17-02-2022 дата публикации

NARROW DRAM CHANNEL SYSTESM AND METHODS

Номер: US20220050794A1

Автор: LI Shuangchen, LIN Jilan, NIU Dimin, XIE Yuan, Zheng Hongzhong

Принадлежит:

The systems and methods are configured to efficiently and effectively access memory. In one embodiment, a memory controller comprises a request queue, a buffer, a control component, and a data path system. The request queue receives memory access requests. The control component is configured to process information associated with access requests via a first narrow memory channel and a second narrow memory channel. The first narrow memory channel and the second narrow memory channel can have a portion of command/control communication lines and address communication lines that are included in and shared between the first narrow memory channel and the second narrow memory channel. The data path system can include a first data module and one set of unshared data lines associated with the first memory channel and a second data module and another set of unshared data lines associated with second memory channel. 1. A memory controller comprising;a request queue configured to receive memory access requests;a buffer configured to buffer data associated with the memory access requests;a control component configured to process the memory access requests, wherein commands, address, and data associated with the memory access requests are configured based upon communications between the control component and a first narrow memory channel and a second narrow memory channel, wherein the first narrow memory channel and the second narrow memory channel comprise communication lines including data communication lines, command/control communication lines, and address communication lines, and wherein a portion of the command/control communication lines and the address communication lines are included in and shared between the first narrow memory channel and the second narrow memory channel; anda data path system configured to process data associated with the plurality of access requests, wherein the data path system includes a first data module associated with the first narrow memory ...

Подробнее

Номер записи: 69

01-02-2018 дата публикации

Apparatuses and methods for operations in a self-refresh state

Номер: US20180033479A1

Автор: Glen E. Hush, Perry V. Lea

Принадлежит: Micron Technology Inc

The present disclosure includes apparatuses and methods for performing operations by a memory device in a self-refresh state. An example includes an array of memory cells and a controller coupled to the array of memory cells. The controller is configured to direct performance of compute operations on data stored in the array when the array is in a self-refresh state.

Подробнее

Номер записи: 70

30-01-2020 дата публикации

SEMICONDUCTOR APPARATUS AND DATA PROCESSING SYSTEM

Номер: US20200035274A1

Автор: JOO Young Pyo, KIM Myoung Seo, LEE SEUNG YONG

Принадлежит:

A semiconductor apparatus may include: a pad unit including a plurality of pads; a memory cell array coupled to the pad unit through input/output signal lines; and a pad configuration control circuit configured to change a pad configuration of the pad unit by dividing the plurality of pads into a plurality of groups and setting the plurality of groups to different modes, respectively. 1. A semiconductor apparatus comprising:a pad unit comprising a plurality of pads;a memory cell array coupled to the pad unit through input and output (input/output) signal lines; anda pad configuration control circuit configured to change a pad configuration of the pad unit by dividing the plurality of pads into groups and setting the groups to different modes, respectively.2. The semiconductor apparatus according to claim 1 , wherein the pad configuration control circuit changes the pad configuration of the pad unit by independently controlling input/output paths of the input/output signal lines according to a pad configuration control signal claim 1 , which is generated through source signals inputted from an external device.3. The semiconductor apparatus according to claim 1 , wherein the plurality of pads comprises one or more of address pads claim 1 , command pads and dedicated pads used only to input source signals.4. The semiconductor apparatus according to claim 1 , wherein one or more of the groups are set to one or more of an input/output-combined mode claim 1 , an input-dedicated mode claim 1 , an output-dedicated mode and an input/output blocking mode.5. The semiconductor apparatus according to claim 1 , wherein the pad configuration control circuit comprises a plurality of switches coupled in parallel to each of the input/output signal lines.6. The semiconductor apparatus according to claim 1 , further comprising a pad configuration control signal generation circuit configured to receive source signals from an external device through address pads of the pad unit claim 1 , ...

Подробнее

Номер записи: 71

30-01-2020 дата публикации

Semiconductor devices

Номер: US20200035275A1

Автор: Hyun Seung Kim, Young Jun YOON

Принадлежит: SK hynix Inc

A semiconductor device includes a synthesis control signal generation circuit and a data output control circuit. The synthesis control signal generation circuit generates a synthesis control signal for determining a burst sequence from a latch control signal in response to a first burst mode command and a second burst mode command. The data output control circuit outputs data included in a bank group as internal data in response to the synthesis control signal.

Подробнее

Номер записи: 72

08-02-2018 дата публикации

DATA I/O CIRCUITS AND SEMICONDUCTOR SYSTEMS INCLUDING THE SAME

Номер: US20180039532A1

Автор: JUNG Hun Sam, Kim Chang Hyun, KIM Min Chang, LEE Do Yun, LEE Jae Jin

Принадлежит: SK HYNIX INC.

A semiconductor system may include a first semiconductor device and a second semiconductor device. The first semiconductor device may output an external strobe signal and external data. The second semiconductor device may extract error information from the external data in synchronization with the external strobe signal during a write operation and outputs the external data and the error information through input/output (I/O) lines during the write operation. The second semiconductor device may correct errors of internal data with the error information loaded on the I/O lines to output the corrected internal data as the external data during a read operation. 1. A semiconductor system comprising:a first semiconductor device configured for outputting an external command, an external strobe signal and external data; anda second semiconductor device configured for blocking transmission of at least one bit included in the external data in response to the external command during a write operation, configured for extracting error information from the external data in synchronization with the external strobe signal during the write operation, configured for outputting the external data and the error information through input/output (I/O) lines during the write operation, and configured for correcting errors of internal data with the error information loaded on the I/O lines to output the corrected internal data as the external data during a read operation.2. The semiconductor system of claim 1 , wherein the external command is inputted to the second semiconductor device for an operation that the write operation is executed without outputting the external data after the read operation or for an operation that blocks transmission of at least one bit included in the external data.3. The semiconductor system of claim 1 , wherein the error information includes position information on bits of the external data that are inputted into the second semiconductor device without ...

Подробнее

Номер записи: 73

12-02-2015 дата публикации

APPARATUSES AND METHODS FOR CONFIGURING I/Os OF MEMORY FOR HYBRID MEMORY MODULES

Номер: US20150046631A1

Автор: Matthew A. Prather

Принадлежит: Micron Technology Inc

Apparatuses, hybrid memory modules, memories, and methods for configuring I/Os of a memory for a hybrid memory module are described. An example apparatus includes a non-volatile memory, a control circuit coupled to the non-volatile memory, and a volatile memory coupled to the control circuit. The volatile memory is configured to enable a first subset of I/Os for communication with a bus and enable a second subset of I/O for communication with the control circuit, wherein the control circuit is configured to transfer information between the volatile memory and the non-volatile memory.

Подробнее

Номер записи: 74

24-02-2022 дата публикации

STORAGE DEVICE AND OPERATING METHOD OF THE STORAGE DEVICE

Номер: US20220059142A1

Автор: CHUNG Seung Hyun

Принадлежит: SK HYNIX INC.

A memory device includes: memory cells; an operation mode determiner for determining any one of a normal operation mode and a memory communication operation mode of communicating data with another memory device; a pad control signal generator for generating a pad control signal for determining a pad to receive a signal corresponding to a data movement command of the memory controller according to the determined operation mode; a pad controller for receiving the signal through the determined pad according to the pad control signal; an internal command generator for generating an internal operation command corresponding to the data movement command according to the determined operation mode; and an operation controller for performing one of a read operation of reading first target data from the memory cells and a program operation of storing second target data in the memory cells, based on the internal operation command. 1. A memory device comprising:a plurality of memory cells;an operation mode determiner configured to determine any one of a normal operation mode and a memory communication operation mode of communicating data with another memory device according to an operation mode command input from a memory controller;a pad control signal generator configured to generate a pad control signal for determining a pad to receive a signal corresponding to a data movement command of the memory controller according to the determined operation mode;a pad controller configured to receive the signal corresponding to the data movement command through the determined pad according to the pad control signal;an internal command generator configured to generate an internal operation command corresponding to the data movement command according to the determined operation mode; andan operation controller configured to perform one of a read operation of reading first target data to be output to the another memory device from the plurality of memory cells and a program operation of ...

Подробнее

Номер записи: 75

24-02-2022 дата публикации

Timing delay control circuits and electronic devices including the timing delay control circuits

Номер: US20220059143A1

Автор: Woongrae Kim

Принадлежит: SK hynix Inc

An electronic device includes a strobe signal generation circuit and a data output control circuit. The strobe signal generation circuit delays a mode register command by a first predetermined delay period to generate a mode register strobe signal during a mode register read operation. The strobe signal generation circuit adjusts a timing of the mode register strobe signal by detecting variation of timings of first and second variable delay mode register commands, which is generated based on the mode register command, during the mode register read operation. The data output control circuit delays an operation code, which is generated based on the mode register command, by a second predetermined delay period to generate a delayed operation code. The data output control circuit outputs the delayed operation code as data in synchronization with the mode register strobe signal.

Подробнее

Номер записи: 76

24-02-2022 дата публикации

MEMORY DEVICE, CONTROLLER CONTROLLING THE SAME, MEMORY SYSTEM INCLUDING THE SAME, AND OPERATING METHOD THEREOF

Номер: US20220059144A1

Автор: CHO Hyunyoon, CHO Sukhee, Choi Junghwan, CHOI Youngdon, SON Younghoon

Принадлежит: SAMSUNG ELECTRONICS CO., LTD.

A method of operating a memory device includes receiving a training request for a data channel, detecting at least one mode parameter according to the training request, transmitting the detected mode parameter to an external device, setting at least one of an NRZ mode and a PAM4 mode to a transmission signaling mode based on mode register set setting information from the external device, and performing communications with the external device according to the set transmission signaling mode. 1. A memory device comprising:memory device processing circuitry configured totransmit read data to a data channel according to a transmission signaling mode;receive write data from the data channel according to the transmission signaling mode;store the transmission signaling mode; andperform a training operation on the data channel in response to a training request received from an external device, to detect at least one mode parameter in the training operation, to select one of a first transmission signaling mode and a second transmission signaling mode as the transmission signaling mode using the detected mode parameter, and to output mode flag information, associated with the detected mode parameter, to the external device.2. The memory device of claim 1 , wherein the first transmission signaling mode is a non-return-to-zero (NRZ) mode claim 1 , andthe second transmission signaling mode is a pulse amplitude modulation 4-level (PAM4) mode.3. The memory device of claim 1 , wherein the at least one parameter comprises at least one of a termination voltage corresponding to the data channel claim 1 , current consumed by the memory device claim 1 , and channel loss of the data channel.4. The memory device of claim 3 , wherein the memory device processing circuitry comprises a mode detection circuit which further comprises a termination voltage detector configured to detect the transmission signaling mode by comparing the termination voltage with a reference voltage.5. The memory ...

Подробнее

Номер записи: 77

24-02-2022 дата публикации

ELECTRONIC DEVICES EXECUTING A TERMINATION OPERATION

Номер: US20220059145A1

Автор: KIM Woongrae

Принадлежит: SK HYNIX INC.

An electronic device includes a termination control circuit and a data input/output (I/O) circuit. The termination control circuit is configured to generate a termination enablement signal which is activated during a termination operation period for activating a termination resistor while a write operation is performed. In addition, the termination control circuit is configured to adjust a period that the termination enablement signal is activated according to whether a write command is inputted to the termination control circuit during a set detection period of the write operation. The data I/O circuit is configured to receive data by activating the termination resistor during a period that the termination enablement signal is activated when the write operation is performed. 1. An electronic device comprising:{'claim-text': ['generate a termination enablement signal which is activated during a termination operation period for activating a termination resistor while a write operation is performed; and', 'adjust a period that the termination enablement signal is activated according to whether a write command is inputted to the termination control circuit during a set detection period of the write operation; and'], '#text': 'a termination control circuit configured to:'}a data input/output (I/O) circuit configured to receive data by activating the termination resistor during a period that the termination enablement signal is activated when the write operation is performed.2. The electronic device of claim 1 ,wherein the set detection period is set as a period from a point in time when the write command for the write operation is activated until a point in time when an internal termination-off signal is activated during the write operation; andwherein the internal termination-off signal is generated by delaying a write signal, which is generated based on the write command for the write operation, by a period including a write latency period and a burst length period.3. ...

Подробнее

Номер записи: 78

24-02-2022 дата публикации

ELECTRONIC DEVICES EXECUTING A TERMINATION OPERATION

Номер: US20220059146A1

Автор: KIM Woongrae

Принадлежит: SK HYNIX INC.

An electronic device includes a write shift circuit configured to generate, when a write operation is performed, a period signal which is activated for a clock enable period, based on a write command in synchronization with a write clock signal. The electronic device also includes a clock generation circuit configured to generate, when the write operation is performed, the write clock signal based on the period signal. The electronic device further includes a termination control circuit configured to generate a termination enablement signal, based on the period signal in the write operation, which is activated for a termination operation period. 1. An electronic device comprising:a write shift circuit configured to generate, when a write operation is performed, a period signal which is activated for a clock enable period, based on a write command in synchronization with a write clock signal;a clock generation circuit configured to generate, when the write operation is performed, the write clock signal based on the period signal; anda termination control circuit configured to generate a termination enablement signal, based on the period signal in the write operation, which is activated for a termination operation period.2. The electronic device according to claim 1 , wherein the clock generation circuit is configured to activate the write clock signal for a period in which the period signal is activated claim 1 , based on a clock signal.3. The electronic device according to claim 1 , wherein the termination control circuit is configured to:activate the termination enablement signal based on a set code and an internal latency write signal; andinactivate the termination enablement signal when the period signal is inactivated.4. The electronic device according to claim 1 , wherein:the write shift circuit is configured to generate, when the write operation is performed, a write flag signal for the write operation, by delaying the write command by a set delay period; ...

Подробнее

Номер записи: 79

07-02-2019 дата публикации

INTERLEAVE SET AWARE OBJECT ALLOCATION

Номер: US20190042409A1

Автор: Jereczek Grzegorz, LEBIODA Pawel, MACIEJEWSKI Maciej, MAKOWSKI Pawel, PELPLINSKI Piotr, Radtke Jakub, WISZ Aleksandra

Принадлежит: Intel Corporation

An embodiment of a semiconductor apparatus may include technology to identify a group of objects based on a common object structure, and allocate the group of objects to two or more memory channels based on interleave set information. Other embodiments are disclosed and claimed. 1. An electronic processing system , comprising:a processor;memory communicatively coupled to the processor; and identify a group of objects based on a common object structure, and', 'allocate the group of objects to two or more memory channels based on interleave set information., 'logic communicatively coupled to the processor to2. The system of claim 1 , wherein the logic is further to:identify an alignment field of the common object structure; andallocate the group of objects to start the alignment field for each object on a different one of the two or more memory channels.3. The system of claim 2 , wherein the logic is further to:add padding to each object to align the alignment field to start on the different one of the two or more memory channels.4. The system of claim 1 , wherein the logic is further to:access the group of objects with two or more of the memory channels.5. The system of claim 4 , wherein the logic is further to:access the group of objects with one or more of multi-threaded access, prefetch access, and vector instruction access.6. The system of claim 1 , wherein the two or more memory channels include non-volatile memory channels claim 1 , and wherein the group of objects include one or more of key-value objects and database objects.7. A semiconductor apparatus claim 1 , comprising:one or more substrates; and identify a group of objects based on a common object structure, and', 'allocate the group of objects to two or more memory channels based on interleave set information., 'logic coupled to the one or more substrates, wherein the logic is at least partly implemented in one or more of configurable logic and fixed-functionality hardware logic, the logic coupled to ...

Подробнее

Номер записи: 80

06-02-2020 дата публикации

LOGIC DRIVE BASED ON STANDARD COMMODITY FPGA IC CHIPS

Номер: US20200042665A1

Автор: Lee Jin-Yuan, Lin Mou-Shiung

Принадлежит:

A chip package used as a logic drive, includes: multiple semiconductor chips, a polymer layer horizontally between the semiconductor chips; multiple metal layers over the semiconductor chips and polymer layer, wherein the metal layers are connected to the semiconductor chips and extend across edges of the semiconductor chips, wherein one of the metal layers has a thickness between 0.5 and 5 micrometers and a trace width between 0.5 and 5 micrometers; multiple dielectric layers each between neighboring two of the metal layers and over the semiconductor chips and polymer layer, wherein the dielectric layers extend across the edges of the semiconductor chips, wherein one of the dielectric layers has a thickness between 0.5 and 5 micrometers; and multiple metal bumps on a top one of the metal layers, wherein one of the semiconductor chips is a FPGA IC chip, and another one of the semiconductor chips is a NVMIC chip. 1. A chip package comprising:a first semiconductor chip;a polymer layer on a same plane as the first semiconductor chip;a metal via in the polymer layer;a first interconnection scheme over the first semiconductor chip, polymer layer and metal via and across over an edge of the first semiconductor chip, wherein the first interconnection scheme comprises a first interconnection metal layer over the first semiconductor chip, polymer layer and metal via and across over the edge of the first semiconductor chip, a second interconnection metal layer over the first interconnection metal layer and a first insulating dielectric layer between the first and second interconnection metal layers, wherein the first semiconductor chip couples to the metal via through the first interconnection metal layer; anda second semiconductor chip over the first interconnection scheme and the first semiconductor chip, wherein the second semiconductor chip couples to the first semiconductor chip through the first and second interconnection metal layers.2. The chip package of further ...

Подробнее

Номер записи: 81

18-02-2021 дата публикации

Memory Controller For Selective Rank Or Subrank Access

Номер: US20210049115A1

Автор: Hampel Craig E., Ware Frederick A.

Принадлежит:

A memory module having reduced access granularity. The memory module includes a substrate having signal lines thereon that form a control path and first and second data paths, and further includes first and second memory devices coupled in common to the control path and coupled respectively to the first and second data paths. The first and second memory devices include control circuitry to receive respective first and second memory access commands via the control path and to effect concurrent data transfer on the first and second data paths in response to the first and second memory access commands. 1. (canceled)2. A memory controller comprising:circuitry to determine whether a memory comprising memory arrays is to be operated in a first mode or a second mode; andcircuitry to issue memory access commands; in the first mode, the circuitry to issue is to transmit first memory access command to the memory which selects read data in a first one of the memory arrays and read data in a second one of the memory arrays, and', 'in the second mode, the circuitry to issue is to transmit a second memory access command to the memory which selects read data in the first one of the memory arrays and, prior to output by the memory of the read data from the first one of the memory arrays, is to transmit a third memory access command to the memory which selects read data in the second one of the memory arrays., 'wherein'}3. The memory controller of claim 2 , wherein:the memory controller is to couple to both of the first one of the memory arrays and the second one of the memory arrays via a common control path;the circuitry to issue is to transmit first, second and third memory access commands to the memory via the common control path;the memory controller is to couple to the first one of the memory arrays via a first data path and to the second one of the memory arrays via a second data path;the memory controller comprises further comprises circuitry to receive the read data ...

Подробнее

Номер записи: 82

07-02-2019 дата публикации

Reading circuits and methods

Номер: US20190043542A1

Автор: Jiesheng Chen, Wenxiao LI

Принадлежит: Shanghai Zhaoxin Semiconductor Co Ltd

A reading circuit is provided in the invention. The reading circuit includes a pre-charger, a bit-line selecting circuit, and a latch circuit. The pre-charger receives a pre-charging control signal and the pre-charger is opened or closed according to the pre-charging control signal. The bit-line selecting circuit is coupled with the pre-charger at a node and selects a bit line for reading data according to a selecting signal. The latch circuit is coupled with the pre-charger at a node and outputs and latches the data of the bit line.

Подробнее

Номер записи: 83

07-02-2019 дата публикации

Partial refresh technique to save memory refresh power

Номер: US20190043558A1

Автор: Dexter Tamio Chun, Haw-Jing Lo, Jungwon Suh, Yanru Li

Принадлежит: Qualcomm Inc

In a conventional memory subsystem, a memory controller issues explicit refresh commands to a DRAM memory device to maintain integrity of the data stored in the memory device when the memory device is in an auto-refresh mode. A significant amount of power may be consumed to carry out the refresh. To address this and other issues, it is proposed to allow a partial refresh in the auto-refresh mode in which the refreshing operation may be skipped for a subset of the memory cells. Through such selective refresh skipping, the power consumed for auto-refreshes may be reduced. Operating system kernels and memory drivers may be configured to determine areas of memory for which the refreshing operation can be skipped.

Подробнее

Номер записи: 84

07-02-2019 дата публикации

Semiconductor memory device and control method therefor

Номер: US20190043586A1

Автор: Seiji Sawada

Принадлежит: Renesas Electronics Corp

To prolong the lifetime of a semiconductor memory device without performing complicated control. A semiconductor memory device according to one embodiment is equipped with a bank A and a bank B operable complementarily to each other, and a bank selection circuit which selects either one of the banks A and B. The bank selection circuit alternately switches the bank to be selected, each time an erase command to instruct erasing of data in either one of the banks A and B is issued.

Подробнее

Номер записи: 85

06-02-2020 дата публикации

SEMICONDUCTOR DIES SUPPORTING MULTIPLE PACKAGING CONFIGURATIONS AND ASSOCIATED METHODS

Номер: US20200043532A1

Автор: Brox Martin

Принадлежит:

A memory device configured to support multiple memory densities is provided. The memory device includes a first plurality of electrical contacts corresponding to a first command/address channel, a second plurality of electrical contacts corresponding to a second command/address channel, a third plurality of electrical contacts corresponding to a first data bus, a fourth plurality of electrical contacts corresponding to a second data bus, and mode selection circuitry configured to place the memory device in the first mode or the second mode. In the first mode, the first plurality of memory cells is operatively coupled to the first and third pluralities of electrical contacts and the second plurality of memory cells is operatively coupled to the second and fourth plurality of electrical contacts. In the second mode, the first and second pluralities of memory cells are both operatively coupled to the first and third pluralities of electrical contacts. 1. A memory device , comprising: a first plurality of package electrical contacts corresponding to a first command/address channel,', 'a second plurality of package electrical contacts corresponding to a second command/address channel,', 'a third plurality of package electrical contacts corresponding to a first data bus,', 'a fourth plurality of package electrical contacts corresponding to a second data bus;, 'a package substrate including'} a first memory array including first and second pluralities of memory cells, and', 'first mode selection circuitry configured to place the first memory die into either a first mode or a second mode,', 'wherein, in the first mode, the first plurality of memory cells is operatively coupled to the first and third pluralities of package electrical contacts and the second plurality of memory cells is operatively coupled to the second and fourth pluralities of package electrical contacts, and', 'wherein, in the second mode, the first and second pluralities of memory cells are operatively ...

Подробнее

Номер записи: 86

18-02-2021 дата публикации

MEMORY DEVICE COMPRISING PROGRAMMABLE COMMAND-AND-ADDRESS AND/OR DATA INTERFACES

Номер: US20210050043A1

Автор: Bansal Akash, Ho Fan, Lai Lawrence, Leibowitz Brian S., Oh Kyung Suk, Richardson Wayne S., Secker David A., Shaeffer Ian

Принадлежит: RAMBUS INC.

A memory device comprising a programmable command-and-address (CA) interface and/or a programmable data interface is described. In an operational mode, two or more CA interfaces may be active. In another operational mode, at least one, but not all, CA interfaces may be active. In an operational mode, all of the data interfaces may be active. In another operational mode, at least one, but not all, data interfaces may be active. The memory device can include circuitry to select: an operational mode; a sub-mode within an operational mode; one or more CA interfaces as the active CA interface(s); a main CA interface from multiple active CA interfaces; and/or one or more data interfaces as the active data interfaces. The circuitry may perform these selection(s) based on one or more bits in one or more registers and/or one or more signals received on one or more pins. 120-. (canceled)21. A dynamic random access memory device , comprising:a first set of pins located on a first side of a line of symmetry, the first set of pins corresponding to a first command-and-address (CA) interface;a second set of pins located on a second side of the line of symmetry and in a mirror configuration with respect to the first set of pins, the second set of pins corresponding to a second CA interface; andcircuitry to receive, via the first set of pins, a first command that specifies a first memory access, and, the circuitry to receive, via the second set of pins, a second command that specifies a second memory access.22. The dynamic random access memory device of claim 21 , wherein each pin in the first set of pins mirrors a respective pin in the second set of pins across the line of symmetry.23. The dynamic random access memory device of claim 21 , wherein the first set of pins and the second set of pins are suitably arranged for use in a clamshell configuration.24. The dynamic random access memory device of claim 21 , further comprising a data interface to transfer data corresponding to the ...

Подробнее

Номер записи: 87

07-02-2019 дата публикации

MULTI-LEVEL SIGNALING IN MEMORY WITH WIDE SYSTEM INTERFACE

Номер: US20190044764A1

Автор: Balb Markus, Ebert Ralf, Hollis Timothy M.

Принадлежит:

Techniques are provided herein to increase a rate of data transfer across a large number of channels in a memory device using multi-level signaling. Such multi-level signaling may be configured to increase a data transfer rate without increasing the frequency of data transfer and/or a transmit power of the communicated data. An example of multi-level signaling scheme may be pulse amplitude modulation (PAM). Each unique symbol of the multi-level signal may be configured to represent a plurality of bits of data. 1. An electronic memory apparatus , comprising:an array of memory cells;a controller configured to control access to the array of memory cells;an interposer to operatively couple the array of memory cells with the controller, the interposer including a plurality of channels between the array of memory cells and the controller; anda receiver configured to decode a multi-level signal modulated using a first modulation scheme having at least three levels communicated across at least one channel of the interposer.2. The apparatus of claim 1 , further comprising:a driver configured to generate the multi-level signal to be transmitted across the at least one channel of the interposer based at least in part on a plurality of information bits.3. The apparatus of claim 1 , wherein the receiver further comprises:a plurality of comparators, each comparator configured to compare the multi-level signal to a voltage threshold.4. The apparatus of claim 3 , wherein the receiver further comprises:a decoder configured to determine a plurality of bits represented by the multi-level signal based at least in part on information received from a set of the plurality of comparators.5. The apparatus of claim 1 , wherein:a plurality of information bits are represented by an amplitude of the multi-level signal.6. The apparatus of claim 1 , wherein:the multi-level signal is encoded with information using a pulse-amplitude modulation (PAM) scheme.7. The apparatus of claim 1 , wherein:the ...

Подробнее

Номер записи: 88

16-02-2017 дата публикации

Design structure for reducing pre-charge voltage for static random-access memory arrays

Номер: US20170046465A1

Автор: Alexander Fritsch, Amira Rozenfeld, Dieter Wendel, Rolf Sautter

Принадлежит: International Business Machines Corp

A memory cell arrangement of SRAM cell groups may be provided in which in each of the groups multiple SRAM cells are connected to an input of a local read amplifier by at least one common local bit-line. Outputs of the amplifiers are connected to a shared global bit-line. The global bit-line is connected to a pre-charge circuit, and the pre-charge circuit is adapted for pre-charging the global bit-line with a programmable pre-charge voltage before reading data. The pre-charge circuit comprises a limiter circuit which comprises a pre-charge regulator circuit connected to the global bit-line to pre-charge the global bit-line with the programmable pre-charge voltage, and an evaluation and translation circuit connected to the pre-charge regulator circuit and the global bit-line to compensate leakage current of the global bit-line without changing its voltage level.

Подробнее

Номер записи: 89

16-02-2017 дата публикации

Data Storage Method, Storage Apparatus, and Computing Device

Номер: US20170047119A1

Автор: Jun Xu, Junfeng Zhao

Принадлежит: Huawei Technologies Co Ltd

A data storage method, a storage apparatus and a computing device are disclosed. The method includes receiving a presetting command sent by a CPU, where the presetting command instructs to write 1 to a location, which corresponds to a cache line, in memory; writing, according to the presetting command, 1 to the location, which corresponds to the cache line, in the memory; receiving a write command sent by the CPU of writing data in the cache line to the memory; and writing, according to the write command, data 0 in the cache line to a location, which corresponds to the data 0, in the memory.

Подробнее

Номер записи: 90

15-02-2018 дата публикации

MEMORY DEVICE COMPRISING PROGRAMMABLE COMMAND-AND-ADDRESS AND/OR DATA INTERFACES

Номер: US20180047436A1

Автор: Bansal Akash, Ho Fan, Lai Lawrence, Leibowitz Brian S., Oh Kyung Suk, Richardson Wayne S., Secker David A., Shaeffer Ian

Принадлежит: RAMBUS INC.

A memory device comprising a programmable command-and-address (CA) interface and/or a programmable data interface is described. In an operational mode, two or more CA interfaces may be active. In another operational mode, at least one, but not all, CA interfaces may be active. In an operational mode, all of the data interfaces may be active. In another operational mode, at least one, but not all, data interfaces may be active. The memory device can include circuitry to select: an operational mode; a sub-mode within an operational mode; one or more CA interfaces as the active CA interface(s); a main CA interface from multiple active CA interfaces; and/or one or more data interfaces as the active data interfaces. The circuitry may perform these selection(s) based on one or more bits in one or more registers and/or one or more signals received on one or more pins. 120-. (canceled)21. A method comprising:providing command-and-address (CA) interface configuration information to a pair of memory devices comprising a first memory device and a second memory device, wherein the pair of memory devices is arranged in a clamshell configuration, wherein the CA interface configuration information specifies which pairs of CA interfaces are to be configured as active CA interfaces, wherein each pair of CA interfaces comprises a first CA interface on the first memory device and a second CA interface on the second memory device, and wherein the first CA interface and the second CA interface are physically aligned with each other;providing a CA signal to one or more pairs of CA interfaces.22. The method of claim 21 , wherein the CA interface configuration information specifies an operational mode that is selected from a set of operational modes in which the pair of memory devices can be operated.23. The method of claim 22 , wherein the set of operational modes comprises a first operational mode in which each memory device supports multiple microthreads claim 22 , and a second ...

Подробнее

Номер записи: 91

15-02-2018 дата публикации

SEMICONDUCTOR MEMORY APPARATUS

Номер: US20180047441A1

Автор: EM Ho Seok

Принадлежит: SK HYNIX INC.

A semiconductor memory apparatus includes a bias voltage generation circuit configured to generate a bias voltage according to a read voltage or a write voltage in response to a read signal and a write signal, a data discrimination circuit configured to generate a set enable signal and a reset enable signal in response to data and the write signal. The semiconductor memory apparatus also includes a current selection circuit configured to generate a first current in response to the read signal, the set enable signal, and the reset enable signal. The semiconductor memory apparatus further includes a driver configured to receive the first current and generate a second current in response to a voltage level of the bias voltage, and a first switch configured to provide the second current to a memory cell in response to the read signal and the write signal. 1. A semiconductor memory apparatus comprising:a bias voltage generation circuit configured to generate a bias voltage according to a read voltage or a write voltage in response to a read signal and a write signal;a data discrimination circuit configured to generate a set enable signal and a reset enable signal in response to data and the write signal;a current selection circuit configured to generate a first current in response to the read signal, the set enable signal, and the reset enable signal;a driver configured to receive the first current, and generate a second current in response to a voltage level of the bias voltage; anda first switch configured to provide the second current to a memory cell in response to the read signal and the write signal.2. The semiconductor memory apparatus according to claim 1 , wherein:the bias voltage generation circuit generates the bias voltage in response to a voltage level of the read voltage when the read signal is enabled; andthe bias voltage generation circuit generates the bias voltage when the write signal is enabled, such that a voltage formed between the driver and the ...

Подробнее

Номер записи: 92

03-03-2022 дата публикации

Memory device with configurable error correction modes

Номер: US20220066867A1

Автор: Aaron P. Boehm, Scott E. Schaefer

Принадлежит: Micron Technology Inc

Methods, systems, and apparatus to selectively implement single-error correcting (SEC) operations or single-error correcting and double-error detecting (SECDED) operations, without noticeably impacting die size, for information received from a host device. For example, a host device may indicate that a memory system is to implement SECDED operations using one or more communications (e.g., messages). In another example, the memory system may be hardwired to perform SECDED for certain options. The memory system may adapt circuitry associated with SEC operations to implement SECDED operations without noticeably impacting die size. To implement SECDED operations using SEC circuitry, the memory system may include some additional circuitry to repurpose the SEC circuitry for SECDED operations.

Подробнее

Номер записи: 93

03-03-2022 дата публикации

Computing-In-Memory Architecture

Номер: US20220068328A1

Автор: Chang Jonathan Tsung-Yung, CHIH Yu-Der, LEE Chia-Fu, Shih Yi-Chun

Принадлежит:

Systems and methods are provided for a computing-in memory circuit that includes a bit line and a plurality of computing cells connected to the bit line. Each of the plurality of computing cells includes a memory element, having a data output terminal; a logic element, having a first input terminal, a second input terminal and an output terminal, wherein the first input terminal is coupled to the data output terminal of the memory element, the second input terminal receives a select signal; and a capacitor, having a first terminal and a second terminal, where the first terminal is coupled to the output terminal of the logic element, the second terminal is coupled to the bit line. A voltage of the bit line is driven by the plurality of computing cells. 1. A memory circuit , comprising:a bit line; and a memory element, having a data output terminal;', 'a logic element, having a first input terminal, a second input terminal and an output terminal, wherein the first input terminal is coupled to the data output terminal of the memory element, the second input terminal is configured to receive a select signal; and', 'a capacitor, having a first terminal and a second terminal, wherein the first terminal is coupled to the output terminal of the logic element, the second terminal is coupled to the bit line,, 'a plurality of computing cells, connected to the bit line, and each of the plurality of computing cells comprisingwherein voltage of the bit line is configured to be driven by the plurality of computing cells.2. The circuit of claim 1 , wherein the logic element drives the first terminal of the capacitor to a high level or a low level based on the select signal and a signal from the data output terminal of the memory element.3. The circuit of claim 2 , wherein the logic element prevents the first terminal of the capacitor from floating while the circuit is operational.4. The circuit of claim 1 , further comprising a voltage detector coupled to the bit line.5. The ...

Подробнее

Номер записи: 94

03-03-2022 дата публикации

APPARATUSES AND METHODS TO PERFORM LOW LATENCY ACCESS OF A MEMORY

Номер: US20220068329A1

Автор: He Yuan, Toyama Daigo

Принадлежит: MICRON TECHNOLOGY, INC.

An exemplary memory is configurable to operate in a low latency mode through use of a low latency register circuit to execute a read or write command, rather performing a memory army access to execute the read or write command. A control circuit determines whether an access command should be performed using the low latency mode of operation (e.g., first mode of operation) or a normal mode of operation (e.g., second mode of operation). In some examples, a processor unit directs the memory to execute an access command using the low latency mode of operation via one or more bits (e.g., a low latency enable bit) included in the command and address information. 1. An apparatus comprising:a memory array comprising a plurality of memory cells, wherein a particular one of the plurality of memory cells is configured to retain stored data based on a respective row and column address;a register circuit configured to store addresses and corresponding data; anda control circuit configured to receive, via a command and address bus, command and address information, wherein the command and address information includes the respective row and column address corresponding to the particular one of the plurality of memory cells of the memory array, wherein the control circuit is configured to selectively direct the command and address information including the respective row and column address to the memory array in response to a low latency mode being disabled and to direct the command and address information including the respective row and column address to the register circuit in response to the low latency mode being enabled.2. The apparatus of claim 1 , wherein the low latency mode is enabled via a low latency enable bit of the command and address information claim 1 , wherein the control circuit is configured to determine that the low latency mode is enabled in response to the low latency enable bit having a first value and to determine that the low latency mode is disabled in ...

Подробнее

Номер записи: 95

03-03-2022 дата публикации

MEMORY DEVICE, A CONTROLLER FOR CONTROLLING THE SAME, A MEMORY SYSTEM INCLUDING THE SAME, AND A METHOD OF OPERATING THE SAME

Номер: US20220068366A1

Автор: KIM NAMSUNG, KWON Youngcheon, LEE SUKHAN, O SEONGIL, SOHN KYOMIN, YOUN Jaeyoun

Принадлежит:

A memory device including: a plurality of pins for receiving control signals from an external device; a first bank having first memory cells, wherein the first bank is activated in a first operation mode and a second operation mode; a second bank having second memory cells, wherein the second bank is deactivated in the first operation mode and activated in the second operation mode; a processing unit configured to perform an operation on first data, output from the first memory cells, and second data, output from the second memory cells, in the second operation mode; and a processing-in-memory (PIM) mode controller configured to select mode information, indicating one of the first operation mode and the second operation mode, in response to the control signals and to control at least one memory parameter, at least one mode register set (MRS) value, or a refresh mode according to the mode information.

Подробнее

Номер записи: 96

22-02-2018 дата публикации

I/O MODULE

Номер: US20180052434A1

Автор: MAEKAWA Takaaki

Принадлежит: DENSO WAVE INCORPORATED

In an I/O module, a communication enables communications between first and second external devices upon a voltage being supplied from a power source thereto. A shutoff switch shuts off supply of the voltage to the communication controller when turned off. A capacitor is charged based on the voltage supplied from the voltage source while the shutoff switch is in an on state. The capacitor supplies an operating voltage to the communication controller while the shutoff switch is turned off. The communication controller detects a voltage across the capacitor as a diagnostic voltage, and outputs a turn-off command to the shutoff switch for turning off the shutoff switch. The communication controller determines whether there is a fixedly closed malfunction in the shutoff switch based on the diagnostic voltage while outputting the turn-off command to the shutoff switch. 1. An I/O module to which a first external device and a second external device are connected , the I/O module comprising: enable communications between the first external device and the second external device upon a voltage supplied from the voltage source being equal to or higher than a lower limit of the operable voltage range; and', 'disable communications between the first external device and the second external device upon the voltage supplied from the voltage source being lower than the lower limit of the operable voltage range;, 'a communication controller connected via a power supply path to a voltage source that has a predetermined output voltage range, the communication controller having an operable voltage range, and being configured toa shutoff switch provided on the power supply path; anda capacitor connected to a point of the power supply path, the point being located between the shutoff switch and the communication controller, the capacitor being charged based on the voltage supplied from the voltage source while the shutoff switch is in an on state, the capacitor being configured to supply ...

Подробнее

Номер записи: 97

13-02-2020 дата публикации

Scheduling of read and write memory access requests

Номер: US20200050396A1

Автор: Shane J. Keil

Принадлежит: Apple Inc

A memory system includes a memory circuit including a plurality of pages, including a particular page having a page activation time. The memory system also includes a memory controller circuit configured to receive a memory access request corresponding to data of the particular page. The memory controller circuit is also configured to transmit, in response to a determination that the particular page is inactive, an activation command to the memory circuit to activate the particular page, and to schedule a future transmission of an initial memory command for the particular page based on the page activation time.

Подробнее

Номер записи: 98

14-02-2019 дата публикации

Semiconductor device

Номер: US20190051373A1

Автор: Young-Kyu NOH

Принадлежит: SK hynix Inc

A semiconductor device includes a fuse selection circuit suitable for generating fuse set address signals based on a clock signal; a fuse array including a plurality of fuse sets and suitable for sequentially outputting fuse set data from the fuse sets based on the fuse set address signals; a read circuit suitable for sequentially generating read set data based on the clock signal and the fuse set data; and a calculation circuit suitable for calculating a number of used or unused fuse sets among the fuse sets based on the clock signal and a fuse information signal which includes at least one fuse read signal among a plurality of fuse read signals included in the read set data.

Подробнее

Номер записи: 99

25-02-2021 дата публикации

Methods for providing device status in response to read commands directed to write-only mode register bits and memory devices and systems employing the same

Номер: US20210057003A1

Автор: Matthew A. Prather, Randall J. Rooney

Принадлежит: Micron Technology Inc

Memory devices, memory systems, and methods of operating the same are disclosed in which a memory device, in response to receiving a mode register read (MRR) command directed to one or more write-only bits of a mode register, reads data indicative of a status of the memory device about the memory device from one or more cells of a memory array of the memory device that are different from the write-only mode register. The data can include device settings, environmental conditions, usage statistics, metadata, feature support, feature implementation, device status, temperature, etc. The status information mode can be optionally enabled or disabled. The memory devices can include DDR5 DRAM memory devices.

Подробнее

Номер записи: 100

Настройки

Небесная энциклопедия

Мониторинг СМИ

Форма поиска