Umfangreiche Datenbusarchitektur

Hierarchische Spaltenleitungsauswahl für Multi-Bank-DRAM-Speicher und Verfahren dazu

Data output circuit for semiconductor component, has output driver unit to pass output driver event in response to output of level shifter circuit after maintaining data output connection in high impedance state

An output driver unit is provided for maintaining data output connection in high impedance state in response to high impedance driver data output by level shifter circuit. The output driver unit passes the output driver event in response to pull up and pull down output data signals (DOU,DOD) transferred by level shifter circuit to forward the final data (DQ) over data output connection (L5) to external. The output buffer receives and stores input data signal (DATAB) with predetermined voltage range in response to clock control signal (KDATA) to provide a pair of output data SIGNALS (DATAC,DATACB). The level shifter circuit passes high impedance control signal (HZ) through pair of output lines (L3,L4). The level shifter circuit receives pair of output data signals from output buffer depending on logical state of high impedance control signal and to transfer pull up and pull down data signals (DOU,DOD) through output lines (L3,L4). The voltage range of pull up and pull down output data signals ...

Halbleiteranordnung

Halbleiteranordnung mit: einem Abtastverstärker (44), welcher auf den Empfang eines Lesefreigabesignals ein Signal verstärkt; einer Verzögerungseinheit (52, 54), welche eine Mehrzahl von Übertragungspfaden mit unterschiedlichen Verzögerungszeiten bereitstellen kann und das Lesefreigabesignal durch einen Übertragungspfad entsprechend einem Wahlsignal aus der Mehrzahl von Übertragungspfaden überträgt; gekennzeichnet durch eine Befehlssignalerzeugungsschaltung (122, 124), welche der Verzögerungseinheit (52, 54) als Befehlssignal ein ODER-Ergebnis einer Verknüpfung eines vorbestimmten Maximalverzögerungsbefehlssignals, welches zum Zwecke der Aufnahme eines Übertragungspfads mit der maximalen Verzögerungszeit als Übertragungspfad für das Lesefreigabesignal ausgegeben wird, und eines willkürlichen Wahlsignals zuführt, welches zum Zwecke der Wahl eines willkürlichen Übertragungspfads als Übertragungspfad für das Lesefreigabesignal ausgegeben wird.

Schaltung zur Erzeugung eines Ausgangssignals in Abhängigkeit von zwei Eingangssignalen

Data inverting device, comprises complementary-metal-oxide-semiconductor circuit, two inverting units and control unit, which is provided to control two inverting units

The data inverting device (100) comprises a complementary-metal-oxide-semiconductor circuit (1) with an input (2) and an output (3). Two inverting units (4,5) are connected with the input and the output. A control unit (6) is provided to control two inverting units such that the data, which was inverted during its output from the latter inverting unit and the data, which was not inverted while inputting into the input from the former inverting unit were not inverted from latter inverting unit. An independent claim is also included for a method for data inversion.

Semiconductor device and semiconductor circuitry

A SEMICONDUCTOR INTERGRATED CIRCUIT MEMORY

Semiconductor device and data writing method

SYSTEMS, PROCEDURES AND DEVICES FOR THE TRANSMISSION OF DATA AND DATA MASK BIT IN A CONVENTIONAL FRAME WITH COMMON ERRONEOUS BIT CODE

Low latency multi-level communication interface

Static random access memory

Device for Controlling I/O Strobe Signal of Semiconductor Memory Apparatus

반도체 장치

... 반도체 장치는 디코더, 퓨즈 블록, 테스트 글로벌 라인 및 퓨즈 드라이버를 포함한다. 상기 디코더는 테스트 모드 시 리드 명령이 인가되면, 입력되는 어드레스를 디코딩하여 퓨즈 선택 신호를 생성한다. 상기 퓨즈 블록은 복수의 퓨즈를 포함하고, 상기 퓨즈 선택 신호에 따라 선택된 상기 퓨즈의 퓨즈 정보를 출력한다. 상기 테스트 글로벌 라인은 상기 퓨즈 블록으로부터 상기 퓨즈 정보를 전송한다. 상기 퓨즈 드라이버는 테스트 모드 시 상기 테스트 글로벌 라인으로 전송되는 상기 퓨즈 정보를 패드로 출력한다.

INPUT/OUTPUT DRIVER, ESPECIALLY SEPARATING AN OUTPUT DRIVER FROM A DQ PAD ELECTRICALLY

PURPOSE: An input/output driver is provided to reduce an input capacitance(Cin) of a DDR(Double Data Rate)-3 product effectively. CONSTITUTION: An input buffer(10) supplies input data supplied from a DQ pad(40) during a write mode to a memory cell array. An output driver(20) supplies output data supplied from the memory cell array during a read mode to the DQ pad. And a DQ switch(30) isolates the output driver electrically from the DQ pad during the write mode. The DQ switch is an NMOS transistor or a PMOS transistor. © KIPO 2005 ...

PAGE MODE ACCESS FOR A NON-VOLATILE MEMORY ARRAY, CAPABLE OF IMPROVING AN ACCESS SPEED THROUGH A PAGE MODE AND A VIDEO MODE ACCESS RATHER THAN BIT BY BIT ACCESS

PURPOSE: Page mode access for a non-volatile memory array is provided to read or write an array of non-volatile memory cells arranged in a plurality of logically vertical columns and a plurality of logically horizontal columns and at least one memory cell on the horizontal column in parallel. CONSTITUTION: A two-dimensional array(10) of non-volatile memory elements(12) has a plurality of vertical columns and at least one horizontal column, and each memory element can store at least one bit. A selection circuit(14) selects a plurality of memory elements in the horizontal column at the same time, and can continue to select a plurality of memory elements uninterrupted by refresh cycle. An access circuit accesses the memory elements selected at the same time in the horizontal column. © KIPO 2008 ...

DATA STROBE SIGNAL GENERATOR FOR SEMICONDUCTOR DEVICE

PURPOSE: A DQS(data strobe signal) generator of a semiconductor device is provided to output plural data in a single clock cycle. CONSTITUTION: A DQS generator(300) includes a preamble controller(302) to control the preamble state of a DQS. A pull up/down signal generator(304) receives first/second control signals for generating pull up/down signals. A DQS driver(308) outputs the DQS in response to the pull up/down signals. The preamble controller generates preamble control pulses by detecting the rising edge of DQS control signals. The pull up signal node of first pull up/down signal drivers(306a,316a,326a) and the pull down signal node of second pull up/down signal drivers(306b,316b,326b) are inputted to a pull up signal input terminal(402a) of the DQS driver. The pull down signal node of the first pull up/down signal driver and the pull up signal node of the second pull up/down signal drivers are inputted to a pull down signal input terminal(402b) of the DQS driver. COPYRIGHT 2000 KIPO ...

CIRCUIT AND METHOD FOR DATA TRANSMISSION AND A MEMORY DEVICE INCLUDING THE SAME, INCLUDING A PATTERN DECODING UNIT

PURPOSE: A circuit and method for data transmission and a memory device including the same are provided to reduce the instant maximum current of a data transmission circuit by preventing data transition in an A-B point and a B-C point. CONSTITUTION: In a circuit and method for data transmission and a memory device including the same, a first driver(210) drives data to a first line. A pattern change part(230) changes the pattern of data delivered to the first line. A second driver(220) drives data in which the pattern is changed to a second line. A pattern decoding module(240) decodes the pattern of data. COPYRIGHT KIPO 2012 ...

DATA INPUT AND OUTPUT CIRCUIT FOR INPUTTING AND OUTPUTTING DATA IN A READ OPERATION OR WRITE OPERATION AND A SEMICONDUCTOR MEMORY DEVICE

PURPOSE: A data input and output circuit and a semiconductor memory device are provided to minimize an area by using an amplification unit shared in a read operation and a write operation. CONSTITUTION: An amplification unit(21) generates a data signal by amplifying the data of a first input and output line connected to a bank in a read operation and generates a driving signal by amplifying the data of a second input and output line in a write operation. A read driving unit(22) drives a second input and output line in response to the data signal in the read operation. A write driving unit(23) drives the first input and output line in response to the driving signal in the write operation. COPYRIGHT KIPO 2013 [Reference numerals] (21) Amplification unit; (22) Read driving unit; (23) Write driving unit ...

Semiconductor memory device with less data transfer delay time

In a semiconductor memory device, a memory cell array has an even bank activated based on even numbered addresses and an odd bank activated based on odd numbered addresses. Even read data is outputted from the even bank in response to a first control signal, and odd read data is outputted from the odd bank in response to the first read control signal. A relaying unit receives the even read data on the first even data bus to output the even read data to the second even data bus in response to a second read control signal, and receives the odd read data on the first odd data bus to output the odd read data to the second odd data bus in response to the second read control signal. An I/O circuit receives the even read data from the second even data bus and the odd read data from the second odd data bus, and outputs one of the even read data and the odd read data to the common data bus and then outputs the other to the common data bus, in response to a third read control signal.

INTERNAL COMMAND GENERATION CIRCUIT

The internal command generation circuit includes a burst pulse generation unit and a pulse shifting unit. The burst pulse generation unit is configured to receive a command for a read or write operation, and generate a first burst pulse. The pulse shifting unit is configured to shift the first burst pulse and generate an internal command.

Semiconductor device including buffer circuit

A device includes a power supply line, an output terminal, a circuit configured to perform a logic operation on a first signal and a second signal to produce a third signal, first, second and third transistors. The first transistor is coupled between the power supply line and the output terminal and includes a control gate supplied with the third signal. The second and third transistors are coupled in series between the power supply line and the output terminal. The second transistor includes a control gate supplied with the first signal and the third transistor includes a control gate supplied with a fourth signal that is different from each of the first, second and third signals.

WRITEBACK AND REFRESH CIRCUITRY FOR DIRECT SENSED DRAM MACRO

A writeback and refresh circuit for a direct sense architecture memory wherein a plurality of primary sense amps are connected to a global data line and also to bitlines, each of which is coupled to an array of memory storage cells which are selected for write and read operations by a plurality of wordlines. A single secondary sense amp receives analog level data from the primary sense amps over the global data line, and includes a restore/writeback circuit which digitizes the data and then returns the digitized data over the global data line to the primary sense amp and back into the memory. A 2-cycle read/writeback operation is used for each memory read cycle, a first cycle read operation, and a second cycle writeback operation. The 2-cycle destructive read architecture eliminates the need for a cache and complex caching algorithms.

Integrated circuit device

The present invention includes a memory subsystem comprising at least two semiconductor devices, including at least one memory device, connected to a bus, where the bus includes a plurality of bus lines for carrying substantially all address, data and control information needed by said memory devices, where the control information includes device-select information and the bus has substantially fewer bus lines than the number of bits in a single address, and the bus carries device-select information without the need for separate device-select lines connected directly to individual devices. The present invention also includes a protocol for master and slave devices to communicate on the bus and for registers in each device to differentiate each device and allow bus requests to be directed to a single or to all devices. The present invention includes modifications to prior-art devices to allow them to implement the new features of this invention. In a preferred implementation, 8 bus data ...

System and method to synchronize signals in individual integrated circuit components

A synchronous output signal generated by an integrated circuit (IC) component is synchronized to an applied clock signal for each individual IC component. A variable feedback delay in the IC component is incrementally altered to alter the phase skew between the clock signal and the output signal. The relative phase order of the clock and output signals is monitored in the IC component. In response to detecting a swap in the relative phase order of the clock and output signals, the variable feedback delay ceases to be altered. In some embodiments, the IC component may be a SDRAM component.

Semiconductor device

A semiconductor device has a DLL circuit or the like for adjusting the phase of an external clock and producing an internal clock that lags behind by a given phase. The semiconductor device further includes a clock frequency judging unit for judging the frequency of a first clock on the basis of an indication signal indicating a delay value of the first clock in the DLL circuit or the like to output a control signal; and a clock selecting unit for selecting either one of the first clock and the second clock, in response to the control signal.

Controlling execution of additional function during a refresh operation in a semiconductor memory device

A semiconductor memory device includes a mode register, an additional function executer, and an additional function controller. The mode register activates an additional function control signal when a mode register set code indicates that an additional function is to be executed concurrently with a refresh operation. The additional function controller controls the additional function executer to carry out the additional function concurrently with the refresh operation when the additional function control signal is activated.

Semiconductor integrated circuit

In order to provide high speed and low power consumption, a semiconductor integrated circuit is constructed to utilize both CMOS elements and bipolar transistors. The bipolar transistors are used in the output portions to take advantage of their speed of operation to allow rapid charging and discharging of output lines. In the meantime, the principal operating portions of the circuit use CMOS elements of low power consumption. This arrangement is particularly advantageous in memory circuits.

Non-invasive uterine activity sensor

Uterine activity is sensed by passing light through the patient's abdominal wall and detecting the light reflected from abdominal tissues. The intensity of the reflected light varies with the state of contraction of the patient's uterus. The use of light for monitoring uterine activity avoids the problems of size, fixation, and measurement accuracy exhibited by the conventional tocodynamometer technique.

SEMICONDUCTOR INTEGRATED CIRCUIT HAVING DIFFERENTIAL SIGNAL TRANSMISSION STRUCTURE AND METHOD FOR DRIVING THE SAME

A semiconductor integrated circuit includes an input data line pair, a sense amplifier configured to sense and amplify data loaded in the input data line pair and transmit the amplified data to an output data line pair, in response to a control signal, and a sense amplification controller configured to sense an amplification level of the output data line pair, limit an activation period of a sense amplification enable signal, and output the limited signal as the control signal.

Address wrap function for addressable memory devices

The invention is a selectable function that permits the address portion of data words to be separated from the storable content portion and that address portion to be used for different purposes without disturbing the stored contents in the memory array. The invention may be viewed as a command capability that permits analysis of signals for errors in such items as addresses, impedance calibration, timing, and component drift that develop in and between regions of an overall memory array. Techniques are advanced involving data responsive selectable array circuitry modification for such operations as address correctness verification, machine timing and component drift correction purposes. The principles are illustrated with memory systems built of Synchronous Dynamic Random Access Memory with Double Data Rate (SDRAM-DDR) elements.

Data bus power-reduced semiconductor storage apparatus

In one or more of the disclosed embodiments, the number of times toggle operations of a data bus are performed at the time of a data transmission in a semiconductor storage apparatus is reduced, thereby reducing the power consumption. For example, a semiconductor storage apparatus according to one embodiment of the present invention comprises a DRF bus, a DR11F bus, a GDRF bus and a GDR11F bus. The DRF bus and DR11F bus, and the GDRF bus and GDR11F bus, are placed in parallel for the purpose of reducing the number of times toggle operations of a data bus are performed at the time of a data transmission. The DR11F bus is added to make the DRF11F bus perform a toggle operation only when the DRF buses on both sides are made to perform a toggle operation if the data transmission were performed in a conventional system.

CONTROL CIRCUIT OF READ OPERATION FOR SEMICONDUCTOR MEMORY APPARATUS

A control circuit for a read operation of a SERDES (SERializer and DESeriallizer) type semiconductor memory apparatus is disclosed that includes a first delay unit that is configured to generate and output a first delay signal to a first global input/output line driver by receiving a sensing-enable signal 'IOSTB', and to generate and output a second delay signal to a second global input/output line driver by receiving the sensing-enable signal. The first delay unit generates the second delay signal by delaying the sensing-enable signal in synchronization with a clock. The semiconductor memory apparatus also includes a second delay unit configured to generate a pipe latch control signal in response to the first delay signal and the second delay signal.

Method and apparatus for low capacitance, high output impedance driver

An apparatus is described having a feedback loop. The feedback loop has an output that approaches a steady state as a data line voltage approaches a reference voltage. The apparatus also includes a driving transistor that drives the data line. The driving transistor has an output impedance that is controlled by the feedback loop output, the feedback loop output keeps the driving transistor output impedance within a high output impedance region when the feedback loop output reaches the steady state.

Processing-in-memory (PIM) device

A PIM device includes a plurality of first storage regions, a second storage region, and a column control circuit. The second storage region is coupled to each of the plurality of first storage regions through a data transmission line. The column control circuit generates a memory read control signal for reading data stored in an initially selected storage region of the plurality of first storage regions and a buffer write control signal for writing the data read from the initially selected storage region to the second storage region. The column control circuit generates a global buffer read control signal for reading the data written to the second storage region and a memory write control signal for writing the data read from the second storage region to a subsequently selected storage region of the plurality of first storage regions.

MEMORY ARRAY WITH PROGRAMMABLE NUMBER OF FILTERS

Aspects of the present disclosure are directed to devices and methods for performing MAC operations using a memory array as a compute-in-memory (CIM) device that can enable higher computational throughput, higher performance and lower energy consumption compared to computation using a processor outside of a memory array. In some embodiments, an activation architecture is provided using a bit cell array arranged in rows and columns to store charges that represent a weight value in a weight matrix. A read word line (RWL) may be repurposed to provide the input activation value to bit cells within a row of bit cells, while a read-bit line (RBL) is configured to receive multiplication products from bit cells arranged in a column. Some embodiments provide multiple sub-arrays or tiles of bit cell arrays.

Systems and methods for dual standby modes in memory

The present disclosure is drawn to, among other things, a method for accessing memory using dual standby modes, the method including receiving a first standby mode indication selecting a first standby mode from a first standby mode or a second standby mode, configuring a read bias system to provide a read bias voltage and a write bias system to provide approximately no voltage, or any voltage outside the necessary range for write operation, based on the first standby mode, receiving a second standby mode indication selecting the second standby mode, and configuring the read bias system to provide at least the read bias voltage and the write bias system to provide a write bias voltage based on the second standby mode, the read bias voltage being lower than the write bias voltage.

MEMORY CIRCUITS

A circuit is provided. The circuit includes a first die that includes a memory array, and the memory array includes a plurality of memory cells, a sensing element coupled to the plurality of memory cells, and a first plurality of conductive pads coupled to the sensing element. The circuit also includes a second die that includes an address decoder associated with the memory array of the first die and a second plurality of conductive pads coupled to the address decoder. The first die is coupled to the second die by an interposer. The address decoder of the second die is coupled to the sensing element of the first die. A first voltage swing of the first die is larger than a second voltage swing of the second die.

SEMICONDUCTOR DEVICE

PROBLEM TO BE SOLVED: To provide a semiconductor device capable of operating at high speed and improving margin by securing sufficient amplitude for transmitting a signal from a sense amplifier to an amplifier circuit via a transmission circuit. SOLUTION: A semiconductor device of the present invention comprises a sense amplifier 20, a lead amplifier 21, a floating body type transistor QF, a local input output line LIO and a main input output line MIO that form a transmission circuit between them, transistors Q10, Q12, and Q14 serving as switches, and transistors Q11 and Q13 serving as pre-charge circuits. The transistor QF has a gate connected to an input node N1, and a control signal CF is applied to a source and a drain thereof. During the amplification operation of the lead amplifier 21, the control signal CF is controlled so as to transfer from a first voltage level that keeps the gate capacitance of the transistor QF low to a second voltage level that increases the gate capacitance ...

БИМОДАЛЬНЫЙ РЕЖИМ ФУНКЦИОНИРОВАНИЯ ФЕРРОЭЛЕКТРИЧЕСКИХ И ЭЛЕКТРЕТНЫХ ЯЧЕЕК ПАМЯТИ И ЗАПОМИНАЮЩИХ УСТРОЙСТВ НА ИХ ОСНОВЕ

... 1. Способ адресации к ферроэлектрической или электретной ячейке памяти, причем адресация включает операции считывания и операции записи или возвращения в исходное состояние, а при осуществлении начальной операции записи ячейку памяти устанавливают в первое или второе стабильное поляризационное состояние, которым приписывают соответствующие логические значения, после чего обеспечивают ячейке памяти возможность достичь состояния импринтинга, отличающийся тем, что на ячейку памяти подают один или более импульсов напряжения, параметры которого (которых), включая профиль, полярность и/или интегральное значение напряжения, выбирают из условия достижения релаксации состояния импринтинга, после чего осуществляют либо операцию считывания с получением сигнала, соответствующего логическому значению, представленному поляризационным состоянием ячейки, либо выполняют операцию записи путем подачи на ячейку памяти одного или более импульсов напряжения, параметры которого (которых), включая профиль, полярность ...

Ausgangspuffer

Vorrichtung und Verfahren zum Auslesen einer Speicherinformation

Eine Vorrichtung (100) zum Auslesen einer in einem Speicher (102) speicherbaren Speicherinformation weist eine Integrationseinrichtung (104) und eine Vergleichseinrichtung (106) auf. Der Speicher stellt in einer Haltephase einen Leckstrom und in einer Auslesephase einen Auslesestrom bereit. Der Auslesestrom ist abhängig von der gespeicherten Speicherinformation. Die Integrationseinrichtung (104) ist ausgebildet, um eine von dem Leckstrom hergeleitete Größe während der Haltephase aufzuintegrieren und eine einem aufintegrierten Leckstrom entsprechende Leckspannung bereitzustellen. Ferner ist die Integrationseinrichtung (104) ausgebildet, um eine von dem Auslesestrom hergeleitete Größe während der Auslesephase aufzuintegrieren und ein einem aufintegrierten Auslesestrom entsprechender Auslesespannung bereitzustellen. Die Vergleichseinrichtung (106) kann die Leckspannung mit der Auslesespannung vergleichen und abhängig von dem Vergleich einen Auslesewert bereitstellen, der der Speicherinformation ...

Verstärker mit verringertem Leistungsverbrauch

Eine Verstärkerschaltung mit verbesserter Schaltgeschwindigkeit und verringertem Leistungsverbrauch ist so konfiguriert, daß sie ein Eingangssignal von einem ersten Segment (140a) einer Signalleitung empfängt und das Signal in Reaktion auf ein aktives Steuersignal an ein zweites Segment (140b) der Signalleitung weiterleitet.

Eingang/Ausgang einer integrierten Schaltung mit einer Hochleistungsbusschnittstelle

Data output circuit and data output method

Semiconductor device

DEVICE OF DYNAMIC, AND PROCEEDED RANDOM ACCESS MEMORY OF READING CORRESPONDING

MEMORY CIRCUIT

SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD THEREOF

... 전원 IC나 각종 수동 소자를 모듈화해, 콘트롤러 전원 전압의 저전압화나 콘트롤러 및 NAND형 플래시 메모리의 복수 전원화에 대응한 반도체 기억 장치를 제공한다. 이면에 BGA 단자를 가지는 콘트롤러 패키지(110)과 각각 반도체 기억 소자를 복수 가지고, 콘트롤러 패키지 상에 탑재된, 하나 또는 복수의 메모리 패키지(120)과로부터 구성된 반도체 기억 장치(100)이다. 콘트롤러 패키지는, 이면에 BGA 단자를 가지는 기판과 바텀(Bottom) 기판 상에 탑재된 복수 전원을 공급하는 전원 IC와 바텀 기판 상에 탑재되어 전원 IC로부터 공급된 복수의 전원에 의해 동작해, BGA 단자를 통해 외부 시스템과의 인터페이스를 제공함과 동시에, 반도체 기억 소자에 대한 독출(Read) 및 서입(Write) 동작을 제어하는 콘트롤러를 포함한다.

semiconductor memory device having memory cell arrays capable of accomplishing random access

Data Output Apparatus and Method of Semiconductor Memory

DATA LINE DRIVING CIRCUIT

OUTPUT DRIVER FOR INITIALLY ENHANCING OUTPUT DATA WITH TIMING AND AN OUTPUT DRIVING METHOD, SPECIALLY IN CONNECTION WITH PREVIOUSLY COMPENSATING ATTENUATION OF TRANSMISSION DATA DURING DATA COMMUNICATION

PURPOSE: An output driver for initially enhancing output data with timing and an output driving method are provided to previously generate logical state transition of output data so that an effect like initial enhancement of data is generated, thus circuits for generating high voltages and low voltages are not required. CONSTITUTION: A select signal generator(110) generates a select signal in accordance with input data continuously having available data bits during consecutive bit sections. The select signal is in an active state at a transition time of the input data, which occurs after the same logical state is continued during more than a predetermined number of continuous bit sections. A reference data generator(130) delays the input data for a shorter delay time than the bit sections, and generates the delayed data as reference data. A selector(150) is driven to transit the logical state of the output data by responding to transition of one logical state of the reference data and the ...

DATA INPUT/OUTPUT APPARATUS OF MEMORY DEVICE CAPABLE OF REMOVING COUPLING NOISE GENERATED BETWEEN GLOBAL INPUT/OUTPUT LINES

PURPOSE: A data input/output apparatus of a memory device is provided to reduce fail of the memory device by removing coupling noise generated between global input/output lines as data input/output lines. CONSTITUTION: An input/output sense amplifier(10) is installed at each of banks of a memory device. A transceiver(20) is used for receiving a plurality of global input/output signals(GIO1 to GIOn) from the input/output sense amplifier, comparing the received global input/output signals with adjacent global input/output signals, converting the received global input/output signals to global input/output signals having the same polarity, and outputting the converted global input/output signals and control signals for conversion. A receiver(30) is used for receiving the converted global input/output signals and the control signals for conversion, recovering the global input/output signals by using the control signals for conversion, and outputting the recovered global input/output signals ...

SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE

PURPOSE: To provide a new semiconductor integrated circuit device equipped with a memory circuit, a high speed memory, and a mass storage memory circuit which enable speed-up and facilitate setup of timing. CONSTITUTION: In a read circuit of a memory cell in which a memory current is made to flow or not in accordance with a selection operation of a word line and storage information, gates are supplied to a plurality of bit lines connected by the above memory cells respectively. A first amplifier circuit includes a first MOSFET of a first conductive type which is maintained at off-state under a pre-charge voltage given to such bit lines and is made to an operation state corresponding to a selection signal of a bit line. A second amplifier circuit which includes a plurality of a second MOSFET of a second conductive type to which a plurality of such amplifier signals of the first amplifier circuit are supplied to each gate and connected in parallel mode, and forms amplifier signals corresponding ...

SEMICONDUCTOR MEMORY WITH EFFICIENT ARRANGEMENT

PURPOSE: A semiconductor memory device with an efficient arrangement is provided in which functional blocks are efficiently arranged in order to reduce the chip area. CONSTITUTION: A semiconductor memory device includes the first and second memory core blocks, a pipeline block(406) and an interface logic block(405). The first and second memory core blocks respectively include memory cell arrays(401,402,403,404) and control circuits for controlling the arrays. The pipeline block is arranged between the first and second memories core blocks and transceive data to/from the first or second memory core block in a pipeline manner through the first or second input/output lines. The interface logic block is arranged between the first and second memory core blocks and receives a command input from the outside to generate signals for controlling the first and second blocks. The first and second memory core blocks share input/output line sense amplifiers and input/output line drivers. The sense amplifiers ...

DELTA SIGMA SENSE AMPLIFIER COMPRISING DIGITAL FILTERS AND MEMORY

A memory device that, in certain embodiments, includes a memory element coupled to a bit-line and a quantizing circuit coupled to the memory element via the bit-line. In some embodiments, the quantizing circuit includes an analog-to-digital converter having an input and output and a digital filter that includes memory. The input of the analog-to-digital converter may be coupled to the bit-line, and the output of the analog-to-digital converter may be coupled to the digital filter. COPYRIGHT KIPO & WIPO 2010 ...

DATA VERIFICATION DEVICE

SEMICONDUCTOR STORAGE DEVICE

PURPOSE: To provide a semiconductor storage device in which a consumption current is reduced by changing the number of activation amplifiers in accordance with the number of pieces of input-output data. CONSTITUTION: This semiconductor storage device includes the number of pieces of data selection signal generation circuit for generating the number of pieces of data selection signal showing the number of set pieces of input-output data, a bit line for transferring read and write data of a memory cell, and a plurality of sense amplifiers which are connected to the bit line and are activated as much as the number corresponding to the number of pieces of data selection signal. © KIPO & JPO 2002 ...

Semiconductor device and memory system

According to one embodiment, in a first differential amplifier circuit of a semiconductor device, a first transistor receives an input signal at the gate. A second transistor forms a differential pair with the first transistor. The second transistor receives a reference signal at the gate. A third transistor is connected in series with the first transistor. A fourth transistor is connected in series with the second transistor. A fifth transistor is disposed on the output side. The fifth transistor forms a first current mirror circuit with the fourth transistor. A sixth transistor is connected to the drain of the second transistor in parallel with the fourth transistor. The sixth transistor forms a second current mirror circuit with the fifth transistor. A first discharge circuit is connected to the source of the sixth transistor.

Data output driver for reducing noise

A data input/output driver for use in a semiconductor memory device includes a data transmitting block for transmitting a data between an inside and an outside of the semiconductor memory device and generating a data driving signal in order to indicate a timing of outputting the data; a reference data generating block for generating a reference data; and a switching block for outputting the reference data in response to the data driving signal, wherein the data and the reference data are combined as an output signal.

INTEGRATED MEMORY WITH DE-ACTIVATABLE DATA OUTPUT

The invention relates to a dynamic memory in which changes in the bit address BADR are detected by an address change detection signal ATD. Its data output DOUT driven by a tristate driver T is de-activated as a function of the address change detection signal ATD when, at the same time as the activation thereof, a column address control signal CASN has a low level. In this way, there is no short circuiting of the supply potentials VCC, or earth of the driver T when two divergent data are read out in succession in extended data out mode.

Integrated circuit having memory which synchronously samples information with respect to external clock signals

A synchronous memory device having at least one memory section which includes a plurality of memory cells. The memory device includes clock receiver circuitry, clock generation circuitry and input receiver circuitry. The clock receiver circuitry receives an external clock signal from an external bus. The clock generation circuitry is coupled to the clock receiver circuitry, and includes a delay locked loop to generate a first internal clock signal. The input receiver circuitry is coupled to the clock generation circuitry and the external bus to sample information from the external bus in response to the first internal clock signal.

Memory devices with page buffer having dual registers and method of using the same

A nonvolatile memory device and programming method and apparatus therefore are described that include operatively coupled first and second sense amplifiers having first and second data registers or latches, a storage circuit for storing a data of the second amplifier, a pass/fail check circuit for checking the content of the second data register whether a cell of the memory device has been sufficiently programmed and a restore circuit for resetting the second data register for reprogramming the device until sufficiently programmed.

Data-output driver circuit and method

Digital calibration circuits, devices and systems including same, and methods of operation

A calibration circuit for matching the output impedance of a driver by calibrating adjustments to the driver is described. The calibration circuit includes a driver circuit with a plurality of calibration transistors configured to receive a plurality of adjustment signals. The calibration circuit also includes a comparator circuit, and a binary searcher. The driver provides a signal corresponding to an output impedance to the comparator circuit. The output impedance signal is compared to a target impedance, and the comparator circuit then provides logic signals to the binary searcher representing whether the output impedance is greater than the target impedance. The binary searcher then selects a type of step size and count direction, in response to the logic signals, to count the number of steps for adjusting the calibration transistors of the driver.

Integrated circuit data latch driver circuit

A synchronous memory device and system are described which communicates bi-directional data via a bus and data clock. To capture data from the bus, a memory device latch circuit is described which operates in response to internally generated clock signals. A pulse generator circuit is described which produces these internal clock signals, and insures accurate latching of data by minimizing signal skew between the internal clock signals to avoid wasting valuable timing. The pulse generator circuit has at least two propagation paths that are symmetrical and operate in response to clock signals which are 90 degrees out-of-phase. A second pulse generator circuit is described minimizes skew by having symmetrical clock paths and also corrects duty cycle error present on the data clock. This second circuit uses three clock signals which have relative phases of 0, 90 and 180 degrees.

High speed multiple memory interface I/O cell

An input/output (I/O) cell including one or more driver-capable segments and one or more on-die termination (ODT) capable segments. The I/O cell may be configured as an output driver in a first mode and Thevenin equivalent termination in a second mode.

METHOD AND APPARATUS FOR FILTERING OUTPUT DATA

Apparatus and methods for filtering spurious output transitions with an adaptive filtering circuit which tracks the memory architecture and form factors with a reduced speed penalty. The filtering is selectable by a fuse option.

Semiconductor memory device having hierarchical structure of data input/output line and precharge method thereof

A semiconductor memory device having a hierarchical structure of data input/output lines and a precharge method thereof. A precharge method in a semiconductor memory device having a hierarchical structure includes precharging the global input/output line pairs with half of a memory cell array voltage, and precharging the local input/output line pairs with the half of the memory cell array voltage.

CIRCUIT FOR MEASURING CURRENT IN A NAND FLASH MEMORY

A circuit measures current passing through a memory cell in a NAND flash memory. The circuit includes a decoder and an analog mixer. The decoder is configured to select at least one data line coupled to page buffers and column decoders in accordance with a controlling signal. The analog mixer is configured to output current passing through the selected data line, or to couple all of the data lines to a means for measuring current in accordance with a total current measurement controlling signal.

Serially sensing the output of multilevel cell arrays

In accordance with one embodiment, a serial sensing scheme may be utilized to sense the information stored on a multilevel cell. The more significant bit of the information in the cell may sense initially. The more significant bit information may be used to determine which of at least two reference levels to utilize to determine a less significant bit of the cell.

DATA SORTING CONTROL CIRCUIT AND MEMORY DEVICE INCLUDING THE SAME

A data sorting control circuit includes a phase detector suitable for detecting a phase of each of a first clock signal, a second clock signal, a third clock signal, and a fourth clock signal in response to a read command, an order determiner suitable for determining a data order as a first order or a second order based on a seed address and the detected phase of each of the clock signals, and an sorting control signal generator suitable for shifting the read command based on the first clock signal to the fourth clock signal to generate a first sorting control signal, a second sorting control signal, a third sorting control signal, and a fourth sorting control signal, and outputting the first sorting control signal to the fourth sorting control signal according to the first order or the second order.

Semiconductor memory

A semiconductor memory including a memory cell, a bit line pair connected to the memory cell, a data line pair connected to the bit line pair through a switching element capable of ON/OFF switching in response to a value of a column selection signal and a precharge circuit for controlling an initial potential common between the data line pair. The semiconductor memory comprises a precharge potential control circuit which applies, in a precharge period, a low apply voltage not higher than a first predetermined potential to the data line pair when the initial potential of the data line pair is higher than the first predetermined potential, a high apply voltage not lower than a second predetermined potential to the data line pair when the potential of the data line pair is lower than the second predetermined potential or no voltage when the potential of the data line pair is not higher than the first predetermined potential and not lower than the second predetermined potential.

Memory data path circuit

A memory device with a data path circuit having support in the sense-amp region for compression testing of the device. The data path circuit uses NOR logic compression to provide a scalable design which may be extended to large circuits.

Data flow scheme for low power DRAM

Circuits and methods to minimize power required for sensing and precharge of DRAMs have been achieved. A control circuit ensures that during READ operations the duration of sensing of DRAM cell and precharging is kept to a minimum. A test DRAM cell is used to determine the exact time required for data sensing. Furthermore no precharging is performed during WRITE-operations. In case data is changing from 1 to 0 or vice versa data lines are inverted accordingly during WRITE operation.

Data input/output multiplexer of semiconductor device

There is provided an input/output multiplexer capable of reducing a layout area in designing a device by disposing first and second multiplexers at either side of a specific data input/output (I/O) pad. An apparatus for multiplexing data inputted or outputted to a global input/output (I/O) line includes a first multiplexer for multiplexing the data and supplying a first multiplexed data to the global I/O line and a second multiplexer for multiplexing the first multiplexed data supplied to the global I/O line, wherein the first and second multiplexers are formed at either side of the global I/O line.

Data output circuit of synchronous memory device

A data output circuit of a synchronous memory device including a plurality of pipelatches having an N bits prefetch function. Each pipelatch comprises a data switching section for switching an output path of N bits data; a first data selection section for receiving one half of the N bits data and outputting the one half in response to a first control signal; a second data selection section for receiving the other half of the N bits data and outputting the other half in response to the first control signal; a first shifter for outputting a second control signal delayed by a first time after receiving the first control signal; and a second shifter for receiving the data outputted from the second data selection section and outputting the data with a delay of the first time in response to the second control signal.

Semiconductor memory device having improved data output circuit

A data out circuit of a DRAM includes a normal operation determining part receiving a RASB (row address strobe bar) and a CASB (column address strobe bar) to determine whether a normal operation or an abnormal operation to be performed, a write/read determining part determining whether a read operation or a write operation to be performed, a first delaying part generating an OEC (out enable control) signal to delay a DOE (data output enable) generation signal, a controlling part outputting an EQSWB (equalizer switch bar) to control the DOE to transit only a first transit of the CASB, and a switching part receiving signals from the first delaying part and the controlling part, and switching the DOE, and a DOE generating part receiving signals from the normal operation recognizing part and the write/read determining part, and the switching part to generate the DOE signal outputting only a valid data.

Method of operating a synchronous memory device having a variable data output length

The present invention is directed to a method of operating a memory device wherein the memory device includes a plurality of memory cells. The method comprises providing first block size information to the memory device, wherein the first block size information defines a first amount of data to be output onto a bus in response to a read request. The method further includes issuing a first read request to the memory device, wherein in response to the first read request, the memory device outputs the first amount of data corresponding to the first block size information onto the bus synchronously with respect to a first external clock signal and a second external clock signal. In one preferred embodiment, the method may further include providing a code which is representative of a number of clock cycles of the first and second external clock which are to transpire before data is output by the memory device onto the bus. The memory device stores the code in a programmable register on the memory ...

Semiconductor IC device and data output method of the same

A semiconductor IC device includes a core strobe signal generator configured to latch a read command signal according to an internal clock signal to generate a core strobe signal, a core block configured to output data stored in a memory cell in response to the core strobe signal, a data output unit configured to latch data output from the core block according to a plurality of control signals and output the latched data in a predetermined order, and a controller configured to generate the plurality of control signals by using both the core strobe signal and the internal clock signal.

SEMICONDUCTOR DEVICES

A semiconductor device includes a synthesis signal generation circuit, a column control circuit, and a control signal generation circuit. The synthesis signal generation circuit generates a register synthesis signal in response to first and second read pulses sequentially generated during a read operation. The column control circuit generates any one of a first bank selection signal and a second bank selection signal for respectively selecting a first bank group and a second bank group included in a core circuit in response to the first and second read pulses. The control signal generation circuit generates a control signal for controlling an output operation of a mode register in response to the register synthesis signal. 1. A semiconductor device comprising:a synthesis signal generation circuit configured to generate a register synthesis signal in response to a first read pulse and a second read pulse which are sequentially generated during a read operation;a column control circuit configured to generate any one of a first bank selection signal and a second bank selection signal for respectively selecting a first bank group and a second bank group of a core circuit in response to the first read pulse and the second read pulse; anda control signal generation circuit configured to generate a control signal for controlling an output operation of a mode register in response to the register synthesis signal.2. The semiconductor device of claim 1 ,wherein the first and second bank selection signals are transmitted through a first memory input/output (I/O) line and a second memory I/O line, respectively;wherein the control signal is transmitted through a register I/O line; andwherein a length of the first and second memory I/O lines is greater than a length of the register I/O line.3. The semiconductor device of claim 1 ,wherein each of the first and second bank selection signals includes a pulse having a first pulse width;wherein the control signal includes a pulse ...

SEMICONDUCTOR STORAGE DEVICE AND METHOD FOR PRODUCING THE SAME

A semiconductor storage device 100 includes a controller package 110 having a BGA terminal on a bottom surface thereof; and one or a plurality of memory packages 120 each including a plurality of semiconductor storage elements and mounted on the controller package. The controller package includes a bottom substrate having the BGA terminal on a bottom surface thereof; a power supply IC, mounted on the bottom substrate, for supplying a plurality of power supplies; and a controller mounted on the bottom substrate and operable by the plurality of power supplies supplied from the power supply IC. The controller provides an interface with an external system via the BGA terminal and controls a read operation from the semiconductor storage elements and a write operation to the semiconductor storage elements.

VERIFYING A DATA PATH IN A SEMICONDUCTOR APPARATUS

A semiconductor apparatus includes a memory array configured to store write data transmitted through data transmission lines and transmit stored data to the data transmission line as read data; a data write unit configured to drive the write data to the data transmission lines in response to a data write command; and a data read unit configured to sense the read data transmitted through the data transmission lines in response to a data read command when a data verification signal is deactivated and sense the write data transmitted through the data transmission lines in response to the data write command when the data verification signal is activated.

Semiconductor memory device for high speed data access

A semiconductor memory device having a high speed for a data transmission includes a plurality of cell blocks, each having a plurality of unit cells for storing data; a plurality of local bit line sense amplifying block, each for sensing and amplifying the data stored in the N number of cell blocks; a global bit line sense amplifying block for latching the data amplified by the local bit line sense amplifying blocks; and a data transferring block for transmitting the data from the local bit line sense amplifying block to the global bit line sense amplifying block.

Read-write conversion circuit, read-write conversion circuit driving method, and memory

A read-write conversion circuit, a read-write conversion circuit driving method, and a memory are provided. The read-write conversion circuit includes a first precharge circuit, a positive feedback circuit, a second precharge circuit, a fourth switch unit, a sixth switch unit, a seventh switch unit, an eighth switch unit, a tenth switch unit, an eleventh switch unit, a twelfth switch unit, a thirteenth switch unit, a fourteenth switch unit, and a fifteenth switch unit. In the read-write conversion circuit, corresponding signals can be read from a third signal terminal and a fourth signal terminal by using only one of a first signal terminal or a second signal terminal in a signal read stage, and corresponding signals can be written to the first signal terminal and the second signal terminal by using only one of the third signal terminal or the fourth signal terminal in a signal write stage.

CHANNEL AND SUB-CHANNEL THROTTLING FOR MEMORY CONTROLLERS

An arbiter is operable to pick commands from a command queue for dispatch to a memory. The arbiter includes a traffic throttle circuit for mitigating excess power usage increases in coordination with one or more additional arbiters. The traffic throttle circuit includes a monitoring circuit and a throttle circuit. The monitoring circuit is for measuring a number of read and write commands picked by the arbiter and the one or more additional arbiters over a first predetermined period of time. The throttle circuit, responsive to a low activity state, limits a number of read and write commands issued by the arbiter during a second predetermined period of time.

Signal generator for controlling timing of signal in memory device

A device includes a memory array, bit line pairs, word lines, a modulation circuit and a control signal generator. The memory array has bit cells arranged in rows and columns. Each bit line pair is connected to a respective column of bit cells. Each word line is connected to a respective row of bit cells. The modulation circuit is coupled with at least one bit line pair. The control signal generator is coupled with the modulation circuit. The control signal generator includes a tracking wiring with a tracking length positively correlated with a depth distance of the word lines. The control signal generator is configured to produce a control signal, switching to a first voltage level for a first time duration in reference with the tracking length, for controlling the modulation circuit. A method of controlling aforesaid device is also disclosed.

Dynamic sensing levels for nonvolatile memory devices

Systems, methods, and devices dynamically determine sensing levels for memory devices. Devices include nonvolatile memory cells included in a plurality of memory sectors, a plurality of static reference cells configured to represent a first reference value for distinguishing between memory states, and a plurality of dynamic reference cells configured to represent the first reference value after a designated amount of memory sector activity. Devices also include a comparator configured to be coupled to at least one memory cell of the plurality of memory cells and to at least two of the plurality of static reference cells and the plurality of dynamic reference cells, and further configured to determine a memory state of the at least one memory cell based, at least in part, on a second reference value determined by a combination of at least two of the plurality of static reference cells and the plurality of dynamic reference cells.

SEMICONDUCTOR STORAGE DEVICE

A semiconductor storage device includes a first cell array including a plurality of memory cells that are connected to a first word line and each of which is connected to each member of a first pair of bit lines. The semiconductor storage device also includes a second cell array including a plurality of memory cells that are connected to a second word line and each of which is connected to each member of a second pair of bit lines. The semiconductor storage device further includes a redundant cell array including a plurality of memory cells that are connected to a word line different from the first and the second word lines and each of which is connected to one member of the first pair of bit lines and to one member of the second pair of bit lines.

Output stage for a memory device and for low voltage applications

Digital transmission with controlled rise and fall times

The invention addresses the reduction of common mode signals by mean of switched capacitor circuitry.

SEMICONDUCTOR STORAGE DEVICE

PURPOSE: To provide the semiconductor storage device which allows the changeover of constitution and high-speed reading out even after completion of production. CONSTITUTION: The data read out of a memory cell 70 of this semiconductor memory device is amplified by a local sense amplifier 21 of a current output type and is then transmitted via corresponding data busses 77 to plural main sense amplifiers 138. The respective main sense amplifiers 138 are connected to the corresponding reading out data busses 77 via clamp transistors for maintaining the potentials of the reading out data busses 77 always at the specified potential. This semiconductor memory device has the changeover control means for selectively changing over the plural main sense amplifiers 138 by controlling the control potentials of the respective clamp TRs. COPYRIGHT: (C)1992,JPO&Japio ...

Data paths using a first signal to capture data and a second signal to output data and methods for providing data

Data paths, memories, and methods for providing data from memory are disclosed. An example read data path includes a delay path, and a clocked data register. The data path has a data propagation delay and is configured to receive data and propagate the data therethrough. The delay path is configured to receive a clock signal and provide a delayed clock signal having a delay relative to the clock signal that models the data propagation delay. The clocked data register is configured to clock in data responsive at least in part to the delayed clock signal. The clocked data register is further configured to clock out data responsive at least in part to the clock signal.

Advanced memory device having improved performance, reduced power and increased reliability

An advanced memory having improved performance, reduced power and increased reliability. A memory device includes a memory array, a receiver for receiving a command and associated data, error control coding circuitry for performing error control checking on the received command, and data masking circuitry for preventing the associated data from being written to the memory array in response to the error control coding circuitry detecting an error in the received command. Another memory device includes a programmable preamble. Another memory device includes a fast exit self-refresh mode. Another memory device includes auto refresh function that is controlled by the characteristic device. Another memory device includes an auto refresh function that is controlled by a characteristic of the memory device.

High speed multiple memory interface i/o cell

A calibration circuit includes an amplifier, a current steering digital-to-analog converter (DAC), a comparator, a slew calibration network, and an on-die termination (ODT) network. The amplifier generally has a first input, a second input, and an output. The first input generally receives a reference signal. The current steering digital-to-analog converter (DAC) generally has a first input coupled to the output of the amplifier, a first output coupled to the second input of the amplifier, and a second output coupled to a circuit node. The comparator generally has a first input receiving the reference signal, a second input coupled to the circuit node, and an output at which an output of the calibration circuit may be presented. The slew calibration network is generally coupled to the circuit node and configured to adjust a slew rate of the calibration circuit. The on-die termination (ODT) network is generally coupled to the circuit node.

MEMORY DEVICE AND METHOD OF OPERATING THE SAME

The present technology relates to a memory device that generates various signals used in a read training operation and a method of operating the memory device. The memory device according to an embodiment of the present disclosure includes an address counter configured to generate a plurality of count signals based on a read training enable signal and a first clock signal received from a memory controller, and an address section identification signal generator configured to generate address section identification signals used in identifying a plurality of address sections based on at least one of the plurality of count signals. 1. A memory device comprising:an address counter configured to generate a plurality of count signals based on a read training enable signal and a first clock signal received from a memory controller; andan address section identification signal generator configured to generate address section identification signals used in identifying a plurality of address sections based on at least one of the plurality of count signals.2. The memory device of claim 1 , further comprising:a delayed signal generator configured to delay an address latch enable signal received from the memory controller to generate the read training enable signal.3. The memory device of claim 1 , wherein the address counter comprises:a counter clock generator configured to generate a second clock signal based on the read training enable signal and the first clock signal; anda counter configured to generate the count signals based on the second clock signal.4. The memory device of claim 3 , wherein the counter signals include:first count signals for counting a number of the address sections; andsecond count signals that are inverted signals of the first count signals.5. The memory device of claim 4 , wherein the counter comprises:a first count signal generator configured to generate a lower bit count signal corresponding to a lower bit among the first count signals; anda second ...

SEMICONDUCTOR MODULES

A semiconductor module may include a host, a first semiconductor device, and a second semiconductor device. The first host line may be connected to the first and second semiconductor device or devices, according to a set mode. 1. A semiconductor module comprising:a host configured to include a first host line and a second host line;a first semiconductor device configured to include a first channel and a second channel; anda second semiconductor device configured to include a third channel and a fourth channel,wherein the first host line is connected to the first and third channels or to the first and second channels according to a set mode, andwherein the second host line is connected to the second and fourth channels or to the third and fourth channels according to the set mode.2. The semiconductor module of claim 1 ,wherein if the set mode is a first set mode, the first host line is connected to the first and third channels to receive or output a first signal and the second host line is connected to the second and fourth channels to receive or output a second signal.3. The semiconductor module of claim 1 ,wherein if the set mode is a second set mode, the first host line is connected to the first and second channels to receive or output a first signal and the second host line is connected to the third and fourth channels to receive or output a second signal.4. The semiconductor module of claim 1 , wherein if the set mode is a third set mode claim 1 , the first host line is connected to the first and second channels to receive or output a first signal and the second host line is connected to the third and fourth channels to receive or output a second signal after the first host line is connected to the first channel to receive or output the first signal and the second host line is connected to the second channel to receive or output the second signal.5. The semiconductor module of claim 4 , wherein the third set mode is set to correspond to a case that an operation ...

SENSE AMPLIFIER, MEMORY AND METHOD FOR CONTROLLING SENSE AMPLIFIER

The disclosure provides a Sense Amplifier (SA), a memory and a method for controlling the SA, and relates to the technical field of semiconductor memories. The SA includes: an amplifier module; an offset voltage storage unit electrically connected to the amplifier module and configured to store an offset voltage of the amplifier module in an offset elimination stage of the SA; and a load compensation unit electrically connected to the amplifier module and configured to compensate a difference between loads of the amplifier module in an amplification stage of the SA. The disclosure may improve an accuracy of reading data of the SA. 1. A Sense Amplifier (SA) , comprising:an amplifier circuit;an offset voltage storage circuit electrically connected to the amplifier circuit, and configured to store an offset voltage of the amplifier circuit in an offset elimination stage of the SA; anda load compensation circuit electrically connected to the amplifier circuit, and configured to compensate a difference between loads of the amplifier circuit in an amplification stage of the SA.2. The SA of claim 1 , wherein the amplifier circuit comprises:a first P-channel Metal Oxide Semiconductor (PMOS) transistor;a second PMOS transistor, a source of the second PMOS transistor being connected to a source of the first PMOS transistor;a first N-channel Metal Oxide Semiconductor (NMOS) transistor, a drain of the first NMOS transistor being connected to a drain of the first PMOS transistor and a first end of the offset voltage storage circuit, and a gate of the first NMOS transistor being connected to a gate of the first PMOS transistor; anda second NMOS transistor, a drain of the second NMOS transistor being connected to a drain of the second PMOS transistor, a source of the second NMOS transistor being connected to a source of the first NMOS transistor, and a gate of the second NMOS transistor being connected to a second end of the offset voltage storage circuit,wherein in the offset ...

CONTROLLER, MEMORY SYSTEM, AND OPERATING METHODS THEREOF

A memory system includes a nonvolatile memory device and a controller configured to control the nonvolatile memory device. The nonvolatile memory device includes a first data storage region in which a memory cell stores one-bit data in a first mode and a second data storage region in which a memory cell stores two-bit or more data in a second mode. The controller controls the nonvolatile memory device to perform a read operation on the first data storage region and the second data storage region in the second mode. The controller decodes first data read from the first data storage region, and decodes second data read from the second data storage region. The controller controls the nonvolatile memory device to perform the read operation on the first data storage region in the second mode. 1. A memory system comprising:a nonvolatile memory device; anda controller configured to control the nonvolatile memory device,wherein the nonvolatile memory device includes a first data storage region in which a memory cell stores one-bit data in a first mode and a second data storage region in which a memory cell stores two-bit or more data in a second mode,the controller controls the nonvolatile memory device to perform a read operation on the first data storage region and the second data storage region in the second mode,the controller decodes, as data of the first mode, first data read from the first data storage region through the read operation,the controller decodes, as data of the second mode, second data read from the second data storage region through the read operation, andthe controller controls the nonvolatile memory device to perform the read operation on the first data storage region in the second mode by changing any one of a plurality of read voltages for reading the data of the second mode to a read voltage value for reading the data of the first mode.2. The memory system of claim 1 ,wherein the controller receives and queues a first read command for the first ...

INPUT/OUTPUT LINE SHARING FOR MEMORY ARRAYS

Methods, systems, and devices for input/output line sharing for memory subarrays are described. I/O lines may be shared across subarrays, which may correspond to separate memory tiles. The sharing of I/O lines may allow an I/O line to carry data from one subarray in response to access commands associated with one address range, and to carry data from another subarray in response to access commands associated with another address range. In some cases, sense amplifiers and other components may also be shared across subarrays, including across subarrays in different banks. The sharing of I/O lines may, in some cases, support activating only a subset of subarrays in a bank when accessing data stored in the bank, which may provide power savings. 1. A method , comprising:receiving, at a memory device comprising a first subarray and a second subarray, an access command associated with data for the first subarray;activating, based at least in part on receiving the access command, a first sense component coupled with the first subarray and a second sense component coupled with the first subarray;coupling, based at least in part on receiving the access command, the first sense component with a first input/output (I/O) line that at least partially traverses the first subarray of the memory device and the second sense component with a second I/O line that at least partially traverses the second subarray of the memory device; andreceiving or transmitting the data for the first subarray based at least in part on coupling the first sense component with the first I/O line and the second sense component with the second I/O line.2. The method of claim 1 , further comprising:activating a first driver coupled with the first I/O line, wherein coupling the first sense component with the first I/O line is based at least in part on activating the first driver; andactivating a second driver coupled with the second I/O line, wherein coupling the second sense component with the second I/O ...

OUTPUT DRIVER FOR MULTI-LEVEL SIGNALING

A driver of a multi-level signaling interface is provided. The driver may be configured reduce noise in a multi-level signal (e.g., a pulse amplitude modulation signal) generated by the driver using switching components of different polarities. The driver may include a pull-up circuit and/or a pull-down circuit. The pull-up circuit and the pull-down circuit may include at least one switching component of a first polarity (e.g., nmos transistor) and at least one switching component of a second polarity different from the first polarity (e.g., pmos transistor). Such a configuration of pull-up and pull down circuits may generate a more linear relationship between an output current and an output voltage of an output of the driver, thereby improving one or more characteristics of the multi-level signal. 1. (canceled)2. A method , comprising:identifying a plurality of information bits to be read from an array of memory cells;generating a multi-level signal modulated using a first modulation scheme having at least three levels based at least in part on the plurality of information bits using a driver having a pull-up circuit including a first switching component having a first gate polarity and a second switching component having a second gate polarity different than the first gate polarity; andtransmitting the multi-level signal to a controller of a memory device.3. The method of claim 2 , wherein generating the multi-level signal further comprises:activating the first switching component during a first time period; andactivating the second switching component during a second time period that overlaps with the first time period.4. The method of claim 2 , wherein the driver includes a pull-down circuit including a third switching component having the first gate polarity and a fourth switching component having the second gate polarity.5. The method of claim 4 , wherein generating the multi-level signal further comprises:activating the third switching component during a ...

BOOST BYPASS CIRCUITRY IN A MEMORY STORAGE DEVICE

The present disclosure describes various exemplary memory storage devices that can be programmed to bypass one or more memory cells in a bypass mode of operation. The various exemplary memory storage devices can adjust, for example, pull-up or pull-down, the electronic data as the electronic data passes through these exemplary memory storage devices in the bypass mode of operation. In some situations, the various exemplary memory storage devices may introduce an unwanted bias into the electronic data as the electronic data passes through these exemplary memory storage devices in the bypass mode of operation. The various exemplary memory storage devices can pull-down the electronic data and/or pull-up the electronic data as the electronic data is passing through these exemplary memory storage devices in the bypass mode of operation to compensate for this unwanted bias. 1. A memory storage device , comprising:a memory cell coupled to a bitline;a write driver configured to provide an input data bit to the bitline;switch circuitry configured to electrically couple the bitline to a data line to pass the input data bit from the bitline to the data line;boost circuitry configured to adjust a potential of the input data bit on the data line to be a potential of the input data bit on the bitline; anda sense amplifier configured to read the input data bit from the data line to provide an output data bit.2. The memory storage device of claim 1 , wherein the boost circuitry is configured to pull-down a voltage of the input data bit on the data line to be a voltage of the input data bit on the bitline.3. The memory storage device of claim 1 , wherein the boost circuitry is configured to pull-up a voltage of the input data bit on the data line to be a voltage of the input data bit on the bitline.4. The memory storage device of claim 1 , wherein the memory storage device is configured to operate in a read mode of operation claim 1 ,wherein the switch circuitry is configured to ...

MEMORY WITH HIGH-SPEED AND AREA-EFFICIENT READ PATH

A read path for a memory is provided that includes an integrated sense mixing and redundancy shift stage coupled between a sense amplifier and a data latch. The data latch is integrated with a level shifter. 1. A read path for a memory , comprising:a sense amplifier configured to sense a bit decision signal responsive to a read operation; anda level-shifting data latch configured to latch the bit decision signal to form a latched bit decision signal and to level shift the latched bit decision signal from a memory domain power supply voltage to an external domain power supply voltage.2. The read path of claim 1 , further comprising an output data driver configured to drive the latched bit decision signal from the memory.3. The read path of claim 1 , further comprising;a first transistor coupled between an output node of the sense amplifier and an input node to the level-shifting data latch; anda first logic gate configured to assert a combined sense enable and redundancy shift-off signal in response to an assertion of both a sense enable signal and a redundancy shift-off signal, wherein the first transistor is configured to switch on in response to the assertion of the combined sense enable and redundancy shift-off signal to conduct the bit decision signal from the sense amplifier to the integrated data latch and level shifter.4. The read path of claim 3 , wherein the first logic gate comprises a NOR gate. The present application is a divisional application of U.S. Non-Provisional patent application Ser. No. 16/421,365, filed May 23, 2019, which is hereby incorporated by reference in its entirety.This application relates to memories, and more particularly to an improved memory read path.In a conventional memory such as a static random-access memory (SRAM), a sense amplifier makes a bit decision for an accessed bitcell during a read operation. But the output of the sense amplifier is only valid during a sense enable period, so the sense amplifier typically drives a ...

Processing-in-memory (pim) devices

A processing-in-memory (PIM) device includes first to Lth multiplication/accumulation (MAC) operators, first to Lth memory banks, and a plurality of data input/output (I/O) circuits. The first to Lth MAC operators include first to Lth left MAC operators and first to Lth right MAC operators. The plurality of data I/O circuits include left data I/O circuits and right data I/O circuits. A Uth MAC operator among the first to Lth MAC operators is configured to output one of the first to Mth MAC result data through a Uth left MAC operator among the first to Lth left MAC operators or a Uth right MAC operator among the first to Lth right MAC operators. The PIM device is configured to output the MAC result data outputted through the left MAC operators through the left data I/O circuits, and output the MAC result data outputted through the right MAC operators through the right data I/O circuits.

DRAM INTERFACE MODE WITH IMPROVED CHANNEL INTEGRITY AND EFFICIENCY AT HIGH SIGNALING RATES

An IC memory controller includes a first controller command/address (C/A) interface to transmit first and second read commands for first and second read data to a first memory C/A interface of a first bank group of memory. A second command/address (C/A) interface transmits third and fourth read commands for third and fourth read data to a second memory C/A interface of a second bank group of memory. For a first operating mode, the first and second read data are received after respective first delays following transmission of the first and second read commands and at a first serialization ratio. For a second operating mode, the first and second read data are received after respective second and third delays following transmission of the first and second read commands. The second and third delays are different from the first delays and from each other. The first and second data are received at a second serialization ratio that is different than the first serialization ratio. 1. An integrated circuit (IC) memory controller , comprising:a first command/address (C/A) interface to transmit, to a first memory C/A interface of a first bank group of memory, first and second read commands for first and second read data;a second command/address (C/A) interface to transmit, to a second memory C/A interface of a second bank group of memory, third and fourth read commands for third and fourth read data;receiver circuitry to receive the first and second read data via a first data link interface and to receive the third and fourth read data via the second data link interface, the third and fourth read data received in a pipelined fashion with respect to the first and second read data;wherein for a first operating mode, the first and second read data are received after respective first delays following transmission of the first and second read commands and wherein the first and second data are received at a first serialization ratio; andwherein for a second operating mode, the first ...

FIRST IN FIRST OUT MEMORY AND MEMORY DEVICE

A First In First Out (FIFO) memory includes storage units. Outputs of the storage units are connected to one node. The storage unit includes storage sub-units, a selector, and a drive. An input of the selector is connected to outputs of the storage sub-units. An input of the drive is connected to an output of the selector. Driven by a first pointer signal, the storage sub-units receive storage data. Driven by a second pointer signal, the drive outputs the storage data. 1. A First In First Out (FIFO) memory , comprising:storage units, outputs of the storage units being connected to one node;a storage unit of the storage units comprising storage sub-units, a selector, and a drive; an input of the selector being connected to outputs of the storage sub-units; an input of the drive being connected to an output of the selector; driven by a first pointer signal, the storage sub-units receiving storage data; driven by a second pointer signal, the drive outputting the storage data.2. The FIFO memory of claim 1 , wherein data inputs of the storage sub-units are connected to one data signal line.3. The FIFO memory of claim 1 , wherein a control terminal of the selector is connected to one selecting clock line.4. The FIFO memory of claim 1 , wherein the first pointer signal is generated by a first counter circuit claim 1 , the second pointer signal is generated by a second counter circuit claim 1 , and a drive clock rate of the first counter circuit and a drive clock rate of the second counter circuit are identical.5. The FIFO memory of claim 4 , wherein a counting cycle number of the first counter circuit and a counting cycle number of the second counter circuit are identical.6. The FIFO memory of claim 5 , wherein the first counter circuit comprises a first counter and a first pointer signal generator claim 5 ,wherein the first counter is configured to count clock cycles of a reference clock signal, the counting cycle number of the first counter being equal to a total number ...

STACK ACCESS CONTROL FOR MEMORY DEVICE

Apparatuses and methods including an interface die that interfaces with dice through memory channels are described. An example apparatus includes a first die. The first die receives a first command including first command information and second command information provided after the first command information. The first die changes an order of providing the first command information and the second command information and provides a second command to a second die, the second command including the second command information and the first command information provided after the second command information in the changed order. The first command information is related to a command function and the second command information is related to a destination of the command function. 1. An apparatus comprising:at least one stack group corresponding, respectively, to at least one stack identifier; anda first die including a command circuit configured to receive command information including one stack identifier of the at least one stack identifier in relation to a falling edge of a first clock signal, the command circuit further configured to provide the command information including the one stack identifier in relation to a rising edge of a second clock signal.2. The apparatus of claim 1 , wherein claim 1 , before receiving the command information claim 1 , the first die is configured to receive other command information claim 1 , andwherein the first die is further configured to provide the other command information in relation to a falling edge of the second clock signal.3. The apparatus of claim 1 , wherein the first die is configured to receive other command information in relation to a rising edge of the first clock signal.4. The apparatus of claim 1 , wherein claim 1 , before receiving the command information claim 1 , the first die is configured to receive other command information claim 1 , andwherein, after providing the command information, the first die is configured to ...

Semiconductor devices

A semiconductor device includes a synthesis control signal generation circuit and a data output control circuit. The synthesis control signal generation circuit generates a synthesis control signal for determining a burst sequence from a latch control signal in response to a first burst mode command and a second burst mode command. The data output control circuit outputs data included in a bank group as internal data in response to the synthesis control signal.

TIMING BASED ARBITRATION METHODS AND APPARATUSES FOR CALIBRATING IMPEDANCES OF A SEMICONDUCTOR DEVICE

Systems and apparatuses are provided for an arbiter circuit for timing based ZQ calibration. An example system includes a resistor and a plurality of chips. Each of the plurality of chips further includes a terminal coupled to the resistor and a calibration circuit. The calibration circuit determines whether the resistor is available based, at least in part, on timing information that is unique to a corresponding chip of the plurality of chip. The timing information of each chip of the plurality of chips has a fixed duration of time common to the plurality of chips. 1. A system comprising:a resistor; and a terminal coupled to the resistor; and', 'a calibration circuit configured to determine whether the resistor is available based, at least in part, on timing information unique to a corresponding chip., 'a plurality of chips, each chip of the plurality of chips including2. The system of claim 1 , wherein the timing information of each chip of the plurality of chips has a fixed duration of time common to the plurality of chips.3. The system of claim 2 , wherein the calibration circuit of each chip of the plurality of chips includes:a driver circuit coupled to the terminal; andan arbiter circuit configured to enable and disable the driver circuit for the fixed duration of time based on the liming information unique to each respective chip among the plurality of chips.4. The system of claim 2 , wherein the calibration circuit of each chip of the plurality of chips includes:a driver circuit coupled to the terminal; andan arbiter circuit configured to disable the driver circuit to change a voltage of the terminal for a predetermined time in the beginning of the fixed duration of time and further configured to enable the driver circuit after the predetermined time.5. The system of claim 1 , wherein the calibration circuit of each chip of the plurality of chips includes an arbiter circuit claim 1 , andwherein an order in which the plurality of chips requesting calibration ...

TIMING BASED ARBITRATION METHODS AND APPARATUSES FOR CALIBRATING IMPEDANCES OF A SEMICONDUCTOR DEVICE

Systems and apparatuses are provided for an arbiter circuit for timing based ZQ calibration. An example system includes a resistor and a plurality of chips. Each of the plurality of chips further includes a terminal coupled to the resistor and a calibration circuit. The calibration circuit determines whether the resistor is available based, at least in part, on timing information that is unique to a corresponding chip of the plurality of chip. The timing information of each chip of the plurality of chips has a fixed duration of time common to the plurality of chips. 1. An apparatus comprising:a driver circuit coupled to a terminal of a chip; andan arbiter circuit configured to enable the driver circuit to change a voltage of the terminal before determining a resistor coupled to the terminal is available for a calibration operation of the chip, wherein the arbiter circuit enables the driver circuit based at least in part, on timing information unique to the chip.2. The apparatus of claim 1 , further comprising a calibration control circuit coupled to the driver circuit wherein the calibration control circuit is configured to adjust an impedance of the driver circuit when the resistor is available for the calibration operation.3. The apparatus of claim 1 , wherein the driver circuit includes a pull-up circuit and a pull-down circuit.4. The apparatus of claim 3 , wherein the pull-up circuit includes a first plurality of transistors coupled in parallel between a first power supply terminal and a node and the pull-down circuit includes a second plurality of transistors coupled in parallel between a second power supply terminal and the node.5. The apparatus of claim 1 , further comprising a comparator configured to compare a first voltage to a reference voltage and provide a comparator result to the arbiter circuit.6. The apparatus of claim 5 , further comprising a reference voltage generator configured to provide the reference voltage to the comparator.7. The apparatus ...

Memory device and semiconductor device

Provided is a memory device with a reduced layout area. The memory device includes a sense amplifier electrically connected to first and second wirings and positioned in a first layer, and first and second circuits positioned in a second layer over the first layer. The first circuit includes a first switch being turned on and off in accordance with a potential of a third wiring, and a first capacitor electrically connected to the first wiring via the first switch. The second circuit includes a second switch being turned on and off in accordance with a potential of a fourth wiring, and a second capacitor electrically connected to the second wiring via the second switch. The first wiring intersects the third wiring and does not intersect the fourth wiring in the second layer. The second wiring intersects the fourth wiring and does not intersect the third wiring in the second layer.

METHOD OF GENERATING A MULTI-LEVEL SIGNAL USING A SELECTIVE LEVEL CHANGE, A METHOD OF TRANSMITTING DATA USING THE SAME, AND A TRANSMITTER AND MEMORY SYSTEM PERFORMING THE SAME

A method of generating a multi-level signal having one of three or more voltage levels that are different from each other, the method including: performing a first voltage setting operation in which first and second voltage intervals are adjusted to be different from each other, wherein the first voltage interval represents a difference between a first pair of adjacent voltage levels and the second voltage interval represents a difference between a second pair of adjacent voltage levels; performing a second voltage setting operation in which a voltage swing width is adjusted, the voltage swing width representing a difference between a lowest and a highest voltage level among the three or more voltage levels; and generating an output data signal that is the multi-level signal based on input data including two or more bits, a result of the first voltage setting operation and a result of the second voltage setting operation. 1. A method of generating a multi-level signal having one of three or more voltage levels that are different from each other , the method comprising:performing, a first voltage setting operation in which a first voltage interval and a second voltage interval are adjusted to be different from each other, wherein the first voltage interval represents a difference between a first pair of adjacent voltage levels among the three or more voltage levels and the second voltage interval represents a difference between a second pair of adjacent voltage levels among the three or more voltage levels;performing a second voltage setting operation in which a voltage swing width is adjusted, the voltage swing width representing a difference between a lowest voltage level and a highest voltage level among the three or more voltage levels; andgenerating an output data signal that is the multi-level signal based on input data including two or more bits, a result of the first voltage setting operation and a result of the second voltage setting operation.2. The method ...

Method for configuring multiple input-output channels

A system comprises an interposer including multiple conductive interconnects; multiple chiplets arranged on the interposer and interconnected by the interposer; each chiplet including a die-to-die physical layer interface including one or more pads to engage the interconnect of the interposer; and wherein at least one chiplet includes multiple input-output channels organized into at least one column and arranged in an order at a periphery of the chiplet forming a die-to-die physical layer interface to engage the interconnects of the interposer, wherein the order of the channels of the column is programmable.

MEMORY

A memory is provided. The memory includes a control chip () and a plurality of memory chips (). The plurality of memory chips are electrically connected to the control chip () by sharing a channel (). The plurality of memory chips () are configured to adopt the same clock signal, and each of the plurality of memory chips () is configured to perform information interaction with the control chip () in a different clock state of the clock signal.

Methods and Systems for Improving Read and Write of Memory Cells

A method for accessing of memory cells where a set of user data is stored in a plurality of memory cells of the memory array, including: latching a current row address of a selected plurality of memory access; comparing a last row address with the current row address; if the result of the comparison is negative, executing a leakage compensation algorithm through a memory sensing circuitry; if the result of the comparison is positive, waiting for the completion of a write to read procedure on the selected plurality of memory cells.

SIGNALING SYSTEM WITH ADAPTIVE TIMING CALIBRATION

A signaling system is disclosed. The signaling system includes a first integrated circuit (IC) chip to receive a data signal and a strobe signal. The first IC includes circuitry to sample the data signal at times indicated by the strobe signal to generate phase error information and circuitry to output the phase error information from the first IC device. The system further includes a signaling link and a second IC chip coupled to the first IC chip via the signaling link to output the data signal and the strobe signal to the first IC chip. The second IC chip includes delay circuitry to generate the strobe signal by delaying an aperiodic timing signal for a first time interval and timing control circuitry to receive the phase error information from the first IC chip and adjust the first time interval in accordance with the phase error information.

SEMICONDUCTOR DEVICES

A semiconductor device includes first and second memory regions spaced apart from each other and a fail information storage region disposed between the first and second memory regions. A parity including error information on data is stored in a first parity region of the fail information storage region while a write operation is applied to the first memory region. The parity is stored in a second parity region of the fail information storage region while the write operation is applied to the second memory region. An error of the data is corrected by the parity stored in the first parity region while a read operation is applied to the first memory region. The error of the data is corrected by the parity stored in the second parity region while the read operation is applied to the second memory region. 1. A semiconductor device comprising:a first memory region and a second memory region spaced apart from each other; anda fail information storage region disposed between the first and second memory regions,wherein a parity including error information on data is stored in a first parity region of the fail information storage region while a write operation is applied to the first memory region,wherein the parity is stored in a second parity region of the fail information storage region while the write operation is applied to the second memory region,wherein an error of the data is corrected by the parity stored in the first parity region while a read operation is applied to the first memory region, andwherein the error of the data is corrected by the parity stored in the second parity region while the read operation is applied to the second memory region.2. The semiconductor device of claim 1 ,wherein a distance between the first parity region and the first memory region is less than a distance between the second parity region and the first memory region; andwherein a distance between the second parity region and the second memory region is less than a distance between ...

Static random access memory

A static random access memory includes a first inverter and a second inverter, a first n-type metal-oxide-semiconductor (NMOS) transistor, and a second NMOS transistor. An output terminal of the first inverter is connected to an input terminal of the second inverter, and an input terminal of the first inverter is connected to an output terminal of the second inverter. The first NMOS transistor is configured to control a write signal, and the second NMOS transistor is configured to control a read signal. The first NMOS transistor is connected to the input terminal of the first inverter, the output terminal of the second inverter, a write word line, and a write bit line. The second NMOS transistor is connected to the output terminal of the first inverter, the input terminal of the second inverter, a read word line, and an internal line.

READ DATA FIFO CONTROL CIRCUIT

Disclosed herein is an apparatus that includes a memory cell array configured to output a read data and a timing signal in response to a read command signal, an input counter configured to update an input count value in response to the timing signal, an output counter configured to update an output count value in response to the read command signal, and a data FIFO circuit having a plurality of data registers, the data FIFO circuit being configured to store the read data into one of the data registers indicated by the input count value and configured to output the read data stored in one of the data registers indicated by the output count value. The output counter is configured to maintain the output count value without updating in response to the read command signal when an active judge signal is in an inactive state. 1. An apparatus comprising:a memory cell array configured to output a read data and a tuning signal in response to a read command signal;an input counter configured to update an input count value in response to the timing signal;an output counter configured to update an output count value in response to the read command signal; anda data FIFO circuit having a plurality of data registers, the data FIFO circuit being configured to store the read data into one of the data registers indicated by an input point value and configured to output the read data stored in one of the data registers indicated by an output point value,wherein the output counter is configured to maintain the output count value without updating in response to the read command signal when an active judge signal is in an inactive state.2. The apparatus of claim 1 , wherein the memory cell array is configured to output the read data and the timing signal substantially synchronously3. The apparatus of claim 2 , further comprising a latency control circuit configured to delay the read command signal claim 2 ,wherein the memory cell array is supplied with the read command signal without ...

Memory device performing configurable mode setting and method of operating the same

A memory device according to an aspect may include a memory cell array including a first bank region and a second bank region each including a plurality of banks; an operation logic including one or more first processing elements (PEs) corresponding to the first bank region and one or more second PEs corresponding to the second bank region; a control logic configured to control modes of the first bank region and the second bank region based on externally sourced setting information; first and second mode signal generators configured to control enabling the first PEs, wherein the first mode signal generator is configured to output the first mode signal to enable the first PEs and the second mode signal generator is configured to output the second mode signal to disable the second PEs responsive to the first bank region being set to an operation mode and the second bank region being set to a normal mode.

APPARATUSES AND METHODS TO MASK WRITE OPERATIONS FOR A MODE OF OPERATION USING ECC CIRCUITRY

An exemplary semiconductor device includes an input/output (I/O) circuit configured to combine data corresponding to a write command received via data terminals with a first subset of corrected read data retrieved from a memory cell array to provide write data. The exemplary semiconductor device further includes a write driver circuit configured to mask a write operation of a first bit of the write data that corresponds to a bit of the first subset of the read data and to perform a write operation for a second bit of the write data that corresponds to the data received via the data terminals. 1. An apparatus comprising:an input/output (I/O) circuit configured to combine data corresponding to a write command received via data terminals with a first subset of corrected read data retrieved from a memory cell array to provide write data; anda write driver circuit configured to mask a write operation of a first bit of the write data that corresponds to a bit of the first subset of the read data and to perform a write operation for a second bit of the write data that corresponds to the data received via the data terminals.2. The apparatus of claim 1 , further comprising an error-correcting code (ECC) control circuit configured to receive read data and read parity data and is configured to generate the corrected read data from the read data based on the read parity data.3. The apparatus of claim 2 , wherein the ECC control circuit is configured to generate syndrome data based on the read parity data and to decode the syndrome data to determine a location of an error in the read data.4. The apparatus of claim 3 , wherein the write driver circuit is configured to perform a write operation for a third bit of the write data that corresponds to the location of the error in the read data.5. The apparatus of claim 3 , further comprising a control circuit configured to cause a column decoder to disable a column select signal in response to the ECC control circuit indicating that ...

Semiconductor devices performing a write leveling training operation and semiconductor systems including the semiconductor devices

A method includes performing a first write leveling training operation and performing a second write leveling training operation. The first write leveling training operation is performed to generate transmission data based on a data strobe signal and an internal command pulse and to generate a latency code. The second write leveling training operation is performed to generate the transmission data based on the data strobe signal and the internal command pulse.

TEST CIRCUIT, SEMICONDUCTOR DEVICE AND TEST SYSTEM INCLUDING THE TEST CIRCUIT

A test circuit includes a comparator and a comparison control circuit. The comparator is configured to compare a first input signal with a second input signal to generate a comparison result signal. The comparison control circuit is configured to perform at least one of an operation for latching the comparison result signal as reference data and an operation for outputting the comparison result signal as a first output signal. The comparison control circuit is configured to provide expectation data as the first input signal and read data as the second input signal in accordance with the reference data. 1. A test circuit comprising:a comparator configured to compare a first input signal with a second input signal to generate a comparison result signal; anda comparison control circuit configured to perform at least one of an operation for latching the comparison result signal as reference data and an operation for outputting the comparison result signal as a first output signal,wherein the comparison control circuit is configured to provide expectation data as the first input signal and read data as the second input signal in accordance with the reference data.2. The test circuit of claim 1 , wherein the comparison control circuit configured to output the first output signal as a pass determination level regardless of the expectation data and the read data when the reference data has a fail determination level.3. The test circuit of claim 1 , wherein the comparison control circuit is configured to provide the expectation data as the first input signal and the read data as the second input signal when the reference data has a pass determination level.4. The test circuit of claim 1 , wherein the comparison control circuit is configured to latch the comparison result signal as the reference data when a clock enable signal has a first level.5. The test circuit of claim 4 , wherein the comparison control circuit is configured to output the comparison result signal as the ...

Memory system

According to one embodiment, a memory system includes a non-volatile semiconductor memory with a plurality of dies and a memory controller. A temperature sensor is provided for each of the dies. The temperature sensors measures a temperature of each die. The memory controller schedules execution of access commands for each of the dies based on the measured die temperature, a predetermined limit temperature for each of the dies, and the type of access command that has been received by the memory controller.

Semiconductor memory device

A semiconductor memory device includes a first pad which outputs data to the outside; an output driver coupled to the first pad; a calibration circuit which adjusts impedance of the output driver; and a controller. The controller controls a calibration operation by the calibration circuit, in response to a first command received from the outside, and performs a write operation on a mode resister, in response to a second command received from the outside, the second command being different from the first command.

Drive strength calibration for multi-level signaling

Methods, systems, and devices for drive strength calibration for multi-level signaling are described. A driver may be configured to have an initial drive strength and to drive an output pin of a transmitting device toward an intermediate voltage level of a multi-level modulation scheme, where the output pin is coupled with a receiving device via a channel. The receiving device may generate, and the transmitting device may receive, a feedback signal indicating a relationship between the resulting voltage of the channel and an value for the intermediate voltage level. The transmitting device may determine and configure the driver to use an adjusted drive strength for the intermediate voltage level based on the feedback signal. The driver may be calibrated (e.g., independently) for each intermediate voltage level of the multi-level modulation scheme. Further, the driver may be calibrated for the associated channel.

MEMORY SYSTEM THAT SUPPORTS DUAL-MODE MODULATION

Methods, systems, and devices that supports dual-mode modulation in the context of memory access are described. A system may include a memory array coupled with a buffer, and a multiplexer may be coupled with the buffer, where the multiplexer may be configured to output a bit pair representative of data stored within the memory array. The multiplexer may also be coupled with a driver, where the driver may be configured to generate a symbol representative of the bit pair that is output by the multiplexer. 1. A method , comprising:determining a first signaling mode for an output circuit of a plurality of output circuits coupled with a memory array;configuring the output circuit to generate non-binary symbols representative of data stored within the memory array based at least in part on determining the first signaling mode; andoutputting, by the output circuit, the non-binary symbols based at least in part on configuring the output circuit to generate the non-binary symbols.2. The method of claim 1 , further comprising:determining a second signaling mode for the output circuit; andconfiguring the output circuit to generate binary symbols representative of data stored within the memory array based at least in part on determining the second signaling mode.3. The method of claim 2 , wherein the first signaling mode and the second signaling mode use a same symbol rate.4. The method of claim 2 , wherein the first signaling mode uses a first symbol rate and the second signaling mode uses a second symbol rate different from the first symbol rate.5. The method of claim 2 , further comprising:configuring an additional output circuit to generate binary symbols representative of data stored within the memory array based at least in part on determining the second signaling mode.6. The method of claim 2 , further comprising:detecting a data rate associated with the memory array for a temporal duration; anddetermining that the data rate is below a threshold data rate, wherein ...

Ram cell processing circuit

A method includes generating a voltage difference indication between a previous voltage on the bit line of a DRAM and a current voltage on a bit line. In an embodiment, the previous voltage corresponds to a logic 1 voltage or a logic 0 voltage stored in a previous DRAM cell of a column of DRAM cells, the current voltage corresponds to a logic 1 voltage or a logic 0 voltage being stored in the current DRAM cell of the column of DRAM cells, and the bit line is coupled to the column of DRAM cells. When the current DRAM cell is in a read mode, the method further includes the following steps: Generating a read voltage reference based on the voltage difference indication; Generating a read output voltage based on the read voltage reference; Supplying the read output voltage on to the bit line; and Outputting a representation of the read output voltage.

Semiconductor memory device

A semiconductor memory device includes a control circuit, first wirings, second wirings intersecting the first wirings, and memory cells formed between the first wirings and the second wirings. The control circuit is configured to supply, in a set operation, a set pulse between one of the first wirings and one of the second wirings, supply, in a reset operation, a reset pulse between one of the first wirings and one of the second wirings, and supply, in a first operation, a first pulse between one of the first wirings and one of the second wirings. The first pulse has an amplitude larger than a larger one of an amplitude of the set pulse or an amplitude of the reset pulse, or the same amplitude as the larger amplitude. The first pulse has a pulse width larger than a pulse width of the reset pulse.

Input-output line sense amplifier having adjustable output drive capability

An input-output line sense amplifier configured to drive input data signals over an input-output signal line to an output driver circuit, the input-output line sense amplifier having an output driver stage having a plurality of different programmable output drive capacities to tailor the output drive of the sense amplifier.

PACKAGE MODULES AND METHODS OF TESTING OPERATIONS OF CHIPS INCLUDED THEREIN

A package module may be provided. The package module may include a first chip and a second chip. The first chip may be configured to receive first pattern data to generate first transmission data in a first write mode. The second chip may be configured to receive the first transmission data to generate and output first sense data in a first read mode. 1. A package module comprising:a first chip configured to operate in a first write mode and receive pattern data; anda second chip configured to operate in a first read mode and output first sense data,wherein whether the first chip has a normal transmitting function and the second chip has a normal receiving function is determined based on a comparison between the pattern data and the first sense data.2. The package module of claim 1 , further comprising a control chip configured to transmit first pattern data to the first chip and configured to receive the first sense data to discriminate whether the first chip has a normal transmitting function and the second chip has a normal receiving function.3. The package module of claim 1 , wherein the first chip includes:a first pad receiving first pattern data to provide write data;a first selection circuit configured to selectively output the write data as selection write data; anda first transceiver configured to generate first transmission data from the selection write data and configured to output the first transmission data.4. The package module of claim 3 , wherein the second chip includes:a second transceiver configured to receive the first transmission data to generate read data;an output circuit configured to generate selection read data from the read data in the first read mode; anda second pad outputting the selection read data as the first sense data.5. The package module of claim 1 , wherein the first chip receives a first pattern strobe signal to generate and transmit a transmission strobe signal in the first write mode.6. The package module of claim 5 , ...

MEMORY DEVICE AND OPERATION METHOD THEREOF

A memory device may include a first data line driver circuit that generates a first reference voltage set based on a first code and a second code associated with a first data line, and determines bit values of the first input data received through the first data line, based on the first reference voltage set. A second data line driver circuit may similarly generate a second reference voltage set. The reference voltages may have levels based on a decision feedback equalization (DFE) technique to reduce bit errors otherwise caused by inter symbol interference. 1. A memory system comprising:a memory device; anda memory controller configured to transmit input data to the memory device through a first data line and a second data line,wherein the memory controller is further configured to store first to fourth codes in the memory device by performing a training operation, the first code including information of a first reference voltage level associated with the first data line, the second code including information of a first decision feedback equalization (DFE) level associated with the first data line, the third code including information of a second reference voltage level associated with the second data line, and the fourth code including information of a second DFE level associated with the second data line;wherein the memory device comprises:a first data line driver circuit configured to generate a first reference voltage set based on the first and second codes associated with the first data line, and to determine first bit values of the input data received through the first data line based on the first reference voltage set; anda second data line driver circuit configured to generate a second reference voltage set based on the third and fourth codes associated with the second data line, and to determine second bit values of the input data received through the second data line based on the first reference voltage set.2. The memory system of claim 1 , wherein the ...

TIMING BASED ARBITRATION METHODS AND APPARATUSES FOR CALIBRATING IMPEDANCES OF A SEMICONDUCTOR DEVICE

Systems and apparatuses are provided for an arbiter circuit for timing based ZQ calibration. An example system includes a resistor and a plurality of chips. Each of the plurality of chips further includes a terminal coupled to the resistor and a calibration circuit. The calibration circuit determines whether the resistor is available based, at least in part, on timing information that is unique to a corresponding chip of the plurality of chip. The timing information of each chip of the plurality of chips has a fixed duration of time common to the plurality of chips. 1. A method comprising:floating a voltage of an external pad for a first period of time;pulling down the voltage of the external pad to a first voltage state for a second period of time; andpulling down or floating the voltage of the external pad for individual ones of a plurality of clock cycles, wherein whether the voltage of the external pad is pulled down or floated for a clock cycle of the plurality of clock cycles is based, at least in part, on timing information unique to a chip of a plurality of chips.2. The method of claim 1 , further comprising claim 1 , prior to pulling down the voltage of the external pad to the second voltage state for the second period of time claim 1 , comparing the voltage of the external pad to a reference voltage to determine whether the voltage of the external pad is at the first voltage state or a second voltage state claim 1 , wherein when the voltage of the external pad is determined to be the first voltage state claim 1 , the method further comprises repeating floating the voltage of the external pad for the first period of time.3. The method of claim 1 , further comprising comparing the voltage of the external pad to a reference voltage to determine whether the voltage of the external pad is at the first voltage state or a second voltage state after each clock cycle of the plurality of clock cycles claim 1 , wherein when the voltage of the external pad is ...

Apparatus with access control mechanism and methods for operating the same

Methods, apparatuses, and systems related to die-to-die communications are described. An apparatus may include an interfacing die and at least one additional die communicatively coupled to each other through an internal bus. The interfacing die may be configured to provide a combined external interface for the coupled dies. For the die-to-die communications, a target die may coordinate transfer of communicated data to the internal interface according to a timing signal generated by a source external to the at least one additional die.

Semiconductor memory device

A semiconductor memory device includes first and second memory blocks arranged along a first direction, a first bit line extending in the first direction and including first and second portions respectively through which the first and second memory blocks are connected to the first bit line, a first sense amplifier connected to the first bit line, a first wiring which extends in a second direction intersecting the first direction, and overlaps the second portion of the first bit line when viewed in a third direction intersecting the first and second directions, and a controller which applies a first voltage to the first bit line, and a second voltage to the first wiring during a read operation. A first distance between the first sense amplifier and the first portion is shorter than a second distance between the first sense amplifier and the second portion.

MEMORY DEVICE AND OPERATING METHOD THEREOF

The memory device includes a memory cell array including a plurality of memory blocks each including a plurality of strings, wherein the plurality of memory blocks are controlled to have a set temperature; a peripheral circuit for performing a read operation on a selected memory block among the plurality of memory blocks; a temperature detection circuit for detecting a temperature of the memory cell array and generating a temperature detection signal based on the temperature of the memory cell array; and a control logic for controlling the peripheral circuit during the read operation and configured to generate a heating control signal that may control the selected memory block to have the set temperature in response to the temperature detection signal, 1. A memory device comprising:a memory cell array including a plurality of memory blocks, each including a plurality of strings, wherein the plurality of memory blocks are controlled to have a set temperature;a peripheral circuit configured to perform a read operation on a selected memory block among the plurality of memory blocks;a temperature detection circuit configured to detect a temperature of the memory cell array and generate a temperature detection signal based on the temperature of the memory cell array; anda control logic configured to control the peripheral circuit during the read operation and configured to generate a heating control signal that may control the selected memory block to have the set temperature in response to the temperature detection signal.2. The memory device of claim 1 , wherein each of the plurality of strings has a channel structure including a heating layer claim 1 , a channel layer claim 1 , a tunnel insulating layer claim 1 , and a charge storage layer.3. The memory device of claim 2 , wherein the heating layer controls the selected memory block to have the set temperature by generating heat in response to the heating control signal.4. The memory device of claim 3 , wherein the ...

Ferroelectric fet-based content addressable memory

An efficient FeFET-based CAM is disclosed which is capable of performing normal read, write but has the ability to match input data with don't-care. More specifically, a Ferroelectric FET Based Ternary Content Addressable Memory is disclosed. The design in some examples utilizes two FeFETs and four MOSFETs per cell. The CAM can be written in columns through multi-phase writes. It can be used a normal memory with indexing read. It also has the ability for ternary content-based search. The don't-care values can be either the input or the stored data.

DATA PATHS USING A FIRST SIGNAL TO CAPTURE DATA AND A SECOND SIGNAL TO OUTPUT DATA AND METHODS FOR PROVIDING DATA

Data paths, memories, and methods for providing data from memory are disclosed. An example read data path includes a delay path, and a clocked data register. The data path has a data propagation delay and is configured to receive data and propagate the data therethrough. The delay path is configured to receive a clock signal and provide a delayed clock signal having a delay relative to the clock signal that models the data propagation delay. The clocked data register is configured to clock in data responsive at least in part to the delayed clock signal. The clocked data register is further configured to clock out data responsive at least in part to the clock signal. 1. An apparatus comprising:a memory array comprising a plurality of memory cells;an input/output (I/O) bus through which at least command signals, address signals, write data signals and read data signals are transferred;a first register coupled to the memory array, the first register configured to capture data read from the memory array and to output data stored therein responsive, at least in part, to a first clock signal;a second register coupled to the first register, the second register configured to capture data provided from the first register responsive, at least in part, to a second clock signal, the second register further configured to output data stored therein to provide the read data signals; anda first circuit providing the second clock signal responsive, at least in part, to the first signal.2. The apparatus of claim 1 , wherein the second register is configured to output the data responsive claim 1 , at least in part claim 1 , to the first clock signal.3. The apparatus of claim 1 , wherein the first register is configured to sequentially output the data responsive claim 1 , at least in part claim 1 , to the first clock signal claim 1 , and the second register is configured to sequentially capture the data provided from the first register responsive claim 1 , at least in part claim 1 , to ...

APPARATUSES AND METHODS FOR SEMICONDUCTOR DEVICES INCLUDING CLOCK SIGNAL LINES

Apparatuses for providing a clock signal for a semiconductor device are described. An example apparatus includes a chip including a first clock tree and a second clock tree. The first clock tree includes a first wiring segment extending in a first direction and a second wiring segment extending in a second direction perpendicular to the first direction and coupled the first wiring segment. The second clock tree includes a third wiring segment extending in the second direction, a fourth wiring segment extending in the first direction and coupled to the third wiring segment, and a fifth wiring segment extending in the second direction and coupled to the fourth wiring segment. 1. An apparatus comprising a chip including:a first side and a second side extending in a first direction;a center region disposed between the first and second sides;a side region disposed between the center region and the first side;a first clock driver disposed in the center region;a second clock driver disposed in the center region;a third clock driver disposed in the side region; 'a first wiring segment extending in the center region and coupled to the first clock driver, and', 'a first clock signal line including 'a second wiring segment extending from the center region to the side region and coupled to the second clock driver and further coupled to the third clock driver.', 'a second clock signal line including2. The apparatus of claim 1 , wherein the chip is a memory core chip comprising a plurality of data queue (DQ) core cells configured to receive or provide data claim 1 , andwherein the second clock signal line further comprises a third wiring segment coupled to the third clock driver and extending to the plurality of DQ core cells.3. The apparatus of claim 1 , wherein the first clock driver is configured to drive a first plurality of clock signals and the second clock driver is configured to drive a second plurality of clock signals different from the first plurality of clock signals. ...

Timing of read and write operations to reduce interference, and related devices, systems, and methods

Devices, systems, and methods for timing elements of memory read and write operations are disclosed. A device may include a first DQ pin, a second DQ pin, and an output circuit. The output circuit may be configured to provide: a first signal at the first DQ pin and a second signal at the second DQ pin, based on the timing pattern. In some embodiments, based on the timing pattern, the output circuit may be configure to delay the first signal relative to the second signal such that rising and falling edges of the first signal do not coincide with rising and falling edges of the second signal. In these or other embodiments, the device may further include a mode register, wherein a slew rate of the first signal is based at least in part on a value of the mode register. Associated systems and methods are also disclosed.

Systems and Methods for Memory Operation Using Local Word Lines

Systems and method are provided for a memory circuit. In embodiments, the circuit includes a plurality of memory cells corresponding to a word of data and a global write word line. A plurality of local write lines are connected to a subset of the plurality of memory cells of the word of data. Selection logic is configured to activate a particular subset of memory cells for writing via a particular local write line based on a signal on the global write word line and a selection signal associated with the particular subset of memory cells.

Information processing apparatus and method for controlling information processing apparatus

An apparatus includes a nonvolatile semiconductor memory device storing identification information and first setting information on an output signal, a memory holding identification information of nonvolatile semiconductor memory devices, the identification information including the identification information of the nonvolatile semiconductor memory device, and setting information on an output signal associated with the identification information of the nonvolatile semiconductor memory devices, the setting information including at least second setting information on the output signal, and a processor acquiring the identification information of the nonvolatile semiconductor memory.

SIGNALING SYSTEM WITH ADAPTIVE TIMING CALIBRATION

A signaling system is disclosed. The signaling system includes a first integrated circuit (IC) chip to receive a data signal and a strobe signal. The first IC includes circuitry to sample the data signal at times indicated by the strobe signal to generate phase error information and circuitry to output the phase error information from the first IC device. The system further includes a signaling link and a second IC chip coupled to the first IC chip via the signaling link to output the data signal and the strobe signal to the first IC chip. The second IC chip includes delay circuitry to generate the strobe signal by delaying an aperiodic timing signal for a first time interval and timing control circuitry to receive the phase error information from the first IC chip and adjust the first time interval in accordance with the phase error information. 1. (canceled)2. An integrated circuit (IC) memory controller , comprising:a timing signal pin to receive a timing signal;a data pin to receive data during live data transfer operations and having sampling circuitry;a timing controller coupled to the timing signal pin and the data pin, the timing controller operative during an initialization mode to determine whether devices generating the data support an adaptive calibration mode associated with the live data transfer operations, the initialization mode occurring outside of the live data transfer operations, the timing controller operative during the adaptive calibration mode to detect a phase difference between a phase of the timing signal and a phase of the data, and to adjust the phase of the data to a calibrated phase based on the phase difference; andwherein the first sampling circuitry samples the first data based on the first calibrated phase.3. The integrated circuit (IC) memory controller of wherein:the data pin includes a first adjustable delay circuit responsive to the timing controller to delay the data by a delay value based on the phase difference.4. The ...

Data sorting control circuit and memory device including the same

A data sorting control circuit includes a phase detector suitable for detecting a phase of each of a first clock signal, a second clock signal, a third clock signal, and a fourth clock signal in response to a read command, an order determiner suitable for determining a data order as a first order or a second order based on a seed address and the detected phase of each of the clock signals, and an sorting control signal generator suitable for shifting the read command based on the first clock signal to the fourth clock signal to generate a first sorting control signal, a second sorting control signal, a third sorting control signal, and a fourth sorting control signal, and outputting the first sorting control signal to the fourth sorting control signal according to the first order or the second order.

SEMICONDUCTOR MEMORY APPARATUS AND OPERATING METHOD OF THE SEMICONDUCTOR MEMORY APPARATUS

A semiconductor memory apparatus includes a memory cell. The semiconductor apparatus includes a current supply circuit configured to change a resistance state of the memory cell, by changing an amount of current flowing through the memory cell, with or without limiting a voltage level across the memory cell to a level of a clamping voltage based on a state of the memory cell. 1. A semiconductor memory apparatus comprising:a memory cell; anda current supply circuit configured to perform a write operation by changing an amount of current flowing through the memory cell, perform a reset write operation without limiting a voltage level across the memory cell, and limit the voltage level across the memory cell to a level of a clamping voltage in a set write operation.2. The semiconductor memory apparatus according to claim 1 ,wherein the memory cell is coupled between a global bit line and a global word line, andis wherein the current supply circuit comprises:a first limit circuit coupled with the global bit line, and configured to change a current applied to the memory cell; anda second limit circuit coupled with the global word line, and configured to change a current flowing through the memory cell.3. The semiconductor memory apparatus according to claim 2 , wherein the first limit circuit changes a voltage level of the global bit line claim 2 , and the second limit circuit changes a voltage level of the global word line.4. The semiconductor memory apparatus according to claim 2 , further comprising:a write controller configured to control the first and second limit circuits based on a reset write signal and a set write signal.5. The semiconductor memory apparatus according to claim 2 , further comprising:a bit line supply configured to provide a high voltage to the first limit circuit; anda word line supply configured to provide a low voltage having a level lower than the high voltage, to the second limit circuit.6. The semiconductor memory apparatus according to ...

Memory device and system including the same

A memory device include a memory array, a transmitter suitable for outputting data to the outside of the memory device, and a data bus suitable for transmitting data of a selected memory cell in the memory array to the transmitter during a read operation. When successive read commands for the same memory cell are applied, data transmission from the memory array to the data bus is blocked, and data previously loaded in the data bus is outputted through the transmitter.

SUPPORT FOR MULTIPLE WIDTHS OF DRAM IN DOUBLE DATA RATE CONTROLLERS OR DATA BUFFERS

An apparatus includes a control circuit comprising (i) a first differential data strobe input/output circuit having a first set of driver and termination control inputs and (ii) a second differential data strobe input/output circuit having a second set of driver and termination control inputs. The first and the second sets of driver and termination control inputs are independently programmable. The first and the second differential data strobe input/output circuits operate in a first mode when the first differential data strobe input/output circuit is connected to a first memory device having a first data width and the second differential data strobe input/output circuit is connected to a second memory device having the first data width. The first and the second differential data strobe input/output circuits operate in a second mode when the first differential data strobe input/output circuit and the second differential data strobe input/output circuit are connected in parallel to a single memory device having a second data width. 1. An apparatus comprising:a control circuit comprising (i) a first differential data strobe input/output circuit having a first set of driver and termination control inputs and (ii) a second differential data strobe input/output circuit having a second set of driver and termination control inputs, whereinsaid first and said second sets of driver and termination control inputs are independently programmable,said first and said second differential data strobe input/output circuits operate in a first mode when said first differential data strobe input/output circuit is connected to a first memory device having a first data width and said second differential data strobe input/output circuit is connected to a second memory device having said first data width, andsaid first and said second differential data strobe input/output circuits operate in a second mode when said first differential data strobe input/output circuit and said second ...

MEMORY CONTROL CIRCUIT AND METHOD FOR CONTROLLING THE SAME

A memory control circuit is configured to access a memory including a plurality of banks. The memory control circuit comprises: a holding unit configured to hold an access request from an external circuit; a management unit configured to manage states of the plurality of banks; a determination unit configured to determine, based on an access type of an access request held in the holding unit and the states of the plurality of banks, which access type of command issuance that is read or write is to be prioritized; and an issuance unit configured to issue a command of an access request corresponding to the access type determined to be prioritized by the determination unit, among the access requests held in the holding unit. 1. A memory control circuit configured to access a memory including a plurality of banks , the memory control circuit comprising:a holding unit configured to hold an access request from an external circuit;a management unit configured to manage states of the plurality of banks;a determination unit configured to determine, based on an access type of an access request held in the holding unit and the states of the plurality of banks, which access type of command issuance that is read or write is to be prioritized; andan issuance unit configured to issue a command of an access request corresponding to the access type determined to be prioritized by the determination unit, among the access requests held in the holding unit.2. The memory control circuit according to claim 1 , wherein the management unit manages claim 1 , for each of the plurality of banks claim 1 , whether a bank is open and claim 1 , in a case where the bank is open claim 1 , which page is open.3. The memory control circuit according to claim 2 , whereinthe determination unitprioritizes read when only read access requests are held in the holding unit,prioritizes write when only write access requests are held in the holding unit; andwhen both read and write access requests are held in ...

Memory device including processing circuit, and electronic device including system on chip and memory device

A memory device includes a buffer die configured to receive a first broadcast command and a second broadcast command from an external device; and a plurality of core dies stacked on the buffer die. The plurality of core dies include: a first core die including a first processing circuit, a first memory cell array, a first command decoder configured to decode the first broadcast command, and a first data input/output circuit configured to output data of the first memory cell array to a common data input/output bus under control of the first command decoder; and a second core die including a second processing circuit, a second memory cell array, a second command decoder configured to decode the second broadcast command, and a second data input/output circuit configured to receive the data of the first memory cell array through the common data input/output bus under control of the second command decoder.

SEMICONDUCTOR MEMORY APPARATUS AND SEMICONDUCTOR SYSTEM INCLUDING THE SAME

A semiconductor memory apparatus includes first and second byte pads. A left-side peri-line couples the first byte pad and a first memory bank region and a right-side peri-line couples the second byte pad and a second memory bank region. A peri-repeater couples the left-side peri-line and the right-side peri-line based on a peri-strobe signal. The peri-strobe signal is generated based on byte information and memory bank selection information. 1. A semiconductor memory apparatus comprising:a left-side peri-line configured to couple a first byte pad and a first memory bank region;a right-side peri-line configured to couple a second byte pad and a second memory bank region;a peri-repeater configured to couple the left-side peri-line and the right-side peri-line based on a peri-strobe signal;a first bank repeater configured to couple the left-side peri-line and a first bank line arranged in the first memory bank region based on a first bank strobe signal;a second bank repeater configured to couple the right-side peri-line and a second bank line arranged in the second memory bank region based on a second bank strobe signal; anda control circuit is configured to generate the peri-strobe signal, the first bank strobe signal, and the second bank strobe signal based on byte information and memory bank selection information.2. The semiconductor memory apparatus of claim 1 ,wherein the first byte pad is coupled to a first data bus, andwherein the second byte pad coupled to a second data bus.3. The semiconductor memory apparatus of claim 2 ,wherein one among the first byte pad and the second byte pad is activated in a first byte operation mode, andwherein both the first byte pad and the second byte pad are activated in a second byte operation mode.4. The semiconductor memory apparatus of claim 1 , wherein when the first byte pad is activated and the first memory bank region is selected the control circuit is configured to enable the first bank strobe signal and disable the peri ...

SEMICONDUCTOR MEMORY DEVICE WITH POWER GATING CIRCUIT FOR DATA INPUT/OUTPUT CONTROL BLOCK AND DATA INPUT/OUTPUT BLOCK AND SEMICONDUCTOR SYSTEM INCLUDING THE SAME

A semiconductor device includes a data input/output control block including a first power gating circuit coupled to a supply terminal of a first voltage and a second power gating circuit coupled to a supply terminal of a second voltage, the data input/output control block suitable for generating a control signal using the first and second voltages, a data input/output block including a third power gating circuit coupled to any one of the supply terminal of the first voltage and the supply terminal of the second voltage, the data input/output block suitable for inputting and outputting a data signal using the first and second voltages based on the control signal, and a memory block, coupled to the data input/output block, suitable for writing or reading the data signal. 1. A semiconductor device , comprising:a write path control block including a first power gating circuit coupled to a supply terminal of a first voltage and a second power gating circuit coupled to a supply terminal of a second voltage, the write path control block suitable for generating a write control signal using the first and second voltages in a write mode;a write driving block including a third power gating circuit coupled to any one of the supply terminal of the first voltage and the supply terminal of the second voltage, the write driving block suitable for transmitting a data signal to a data input/output line using the first and second voltages based on the write control signal; anda memory block, coupled to the data input/output line, suitable for writing or reading the data signal.2. The semiconductor device of claim 1 , wherein the first power gating circuit is coupled between the supply terminal of the first voltage and a supply terminal of a third voltage;the second power gating circuit is coupled between the supply terminal of the second voltage and a supply terminal of a fourth voltage; andwherein the write path control block further includes a first logic circuit coupled to the ...

STACKED MEMORY DEVICE, A SYSTEM INCLUDING THE SAME AND AN ASSOCIATED METHOD

A stacked memory device includes: a logic semiconductor die; a plurality of memory semiconductor dies stacked with the logic semiconductor die, wherein each of the memory semiconductor dies includes a memory integrated circuit and one or more of the memory semiconductor dies is a calculation semiconductor die including a calculation unit; and through-silicon vias electrically connecting the logic semiconductor die and the plurality of memory semiconductor dies, wherein each of the calculation units is configured to perform calculations based on broadcast data and internal data and to generate calculation result data, wherein the broadcast data is commonly provided to the calculation semiconductor dies through the through-silicon vias, and the internal data is respectively read from the memory integrated circuits of the calculation semiconductor dies. 1. A stacked memory device comprising: a first memory bank including first memory cells and a first calculation unit configured to perform calculations based on broadcast data and first internal data; and', 'a second memory bank including second memory cells and a second calculation unit configured to perform calculations based on the broadcast data and second internal data;, 'a plurality of memory semiconductor dies that are vertically stacked, at least one of the plurality of memory semiconductor dies comprising,'}wherein the broadcast data is commonly provided to the first memory bank and the second memory bank, the first internal data is read from the first memory cells, and the second internal data is read from the second memory cells.2. The stacked memory device of claim 1 , wherein the first calculation unit and the second calculation unit perform the calculations in parallel based on the broadcast data.3. The stacked memory device of claim 1 , wherein each of the first and second memory banks includes a plurality of calculation units and the calculation units of each of the first memory bank and the second ...

Transmission of data for a machine learning operation using different microbumps

A system includes a memory device with microbumps and a processing device. The processing device is operatively coupled with the memory device to perform operations. The operations include transmitting data for a machine learning operation based on a set of the microbumps of the memory device where the data is being stored at the memory device. In addition, the operations include determining a change in a condition of the machine learning operation. Furthermore, the operations include that, in response to determining the change in the condition of the machine learning operation, determining a new set of the microbumps of the memory device that are to transmit subsequent data for the machine learning operation. Moreover, the operations include transmitting the subsequent data using the new set of microbumps of the memory device.

DATA RECEIVING DEVICES, MEMORY DEVICES HAVING THE SAME, AND OPERATING METHODS THEREOF

A data receiving device of a memory device comprises a first pre-amplifier configured to receive previous data, a first reference voltage, and input data, and to output differential signals by comparing the input data with the first reference voltage in response to a clock, when the first pre-amplifier is selected in response to the previous data, a second pre-amplifier configured to receive inverted previous data, a second reference voltage, different from the first reference voltage, and the input data, and outputting a common signal in response to the clock, when the second pre-amplifier is unselected in response to the previous data; and an amplifier configured to receive the differential signals and the common signal, and to latch the input data by amplifying the differential signals. 1. A data receiving device of a memory device , the data receiving device comprising:a first pre-amplifier configured to receive previous data, a first reference voltage, and input data, and to output differential signals by comparing the input data with the first reference voltage in response to a clock, when the first pre-amplifier is selected in response to the previous data;a second pre-amplifier configured to receive inverted previous data, a second reference voltage different from the first reference voltage, and the input data, and to output a common signal in response to the clock, when the second pre-amplifier is unselected in response to the previous data; andan amplifier configured to receive the differential signals and the common signal, and to latch the input data by amplifying the differential signals.2. The data receiving device of claim 1 ,wherein the first pre-amplifier is further configured to output a common signal in response to the clock, when the first pre-amplifier is unselected in response to the inverted previous data, andwherein the second pre-amplifier is further configured to output differential signals by comparing the input data with the second ...

SEMICONDUCTOR MEMORY DEVICE WITH POWER GATING CIRCUIT FOR DATA INPUT/OUTPUT CONTROL BLOCK AND DATA INPUT/OUTPUT BLOCK AND SEMICONDUCTOR SYSTEM INCLUDING THE SAME

A semiconductor device includes a data input/output control block including a first power gating circuit coupled to a supply terminal of a first voltage and a second power gating circuit coupled to a supply terminal of a second voltage, the data input/output control block suitable for generating a control signal using the first and second voltages, a data input/output block including a third power gating circuit coupled to any one of the supply terminal of the first voltage and the supply terminal of the second voltage, the data input/output block suitable for inputting and outputting a data signal using the first and second voltages based on the control signal, and a memory block, coupled to the data input/output block, suitable for writing or reading the data signal. 1. A semiconductor device , comprising:a write path control block including a first power gating circuit coupled to a supply terminal of a first voltage and a second power gating circuit coupled to a supply terminal of a second voltage, the write path control block suitable for generating a write control signal using the first and second voltages in a write mode;a write driving block including a third power gating circuit coupled to any one of the supply terminal of the first voltage and the supply terminal of the second voltage, the write driving block suitable for transmitting a data signal to a data input/output line using the first and second voltages based on the write control signal;a memory block, coupled to the data input/output line, suitable for writing or reading the data signal;a read path control block including a fourth power gating circuit coupled to the supply terminal of the first voltage and a fifth power gating circuit coupled to the supply terminal of the second voltage, the read path control block suitable for generating a read control signal using the first and second voltages in a read mode; anda pipe latch block including a sixth power gating circuit coupled to any one of the ...

TRANSMITTER WITH SELF-TRIGGERED TRANSITION EQUALIZER

A transmitting device includes an output node, at least one driver circuit and transition equalization circuitry. The driver circuit drives an output data signal including a data transition onto the output node. The output of the transition equalization circuitry is coupled to the output node. The transition equalization circuitry begins to drive the output node at the data transition and ends driving of the output node a pre-determined delay after beginning to drive the output node. The transition equalization circuitry drives the output node by injecting current onto the output node if the data transition is a positive transition, and sinking current from the output node if the data transition is a negative transition. 1. A transmitting device , comprising:an output node;at least one driver circuit to drive an output data signal onto the output node, the output data signal having a plurality of data transitions; andtransition equalization circuitry having an output coupled to the output node, the transition equalization circuitry driving the output node with a drive strength that varies depending on a magnitude of change of digital data in the plurality of data transitions.2. The transmitting device of claim 1 , wherein the transition equalization circuitry drives the output node by injecting current onto the output node responsive to a first data transition in the plurality of data transitions being a positive transition claim 1 , and sinking current from the output node responsive to a second data transition in the plurality of data transitions being a negative transition.3. The transmitting device of claim 2 , wherein the drive strength of the transition equalizer circuitry varies by adjusting an amount of the current injected into or sunk from the output node based on the magnitude of change of the digital data.4. The transmitting device of claim 1 , wherein the drive strength of the transition equalization circuitry is adjustable.5. The transmitting device of ...

MEMORY DEVICE AND OPERATING METHOD THEREOF

A memory device includes a memory cell array including a plurality of memory blocks and a storage block storing a plurality of pieces of option parameter information; a parameter determining circuit outputting a parameter information signal by measuring a skew of the memory device; a peripheral circuit performing a read operation on the storage block; and a control logic controlling the peripheral circuit to perform the read operation on a selected piece of option parameter information, among the plurality of pieces of option parameter information, in response to the parameter information signal, and setting an option parameter according to the selected piece of option parameter information. 1. A memory device , comprising:a memory cell array including a plurality of memory blocks and a storage block storing a plurality of pieces of option parameter information;a parameter determining circuit outputting a parameter information signal by measuring a skew of the memory device;a peripheral circuit performing a read operation on the storage block; anda control logic controlling the peripheral circuit to perform the read operation on a selected piece of option parameter information, among the plurality of pieces of option parameter information, in response to the parameter information signal, and setting an option parameter according to the selected piece of option parameter information.2. The memory device of claim 1 , wherein the parameter determining circuit comprises:a ring oscillator generating a clock signal having a period changed by reflecting variations in process, voltage and temperature (PVT) of elements; anda clock skew measuring circuit measuring the skew of the memory device by using the clock signal to output the parameter information signal.3. The memory device of claim 2 , wherein the clock skew measuring circuit counts the number of toggles of the clock signal for a predetermined time and measures the skew in response to the counted number of toggles.4. ...

SEMICONDUCTOR DEVICE INCLUDING ANTI-FUSE CELL

A structure includes anti-fuse cells. The anti-fuse cells include a first active area, a first gate, a second gate, at least one first gate via, and at least one second gate via. The first gate and the second gate are separate from each other. The first gate and the second gate extend to cross over the first active area. The at least one first gate via is coupled to the first gate and disposed directly above the first active area. The at least one second gate via is coupled to the second gate. The first gate is coupled through the at least one first gate via to a first word line for receiving a first programming voltage, and the second gate is coupled through the at least one second gate via to a second word line for receiving a first reading voltage. 1. A semiconductor device , comprising: a first active area;', 'a first gate and a second gate that are separate from each other, wherein the first gate and the second gate extend to cross over the first active area;', 'at least one first gate via coupled to the first gate and disposed directly above the first active area; and', 'at least one second gate via coupled to the second gate;, 'a plurality of anti-fuse cells comprisingwherein the first gate is coupled through the at least one first gate via to a first word line for receiving a first programming voltage, and the second gate is coupled through the at least one second gate via to a second word line for receiving a first reading voltage.2. The semiconductor device of claim 1 , wherein the plurality of anti-fuse cells further comprise:a second active area separate from the first active area; andat least one third gate via coupled to the first gate and disposed directly above the second active area;wherein the first gate is further coupled through the at least one third gate via to the first word line for receiving the first programming voltage.3. The semiconductor device of claim 2 , wherein the plurality of anti-fuse cells further comprise:at least one conductive ...

DATA PROCESSING CIRCUIT AND DEVICE

An embodiment provides a data processing circuit and a device. The circuit includes: a first bank group and a second bank group a write circuit and a read circuit The write circuit includes a write input cache circuit and is configured to: receive stored data from a write bus through the write input cache circuit write the stored data into the first bank group through a first read-write bus and write the stored data into the second bank group through a second read-write bus The read circuit includes a read output cache circuit and is configured to: read the stored data from the first bank group through the first read-write bus and read the stored data from the second bank group through the second read-write bus 1. A data processing circuit , comprising:a first bank group and a second bank group;a write circuit, comprising a write input cache circuit, the write circuit being configured to: receive stored data from a write bus through the write input cache circuit, write the stored data into the first bank group through a first read-write bus, and write the stored data into the second bank group through a second read-write bus; anda read circuit, comprising a read output cache circuit, the read circuit being configured to: read the stored data from the first bank group through the first read-write bus, read the stored data from the second bank group through the second read-write bus, and transmit the stored data to a read bus through the read output cache circuit.2. The data processing circuit according to claim 1 , wherein the write circuit further comprises:a write control circuit, respectively connected to the write input cache circuit, a first write output cache circuit and a second write output cache circuit, the write control circuit being configured to transmit the stored data transmitted by the write input cache circuit to the first write output cache circuit or the second write output cache circuit;the first write output cache circuit, connected to the first ...

MEMORY DEVICE WITH STRAP CELLS

A device includes a memory array. The memory array includes a first sub-bank, a first strap cell coupled to the first sub-bank, and a first continuous data line. The first continuous data line includes a first portion and a second portion coupled to the first sub-bank via the first strap cell. The first portion of the first continuous data line is disposed above the first strap cell and the second portion of the first continuous data line is disposed above the first portion of the first continuous data line. 1. A device , comprising: a first sub-bank;', 'a first strap cell coupled to the first sub-bank; and', 'a first continuous data line comprising a first portion and a second portion coupled to the first sub-bank via the first strap cell,', 'wherein the first portion of the first continuous data line is disposed above the first strap cell and the second portion of the first continuous data line is disposed above the first portion of the first continuous data line., 'a memory array, comprising2. The device of claim 1 , wherein the memory array further comprises:a second sub-bank, wherein the first strap cell is arranged between the first sub-bank and the second sub-bank; anda data line coupled to the second sub-bank;wherein the first portion of the first continuous data line and the data line are disposed at separate layers.3. The device of claim 2 , wherein the memory array further comprises:a continuous power line comprising a first portion and a second portion, wherein the first portion of the continuous power line is coupled to the first sub-bank, and the second portion of the continuous power line is disposed across the second sub-bank;wherein the continuous power line and the first continuous data line are disposed at separate layers.4. The device of claim 1 , further comprising:a continuous power line comprising a first portion coupled to the first sub-bank and a second portion, wherein the first portion of the continuous power line and the second portion of ...

STACKED MEMORY DEVICE, A SYSTEM INCLUDING THE SAME AND AN ASSOCIATED METHOD

A stacked memory device includes: a logic semiconductor die; a plurality of memory semiconductor dies stacked with the logic semiconductor die, wherein each of the memory semiconductor dies includes a memory integrated circuit and one or more of the memory semiconductor dies is a calculation semiconductor die including a calculation unit; and through-silicon vias electrically connecting the logic semiconductor die and the plurality of memory semiconductor dies, wherein each of the calculation units is configured to perform calculations based on broadcast data and internal data and to generate calculation result data, wherein the broadcast data is commonly provided to the calculation semiconductor dies through the through-silicon vias, and the internal data is respectively read from the memory integrated circuits of the calculation semiconductor dies. 1. A method of operating a stacked memory device , the stacked memory device including calculation units in each of a plurality of calculation semiconductor dies stacked in a vertical direction , the method comprising:providing broadcast data, in common, to each of the calculation units through through-silicon vias electrically connecting the calculation semiconductor dies;providing internal data respectively read from memory integrated circuits of the calculation semiconductor dies to each of calculation units; andperforming a plurality of calculations based on the broadcast data and the internal data simultaneously using the calculation units.2. The method of claim 1 , wherein each of the calculation semiconductor dies includes a plurality of memory banks and the calculation units are disposed in the memory banks included in the calculation semiconductor dies.3. The method of claim 2 , wherein the calculation units included in the memory banks of the calculation semiconductor dies commonly receive the broadcast data and perform the calculations based on the broadcast data simultaneously.4. The method of claim 2 , ...

Semiconductor memory device, and signal line layout structure thereof

A memory device includes first and second memory blocks each including a memory cell array, a sub-word line drive region and a bit line sense amplifier region corresponding to the memory cell array, first and second data transmission lines disposed in the bit line sense amplifier region of each memory block, wherein the first and second data transmission lines extend on an identical row and transmit data of the memory cell array of the memory block, a row decoder configured to select one of the first and second memory blocks in response to a row address and enable a word line of the memory cell array included in the selected memory block, and a column decoder configured to generate, in response to a column address, first and second column select signals corresponding to the first and second data transmission lines of the bit line sense amplifier region.

DATA TRANSMISSION CIRCUIT AND METHOD, AND STORAGE DEVICE

A data transmission circuit and method, and a storage device are provided. The data transmission circuit includes a serial-parallel conversion module, a comparison module, a data conversion module and a write circuit module. The serial-parallel conversion module receives a plurality of pieces of external data in batches and outputs initial parallel data according to the external data. The comparison module compares the received initial parallel data with global data to output a comparison result. The data conversion module, responsive to that the comparison result indicates that the preset threshold is exceeded, inverts the initial parallel data and transmits the inverted data to a data bus, and responsive to that the comparison result indicates that the preset threshold is not exceeded, transmits the initial parallel data to the data bus. The write circuit module transmits data on the data bus to a global data bus. 1. A data transmission circuit , comprising:a serial-parallel conversion module configured to receive a plurality of pieces of external data in batches and output initial parallel data according to the external data, wherein a preset bit width of the initial parallel data is equal to a sum of bit widths of the plurality of pieces of external data;a comparison module configured to receive global data on a global data line and the initial parallel data, and compare the initial parallel data with the global data to output a comparison result of whether a number of bits of the initial parallel data which are different from the global data exceeds a preset threshold, wherein the initial parallel data and the global data have identical preset bit widths;a data conversion module electrically connected to the serial-parallel conversion module, the comparison module and a data bus, and configured to, responsive to that the comparison result indicates that the preset threshold is exceeded, invert the initial parallel data and transmit the inverted data to the data ...

Semiconductor device and continuous reading method

The invention provides a semiconductor device and a continuous reading method for suppressing fluctuations of a precharging voltage caused by an increase in a precharging time. The continuous reading method of a NAND flash memory of the invention includes the following steps: a first voltage (VCLMP1+Vth) is applied to a gate of a transistor (BLCLAMP) connected to a bit line and a voltage is supplied to the bit line via the transistor (BLCLAMP) to start precharging of the bit line; and a second voltage (VCLMP1+Vth−α) lower than the first voltage is applied to the gate of the transistor (BLCLAMP) when the precharging time caused by the application of the first voltage has elapsed for a certain period of time.

DATA TRANSMISSION CIRCUIT AND METHOD, AND STORAGE APPARATUS

A data transmission circuit includes: a comparison circuit, configured to compare received first data on a data bus with received second data on a global data line and output a comparison result of whether a number of different bits between the first data and the second data exceeds a preset threshold; a data conversion circuit, configured to: if the comparison result indicates that the number of different bits exceeds the preset threshold, invert the first data and transmit the inverted first data to the global data line, and otherwise, transmit the first data to the global data line; and a read-write conversion circuit, configured to: if the comparison result indicates that the number of different bits exceeds the preset threshold, transmit data on the global data line to a complementary local data line, and otherwise, transmit data on the global data line to a local data line. 1. A data transmission circuit , comprising:a comparison circuit, configured to receive first data on a data bus and second data on a global data line, and compare the first data with the second data to output a comparison result of whether a number of different bits between the first data and the second data exceeds a preset threshold, wherein the first data and the second data have a same preset bit width;a data conversion circuit, electrically connected to the data bus, the comparison circuit and the global data line, and configured to: invert the first data and transmit the inverted first data to the global data line in response to the comparison result indicating that the number of different bits exceeds the preset threshold, and transmit the first data to the global data line in response to the comparison result indicating that the number of different bits does not exceed the preset threshold; anda read-write conversion circuit, electrically connected to the global data line, a local data line and a complementary local data line, and configured to: transmit data on the global data ...

Output drive circuit and memory device

The present invention provides an output driving circuit and a memory device. The output driving circuit is provided with a pull-up pre-amplification unit and a pull-down pre-amplification unit between a signal input terminal and a signal output terminal, the pull-up pre-amplification unit and the pull-down pre-amplification unit adjust the duty cycle ratios of the positive input signal and the negative input signal so that the duty cycle ratios of the output signals at the signal output terminal is the same as that of the input signal at the signal input terminal, which avoids the mismatch of output impedance under different output voltages, thereby eliminating the problem of duty cycle ratio deviation of the output signal that affects the signal quality.

STORAGE DEVICE

A storage device includes a memory, a write circuit, a read circuit, and a debug information register. The memory includes a data area and a redundant area that corresponds to the data area. The write circuit writes first data specified in a write command to the data area, and first information about a transmission source which has transmitted the write command, to the redundant area. The read circuit reads the first data as second data from the data area, and reads the first information as second information from the redundant area, in response to a read command. The debug information register stores the second information read by the read circuit. 1. A storage device comprising:a memory that includes a data area and a redundant area that corresponds to the data area;a write circuit configured to write first data specified in a write command to the data area, and write first information about a transmission source which has transmitted the write command, to the redundant area;a read circuit configured to read the first data as second data from the data area, and read the first information as second information from the redundant area, in response to a read command; anda first storage circuit configured to store the second information read by the read circuit.2. The storage device according to claim 1 , wherein the read circuit is configured to return the second data and the second information to a read destination which has transmitted the read command.3. The storage device according to claim 2 , wherein the read destination of the read command is a first central processing unit (CPU) and the transmission source of the write command is a second CPU claim 2 , and the second information includes information indicating the second CPU.4. The storage device according to claim 3 , wherein the second information is provided to the first CPU and the first CPU is configured to detect whether or not data written by the first CPU to the data area has been overwritten by the ...

DEVICES, MEMORY DEVICES, AND ELECTRONIC SYSTEMS

A semiconductor device comprises a stack structure comprising decks each comprising a memory level comprising memory elements, a control logic level vertically adjacent and in electrical communication with the memory level and comprising control logic devices configured to effectuate a portion of control operations for the memory level, and an additional control logic level vertically adjacent and in electrical communication with the memory level and comprising additional control logic devices configured to effectuate an additional portion of the control operations for the memory level. A memory device, a method of operating a semiconductor device, and an electronic system are also described. 1. A device , comprising: a first memory level comprising first memory cells;', 'a first control logic level underlying the first memory level and comprising first control logic devices comprising first thin film transistors, the first control logic devices configured to effectuate a portion of control operations for the first memory level; and', 'a second control logic level overlying the first memory level and comprising second control logic devices comprising second thin film transistors, the second control logic devices configured to effectuate an additional portion of the control operations for the first memory level., 'a first stack structure comprising2. The device of claim 1 , wherein the first control logic devices and the second control logic devices comprise complementary metal oxide semiconductor devices.3. The device of claim 1 , wherein the first stack structure further comprises:a second memory level comprising second memory cells overlying the second control logic level, the second control logic devices of the second control logic level configured to effectuate a portion of control operations for the second memory level; anda third control logic level overlying the second memory level and comprising third control logic devices comprising third thin film ...

MEMORY DEVICE WITH STRAP CELLS

A device includes a memory array. The memory array includes a first sub-bank, a second sub-bank, a strap cell and a continuous data line. The strap cell is arranged between the first sub-bank and the second sub-bank. The continuous data line includes a first portion coupled to the first sub-bank and a second portion disposed across the second sub-bank. The first portion of the continuous data line and the second portion of the continuous data line are disposed at separate layers above the strap cell. 1. A device , comprising: a first sub-bank;', 'a second sub-bank;', 'a strap cell arranged between the first sub-bank and the second sub-bank; and', 'a continuous data line comprising a first portion coupled to the first sub-bank and a second portion disposed across the second sub-bank,', 'wherein the first portion of the continuous data line and the second portion of the continuous data line are disposed at separate layers above the strap cell., 'a memory array including2. The device of claim 1 , wherein the memory array further includes a data line coupled to the second sub-bank claim 1 , wherein the data line is disconnected from the continuous data line.3. The device of claim 2 , wherein the continuous data line and the data line are coupled to a first input/output (I/O) circuit.4. The device of claim 1 , further comprising:a first continuous power line comprising a first portion and a second portion, wherein the first portion of the first continuous power line is coupled to the first sub-bank, and the second portion of the first continuous power line is disposed across the second sub-bank.5. The device of claim 4 , wherein the first portion of the first continuous power line and the second portion of the first continuous power line are disposed at separate layers above the strap cell.6. The device of claim 4 , further comprising:a second power line coupled to the second sub-bank.7. The device of claim 6 , further comprising:a power control module configured to ...

Counter readout circuit

A counter readout circuit includes a plurality of counter registers and an output data computing unit. The plurality of counter registers, each includes a counter which counts per clock signal cycle. The output data computing unit includes a computing unit which adds, for output, the counter value of a counter register to the total clock count from a first timing to a second timing. The counter register is selected from the plurality of counter registers. The first timing is common to all of the plurality of counter registers. The second timing is a timing of selection of the selected counter register.

PROCESSING-IN-MEMORY (PIM) DEVICE

A PIM device includes a plurality of first storage regions, a second storage region, and a column control circuit. The second storage region is coupled to each of the plurality of first storage regions through a data transmission line. The column control circuit generates a memory read control signal for reading data stored in an initially selected storage region of the plurality of first storage regions and a buffer write control signal for writing the data read from the initially selected storage region to the second storage region. The column control circuit generates a global buffer read control signal for reading the data written to the second storage region and a memory write control signal for writing the data read from the second storage region to a subsequently selected storage region of the plurality of first storage regions. 1. A method for operating a processing-in-memory (PIM) device including at least a first storage region and a second storage region , the method comprising:accessing a column coupled to a first row of a first memory bank of the first storage region, reading data stored in a memory cell coupled to the column, and writing the data read from the memory cell coupled to the column coupled to the first row of the first memory bank to a global buffer of the second storage region; andreading the data written to the global buffer, accessing a column coupled to a second row of the first memory bank of the first storage region or a third row of a second memory bank of the first memory region, and writing the data read from the global buffer to a memory cell coupled to the second row or the third row.2. The method according to claim 1 , further comprising:enabling, before the writing to the global buffer, the first row of the first memory bank of the first storage region.3. The method according to claim 1 , further comprising:enabling, after the writing to the global buffer, the second row or the third row.4. The method according to claim 1 , ...

MEMORY DEVICE WITH STRAP CELLS

A device disclosed includes first and second rows of memory cells, a first data line, and a first continuous data line. The first and second rows of memory cells are arranged in a first sub-bank and a second sub-bank, separated from the first sub-bank, respectively. The first data line is arranged across the first sub-bank and coupled to a first memory cell in the first row of memory cells. The first continuous data line includes a first portion arranged across the first sub-bank and a second portion arranged across the second sub-bank. The first continuous data line is coupled to a second memory cell in the second row of memory cells. The first portion of the first continuous data line is disposed in a first metal layer. The first data line and the second portion of the first continuous data line are in a second metal layer. 1. A device , comprising:a first row of memory cells arranged in a first sub-bank and a second row of memory cells arranged in a second sub-bank separated from the first sub-bank;a first data line arranged across the first sub-bank and coupled to a first memory cell in the first row of memory cells; anda first continuous data line comprising a first portion arranged across the first sub-bank and a second portion arranged across the second sub-bank, wherein the first continuous data line is configured to be coupled to a second memory cell in the second row of memory cells;wherein the first portion of the first continuous data line is disposed in a first metal layer, andthe first data line and the second portion of the first continuous data line are disposed in a second metal layer different from the first metal layer.2. The device of claim 1 , further comprising:a strap cell arranged between the first sub-bank and the second sub-bank, wherein the strap cell separates the first data line from the second portion of the first continuous data line.3. The device of claim 2 , further comprising:a continuous power line comprising a first portion and a ...

MEMORY CIRCUIT

A data receiving stage circuit of a memory circuit receives a serial input signal and a chip enable signal. A data writing circuit of the memory circuit generates at least one of a command signal and a data signal according to the serial input signal. A power supply circuit of the memory circuit generates an operating voltage for a memory cell array to perform a data access operation. A data output stage circuit of the memory circuit outputs a readout data. A controller of the memory circuit performs a switching operation of an operating state of the memory circuit according to a change of the chip enable signal. The controller determines a disable or enable state of the data receiving stage circuit, the data writing circuit, the power supply circuit, and the data output stage circuit according to the operating state. 1. A memory circuit , having a memory cell array , and comprising:a data receiving stage circuit, configured to receive a serial input signal and a chip enable signal;a data writing circuit, coupled to the data receiving stage circuit, and configured to generate at least one of a command signal and a data signal according to the serial input signal;a power supply circuit, configured to generate an operating voltage for the memory cell array to perform a data access operation;a data output stage circuit, coupled to the memory cell array, and configured to output a readout data; and perform a switching operation of an operating state of the memory circuit according to a changing state of the chip enable signal; and', 'determine a disable or enable state of the data receiving stage circuit, the data writing circuit, the power supply circuit and the data output stage circuit according to the operating state of the memory circuit., 'a controller, coupled to the data writing circuit and the power supply circuit, and configured to2. The memory circuit as claimed in claim 1 , wherein the operating state comprises a standby state claim 1 , an active state and a ...

SEMICONDUCTOR DEVICE, ELECTRONIC DEVICE, DATA TRANSMISSION METHOD, TIMING CONTROLLER, AND VEHICLE

A semiconductor device, includes: a data input pin; a data output pin; an internal circuit; a register accessible by the internal circuit; and a transceiver circuit including a transfer buffer and configured to: write data input through the data input pin to the transfer buffer, and output the data through the data output pin; and transfer data stored in the transfer buffer to the register when a transfer command is input through the data input pin. 1. A semiconductor device , comprising:a data input pin;a data output pin;an internal circuit;a register accessible by the internal circuit; and write data input through the data input pin to the transfer buffer, and output the data through the data output pin; and', 'transfer data stored in the transfer buffer to the register when a transfer command is input through the data input pin., 'a transceiver circuit including a transfer buffer and configured to2. The device of claim 1 , wherein the transceiver circuit is configured to write at least write data and an address to the transfer buffer and to output the at least write data and the address through the data output pin.3. The device of claim 1 , wherein the transceiver circuit is configured to directly write the data input through the data input pin to the register in a direct mode.4. The device of claim 1 , wherein the device is a timing controller.5. A semiconductor device for writing data to a slave device claim 1 , comprising:a data output pin connected to a data input pin of the slave device;a data input pin connected to a data output pin of the slave device; and output a write command, and an address and first write data following the write command through the data output pin while receiving second write data output from the slave device through the data input pin; and', 'output a transfer command through the data output pin when the second write data matches the first write data., 'a transceiver circuit configured to6. The device of claim 5 , wherein the ...

MEMORY SYSTEM

A semiconductor memory device includes a memory cell array, an input/output circuit configured to output read data from the semiconductor memory device, a first data latch configured to latch data read from the memory cell array as the read data, a second data latch to which the read data is transferred from the first data latch and from which the read data is transferred to the input/output circuit, a signaling circuit configured to output a ready signal or a busy signal, and a control circuit configured to control the signaling circuit to output the busy signal while the read data is being latched in the first data latch during a read operation performed on the memory cell array and to output the ready signal while the read data latched in the first data latch is being transferred from the first latch to the second latch. 1. A semiconductor memory device comprising:a memory cell array;an input/output circuit configured to output read data from the semiconductor memory device;a first data latch configured to latch data read from the memory cell array as the read data;a second data latch to which the read data is transferred from the first data latch and from which the read data is transferred to the input/output circuit;a signaling circuit configured to output a ready signal or a busy signal; anda control circuit configured to control the signaling circuit to output the busy signal while the read data is being latched in the first data latch during a read operation performed on the memory cell array and to output the ready signal while the read data latched in the first data latch is being transferred from the first latch to the second latch.2. The semiconductor memory device according to claim 1 , wherein the input/output circuit receives commands through the input/output pins while the read data latched in the first data latch is being transferred from the first latch to the second latch.3. The semiconductor memory device according to claim 1 , wherein the ...

FERROELECTRIC FET-BASED CONTENT ADDRESSABLE MEMORY

An efficient FeFET-based CAM is disclosed which is capable of performing normal read, write but has the ability to match input data with don't-care. More specifically, a Ferroelectric FET Based Ternary Content Addressable Memory is disclosed. The design in some examples utilizes two FeFETs and four MOSFETs per cell. The CAM can be written in columns through multi-phase writes. It can be used a normal memory with indexing read. It also has the ability for ternary content-based search. The don't-care values can be either the input or the stored data. 1. A memory device , comprising: a matchline (“ML”) switching transistor; and', 'a serial combination of a ferroelectric field-effect transistor (“FeFET”) and an input switching transistor,, 'a first and second data storage units, each adapted to store one binary bit, each of data storage units includingthe ML switching transistors of the first and second data storage units being connected to each other at a junction, forming a serial combination having a first end and a second end,one end of the serial combination of the FeFET and input switching transistor in the first data storage units being connected to the first end of the serial combination of the ML switching transistors at a junction, and one end of the serial combination of the FeFET and input switching transistor in the second data storage units being connected to the junction between the ML switching transistors.2. The memory device of claim 1 , wherein the FeFET in each of the first and second data storage units has a gate claim 1 , a source and a drain claim 1 , the drain of the FeFET in the first data storage unit being connected to the first end of the serial combination of the ML switching transistors claim 1 , and the drain of the FeFET in the second data storage unit being connected to the junction between the ML switching transistors.3. The memory device of claim 2 , wherein each of the ML switching transistors and input switching transistors is a ...

CHANNEL EQUALIZATION FOR MULTI-LEVEL SIGNALING

A memory interface may include a transmitter that generates multi-level signals made up of symbols that convey multiple bits of data. The transmitter may include a first data path for a first bit (e.g., a least significant bit (LSB)) in a symbol and a second data path for a second bit (e.g., the most significant bit (MSB)) in the symbol. Each path may include a de-emphasis or pre-emphasis buffer circuit that inverts and delays signals received at the de-emphasis or pre-emphasis buffer circuit. The delayed and inverted data signals may control de-emphasis or pre-emphasis drivers that are configured to apply de-emphasis or pre-emphasis to a multi-level signal. 1. An apparatus , comprising:a first driver configured to generate a first electrical pulse representative of a first data bit;a second driver coupled with the first driver and configured to reduce an amplitude of the first electrical pulse generated by the first driver;a third driver configured to generate a second electrical pulse representative of a second data bit; anda fourth driver configured to reduce an amplitude of the second electrical pulse generated by the second driver2. The apparatus of claim 1 , wherein the first data bit comprises a least significant bit of a symbol of a multilevel signal and the second data bit comprises a most significant bit of the symbol claim 1 , and wherein the symbol is a combination of the first electrical pulse and the second electrical pulse and the multilevel signal is modulated according pulse amplitude modulation scheme comprising three or more levels.3. The apparatus of claim 2 , further comprising:a fifth driver configured to generate the second electrical pulse in conjunction with the third driver; anda sixth driver configured to partially reduce the amplitude of the second electrical pulse in conjunction with the fourth driver.4. The apparatus of further comprising:a controller configured to enable the second driver based at least in part on the amplitude of the ...

SEMICONDUCTOR DEVICE AND SEMICONDUCTOR MEMORY DEVICE

A semiconductor device includes an output driver having a variable current driving ability, for outputting an amplified data signal to the outside through a transmission line; a nonvolatile memory having a specific area for storing output adjustment data to adjust the current driving ability of the output driver; an output adjustment data readout unit for reading out the output adjustment data from the specific area of the memory in response to powering on; and a current driving ability adjustment unit for adjusting the current driving ability of the output driver on the basis of the output adjustment data read out from the memory. 1. A semiconductor device comprising:an output driver having a variable current driving ability, for outputting an amplified data signal to outside through a transmission line;a nonvolatile memory having a specific area for storing output adjustment data to adjust the current driving ability of the output driver;an output adjustment data readout unit for reading out the output adjustment data from the specific area of the memory in response to powering on; anda current driving ability adjustment unit for adjusting the current driving ability of the output driver on a basis of the output adjustment data read out from the memory.2. The semiconductor device according to claim 1 , whereinthe memory has a data area in which a data storage address is specified by a data address, and a power-on detector for generating a power-on detection signal in response to powering on;', 'a selector for selecting a specific address specifying the address of the specific area, out of the specific address and the data address, and supplying the specific address to the memory in response to the power-on detection signal only during a predetermined period; and', 'a readout signal supply unit for supplying a readout signal to the memory in response to the power-on detection signal., 'the output adjustment data readout unit includes3. The semiconductor device ...

Synapse circuit with memory

A synapse circuit with an arrayed structured memory for machine learning applications is disclosed. The synapse circuit comprises a controlled variable resistance, a controlled switch connected to a contact terminal of the controlled variable resistance, and a memory cell for storing a weight variable. The memory cell is operatively connected to a control terminal of the controlled switch. A control terminal of the controlled variable resistance is configured for receiving an activation signal. The controlled variable resistance has a first resistance value and a second resistance value substantially larger than the first resistance value. A ratio of the second resistance value to the first resistance value is at least one hundred. A current, flowing through the controlled switch and the controlled variable resistance, (1) is indicative of the activation signal weighted by the stored weight variable if the controlled variable resistance is the first resistance value and (2) is smaller or equal to one picoampere at room temperature if the controlled variable resistance is adopting the second resistance value.

SEMICONDUCTOR MEMORY DEVICE, CONTROLLER, STORAGE DEVICE HAVING THE SAME, AND OPERATING METHOD THEREOF

A controller controls an operation of a semiconductor memory device. The controller includes an erased page search controller, a command generator, and a data receiver. The erased page search controller determines a search mode of the semiconductor memory device, selects a page to search for, among a plurality of pages, based on the search mode, and generates a search control signal corresponding to a selected page. The command generator generates a search read command for the selected page based on the search control signal. The data receiver receives, from the semiconductor memory device, search read data corresponding to the search read command. The search read command is a command for controlling the semiconductor memory device to perform a read operation by applying a read voltage to multiple word lines including a word line corresponding to the selected page. 1. A controller controlling an operation of a semiconductor memory device , comprising:an erased page search controller determining a search mode of the semiconductor memory device, selecting a page to search for, among a plurality of pages, based on the search mode, and generating a search control signal corresponding to a selected page;a command generator generating a search read command for the selected page based on the search control signal; anda data receiver receiving, from the semiconductor memory device, search read data corresponding to the search read command,wherein the search read command is a command for controlling the semiconductor memory device to perform a read operation by applying a read voltage to multiple word lines including a word line corresponding to the selected page.2. The controller of claim 1 , wherein the data receiver transfers the search read data to the erased page search controller claim 1 , andwherein the erased page search controller determines whether the selected page is an initially erased page on the basis of the search read data.3. The controller of claim 2 , ...

MEMORY DEVICES

A semiconductor device comprises a stack structure comprising decks each comprising a memory level comprising memory elements, a control logic level vertically adjacent and in electrical communication with the memory level and comprising control logic devices configured to effectuate a portion of control operations for the memory level, and an additional control logic level vertically adjacent and in electrical communication with the memory level and comprising additional control logic devices configured to effectuate an additional portion of the control operations for the memory level. A memory device, a method of operating a semiconductor device, and an electronic system are also described. 120.-. (canceled)21. A memory device , comprising: [ rows of memory elements extending in the first horizontal direction; and', 'columns of memory elements extending in the second horizontal direction;, 'two vertically neighboring memory levels, each of the two vertically neighboring memory levels comprising, a first control logic level comprising control logic circuitry configured to control operations on the rows of memory elements of at least one of the two vertically neighboring memory levels; and', 'a second control logic level comprising additional control logic circuitry configured to control operations on the columns of memory elements of at least one of the two vertically neighboring memory levels;, 'two vertically neighboring control logic levels, comprising], 'a first stack structure neighboring a second stack structure in a first horizontal direction and a third stack structure in a second horizontal direction orthogonal to the second horizontal direction, each of the first stack structure, the second stack structure, and the third stack structure comprisinga first socket region interposed between the first stack structure and the second stack structure in the first horizontal direction, the first socket region comprising first interconnect structures coupled to and ...

SENSE ARCHITECTURE

Devices and methods for a sensing scheme are described. A device may include a memory array and a column select line configured to couple with a single page of a set of pages within the memory array when the single page is selected during an access operation. The column select line may be isolated from other pages (e.g., unselected pages) of the set. The device may include a set of sense component groups coupled with the single page. Each sense component group of the set may be configured to access one or more memory cells of the single page using the column select line. The device may include a decoding component configured to couple a sense component group of the set with an I/O line of an I/O channel. The device may communicate information with the I/O line during the access operation. 1. A device , comprising:a memory array comprising a plurality of pages that each comprise a memory cell;a column select line that is configured to couple with a single page of the plurality of pages based at least in part on the single page being accessed; anda plurality of sense component groups coupled with the single page of the plurality of pages, each sense component group of the plurality of sense component groups configured to access the memory cell of the single page using the column select line.2. The device of claim 1 , further comprising:a decoding component configured to couple a sense component group of the plurality of sense component groups with an input/output (I/O) line of an I/O channel.3. The device of claim 2 , wherein the decoding component comprises at least one transistor configured to selectively couple at least one sense component group of the plurality of sense component groups with at least one I/O line of the I/O channel using a sense output select line.4. The device of claim 2 , wherein the I/O line of the I/O channel is configured to couple with a voltage source to precharge a node of the single page during a read operation.5. The device of claim 1 , ...

CONTROLLER, MEMORY SYSTEM, AND OPERATING METHODS THEREOF

A memory system includes a nonvolatile memory device and a controller configured to control the nonvolatile memory device. The nonvolatile memory device includes a first data storage region in which a memory cell stores one-bit data in a first mode and a second data storage region in which a memory cell stores two-bit or more data in a second mode. The controller controls the nonvolatile memory device to perform a read operation on the first data storage region and the second data storage region in the second mode. The controller decodes first data read from the first data storage region, and decodes second data read from the second data storage region. The controller controls the nonvolatile memory device to perform the read operation on the first data storage region in the second mode. 115-. (canceled)16. A memory system comprising:a nonvolatile memory device includes a first data storage region storing one-bit data per cell and a second data storage region storing two-bit or more data per cell; anda controller configured to:select one first read voltage among a plurality of read voltages for reading the second data storage region,change the selected first read voltage to a second read voltage for reading the first data storage region, andsimultaneously read the first and second data storage regions using the plurality of read voltages and the second read voltage.17. The memory system of claim 16 ,wherein the controller decodes, as data of a single level cell (SLC) mode, first data read from the first data storage region using the second read voltage, andwherein the controller decodes, as data of a multi-level cell (MLC) mode, second data read from the second data storage region using the plurality of read voltages.18. The memory system of claim 16 , wherein the first and second data storage regions are simultaneously read in a way-interleaving scheme.19. The memory system of claim 16 , wherein the controller selects claim 16 , as the first read voltage claim 16 , ...

Memory system and method using stacked memory device dice, and system using the memory system

A memory system and method uses stacked memory device dice coupled to each other and to a logic die. The logic die may include a timing correction system that is operable to control the timing at which the logic die receives signals, such as read data signals, from each of the memory device dice. The timing correction controls the timing of the read data or other signals by adjusting the timing of respective strobe signals, such as read strobe signals, that are applied to each of the memory device dice. The memory device dice may transmit read data to the memory device at a time determined by when it receives the respective strobe signals. The timing of each of the strobe signals is adjusted so that the read data or other signals from all of the memory device dice are received at the same time.

Stack access control for memory device

Apparatuses and methods including an interface die that interfaces with dice through memory channels are described. An example apparatus includes a first die. The first die receives a first command including first command information and second command information provided after the first command information. The first die changes an order of providing the first command information and the second command information and provides a second command to a second die, the second command including the second command information and the first command information provided after the second command information in the changed order. The first command information is related to a command function and the second command information is related to a destination of the command function.

Method for writing data in a memory of a contactless transponder, and corresponding contactless transponder device

A contactless transponder includes a non-volatile static random access memory including memory points. Each memory point is formed by a volatile memory cell and a non-volatile memory cell. A protocol processing circuit receives data and stores the received data in the volatile memory cells of the memory. A write processing circuit is configured, at the end of the reception and storage of the data, to record, in a single write cycle, the data from the volatile memory cells to the non-volatile memory cells of the respective memory points.

SEMICONDUCTOR STORAGE DEVICE

A semiconductor storage device includes a first input driver configured to receive a first signal from a memory controller, a second input driver configured to receive a chip enable signal from the memory controller, and a first control circuit. The first control circuit is configured to set the semiconductor storage device in an enabled state or a disabled state depending on whether or not the first signal which is received during a time period that starts with assertion of the chip enable signal and is prior to receipt of a command sequence, corresponds to a first chip address. 1. A semiconductor storage device , comprising:a first input driver configured to receive a first signal from a memory controller;a second input driver configured to receive a chip enable signal from the memory controller; anda first control circuit configured to set the semiconductor storage device in an enabled state or a disabled state depending on whether or not the first signal which is received during a time period that starts with assertion of the chip enable signal and is prior to receipt of a command sequence, corresponds to a first chip address.2. The semiconductor storage device according to claim 1 , whereinthe first control circuit is configured to determine whether or not the first signal corresponds to the first chip address, in synchronization with the assertion of the chip enable signal.3. The semiconductor storage device according to claim 1 , whereinthe first control circuit is configured to determine whether or not the first signal corresponds to the first chip address, after the assertion of the chip enable signal.4. The semiconductor storage device according to claim 3 , whereinthe first control circuit is configured to start power supply to the first input driver in response to the assertion of the chip enable signal.5. The semiconductor storage device according to claim 4 , whereinthe first control circuit is configured to, upon determining that the first signal does ...

PHYSICAL UNCLONABLE FUNCTION DEVICE AND METHOD

An embodiment system comprises a physical unclonable function device, wherein the device comprises a first assembly of non-volatile memory cells each having a selection transistor embedded in a semiconductor substrate and a depletion-type state transistor having a control gate and a floating gate that are electrically connected, the state transistors having respective effective threshold voltages belonging to a common random distribution, and a processing circuit configured to deliver, to an output interface of the device, a group of output data based on a reading of the effective threshold voltages of the state transistors of the memory cells of the first assembly.

Method of controlling on-die termination and system performing the same

enabling the ODT circuits of a write target memory rank and non-target memory ranks among the plurality of memory ranks during a write operation; and disabling the ODT circuit of a read target memory rank among the plurality of memory ranks while enabling the ODT circuits of non-target memory ranks among the plurality of memory ranks during a read operation.

HIGH-DENSITY HIGH-BANDWIDTH STATIC RANDOM ACCESS MEMORY (SRAM) WITH PHASE SHIFTED SEQUENTIAL READ

The present disclosure relates to a structure including a read controller configured to receive a burst enable signal and a word line pulse signal, identify consecutive read operations from storage cells accessed via a word line, precharge bit lines once during consecutive, sequential reads, and hold the word line active through N− of the consecutive read operations, and N is an integer number of the consecutive read operations. 1. A structure comprising a read controller configured to receive a burst enable signal and a word line pulse signal , identify consecutive read operations from storage cells accessed via a word line , precharge bit lines once during consecutive , sequential reads , and hold the word line active through N−1 of the consecutive read operations , wherein N is an integer number of the consecutive read operations.2. The structure of claim 1 , further comprising an array of the storage cells arranged as rows and columns.3. The structure of claim 2 , further comprising word lines that correspond to the rows of the array and bit lines that correspond to the columns of the array.4. The structure of claim 1 , wherein the holding the word line active through N−1 of the consecutive read operations is enabled by an alternative read path that senses data using a tri-buffer and a latch in parallel with the (N−1)th column read.5. The structure of claim 1 , wherein the read controller is part of a static random access memory (SRAM).6. The structure of claim 1 , wherein the precharging bit lines once during consecutive claim 1 , sequential reads and holding the word line active through N−1 of the consecutive reads occurs based on the burst enable signal and the word line pulse signal indicating that a SRAM is operating in a sequential read mode.7. The structure of claim 6 , wherein the sequential read mode hides a bit line restore time and allows an early bit line restore and early word line activation of a next word.8. The structure of claim 7 , wherein the ...

Asymmetric on-state resistance driver optimized for multi-drop ddr4

An apparatus comprising a plurality of driver circuits and a plurality of control registers. The plurality of driver circuits may be configured to modify a memory signal that transfers read data across a read line to a memory controller. The plurality of control registers may be configured to enable one or more of the driver circuits. A pull up strength and a pull down strength of the memory signal may be configured in response to how many of the plurality of driver circuits are enabled. The plurality of driver circuits implement an asymmetric pull up and pull down of the memory signal.