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Небесная энциклопедия

Космические корабли и станции, автоматические КА и методы их проектирования, бортовые комплексы управления, системы и средства жизнеобеспечения, особенности технологии производства ракетно-космических систем

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Применить Всего найдено 6979. Отображено 100.

19-01-2012 дата публикации

Solid state lighting devices with reduced crystal lattice dislocations and associated methods of manufacturing

Номер: US20120012812A1

Автор: Cem Basceri, Thomas Gehrke

Принадлежит: Micron Technology Inc

Solid state lighting devices and associated methods of manufacturing are disclosed herein. In one embodiment, a solid state lighting device includes a substrate material having a substrate surface and a plurality of hemispherical grained silicon (“HSG”) structures on the substrate surface of the substrate material. The solid state lighting device also includes a semiconductor material on the substrate material, at least a portion of which is between the plurality of HSG structures.

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Номер записи: 1

19-01-2012 дата публикации

Semiconductor light emitting device and method for manufacturing same

Номер: US20120012814A1

Автор: Hajime Nago, Koichi Tachibana, Shinya Nunoue, Tomonari SHIODA, Toshiki Hikosaka, Yoshiyuki Harada

Принадлежит: Toshiba Corp

According to one embodiment, a semiconductor light emitting device includes an n-type semiconductor layer, a p-type semiconductor layer, and a light emitting part provided therebetween. The light emitting part includes a plurality of light emitting layers. Each of the light emitting layers includes a well layer region and a non-well layer region which is juxtaposed with the well layer region in a plane perpendicular to a first direction from the n-type semiconductor layer towards the p-type semiconductor layer. Each of the well layer regions has a common An In composition ratio. Each of the well layer regions includes a portion having a width in a direction perpendicular to the first direction of 50 nanometers or more.

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Номер записи: 2

01-03-2012 дата публикации

Integrated electronic device and method for manufacturing thereof

Номер: US20120049902A1

Автор: Antonio Giuseppe Grimaldi, Corrado IACONO, Donato CORONA, Monica Micciche', Nicolo' FRAZZETTO

Принадлежит: STMICROELECTRONICS SRL

An embodiment of an integrated electronic device formed in a body of semiconductor material, which includes: a substrate of a first semiconductor material, the first semiconductor material having a first bandgap; a first epitaxial region of a second semiconductor material and having a first type of conductivity, which overlies the substrate and defines a first surface, the second semiconductor material having a second bandgap wider than the first bandgap; and a second epitaxial region of the first semiconductor material, which overlies, and is in direct contact with, the first epitaxial region. The first epitaxial region includes a first buffer layer, which overlies the substrate, and a drift layer, which overlies the first buffer layer and defines the first surface, the first buffer layer and the drift layer having different doping levels.

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Номер записи: 3

12-04-2012 дата публикации

Heterogeneous substrate, nitride-based semiconductor device using same, and manufacturing method thereof

Номер: US20120086017A1

Автор: Hyung Do YOON, Jae Hyoun Park, Kwang Hyeon BAIK, Sung Min Hwang, Yong Gon SEO

Принадлежит: KOREA ELECTRONICS TECHNOLOGY INSTITUTE

Provided are a heterogeneous substrate, a nitride-based semiconductor device using the same, and a manufacturing method thereof to form a high-quality non-polar or semi-polar nitride layer on a non-polar or semi-polar plane of the heterogeneous substrate by adjusting a crystal growth mode. A base substrate having one of a non-polar plane and a semi-polar plane is prepared, and a nitride-based nucleation layer is formed on the plane of the base substrate. A first buffer layer is grown faster in the vertical direction than in the lateral direction on the nucleation layer. A lateral growth layer is grown faster in the lateral direction than in the vertical direction on the first buffer layer. A second buffer layer is formed on the lateral growth layer. A silicon nitride layer having a plurality of holes may be formed between the lateral growth layer on the first buffer layer and the second buffer layer.

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Номер записи: 4

03-05-2012 дата публикации

Iii nitride semiconductor substrate, epitaxial substrate, and semiconductor device

Номер: US20120104558A1

Автор: Keiji Ishibashi

Принадлежит: Sumitomo Electric Industries Ltd

In a semiconductor device 100 , it is possible to prevent C from piling up at a boundary face between an epitaxial layer 22 and a group III nitride semiconductor substrate 10 by the presence of 30×10 10 pieces/cm 2 to 2000×10 10 pieces/cm 2 of sulfide in terms of S and 2 at % to 20 at % of oxide in terms of O in a surface layer 12 . By thus preventing C from piling up, a high-resistivity layer is prevented from being formed on the boundary face between the epitaxial layer 22 and the group III nitride semiconductor substrate 10 . Accordingly, it is possible to reduce electrical resistance at the boundary face between the epitaxial layer 22 and the group III nitride semiconductor substrate 10 , and improve the crystal quality of the epitaxial layer 22 . Consequently, it is possible to improve the emission intensity and yield of the semiconductor device 100.

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Номер записи: 5

10-05-2012 дата публикации

Group-iii nitride semiconductor device, method for fabricating group-iii nitride semiconductor device, and epitaxial substrate

Номер: US20120112203A1

Автор: Koji Nishizuka, Takamichi Sumitomo, Takashi Kyono, Yohei Enya, Yusuke Yoshizumi

Принадлежит: Sumitomo Electric Industries Ltd

Provided is a Group III nitride semiconductor device, which comprises an electrically conductive substrate including a primary surface comprised of a first gallium nitride based semiconductor, and a Group III nitride semiconductor region including a first p-type gallium nitride based semiconductor layer and provided on the primary surface. The primary surface of the substrate is inclined at an angle in the range of not less than 50 degrees, and less than 130 degrees from a plane perpendicular to a reference axis extending along the c-axis of the first gallium nitride based semiconductor, an oxygen concentration Noxg of the first p-type gallium nitride based semiconductor layer is not more than 5×10 17 cm −3 , and a ratio (Noxg/Npd) of the oxygen concentration Noxg to a p-type dopant concentration Npd of the first p-type gallium nitride based semiconductor layer is not more than 1/10.

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Номер записи: 6

07-06-2012 дата публикации

Compound semiconductor device and method of manufacturing the same

Номер: US20120138956A1

Автор: Atsushi Yamada, Kenji Imanishi, Sanae Shimizu, Toyoo Miyajima

Принадлежит: Fujitsu Ltd

A compound semiconductor device includes: a substrate; an electron transit layer formed over the substrate; an electron supply layer formed over the electron transit layer; and a buffer layer formed between the substrate and the electron transit layer and including Al x Ga 1-x N(0≦x≦1), wherein the x value represents a plurality of maximums and a plurality of minimums in the direction of the thickness of the buffer layer, and the variation of x in any area having a 1 nm thickness in the buffer layer is 0.5 or less.

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Номер записи: 7

21-06-2012 дата публикации

Semiconductor Device And Method Of Manufacturing The Same

Номер: US20120153261A1

Автор: Hyun-gi Hong, Jun-Youn Kim, Su-hee Chae, Young-jo Tak

Принадлежит: SAMSUNG ELECTRONICS CO LTD

Example embodiments relate to a semiconductor device and a method of manufacturing the semiconductor device. The semiconductor device may include a pre-seeding layer and a nucleation layer. The pre-seeding layer may include a first material for pre-seeding and a second material for masking so as to reduce tensile stress.

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Номер записи: 8

28-06-2012 дата публикации

Epitaxial substrate and method for manufacturing epitaxial substrate

Номер: US20120161152A1

Автор: Makoto Miyoshi, Mikiya Ichimura, Mitsuhiro Tanaka, Shigeaki Sumiya, Sota Maehara

Принадлежит: NGK Insulators Ltd

Provided is a crack-free epitaxial substrate having a small amount of warping, in which a silicon substrate is used as a base substrate. The epitaxial substrate includes a (111) single crystal Si substrate, a buffer layer, and a crystal layer. The buffer layer is formed of a first lamination unit and a second lamination unit being alternately laminated. The first lamination unit includes a composition modulation layer and a first intermediate layer. The composition modulation layer is formed of a first unit layer and a second unit layer having different compositions being alternately and repeatedly laminated so that a compressive strain exists therein. The first intermediate layer enhances the compressive strain existing in the composition modulation layer. The second lamination unit is a second intermediate layer that is substantially strain-free.

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Номер записи: 9

09-08-2012 дата публикации

Method for Growth of Indium-Containing Nitride Films

Номер: US20120199952A1

Автор: Christiane Poblenz, Mark P. D'Evelyn, Michael R. Krames

Принадлежит: Soraa Inc

A method for growth of indium-containing nitride films is described, particularly a method for fabricating a gallium, indium, and nitrogen containing material. On a substrate having a surface region a material having a first indium-rich concentration is formed, followed by a second thickness of material having a first indium-poor concentration. Then a third thickness of material having a second indium-rich concentration is added to form a sandwiched structure which is thermally processed to cause formation of well-crystallized, relaxed material within a vicinity of a surface region of the sandwich structure.

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Номер записи: 10

30-08-2012 дата публикации

Nitride based light emitting device with excellent crystallinity and brightness and method of manufacturing the same

Номер: US20120217470A1

Автор: JOO Jin, Kun Park

Принадлежит: Semimaterials Co Ltd

Disclosed is a nitride-based light emitting device having an inverse p-n structure in which a p-type nitride layer is first formed on a growth substrate. The light emitting device includes a growth substrate, a powder type seed layer for nitride growth formed on the growth substrate, a p-type nitride layer formed on the seed layer for nitride growth, a light emitting active layer formed on the p-type nitride layer, and an n-type ZnO layer formed on the light emitting active layer. The p-type nitride layer is first formed on the growth layer and the n-type ZnO layer having a relatively low growth temperature is then formed thereon instead of an n-type nitride layer, thereby providing excellent crystallinity and high brightness. A method of manufacturing the same is also disclosed.

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Номер записи: 11

30-08-2012 дата публикации

Nitride based light emitting device using silicon substrate and method of manufacturing the same

Номер: US20120217504A1

Автор: JOO Jin, Kun Park

Принадлежит: Semimaterials Co Ltd

Disclosed is a nitride-based light emitting device using a silicon substrate. The nitride-based light emitting device includes a silicon (Si) substrate, a seed layer for nitride growth formed on the silicon substrate, and a light emitting structure formed on the seed layer and having a plurality of nitride layers stacked therein. The seed layer for nitride growth is comprised of GaN powders, thereby minimizing occurrence of dislocations caused by a difference in lattice constant between a nitride layer and the silicon substrate. A method of manufacturing the same is also disclosed.

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Номер записи: 12

27-09-2012 дата публикации

Semiconductor device based on the cubic silicon carbide single crystal thin film

Номер: US20120241764A1

Автор: Masaaki Sakuta, Mitsuhiko Ogihara

Принадлежит: Oki Data Corp

A semiconductor apparatus includes a cubic silicon carbide single crystal thin film of a multilayer structure including an Al x Ga 1-x As (0.6>x≧ 0 ) layer and a cubic silicon carbide single crystal layer. The apparatus also includes a substrate on which a metal layer is formed. The multilayer structure is bonded to a surface of the metal layer with the Al x Ga 1-x As (0.6>x≧ 0 ) in direct contact with the metal layer.

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Номер записи: 13

18-10-2012 дата публикации

Semiconductor device and manufacturing method of the semiconductor device

Номер: US20120261760A1

Автор: Akira Katakami, Akiyoshi Hatada, Kazuya Okubo, Masaki HANEDA, Yuka Kase

Принадлежит: Fujitsu Semiconductor Ltd

A semiconductor device includes a semiconductor substrate, a device region including first and second parts, first and second gate electrodes formed in the first and the second parts, first and second source regions, first and second drain regions, first, second, third, and fourth embedded isolation film regions formed under the first source, the first drain, the second source, and the second drain regions, respectively. Further, the first drain region and the second source region form a single diffusion region, the second and the third embedded isolation film regions form a single embedded isolation film region, an opening is formed in a part of the single diffusion region so as to extend to the second and the third embedded isolation film regions, and the opening is filled with an isolation film.

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Номер записи: 14

25-10-2012 дата публикации

GaN FILM STRUCTURE, METHOD OF FABRICATING THE SAME, AND SEMICONDUCTOR DEVICE INCLUDING THE SAME

Номер: US20120267638A1

Автор: Joo-ho Lee, Jun-hee Choi, Mi-Jeong Song, Sang-Hun Lee

Принадлежит: SAMSUNG ELECTRONICS CO LTD

A method of fabricating a gallium nitride (GaN) thin layer structure includes forming a sacrificial layer on a substrate, forming a first buffer layer on the sacrificial layer, forming an electrode layer on the first buffer layer, forming a second buffer layer on the electrode layer, partially etching the sacrificial layer to form at least two support members configured to support the first buffer layer and define at least one air cavity between the substrate and the first buffer layer, and forming a GaN thin layer on the second buffer layer.

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Номер записи: 15

01-11-2012 дата публикации

Epitaxial substrate for electronic device and method of producing the same

Номер: US20120273759A1

Автор: Jo Shimizu, Tetsuya Ikuta, Tomohiko Shibata

Принадлежит: Dowa Electronics Materials Co Ltd

An epitaxial substrate for an electronic device, in which a lateral direction of the substrate is defined as a main current conducting direction and a warp configuration of the epitaxial substrate is adequately controlled, as well as a method of producing the epitaxial substrate. Specifically, the epitaxial substrate for an electron device, including: a Si single crystal substrate; and a Group III nitride laminated body formed by epitaxially growing plural Group III nitride layers on the Si single crystal substrate, wherein a lateral direction of the epitaxial substrate is defined as a main current conducting direction, is characterized in that the Si single crystal substrate is a p-type substrate having a specific resistance value of not larger than 0.01 Ω·cm.

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Номер записи: 16

06-12-2012 дата публикации

Nitride semiconductor light emitting element and method for manufacturing the same

Номер: US20120305934A1

Автор: Mayuko Fudeta

Принадлежит: Sharp Corp

A nitride semiconductor light emitting element has: a substrate for growth; an n-type nitride semiconductor layer formed on the substrate for growth; a light emitting layer formed on the n-type nitride semiconductor layer; and a p-type nitride semiconductor layer formed on the light emitting layer, wherein pipe holes are formed at a density of 5000 pipe holes/cm 2 or less, each of which extends substantially vertically from a surface of the n-type nitride semiconductor layer on the light emitting layer side toward the substrate and has a diameter of 2 to 200 nm.

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Номер записи: 17

06-12-2012 дата публикации

Semiconductor structure and method for forming the same

Номер: US20120305986A1

Автор: Jing Wang, Lei Guo

Принадлежит: TSINGHUA UNIVERSITY

A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a wafer; a plurality of convex structures formed on the wafer, in which every two adjacent convex structures are separated by a cavity in a predetermined pattern and arranged in an array, and the cavity between every two adjacent convex structures is less than 50 nm in width; and a first semiconductor film formed on the plurality of convex structures, in which a part of the first semiconductor film is spaced apart from the wafer.

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Номер записи: 18

27-12-2012 дата публикации

Solid state lighting devices with reduced crystal lattice dislocations and associated methods of manufacturing

Номер: US20120329191A1

Автор: Cem Basceri, Thomas Gehrke

Принадлежит: Micron Technology Inc

Solid state lighting devices and associated methods of manufacturing are disclosed herein. In one embodiment, a solid state lighting device includes a substrate material having a substrate surface and a plurality of hemispherical grained silicon (“HSG”) structures on the substrate surface of the substrate material. The solid state lighting device also includes a semiconductor material on the substrate material, at least a portion of which is between the plurality of HSG structures.

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Номер записи: 19

17-01-2013 дата публикации

Monolithic integrated semiconductor structure

Номер: US20130015503A1

Автор: Bernardette Kunert

Принадлежит: NASP III/V GMBH

A monolithic integrated semiconductor structure includes: A) an Si carrier layer, B) a layer having the composition B x Al y Ga z N t P v , wherein x=0−0.1, y=0−1, z=0−1, t=0−0.1 and v=0.9−1, C) a relaxation layer having the composition B x Al y Ga z In u P v Sb w , wherein x=0−0.1, y=0−1, z=0−1, u=0−1, v=0−1 and w=0−1, wherein w and/or u is on the side facing toward layer A) or B) smaller than, equal to, or bigger than on the side facing away from layer A) or B) and wherein v=1−w and/or y=1−u−x−z, and D) a group III/V, semiconductor material. The sum of the above stoichiometric indices for all group III elements and for all group V elements are each equal to one.

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Номер записи: 20

17-01-2013 дата публикации

Method for producing a group iii nitride semiconductor light-emitting device

Номер: US20130017639A1

Автор: Shinya Boyama, Yasuhisa Ushida

Принадлежит: Toyoda Gosei Co Ltd

The present invention is a method for producing a light- emitting device whose p contact layer has a p-type conduction and a reduced contact resistance with an electrode. On a p cladding layer, by MOCVD, a first p contact layer of GaN doped with Mg is formed. Subsequently, after lowering the temperature to a growth temperature of a second p contact layer being formed in the subsequent process, which is 700° C., the supply of ammonia is stopped and the carrier gas is switched from hydrogen to nitrogen. Thereby, Mg is activated in the first p contact layer, and the first p contact layer has a p-type conduction. Next, the second p contact layer of InGaN doped with Mg is formed on the first p contact layer by MOCVD using nitrogen as a carrier gas while maintaining the temperature at 700° C. which is the temperature of the previous process.

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Номер записи: 21

24-01-2013 дата публикации

Secondary Treatment of Films of Colloidal Quantum Dots for Optoelectronics and Devices Produced Thereby

Номер: US20130019930A1

Автор: Hsiang-Yu Chen, Joseph M. Luther, Matthew C. Beard, Octavi Escala Semonin

Принадлежит: Alliance for Sustainable Energy LLC

A method of forming an optoelectronic device. The method includes providing a deposition surface and contacting the deposition surface with a ligand exchange chemical and contacting the deposition surface with a quantum dot (QD) colloid. This initial process is repeated over one or more cycles to form an initial QD film on the deposition surface. The method further includes subsequently contacting the QD film with a secondary treatment chemical and optionally contacting the surface with additional QDs to form an enhanced QD layer exhibiting multiple exciton generation (MEG) upon absorption of high energy photons by the QD active layer. Devices having an enhanced QD active layer as described above are also disclosed.

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Номер записи: 22

24-01-2013 дата публикации

Chemical vapor deposition and method of manufacturing light-emitting device using chemical vapor deposition

Номер: US20130023080A1

Автор: Bum-Joon Kim, Doek-gil Ko, Eui-joon Jeong, Jin-young Lim, Ki-Sung Kim, Young-sun Kim

Принадлежит: SAMSUNG ELECTRONICS CO LTD

A chemical vapor deposition (CVD) method includes forming a first semiconductor layer on a substrate that is mounted on a satellite disk at a first process temperature; and forming a second semiconductor layer on the first semiconductor layer at a second process temperature. Also, a method of manufacturing a light-emitting device (LED) includes: forming a quantum well layer on a substrate that is mounted on a satellite disk at a first process temperature; and forming a quantum barrier layer on the quantum well layer at a second process temperature.

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Номер записи: 23

28-02-2013 дата публикации

Deposition methods for the formation of iii/v semiconductor materials, and related structures

Номер: US20130049012A1

Автор: Christophe Figuet, Pierre Tomasini

Принадлежит: Soitec SA

Methods of forming ternary III-nitride materials include epitaxially growing ternary III-nitride material on a substrate in a chamber. The epitaxial growth includes providing a precursor gas mixture within the chamber that includes a relatively high ratio of a partial pressure of a nitrogen precursor to a partial pressure of one or more Group III precursors in the chamber. Due at least in part to the relatively high ratio, a layer of ternary III-nitride material may be grown to a high final thickness with small V-pit defects therein. Semiconductor structures including such ternary III-nitride material layers are fabricated using such methods.

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Номер записи: 24

07-03-2013 дата публикации

Nitride semiconductor light emitting device and manufacturing method thereof

Номер: US20130056747A1

Автор: Cheol Soo Sone, Jin Sub Lee, Jung Sup Kim, Seong Suk Lee, Tae Young Park

Принадлежит: Individual

A nitride semiconductor light emitting device and a manufacturing method thereof are provided. The nitride semiconductor light emitting device includes: forming a first conductivity-type nitride semiconductor layer on a substrate; forming an active layer on the first conductivity-type nitride semiconductor layer; and forming a second conductivity-type nitride semiconductor layer on the active layer. High output can be obtained by increasing doping efficiency in growing the conductivity type nitride semiconductor layer.

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Номер записи: 25

21-03-2013 дата публикации

Compound semiconductor device and method of manufacturing the same

Номер: US20130069113A1

Автор: Atsushi Yamada

Принадлежит: Fujitsu Ltd

An embodiment of a compound semiconductor device includes: a Si substrate; a Si oxide layer formed over a surface of the Si substrate; a nucleation layer formed over the Si oxide layer, the nucleation layer exposing a part of the Si oxide layer; and a compound semiconductor stacked structure formed over the Si oxide layer and the nucleation layer.

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Номер записи: 26

28-03-2013 дата публикации

Semiconductor device

Номер: US20130075786A1

Автор: Tetsuro ISHIGURO

Принадлежит: Fujitsu Ltd

A semiconductor device including a high resistance layer formed on a substrate, the high resistance layer being formed with a semiconductor material doped with an impurity element that makes the semiconductor material highly resistant; a multilayer intermediate layer formed on the high resistance layer; an electron transit layer formed with a semiconductor material on the multilayer intermediate layer; and an electron supply layer formed with a semiconductor material on the electron transit layer, wherein the multilayer intermediate layer is formed with a multilayer film in which a GaN layer and an AlN layer are alternately laminated.

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Номер записи: 27

11-04-2013 дата публикации

Nitride semiconductor wafer, nitride semiconductor device, and method for growing nitride semiconductor crystal

Номер: US20130087762A1

Автор: Hung Hung, Jongil Hwang, Naoharu Sugiyama, Shinya Nunoue, Tomonari SHIODA

Принадлежит: Toshiba Corp

According to one embodiment, a nitride semiconductor wafer includes a silicon substrate, a lower strain relaxation layer provided on the silicon substrate, an intermediate layer provided on the lower strain relaxation layer, an upper strain relaxation layer provided on the intermediate layer, and a functional layer provided on the upper strain relaxation layer. The intermediate layer includes a first lower layer, a first doped layer provided on the first lower layer, and a first upper layer provided on the first doped layer. The first doped layer has a lattice constant larger than or equal to that of the first lower layer and contains an impurity of 1×10 18 cm −3 or more and less than 1×10 21 cm −3 . The first upper layer has a lattice constant larger than or equal to that of the first doped layer and larger than that of the first lower layer.

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Номер записи: 28

25-04-2013 дата публикации

Method of manufacturing semiconductor device

Номер: US20130102131A1

Автор: Hiromu Yamaguchi, Kazuaki Tonari, Satoru Sugiyama

Принадлежит: Elpida Memory Inc

A method of manufacturing a semiconductor device wherein a film containing Si and Ge is formed on a conducting film over a substrate by using a raw material gas containing Si and a raw material gas containing Ge, includes: forming Si nuclei on the conducting film at a first ratio of a flow rate of the raw material gas containing Ge to a flow rate of the raw material gas containing Si; and forming, on the Si nuclei, a film having Si and Ge at a second ratio of the flow rate of the raw material gas containing Ge to the flow rate of the raw material gas containing Si, the second ratio being greater than the first ratio.

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Номер записи: 29

23-05-2013 дата публикации

Method for manufacturing a semiconductor device

Номер: US20130130480A1

Автор: Gil Sun Jang, Hai Won Kim, Sang Ho Woo, Sung Kill Cho

Принадлежит: Eugene Technology Co Ltd

Disclosed is a method for manufacturing a semiconductor device having a multilayer structure. The method for manufacturing a semiconductor device according to the present invention comprises the loading of a substrate into the chamber of a chemical vapor deposition apparatus and the forming of a multilayer structure in which a plurality of doped amorphous silicon layers and a plurality of insulation layers are alternately stacked. Said layers are stacked by alternately and repetitively forming the doped amorphous silicon layer on the substrate by supplying a conductive dopant and silicon precursor into the chamber where the substrate is loaded, and forming the insulation layer containing silicon on the substrate by introducing the silicon precursor and a reaction gas into the chamber where the substrate is loaded.

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Номер записи: 30

27-06-2013 дата публикации

Semiconductor devices including substrate layers and overlying semiconductor layers having closely matching coefficients of thermal expansion, and related methods

Номер: US20130161637A1

Автор: Chantal Arena, Christiaan J. Werkhoven

Принадлежит: Soitec SA

Embodiments relate to semiconductor structures and methods of forming semiconductor structures. The semiconductor structures include a substrate layer having a CTE that closely matches a CTE of one or more layers of semiconductor material formed over the substrate layer. In some embodiments, the substrate layers may comprise a composite substrate material including two or more elements. The substrate layers may comprise a metal material and/or a ceramic material in some embodiments.

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Номер записи: 31

15-08-2013 дата публикации

InGaN-Based Double Heterostructure Field Effect Transistor and Method of Forming the Same

Номер: US20130207078A1

Автор: Cao Yu, Johnson Wayne, Laboutin Oleg

Принадлежит: Kopin Corporation

A double heterojunction field effect transistor (DHFET) includes a substrate, a buffer layer consisting of GaN back-barrier buffer layer formed on the substrate, a channel layer consisting of an InGaN ternary alloy in one embodiment, and in another embodiment, InGaN/GaN superlattice (SL) formed on the GaN back-barrier buffer layer opposite to the substrate. A GaN spacer layer is formed on the InGaN or InGaN/GaN superlattice channel layer opposite to the GaN buffer layer and a carrier-supplying layer consisting of an AlInN ternary alloy is formed on the GaN spacer layer opposite to the channel layer. A preferred thickness of the GaN spacer layer is less than about 1.5 nm. The InGaN/GaN SL preferably includes 1 to 5 InGaN—GaN pairs and a preferred thickness of the InGaN layer in the InGaN/GaN SL is equal to or less than about 0.5 nm. A two-dimensional electron gas is formed at the interface between the InGaN or InGaN/GaN SL channel and GaN spacer layers. 1. A double-heterojunction field effect transistor , comprising:a) a substrate;b) a GaN back-barrier buffer layer on said substrate; [{'sub': x', '1-x, 'i) a InGaN channel layer on said GaN back-barrier buffer layer opposite said substrate, and'}, {'sub': x', '1-x, 'ii) a GaN spacer layer on said InGaN channel layer opposite said GaN back-barrier buffer layer, wherein a two-dimensional electron gas region is contained within the composite channel layer; and'}], 'c) a composite channel layer, the composite channel layer including,'}{'sub': x', '1-x, 'd) a carrier-supplying barrier layer on said GaN spacer layer opposite InGaN channel layer.'}2. The double-heterojunction field effect transistor of claim 1 , wherein the carrier-supplying barrier layer comprises AlInN.3. The double-heterojunction field effect transistor of claim 2 , wherein the carrier-supplying barrier layer comprises of AlGaN claim 2 , wherein 0.1≦z≦1.4. The double-heterojunction field effect transistor of claim 1 , wherein said GaN spacer layer is less ...

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Номер записи: 32

15-08-2013 дата публикации

Method of manufacturing compound semiconductor device

Номер: US20130210203A1

Автор: Kenji Imanishi, Toshihide Kikkawa

Принадлежит: Fujitsu Ltd

A compound semiconductor device has a buffer layer formed on a conductive SiC substrate, an AlxGa1-xN layer formed on the buffer layer in which an impurity for reducing carrier concentration from an unintentionally doped donor impurity is added and in which the Al composition x is 0<x<1, a GaN-based carrier transit layer formed on the AlxGa1-xN layer, a carrier supply layer formed on the carrier transit layer, a source electrode and a drain electrode formed on the carrier supply layer, and a gate electrode formed on the carrier supply layer between the source electrode and the drain electrode. Therefore, a GaN-HEMT that is superior in device characteristics can be realized in the case of using a relatively less expensive conductive SiC substrate compared with a semi-insulating SiC substrate.

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Номер записи: 33

22-08-2013 дата публикации

Fabrication method of nitride forming on silicon substrate

Номер: US20130217212A1

Автор: Chih-Chung Yang, Chih-Yen Chen

Принадлежит: National Taiwan University NTU

The invention is directed to a method for forming a nitride on a silicon substrate. In the method of the present invention, a silicon substrate is provided and a buffer layer is formed on the silicon substrate. The formation of the buffer layer includes a multi-level temperature modulation process having a plurality temperature levels and a plurality of temperature modulations. For each of the temperature modulations, the temperature is gradually decreased. A nitride is formed on the buffer layer.

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Номер записи: 34

29-08-2013 дата публикации

THICK NITRIDE SEMICONDUCTOR STRUCTURES WITH INTERLAYER STRUCTURES AND METHODS OF FABRICATING THICK NITRIDE SEMICONDUCTOR STRUCTURES

Номер: US20130221327A1

Автор: Burk, JR. Albert Augustus, Saxler Adam William

Принадлежит: CREE, INC.

A semiconductor structure includes a substrate, a nucleation layer on the substrate, a compositionally graded layer on the nucleation layer, and a layer of a nitride semiconductor material on the compositionally graded layer. The layer of nitride semiconductor material includes a plurality of substantially relaxed nitride interlayers spaced apart within the layer of nitride semiconductor material. The substantially relaxed nitride interlayers include aluminum and gallium and are conductively doped with an n-type dopant, and the layer of nitride semiconductor material including the plurality of nitride interlayers has a total thickness of at least about 2.0 μm. 1. A method of forming a semiconductor structure , comprising:{'sub': '2', 'heating a silicon substrate in a reactor chamber including H;'}providing a silicon-containing gas in the reactor chamber; andthereafter forming a nucleation layer on the substrate.2. The method of claim 1 , further comprising cleaning the substrate with hydrofluoric acid and/or a buffered oxide etch solution before flowing the silicon containing gas across the substrate.3. The method of claim 1 , wherein forming the nucleation layer comprises forming the nucleation layer at a temperature of 1000° C. to 1100° C.4. The method of claim 1 , wherein the silicon-containing gas comprises SiH claim 1 , SiH claim 1 , SiCl claim 1 , SiBr claim 1 , and/or SiN.5. The method of claim 1 , wherein providing the silicon-containing gas comprises flowing the silicon-containing gas across the substrate at a temperature of 1000° C. and a pressure of 0.2 atmospheres.6. The method of claim 1 , wherein the nucleation layer comprises AlN.7. The method of claim 1 , wherein a ratio of the silicon-containing gas to His 10:1.8. The method of claim 1 , wherein providing the silicon-containing gas comprises providing a silicon coating on one or more parts of the reactor claim 1 , or placing solid silicon upstream from the substrate in the reactor.9. The method of ...

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Номер записи: 35

19-09-2013 дата публикации

Method of forming a laminated semiconductor film

Номер: US20130244399A1

Автор: Mitsuhiro Okada

Принадлежит: Tokyo Electron Ltd

According to some embodiments of the present disclosures, a method of forming a laminated semiconductor film is constituted by alternately laminating first and second semiconductor films on an underlying film of each of a plurality of substrates to be processed. The method includes performing a first operation of forming the first semiconductor film and a second operation of forming the second semiconductor film until a predetermined number of laminated films are obtained. In the method, a film forming temperature in the first operation and a film forming temperature in the second operation are set to be equal to each other, and temperatures between the first and second operations are set to be constant.

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Номер записи: 36

03-10-2013 дата публикации

Method of Forming P-Type ZnO Film

Номер: US20130256654A1

Автор: Jang Won KANG, Seong Ju Park, Yong Seok Choi

Принадлежит: GWANGJU INSTITUTE OF SCIENCE AND TECHNOLOGY

Disclosed herein is a method of forming a p-type zinc oxide thin film. A zinc oxide layer and an antimony oxide layer are alternately stacked one above another on a substrate, forming a superlattice layer. The superlattice layer is modified into a p-type zinc oxide thin film by annealing. Upon annealing, zinc atoms of the zinc oxide layer are diffused into the antimony oxide layer and antimony atoms of the antimony oxide layer are diffused into the zinc oxide layer.

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Номер записи: 37

03-10-2013 дата публикации

Compound semiconductor device and method of manufacturing the same

Номер: US20130256682A1

Автор: Atsushi Yamada, Kenji Imanishi, Norikazu Nakamura, Tetsuro ISHIGURO

Принадлежит: Fujitsu Ltd

An embodiment of a method of manufacturing a compound semiconductor device includes: forming an initial layer over a substrate; forming a buffer layer over the initial layer; forming an electron transport layer and an electron supply layer over the buffer layer; and forming a gate electrode, a source electrode and a gate electrode over the electron supply layer. The forming an initial layer includes: forming a first compound semiconductor film with a flow rate ratio being a first value, the flow rate ratio being a ratio of a flow rate of a V-group element source gas to a flow rate of a III-group element source gas; and forming a second compound semiconductor film with the flow rate ratio being a second value different from the first value over the first compound semiconductor film. The method further includes forming an Fe-doped region between the buffer layer and the electron transport layer.

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Номер записи: 38

07-11-2013 дата публикации

High throughput epitaxial liftoff for releasing multiple semiconductor device layers from a single base substrate

Номер: US20130292801A1

Автор: Cheng-Wei Cheng, Kuen-Ting Shiu, Ning Li

Принадлежит: International Business Machines Corp

A semiconductor structure is provided that includes a base substrate, and a multilayered stack located on the base substrate. The multilayered stack includes, from bottom to top, a first sacrificial material layer having a first thickness, a first semiconductor device layer, a second sacrificial material layer having a second thickness, and a second semiconductor device layer, wherein the first thickness is less than the second thickness.

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Номер записи: 39

21-11-2013 дата публикации

Semiconductor device and method for manufacturing semiconductor device

Номер: US20130307023A1

Автор: Makoto Utsumi, Masayuki Iwami, Sadahiro KATOU, Takuya Kokawa

Принадлежит: ADVANCED POWER DEVICE RESEARCH ASSOCIATION

Provided is a semiconductor device that has a buffer layer with which a dislocation density is decreased. The semiconductor device includes a substrate, a buffer region formed over the substrate, an active layer formed on the buffer region, and at least two electrodes formed on the active layer. The buffer region includes at least one composite layer in which a first semiconductor layer having a first lattice constant, a second semiconductor layer having a second lattice constant that is different from the first lattice constant and formed in contact with the first semiconductor layer, and a third semiconductor layer having a third lattice constant that is between the first lattice constant and the second lattice constant are sequentially laminated.

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Номер записи: 40

21-11-2013 дата публикации

MANUFACTURING METHOD OF GaN-BASED SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE

Номер: US20130307063A1

Автор: Akinobu Teramoto, Hiroshi Kambayashi, Tadahiro Ohmi

Принадлежит: ADVANCED POWER DEVICE RESEARCH ASSOCIATION, Tohoku University NUC

Provided is a method of manufacturing a gallium-nitride-based semiconductor device, comprising forming a first semiconductor layer of a gallium-nitride-based semiconductor; and forming a recessed portion by dry etching a portion of the first semiconductor layer via a microwave plasma process using a bromine-based gas.

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Номер записи: 41

28-11-2013 дата публикации

Laminate substrate and method of fabricating the same

Номер: US20130313577A1

Автор: Shiro Sakai

Принадлежит: Seoul Optodevice Co Ltd

Embodiments of the invention provide a crystalline aluminum carbide layer, a laminate substrate having the crystalline aluminum carbide layer formed thereon, and a method of fabricating the same. The laminate substrate has a GaN layer including a GaN crystal and an AlC layer including an AlC crystal. Further, the method of fabricating the laminate substrate, which has the AlN layer including the AlN crystal and the AlC layer including the AlC crystal, includes supplying a carbon containing gas and an aluminum containing gas to grow the AlC layer.

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Номер записи: 42

05-12-2013 дата публикации

Semiconductor device and method for manufacturing the same

Номер: US20130320335A1

Автор: Shunpei Yamazaki

Принадлежит: Semiconductor Energy Laboratory Co Ltd

A semiconductor device is provided which is used as a power device for a high-power application, includes an oxide semiconductor, and has high withstand voltage and high reliability. A semiconductor device for a high-power application with high productivity is also provided. In a crystal part included in an oxide semiconductor film having a crystalline structure, a c-axis is aligned in a direction parallel to a normal vector of a surface where the oxide semiconductor film is formed or a normal vector of a surface of the oxide semiconductor film, triangular or hexagonal atomic arrangement which is seen from the direction perpendicular to the a-b plane is formed, and metal atoms are arranged in a layered manner or metal atoms and oxygen atoms are arranged in a layered manner when seen from the direction perpendicular to the c-axis.

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Номер записи: 43

19-12-2013 дата публикации

SEMICONDUCTOR DEVICE, SUPERLATTICE LAYER USED IN THE SAME, AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE

Номер: US20130334496A1

Автор: KIM Jae-kyun, KIM Jun-youn, TAK Young-jo

Принадлежит:

A semiconductor device includes a silicon substrate; a nitride nucleation layer disposed on the silicon substrate; at least one superlattice layer disposed on the nitride nucleation layer; and at least one gallium nitride-based semiconductor layer disposed on the superlattice layer. The at least one superlattice layer includes a stack of complex layers, each complex layer including a first layer and a second layer such that each of the complex layers has a plurality of nitride semiconductor layers having different compositions, at least one of the plurality of nitride semiconductor layers having a different thickness based on a location of the at least one nitride semiconductor layer within the stack, and at least one stress control layer having a thickness greater than a critical thickness for pseudomorphic growth. 1. A semiconductor device comprising:a silicon substrate;a nitride nucleation layer disposed on the silicon substrate;at least one superlattice layer disposed on the nitride nucleation layer; and a stack of complex layers, each complex layer including a first layer and a second layer such that each of the complex layers has a plurality of nitride semiconductor layers having different compositions, at least one of the plurality of nitride semiconductor layers having a different thickness based on a location of the at least one nitride semiconductor layer within the stack, and', 'at least one stress control layer having a thickness greater than a critical thickness for pseudomorphic growth, the at least one stress control layer being disposed between one of the plurality of nitride semiconductor layers and the complex layers., 'at least one gallium nitride-based semiconductor layer disposed on the superlattice layer, the at least one superlattice layer including,'}2. The semiconductor device of claim 1 , wherein the nitride nucleation layer comprises aluminum nitride (AlN).3. The semiconductor device of claim 1 , wherein each of the first layers comprises ...

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Номер записи: 44

19-12-2013 дата публикации

Manufacturing process of vertical type solid state light emitting device

Номер: US20130337598A1

Автор: Wen-Teng Liang

Принадлежит: Lextar Electronics Corp

A manufacturing process of a vertical type solid state light emitting device is provided. A substrate is provided. M metal nitride buffer layer is formed on the substrate, and a breakable structure containing M metal droplet structures is formed on the buffer layer. A first type semiconductor layer, an active layer and a second type semiconductor layer are sequentially formed on the breakable structure. A second type electrode is formed on the second type semiconductor layer. The first type semiconductor layer, the active layer, the second type semiconductor layer and the second type electrode are stacked to form a light emitting stacking structure. The breakable structure is damaged to separate from the light emitting stacking structure, so that a surface of the first type semiconductor layer of the light emitting stacking structure is exposed. A first type electrode is formed on the surface of the first type semiconductor layer.

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Номер записи: 45

09-01-2014 дата публикации

Semiconductor device

Номер: US20140008615A1

Автор: Makoto Utsumi, Masayuki Iwami, Sadahiro KATOU, Takuya Kokawa

Принадлежит: ADVANCED POWER DEVICE RESEARCH ASSOCIATION

A semiconductor device includes a substrate, a channel layer that is formed above the substrate, where the channel layer is made of a first nitride series compound semiconductor, a barrier layer that is formed on the channel layer, a first electrode that is formed on the barrier layer, and a second electrode that is formed above the channel layer. Here, the barrier layer includes a block layers and a quantum level layer. The block layer is formed on the channel layer and made of a second nitride series compound semiconductor having a larger band gap energy than the first nitride series compound semiconductor, and the quantum level layer is made of a third nitride series compound semiconductor having a smaller band gap energy than the second nitride series compound semiconductor, and has a quantum level formed therein.

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Номер записи: 46

30-01-2014 дата публикации

Device including quantum dots

Номер: US20140027713A1

Автор: Craig Breen, Jonathan S. Steckel, Marshall Cox, Zhaoqun ZHOU

Принадлежит: QD Vision Inc

A method for making a device, the method comprising: depositing a layer comprising quantum dots over a first electrode, the quantum dots including ligands attached to the outer surfaces thereof; treating the surface of the deposited layer comprising quantum dots to remove the exposed ligands; and forming a device layer thereover. Also disclosed is a device made in accordance with the disclosed method. Another aspect of the invention relates to a device comprising a first electrode and a second electrode, and a layer comprising quantum dots between the two electrodes, the layer comprising quantum dots deposited from a dispersion that have been treated to remove exposed ligands after formation of the layer in the device. Another aspect of the invention relates to a device comprising a first electrode and a second electrode, a layer comprising a first inorganic semiconductor material disposed between the first and second electrodes, and a plurality of quantum dots disposed between the first and second electrodes, the outer surface of the quantum dots comprising a second inorganic semiconductor material, wherein the composition of the first inorganic semiconductor material and the second inorganic semiconductor material is the same (without regard to any ligands on the outer surface of the quantum dot).

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Номер записи: 47

27-02-2014 дата публикации

Method for Producing an Optoelectronic Semiconductor Chip

Номер: US20140057417A1

Автор: Andreas Biebersdorf, Anton Vogl, Christian Leirer, Joachim Hertkorn, Rainer Butendeich, Tetsuya Taki

Принадлежит: OSRAM Opto Semiconductors GmbH

A method for producing an optoelectronic semiconductor chip is disclosed. A growth substrate is provided in an epitaxy installation. At least one intermediate layer is deposited by epitaxy on the growth substrate. A structured surface that faces away from the growth substrate is produced on the side of the intermediate layer facing away from the growth substrate. An active layer is deposited by epitaxy on the structured surface. The structured surface is produced in the epitaxy installation and the active layer follows the structuring of the structured surface at least in some regions in a conformal manner or at least in some sections essentially in a conformal manner.

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Номер записи: 48

06-03-2014 дата публикации

Nitride semiconductor wafer

Номер: US20140061665A1

Автор: TADAYOSHI TSUCHIYA

Принадлежит: Hitachi Metals Ltd

A nitride semiconductor wafer includes a substrate, and a buffer layer formed on the substrate and including an alternating layer of Al x Ga 1-x N (0≦x≦0.05) and Al y Ga 1-y N (0<y≦1 and x<y) layers. Only the Al y Ga 1-y N layer in the alternating layer is doped with an acceptor.

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Номер записи: 49

06-03-2014 дата публикации

EPITAXIAL GROWTH OF IN-PLANE NANOWIRES AND NANOWIRE DEVICES

Номер: US20140064312A1

Автор: Brueck Steven R.J., Lee Seung Chang

Принадлежит: STC.UNM

Exemplary embodiments provide semiconductor nanowires and nanowire devices/applications and methods for their formation. In embodiments, in-plane nanowires can be epitaxially grown on a patterned substrate, which are more favorable than vertical ones for device processing and three-dimensional (3D) integrated circuits. In embodiments, the in-plane nanowire can be formed by selective epitaxy utilizing lateral overgrowth and faceting of an epilayer initially grown in a one-dimensional (1D) nanoscale opening. In embodiments, optical, electrical, and thermal connections can be established and controlled between the nanowire, the substrate, and additional electrical or optical components for better device and system performance. 1. A method for forming a nanowire device comprising:forming an in-plane nanowire core by forming a first doped region of a nanowire core material, forming an undoped layer surrounding the first doped region, and forming a second doped region of the nanowire core material having a polarity opposite that of the first doped region, wherein the first and second doped regions form a p-n junction; andforming a she layer surrounding the in-plane nanowire core, wherein the shell layer comprises a higher bandgap material than the in-plane nanowire core material having an interface characterized by a bandgap discontinuity with the in-plane nanowire core.2. The method of claim 1 , wherein the interface comprises a plurality of cladding pairs formed by parallel faceted regions of the in-plane nanowire core to form a waveguide.3. The method of claim 1 , further comprising forming end mirrors of a laser diode either with faceting in epitaxial growth or by etching in device processing.4. The method of claim 1 , further comprising controlling a lateral size of the in-plane nanowire core that supports a single transverse mode of a radiation field of a laser diode.5. The method of claim 1 , wherein the first doped region comprises an n-doped region.6. The method ...

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Номер записи: 50

06-03-2014 дата публикации

Method for making light emitting diode

Номер: US20140065742A1

Автор: Shou-Shan Fan, Yang Wei

Принадлежит: Hon Hai Precision Industry Co Ltd, TSINGHUA UNIVERSITY

A method for making a light emitting diode includes the following steps. A first epitaxial substrate having a first epitaxial growth surface is provided. A carbon nanotube layer is placed on the first epitaxial growth surface. An intrinsic semiconductor layer is grown on the first epitaxial growth surface epitaxially. A second epitaxial substrate is formed by removing the carbon nanotube layer, wherein the second epitaxial substrate has a second epitaxial growth surface. A first semiconductor layer, an active layer and a second semiconductor layer are grown on the second epitaxial growth surface in that order. A part of the first semiconductor layer is exposed by etching a part of the active layer and the second semiconductor layer. A first electrode is applied on the first semiconductor layer and a second electrode is applied on the second semiconductor layer.

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Номер записи: 51

06-03-2014 дата публикации

LOW TEMPERATURE POLYSILICON THIN FILM AND MANUFACTURING METHOD THEREOF

Номер: US20140065804A1

Автор: Long Chunping, Tian Xueyan, Yao Jiangfeng

Принадлежит: BOE Technology Group Co., Ltd.

An embodiment of the present invention relates to a low temperature polysilicon thin film and a manufacturing method thereof. The manufacturing method comprises: forming a buffer layer on a substrate (S); forming a seed layer comprising a plurality of uniformly distributed crystal nuclei on the buffer layer by using a patterning process (S); forming an amorphous silicon layer on the seed layer (S); and performing an excimer laser annealing process on the amorphous silicon layer (S). 1. A manufacturing method of a low temperature polysilicon thin film , comprising:forming a buffer layer on a substrate;forming a seed layer which comprises a plurality of uniformly distributed crystal nuclei on the buffer layer by using a patterning process;forming an amorphous silicon layer on the seed layer; andperforming an excimer laser annealing process on the amorphous silicon layer.2. The manufacturing method according to claim 1 , wherein the seed layer is an amorphous silicon seed layer claim 1 , and the forming the seed layer which comprises a plurality of uniformly distributed crystal nuclei on the buffer layer by using the patterning process comprises: depositing an amorphous silicon material layer on the buffer layer using a plasma enhanced chemical vapor deposition method; and patterning the amorphous silicon material layer on the buffer layer into a plurality of uniformly distributed amorphous silicon islands by using a patterning process claim 1 , and the plurality of amorphous silicon islands are used as a plurality of crystal nuclei.3. The manufacturing method according to claim 1 , wherein the seed layer is a microcrystalline silicon-type seed layer claim 1 , and the forming the seed layer which comprises a plurality of uniformly distributed crystal nuclei on the buffer layer by using the patterning process comprises: forming a microcrystalline silicon material layer on the buffer layer; and patterning the microcrystalline silicon material layer on the buffer layer ...

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Номер записи: 52

27-03-2014 дата публикации

Nitride semiconductor wafer, nitride semiconductor device, and method for manufacturing nitride semiconductor wafer

Номер: US20140084296A1

Автор: Hisashi Yoshida, Naoharu Sugiyama, Shinya Nunoue, Toshiki Hikosaka, Yoshiyuki Harada

Принадлежит: Individual

A nitride semiconductor wafer includes a silicon substrate, a stacked multilayer unit, a silicon-containing unit, and an upper layer unit. The silicon substrate has a major surface. The stacked multilayer unit is provided on the major surface. The stacked multilayer unit includes N number of buffer layers. The buffer layers include an i-th buffer layer, and an (i+1)-th buffer layer provided on the i-th buffer layer. The i-th buffer layer has an i-th lattice length Wi in a first direction parallel to the major surface. The (i+1)-th buffer layer has an (i+1)-th lattice length W(i+1) in the first direction. A relation that (W(i+1)−Wi)/Wi≦0.008 is satisfied for all the buffer layers. The silicon-containing unit is provided on the stacked multilayer unit. The upper layer unit is provided on the silicon-containing unit.

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Номер записи: 53

03-04-2014 дата публикации

Semiconductor apparatus

Номер: US20140091313A1

Автор: Atsushi Yamada, Junji Kotani, Norikazu Nakamura, Tetsuro ISHIGURO

Принадлежит: Fujitsu Ltd

A semiconductor apparatus includes a substrate; a buffer layer formed on the substrate; a first semiconductor layer formed on the buffer layer; and a second semiconductor layer formed on the first semiconductor layer. Further, the buffer layer is formed of AlGaN and doped with Fe, the buffer layer includes a plurality of layers having different Al component ratios from each other, and the Al component ratio of a first layer is greater than the Al component ratio of a second layer and a Fe concentration of the first layer is less than the Fe concentration of the second layer, the first and second layers being included in the plurality of layers, and the first layer being formed on a substrate side of the second layer.

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Номер записи: 54

03-04-2014 дата публикации

Semiconductor apparatus

Номер: US20140091318A1

Автор: Atsushi Yamada, Norikazu Nakamura, Tetsuro ISHIGURO

Принадлежит: Fujitsu Ltd

A semiconductor apparatus includes: a substrate; a buffer layer formed on the substrate; a strained layer superlattice buffer layer formed on the buffer layer; an electron transit layer formed of a semiconductor material on the strained layer superlattice buffer layer; and an electron supply layer formed of a semiconductor material on the electron transit layer; the strained layer superlattice buffer layer being an alternate stack of first lattice layers including AlN and second lattice layers including GaN; the strained layer superlattice buffer layer being doped with one, or two or more impurities selected from Fe, Mg and C.

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Номер записи: 55

06-01-2022 дата публикации

METHOD OF FORMING SILICON FILM ON SUBSTRATE HAVING FINE PATTERN

Номер: US20220005690A1

Автор: Hashimoto Hiroyuki, Masuda Takashi, NAKAMURA Mayuko, TAKAGISHI Hideyuki, Tanaka Yuki

Принадлежит:

A method of forming a silicon film on a substrate having a fine pattern includes performing surface treatment with an adhesion promoter on the substrate having the fine pattern, forming a coating film by applying a silane polymer solution to the substrate on which the surface treatment has been performed, and heating the coating film. 110-. (canceled)11. A method of forming a silicon film on a substrate having a fine pattern , the method comprising:performing surface treatment with an adhesion promoter on the substrate having the fine pattern;forming a coating film by applying a silane polymer solution to the substrate on which the surface treatment has been performed; andheating the coating film.12. The method of claim 11 , wherein the fine pattern includes a groove.13. The method of claim 12 , wherein the groove has a width of 50 nm or less.14. The method of claim 13 , wherein the fine pattern includes a dummy gate pattern.15. The method of claim 14 , wherein the adhesion promoter is a silane compound represented by formula (1) below claim 14 ,{'br': None, 'sub': m1', '2', '4-m1-m2, 'sup': 1', '2, 'i': 'm', 'Si(X)(R)(R)\u2003\u2003(1)'}[In the formula, X represents a monovalent group including a functional group that contributes to bonding to the silane polymer,{'sup': '1', 'Rrepresents a hydroxy group, an alkoxy group, or a halogen atom,'}{'sup': '2', 'Rrepresents a hydrogen atom, an alkyl group, or an aryl group, and'}{'sup': 1', '1', '2', '2, 'each of m1 and m2 represents an integer of 1 to 3 satisfying a condition that a sum of m1 and m2 is 4 or less. When there are multiple Xs, the multiple Xs are the same as or different from each other, when there are multiple Rs, the multiple Rs are the same as or different from each other, and when there are multiple Rs, the multiple Rs are the same as or different from each other].'}16. The method of claim 15 , wherein X represents the monovalent group including the functional group selected from a group including a ...

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Номер записи: 56

06-01-2022 дата публикации

Semiconductor device and fabrication method

Номер: US20220006264A1

Автор: Alwyn Seeds, Huiyun Liu, Jiang Wu, Mengya LIAO, Mingchu TANG, Siming Chen

Принадлежит: UCL BUSINESS LTD

A semiconductor device comprising a nominally or exactly or equivalent orientation silicon substrate on which is grown directly a <100 nm thick nucleation layer (NL) of a III-V compound semiconductor, other than GaP, followed by a buffer layer of the same compound, formed directly on the NL, optionally followed by further III-V semiconductor layers, followed by at least one layer containing III-V compound semiconductor quantum dots, optionally followed by further III-V semiconductor layers. The NL reduces the formation and propagation of defects from the interface with the silicon, and the resilience of quantum dot structures to dislocations enables lasers and other semiconductor devices of improved performance to be realized by direct epitaxy on nominally or exactly or equivalent orientation silicon.

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Номер записи: 57

05-01-2017 дата публикации

Semiconductor Heterostructure with Stress Management

Номер: US20170005228A1

Автор: Alexander Dobrinsky, Daniel Billingsley, Maxim S. Shatalov, Michael Shur, Rakesh Jain, Remigijus Gaska, Robert M. Kennedy, Wenhong Sun

Принадлежит: Sensor Electronic Technology Inc

A heterostructure for use in fabricating an optoelectronic device is provided. The heterostructure includes a layer, such as an n-type contact or cladding layer, that includes thin sub-layers inserted therein. The thin sub-layers can be spaced throughout the layer and separated by intervening sub-layers fabricated of the material for the layer. The thin sub-layers can have a distinct composition from the intervening sub-layers, which alters stresses present during growth of the heterostructure.

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Номер записи: 58

07-01-2021 дата публикации

Method for manufacturing a silicon on nitride substrate

Номер: US20210005444A1

Автор: Hu Liang, LAN Peng

Принадлежит: Interuniversitair Microelektronica Centrum vzw IMEC

According to an aspect of the present inventive concept there is provided a method for manufacturing a silicon on nitride, SON, substrate. The method comprises the steps of providing a semiconductor layer of a first crystal orientation, forming, on the semiconductor layer, an interface layer comprising a monocrystalline III-nitride layer forming a nucleation layer for a subsequent epitaxy process, and bonding a silicon substrate of a second crystal orientation with the interface layer.

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Номер записи: 59

07-01-2021 дата публикации

VERTICAL NANOWIRE SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREFOR

Номер: US20210005453A1

Автор: HONG Ying

Принадлежит:

Provided is a method of manufacturing a nanowire semiconductor device, the method including: forming a seed layer on a substrate; forming, on the seed layer, a multilayer in which a first conductive layer, a semiconductor layer, a second conductive layer are sequentially stacked; forming a vertical nanowire above the substrate by patterning the multilayer; crystallizing the vertical nanowire by heat treatment; forming an insulating layer covering the vertical nanowire; forming a gate surrounding a channel area by the semiconductor silicon layer of the vertical nanowire; and forming a metal pad electrically connected to the gate, the first conductive layer, and the second conductive layer. 1. A method of manufacturing a nanowire semiconductor device , the method comprising:forming a seed layer on a substrate;forming, on the seed layer, a multilayer in which a first conductive layer, a semiconductor layer, a second conductive layer are sequentially stacked;forming a vertical nanowire above the substrate by patterning the multilayer;crystallizing the vertical nanowire by heat treatment;forming an insulating layer covering the vertical nanowire;forming a gate surrounding a channel area by the semiconductor layer of the vertical nanowire; andforming a metal pad electrically connected to the gate, the first conductive layer, and the second conductive layer.2. The method of claim 1 , further comprising:forming, above the substrate, an ILD layer covering the vertical nanowire and having a plurality of contact holes corresponding to the first conductive layer, the second conductive layer, and the gate; andforming, on the ILD layer, a plurality of metal pads respectively corresponding to the gate, the first conductive layer, and the second conductive layer.3. The method of claim 1 , wherein the seed layer is formed of at least one selected from the group consisting of NiOx claim 1 , NiCxOy claim 1 , NiNxOy claim 1 , NiCxNyOz claim 1 , NiCxOy:H claim 1 , NiNxOy:H claim 1 , ...

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Номер записи: 60

04-01-2018 дата публикации

PHOTOELECTRIC CONVERSION ELEMENT AND PHOTOELECTRIC CONVERSION DEVICE INCLUDING THE SAME

Номер: US20180006174A1

Автор: Arakawa Yasuhiko, IZUMI Makoto, KAGEYAMA Takeo, Yoshikawa Hirofumi

Принадлежит:

A photoelectric conversion element includes a buffer layer, a BSF layer, a base layer, a photoelectric conversion layer, an emitter layer, a window layer, a contact layer, and a p-type electrode sequentially on one surface of a substrate, and includes an n-type electrode on the other surface of the substrate. The photoelectric conversion layer has at least one quantum dot layer. The at least one quantum dot layer includes a quantum dot and a barrier layer. A photoelectric conversion member including the buffer layer, the BSF layer, the base layer, the photoelectric conversion layer, the emitter layer, the window layer, and the contact layer has an edge of incidence that receives light in an oblique direction relative to the growth direction of the quantum dot. A concentrator concentrates sunlight and causes the concentrated sunlight to enter the photoelectric conversion member from the edge of incidence. 1. A photoelectric conversion element comprising:a substrate;a photoelectric conversion layer disposed on the substrate and having at least one quantum layer;a concentrator;a first electrode disposed at one side of the photoelectric conversion layer in a thickness direction; anda second electrode disposed at the other side of the photoelectric conversion layer in the thickness direction, wherein the photoelectric conversion layer has an edge of incidence at one end of the photoelectric conversion layer in a direction perpendicular to the thickness direction of the photoelectric conversion layer, the edge of incidence guiding light from the concentrator to the photoelectric conversion layer in an oblique direction relative to the thickness direction of the photoelectric conversion layer.2. The photoelectric conversion element according to claim 1 , further comprising a first metal layer disposed on an edge opposite to the edge of incidence in the direction perpendicular to the thickness direction of the photoelectric conversion layer.3. The photoelectric conversion ...

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Номер записи: 61

07-01-2021 дата публикации

LOW TEMPERATURE POLYCRYSTALLINE SEMICONDUCTOR DEVICE AMD MANUFACTURING METHOD THEREOF

Номер: US20210005737A1

Автор: HONG Ying

Принадлежит:

Provided is a method of manufacturing a semiconductor device, the method including: forming a buffer layer of an insulating layer on a substrate; a seed layer formation operation of forming, on the buffer layer, a seed layer of at least one selected from the group consisting of NiCxOy, NiNxOy, NiCxNyOz, NiCxOy:H, NiNxOy:H, NiCxNyOz:H, NixSiy, and NixGey; a silicon layer formation operation of forming an amorphous silicon layer on the seed layer; and a crystallization operation of crystallizing the amorphous silicon layer by a catalytic action of Ni by thermally treating the amorphous silicon layer. 1. A method of manufacturing a semiconductor device , the method comprising:forming a buffer layer of an insulating material on a substrate;a seed layer formation operation of forming, on the buffer layer, a seed layer of at least one selected from the group consisting of NiCxOy, NiNxOy, NiCxNyOz, NiCxOy:H, NiNxOy:H, NiCxNyOz:H, NixSiy, and NixGey;a silicon layer formation operation of forming an amorphous silicon layer on the seed layer; anda crystallization operation of crystallizing the amorphous silicon layer by a catalytic action of Ni by thermally treating the amorphous silicon layer.2. The method of claim 1 , further comprising:forming a catalytic reaction control layer between the seed layer formation operation and the silicon layer formation operation.3. The method of claim 1 , wherein the silicon layer formation operation comprises:forming, on the buffer layer, an amorphous intrinsic silicon layer for forming a channel;forming, on the amorphous intrinsic silicon layer, a non-intrinsic silicon layer for forming a source and/or drain; andforming a metal layer on the non-intrinsic silicon layer.4. The method of claim 3 , wherein the non-intrinsic silicon layer is formed so that a first non-intrinsic silicon layer claim 3 , in contact with an amorphous silicon layer for forming a semiconductor channel claim 3 , has a lower doping concentration than a second non- ...

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Номер записи: 62

03-01-2019 дата публикации

High Mobility Silicon on Flexible Substrates

Номер: US20190006170A1

Автор: DUTTA Pavel, Gao Ying, Selvamanickam Venkat

Принадлежит: UNIVERSITY OF HOUSTON SYSTEM

A semiconductor device and method for fabricating same is disclosed. Embodiments are directed to a semiconductor device and fabrication of same which include a flexible substrate and a buffer stack overlying the substrate. The buffer stack comprises at least one epitaxial buffer layer. An epitaxial doped layer comprised predominantly of silicon overlies the at least one epitaxial buffer layer. Mobility of the device is greater than 100 cm/Vs and carrier concentration of the epitaxial doped layer is less than 10cm. 1. A semiconductor device comprising:a flexible substrate;a buffer stack overlying the substrate, wherein the buffer stack comprises at least one epitaxial buffer layer; andan epitaxial doped layer comprised predominantly of silicon and overlying the at least one epitaxial buffer layer;{'sup': 2', '16', '−3, 'wherein mobility of the device is greater than 100 cm/Vs and carrier concentration of the epitaxial doped layer is less than 10cm.'}2. The semiconductor device of claim 1 , wherein mobility of the epitaxial doped layer is greater than 100 cm/Vs.3. The semiconductor device of claim 1 , wherein the at least one epitaxial buffer layer is comprised predominantly of germanium.4. The semiconductor device of claim 1 , wherein the flexible substrate comprises a non-single crystal material.5. The semiconductor device of claim 1 , wherein the flexible substrate comprises a flexible material selected from the group consisting of metals claim 1 , glasses claim 1 , ceramics claim 1 , and combinations thereof.6. The semiconductor device of claim 1 , wherein the buffer stack comprises a biaxially-textured Ion Beam-Assisted Deposition (IBAD) layer.7. The semiconductor device of claim 1 , wherein the epitaxial doped layer is at least 0.05 μm thick.8. The semiconductor device of claim 1 , wherein the epitaxial doped layer is grown via plasma enhanced chemical vapor deposition.9. The semiconductor device of claim 1 , wherein the buffer stack comprises an amorphous ...

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Номер записи: 63

03-01-2019 дата публикации

Epitaxies of a Chemical Compound Semiconductor

Номер: US20190006173A1

Автор: Chang Yi, Wang Tsun-Ming, Yu Hung-wei

Принадлежит:

Methods and structures includes providing a substrate, forming a prelayer over a substrate, forming a barrier layer over the prelayer, and forming a channel layer over the barrier layer. Forming the prelayer may include growing the prelayer at a graded temperature. Forming the barrier layer is such that the barrier layer may include GaAs or InGaAs. Forming the channel layer is such that the channel layer may include InAs or an Sb-based heterostructure. Thereby structures are formed. 1. A method comprising:providing a substrate;forming a prelayer over a substrate;forming over the prelayer a barrier layer that includes one of GaAs and InGaAs; andforming a channel layer over the barrier layer.2. The method of claim 1 , wherein forming the barrier layer includes doping the barrier layer.3. The method of claim 1 , wherein forming the barrier layer includes depositing the one of GaAs and InGaAs on the substrate using a metal organic chemical vapor deposition (MOCVD).4. The method of claim 1 , further comprising fabricating a transistor that includes the channel layer.5. The method of claim 1 , wherein forming the prelayer includes growing the prelayer at a graded temperature.6. A method comprising:providing a substrate;forming over the substrate a prelayer at a graded temperature;forming a barrier layer over the prelayer; andforming a channel layer over the barrier layer.7. The method of claim 6 , wherein forming the prelayer includes growing the prelayer on the substrate at a ramping temperature.8. The method of claim 6 , wherein forming the prelayer includes depositing the prelayer on the substrate using a metal organic chemical vapor deposition (MOCVD).9. The method of claim 6 , wherein forming the prelayer includes depositing As on the substrate.10. The method of claim 6 , further comprising fabricating a transistor that includes the channel layer.11. The method of claim 6 , wherein forming the barrier layer includes doping the barrier layer.12. A structure comprising ...

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Номер записи: 64

03-01-2019 дата публикации

SILICON GERMANIUM SELECTIVE OXIDATION PROCESS

Номер: US20190006175A1

Автор: TJANDRA Agus Sofian

Принадлежит:

Implementations described herein relate to selective oxidation processes for semiconductor device manufacturing. In one implementation, the process includes delivering a substrate having a semiconductor device comprising at least a silicon material and a silicon germanium material formed thereon to a process chamber. Process variables are determined based upon the germanium concentration of the silicon germanium material and a desired oxide thickness and a selective oxidation process is performed utilizing the determined process variables. 1. A selective oxidation method , comprising:heating a process region of a process chamber to a temperature less than about 700° C.;generating reactive species comprising hydrogen and oxygen in the process region; andexposing a substrate comprising at least a silicon material and a silicon germanium material to the reactive species to selectively oxidize the silicon germanium material preferentially to the silicon material.2. The method of claim 1 , wherein the silicon material and the silicon germanium material are simultaneously exposed to the reactive species.3216. The method of claim 2 , wherein the silicon germanium material is selectively oxidized at a rate of between times and times greater than an oxidation rate of the silicon material.4. The method of claim 1 , wherein the reactive species are hydroxyl radicals.5. The method of claim 1 , wherein the reactive species are hydroxide ions.6. The method of claim 1 , wherein the reactive species are hydrogen and oxygen radicals.7. The method of claim 1 , wherein the reactive species are hydrogen and oxygen ions.8. The method of claim 1 , wherein a ratio of oxygen to hydrogen is between 19:1 and 1:9.9. The method of claim 1 , further comprising:generating hydroxyl radicals remotely from the process chamber and delivering the hydroxyl radicals to the process region.10. The method of claim 1 , further comprising:generating hydrogen and oxygen radicals remotely from the process ...

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Номер записи: 65

03-01-2019 дата публикации

ENCAPSULATED SUBSTRATE, MANUFACTURING METHOD, HIGH BAND-GAP DEVICE HAVING ENCAPSULATED SUBSTRATE

Номер: US20190006177A1

Автор: Liu Po-Yen, Sung Kao-Mei, Wang Hsiao-Lei

Принадлежит:

An encapsulated substrate includes a zinc oxide substrate and a composite barrier layer. The composite barrier layer includes a first film layer having a first material different from zinc oxide, a second film layer covered on a surface of the first film layer and having a second material different from the zinc oxide and the first material, and an active layer formed on the composite barrier layer and corresponding to an acting surface of a zinc oxide substrate and having an acting material different from the zinc oxide. 1. An encapsulated substrate , comprising:a zinc oxide substrate comprising at least one acting surface and being a zinc oxide material having a standard lattice structure of a wurtzite lattice structure; anda composite barrier layer having a thickness greater than 1 nanometer and being surroundingly covered on the zinc oxide substrate, comprising a first film layer which has a thickness greater than 0.1 nanometer and is directly covered and formed on the zinc oxide substrate comprises a first material different from zinc oxide and is provided with a lattice constant ranged between 120% and 115% or between 105% and 95% of the standard lattice structure as being in the form of the wurtzite lattice structure; a second film layer which has a thickness greater than 0.1 nanometer and is directly covered and formed on a surface of the first film layer comprises a second material different from the zinc oxide and the first material and is provided with a lattice constant ranged between 120% and 115% or between 105% and 95% of the standard lattice structure as being in the form of the wurtzite lattice structure; a plurality of accumulating film layers sequentially formed on the second film layer and each of which being different from the adjacent accumulating film layer and/or the second film layer and provided with a lattice constant ranged between 120% and 115% or between 105% and 95% of the standard lattice structure as being in the form of the wurtzite ...

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Номер записи: 66

03-01-2019 дата публикации

SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME

Номер: US20190006178A1

Автор: Huang Yen-Lun, Lin Man-Hsuan, Liu Jia-Zhe

Принадлежит: GlobalWafers Co., Ltd.

A semiconductor device including a substrate, a semiconductor layer, and a buffer structure is provided. The semiconductor layer is located on the substrate. The buffer structure is located between the substrate and the semiconductor layer. The buffer structure includes a plurality of first layers and a plurality of second layers. The first layers and the second layers are alternately stacked with a same pitch or different pitches. 1. A semiconductor device , comprising:a substrate;a semiconductor layer, located on the substrate; anda buffer structure located between the substrate and the semiconductor layer, the buffer structure comprising a plurality of first layers and a plurality of second layers, the first layers and the second layers being alternately stacked, wherein a number of the first layers is greater than or equal to 56, and a bow of the semiconductor device is less than 10 μm.2. The semiconductor device as claimed in claim 1 , wherein a sum of thicknesses of the first layers accounting for 17% to 21% of a total thickness of the buffer structure when the first layers and the second layers are alternately stacked with a same pitch.3. The semiconductor device as claimed in claim 1 , wherein the number of the first layers ranges between 56 and 70.4. The semiconductor device as claimed in claim 1 , wherein the buffer structure has a bottom region claim 1 , a middle region claim 1 , and a top region claim 1 , and the number of the first layers at the bottom region is equal to the number of the first layers at the top region claim 1 , and the number of the first layers at the bottom region is greater than the number of the first layers at the middle region when the first layers and the second layers are alternately stacked with different pitches claim 1 ,wherein a sum of thicknesses of the first layers accounts for less than 20% of a total thickness of the buffer structure.5. The semiconductor device as claimed in claim 1 , wherein the buffer structure has a ...

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Номер записи: 67

02-01-2020 дата публикации

GROWTH OF CUBIC CRYSTALLINE PHASE STRUCTURE ON SILICON SUBSTRATES AND DEVICES COMPRISING THE CUBIC CRYSTALLINE PHASE STRUCTURE

Номер: US20200006597A1

Автор: Brueck Steven R.J., Durniak Mark, Lee Seung-Chang, Wetzel Christian

Принадлежит:

A method of forming a semiconductor structure includes providing a substrate comprising a first material portion and a single crystal silicon layer on the first material portion. The substrate further comprises a major front surface, a major backside surface opposing the major front surface, and a plurality of grooves positioned in the major front surface. A buffer layer is deposited in one or more of the plurality of grooves. A semiconductor material is epitaxially grown over the buffer layer and in the one or more plurality of grooves, the epitaxially grown semiconductor material comprising a hexagonal crystalline phase layer and a cubic crystalline phase structure disposed over the hexagonal crystalline phase. 1. A light emitting diode comprising:a substrate comprising a Group III/V compound semiconductor material having a cubic crystalline phase, an active region being positioned in the cubic crystalline phase;a first metal contact and a second metal contact, the first and second metal contacts being positioned to provide electrical connectivity to the light emitting diode, at least one of the first and second metal contacts being transparent to visible light;wherein the light emitting diode is not attached to a substrate comprising a Group IV semiconductor material.2. The light emitting diode of claim 1 , wherein the cubic crystalline phase structure has a length dimension claim 1 , a width dimension and a height dimension claim 1 , the width dimension decreasing with the height so that the structure is tapered claim 1 , the hexagonal crystalline material being formed adjacent to the tapered structure.3. The light emitting diode of claim 2 , wherein the cubic crystalline phase is positioned between a first hexagonal crystalline phase and a second hexagonal crystalline phase.4. The light emitting diode of claim 2 , wherein the Group III/V compound semiconductor material is a Group III-nitride.5. The light emitting diode of claim 2 , wherein the active region ...

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Номер записи: 68

12-01-2017 дата публикации

LOW DEFECT RELAXED SiGe/STRAINED Si STRUCTURES ON IMPLANT ANNEAL BUFFER/STRAIN RELAXED BUFFER LAYERS WITH EPITAXIAL RARE EARTH OXIDE INTERLAYERS AND METHODS TO FABRICATE SAME

Номер: US20170011920A1

Автор: Alexander Reznicek

Принадлежит: International Business Machines Corp

A method provides a substrate having a top surface; forming a first semiconductor layer on the top surface, the first semiconductor layer having a first unit cell geometry; epitaxially depositing a layer of a metal-containing oxide on the first semiconductor layer, the layer ofmetal-containing oxide having a second unit cell geometry that differs from the first unit cell geometry; ion implanting the first semiconductor layer through the layer of metal-containing oxide; annealing the ion implanted first semiconductor layer; and forming a second semiconductor layer on the layer of metal-containing oxide, the second semiconductor layer having the first unit cell geometry. The layer of metal-containing oxide functions to inhibit propagation of misfit dislocations from the first semiconductor layer into the second semiconductor layer. A structure formed by the method is also disclosed.

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Номер записи: 69

14-01-2016 дата публикации

SEMICONDUCTOR DEVICE HAVING FIN-TYPE CHANNEL AND METHOD FOR FORMING THE SAME

Номер: US20160013054A1

Автор: Huang Mao-Lin, Lin Chun-Hsiung, Wang Chien-Hsun

Принадлежит:

A method for forming a semiconductor device having a fin-type channel is provided. The method may include the following operations: forming a first buffer layer over a substrate; forming a first dielectric layer over the first buffer layer; patterning the first dielectric layer over the first buffer layer; forming a barrier layer over the first buffer layer; forming a second dielectric layer over the barrier layer; patterning the second dielectric layer over the barrier layer; forming a channel layer over the barrier layer; and patterning the second dielectric layer, such that at least a portion of the channel layer protrudes to form the fin-type channel. 1. A method for forming a semiconductor device having a fin-type channel , comprising:forming a first buffer layer over a substrate;forming a first dielectric layer over the first buffer layer;patterning the first dielectric layer over the first buffer layer;forming a barrier layer over the first buffer layer;forming a second dielectric layer over the barrier layer;patterning the second dielectric layer over the barrier layer;forming a channel layer over the barrier layer; andpatterning the second dielectric layer, such that at least a portion of the channel layer protrudes to form the fin-type channel.2. The method of claim 1 , further comprising patterning the substrate to define a first recess.3. The method of claim 2 , further comprising forming the first buffer layer in the first recess.4. The method of claim 2 , wherein patterning the first dielectric layer over the first buffer layer further comprises patterning the first dielectric layer to define a second recess.5. The method of claim 4 , wherein patterning the substrate to define the first recess further comprises defining the first recess having a first width claim 4 , and wherein patterning the first dielectric layer to define the second recess further comprises defining the second recess having a second width smaller than the first width.6. The method ...

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Номер записи: 70

15-01-2015 дата публикации

III-N MATERIAL GROWN ON REN EPITAXIAL BUFFER ON Si SUBSTRATE

Номер: US20150014676A1

Автор: Andrew Clark, Erdem Arkun, Michael Lebby, Robin Smith, Rytis Dargis

Принадлежит: Andrew Clark, Erdem Arkun, Michael Lebby, Robin Smith, Rytis Dargis

A method of growing III-N material on a silicon substrate includes the steps of epitaxially growing a single crystal rare earth oxide on a silicon substrate, epitaxially growing a single crystal rare earth nitride on the single crystal rare earth oxide, and epitaxially growing a layer of single crystal III-N material on the single crystal rare earth nitride.

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Номер записи: 71

11-01-2018 дата публикации

SEMICONDUCTOR STRUCTURE HAVING A GROUP III-V SEMICONDUCTOR LAYER COMPRISING A HEXAGONAL MESH CRYSTALLINE STRUCTURE

Номер: US20180012757A1

Автор: Charles Matthew

Принадлежит: Commissariat A L'Energie Atomique Et Aux Energies Alternatives

A semiconductor structure () comprising: 1. A semiconductor structure comprising:a sub strategy,{'sub': X', 'Y', '(1−X−Y), 'a first semiconductor layer corresponding to AlGaInN, where 0≦X<1, 0 Подробнее

Номер записи: 72

11-01-2018 дата публикации

GaN-on-Si SEMICONDUCTOR DEVICE STRUCTURES FOR HIGH CURRENT/ HIGH VOLTAGE LATERAL GaN TRANSISTORS AND METHODS OF FABRICATION THEREOF

Номер: US20180012770A1

Автор: KLOWAK Greg P., MACELWEE Thomas, TWEDDLE Howard

Принадлежит:

A GaN-on-Si device structure and a method of fabrication are disclosed for improved die yield and device reliability of high current/high voltage lateral GaN transistors. A plurality of conventional GaN device structures comprising GaN epi-layers are fabricated on a silicon substrate (GaN-on-Si die). After processing of on-chip interconnect layers, a trench structure is defined around each die, through the GaN epi-layers and into the silicon substrate. A trench cladding is provided on proximal sidewalls, comprising at least one of a passivation layer and a conductive metal layer. The trench cladding extends over exposed surfaces of the GaN epi-layers, over the interface region with the substrate, and over the exposed surfaces of the interconnect layers. This structure reduces risk of propagation of dicing damage and defects or cracks in the GaN epi-layers into active device regions. A metal trench cladding acts as a barrier for electro-migration of mobile ions. 1. A wafer scale nitride semiconductor device structure comprising:a silicon substrate having formed thereon an GaN epi-layer stack for a plurality of GaN die (GaN-on-Si die), said plurality of GaN die being arranged as an array with dicing streets therebetween; a part of the GaN epi-layer stack, the GaN epi-layer stack comprising a GaN/AlGaN hetero-layer structure defining a two-dimensional electron gas (2DEG) active layer for a lateral GaN transistor;', 'a conductive metallization layer formed thereon defining source and drain electrodes of the lateral GaN transistor, and a gate electrode formed on a channel region between respective source and drain electrodes of the lateral GaN transistor; said source, drain and gate electrodes being provided on a front-side of the epi-layer stack over an active area of the die, an inactive area of the GaN epi-layer stack surrounding said active area of each die, and an overlying interconnect structure comprising metallization and dielectric layers formed thereon; and, ' ...

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Номер записи: 73

14-01-2016 дата публикации

METHOD AND APPARATUS FOR 3D CONCURRENT MULTIPLE PARALLEL 2D QUANTUM WELLS

Номер: US20160013306A1

Автор: Cai Ming, Li Xia, YANG Bin

Принадлежит:

An inner fin of a high bandgap material is on a substrate, having two vertical faces, and is surrounded by a carrier redistribution fin of a low bandgap material. The inner fin and the carrier redistribution fin have two vertical interfaces. The carrier redistribution fin has a thickness and a bandgap relative to the bandgap of the inner fin that establishes, along the two vertical interfaces, an equilibrium of a corresponding two two-dimensional electron gasses. 1. A multiple quantum well (QW) FinFET comprisinga fin base supported on a substrate, the fin base comprising a first material, the first material having a high bandgap;an inner fin, comprising a second material, the second material having a high bandgap, the inner fin having a first vertical face and a second vertical face, the second vertical face being spaced a fin thickness from and parallel to the first vertical face; anda carrier redistribution fin, comprising a third material, the third material having a low bandgap, the carrier redistribution fin surrounding the inner fin, and the carrier redistribution fin having a first planar inner surface that is parallel to and interfaces the first vertical face at a first vertical planar interface, and the carrier redistribution fin having second planar inner surface that is parallel to and interfaces and the second vertical face at a second vertical planar interface,the second material having a doping,the first material being reverse doped relative to the doping of the second material, andthe third material having a low doping or being undoped.2. The multiple QW FinFET of claim 1 , a bandgap of the first material and a bandgap of the second material being configured to establish at least a first quantum well (QW) and claim 1 , concurrent with the first QW claim 1 , a second QW claim 1 , the first QW being in a first region of the carrier redistribution fin claim 1 , the second QW being in a second region of the carrier redistribution fin claim 1 , the first ...

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Номер записи: 74

10-01-2019 дата публикации

TRANSDERMAL MICRONEEDLE CONTINUOUS MONITORING SYSTEM

Номер: US20190013425A1

Автор: HUANG Juang-Tang

Принадлежит:

Transdermal microneedles continuous monitoring system is provided. The continuous system monitoring includes a substrate, a microneedle unit, a signal processing unit and a power supply unit. The microneedle unit at least comprises a first microneedle set used as a working electrode and a second microneedle set used as a reference electrode, the first and second microneedle sets arranging on the substrate. Each microneedle set comprises at least a microneedle. The first microneedle set comprises at least a sheet having a through hole on which a barbule forms at the edge. One of the sheets provides the through hole from which the barbules at the edge of the other sheets go through, and the barbules are disposed separately. 1. A transdermal microneedles continuous monitoring system , comprising:a substrate;a microneedle unit comprising at least a first microneedle set used as a working electrode and a second microneedle set used as a reference electrode, each of the microneedle sets comprising at least a microneedle, the first microneedle set comprising at least two sheets, each of the sheets having a through hole defined thereon and a barbule arranged at the peripheral of the through hole, the through hole on one sheet allowing the corresponding barbules of an other sheet to pass and the barbules being disposed separately;a signal processing unit arranged on the substrate and electrically connecting to the first microneedle set and the second microneedle set; anda power supply unit providing working power to the transdermal microneedles continuous monitoring system,wherein the at least two sheets comprise a first sheet, a second sheet and a third sheet stacked with each other, the first sheet having at least one first through hole defined thereon and a first barbule at the peripheral of the first through hole, the second sheet having at least one second through hole defined thereon and a second barbule at the peripheral of the second through hole, the third sheet ...

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Номер записи: 75

19-01-2017 дата публикации

HORIZONTAL GATE ALL AROUND DEVICE ISOLATION

Номер: US20170018624A1

Автор: CHUDZIK Michael, Colombeau Benjamin, GUARINI Theresa Kramer, Jun Sung Won, Sun Shiyu, Yoshida Naomi

Принадлежит:

Embodiments described herein generally relate to methods and apparatus for horizontal gate all around (hGAA) isolation. A superlattice structure comprising different materials arranged in an alternatingly stacked formation may be formed on a substrate. The different materials may be silicon containing materials and one or more III/V materials. In one embodiment, at least one of the layers of the superlattice structure may be oxidized to form a buried oxide layer adjacent the substrate. 1. A method of forming a semiconductor device , comprising: a first material layer;', 'a second material layer; and', 'a third material layer;, 'forming a superlattice structure on a substrate, wherein the superlattice structure comprisesetching the superlattice structure;depositing a liner on the superlattice structure;depositing an oxide material layer on the substrate; andoxidizing at least one of the first material layer, the second material layer, or the third material layer to form a buried oxide layer, wherein the liner selectively prevents oxidation of two of the material layers preferentially to the material layer which forms the buried oxide.2. The method of claim 1 , wherein the first material layer and the second material layer are disposed within the superlattice structure in an alternating stacked arrangement.3. The method of claim 1 , wherein the second material layer and the third material layer comprise silicon germanium.4. The method of claim 3 , wherein the second material layer comprises about 70% silicon and about 30% germanium claim 3 , and the third material layer comprises about 30% silicon and about 70% germanium.5. The method of wherein the second material layer is disposed on the substrate and the third material layer is disposed on the second material layer.6. The method of claim 1 , wherein the substrate and the first material layer comprise a silicon containing material.7. The method of claim 1 , wherein depositing the liner comprises:performing a ...

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Номер записи: 76

21-01-2021 дата публикации

SEMICONDUCTOR EPITAXIAL STRUCTURE AND METHOD OF FORMING THE SAME

Номер: US20210017669A1

Автор: Huang Yen-Lun, Shih Ying-Ru, Su Ke-Hong

Принадлежит: GlobalWafers Co., Ltd.

Provided is a semiconductor epitaxial structure including a nucleation layer disposed on a substrate; a buffer layer disposed on the nucleation layer; a semiconductor layer disposed on the buffer layer; a barrier layer disposed on the semiconductor layer; and a cap layer disposed on the barrier layer. In a case where a bowing of the semiconductor epitaxial structure is less than or equal to +/−30 μm, a maximum value or a minimum value of a ratio of a thickness of the buffer layer to a thickness of the semiconductor layer is represented as following formula: Y=aX1−bX2+cX3, X1≥0 nm, X2≥750 nm, X3≥515 nm, wherein X1 is a thickness of the nucleation layer, X2 is the thickness of the buffer layer, X3 is the thickness of the semiconductor layer, a, b and c are constants respectively, and Y is a ratio of X3 to X2. 1. A semiconductor epitaxial structure , comprising:a substrate;a nucleation layer disposed on a substrate;a buffer layer disposed on the nucleation layer;a semiconductor layer disposed on the buffer layer;a barrier layer disposed on the semiconductor layer; and {'br': None, 'i': Y=aX', 'bX', 'cX', 'X', 'X', 'X, '1−2+3, 1≥0 nm, 2≥750 nm, 3≥515 nm,'}, 'a cap layer disposed on the barrier layer, wherein in a case where a bowing of the semiconductor epitaxial structure is less than or equal to +/−30 μm, a maximum value or a minimum value of a ratio of a thickness of the semiconductor layer to a thickness of the buffer layer is represented as a formula ofwherein X1 is a thickness of the nucleation layer, X2 is the thickness of the buffer layer, X3 is the thickness of the semiconductor layer, a, b and c are constants respectively, and Y is the ratio of the thickness of the semiconductor layer to the thickness of the buffer layer (X3/X2) and falls between the maximum value or the minimum value.2. The semiconductor epitaxial structure according to claim 1 , wherein the maximum value of the ratio of the thickness of the semiconductor layer to the thickness of the buffer ...

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Номер записи: 77

18-01-2018 дата публикации

PRODUCTION OF A SEMICONDUCTOR SUPPORT BASED ON GROUP III NITRIDES

Номер: US20180019120A1

Автор: FRAYSSINET Eric, MASSIES Jean, SEMOND Fabrice

Принадлежит: CENTRE NATIONAL DE LA RECHERCHE SCIENTIFIQUE (CNRS)

The invention relates to a method for producing a support for the production of a semiconductor structure based on group III nitrides, characterised in that the method comprises the steps of: 1. Method for producing a support for production of a semiconductor structure based on group III nitrides , the method comprising the steps of:formation of a buffer layer on a substrate, said buffer layer comprising an upper layer based on group III nitrides,deposition of a crystalline layer on the buffer layer, said crystalline layer being deposited from silicon atoms so as to cover the entire surface of the upper layer based on group III nitrides, said crystalline layer having a triple periodicity of silicon atoms in a crystallographic direction [1-100] such that a diffraction image of said crystalline layer obtained by grazing-incidence diffraction of electrons in the direction [1-100] comprises:a central line (0, 0) and integer order lines (0, −1) and (0, 1),two fractional order diffraction lines (0, −1/3) and (0, −2/3) between the central line (0, 0) and the integer order line (0, −1), andtwo fractional order diffraction lines (0, 1/3) and (0, 2/3) between the central line (0, 0) and the integer order line (0, 1).2. Method according to claim 1 , wherein the crystalline layer has a single periodicity in a crystallographic direction [1-210] such that a diffraction image of said crystalline layer obtained by grazing-incidence diffraction of electrons in the direction [1-210] comprises a central line (0 claim 1 , 0) and integer order lines (0 claim 1 , −1) and (0 claim 1 , 1) without fractional order lines between them.3. Method according to claim 1 , wherein the step of deposition of the crystalline layer is interrupted at an instant corresponding to a maximum of luminous intensity of intermediate fractional order lines of a diffraction image in the crystallographic direction [1-100].4. Method according to claim 1 , wherein the substrate is based on silicon and the step of ...

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Номер записи: 78

22-01-2015 дата публикации

Transistor having high breakdown voltage and method of making the same

Номер: US20150021661A1

Автор: Chi-Ming Chen, Chia-Shiung Tsai, Chung-Yi Yu, Po-Chun Liu, Xiaomeng Chen

Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

A transistor includes a substrate and a graded layer on the substrate, wherein the graded layer is doped with p-type dopants. The transistor further includes a superlattice layer (SLS) on the graded layer, wherein the SLS has a p-type dopant concentration equal to or greater than 1×10 19 ions/cm 3 . The transistor further includes a buffer layer on the SLS, wherein the buffer layer comprises p-type dopants. The transistor further includes a channel layer on the buffer layer and an active layer on the second portion of the channel layer, wherein the active layer has a band gap discontinuity with the second portion of the channel layer.

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Номер записи: 79

16-01-2020 дата публикации

PROCESS FOR FABRICATING AT LEAST ONE SEMICONDUCTOR STRUCTURE COMPRISING A STEP OF SEPARATION RELATIVE TO THE GROWTH SUBSTRATE

Номер: US20200020527A1

Автор: OBRECHT Remy, Pernel Carole

Принадлежит: Commissariat A L'Energie Atomique Et Aux Energies Alternatives

The invention relates to a process for fabricating at least one semiconductor structure () separated from a support substrate (), comprising the following steps: 1. A process for fabricating at least one semiconductor structure separated from a support substrate , comprising the following steps:i) producing, starting from a support substrate, a nucleation layer formed of a two-dimensional material comprising at least three monolayers, including at least one interlayer monolayer, each monolayer being formed of a two-dimensional crystal lattice; so as to be bordered by a lateral zone in which the nucleation layer has a free surface,', 'an upper face of the support substrate, on which the nucleation layer rests, comprising a first surface not covered by the nucleation layer, so that the free surface has an upper face and a lateral edge;, 'ii) producing, by epitaxy starting from the nucleation layer, at least one semiconductor structure,'}iii) obtaining a conductive surface of a first electrode, located in said lateral zone and different from said free surface;iv) placing the structure thus obtained in an aqueous electrolytic bath, in which is placed a second electrode, the aqueous electrolyte then coming into contact, in the lateral zone, with the free surface of the nucleation layer and with the conductive surface of the first electrode;v) applying a potential difference between said electrodes, suitable for causing the formation of hydroxyl radicals at the interface between the conductive surface and the aqueous electrolyte, which then react with the upper face and the lateral edge of the free surface of the nucleation layer, then degrading at least one interlayer monolayer of the nucleation layer until the separation of the semiconductor structure relative to the support substrate is brought about.2. The process according to claim 1 , in which step iii) of obtaining the conductive surface comprises the production of a metal portion forming the first electrode claim ...

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Номер записи: 80

21-01-2021 дата публикации

A Two-Dimensional AlN Material and its Preparation Method and Application

Номер: US20210020428A1

Автор: Guoqiang Li, Wenliang Wang, Yulin ZHENG

Принадлежит: South China University of Technology SCUT

The present invention discloses a two-dimensional AlN material and its preparation method and application, wherein the preparation method comprises the following steps: (1) selecting a substrate and its crystal orientation; (2) cleaning the surface of the substrate; (3) transferring a graphene layer to the substrate layer; (4) annealing the substrate; (5) using the MOCVD process to introduce H 2 to open the graphene layer and passivate the surface of the substrate; and (6) using the MOCVD process to grow a two-dimensional AlN layer. The preparation method of the present invention has the advantages that the process is simple, time saving and efficient. Besides, the two-dimensional AlN material prepared by the present invention can be widely used in HEMT devices, deep ultraviolet detectors or deep ultraviolet LEDs, and other fields.

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Номер записи: 81

21-01-2021 дата публикации

SEMICONDUCTOR MATERIAL HAVING TUNABLE PERMITTIVITY AND TUNABLE THERMAL CONDUCTIVITY

Номер: US20210020436A1

Автор: Clark Andrew, Gott Alan, Hammond Richard, Nelson Drew, Pelzel Rodney

Принадлежит:

A layered structure for semiconductor application is described herein. The layered structure includes a starting material and a fully depleted porous layer formed over the starting material with high resistivity. In some embodiments, the layered structure further includes epitaxial layer grown over the fully depleted porous layer. Additionally, a process of making the layered structure including forming the fully depleted porous layer and epitaxial layer grown over the porous layer is described herein. 1. A layered structure comprising:a starting material layer; anda fully depleted porous layer over the starting material layer, wherein a first band gap of the fully depleted porous layer is greater than a second band gap of the starting material and the fully depleted porous layer is elementally identical to the starting material.2. The layered structure of claim 1 , wherein the fully depleted porous layer is between 10-20 μm thick with resistivity greater than 10000 ohm-cm.3. The layered structure of claim 1 , wherein the starting material comprises silicon.4. The layered structure of claim 1 , wherein the starting material comprises a material having resistivity in a range of 0.1 to 10 ohm-cm.5. The layered structure of claim 1 , the starting material comprises a plurality of layers stacked vertically claim 1 , wherein a resistivity of the plurality of layers of the starting material varies.6. The layered structure of claim 1 , wherein the starting material layer is a silicon substrate with a <111> or <100> crystal orientation.7. The layered structure of claim 1 , wherein the fully depleted porous layer comprises a first porosity in a first region and a second porosity in a second region.8. The layered structure of claim 1 , wherein the fully depleted porous layer is lattice matched to the starting material.9. The layered structure of claim 7 , wherein the fully depleted porous layer comprises a plurality of sublayers stacked vertically claim 7 , whereina porosity ...

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Номер записи: 82

16-01-2020 дата публикации

COMPOUND SEMICONDUCTOR SUBSTRATE

Номер: US20200020778A1

Автор: Kawamura Keisuke, NARUKAWA Mitsuhisa, OUCHI Sumito, Suzuki Hiroki

Принадлежит:

A compound semiconductor substrate includes a SiC (silicon carbide) layer, a AlN (aluminum nitride) buffer layer formed on the SiC layer, an Al (aluminum) nitride semiconductor layer formed on the AlN buffer layer, a composite layer formed on the Al nitride semiconductor layer, a GaN (gallium nitride) layer as an electron transition layer formed on the composite layer, and an Al nitride semiconductor layer as a barrier layer formed on the GaN layer. The composite layer includes C—GaN layers stacked in a vertical direction, and an AlN layer formed between the C—GaN layers. 1. A compound semiconductor substrate comprising:a SiC layer,a buffer layer consisting of AlN, formed on the SiC layer,a nitride semiconductor layer containing Al formed on the buffer layer,a composite layer formed on the nitride semiconductor layer,an electron transition layer consisting of GaN, formed on the composite layer, anda barrier layer formed on the electron transition layer, whereinthe composite layer includes a plurality of first layers, being stacked in a vertical direction, consisting of GaN including carbon, and a second layer consisting of AlN formed between the plurality of the first layers.2. The compound semiconductor substrate according to claim 1 , wherein{'sup': 18', '3', '21', '3, 'each of the plurality of the first layers has an average carbon atomic concentration of 1*10atoms/cmor more and 1*10atoms/cmor less.'}3. The compound semiconductor substrate according to claim 1 , whereinthe second layer has a thickness of 10 nanometers or more and 15 nanometers or less.4. The compound semiconductor substrate according to claim 1 , whereinthe first layer has a thickness of 550 nanometers or more and 2000 nanometers or less.5. The compound semiconductor substrate according to claim 1 , whereinthe compositional ratio of Al inside the nitride semiconductor layer decreases from a bottom to a top.6. The compound semiconductor substrate according to claim 1 , wherein the nitride ...

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Номер записи: 83

17-04-2014 дата публикации

METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE

Номер: US20140106505A1

Автор: Maruyama Hotaka, OIKAWA Yoshiaki, OKAZAKI Kenichi

Принадлежит: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Disclosed is a method to manufacture a thin film transistor having an oxide semiconductor as a channel formation region. The method includes; forming an oxide semiconductor layer over a gate insulating layer; forming a source and drain electrode layers over and in contact with the oxide semiconductor layer so that at least portion of the oxide semiconductor layer is exposed; and forming an oxide insulating film over and in contact with the oxide semiconductor layer. The exposed portion of the oxide semiconductor may be exposed to a gas containing oxygen in the presence of plasma before the formation of the oxide insulating film. The method allows oxygen to be diffused into the oxide semiconductor layer, which contributes to the excellent characteristics of the thin film transistor. 1. (canceled)2. A method for manufacturing a semiconductor device , the method comprising the steps of:forming a gate electrode layer, a gate insulating layer, and an oxide semiconductor layer over a substrate; andperforming plasma treatment on the oxide semiconductor layer in the presence of a gas containing an oxygen element.3. The method according to claim 2 ,wherein the step of forming the oxide semiconductor layer is performed so that a part of the oxide semiconductor layer is exposed.4. The method according to claim 2 , further comprising a step of forming an oxide insulating film over the gate electrode layer claim 2 , the gate insulating layer claim 2 , and the oxide semiconductor layer.5. The method according to claim 4 ,wherein the oxide insulating film comprises silicon.6. The method according to claim 2 ,wherein the gas is selected from an oxygen gas, a nitrogen oxide gas, and a nitrogen dioxide gas.7. The method according to claim 2 ,wherein the oxide semiconductor layer comprises indium, zinc, oxygen, and a metal which is selected from Ga, Fe, Ni, Mn, and Co.8. The method according to claim 2 , further comprising the step of forming a source electrode layer and a drain ...

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Номер записи: 84

28-01-2016 дата публикации

Fabrication of Semiconductor Device Using Alternating High and Low Temperature Layers

Номер: US20160027643A1

Автор: Beach Robert, Bridger Paul

Принадлежит:

A method for fabricating a III-nitride semiconductor body that includes high temperature and low temperature growth steps. 121-. (canceled)22. A method of fabricating a semiconductor device , said method comprising:providing a substrate;growing a III-nitride body over a major surface of said substrate to a final thickness over a growth period of time, wherein a growth temperature is varied over said growth period of time;said III-nitride body comprising at least two AlN layers grown at different temperatures.23. The method of claim 22 , wherein said III-nitride body further comprises a superlattice.24. The method of claim 22 , wherein said III-nitride body further comprises a superlattice claim 22 , and wherein a number of layers grown at a high temperature is equal to a number of layers grown at a low temperature.25. The method of claim 22 , wherein said growth temperature is varied in cycles over said growth period of time claim 22 , each cycle including a period of a high temperature and a period of a low temperature.26. The method of claim 22 , further comprising forming a buffer layer over said III-nitride body.27. The method of claim 26 , further comprising forming an active layer over said buffer layer claim 26 , said active layer providing an active region for fabricating a power FET.28. The method of claim 25 , wherein said low temperature in each cycle is varied.29. The method of claim 25 , wherein said high temperature in each cycle is varied.30. The method of claim 25 , wherein said low temperature and said high temperature in each cycle are varied.31. The method of claim 25 , wherein said high temperature in each cycle is the same.32. The method of claim 25 , wherein said low temperature in each cycle is the same.33. The method of claim 22 , wherein a period of high temperature growth is varied.34. The method of claim 22 , wherein a period of low temperature growth is varied.35. The method of claim 22 , wherein a period of high temperature growth and a ...

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Номер записи: 85

26-01-2017 дата публикации

Nitride semiconductor component and process for its production

Номер: US20170025564A1

Автор: Alois Krost, Armin Dadgar

Принадлежит: Allos Semiconductors GmbH

A process for the production of a layer structure of a nitride semiconductor component on a silicon surface, comprising: provision of a substrate having a silicon surface; deposition of an aluminium-containing nitride nucleation layer on the silicon surface of the substrate; optional: deposition of an aluminium-containing nitride buffer layer on the nitride nucleation layer; deposition of a masking layer on the nitride nucleation layer or, if present, on the first nitride buffer layer; deposition of a gallium-containing first nitride semiconductor layer on the masking layer, wherein the masking layer is deposited in such a way that, in the deposition step of the first nitride semiconductor layer, initially separate crystallites grow that coalesce above a coalescence layer thickness and occupy an average surface area of at least 0.16 μm 2 in a layer plane of the coalesced nitride semiconductor layer that is perpendicular to the growth direction.

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Номер записи: 86

26-01-2017 дата публикации

Uv light emitting devices and systems and methods for production

Номер: US20170025565A1

Автор: Doug Collins, Robert Walker, Yitao Liao

Принадлежит: RayVio Corp

A method of fabricating an ultraviolet (UV) light emitting device includes receiving a UV transmissive substrate, forming a first UV transmissive layer comprising aluminum nitride upon the UV transmissive substrate using a first deposition technique at a temperature less than about 800 degrees Celsius or greater than about 1200 degrees Celsius, forming a second UV transmissive layer comprising aluminum nitride upon the first UV transmissive layer comprising aluminum nitride using a second deposition technique that is different from the first deposition technique, at a temperature within a range of about 800 degrees Celsius to about 1200 degrees Celsius, forming an n-type layer comprising aluminum gallium nitride layer upon the second UV transmissive layer, forming one or more quantum well structures comprising aluminum gallium nitride upon the n-type layer, and forming a p-type nitride layer upon the one or more quantum well structures.

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Номер записи: 87

26-01-2017 дата публикации

Light emitting diode and method of manufacturing the same

Номер: US20170025568A1

Автор: Jaesam SHIM, Jinhong LEE, Jinyoung Park, Kwangjae Lee, Taeksoo JI, Wangki KIM

Принадлежит: INDUSTRY FOUNDATION OF CHONNAM NATIONAL UNIVERSITY

A light emitting diode and a method of manufacturing the light emitting diode are provided. The light emitting diode includes an n-type semiconductor layer, an inclined type superlattice thin film layer, an active layer, and a p-type semiconductor layer. The n-type semiconductor layer is disposed on a substrate. The inclined type superlattice thin film layer is disposed on the n-type semiconductor layer and includes a plurality of thin film pairs in which InGaN thin films and GaN thin films are sequentially stacked. The active layer having a quantum well structure is disposed on the inclined type superlattice thin film layer. The p-type semiconductor layer is disposed on the active layer. Composition ratio of Indium (In) included in the InGaN thin film is increased as getting closer to the active layer. Thus, internal residual strain is reduced, and quantum confinement effect is enhanced, and internal quantum efficiency is increased.

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Номер записи: 88

24-01-2019 дата публикации

INTEGRATED PHOTONICS INCLUDING GERMANIUM

Номер: US20190025513A1

Автор: Adam Thomas, COOLBAUGH Douglas, Leake Gerald L.

Принадлежит:

A photonic structure can include in one aspect one or more waveguides formed by patterning of waveguiding material adapted to propagate light energy. Such waveguiding material may include one or more of silicon (single-, poly-, or non-crystalline) and silicon nitride. 1. A photonic structure comprising:dielectric material formed over silicon;a trench formed in the dielectric material extending to the silicon;a germanium formation formed in the trench;a top doping region formed in an area of the germanium formation so that the top doping region is spaced from the trench by a spacing distance equal to or greater than a threshold distance;a top contact formed on the top doping region, wherein the top contact is formed of a semiconductor compatible metallization material that is reflective to wavelengths in the range of from about 900 nm to about 1600 nm.2. The photonic structure of claim 1 , wherein an entire perimeter of the top doping region is spaced from the trench by a spacing distance equal to or greater than a threshold distance.3. (canceled)4. The photonic structure of claim 1 , wherein the threshold distance is in the range of 200 nm to 1000 nm.5. (canceled)6. The photonic structure of claim 1 , wherein the threshold distance is 750 nm.7. (canceled)8. The photonic structure of claim 1 , wherein the top contact formed on the doping region is formed in an area of the doping region so that an entire perimeter of the contact is spaced from a perimeter of the doping region by a spacing distance that is equal to or greater than a threshold distance.9. A photonic structure comprising:silicon having a doping region;a germanium formation adapted to receive light transmitted by the silicon;an oppositely doped doping region formed on the germanium formation;a silicide formation formed on the doping region of the silicon;a conductive material formation formed on the silicide formation; anda conductive material formation formed on the germanium formation.10. The photonic ...

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Номер записи: 89

23-01-2020 дата публикации

INTEGRATED PHOTONICS INCLUDING GERMANIUM

Номер: US20200026003A1

Автор: Adam Thomas, COOLBAUGH Douglas, Leake Gerald L.

Принадлежит:

A photonic structure can include in one aspect one or more waveguides formed by patterning of waveguiding material adapted to propagate light energy. Such waveguiding material may include one or more of silicon (single-, poly-, or non-crystalline) and silicon nitride. 1. A method of fabricating a photodetector structure comprising:forming dielectric material over a silicon waveguide;etching a trench in the dielectric material extending to the silicon waveguide;epitaxially growing germanium within the trench;annealing germanium formed by the epitaxially growing;repeating the epitaxially growing and the annealing;depositing metal within a second trench, the second trench having a bottom defined by the silicon waveguide and a sidewall defined by the dielectric material;performing silicide formation annealing so that the metal reacts with the silicon to form a silicide formation at a bottom of the trench; andperforming transformation stage annealing so that the silicide formation is transformed into a low resistivity phase.2. The method of claim 1 , wherein the depositing metal results in unreacted metal being formed on a sidewall of the second trench claim 1 , and wherein the method includes forming a capping layer over the metal with the metal in an unreacted state prior to the performing silicide formation annealing.3. The method of claim 1 , wherein the depositing metal results in unreacted metal being formed on a sidewall of the second trench claim 1 , wherein the method includes forming a capping layer over the metal with the metal in an unreacted state prior to the performing silicide formation annealing claim 1 , and wherein the method includes removing the capping layer and the unreacted metal prior to the performing transformation stage annealing.4. The method of claim 1 , wherein the transformation stage annealing is performed at a higher annealing temperature than the silicide formation annealing.5. The method of claim 1 , wherein the metal is selected from ...

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Номер записи: 90

24-01-2019 дата публикации

SEMICONDUCTOR STRUCTURE HAVING SETS OF III-V COMPOUND LAYERS AND METHOD OF FORMING

Номер: US20190027360A1

Автор: Chen Chi-Ming, Liu Po-Chun, Tsai Chia-Shiung, Yu Chung-Yi

Принадлежит:

A semiconductor structure including a substrate and a nucleation layer over the substrate. The semiconductor structure further includes a first III-V layer over the nucleation layer, wherein the first III-V layer includes a first dopant type. The semiconductor structure further includes one or more sets of III-V layers over the first III-V layer. Each set of the one or more sets of III-V layers includes a lower III-V layer, wherein the lower III-V layer has a second dopant type opposite the first dopant type, and an upper III-V layer on the lower III-V layer, wherein the upper III-V layer has the first dopant type. The semiconductor structure further includes a second III-V layer over the one or more sets of III-V layers, the second III-V layer having the second dopant type. 1. A semiconductor structure comprising:a substrate;a nucleation layer over the substrate;a first III-V layer over the nucleation layer, wherein the first III-V layer includes a first dopant type; a lower III-V layer, wherein the lower III-V layer has a second dopant type opposite the first dopant type, and', 'an upper III-V layer on the lower III-V layer, wherein the upper III-V layer has the first dopant type; and', 'a second III-V layer over the one or more sets of III-V layers, the second III-V layer having the second dopant type., 'one or more sets of III-V layers over the first III-V layer, each set of the one or more sets of III-V layers comprising2. The semiconductor structure of claim 1 , further comprising a dielectric layer over the second III-V layer.3. The semiconductor structure of claim 2 , further comprising an active layer between the dielectric layer and the second III-V layer.4. The semiconductor structure of claim 2 , further comprising a gate electrode over the dielectric layer.5. The semiconductor structure of claim 1 , further comprising a pair of source/drain (S/D) electrodes claim 1 , wherein each of the pair of S/D electrodes directly contacts the second III-V layer.6. ...

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Номер записи: 91

28-01-2021 дата публикации

SEMICONDUCTOR STRUCTURE HAVING SETS OF III-V COMPOUND LAYERS AND METHOD OF FORMING

Номер: US20210028016A1

Автор: Chen Chi-Ming, Liu Po-Chun, Tsai Chia-Shiung, Yu Chung-Yi

Принадлежит:

A semiconductor structure includes a substrate. The semiconductor structure further includes a buffer layer over the substrate, wherein the buffer layer comprises a plurality of III-V layers, and a dopant type of each III-V layer of the plurality of III-V layers is opposite to a dopant of adjacent III-V layers of the plurality of III-V layers. The semiconductor structure further includes an active layer over the buffer layer. The semiconductor structure further includes a dielectric layer over the active layer. 1. A semiconductor structure comprising:a substrate;a buffer layer over the substrate, wherein the buffer layer comprises a plurality of III-V layers, and a dopant type of each III-V layer of the plurality of III-V layers is opposite to a dopant of adjacent III-V layers of the plurality of III-V layers;an active layer over the buffer layer; anda dielectric layer over the active layer.2. The semiconductor structure of claim 1 , further comprising a channel layer between the buffer layer and the active layer.3. The semiconductor structure of claim 2 , further comprising a source electrode directly contacting the channel layer.4. The semiconductor structure of claim 1 , wherein at least one of plurality of III-V layers comprises GaN.5. The semiconductor structure of claim 1 , further comprising a nucleation layer between the substrate and the buffer layer.6. The semiconductor structure of claim 5 , wherein the nucleation layer comprises AlN.7. The semiconductor structure of claim 5 , wherein the nucleation layer is configured to reduce lattice mismatch between the substrate and the buffer layer.8. The semiconductor structure of claim 1 , wherein the buffer layer directly contacts the substrate.9. A method of forming a semiconductor structure claim 1 , the method comprising:forming a nucleation layer over a substrate;growing a buffer layer over the nucleation layer, wherein growing the buffer layer comprises growing a plurality of pairs of layers, each pair of ...

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Номер записи: 92

02-02-2017 дата публикации

Breakdown Resistant HEMT Substrate and Device

Номер: US20170033210A1

Автор: Gilberto Curatola, Ingo Daumiller, Martin Huber

Принадлежит: INFINEON TECHNOLOGIES AUSTRIA AG

A compound semiconductor device structure having a main surface and a rear surface includes a silicon substrate including first and second substrate layers. The first substrate layer extends to the rear surface. The second substrate layer extends to a first side of the substrate that is opposite from the rear surface such that the first substrate layer is completely separated from the first side by the second substrate layer. A nucleation region is formed on the first side of the silicon substrate and includes a nitride layer. A lattice transition layer is formed on the nucleation region and includes a type III-V semiconductor nitride. The lattice transition layer is configured to alleviate stress arising in the silicon substrate due to lattice mismatch between the silicon substrate and other layers in the compound semiconductor device structure. The second substrate layer is configured to suppress an inversion layer in the silicon substrate.

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Номер записи: 93

01-02-2018 дата публикации

SILICON GERMANIUM SELECTIVE OXIDATION PROCESS

Номер: US20180033615A1

Автор: TJANDRA Agus Sofian

Принадлежит:

Implementations described herein relate to selective oxidation processes for semiconductor device manufacturing. In one implementation, the process includes delivering a substrate having a semiconductor device comprising at least a silicon material and a silicon germanium material formed thereon to a process chamber. Process variables are determined based upon the germanium concentration of the silicon germanium material and a desired oxide thickness and a selective oxidation process is performed utilizing the determined process variables. 1. A selective oxidation method , comprising:pressurizing a process chamber to greater than about 500 Torr;heating a process region of the process chamber to a temperature less than about 700° C.;generating reactive species comprising hydrogen and oxygen in the process region; andexposing a substrate comprising at least a silicon material and a silicon germanium material to the reactive species to selectively oxidize the silicon germanium material preferentially to the silicon material.2. The method of claim 1 , wherein the silicon material and the silicon germanium material are simultaneously exposed to the reactive species.3. The method of claim 2 , wherein the silicon germanium material is selectively oxidized at a rate of between 2 times and 16 times greater than an oxidation rate of the silicon material.4. The method of claim 1 , wherein the reactive species are hydroxyl radicals.5. The method of claim 1 , wherein the reactive species are hydroxide ions.6. The method of claim 1 , wherein the reactive species are hydrogen and oxygen radicals.7. The method of claim 1 , wherein the reactive species are hydrogen and oxygen ions.8. The method of claim 1 , wherein a ratio of oxygen to hydrogen is between 19:1 and 1:9.9. The method of claim 1 , further comprising:generating hydroxyl radicals remotely from the process chamber and delivering the hydroxyl radicals to the process region.10. The method of claim 1 , further comprising: ...

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Номер записи: 94

01-02-2018 дата публикации

METHOD OF UNIFORM CHANNEL FORMATION

Номер: US20180033873A1

Автор: BAO XINYU, Yan Chun

Принадлежит:

Embodiments described herein generally provide a method and apparatus to form semiconductor devices. Specifically, embodiments describe an apparatus and methods of forming channels in sub-5 nm node FinFETS. The method provides for various processing steps to deposit a dielectric layer over a substrate. The method continues by etching a trench in the dielectric layer, depositing a silicon layer within the trench, depositing a buffer layer on top of the silicon layer in the trench, removing a portion of the buffer layer to form a planar surface, etching the buffer layer into a v-shape, and depositing a channel layer on top of the v-shaped buffer layer. The v-shaped buffer layer advantageously negates facet formation and provides for an InGaAs fin-channel with uniform distribution of indium and gallium throughout the channel. 1. A method of channel formation , comprising:depositing a dielectric material on a substrate;etching the dielectric material to form a trench;depositing a silicon material in the trench;overfilling the trench with a buffer material;planarizing the buffer material to remove the overfill;etching the buffer material to form a v-shaped trench; anddepositing a channel material in the v-shaped trench.2. The method of claim 1 , wherein the etching the dielectric material to form the trench exposes a portion of the substrate and wherein the silicon material is deposited on the exposed portion of the substrate.3. The method of claim 1 , further comprising etching the dielectric material to expose the channel material.4. The method of claim 1 , wherein the buffer material is a type III-V semiconductor material.5. The method of claim 4 , wherein the buffer material is selected from the group consisting of gallium arsenide (GaAs) and indium phosphide (InP).6. The method of claim 1 , wherein the dielectric material is selected from the group consisting of silicon oxide claim 1 , silicon nitride claim 1 , and aluminum oxide.7. The method of claim 1 , wherein ...

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Номер записи: 95

17-02-2022 дата публикации

NUCLEATION LAYER DEPOSITION METHOD

Номер: US20220051893A1

Автор: MAUDER Christof Martin

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A nucleation layer comprised of group III and V elements is directly deposited onto the surface of a substrate made of a group IV element. Together with a first gaseous starting material containing a group III element, a second gaseous starting material containing a group V element is introduced at a process temperature of greater than 500° C. into a process chamber containing the substrate. It is essential that at least at the start of the deposition process of the nucleation layer, a third gaseous starting material containing a group IV element is fed into the process chamber, together with the first and second gaseous starting material. The third gaseous starting material develops an n-doping effect in the deposited III-V crystal, which causes a decrease in damping at a dopant concentration of less than 1×10cm. 1321. A method for depositing a nucleation layer () comprised of group III and V elements directly onto a surface () of a substrate () made of a group IV element , the method comprising:{'b': ['8', '1'], '#text': 'introducing a first gaseous starting material containing a group III element together with a second gaseous starting material containing a group V element into a process chamber () containing the substrate () at a process temperature greater than 500° C.;'}{'b': ['3', '8'], '#text': 'at least at a start of the deposition of the nucleation layer (), feeding a third gaseous starting material containing a group IV element into the process chamber () together with the first and second gaseous starting materials; and'}{'b': ['4', '3', '6', '4', '5', '6', '4'], '#text': 'depositing a buffer layer () on the nucleation layer () and depositing an active layer () on the buffer layer () in such manner that a two-dimensional electron gas develops on a boundary surface () between the active layer () and the buffer layer (),'}{'b': '8', 'sup': ['17', '18', '−3'], '#text': 'wherein a partial pressure and/or mass flow of the third gaseous starting material in ...

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Номер записи: 96

05-02-2015 дата публикации

Method of fabricating a superlattice structure

Номер: US20150037925A1

Автор: Allan Evans, Andrew Hood, William Tennant

Принадлежит: Teledyne Scientific and Imaging LLC

A method of fabricating a superlattice structure requires that atoms of a first III-V semiconductor compound be introduced into a vacuum chamber such that the atoms are deposited uniformly on a substrate. Atoms of at least one additional III-V compound are also introduced such that the atoms of the two III-V compounds form a repeating superlattice structure of alternating thin layers. Atoms of a surfactant are also introduced into the vacuum chamber while the III-V semiconductor compounds are being introduced, or immediately thereafter, such that the surfactant atoms act to improve the quality of the resulting SL structure. The surfactant is preferably bismuth, and the III-V semiconductor compounds are preferably GaSb along with either InAs or InAsSb; atoms of each material are preferably introduced using molecular beam epitaxy. The resulting superlattice structure is suitably used to form at least a portion of an IR photodetector.

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Номер записи: 97

17-02-2022 дата публикации

Advanced electronic device structures using semiconductor structures and superlattices

Номер: US20220052223A1

Автор: Matthew GODFREY, Petar Atanackovic

Принадлежит: Silanna UV Technologies Pte Ltd

Semiconductor structures and methods for forming those semiconductor structures are disclosed. For example, a semiconductor structure with a p-type superlattice region, an i-type superlattice region, and an n-type superlattice region is disclosed. The semiconductor structure can have a polar crystal structure with a growth axis that is substantially parallel to a spontaneous polarization axis of the polar crystal structure. In some cases, there are no abrupt changes in polarisation at interfaces between each region. At least one of the p-type superlattice region, the i-type superlattice region and the n-type superlattice region can comprise a plurality of unit cells exhibiting a monotonic change in composition from a wider band gap (WBG) material to a narrower band gap (NBG) material or from a NBG material to a WBG material along the growth axis to induce p-type or n-type conductivity.

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Номер записи: 98

31-01-2019 дата публикации

GROWTH OF III-NITRIDE SEMICONDUCTORS ON THIN VAN DER WAALS BUFFERS FOR MECHANICAL LIFT OFF AND TRANSFER

Номер: US20190035624A1

Автор: Paduano Qing, Siegel Gene P., Snure Michael R.

Принадлежит:

A semiconductor device includes a mechanical release layer, such as a van der Waals buffer layer, with a predetermined material roughness and thickness adjacent to a first substrate; a nucleation layer adjacent to the mechanical release layer; and a first semiconductor layer attached to the nucleation layer. The first semiconductor layer, the nucleation layer, and a portion of the mechanical release layer are releasably connected to the first substrate. The predetermined material roughness and thickness of the mechanical release layer determines a bonding strength of the first semiconductor layer to the first substrate. The semiconductor device may include an aluminum nitride insert layer adjacent to the first semiconductor layer; an aluminum gallium nitride barrier layer adjacent to the aluminum nitride insert layer; and a second semiconductor layer adjacent to the aluminum gallium nitride barrier layer. The semiconductor device may include a second substrate attached to the released first semiconductor layer. 1. A semiconductor device comprising:a first substrate;a mechanical release layer comprising a predetermined material roughness and thickness adjacent to the first substrate;a nucleation layer adjacent to the mechanical release layer; anda first semiconductor layer attached to the nucleation layer,wherein the first semiconductor layer, the nucleation layer, and a portion of the mechanical release layer are configured to be releasably connected to the first substrate, andwherein the predetermined material roughness and thickness of the mechanical release layer determines a bonding strength of the mechanical release layer to the first substrate.2. The semiconductor device of claim 1 , wherein the mechanical release layer comprises a substantially planar surface interfacing with the nucleation layer.3. The semiconductor device of claim 1 , wherein the mechanical release layer comprises a substantially non-planar surface interfacing with the nucleation layer.4. ...

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Номер записи: 99

30-01-2020 дата публикации

Buffer layer for Gallium Nitride-on-Silicon epitaxy

Номер: US20200035482A1

Автор: Knieriem Karl M., Ramer Jeff C.

Принадлежит:

Embodiments generally relate to multi-layer buffer structures on silicon. One method for forming such a structure comprises: providing a (111) silicon substrate; using ALD to deposit a first layer of AlN on the substrate; using first and second precursor materials at a first V-III ratio to deposit a plurality of AlN islands forming a second layer on the first layer; using the first and second precursor materials at a second V-III ratio, to deposit a third layer of AlN overlying and in contact with the islands and the first layer between the islands, forming domains; and using the first and second precursor materials at a third V-III ratio, to deposit a fourth layer of AlN on the third layer. All depositions occur at one predetermined temperature range. The fourth layer is characterized by a fourth layer top surface that is anatomically smooth. 1. A method for forming a multi-layer AlN buffer structure on silicon , the method comprising:providing a (111) oriented silicon substrate having a top surface;using atomic layer deposition to deposit, at a predetermined temperature range, a first layer of AlN on the top surface;using first and second precursor materials, characterized by a first V-III ratio, to deposit, at the predetermined temperature range, a plurality of AlN islands forming a second layer overlying and in contact with the first layer;using the first and second precursor materials, characterized by a second V-III ratio, to deposit, at the predetermined temperature range, a third layer of AlN, the third layer overlying and in contact with the islands and the first layer between the islands, forming domains; andusing the first and second precursor materials, characterized by a third V-III ratio, to deposit, at the predetermined temperature range, a fourth layer of AlN, the fourth layer overlying and in contact with the third layer, wherein the fourth layer is characterized by a fourth layer top surface that is anatomically smooth.2. The method of claim 1 , ...

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Номер записи: 100