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Небесная энциклопедия

Космические корабли и станции, автоматические КА и методы их проектирования, бортовые комплексы управления, системы и средства жизнеобеспечения, особенности технологии производства ракетно-космических систем

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Мониторинг СМИ

Мониторинг СМИ и социальных сетей. Сканирование интернета, новостных сайтов, специализированных контентных площадок на базе мессенджеров. Гибкие настройки фильтров и первоначальных источников.

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Применить Всего найдено 595. Отображено 100.
26-07-2012 дата публикации

Integrated structures of high performance active devices and passive devices

Номер: US20120192139A1
Автор: Anthony K. Stamper, Daniel S. Vanslette, Robert M. Rassel
Принадлежит: International Business Machines Corp

Integrated structures having high performance CMOS active devices mounted on passive devices are provided. The structure includes an integrated passive device chip having a plurality of through wafer vias, mounted to a ground plane. The structure further includes at least one CMOS device mounted on the integrated passive device chip using flip chip technology and being grounded to the ground plane through the through wafer vias of the integrated passive device chip.

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Номер записи: 1
01-01-2015 дата публикации

DE-POP ON-DEVICE DECOUPLING FOR BGA

Номер: US20150001716A1
Автор: BROWN Paul James, Chan Alex
Принадлежит:

Embodiments of the invention place surface-mount devices such as decoupling capacitors, resistors or other devices directly on the underside of a ball grid array (BGA) electronic integrated circuit (EIC) package, in place of de-populated BGA pads. 1. An electronic integrated circuit (EIC) package comprising:an EIC substrate;an array of ball grid array (BGA) pads on a first side of said EIC substrate, arranged in a grid pattern of rows and columns; andcontact pads on said first side of said EIC substrate to accommodate electrical connection of a surface-mount device, wherein said surface-mount device occupies a grid location of said grid pattern in place of one or more BGA pads.2. The EIC package of claim 1 , wherein said contact pads comprise at least two adjacent contact pads.3. The EIC package of claim 2 , wherein each of the contact pads is connected to an adjacent BGA pad by a conductor on said first side of said EIC substrate.4. The EIC package of claim 1 , wherein said surface-mount device comprises a two-port device.5. The EIC package of claim 4 , wherein said surface-mount device comprises a decoupling capacitor.6. The EIC package of claim 1 , wherein said surface-mount device is selected from a set of a capacitor claim 1 , a resistor claim 1 , an inductor claim 1 , a diode claim 1 , a transistor claim 1 , a capacitor array claim 1 , and a resistor-capacitor circuit.7. The EIC package of claim 1 , wherein said BGA grid comprises a pitch of between about 0.4 mm×0.4 mm and about 1.27 mm×1.27 mm.8. The EIC package of claim 7 , wherein said BGA grid comprises an irregular pitch.9. A computer-aided design tool for accommodating a surface-mount device on a first surface of a ball grid array (BGA) electronic integrated circuit (EIC) package claim 7 , said tool comprising:a design tool configured to identify, in an EIC configuration of BGA pads in a grid pattern on said first side of said EIC package, at least two contact pads for forming directly on said first ...

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Номер записи: 2
01-01-2015 дата публикации

Semiconductor package having wire bond wall to reduce coupling

Номер: US20150002226A1
Автор: Margaret Szymanowski, Paul Hart, Shun Meen Kuo
Принадлежит: FREESCALE SEMICONDUCTOR INC

A system and method for a package including a wire bond wall to reduce coupling is presented. The package includes a substrate, and a first circuit on the substrate. The first circuit includes a first electrical device, a second electrical device, and a first wire bond array interconnecting the first electrical device and the second electrical device. The package includes a second circuit on the substrate adjacent to the first circuit, the second circuit includes a second wire bond array interconnecting a third electrical device and a fourth electrical device. The package includes a wire bond wall including a plurality of wire bonds over the substrate between the first circuit and the second circuit. The wire bond wall is configured to reduce an electromagnetic coupling between the first circuit and the second circuit during an operation of at least one of the first circuit and the second circuit.

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Номер записи: 3
06-01-2022 дата публикации

INTERPOSER

Номер: US20220005757A1
Автор: AN Youngjun, LEE Gilseon, Oh Changwoo, SHIN Jungkyun
Принадлежит: AMOSENSE CO., LTD

The present disclosure relates to an interposer. The interposer includes: a support body formed of a ceramic material, a connection electrode configured to the top surface and bottom surface of the support body, and a shielding member disposed at an outer surface of the support body. At least a part of the support body is disposed along the edge of a substrate, and electrically connects the substrate and a substrate. The interposer is formed of a ceramic material and thus make it possible to implement a fine pattern, to improve dimensional stability by preventing the bending deformation of ceramic green sheets, and to raise the reliability of signal transmission. Therefore, the interposer can contribute to implementing high performance of an electronic device and reducing the size of the electronic device. 1. An interposer comprising:a support body including a top surface and a bottom surface, at least a part of the support body disposed along the edge of a substrate;a connection electrode configured to connect the top surface and bottom surface of the support body; anda shielding member disposed at an outer surface of the support body.2. The interposer of claim 1 , wherein the support body is disposed along the edge of the substrate claim 1 , as one part or a combination of two or more parts claim 1 , selected from a group including:a straight part disposed in a straight line shape along a part of the edge of the substrate;a inclined part disposed in an inclined shape so as to be adjacent to a part of the edge of the substrate or a corner of the substrate; anda curved part disposed in a round shape.3. The interposer of claim 1 , wherein the support body is formed of a ceramic material.4. The interposer of claim 1 , wherein the connection electrode is formed as a conductive material filled in a via hole formed through the support body in a thickness direction thereof to connect the top and bottom surfaces of the support body.5. The interposer of claim 4 , wherein ...

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Номер записи: 4
07-01-2021 дата публикации

SEMICONDUCTOR DEVICE

Номер: US20210005535A1
Автор: HANGAI Masatake, SHINJO Shintaro, YAMAGUCHI Yutaro, YAMANAKA Koji
Принадлежит: Mitsubishi Electric Corporation

In a semiconductor device including gate fingers each having a linear shape extending from a feed line, and arranged in areas between drain electrodes and source electrodes, open stubs are connected directly to the feed line. 1. A semiconductor device comprising:a semiconductor substrate;a plurality of drain electrodes, each of the drain electrodes being disposed along one direction on the semiconductor substrate;a plurality of source electrodes, each of the source electrodes being disposed in an area between corresponding adjacent two of the drain electrodes on the semiconductor substrate, and being disposed along the one direction;a feed line being disposed on the semiconductor substrate, and having a band shape extending in the one direction; an input line disposed on the semiconductor substrate;', 'an air bridge connecting the feed line and the input line;, 'a plurality of gate fingers, each of the gate fingers having a linear shape extending from the feed line, and being disposed in an area between two adjacent electrodes on the semiconductor substrate, one of the two adjacent electrodes being a corresponding one of the drain electrodes and the other being a corresponding one of the source electrodes; and'}a plurality of open stubs being disposed on the semiconductor substrate, and having a line length that eliminates a target higher harmonic wave, and each of the open stubs passing under the air bridge and being connected directly to the feed line.2. The semiconductor device according to claim 1 , wherein the open stubs are arranged so as to correspond one-to-one to the gate fingers.3. The semiconductor device according to claim 1 , wherein the open stubs are made from a metallic material identical to that of the gate fingers.4. A semiconductor device comprising:a semiconductor substrate;a plurality of drain electrodes, each of the drain electrodes being disposed along one direction on the semiconductor substrate;a plurality of source electrodes, each of the ...

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Номер записи: 5
02-01-2020 дата публикации

INDUCTOR AND TRANSMISSION LINE WITH AIR GAP

Номер: US20200006261A1
Автор: LIN Kevin
Принадлежит:

An integrated circuit structure comprises one or more sets of first and second conductive lines along a same direction in an interlayer dielectric (ILD), the first and second conductive lines having a width greater than 2 μm. An air gap is in the ILD between the first and second conductive lines, the air gap extending across the ILD to sidewalls of the first and second conductive lines. 1. An integrated circuit structure , comprising:one or more sets of first and second conductive lines along a same direction in an interlayer dielectric (ILD), the first and second conductive lines having a width greater than 2 μm; andan air gap in the ILD between the first and second conductive lines, the air gap extending across the ILD to sidewalls of the first and second conductive lines.2. The integrated circuit structure of claim 1 , wherein the width of the air gap and a distance between the first and second conductive lines is approximately 1 to 10 μm.3. The integrated circuit structure of claim 1 , wherein the air gap includes one or more spacers along at least one top corner of the air gap and at least one sidewall of the first and second conductive lines.4. The integrated circuit structure of claim 3 , wherein the one or more spacers leave an opening in the air gap of approximately 100-300 nm.5. The integrated circuit structure of claim 3 , wherein the air gap includes left and right spacers formed along the sidewalls of the first and second conductive lines claim 3 , respectively claim 3 , where the left and right spacers are coplanar with a top surface of the first and second conductive lines.6. The integrated circuit structure of claim 1 , wherein the air gap is formed as a continuous recess between the first and second conductive lines.7. The integrated circuit structure of claim 1 , wherein the air gap is formed as non-contiguous air gap segments that are spaced apart by the ILD to provide structural support to the sidewalls of the first and second conductive lines.8. ...

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Номер записи: 6
03-01-2019 дата публикации

GUARD BOND WIRES IN AN INTEGRATED CIRCUIT PACKAGE

Номер: US20190006286A1
Автор: Cuoco Vittorio, Van Der Zanden Josephus, VOLKHINE Youri, Walesieniuk Anna, ZHU Yi
Принадлежит:

An integrated circuit package is provided. The integrated circuit package comprises a first and second guard bond wire. The first guard bond wire has a first and second end coupled to ground. The second guard bond wire has a first and second end coupled to ground. The integrated circuit package further comprises a die. The die is mounted between the first and second guard bond wires such that the first and second guard bond wires distort a magnetic field between at least an input terminal and an output terminal of the die. 1. An integrated circuit package , comprising:a first guard bond wire having a first and second end coupled to ground;a second guard bond wire having a first and second end coupled to ground;a die mounted between the first and second guard bond wires such that the first and second guard bond wires distort a magnetic field between at least an input terminal and an output terminal of the die, wherein the die has a surface area with a first side and a second side that is opposite to the first side and at least a portion of the first guard bond wire is aligned with the first side of the die and at least a portion of the second guard bond wire is aligned with the second side of the die; anda flange on which the die is mounted;wherein the at least a portion of the first guard bond wire is aligned with the first side such that the at least a portion of the first bond wire runs parallel to the first side of the die, and wherein the at least a portion of the second guard bond wire is aligned with the second side such that the at least a portion of the second guard bond wire runs parallel to the second side of the die,wherein the first and/or second end of the first guard bond wire is/are coupled to ground through a flange mounted first and/or second capacitor, respectively, and the first and/or second end of the second guard bond wire is/are coupled to ground through a flange mounted third and/or fourth capacitor, respectively.215-. (canceled)16. The ...

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Номер записи: 7
02-01-2020 дата публикации

Voltage controlled oscillator circuit, device, and method

Номер: US20200007080A1
Автор: Chi-Hsien Lin, HO-HSIANG Chen, Hsien-Yuan LIAO, Tzu-Jin Yeh, Ying-Ta Lu
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

A voltage-controlled oscillator (VCO) includes a power supply node configured to have a power supply voltage. A reference node is configured to have a first reference voltage. A transformer-coupled band-pass filter (BPF) is coupled to a cross-coupled pair of transistors. The cross-coupled pair of transistors and the transformer-coupled band-pass filter are positioned between the power supply node and the reference node.

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Номер записи: 8
02-01-2020 дата публикации

PROCESS-INVARIANT DELAY CELL

Номер: US20200007105A1
Автор: CHENG Haitao, Lu Ye, Qiao Dongjiang, Song Chao
Принадлежит:

An integrated circuit (IC) device includes a first resistive strip having an input terminal and an output terminal. The IC device further includes a second resistive strip having a terminal coupled to a voltage. The second resistive strip may be coplanar with the first resistive strip. The IC device further includes a capacitor formed by the first resistive strip and the second resistive strip. 1. An integrated circuit (IC) device comprising:a first resistive strip having an input terminal and an output terminal;a second resistive strip having a terminal coupled to a voltage, the second resistive strip being coplanar with the first resistive strip; anda capacitor formed by the first resistive strip and the second resistive strip.2. The IC device of claim 1 , wherein the first resistive strip and the second resistive strip comprise polysilicon.3. The IC device of claim 1 , wherein the second resistive strip includes portions substantially parallel to the first resistive strip.4. The IC device of claim 1 , wherein the first resistive strip is interdigitated with the second resistive strip.5. The IC device of claim 1 , wherein the first resistive strip and the second resistive strip are configured to be part of a delay cell or a filter.6. The IC device of claim 1 , wherein the first resistive strip and the second resistive strip are serpentine claim 1 , spiral claim 1 , octagonal claim 1 , and/or circular in shape.7. The IC device of claim 1 , wherein the first resistive strip comprises a first resistive material and the second resistive strip comprises a second resistive material that is different from the first resistive material.8. The IC device of claim 1 , wherein a width of the first resistive strip is substantially equal to a gap between the first resistive strip and the second resistive strip.9. The IC device of claim 8 , wherein the width of the first resistive strip is correlated to the gap between the first resistive strip and the second resistive strip such ...

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Номер записи: 9
12-01-2017 дата публикации

CORE FOR HIGH-FREQUENCY TRANSFORMER, AND MANUFACTURING METHOD THEREFOR

Номер: US20170011829A1
Автор: MORITSUGU Nakao, OGURA Katsuhiro
Принадлежит: HITACHI METALS, LTD.

This core for a high-frequency transformer has shape formed by a single roll process by winding a Fe-based nanocrystal alloy thin strip that has a roll contact surface and a free surface while interposing an insulating layer, characterized in that projections having a crater-form depression are dispersed on the free surface of the Fe-based nanocrystal alloy thin strip, and the apexes of the projections are ground and blunted. 1. A core for a high-frequency transformer , having a shape formed by winding an Fe-based nanocrystalline alloy ribbon by a single-roll process with an insulating layer interposed , the Fe-based nanocrystalline alloy ribbon having a roll contact surface and a free surface , whereinthe free surface of the Fe-based nanocrystalline alloy ribbon has dispersed thereon crater-like projections with a concave, and the projections each have a top part that is ground and blunted.2. The core for a high-frequency transformer according to claim 1 , wherein the Fe-based nanocrystalline alloy ribbon has a thickness of 10 to 15 μm.3. A method for manufacturing the core for a high-frequency transformer according to claim 1 , comprising:(1) a step of producing an Fe-based amorphous alloy ribbon for an Fe-based nanocrystalline alloy ribbon by a single-roll process;(2) a step of bring a free surface of the Fe-based amorphous alloy ribbon into contact with a rotating peripheral surface of a cylindrical grindstone, thereby pressure-grinding and blunting top parts of crater-like projections with a concave dispersed on the free surface;(3) a step of forming an insulating layer on the free surface and/or roll contact surface of the Fe-based amorphous alloy ribbon;(4) a step of winding the Fe-based amorphous alloy ribbon having the insulating layer formed thereon; and(5) a step of heat-treating the wound Fe-based amorphous alloy ribbon to cause nanocrystallization, thereby giving an Fe-based nanocrystalline alloy ribbon.4. The core for a high-frequency transformer ...

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Номер записи: 10
21-01-2021 дата публикации

ELECTRONIC DEVICE WITH AN INTEGRAL FILTERING COMPONENT

Номер: US20210020590A1
Автор: CHIU Hsih-Yang, KANG Ting-Cih
Принадлежит:

The present disclosure relates to an electronic device with an integral filtering component. The electronic device includes a semiconductor component, an insulating layer, at least one contact plug, and a filtering component. The insulating layer is disposed on the semiconductor component. The contact plug penetrates through the insulating layer. The filtering component is disposed on the insulating layer and the contact plug. The filtering component includes a bottom electrode, an isolation layer, a top electrode, and a dielectric layer. The bottom electrode is divided into a first segment connected to the contact plug and a second segment separated from the first segment. The isolation layer is disposed on the bottom electrode, the top electrode is disposed in the isolation layer, and the dielectric layer is disposed between the bottom electrode and the top electrode. 1. An electronic device , comprising:a semiconductor component;an insulating layer disposed on the semiconductor component;at least one contact plug penetrating through the insulating layer; and a bottom electrode divided into a first segment connected to the contact plug and a second segment separated from the first segment;', 'an isolation layer disposed on the bottom electrode;', 'a top electrode disposed in the isolation layer; and', 'a dielectric layer disposed between the bottom electrode and the top electrode., 'a filtering component disposed on the insulating layer and the contact plug, the filtering component comprising2. The electronic device of claim 1 , wherein the isolation layer is further disposed in a gap between the first segment and the second segment.3. The electronic device of claim 2 , wherein a lower surface of the bottom electrode is coplanar with a bottom surface of the isolation layer opposite to a top surface of the isolation layer.4. The electronic device of claim 1 , wherein the dielectric layer extends along a top surface of the isolation layer and encircles the top ...

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Номер записи: 11
21-01-2021 дата публикации

THREE DIMENSIONAL METAL INSULATOR METAL CAPACITOR STRUCTURE

Номер: US20210020739A1
Автор: Huang Yen-Chieh, Yeong Sai-Hooi, YU Chia-Ta
Принадлежит: Taiwan Semiconductor Manufacturing Co., Ltd.

The present disclosure relates to a semiconductor device and a manufacturing method, and more particularly to a 3D metal insulator metal (MIM) capacitor structure with an increased capacitance per unit area in a semiconductor structure. The MIM structure includes a substrate, an oxide layer formed over the substrate, and a first metal layer formed over the oxide layer. The first metal layer includes a plurality of mandrels formed on a surface of the first metal layer. The MIM structure also includes a dielectric layer formed over the first metal layer and the plurality of mandrels, a second metal layer formed over on the dielectric layer, and one or more interconnect structures electrically connected to the first and second metal layers. 1. A metal insulator metal (MIM) structure , comprising:a substrate;an oxide layer formed over the substrate;a first metal layer formed over the oxide layer, wherein the first metal layer comprises a plurality of mandrels formed on a surface of the first metal layer;a dielectric layer formed over the first metal layer and the plurality of mandrels;a second metal layer formed over on the dielectric layer; andone or more interconnect structures electrically connected to the first and second metal layers.2. The MIM structure of claim 1 , wherein the first metal layer comprises one or more metal sublayers.3. The MIM structure of claim 1 , wherein the first metal layer comprises titanium nitride.4. The MIM structure of claim 1 , wherein the dielectric layer has a dielectric constant between about 3.9 and about 1000.5. The MIM structure of claim 1 , wherein a height of the plurality of mandrels ranges from about 10 nm to about 300 nm.6. The MIM structure of claim 1 , wherein a space between the plurality of mandrels ranges from about 10 nm to about 100 nm.7. The MIM structure of claim 1 , wherein an aspect ratio of the plurality of mandrels ranges from about 1 to about 30 claim 1 , the aspect ratio being a ratio of a height to a width of ...

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Номер записи: 12
25-01-2018 дата публикации

SEMICONDUCTOR DEVICE

Номер: US20180025998A1
Автор: KARIYAZAKI Shuuichi
Принадлежит:

A semiconductor device with enhanced performance. The semiconductor device has a high speed transmission path which includes a first coupling part to couple a semiconductor chip and an interposer electrically, a second coupling part to couple the interposer and a wiring substrate, and an external terminal formed on the bottom surface of the wiring substrate. The high speed transmission path includes a first transmission part located in the interposer to couple the first and second coupling parts electrically and a second transmission part located in the wiring substrate to couple the second coupling part and the external terminal electrically. The high speed transmission path is coupled with a correction circuit in which one edge is coupled with a branching part located midway in the second transmission part and the other edge is coupled with a capacitative element, and the capacitative element is formed in the interposer. 1. A semiconductor device comprising:a first substrate having a first front surface and a first back surface opposite to the first front surface;a second substrate having a second front surface and a second back surface opposite to the second front surface and being mounted over the first substrate with the first front surface of the first substrate facing the second back surface; anda first semiconductor component mounted over the second front surface of the second substrate and coupled with a first signal transmission path,the first signal transmission path comprising:a first coupling part to couple the first semiconductor component and the second substrate electrically;a second coupling part to couple the second substrate and the first substrate;a first external terminal formed on the first back surface of the first substrate;a first transmission part located in the second substrate to couple the first coupling part and the second coupling part electrically; anda second transmission part located in the first substrate to couple the second ...

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Номер записи: 13
28-01-2021 дата публикации

SEMICONDUCTOR DEVICE

Номер: US20210028132A1
Автор: HIRAYAMA Masahiro
Принадлежит: SUMITOMO ELECTRIC DEVICE INNOVATIONS, INC.

A 2nd signal line has impedance lower than impedance of a 1st signal line. A capacitor includes a 1st extension part and a 2nd extension part, a 1st ground part and a 2nd ground part. The 1st extension part and the 2nd extension part are connected to a 2nd signal line and are on an insulation substrate to extend along a longitudinal direction of the 2nd signal line. The 1st ground part and the 2nd ground part are at least a part of a ground pattern, and are between the 1st extension part and the 2nd extension part and the 2nd signal line, and between the 1st extension part and the 2nd extension part and an end part of the insulation substrate, to be electrically coupled with the 1st extension part and the 2nd extension part. 1. A semiconductor device comprising:an insulation substrate provided with a ground pattern having a reference potential;a semiconductor element provided on the insulation substrate;an input terminal provided on the insulation substrate and to which an electric signal to be supplied to the semiconductor element is input;a 1st signal line electrically connected between the semiconductor element and the input terminal, and provided on the insulation substrate;a 2nd signal line electrically connected between the 1st signal line and the input terminal, and provided on the insulation substrate; anda capacitor connected to the 2nd signal line and provided on the insulation substrate,wherein the 2nd signal line has impedance lower than impedance of the 1st signal line, a 1st metal pattern provided on the insulation substrate so as to connect to the 2nd signal line and extend along a longitudinal direction of the 2nd signal line, and', 'a 2nd metal pattern which is at least a part of the ground pattern, and is provided between the 1st metal pattern and the 2nd signal line and between the 1st metal pattern and an end part of the insulation substrate, to be electrically coupled with the 1st metal pattern., 'wherein the capacitor includes'}2. The ...

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Номер записи: 14
31-01-2019 дата публикации

POWER FET WITH A RESONANT TRANSISTOR GATE

Номер: US20190035781A1
Автор: de Rochemont L. Pierre
Принадлежит:

A semiconductor FET provides a resonant gate and source and drain electrodes, wherein the resonant gate is electromagnetically resonant at one or more predetermined frequencies. 1. A semiconductor FET , comprising a resonant gate and source and drain electrodes , wherein the resonant gate is electromagnetically resonant at one or more predetermined frequencies.2. The FET of claim 1 , wherein the resonant gate includes integrally constructed reactive components connected in series or parallel with resonant gate segments.3. The FET of claim 2 , wherein the reactive components include ceramic dielectric material.4. The FET of claim 3 , wherein the dielectric material has dielectric properties that vary ≤±1% over temperatures in the range of −40° C. to +120° C.5. The FET of claim 1 , further comprising a plurality of embedded capacitive circuit elements electrically connected in series with one or more resonant gate segments to form a lumped capacitance that reduces overall input capacitance of the resonant gate.6. The FET of claim 1 , wherein the resonant gate has adjacently located segments which reactively couple to each other.7. The FET of claim 6 , further comprising dielectric material integrally constructed to affect the reactive coupling between adjacently located segments of the resonant gate.8. The FET of claim 1 , wherein the resonant gate forms an elongated resonant transmission line.9. The FET of claim 8 , further comprising reactive and resistive components integrally constructed within the resonant gate to form the elongated resonant transmission line in combination with segments of the resonant gate claim 8 , which elongated transmission line is resonant at one or more predetermined frequencies.10. The FET of claim 9 , wherein the resistive component is located to terminate the resonant transmission line.11. The FET of claim 9 , wherein one or more resistive components within the resonant gate are adapted to control bandwidth of the resonant gate.12. The ...

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Номер записи: 15
17-02-2022 дата публикации

Passive device packaging structure embedded in glass medium and method for manufacturing the same

Номер: US20220053644A1
Автор: Benxia Huang, LEI FENG, Xianming Chen, Yejie Hong
Принадлежит: Zhuhai Access Semiconductor Co Ltd

A passive device packaging structure embedded in a glass medium according to an embodiment of the present disclosures includes a glass substrate and at least one capacitor embedded in the glass substrate. The capacitor includes an upper electrode, a dielectric layer, and a lower electrode. The glass substrate is provided on its upper surface with a cavity, the dielectric layer covers a surface of the cavity and has an area larger than that of the cavity. The upper electrode is provided on the dielectric layer. The dielectric layer and the lower electrode are connected by a metal via pillar passing through the glass substrate.

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Номер записи: 16
08-02-2018 дата публикации

Power amplifier, semiconductor integrated circuit, and method of controlling the power amplifier

Номер: US20180041177A1
Автор: Ikuo Soga, Masato Nishimori, Masayuki Hosoda, Tadahiro Imada, Tatsuya Hirose
Принадлежит: Fujitsu Ltd

A power amplifier includes a main amplifier, an auxiliary amplifier, and a control circuit. The main amplifier is configured to amplify input power, and the auxiliary amplifier is configured to amplify the input power when the input power exceeds a certain level. The control circuit, which is provided between a source of the main amplifier and a ground, is configured to control a source potential of the main amplifier so as to increase the source potential when the input power reaches at least a certain value.

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Номер записи: 17
07-02-2019 дата публикации

SINGLE CLOCK SOURCE FOR A MULTIPLE DIE PACKAGE

Номер: US20190041895A1
Автор: Kumashikar Mahesh, Miao Yingyu, Pasdast Gerald, WANG Peipei
Принадлежит:

A processing device includes a package, a plurality of dies disposed on the package, where each die comprises a clock receiver, and a single common clock source to generate a common clock signal. The processing device also includes a clock distribution circuitry coupled to the single common clock source. The clock distribution circuitry distributes the common clock signal from the single common clock source to each of the plurality of dies individually. The clock distribution circuitry includes a first group of terminated transmission lines. The first group of terminated transmission lines includes a first terminated transmission line, a second terminated transmission line, and a first termination resistor coupled between the first terminated transmission line and the second terminated transmission line. The first terminated transmission line and the second terminated transmission line receive the common clock signal from the single common clock source. 1. A processing device comprising:a package;a plurality of dies disposed on the package, wherein each die comprises a clock receiver;a single common clock source to generate a common clock signal; and a first terminated transmission line; and', 'a second terminated transmission line, wherein the first terminated transmission line and the second terminated transmission line receive the common clock signal from the single common clock source., 'a first group of terminated transmission lines, comprising, 'a clock distribution circuitry coupled to the single common clock source, the clock distribution circuitry to distribute the common clock signal from the single common clock source to each of the plurality of dies individually, wherein the clock distribution circuitry comprises2. The processing device of claim 1 , wherein the clock distribution circuitry further comprises: a third terminated transmission line;', 'a fourth terminated transmission line, wherein the third terminated transmission line and the fourth ...

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Номер записи: 18
15-02-2018 дата публикации

PACKAGE COMPRISING SWITCHES AND FILTERS

Номер: US20180047673A1
Автор: Fanelli Steve, Gu Shiqun, Masaracioglu Husnu Ahmet, Zuo Chengjie
Принадлежит:

A package includes a redistribution portion, a first portion, and a second portion. The first portion is coupled to the redistribution portion. The first portion includes a first switch comprising a plurality of switch interconnects, and a first encapsulation layer that at least partially encapsulates the first switch. The second portion is coupled to the first portion. The second portion includes a first plurality of filters. Each filter includes a plurality of filter interconnects. The second portion also includes a second encapsulation layer that at least partially encapsulates the first plurality of filters. The first portion includes a second switch positioned next to the first switch, where the first encapsulation layer at least partially encapsulates the second switch. The second portion includes a second plurality of filters positioned next to the first plurality of filters, where the second encapsulation layer at least partially encapsulates the second plurality of filters. 1. A package comprising:a redistribution portion; a first switch comprising a plurality of switch interconnects; and', 'a first encapsulation layer at least partially encapsulating the first switch; and, 'a first portion coupled to the redistribution portion, the first portion comprising a plurality of first filters, each first filter comprising a plurality of first filter interconnects; and', 'a second encapsulation layer at least partially encapsulating the plurality of first filters., 'a second portion coupled to the first portion, the second portion comprising2. The package of claim 1 , wherein the first portion further comprises a second switch positioned next to the first switch claim 1 , wherein the first encapsulation layer at least partially encapsulates the second switch.3. The package of claim 1 , wherein the second portion farther comprises a plurality of second filters positioned next to the plurality of first filters claim 1 , wherein the second encapsulation layer at least ...

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Номер записи: 19
25-02-2016 дата публикации

MULTILAYER WIRING BOARD

Номер: US20160057862A1
Автор: KITAJIMA Hiromichi
Принадлежит:

A method reduces an area of a mounting electrode provided on a first surface of a multilayer body and connected to a specific component is reduced and decreases a pitch between mounting electrodes. A plating film is formed on the mounting electrodes with the reduced area. The mounting electrodes for connection to specific components are defined by first end surfaces of first via conductors, and hence, the areas of the mounting electrodes are significantly reduced, and the pitch between the mounting electrodes is significantly decreased. Also, the mounting electrodes defined by the first end surfaces of the first via conductors are connected to plane electrodes at end surfaces of second via conductors exposed from a surface of the multilayer body with internal wiring electrodes interposed therebetween. Thus, a plating film is able to be reliably provided on the mounting electrodes. 1. A multilayer wiring substrate comprising:a multilayer body including a laminate of a plurality of insulating layers;a first via conductor provided in the multilayer body, including a first end surface exposed from a first surface of the multilayer body, and defining a mounting electrode for connection with a specific component;a second via conductor provided in the multilayer body, and including first and second end surfaces, at least one of the first and second end surfaces being exposed from a surface of the multilayer body;a plane electrode located on the at least one of the first and second end surfaces of the second via conductor exposed from the surface of the multilayer body; andan internal wiring electrode provided in the multilayer body; whereinthe first via conductor is connected to the second via conductor with the internal wiring electrode interposed therebetween.2. The multilayer wiring substrate according to claim 1 , whereina plurality of mounting electrodes defined by the first end surface of a plurality of first via conductors are provided in a mounting region of the ...

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Номер записи: 20
05-03-2015 дата публикации

METAL TRENCH DE-COUPLING CAPACITOR STRUCTURE AND METHOD FOR FORMING THE SAME

Номер: US20150061075A1
Автор: Yeh Ta-Hsun
Принадлежит:

A metal trench de-coupling capacitor structure includes a vertical trench disposed in a substrate, an insulating layer deposited on the sidewall of the vertical trench, an inter-layer dielectric layer covering the substrate and the insulating layer, and a metal layer penetrating the interlayer dielectric layer to fill up the vertical trench. The metal layer is electrically connected to a power source. 1. A metal trench de-coupling capacitor structure , comprising:a substrate which is grounded;a vertical trench disposed in said substrate;an insulating layer disposed on the sidewall of said vertical trench; andan inter-metal connection layer, disposed on said substrate and filling up said vertical trench, wherein said inter-metal connection layer is electrically connected to a power.2. The metal trench de-coupling capacitor structure of claim 1 , wherein said substrate further comprises:at least one element region adjacent to said vertical trench; anda shallow trench isolation, to surround at least one said element region.3. The metal trench de-coupling capacitor structure of claim 2 , wherein at least one said element region comprises a digital circuit element region claim 2 , an analog circuit element region claim 2 , a dummy element region and a radio frequency circuit element region.4. The metal trench de-coupling capacitor structure of claim 3 , wherein said vertical trench is deeper than at least one said element region.5. The metal trench de-coupling capacitor structure of claim 3 , wherein said inter-metal connection layer decreases a power noise coming from at least one said element region by means of de-coupling.6. The metal trench de-coupling capacitor structure of claim 3 , wherein said vertical trench is disposed in said dummy element region claim 3 , and surrounded by said shallow trench isolation.7. The metal trench de-coupling capacitor structure of claim 2 , wherein said vertical trench penetrates said shallow trench isolation and surrounded by said ...

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Номер записи: 21
07-03-2019 дата публикации

Orthogonal transistor layouts

Номер: US20190074300A1
Автор: Aniruddha B. Joshi, David Scott Whitefield, Maureen Rosenberg BRONGO, Tzung-Yin LEE
Принадлежит: Skyworks Solutions Inc

A transistor device includes a plurality of drain fingers that are elongate in a first dimension, a plurality of source fingers that are elongate in the first dimension and interleaved with the plurality of drain fingers, one or more drain contact bars extending over a first set of the plurality of drain fingers and a first set of the plurality of source fingers in a second dimension that is orthogonal to the first dimension, and one or more source contact bars extending over a second set of the plurality of drain fingers and a second set of the plurality of source fingers in the second dimension.

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Номер записи: 22
05-03-2020 дата публикации

RADIO FREQUENCY INTERCONNECTIONS FOR OSCILLATORY NEURAL NETWORKS

Номер: US20200074268A1
Автор: Manipatruni Sasikanth, Nikonov Dmitri, Young Ian
Принадлежит: Intel Corporation

Techniques are provided for radio frequency interconnections between oscillators and transmission lines for oscillatory neural networks (ONNs). An ONN gate implementing the techniques according to an embodiment includes a transmission line, a first oscillator circuit tuned to a first frequency based on a first tuning voltage associated with a first synapse weight, and a first capacitive coupler to couple the first oscillator circuit to the transmission line to generate an oscillating signal in the transmission line. The ONN gate further includes a second oscillator circuit tuned to a second frequency based on a second tuning voltage associated with a second synapse weight, and a second capacitive coupler to couple the second oscillator circuit to the transmission line to adjust the oscillating signal in the transmission line such that the amplitude of the adjusted oscillating signal is associated with a degree of match between the first frequency and the second frequency. 1. An oscillatory neural network (ONN) gate comprising:a transmission line;a first oscillator circuit tuned to a first frequency based on a first tuning voltage, the first tuning voltage associated with a first synapse weight;a first capacitive coupler to couple the first oscillator circuit to the transmission line to generate an oscillating signal in the transmission line;a second oscillator circuit tuned to a second frequency based on a second tuning voltage, the second tuning voltage associated with a second synapse weight; anda second capacitive coupler to couple the second oscillator circuit to the transmission line to adjust the oscillating signal in the transmission line, wherein an amplitude of the adjusted oscillating signal is associated with a degree of match between the first frequency and the second frequency.2. The ONN gate of claim 1 , wherein the first oscillator circuit and the second oscillator circuit are ring oscillators.3. The ONN gate of claim 2 , wherein the ring oscillators ...

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Номер записи: 23
31-03-2022 дата публикации

HIGH PERFORMANCE INTEGRATED RF PASSIVES USING DUAL LITHOGRAPHY PROCESS

Номер: US20220102261A1
Автор: Aleksov Aleksandar, Bharath Krishna, EID Feras, Elsherbini Adel A., Jiao Meizi, Kamgaing Telesphor, Lambert William J., Manusharow Mathew J., NAD Suddhasattwa, RAWLINGS Brandon M., Sankman Robert L., Soto Gonzalez Javier
Принадлежит:

Embodiments of the invention include an electrical package and methods of forming the package. In one embodiment, a transformer may be formed in the electrical package. The transformer may include a first conductive loop that is formed over a first dielectric layer. A thin dielectric spacer material may be used to separate the first conductive loop from a second conductive loop that is formed in the package. Additional embodiments of the invention include forming a capacitor formed in the electrical package. For example, the capacitor may include a first capacitor plate that is formed over a first dielectric layer. A thin dielectric spacer material may be used to separate the first capacitor plate form a second capacitor plate that is formed in the package. The thin dielectric spacer material in the transformer and capacitor allow for increased coupling factors and capacitance density in electrical components. 1. A capacitor in an electrical package comprising:a first dielectric layer;a first capacitor plate over a surface of the first dielectric layer;a dielectric spacer over a surface of the first capacitor plate; anda second capacitor plate separated from the first capacitor plate by the dielectric spacer layer.2. The capacitor of claim 1 , wherein the first and second capacitor plates are in a single routing layer of the package.3. The capacitor of claim 2 , wherein the dielectric spacer is less than 10 μm thick.4. The capacitor of claim 2 , wherein the first and second capacitor plates include interdigitated square meander extensions.5. The capacitor plate of claim 4 , wherein the extensions are in three-dimensions.6. A method for forming a capacitor in an electrical package claim 4 , comprising:forming a first capacitor plate over a first dielectric layer;forming a dielectric spacer layer over the first capacitor plate; andforming a second capacitor plate in direct by with the dielectric spacer layer, wherein the first capacitor plate is spaced apart from the ...

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Номер записи: 24
12-03-2020 дата публикации

Multiple Band Multiple Mode Transceiver Front End Flip-Chip Architecture and Circuitry with Integrated Power Amplifiers

Номер: US20200083915A1
Автор: Gorbachov Oleksandr, Zhang Lisette L.
Принадлежит:

An integrated circuit architecture and circuitry is defined by a die structure with a plurality of exposed conductive pads arranged in a grid of rows and columns. The die structure has a first operating frequency region with a first transmit and receive chain, and a second operating frequency region with a second transmit chain and a second receive chain. There is a shared region of the die structure defined by an overlapping segment of the first operating frequency region and the second operating frequency region with a shared power supply input conductive pad connected to the first transmit chain, the second transmit chain, the first receive chain, and the second receive chain, and a shared power detection output conductive pad connected to the first transmit chain and the second transmit chain. 120-. (canceled)21. An integrated circuit architecture defined by a die structure , the integrated circuit architecture comprising:a first operating frequency region corresponding to a physical area on the die structure including a first transmit chain and a first receive chain;a second operating frequency region corresponding to a physical area on the die structure including a second transmit chain and a second receive chain; anda shared region of the die structure defined by an overlapping segment of the first operating frequency region and the second operating frequency region, the shared region including a control input conductive pad connected to both the first transmit chain and the second transmit chain.22. The integrated circuit architecture of wherein the first transmit chain includes at least one first operating frequency power amplifier.23. The integrated circuit architecture of wherein the second transmit chain includes at least one second operating frequency power amplifier.24. The integrated circuit architecture of wherein the first receive chain includes at least one first operating frequency low noise amplifier.25. The integrated circuit architecture of ...

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Номер записи: 25
19-03-2020 дата публикации

PACKAGE STRUCTURE OF A FOLDING MAGNETIC COUPLING ISOLATOR, LEADFRAME COMPONENT, AND LEADFRAME STRUCTURE

Номер: US20200091049A1
Автор: WANG You-Fa
Принадлежит:

The present invention provides a leadframe component and a package structure. The leadframe component includes a first leadframe and a second leadframe. The first leadframe includes a first chip-mounting portion for carrying a first chip, a first coil portion, a plurality of first pins and a plurality of first floated pins. The second leadframe includes a second chip-mounting portion for carrying a second chip, a second coil portion, a plurality of second pins and a plurality of second floated pins. The first leadframe is disposed above or under the second leadframe for aligning the first coil portion with the second coil portion. 1. A leadframe component , comprising:a first leadframe including a first chip-mounting portion for carrying a first chip, a first coil portion, a plurality of first pins and a plurality of first floated pins; anda second leadframe including a second chip-mounting portion for carrying a second chip, a second coil portion, a plurality of second pins and a plurality of second floated pins;wherein the first leadframe is disposed above or under the second leadframe for aligning the first coil portion with the second coil portion.2. The leadframe component according to claim 1 , wherein the first coil portion and the second coil portion have a height difference of from 100 to 500 micrometers therebetween.3. The leadframe component according to claim 1 , wherein one of the first leadframe and the second leadframe comprises at least one bending portion.4. The leadframe component according to claim 3 , wherein the at least one bending portion is formed between the first pin portion and the first coil portion claim 3 , and between the first pin portion and the first chip-mounting portion.5. The leadframe component according to claim 4 , wherein the other one of the first leadframe and the second leadframe comprises at least another one bending portion formed between the second pin portion and the second coil portion claim 4 , and between the second ...

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Номер записи: 26
16-04-2015 дата публикации

SEMICONDUCTOR DEVICE INCLUDING DECOUPLING CAPACITOR AND METHOD OF FORMING THE SAME

Номер: US20150102395A1
Автор: MOON Kwang-Jin, Park Byung-lyul, PARK Jae-Hwa
Принадлежит:

An integrated circuit device includes a semiconductor substrate having first and second semiconductor regions therein, a gate trench in the first semiconductor region and a gate electrode in the gate trench. The gate electrode has an upper surface below a surface of the semiconductor substrate. A semiconductor well region is provided in the second semiconductor region. A capacitor trench extends in the semiconductor well region and an upper capacitor electrode extends in the capacitor trench. An electrical interconnect (e.g., conductive plug) is provided, which is electrically connected to the upper capacitor electrode at an interface therebetween. This interface has an upper surface below the surface of the semiconductor substrate. 1. An integrated circuit device , comprising:a semiconductor substrate having first and second semiconductor regions therein;a gate trench in the first semiconductor region and a gate electrode in the gate trench, said gate electrode having an upper surface below a surface of the semiconductor substrate;a semiconductor well region in the second semiconductor region;a capacitor trench in the semiconductor well region and an upper capacitor electrode in the capacitor trench; andan electrical interconnect electrically connected to the upper capacitor electrode at an interface therebetween, said interface having an upper surface below the surface of the semiconductor substrate.2. The device of claim 1 , wherein a lowermost portion of the gate electrode in the gate trench and a lowermost portion of the upper capacitor electrode in the capacitor trench have equivalent cross-sections when viewed in a first direction parallel to the surface of the semiconductor substrate.3. The device of claim 1 , wherein a depth of the gate trench in the semiconductor substrate is equivalent to a depth of the capacitor trench in the semiconductor substrate.4. The device of claim 1 , wherein the gate electrode is separated from a sidewall and bottom of the gate ...

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Номер записи: 27
19-03-2020 дата публикации

MODULE WITH HIGH PEAK BANDWIDTH I/O CHANNELS

Номер: US20200092014A1
Автор: de Rochemont L. Pierre
Принадлежит:

A high peak bandwidth I/O channel embedded within a multilayer surface interface that forms the bus circuitry electrically interfacing the output or input port on a first semiconductor die with the input or output port on a second semiconductor die. 2. The hybrid computing module of claim 1 , wherein active switching elements embedded within an active semiconductor surface of a semiconductor chip earner claim 1 , a semiconductor die mounted on the semiconductor chip carrier claim 1 , or semiconductor embedded within the stacked assembly of semiconductor chips claim 1 , form an electrical interface with a signal control plane in the multilayer surface interface and the passive network filtering circuit functions as a clock or data recovery circuit.4. The resonant gate transistor of claim 3 , wherein inductors claim 3 , capacitors claim 3 , and resistors embedded within the resonant gate transistor's gate electrode function as band tuning elements to tailor maximal amplification of the attenuated signal at a resonant frequency or over desired spectral frequency bands.5. The high-peak bandwidth I/O channel of claim 3 , wherein the high-peak bandwidth I/O channel additionally comprises conductive means configured as a differential pair and active switching elements that configure the resonant gate transistor to operate as a bi-directional amplification stage.6. The hybrid computing module of claim 1 , wherein the high peak bandwidth I/O channels are distributed across several data signal planes of the multilayer surface interface and comprise ground walls and ground planes claim 1 , and have interconnection density exceeding 200 IO/mm/layer.8. The high peak bandwidth I/O channel of claim 7 , wherein the multilayer surface interface is formed on a dielectric substrate or semiconducting die claim 7 , a semiconductor carrier claim 7 , or an interposer circuit embedded within a stacked assembly of semiconductor chips.9. The high-peak bandwidth I/O channel of claim 8 , ...

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Номер записи: 28
16-04-2015 дата публикации

Noise Decoupling Structure with Through-Substrate Vias

Номер: US20150104925A1
Автор: CHEN Chia-Chung, JOU Chewn-PU, LIU Sally
Принадлежит:

A device includes a substrate having a front surface and a back surface; an integrated circuit device at the front surface of the substrate; and a metal plate on the back surface of the substrate, wherein the metal plate overlaps substantially an entirety of the integrated circuit device. A guard ring extends into the substrate and encircles the integrated circuit device. The guard ring is formed of a conductive material. A through substrate via (TSV) penetrates through the substrate and electrically couples to the metal plate. 1. A method comprising:providing a substrate, the substrate having a first side and a second side;forming a first guard ring around a circuit region on the first side of the substrate, the first guard ring comprising a doped region of the substrate, the first guard ring having a first conductivity type, the circuit region having a second conductivity type;forming an isolation trench around the circuit region on the first side of the substrate;forming through vias, the through vias extending through the isolation trench to the second side of the substrate; andforming a conductive layer over the second side of the substrate, the conductive layer being electrically coupled to the through vias, the conductive layer being over substantially an entirety of the second side of the substrate opposite of the circuit region.2. The method of claim 1 , wherein the first guard ring is interposed between the through vias and the circuit region.3. The method of claim 1 , further comprising forming a second guard ring encircling the first guard ring claim 1 , wherein the through vias are laterally between the first guard ring and the second guard ring claim 1 , the second guard ring having the first conductivity type.4. The method of claim 3 , further comprising forming a well region claim 3 , wherein the first guard ring and the second guard ring are separated by the well region claim 3 , the well region having the second conductivity type.5. The method of ...

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Номер записи: 29
12-05-2022 дата публикации

INTEGRATED CIRCUIT, FRONT-END MODULE, AND COMMUNICATION APPARATUS

Номер: US20220148986A1
Автор: NISHIKAWA Hiroshi
Принадлежит:

An integrated circuit (IC) includes a first switch, a second switch, an amplifier electrically connected between the first switch and the second switch, and a base. The first switch, the second switch, and the amplifier are provided on the base. In a top view of the base, the amplifier is disposed between the first switch and the second switch. 1. An integrated circuit (IC) comprising:a first switch;a second switch;an amplifier electrically connected between the first switch and the second switch; anda base; whereinthe first switch, the second switch, and the amplifier are provided on the base; andin a top view of the base, the amplifier is disposed between the first switch and the second switch.2. The IC according to claim 1 , whereinin the top view of the base, the first switch and the amplifier are disposed next to each other and the amplifier and the second switch are disposed next to each other.3. The IC according to claim 2 , whereinin the top view of the base, the first switch, the amplifier, and the second switch are disposed on a straight line.4. The IC according to claim 1 , whereinan input terminal of the first switch is connected to an antenna; andthe amplifier is a low-noise amplifier.5. The IC according to claim 2 , whereinan input terminal of the first switch is connected to an antenna; andthe amplifier is a low-noise amplifier.6. The IC according to claim 3 , whereinan input terminal of the first switch is connected to an antenna; andthe amplifier is a low-noise amplifier.7. The IC according to claim 1 , further comprising:a third switch provided on the base and electrically connected between the first switch and the amplifier; whereinin the top view of the base, the third switch is disposed between the first switch and the amplifier.8. The IC according to claim 7 , whereinin the top view of the base, the first switch and the third switch are disposed next to each other, the third switch and the amplifier are disposed next to each other, and the ...

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Номер записи: 30
02-04-2020 дата публикации

CIRCUIT SYSTEM HAVING COMPACT DECOUPLING STRUCTURE

Номер: US20200105688A1
Автор: FUJIISHI Yoshitaka, HARAGUCHI Masaru
Принадлежит:

A circuit system having compact decoupling structure, including: a mother board; at least one circuit unit, each having a substrate, a logic-circuit die, a plurality of first metal contacts, and a plurality of second metal contacts, the substrate having a first surface and a second surface, the first metal contacts being formed on the first surface and soldered onto the mother board, the second metal contacts being formed on the logic-circuit die and soldered onto the second surface to form flip-chip pillars, and the flip-chip pillars determining a height of a gap between the die and the substrate; and at least one decoupling unit for providing an AC signals decoupling function for the at least one circuit unit; wherein each of the at least one decoupling unit is placed in the gap of one said circuit unit and includes a mother die and at least one stack-type integrated-passive-device die. 1. A circuit system having compact decoupling structure , including:a mother board;at least one circuit unit, each having a substrate, a logic-circuit die, a plurality of first metal contacts, and a plurality of second metal contacts, wherein the substrate has a first surface and a second surface opposing the first surface, the first metal contacts are formed on the first surface and soldered onto the mother board, the second metal contacts are formed on the logic-circuit die and soldered onto the second surface of the substrate to form flip-chip pillars, and the flip-chip pillars determine a height of a gap between the logic-circuit die and the substrate; andat least one decoupling unit for providing an AC signals decoupling function for the at least one circuit unit;wherein, each of the at least one decoupling unit is placed in the gap of one said circuit unit and includes a mother die, at least one stack-type integrated-passive-device die, and a plurality of third metal contacts, the third metal contacts being formed on the mother die and soldered onto the logic-circuit die, and ...

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Номер записи: 31
24-07-2014 дата публикации

Semiconductor package and method of manufacturing the same

Номер: US20140203395A1
Автор: Chien-Cheng Lin, Chih-Hsien Chiu, Heng-Cheng Chu, Hsin-Lung Chung, Tsung-Hsien Tsai, Yude Chu
Принадлежит: Siliconware Precision Industries Co Ltd

A semiconductor package and a method of manufacturing the same are provided. The semiconductor package includes: a substrate having a plurality of conductive lands and a plurality of bonding pads surrounding the conductive lands formed on a surface thereof; a plurality of passive devices mounted on the conductive lands; an insulation layer formed on the surface and having a portion of the passive devices embedded therein; a semiconductor chip mounted on a top surface of the insulation layer; a plurality of bonding wires electrically connecting the semiconductor chip and the bonding pads; an encapsulant formed on the surface of the substrate to encapsulate the insulation layer, the bonding wires and the semiconductor chip, wherein a region of the semiconductor chip projected onto the substrate covers a portion of an outermost one of the passive devices. Therefore, the mounting density of the passive devices is improved.

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Номер записи: 32
14-05-2015 дата публикации

Tunable guard ring for improved circuit isolation

Номер: US20150130552A1
Автор: Lan Nan, Maulin Pareshbhai Bhagat, Thomas Andrew Myers, ZHANG Jin
Принадлежит: Qualcomm Inc

A tunable guard ring for improved circuit isolation is disclosed. In an exemplary embodiment, an apparatus includes a closed loop guard ring formed on an integrated circuit and magnetically coupled by a selected coupling factor to a first inductor formed on the integrated circuit. The apparatus also includes a tunable capacitor forming a portion of the closed loop guard ring and configured to reduce magnetic field coupling from the first inductor to a second inductor.

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Номер записи: 33
25-04-2019 дата публикации

PACKAGE STRUCTURE OF FOLDING MAGNETIC COUPLING ISOLATOR AND LEADFRAME COMPONENT AND MANUFACTURING METHOD THEREOF

Номер: US20190122971A1
Автор: WANG You-Fa
Принадлежит:

The instant disclosure provides a method for manufacturing a package structure of a folding magnetic coupling isolator. The method includes providing a leadframe structure including a frame body and a first and a second leadframes connected to the frame body, the first and second leadframes including first and second chip-mounting portions, first and second coil portions, and a plurality of first and second pins and floated pins; disposing the first and second chips on the first and second chip-mounting portions and establishing electrical connections between the first and second chips and the first and second pins; and rotating the first leadframe relative to the frame body and moving the first leadframe to a position above or under the second leadframe, thereby electrically isolating the first leadframe from the second leadframe. The first coil portion and the second coil portion are aligned with and magnetically coupled to each other. 1. A method for manufacturing a package structure of folding magnetic coupling isolator comprising:providing a leadframe structure including a frame body, a first leadframe connected to the frame body and a second leadframe connected to the frame body, wherein the first leadframe includes a first chip-mounting portion, at least a first coil portion, a plurality of first pins and a plurality of floated pins, and the second leadframe includes a second chip-mounting portion, at least a second coil portion, a plurality of second pins and a plurality of second floated pins;respectively disposing at least a first chip and at least a second chip on the first chip-mounting portion and the second chip-mounting portion and establishing electrical connections between the first chip and the first pin portion and between the second chip and the second pin portion;rotating the first leadframe relative to the frame body for moving the first leadframe to a position above or under the second leadframe, thereby generating a height difference between ...

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Номер записи: 34
11-05-2017 дата публикации

POWER INTEGRATED MODULE

Номер: US20170133332A1
Автор: Chen Yan, LIANG Le, XIN Xiaoni, ZENG Jianhong
Принадлежит: DELTA ELECTRONICS (SHANGHAI) CO., LTD

A power integrated module, including at least one first bridge formed in a chip, wherein the first bridge includes: a first upper bridge switch, formed by a plurality of first sub switches formed in the chip connected in parallel, and including a first, a second and a control end; a first lower bridge switch, formed by a plurality of second sub switches formed in the chip connected in parallel, and including a first, a second and a control end; a first electrode, connected to the first end of the first upper bridge switch; a second electrode, connected to the second end of the first lower bridge switch; and a third electrode, connected to the second end of the first upper bridge switch and the first end of the first lower bridge switch, wherein the first, the second and the third electrode are bar-type electrodes arranged side by side. 1. A power integrated module , comprising at least one first bridge formed in a chip , a first bus terminal , a second bus terminal and a third bus terminal , wherein the first bridge comprises:a first upper bridge switch, formed by a plurality of first sub switches formed in the chip connected in parallel, and comprising a first end, a second end and a control end;a first lower bridge switch, formed by a plurality of second sub switches formed in the chip connected in parallel, and comprising a first end, a second end and a control end;a first electrode, electrically connected to the first end of the first upper bridge switch;a second electrode, electrically connected to the second end of the first lower bridge switch; anda third electrode, electrically connected to the second end of the first upper bridge switch and the first end of the first lower bridge switch,wherein the first bus terminal is electrically connected to the first electrode, the second bus terminal is electrically connected to the second electrode, and the third bus terminal is electrically connected to the third electrode,the first electrode, the second electrode ...

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Номер записи: 35
02-05-2019 дата публикации

SEMICONDUCTOR DEVICE, SEMICONDUCTOR DEVICE MANUFACTURING METHOD, AND ELECTRONIC DEVICE

Номер: US20190131258A1
Автор: SAKAI Kiyohisa
Принадлежит:

To enable a semiconductor module that connects a wiring substrate and a semiconductor chip mounted on the wiring substrate via a circuit element and that has reduced a wiring length to improve transmission quality of signals or the like so as to achieve miniaturization of the semiconductor module. A semiconductor device including: a wiring substrate; a semiconductor chip disposed on an upper surface of the wiring substrate so as to direct a bottom surface of the chip to face the upper surface; a resin portion formed between the wiring substrate and the semiconductor chip; and a circuit element embedded in the resin portion, in which the circuit element includes: a first terminal connected to wiring formed on the upper surface of the wiring substrate; and a second terminal connected to a bump provided on a lower surface of the semiconductor chip, and the circuit element is embedded in the resin portion with the first terminal facing the upper surface of the wiring substrate and the second terminal facing the lower surface of the semiconductor chip. 1. A semiconductor device comprising:a wiring substrate;a semiconductor chip disposed on an upper surface of the wiring substrate so as to direct a bottom surface of the chip to face the upper surface;a resin portion formed between the wiring substrate and the semiconductor chip; anda circuit element embedded in the resin portion,wherein the circuit element includes: a first terminal connected to wiring formed on the upper surface of the wiring substrate; and a second terminal connected to a bump provided on a lower surface of the semiconductor chip, and the circuit element is embedded in the resin portion with the first terminal facing the upper surface of the wiring substrate and the second terminal facing the lower surface of the semiconductor chip.2. The semiconductor device according to claim 1 , wherein the second terminal is connected to the bump via redistribution wiring formed along an upper surface of the resin ...

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Номер записи: 36
30-04-2020 дата публикации

Additive deposition low temperature curable magnetic interconnecting layer for power components integration

Номер: US20200135381A1
Автор: Anindya Poddar, Ashok Prabhu, Luu Thanh Nguyen, Yi Yan
Принадлежит: Texas Instruments Inc

Apparatus to form a transformer, an inductor, a capacitor or other passive electronic component, with patterned conductive features in a lamination structure, and one or more ferrite sheets or other magnetic core structures attached to the lamination structure via one or more inkjet printed magnetic adhesive layers that join the magnetic core structure or structures to the lamination structure.

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Номер записи: 37
24-05-2018 дата публикации

RF Power Package Having Planar Tuning Lines

Номер: US20180145043A1
Автор: Simcoe Michael
Принадлежит:

An RF power package includes a substrate having a metallized part and an insulating part, an RF power transistor die embedded in or attached to the substrate, the RF power transistor die having a die input terminal, a die output terminal, an input impedance and an output impedance, a package input terminal formed in the metallized part or attached to the insulating part of the substrate, a package output terminal formed in the metallized part or attached to the insulating part of the substrate, and a first plurality of planar tuning lines formed in the metallized part of the substrate and electrically connecting the die output terminal to the package output terminal. The first plurality of planar tuning lines is shaped so as to transform the output impedance at the die output terminal to a higher target level at the package output terminal. 1. An RF power package , comprising:a substrate having a metallized part and an insulating part;an RF power transistor die embedded in or attached to the substrate, the RF power transistor die having a die input terminal, a die output terminal, an input impedance and an output impedance;a package input terminal formed in the metallized part or attached to the insulating part of the substrate;a package output terminal formed in the metallized part or attached to the insulating part of the substrate; anda first plurality of planar tuning lines formed in the metallized part of the substrate and electrically connecting the die output terminal to the package output terminal,wherein the first plurality of planar tuning lines is shaped so as to transform the output impedance at the die output terminal to a higher target level at the package output terminal.2. The RF power package of claim 1 , wherein the substrate comprises a ceramic body and a patterned metallization applied to the ceramic body claim 1 , and wherein the patterned metallization forms the metallized part of the substrate.3. The RF power package of claim 1 , wherein the ...

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Номер записи: 38
09-06-2016 дата публикации

Radio frequency device protected against overvoltages

Номер: US20160163659A1
Автор: Abdelali Zaid, Erwan Bruno
Принадлежит: STMicroelectronics Tours SAS

A device includes passive radio frequency components formed of portions of metal layers separated by insulating layers and crossed by vias. The insulating layers are positioned on an upper surface of an insulating substrate. Islands of a semiconductor material extend into the insulating substrate from the upper surface. Active integrated circuit components are formed in the islands.

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Номер записи: 39
15-06-2017 дата публикации

INTEGRATED CIRCUIT STRUCTURES WITH INTERPOSERS HAVING RECESSES

Номер: US20170170109A1
Автор: LEE Kyu-oh, Salama Islam A.
Принадлежит:

Disclosed herein are integrated circuit (IC) structures having interposers with recesses. For example, an IC structure may include: an interposer having a resist surface; a recess disposed in the resist surface, wherein a bottom of the recess is surface-finished; and a plurality of conductive contacts located at the resist surface. Other embodiments may be disclosed and/or claimed. 125-. (canceled)26. An integrated circuit (IC) structure , comprising:an interposer having a resist surface;a recess disposed in the resist surface, wherein a bottom of the recess is surface-finished; anda plurality of conductive contacts located at the resist surface.27. The IC structure of claim 26 , wherein the plurality of conductive contacts is a first plurality of conductive contacts claim 26 , and wherein the IC structure further comprises:an IC package having a first surface, a second surface opposite to the first surface, a second plurality of conductive contacts located at the second surface of the IC package, and a component coupled to the second surface of the IC package;wherein the second plurality of conductive contacts are electrically coupled to the first plurality of conductive contacts and the IC package is arranged so that the component extends into the recess.28. The IC structure of claim 27 , wherein the component is a capacitor having a capacitance greater than 0.5 microfarads.29. The IC structure of claim 27 , wherein the component has a height that is greater than 200 microns.30. The IC structure of claim 27 , wherein the IC package has a processing core located at the first surface of the IC package and the component is a decoupling capacitor for the processing core.31. The IC structure of claim 27 , wherein a distance between the second surface of the IC package and the resist surface is less than 250 microns.32. The IC structure of claim 27 , further comprising:a solder material in physical contact with one of the first plurality of conductive contacts and also ...

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Номер записи: 40
15-06-2017 дата публикации

Electronic device, assembly and methods of manufacturing an electronic device including a vertical trench capacitor and a vertical interconnect

Номер: US20170170131A1
Автор: BUIJSMAN Adrianus Alphonsus Jozef, Gamand Patrice, HUBERT Gerardus Tarcisius Maria, KEMMEREN Antonius Lucien Adrianus Maria, Roozeboom Freddy
Принадлежит:

A semiconductor substrate comprises both vertical interconnects and vertical capacitors with a common dielectric layer. The substrate can be suitably combined with further devices to form an assembly. The substrate can be made in etching treatments including a first step on the one side, and then a second step on the other side of the substrate. 2. A method as claimed in claim 1 , wherein the first trenches and the second trenches are etched in a single step claim 1 , said first trenches having a smaller diameter than the second trenches leading to the through-holes claim 1 , with the result that the second trenches will extend further into the substrate than the first trenches claim 1 , said trenches having inner faces.3. A method as claimed in claim 2 , characterized in that the step of applying conductive material in the second trenches comprises the steps of applying a seed layer and electroplating.4. A method as claimed in claim 2 , characterized in that a plurality of second trenches are neighbouring and mutually interconnected so as to form a single vertical interconnect.5. A method as claimed in claim 4 , wherein the electrically conductive material applied in the first and the second trenches is polysilicon.6. A method as claimed in claim 1 , wherein the step of removing material for opening the second trenches comprises the step of wet-chemical etching to form a cavity claim 1 , said cavity having a larger diameter than the second trenches.7. A method as claimed in claim 1 , wherein the second trenches are formed by wet-chemical etching from the second side of the substrate before provision of the first trenches claim 1 , said second trenches being shaped as cavities and have a larger diameter than the first trenches.8. A method as claimed in claim 7 , wherein the second trenches are opened by etching in the same step as the etching of the first trenches.9. A method as claimed in claim 7 , wherein the second trenches extend up to the first side of the ...

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Номер записи: 41
01-07-2021 дата публикации

TRANSISTOR DIE WITH OUTPUT BONDPAD AT THE INPUT SIDE OF THE DIE, AND POWER AMPLIFIERS INCLUDING SUCH DIES

Номер: US20210202408A1
Автор: Hill Darrell Glenn, HOLMES Damon G., Khalil Ibrahim, ZHU Ning
Принадлежит:

A power transistor die includes a semiconductor die with input and output die sides, and a transistor integrally formed in the semiconductor die between the input die side and the output die side, where the transistor has an input and an output (e.g., a gate and a drain, respectively). The power transistor die also includes an input bondpad and a first output bondpad integrally formed in the semiconductor die between the input die side and the transistor. The input bondpad is electrically connected to the input of the transistor. A conductive structure directly electrically connects the output of the transistor to the first output bondpad. A second output bondpad, which also may be directly electrically connected to the transistor output, may be integrally formed in the semiconductor die between the transistor and the output die side. 1. A power transistor die comprising:a semiconductor die with an input die side and an opposed output die side;a transistor integrally formed in the semiconductor die between the input die side and the output die side, wherein the transistor has an input and an output;an input bondpad integrally formed in the semiconductor die between the input die side and the transistor, wherein the input bondpad is electrically connected to the input of the transistor;a first output bondpad integrally formed in the semiconductor die between the input die side and the transistor; anda conductive structure integrally formed in the semiconductor die that directly electrically connects the output of the transistor to the first output bondpad.2. The power transistor die of claim 1 , further comprising:a second output bondpad integrally formed in the semiconductor die between the transistor and the output die side, wherein the second output bondpad is directly electrically connected to the output.4. A field effect transistor comprising:a semiconductor die with an input die side and an opposed output die side, wherein the semiconductor die includes a base ...

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Номер записи: 42
01-07-2021 дата публикации

POWER AMPLIFIER PACKAGES CONTAINING MULTI-PATH INTEGRATED PASSIVE DEVICES

Номер: US20210203278A1
Автор: MILLER MONTE G., Uscola Ricardo, Wei Yun
Принадлежит:

Power amplifier (PA) packages, such as Doherty PA packages, containing multi-path integrated passive devices (IPDs) are disclosed. In embodiments, the PA package includes a package body through which first and second signal amplification paths extend, a first amplifier die within the package body and positioned in the first signal amplification path, and a second amplifier die within the package body and positioned in the second signal amplification path. A multi-path IPD is further contained in the package body. The multi-path IPD includes a first IPD region through which the first signal amplification path extends, a second IPD region through which the second signal amplification path extends, and an isolation region formed in the IPD substrate a location intermediate the first IPD region and the second IPD region. 1. A power amplifier (PA) package , comprising:a package body through which a first signal amplification path and a second signal amplification path extend;a first amplifier die contained within the package body and positioned in the first signal amplification path;a second amplifier die contained within the package body and positioned in the second signal amplification path, the second amplifier die spaced from the first amplifier die along a first axis; and an IPD substrate;', 'a first IPD region through which the first signal amplification path extends, the first IPD region formed in the IPD substrate at a first location;', 'a second IPD region through which the second signal amplification path extends, the second IPD region formed in the IPD substrate at a second location spaced from the first location along a second axis perpendicular to the first axis; and', 'an isolation region formed in the IPD substrate at a third location intermediate the first location and the second location., 'a multi-path integrated passive device (IPD) further contained within the package body, the multi-path IPD comprising2. The PA package of claim 1 , wherein the first ...

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Номер записи: 43
23-06-2016 дата публикации

Hybrid passive device and hybrid manufacturing method

Номер: US20160182005A1
Автор: Ming-Da Tsai, Po-Sen Tseng, Tao-Yi Lee
Принадлежит: MediaTek Inc

A hybrid passive device for synergizing at least one passive component which resides in at least one technology is provided. The hybrid passive device includes a first passive component and a second passive component. The first passive component resides in a first technology of the at least one technology and/or a second technology of the at least one technology, the second technology is different from the first technology, and a technology boundary is arranged between the second technology and the first technology. The second passive component of the at least one passive component is different from the first passive component. The second passive component resides in the first technology and/or the second technology, and the first passive component and the second passive component are electromagnetically coupled to each other through the technology boundary.

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Номер записи: 44
22-06-2017 дата публикации

SEMICONDUCTOR DEVICE

Номер: US20170179050A1
Автор: KARIYAZAKI Shuuichi
Принадлежит:

A semiconductor device with enhanced performance. The semiconductor device has a high speed transmission path which includes a first coupling part to couple a semiconductor chip and an interposer electrically, a second coupling part to couple the interposer and a wiring substrate, and an external terminal formed on the bottom surface of the wiring substrate. The high speed transmission path includes a first transmission part located in the interposer to couple the first and second coupling parts electrically and a second transmission part located in the wiring substrate to couple the second coupling part and the external terminal electrically. The high speed transmission path is coupled with a correction circuit in which one edge is coupled with a branching part located midway in the second transmission part and the other edge is coupled with a capacitative element, and the capacitative element is formed in the interposer. 1. A semiconductor device comprising:a first substrate having a first front surface and a first back surface opposite to the first front surface;a second substrate having a second front surface and a second back surface opposite to the second front surface and being mounted over the first substrate with the first front surface of the first substrate facing the second back surface; anda first semiconductor component mounted over the second front surface of the second substrate and coupled with a first signal transmission path,the first signal transmission path comprising:a first coupling part to couple the first semiconductor component and the second substrate electrically;a second coupling part to couple the second substrate and the first substrate;a first external terminal formed on the first back surface of the first substrate;a first transmission part located in the second substrate to couple the first coupling part and the second coupling part electrically; anda second transmission part located in the first substrate to couple the second ...

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Номер записи: 45
28-05-2020 дата публикации

SEMICONDUCTOR PACKAGE WITH IN-PACKAGE COMPARTMENTAL SHIELDING AND FABRICATION METHOD THEREOF

Номер: US20200168566A1
Автор: Tsai Chung-Che
Принадлежит:

A semiconductor package includes a substrate. At least a high-frequency chip and a circuit component susceptible to high-frequency interference are disposed on a top surface of the substrate. A first ground ring is disposed on the substrate surrounding the high-frequency chip. A first metal-post reinforced glue wall is disposed on the first ground ring surrounding the high-frequency chip. A second ground ring is disposed on the top of the substrate surrounding the circuit component. A second metal-post reinforced glue wall is disposed on the second ground ring surrounding the circuit component. A molding compound covers at least the high-frequency chip and the circuit component. A conductive layer is disposed on the molding compound and is coupled to the first metal-post reinforced glue wall and/or the second metal-post reinforced glue wall. 1. A semiconductor package with an in-package compartmental shielding , comprising:a substrate having at least one high-frequency chip and a circuit component susceptible to high-frequency signal interference on a top surface of the substrate;a first ground ring, on the top surface of the substrate, surrounding the high-frequency chip;a first metal-post reinforced glue wall disposed on the first ground ring, surrounding the high-frequency chip;a second ground ring surrounding the circuit component on the top surface of the substrate;a second metal-post reinforced glue wall disposed on the second ground ring surrounding the circuit component;a molding compound covering at least the high-frequency chip and the circuit component; anda conductive layer disposed on the molding compound and in contact with the first metal-post reinforced glue wall and/or the second metal-post reinforced glue wall.2. The semiconductor package with an in-package compartmental shielding according to claim 1 , wherein the first metal-post reinforced glue wall comprises a plurality of first metal posts claim 1 , wherein one end of each of the plurality of ...

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Номер записи: 46
28-05-2020 дата публикации

METHOD FOR MINIMIZING DISTORTION OF A SIGNAL IN A RADIOFREQUENCY CIRCUIT

Номер: US20200169222A1
Автор: Allibert Frederic, Broekaart Marcel, Desbonnets Eric, Rack Martin, Raskin Jean-Pierre
Принадлежит:

A method for minimizing harmonic distortion and/or intermodulation distortion of a radiofrequency signal propagating in a radiofrequency circuit formed on a semiconductor substrate coated with an electrically insulating layer, wherein a curve representing the distortion as a function of a power of the input or output signal exhibits a trough around a given power (P), the method comprises applying, between the radiofrequency circuit and the semiconductor substrate, an electrical potential difference (V) chosen so as to move the trough toward a given operating power of the radiofrequency circuit. 1. A method for minimizing harmonic distortion and/or intermodulation distortion of a radiofrequency signal propagating in a radiofrequency circuit formed on a semiconductor substrate coated with an electrically insulating layer , wherein a curve representing the distortion as a function of a power of an input or output signal exhibits a trough around a given power (P) , the method comprising applying , between the radiofrequency circuit and the semiconductor substrate , an electrical potential difference (V) chosen so as to move the trough toward an operating power of the radiofrequency circuit.2. The method of claim 1 , wherein the electrical potential difference (V) is chosen so as to comply with the following equation: V=|V−V| claim 1 , where Vis the peak voltage of the radiofrequency signal and Vis the flat band voltage.3. The method of claim 1 , wherein the semiconductor substrate has an electrical resistivity of greater than 500 Ω·cm.4. The method of claim 3 , wherein a polycrystalline silicon layer is disposed between the semiconductor substrate and the electrically insulating layer.5. The method of claim 4 , wherein an additional electrically insulating layer is disposed between the semiconductor substrate and the polycrystalline silicon layer.6. The method of claim 1 , wherein the semiconductor substrate comprises silicon.7. The method of claim 1 , further ...

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Номер записи: 47
28-06-2018 дата публикации

INTEGRATED CIRCUIT DEVICES WITH SELECTIVELY ARRANGED THROUGH SUBSTRATE VIAS AND METHOD OF MANUFACTURE THEREOF

Номер: US20180182717A1
Автор: Kim Kevin, Lamey Daniel Joseph, Shilimkar Vikas
Принадлежит:

An integrated circuit device includes a device substrate having first and second opposing surfaces, a first component electrode coupled to the first surface, and a conductive plane coupled to the second surface. The integrated circuit device also includes a plurality of through substrate vias electrically coupling a first region of the first component electrode to the conductive plane through the device substrate, wherein a second adjacent region of the first component electrode is substantially devoid of through substrate vias. Arrangement of the plurality of through substrate vias in the first region is based on a projected current distribution through the first component electrode when the integrated circuit device is operational. 1. An integrated circuit device comprising:a device substrate having first and second opposing surfaces;a first component electrode coupled to the first surface;a conductive plane coupled to the second surface;a plurality of through substrate vias electrically coupling a first region of the first component electrode to the conductive plane through the device substrate, wherein a second adjacent region of the first component electrode is substantially devoid of through substrate vias, wherein arrangement of the plurality of through substrate vias in the first region is based on a projected current distribution through the first component electrode when the integrated circuit device is operational.2. The integrated circuit device of further comprising a current feed mechanism coupled relative to the first component electrode claim 1 , wherein the current feed mechanism is configured to provide current to the first component electrode when the integrated circuit device is operational.32. The integrated circuit device of claim 1 , wherein the first component electrode comprises a first perimeter segment claim 1 , and the current feed mechanism is coupled parallel to and aligned with the first perimeter segment.4. The integrated circuit ...

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Номер записи: 48
04-06-2020 дата публикации

ELECTRONIC DEVICE AND METHOD OF MANUFACTURING THE SAME

Номер: US20200176403A1
Автор: CHIU Hsih-Yang, KANG Ting-Cih
Принадлежит:

The present disclosure relates to an electronic device and a method of manufacturing a filtering component of the electronic device. The electronic device includes a semiconductor component, an insulating layer, at least one contact plug, and a filtering component. The insulating layer is disposed on the semiconductor component. The contact plug penetrates through the insulating layer. The filtering component is disposed on the insulating layer and the contact plug. The filtering component includes a bottom electrode, an isolation layer, a top electrode, and a dielectric layer. The bottom electrode is divided into a first segment connected to the contact plug and a second segment separated from the first segment. The isolation layer is disposed on the bottom electrode, the top electrode is disposed in the isolation layer, and the dielectric layer is disposed between the bottom electrode and the top electrode. 1. An electronic device , comprising:a semiconductor component;an insulating layer disposed on the semiconductor component;at least one contact plug penetrating through the insulating layer; and a bottom electrode divided into a first segment connected to the contact plug and a second segment separated from the first segment;', 'an isolation layer disposed on the bottom electrode;', 'a top electrode disposed in the isolation layer; and', 'a dielectric layer disposed between the bottom electrode and the top electrode., 'a filtering component disposed on the insulating layer and the contact plug, the filtering component comprising2. The electronic device of claim 1 , wherein the isolation layer is further disposed in a gap between the first segment and the second segment.3. The electronic device of claim 2 , wherein a lower surface of the bottom electrode is coplanar with a bottom surface of the isolation layer opposite to a top surface of the isolation layer.4. The electronic device of claim 1 , wherein the dielectric layer extends along a top surface of the ...

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Номер записи: 49
05-07-2018 дата публикации

BONDED STRUCTURES WITH INTEGRATED PASSIVE COMPONENT

Номер: US20180190580A1
Автор: Delacruz Javier A., Guevara Gabriel Z., Haba Belgacem, Huang Shaowu, Katkar Rajesh, Mirkarimi Laura Wills, Mohammed Ilyas
Принадлежит:

In various embodiments, a bonded structure is disclosed. The bonded structure can include an element and a passive electronic component having a first surface bonded to the element and a second surface opposite the first surface. The passive electronic component can comprise a first anode terminal bonded to a corresponding second anode terminal of the element and a first cathode terminal bonded to a corresponding second cathode terminal of the element. The first anode terminal and the first cathode terminal can be disposed on the first surface of the passive electronic component. 1. A microelectronic device comprising:a first insulating substrate;a capacitor having a first surface and a second surface opposite the first surface, the first surface of the capacitor mechanically coupled to the first insulating substrate;a second insulating substrate, the second surface of the capacitor mechanically coupled to the second insulating substrate such that the capacitor is disposed between the first and second insulating substrates;an insulating element disposed between the first and second insulating substrates; anda first interconnect extending through the first insulating substrate to electrically connect to a first terminal of the capacitor.2. The microelectronic device of claim 1 , wherein the first surface of the capacitor is mechanically coupled to the first insulating substrate by way of a first adhesive.3. The microelectronic device of claim 2 , wherein the second surface of the capacitor is mechanically coupled to the second insulating substrate by way of a second adhesive claim 2 , the insulating element further comprising the second adhesive.4. The microelectronic device of claim 2 , wherein the first adhesive comprises solder.5. The microelectronic device of claim 1 , wherein the insulating element comprises a molding compound disposed about portions of the capacitor.6. The microelectronic device of claim 1 , wherein the insulating element comprises a third ...

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Номер записи: 50
11-06-2020 дата публикации

INTEGRALLY-FORMED MULTIPLE-PATH POWER AMPLIFIER WITH ON-DIE COMBINING NODE STRUCTURE

Номер: US20200186097A1
Автор: FU XIN, Hue Xavier, Szymanowski Margaret
Принадлежит:

A multiple-path amplifier (e.g., a Doherty amplifier) includes a semiconductor die, a radio frequency (RF) signal input terminal, a combining node structure integrally formed with the semiconductor die, and first and second amplifiers (e.g., main and peaking amplifiers) integrally formed with the die. Inputs of the first and second amplifiers are electrically coupled to the RF signal input terminal. A plurality of wirebonds is connected between an output of the first amplifier and the combining node structure. An output of the second amplifier is electrically coupled to the combining node structure (e.g., through a conductive path with a negligible phase delay). A phase delay between the outputs of the first and second amplifiers is substantially equal to 90 degrees. The second amplifier may be divided into two amplifier portions that are physically located on opposite sides of the first amplifier. 1. A multiple-path amplifier comprising:a semiconductor die;a radio frequency (RF) signal input terminal;a combining node structure integrally formed with the semiconductor die;a first amplifier integrally formed with the semiconductor die, wherein an input of the first amplifier is electrically coupled to the RF signal input terminal;a plurality of wirebonds connected between an output of the first amplifier and the combining node structure; anda second amplifier integrally formed with the semiconductor die, wherein an input of the second amplifier is electrically coupled to the RF signal input terminal, and an output of the second amplifier is electrically coupled to the combining node structure.2. The multi-path amplifier of claim 1 , wherein the combining node structure comprises an elongated conductive bondpad that is exposed at a top surface of semiconductor die.3. The multi-path amplifier of claim 1 , wherein the output of the second amplifier is connected to the combining node structure with a conductive path having a negligible phase delay.4. The multi-path ...

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Номер записи: 51
21-07-2016 дата публикации

SEMICONDUCTOR PACKAGES HAVING WIRE BOND WALL TO REDUCE COUPLING

Номер: US20160211222A1
Автор: Hart Paul R., KUO SHUN MEEN, SZYMANOWSKI Margaret A
Принадлежит:

A device (e.g., a Doherty amplifier) housed in an air cavity package includes one or more isolation structures over a surface of a substrate and defining an active circuit area. The device also includes first and second adjacent circuits within the active circuit area, first and second leads coupled to the isolation structure(s) between opposite sides of the package and electrically coupled to the first circuit, third and fourth leads coupled to the isolation structure(s) between the opposite sides of the package and electrically coupled to the second circuit, a first terminal over the first side of the package between the first lead and the third lead, a second terminal over the second side of the package between the second lead and the fourth lead, and an electronic component coupled to the package and electrically coupled to the first terminal, the second terminal, or both the first and second terminals. 1. A method of making a device housed within a package that includes a substrate , the method comprising the steps of:defining an active circuit area over the top surface of the substrate;positioning a first lead above the substrate and proximate to a first side of the package;positioning a second lead above the substrate and proximate to a second side of the package;positioning a third lead above the substrate and proximate to the first side of the package;positioning a fourth lead above the substrate and proximate to the second side of the package;attaching a first circuit over the top surface of the substrate within the active circuit area;electrically coupling the first circuit between the first and second leads;attaching a second circuit over the top surface of the substrate within the active circuit area and adjacent to the first circuit;electrically coupling the second circuit between the third and fourth leads;coupling a plurality of connection pads over the substrate in a row between the first circuit and the second circuit;positioning a first terminal ...

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Номер записи: 52
27-06-2019 дата публикации

CIRCUIT SYSTEM HAVING COMPACT DECOUPLING STRUCTURE

Номер: US20190198460A1
Автор: FUJIISHI Yoshitaka, HARAGUCHI Masaru
Принадлежит:

A circuit system having compact decoupling structure, including: a mother board; at least one circuit unit, each having a substrate, a logic-circuit die, a plurality of first metal contacts, and a plurality of second metal contacts, the substrate having a first surface and a second surface, the first metal contacts being formed on the first surface and soldered onto the mother board, the second metal contacts being formed on the logic-circuit die and soldered onto the second surface to form flip-chip pillars, and the flip-chip pillars determining a height of a gap between the die and the substrate; and at least one decoupling unit for providing an AC signals decoupling function for the at least one circuit unit; wherein each of the at least one decoupling unit is placed in the gap of one said circuit unit and includes a mother die and at least one stack-type integrated-passive-device die. 1. A circuit system having compact decoupling structure , including:a mother board;at least one circuit unit, each having a substrate, a logic-circuit die, a plurality of first metal contacts, and a plurality of second metal contacts, wherein the substrate has a first surface and a second surface opposing the first surface, the first metal contacts are formed on the first surface and soldered onto the mother board, the second metal contacts are formed on the logic-circuit die and soldered onto the second surface of the substrate to form flip-chip pillars, and the flip-chip pillars determine a height of a gap between the logic-circuit die and the substrate; andat least one decoupling unit for providing an AC signals decoupling function for the at least one circuit unit;wherein, each of the at least one decoupling unit is placed in the gap of one said circuit unit and includes a mother die, at least one stack-type integrated-passive-device die, and a plurality of third metal contacts, the third metal contacts being formed on the mother die and soldered onto the logic-circuit die, and ...

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Номер записи: 53
29-07-2021 дата публикации

MICROWAVE DEVICE AND ANTENNA

Номер: US20210233865A1
Автор: ISHIDA Kiyoshi, Kimura Makoto, MATSUOKA Hiroaki, MIYAWAKI Katsumi, Tarui Yukinobu
Принадлежит: Mitsubishi Electric Corporation

A microwave device includes: a first multilayer resin substrate including a ground via hole; a semiconductor substrate provided at the first multilayer resin substrate and including a high frequency circuit; and a conductive heat spreader provided at an opposite face of the semiconductor substrate from a face of the semiconductor substrate facing the first multilayer resin substrate. The microwave device includes: a resin provided over the first multilayer resin substrate and covering the semiconductor substrate and the heat spreader such that an opposite face of the heat spreader from a face of the heat spreader facing the semiconductor substrate is exposed as an exposed face; and a conductive film covering the resin and the heat spreader and touching the exposed face. The semiconductor substrate includes a ground through hole extending through the semiconductor substrate. The conductive film is electrically connected to the ground via hole via the heat spreader and the ground through hole. 1. A microwave device comprising:a first multilayer resin substrate including a plurality of ground via holes;a semiconductor substrate disposed at one surface of the first multilayer resin substrate and including a high frequency circuit electrically connected to the first multilayer resin substrate;a conductive heat spreader disposed at an opposite face of the semiconductor substrate from a face of the semiconductor substrate that faces the first multilayer resin substrate, the heat spreader being electrically connected to the semiconductor substrate;a resin disposed over the one surface of the first multilayer resin substrate and covering the semiconductor substrate and the heat spreader such that an opposite face of the heat spreader from a face of the heat spreader that faces the semiconductor substrate is exposed as an exposed face; anda conductive film covering the resin and the heat spreader and in contact with the exposed face, whereinthe semiconductor substrate ...

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Номер записи: 54
04-07-2019 дата публикации

Design and placement of de-coupling capacitors for pdn design

Номер: US20190206815A1
Автор: Abhishek Nagaraj LAGUVARAM, Vinod Arjun HUDDAR
Принадлежит: SEAGATE TECHNOLOGY LLC

Systems and methods for placing capacitors between IC bumps and BGA balls are described. In one embodiment, the method may include placing a ball grid array (BGA) package or integrated circuit (IC) package on a printed circuit board (PCB) of an electronic device, and placing a capacitor between a first BGA ball and a second BGA ball of the BGA package and/or placing a capacitor between a first IC bump and a second IC bump of the IC package to maintain impedance of a power delivery network (PDN) of the BGA package or IC package below a target impedance.

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Номер записи: 55
25-06-2020 дата публикации

HIGH POWER RADIO FREQUENCY AMPLIFIERS AND METHODS OF MANUFACTURE THEREOF

Номер: US20200204121A1
Автор: HOLMES Damon G., Roberts Jeffrey Spencer, ZHU Ning
Принадлежит: NXP USA, Inc.

The embodiments described herein provide radio frequency (RF) amplifiers, and in some embodiments provide amplifiers that can be used in high power RF applications. Specifically, the amplifiers described herein may be implemented with multiple resonant circuits to provide class F and inverse class F amplifiers and methods of operation. In general, the resonant circuits are implemented inside a device package with a transistor die to provide high efficiency amplification for a variety of applications. 1. A class F radio frequency (RF) amplifier configured to operate at a fundamental frequency (f) , the class F RF amplifier comprising: a first transistor die, wherein the first transistor die includes a first transistor, a first input terminal, and a first output terminal, the first transistor including an intrinsic output capacitance providing a first capacitance; and', a first bondwire array connected between the first output terminal and the first output lead, the first bondwire array providing a first inductance;', {'sub': 0', '0', '0, 'a first 2fresonant circuit configured to resonate at a second harmonic frequency (2f) and create a short circuit between the first output terminal and a ground for signal energy at the second harmonic frequency (2f);'}, {'sub': 0', '0', '0, 'a first 3fresonant circuit configured to resonate at a third harmonic frequency (3f) and create a short circuit between the first output lead and the ground for signal energy at the third harmonic frequency (3f); and'}, {'sub': 0', '0', '0', '0', '0', '0', '0, 'wherein when the first 3fresonant circuit resonates, a second 3fresonant circuit is realized, where the second 3fresonant circuit includes the intrinsic output capacitance, the first inductance, and the first 2fresonant circuit, and wherein the second 3fresonant circuit is configured to resonate at the third harmonic frequency (3f) and create an open circuit between the first output terminal and the first output lead for signal energy at ...

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Номер записи: 56
25-06-2020 дата публикации

HIGH POWER RADIO FREQUENCY AMPLIFIERS AND METHODS OF MANUFACTURE THEREOF

Номер: US20200204122A1
Автор: HOLMES Damon G., Roberts Jeffrey Spencer, ZHU Ning
Принадлежит: NXP USA, Inc.

The embodiments described herein provide radio frequency (RF) amplifiers, and in some embodiments provide amplifiers that can be used in high power RF applications. Specifically, the amplifiers described herein may be implemented with multiple resonant circuits to provide class F and inverse class F amplifiers and methods of operation. In general, the resonant circuits are implemented inside a device package with a transistor die to provide high efficiency amplification for a variety of applications. 1. An inverse class F radio frequency (RF) amplifier configured to operate at a fundamental frequency (f) , the inverse class F RF amplifier comprising: a first transistor die, wherein the first transistor die includes a first transistor, a first input terminal, and a first output terminal, the first transistor including an intrinsic output capacitance providing a first capacitance; and', a first bondwire array connected between the first output terminal and the first output lead, the first bondwire array providing a first inductance;', {'sub': 0', '0', '0, 'a first 3fresonant circuit configured to resonate at a third harmonic frequency (3f) and create a short circuit between the first output terminal and a ground for signal energy at the third harmonic frequency (3f);'}, {'sub': 0', '0', '0, 'a first 2fresonant circuit configured to resonate at a second harmonic frequency (2f) and create a short circuit between the first output lead and the ground for signal energy at the second harmonic frequency (2f); and'}, {'sub': 0', '0', '0', '0', '0', '0', '0, 'wherein when the first 2fresonant circuit resonates, a second 2fresonant circuit is realized, where the second 2fresonant circuit includes the intrinsic output capacitance, the first inductance, and the first 3fresonant circuit, and wherein the second 2fresonant circuit is configured to resonate at the second harmonic frequency (2f) and create an open circuit between the first output terminal and the first output lead for ...

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Номер записи: 57
05-08-2021 дата публикации

MITIGATING THERMAL-MECHANICAL STRAIN AND WARPAGE OF AN ORGANIC LAMINATE SUBSTRATE

Номер: US20210242139A1
Автор: Arvin Charles Leon, Ostrander Steven Paul, Quinlan Brian W., Sinha Tuhin, TUNGA Krishna R., Weiss Thomas
Принадлежит:

A multi-chip module (MCM) package includes an organic laminate substrate; first and second semiconductor device chips that are mounted to a top side of the substrate and that define a chip gap region between opposing edges of the chips; and a stiffener that is embedded in the bottom side of the substrate. The stiffener extends across a stiffening region, which underlies the chip gap region, and does not protrude beyond a bottom side metallization of the substrate. 1. A method comprising:providing a stiffener at a bottom side of an organic laminate substrate by indenting the substrate, depositing an adhesive into the indentation in the substrate, and placing the stiffener into the indentation with sufficient pressure to displace the adhesive at contact points between the stiffener and circuitry of the substrate, wherein the stiffener extends across a stiffening region and does not protrude beyond a bottom side metallization of the substrate; andfabricating a multi-chip module by mounting first and second chips to a top side of the substrate, wherein the first and second chips define a chip gap region between opposing edges thereof, and the chip gap region overlies the stiffening region.2. The method of wherein the stiffener is effectively matched to the substrate in coefficient of thermal expansion.3. The method of wherein the stiffener is rectangular in shape and is coextensive with the chip gap region.4. The method of wherein the stiffener extends beyond ends of the chip gap region.5. The method of wherein the stiffener comprises a plurality of stiffener bars that are separated by at least one inter-bar gap claim 1 , further comprising making electrical connections between the chips through the at least one inter-bar gap.6. The method of wherein the stiffener is provided by forming the organic laminate around the stiffener.7. (canceled)8. The method of further comprising making an electrical connection to the stiffener from at least one of the chips through the ...

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Номер записи: 58
04-08-2016 дата публикации

METHOD OF MANUFACTURING SEMICONDUCTOR PACKAGE

Номер: US20160225728A1
Автор: Chiu Chih-Hsien, Chu Heng-Cheng, Chu Yude, Chung Hsin-Lung, Lin Chien-Cheng, TSAI Tsung-Hsien
Принадлежит:

A semiconductor package and a method of manufacturing the same are provided. The semiconductor package includes: a substrate having a plurality of conductive lands and a plurality of bonding pads surrounding the conductive lands formed on a surface thereof; a plurality of passive devices mounted on the conductive lands; an insulation layer formed on the surface and having a portion of the passive devices embedded therein; a semiconductor chip mounted on a top surface of the insulation layer; a plurality of bonding wires electrically connecting the semiconductor chip and the bonding pads; an encapsulant formed on the surface of the substrate to encapsulate the insulation layer, the bonding wires and the semiconductor chip, wherein a region of the semiconductor chip projected onto the substrate covers a portion of an outermost one of the passive devices. Therefore, the mounting density of the passive devices is improved. 15-. (canceled)6. A method of manufacturing a semiconductor package , comprising:providing a substrate having a plurality of conductive lands and a plurality of bonding pads surrounding the conductive lands formed on a surface thereof;mounting a plurality of passive devices on the conductive lands and electrically connecting the passive devices to the conductive lands;forming an insulation layer on the surface of the substrate and having a portion of the passive devices embedded therein;mounting a semiconductor chip on a top surface of the insulation layer and electrically connecting the semiconductor chip to the bonding pads with a plurality of bonding wires, wherein a region of the semiconductor chip projected onto the substrate covers a portion of an outermost one of the passive devices; andforming an encapsulant on the surface of the substrate to encapsulate the insulation layer, the bonding wires and the semiconductor chip.7. The method of claim 6 , wherein the outermost one of the passive devices protrudes 0.1 to 1.5 mm from the region of the ...

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Номер записи: 59
04-08-2016 дата публикации

Power fet with a resonant transistor gate

Номер: US20160225759A1
Автор: L. Pierre de Rochemont
Принадлежит: Individual

A semiconductor FET provides a resonant gate and source and drain electrodes, wherein the resonant gate is electromagnetically resonant at one or more predetermined frequencies.

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Номер записи: 60
03-08-2017 дата публикации

Semiconductor memory device including power decoupling capacitor

Номер: US20170221543A1
Автор: Doo-Young Kim, Sung-Hoon Kim
Принадлежит: SAMSUNG ELECTRONICS CO LTD

A semiconductor memory device includes a power decoupling capacitor (PDC) for preventing effective capacitance reduction during a high frequency operation. The semiconductor memory device includes the PDC to which a cell capacitor type decoupling capacitor is connected in series. The PDC includes a metal conductive layer electrically connected in parallel to a conductive layer formed on the same level as a bit line of a cell array region, wherein a plurality of decoupling capacitors in a first group and a plurality of decoupling capacitors in a second group are respectively connected to each other in parallel in a peripheral circuit region, and a storage electrode of the first group and a storage electrode of the second group are electrically connected to each other in series through the conductive layer.

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Номер записи: 61
11-07-2019 дата публикации

VERTICAL CAPACITORS FOR MICROELECTRONICS

Номер: US20190214353A1
Автор: Delacruz Javier A., Haba Belgacem
Принадлежит: INVENSAS CORPORATION

Vertical capacitors for microelectronics are provided. An example thin capacitor layer can provide one or numerous capacitors to a semiconductor chip or integrated circuit. In an implementation, a thin capacitor layer of 50-100 μm thickness may have 5000 vertically disposed capacitor plates per linear centimeter, while occupying only a thin slice of the package. Electrodes for each capacitor plate are accessible at multiple surfaces. Electrode density for very fine pitch interconnects can be in the range of 2-200 μm separation between electrodes. A redistribution layer (RDL) may be fabricated on one or both sides of the thin capacitor layer to provide fan-out ball grid arrays that occupy insignificant space. RDLs or through-vias can connect together sets of the interior vertical capacitor plates within a given thin capacitor layer to form various capacitors from the plates to meet the needs of particular chips, dies, integrated circuits, and packages. 1. An apparatus , comprising:a capacitor layer to underlie a semiconductor chip, a die, or an integrated circuit;vertical capacitor plates in the capacitor layer interleaved with vertical dielectric layers; andelectrodes of each vertical capacitor plate at a top surface and a bottom surface of the capacitor layer.2. The apparatus of claim 1 , wherein the capacitor layer has a thickness in a range of approximately 50-400 micrometers (μm) between the top surface and the bottom surface.3. The apparatus of claim 1 , wherein the capacitor layer comprises approximately 5000 vertical capacitor plates per linear centimeter of the capacitor layer.4. The apparatus of claim 1 , further comprising a direct-bond between the vertical capacitor plates.5. The apparatus of claim 4 , wherein a thickness of the capacitor layer is selected from the group consisting of a thickness in the range of approximately 50-100 μm claim 4 , a thickness in the range of approximately 100-200 μm claim 4 , and a thickness in the range of approximately ...

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Номер записи: 62
11-07-2019 дата публикации

Switch ic, front-end module, and communication apparatus

Номер: US20190214355A1
Автор: Hiroshi Nishikawa
Принадлежит: Murata Manufacturing Co Ltd

A switch IC includes first, second and third switch units, and an amplifier. The first switch unit and the third switch unit are adjacent to each other. The third switch unit and the amplifier are adjacent to each other. The amplifier and the second switch unit are adjacent to each other. The first, second and third switch units, and the amplifier are disposed on a straight line in an order in which a signal passes through the first switch unit, the second switch unit, the third switch unit, and the amplifier.

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Номер записи: 63
11-07-2019 дата публикации

MAGNETIC COUPLING PACKAGE STRUCTURE FOR MAGNETICALLY COUPLED ISOLATOR WITH DUO LEADFRAMES AND METHOD FOR MANUFACTURING THE SAME

Номер: US20190214368A1
Автор: LAI WEI-WEN, LIN PU-HAN, WANG You-Fa
Принадлежит:

The instant disclosure includes a magnetic coupling package structure with duo leadframes for a magnetically coupled isolator and a method for manufacturing the same. The method includes a leadframe providing step, a chip connecting step and a coil alignment step. The leadframe providing step includes providing a first and a second leadframe each including a chip carrying portion, a coil portion, a plurality of pins and floating pins. The chip connecting step includes disposing at least a first chip and at least a second chip onto the corresponding chip carrying portions for electrically connecting the chips to the pins. The coil alignment step includes arranging the first leadframe above or beneath the second leadframe and applying a first and a second magnetic field to the first and the second leadframes respectively for aligning the coil portions, thereby controlling the coupling effect between two coil portions. 1. A method for manufacturing a magnetic coupling package structure with duo leadframes for a magnetically coupled isolator , comprising:a leadframe providing step including providing a first leadframe and a second leadframe, wherein the first leadframe includes a first chip-mounting portion, at least a coil portion, a plurality of first pins and a plurality of floated pins, and the second leadframe includes a second chip-mounting portion, at least a second coil portion, a plurality of second pins and a plurality of second floated pins;a chip connecting step including respectively disposing at least a first chip and at least a second chip on the first chip-mounting portion and the second chip-mounting portion and establishing electrical connections between the first chip and the first pins and between the second chip and the second pins; anda coil aligning step including disposing the first leadframe at a position above or under the second leadframe and respectively applying a first magnetic field and a second magnetic field to the first leadframe and ...

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Номер записи: 64
02-07-2020 дата публикации

HIGH CUTOFF FREQUENCY METAL-INSULATOR-METAL CAPACITORS IMPLEMENTED USING VIA CONTACT CONFIGURATIONS

Номер: US20200211955A1
Автор: Groves Robert, Rubin Joshua M., SILBERMAN JOEL A.
Принадлежит:

Devices and methods are provided for fabricating a metal-insulator-metal capacitor within an interconnect structure (e.g., back-end-of-line interconnect structure) to provide capacitive decoupling between positive and negative power supply voltage lines of a power distribution network. Various via contact configurations including interlevel via contacts and truncated via contacts are utilized to connect the metal-insulator-metal capacitor electrodes to power supply voltage lines of the power distribution network to provide an array of high-density, low resistance via contact connections at various locations across the capacitor electrodes to reduce the resistance of the metal-insulator-metal capacitor and, thus, enhance the transient response time and increase the cutoff frequency of the metal-insulator-metal capacitor. The truncated via contacts allow for higher density via contact connections to the capacitor electrodes in regions which have a dense array of wiring of a single polarity, where interlevel via contacts cannot be utilized to provide contacts to the capacitor electrodes. 1. A device , comprising:an interconnect structure comprising a first metallization level and a second metallization level, wherein the first and second metallization levels comprise metal lines which form wiring of a power distribution network for distributing power supply voltage of a first polarity and power supply voltage of a second polarity, wherein the second metallization level comprises a dense region of metal lines to distribute power supply voltage of the first polarity;a metal-insulator-metal capacitor disposed between the first and second metallization levels, wherein the metal-insulator-metal capacitor comprises a first capacitor electrode, a second capacitor electrode, and a first capacitor dielectric layer disposed between the first and second capacitor electrodes;a first interlevel via contact which connects a metal line of the first metallization level with a metal ...

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Номер записи: 65
17-08-2017 дата публикации

Semiconductor Device on Leadframe with Integrated Passive Component

Номер: US20170236790A1
Автор: Chinnusamy Satyamoorthi, Reyes Jayson Nathaniel S., Tan Weng Hing
Принадлежит: SEMTECH CORPORATION

A semiconductor device includes a substrate and a first conductive layer formed over a first surface of the substrate. The first conductive layer is patterned into a first portion of a first passive circuit element. The first conductive layer is patterned to include a first coiled portion. A second conductive layer is formed over a second surface of the substrate. The second conductive layer is patterned into a second portion of the first passive circuit element. The second conductive layer is patterned to include a second coiled portion exhibiting mutual inductance with the first coiled portion. A conductive via formed through the substrate is coupled between the first conductive layer and second conductive layer. A semiconductor component is disposed over the substrate and electrically coupled to the first passive circuit element. An encapsulant is deposited over the semiconductor component and substrate. The substrate is mounted to a printed circuit board. 1. A method of making a semiconductor device , comprising:providing a substrate;forming a first conductive layer over a first surface of the substrate;patterning the first conductive layer into a first portion of a first passive circuit element;forming a second conductive layer over a second surface of the substrate;patterning the second conductive layer into a second portion of the first passive circuit element; anddisposing a semiconductor component over the substrate and electrically coupled to the first passive circuit element.2. The method of claim 1 , further including:patterning the first conductive layer to include a first coiled portion; andpatterning the second conductive layer to include a second coiled portion exhibiting a mutual inductance with the first coiled portion.3. The method of claim 1 , further including patterning the first conductive layer to include a plate of a capacitor.4. The method of claim 1 , further including depositing an encapsulant over the semiconductor component and ...

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Номер записи: 66
25-07-2019 дата публикации

Packaged RF Power Amplifier Having a High Power Density

Номер: US20190229077A1
Автор: Albertus Gerardus Wihelmusi Van Zuijlen, Johannes Adrianus Maria De Boet, Jordan Konstantlnov Sveshtarov, Vittorio Cuoco, Yi Zhu, Yuri Volokhine
Принадлежит: Samba Holdco Netherlands BV

A packaged RF power amplifier comprises an output network coupled to the output of a RF power transistor, which output network comprises a plurality of first bondwires extending along a first direction between the output of transistor and an output lead of the package, a series connection of a second inductor and a first capacitor between the output of the RF power transistor and ground, and a series connection of a third inductor and a second capacitor connected in between ground and the junction between the second inductor and the first capacitor. The first and second capacitors are integrated on a single passive die and the third inductor comprises a first part and a second part connected in series, wherein the first part extends at least partially along the first direction, and wherein the second part extends at least partially in a direction opposite to the first direction.

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Номер записи: 67
23-08-2018 дата публикации

3D Low Flux, High-Powered MMIC Amplifiers

Номер: US20180241356A1
Автор: Araki Dean L, Laquer Andrew George, Yang Pohan
Принадлежит:

The present disclosure relates systems and methods for providing a three-dimensional device architecture for transistor elements in a power amplifier circuit. Namely, an example system may include a plurality of high electron mobility transistors disposed on a first substrate. A first portion of the plurality of high electron mobility transistors are electrically coupled via respective first level interconnects disposed on the first substrate. The system also includes a plurality of second level interconnects disposed on a second substrate. A second portion of the plurality of high electron mobility transistors are electrically coupled via respective second level interconnects. The first substrate and the second substrate are coupled such that the plurality of high electron mobility transistors provides an amplified output signal via at least one of the first level interconnects or the second level interconnects. 1. A system comprising:a plurality of high electron mobility transistors disposed on a first substrate, wherein the plurality of high electron mobility transistors is configured to accept an input signal from an input and provide an output signal at an output, wherein the output signal comprises an amplified version of the input signal, wherein a first portion of the plurality of high electron mobility transistors are electrically coupled via respective first level interconnects disposed on the first substrate; anda plurality of second level interconnects disposed on a second substrate, wherein the first substrate and the second substrate comprise different materials, wherein a second portion of the plurality of high electron mobility transistors are electrically coupled via respective second level interconnects, wherein the first substrate and the second substrate are coupled such that the plurality of high electron mobility transistors provides the output signal via at least one of the first level interconnects or the second level interconnects.2. The ...

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Номер записи: 68
01-08-2019 дата публикации

RESISTANCE AND CAPACITANCE BALANCING SYSTEMS AND METHODS

Номер: US20190237417A1
Автор: Dobbins Jim, Jain Sheetal, SHI Wenjun, SUDHAKARAN Sunil, Templeton Don, Zhou Yaping
Принадлежит:

Systems and methods that facilitate resistance and capacitance balancing are presented. In one embodiment, a system comprises: a plurality of ground lines configured to ground components; and a plurality of signal bus lines interleaved with the plurality of ground lines, wherein the interleaving is configured so that plurality of signal bus lines and plurality of ground lines are substantially evenly spaced and the plurality of signal bus lines convey a respective plurality of signals have similar resistance and capacitance constants that are balanced. The plurality of signals can see a substantially equal amount ground surface and have similar amounts of capacitance. The plurality of signal bus lines can have similar cross sections and lengths with similar resistances. The plurality of signal bus lines interleaved with the plurality of ground lines can be included in a two copper layer interposer design with one redistribution layer (RDL). 1. A high speed signal distribution circuit in an integrated circuit , wherein the distribution circuit comprises:a plurality of ground lines configured to supply a ground voltage to components; anda plurality of signal bus lines interleaved with the plurality of ground lines, wherein the interleaving is configured so that the plurality of signal bus lines and the plurality of ground lines are substantially evenly spaced and the plurality of signal bus lines transmit a respective plurality of signals, wherein resistance and capacitance (RC) time constants of the plurality of signal bus lines are balanced, and wherein the plurality of signal bus lines and the plurality of ground lines are included in a corresponding two copper layer interposer design with one associated redistribution layer (RDL).2. The integrated circuit of claim 1 , wherein the plurality of signal bus lines are sufficiently balanced to avoid violating a timing margin.3. The integrated circuit of claim 1 , wherein at least two of the plurality of signal bus lines ...

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Номер записи: 69
31-08-2017 дата публикации

TRANSISTOR LAYOUT WITH LOW ASPECT RATIO

Номер: US20170250200A1
Автор: BRONGO Maureen Rosenberg, JOSHI Aniruddha B., LEE Tzung-Yin, Whitefield David Scott
Принадлежит:

A radio-frequency (RF) device includes a semiconductor substrate, a first field-effect transistor (FET) disposed on the substrate, the first FET having a first plurality of drain fingers, and a second FET connected in series with the first FET along a first dimension, the second FET having a second plurality of drain fingers that extent in a second dimension that is orthogonal with respect to the first dimension. 1. A radio-frequency device comprising:a semiconductor substrate;a first field-effect transistor disposed on the substrate, the first field-effect transistor having a first plurality of drain fingers; anda second field-effect transistor connected in series with the first field-effect transistor along a first dimension, the second field-effect transistor having a second plurality of drain fingers that extent in a second dimension that is orthogonal with respect to the first dimension.2. The radio-frequency device of wherein the second plurality of drain fingers includes more fingers than the first plurality of drain fingers.3. The radio-frequency device of wherein the first field-effect transistor has a length in the second dimension that is substantially equal to a length of the second field-effect transistor in the second dimension.4. The radio-frequency device of wherein the length of the first field-effect transistor and the length of the second field-effect transistor are both less than 15 μm.5. The radio-frequency device of further comprising one or more drain contact bars extending over the second plurality of drain fingers in the first dimension and contacting one or more of the second plurality of drain fingers.6. The radio-frequency device of further comprising a plurality of drain contact bars extending over the second plurality of drain fingers in the first dimension and a plurality of source contact bars extending over source fingers of the second field-effect transistor claim 1 , the plurality of drain contact bars and the plurality of source ...

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Номер записи: 70
07-09-2017 дата публикации

SIGNAL TRANSMISSION DEVICE USING ELECTROMAGNETIC RESONANCE COUPLER

Номер: US20170256507A1
Автор: CHOE Songbaek, NAGAI Shuichi
Принадлежит:

A signal transmission device comprises: a first lead frame having a first major surface and a second major surface opposite to the first major surface; a second lead frame having a third major surface and a fourth major surface and isolated from the first lead frame, the fourth major surface located opposite to the third major surface; a transmission circuit that sends a transmission signal, the transmission circuit located on the first major surface of the first lead frame; a receiving circuit located on the third major surface of the second lead frame; and an electromagnetic resonance coupler located across between the second major surface of the first lead frame and the fourth major surface of the second lead frame to transmit the transmission signal, sent by the transmission circuit, to the receiving circuit in a contactless manner. 1. A signal transmission device comprising:a first lead frame having a first major surface and a second major surface opposite to the first major surface;a second lead frame having a third major surface and a fourth major surface and isolated from the first lead frame, the fourth major surface located opposite to the third major surface;a transmission circuit that sends a transmission signal, the transmission circuit located on the first major surface of the first lead frame;a receiving circuit located on the third major surface of the second lead frame; andan electromagnetic resonance coupler located across between the second major surface of the first lead frame and the fourth major surface of the second lead frame to transmit the transmission signal, sent by the transmission circuit, to the receiving circuit in a contactless manner.2. The signal transmission device according to claim 1 ,wherein an end portion of the first lead frame is bent toward the first major surface side, and an end portion of the second lead frame is bent toward the third major surface side.3. The signal transmission device according to claim 1 ,wherein an ...

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Номер записи: 71
15-08-2019 дата публикации

HIGH-VOLTAGE CAPACITOR STRUCTURE AND DIGITAL ISOLATION APPARATUS

Номер: US20190252331A1
Автор: CHENG CHUN-YI
Принадлежит:

A high-voltage capacitor structure comprises a capacitor. The capacitor includes a substrate, a field oxidation layer, an active region, a dielectric layer, a passivation layer and a metal layer. The field oxidation layer is disposed above the substrate. The active region is disposed above the substrate or in the substrate. The dielectric layer is disposed above the active region and the field oxidation layer. The passivation layer is disposed above the dielectric layer. The metal layer is disposed above the passivation layer. The metal layer and the active region serve as a first electrode and a second electrode of the capacitor, respectively, wherein the active region is disposed below the dielectric layer. Some embodiments provide a digital isolation apparatus comprising at least one high-voltage isolator, each of which includes the above high-voltage capacitor structure. 1. A high-voltage capacitor structure , comprising: a substrate;', 'a field oxidation layer, disposed above the substrate;', 'an active region, disposed above the substrate or in the substrate;', 'a dielectric layer, disposed above the active region and the field oxidation layer;', 'a passivation layer, disposed above the dielectric layer; and', 'a metal layer, disposed above the passivation layer;, 'a capacitor, the capacitor includingwherein the metal layer and the active region serve as a first electrode and a second electrode of the capacitor, respectively, wherein the active region is disposed below the dielectric layer, the field oxidation layer has at least one opening, and the active region is disposed in a location of the substrate corresponding to one of the at least one opening; andwherein no source region and no drain region are disposed correspondingly in the at least one opening of the field oxidation layer and the active region includes no source region and no drain region.2. The high-voltage capacitor structure according to claim 1 , wherein the active region is disposed on a ...

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Номер записи: 72
14-09-2017 дата публикации

MULTILAYER SUBSTRATE

Номер: US20170264260A1
Автор: FUKUCHI Satoru
Принадлежит: KABUSHIKI KAISHA TOSHIBA

According to one embodiment, there is provided a multilayer substrate including a signal layer. The signal layer includes a first line and a second line which form a differential pair. The first line electrically connects a first node and a second node in the signal layer. The second line electrically connects a third node and a fourth node in the signal layer. The interval between the first line and the second line is approximately constant from the first node to the second node. A physical length from the third node to the fourth node in the second line is shorter than a physical length from the first node to the second node in the first line. A width of the second line is thicker than a width of the first line. 1. A multilayer substrate , comprisinga signal layer that includes a first line and a second line which form a differential pair,the first line electrically connecting a first node and a second node in the signal layer,the second line electrically connecting a third node and a fourth node in the signal layer,an interval between the first line and the second line being approximately constant from the first node to the second node,a physical length from the third node to the fourth node in the second line being shorter than a physical length from the first node to the second node in the first line, anda width of the second line being thicker than a width of the first line.2. The multilayer substrate according to claim 1 ,wherein the width of the first line is approximately constant from the first node to the second node, andthe width of the second line is approximately constant from the third node to the fourth node.3. The multilayer substrate according to claim 1 ,wherein an average value of a radius of curvature of a second curve along the second line is smaller than an average value of a radius of curvature of a first curve along the first line.4. The multilayer substrate according to claim 3 ,wherein the first curve and the second curve are bent to one ...

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Номер записи: 73
01-10-2015 дата публикации

SEMICONDUCTOR SOCKET WITH DIRECT SELECTIVE METALIZATION

Номер: US20150279768A1
Автор: Rathburn James
Принадлежит: HSIO TECHNOLOGIES

A semiconductor socket including a substrate with a plurality of through holes extending from a first surface to a second surface. A conductive structure is disposed within the through holes A plurality of discrete contact members are located in the plurality of the through holes, within the conductive structure. The plurality of contact members each include a proximal end accessible from the second surface, and a distal end extending above the first surface. The conductive structure can be electrically coupled to circuit geometry. At least one dielectric layer is bonded to the second surface of the substrate with recesses corresponding to desired circuit geometry. A conductive material deposited in at least a portion of the recesses to form conductive traces redistributing terminal pitch of the proximal ends of the contact members. 1. A semiconductor socket comprising:a plurality of through holes extending through a substrate from a first surface of the substrate to a second surface of the substrate, the each of the plurality of through holes defined by an inner wall of the substrate extending between the first surface and the second surface;a conductive material deposited on the inner walls of the plurality of holes to create a plurality of conductive structures;at least one dielectric layer bonded to the conductive structures; anda plurality of discrete contact members disposed in the plurality of the through holes, the plurality of contact members each comprising a proximal end accessible from the second surface, and a distal end extending above the first surface, wherein the conductive structures extend around at least portion of each of the plurality of discrete contact members.2. The semiconductor socket of claim 1 , wherein the conductive structures comprise conductive sleeves.3. The semiconductor socket of claim 1 , wherein the conductive material comprises electro-less plated metal.4. The semiconductor socket of claim 3 , wherein the conductive structures ...

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Номер записи: 74
20-09-2018 дата публикации

SEMICONDUCTOR PACKAGES HAVING WIRE BOND WALL TO REDUCE COUPLING

Номер: US20180269158A1
Автор: Hart Paul R., KUO SHUN MEEN, Szymanowski Margaret A.
Принадлежит:

A device (e.g., a Doherty amplifier) housed in an air cavity package includes one or more isolation structures over a surface of a substrate and defining an active circuit area. The device also includes first and second adjacent circuits within the active circuit area, first and second leads coupled to the isolation structure(s) between opposite sides of the package and electrically coupled to the first circuit, third and fourth leads coupled to the isolation structure(s) between the opposite sides of the package and electrically coupled to the second circuit, a first terminal over the first side of the package between the first lead and the third lead, a second terminal over the second side of the package between the second lead and the fourth lead, and an electronic component coupled to the package and electrically coupled to the first terminal, the second terminal, or both the first and second terminals. 1. A device comprising:a ground plane having a first surface;a first circuit coupled to the first surface of the ground plane;a second circuit coupled to the first surface of the ground plane adjacent to the first circuit;a first lead coupled to but electrically isolated from the ground plane, which is proximate to a first side of the package, wherein the first lead is electrically coupled to the first circuit;a second lead coupled to but electrically isolated from the ground plane, which is proximate to a second side of the package, wherein the second lead is electrically coupled to the first circuit;a third lead coupled to but electrically isolated from the ground plane, which is proximate to the first side of the package, wherein the third lead is electrically coupled to the second circuit;a fourth lead coupled to but electrically isolated from the ground plane, which is proximate to the second side of the package, wherein the fourth lead is electrically coupled to the second circuit; anda wire bond wall coupled to a region of the ground plane that is located ...

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Номер записи: 75
13-08-2020 дата публикации

MONOLITHIC MULTI-I REGION DIODE LIMITERS

Номер: US20200258883A1
Автор: Barter Margaret Mary, Boles Timothy Edward, Brogle James Joseph, Bukowski Joseph Gerard
Принадлежит:

A number of monolithic diode limiter semiconductor structures are described. The diode limiters can include a hybrid arrangement of diodes with different intrinsic regions, all formed over the same semiconductor substrate. In one example, two PIN diodes in a diode limiter semiconductor structure have different intrinsic region thicknesses. The first PIN diode has a thinner intrinsic region, and the second PIN diode has a thicker intrinsic region. This configuration allows for both the thin intrinsic region PIN diode and the thick intrinsic region PIN diode to be individually optimized. The thin intrinsic region PIN diode can be optimized for low level turn on and flat leakage, and the thick intrinsic region PIN diode can be optimized for low capacitance, good isolation, and high incident power levels. This configuration is not limited to two stage solutions, as additional stages can be used for higher incident power handling. 1. A monolithic diode limiter semiconductor structure , comprising:a first PIN diode comprising a first P-type region formed to a first depth into an intrinsic layer such the first PIN diode comprises a first effective intrinsic region of a first thickness;a second PIN diode comprising a second P-type region formed to a second depth into the intrinsic layer such the second PIN diode comprises a second effective intrinsic region of a second thickness; andat least one blocking capacitor and at least one inductor.2. The monolithic diode limiter semiconductor structure of claim 1 , wherein the first thickness is greater than the second thickness.3. The monolithic diode limiter semiconductor structure of claim 1 , wherein the at least one blocking capacitor and the at least one inductor are formed over the intrinsic layer as part of the monolithic diode limiter semiconductor structure.4. The monolithic diode limiter semiconductor structure of claim 1 , wherein:a cathode of the first PIN diode is electrically coupled to ground in the monolithic diode ...

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Номер записи: 76
13-08-2020 дата публикации

PACKAGE ARCHITECTURE WITH TUNABLE MAGNETIC PROPERTIES FOR EMBEDDED DEVICES

Номер: US20200258975A1
Автор: Grujicic Darko, NAD Suddhasattwa, PIETAMBARAM Srinivas, SHANMUGAM Rengarajan
Принадлежит:

Embodiments disclosed herein include electronic packages with embedded magnetic materials and methods of forming such packages. In an embodiment, the electronic package comprises a package substrate, where the package substrate comprises a plurality of dielectric layers. In an embodiment a plurality of passive components is located in a first dielectric layer of the plurality of dielectric layers. In an embodiment, first passive components of the plurality of passive components each comprise a first magnetic material, and second passive components of the plurality of passive components each comprise a second magnetic material. In an embodiment, a composition of the first magnetic material is different than a composition of the second magnetic material. 1. An electronic package , comprising:a package substrate, wherein the package substrate comprises a plurality of dielectric layers; anda plurality of passive components in a first dielectric layer of the plurality of dielectric layers, wherein first passive components of the plurality of passive components each comprise a first magnetic material, and wherein second passive components of the plurality of passive components each comprise a second magnetic material, wherein a composition of the first magnetic material is different than a composition of the second magnetic material.2. The electronic package of claim 1 , wherein the first passive components are included in a first circuitry block claim 1 , and wherein the second passive components are included in a second circuitry block.3. The electronic package of claim 2 , wherein the first circuitry block provides signal filtering claim 2 , RF shielding claim 2 , or power delivery claim 2 , and wherein the second circuitry block provides a different one of signal filtering claim 2 , RF shielding claim 2 , or power delivery.4. The electronic package of claim 2 , wherein the first magnetic material has a first permeability and the second magnetic material has a second ...

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Номер записи: 77
27-09-2018 дата публикации

DIFFERENTIAL INDUCTOR AND SEMICONDUCTOR DEVICE INCLUDING THE SAME

Номер: US20180277480A1
Автор: KANG Dongwoo, Koo Bon Tae
Принадлежит: Electronics and Telecommunications Research Institute

Provided are a differential inductor and a semiconductor device including the same, the differential inductor including first circular parts and second circular parts disposed on a first layer and composing a first spiral shape, a first semi-circular part disposed on the first layer and in the first circular part that is an innermost one of the first circular parts, and a second semi-circular part disposed outside the first circular part that is an outermost one of the first circular parts, third semi-circular parts and fourth semi-circular parts disposed on a second layer under the first layer and composing a second spiral shape, connection means configured to connect, to one, the first and second circular parts, and the first to fourth semi-circular parts, wherein the second circular parts are respectively interposed between the first circular parts, and a part of the fourth semi-circular parts is respectively interposed between the second semi-circular parts. 1. A differential inductor comprising:first circular parts and second circular parts disposed on a first layer and composing a first spiral shape;a first semi-circular part disposed on the first layer and in the first circular part that is an innermost one of the first circular parts, and a second semi-circular part disposed outside the first circular part that is an outermost one of the first circular parts;third semi-circular parts and fourth semi-circular parts disposed on a second layer under the first layer and composing a second spiral shape;connection means configured to connect, to one, the first and second circular parts, and the first to fourth semi-circular parts,wherein the second circular parts are respectively interposed between the first circular parts, anda part of the fourth semi-circular parts is respectively interposed between the second semi-circular parts.2. The differential inductor of claim 1 , further comprising:a first terminal line disposed on the first layer and connected to the ...

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Номер записи: 78
27-08-2020 дата публикации

CHANNEL LOSS COMPENSATION CIRCUITS

Номер: US20200274566A1
Автор: CHEN Huan-Neng, CHO Lan-Chou, JOU Chewn-PU, KUO Feng Wei, Shen William Wu
Принадлежит:

A circuit includes a transmitter, a transmission channel communicatively coupled with the transmitter, and a receiver communicatively coupled with the transmission channel. The circuit further includes a combiner on a transmitter-side of the transmission channel, a decoupler on a receiver-side of the transmission channel, and a channel loss compensation circuit communicatively coupled between the transmitter and the receiver. The combiner is coupled between the transmitter and the transmission channel. The decoupler is coupled between the receiver and the transmission channel. 1. A circuit , comprising:a transmitter associated with a carrier of a radio frequency interconnect;a transmission channel communicatively coupled with the transmitter;a receiver communicatively coupled with the transmission channel, the receiver being associated with the carrier of the radio frequency interconnect;a combiner on a transmitter-side of the transmission channel, the combiner being coupled between the transmitter and the transmission channel;a decoupler on a receiver-side of the transmission channel, the decoupler being coupled between the receiver and the transmission channel; anda channel loss compensation circuit communicatively coupled between the transmitter and the receiver.2. The circuit of claim 1 , wherein the channel loss compensation circuit is configured to apply a delay having a value based on the carrier.3. The circuit of claim 1 , wherein the channel loss compensation circuit is configured to apply a gain factor having a value based on the carrier.4. The circuit of claim 1 , wherein the channel loss compensation circuit is configured to apply a gain factor having a selectable value.5. The circuit of claim 1 , wherein the channel loss compensation circuit is configured to apply a gain factor having a value based on a channel loss of the transmission channel.6. The circuit of claim 5 , wherein the value based on the channel loss is a predetermined value based on ...

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Номер записи: 79
18-10-2018 дата публикации

INDUCTOR WITH INTEGRATED HEAT DISSIPATION STRUCTURES

Номер: US20180301269A1
Автор: SUNDARAM Arvind
Принадлежит:

Techniques and mechanisms for providing an inductor with integrated heat dissipation structures. In an embodiment, the inductor includes an electrical conductor and a ferromagnetic body, wherein a portion of the conductor extends through the ferromagnetic body. The conductor further includes other portions which extend from the ferromagnetic body, wherein the other portions each further form or couple to respective fin structures. In another embodiment, the inductor includes multiple distinct ferromagnetic bodies, where different portions of the conductor variously extend each through a respective one of the ferromagnetic bodies. 1. An inductor comprising: a first portion which forms a first one or more fin structures, wherein the first portion includes or couples to a first terminal by which the inductor is to couple to first circuitry;', 'a second portion which forms a second one or more fin structures, wherein the second portion includes or couples to a second terminal by which the inductor is to couple to second circuitry; and', 'a third portion disposed between the first portion and the second portion; and, 'a conductor includinga first ferromagnetic body disposed around the third portion.2. The inductor of claim 1 , wherein a volume fraction of ferromagnetic material of the first ferromagnetic body is equal to or less than ninety seven percent (97%).3. The inductor of claim 1 , wherein the first one or more fin structures includes a first plurality of fin structures claim 1 , and wherein the second one or more fin structures includes a second plurality of fin structures.4. The inductor of claim 1 , wherein the first one or more fin structures extend from a first side of a sub-portion of the first portion claim 1 , wherein the first terminal is disposed on a second side of the sub-portion claim 1 , the second side opposite the first side.5. The inductor of claim 1 , wherein the first one or more fin structures extend from a first side of a sub-portion of the ...

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Номер записи: 80
26-09-2019 дата публикации

Vertical Electrode Decoupling/Bypass Capacitor

Номер: US20190295771A1
Автор: Berolini Marianne, Horn Jeffrey A.
Принадлежит:

The invention is directed to a multilayer ceramic capacitor comprising a top surface and an opposing bottom surface and four side surfaces that extend between the top and bottom surfaces, a main body formed from a plurality of dielectric layers and a plurality of internal electrode layers alternately arranged, and external terminals electrically connected to the internal electrode layers wherein a first external terminal is disposed along the top surface and a second external terminal is disposed along the bottom surface. The internal electrode layer includes a first electrode electrically connected to the first external terminal and a second counter electrode electrically connected to the second external terminal, wherein the first electrode includes a central portion extending from the first external terminal toward the second external terminal and wherein the central portion extends 40% to less than 100% a distance from the first external terminal to the second external terminal. 1. A multilayer ceramic capacitor comprising:a top surface and an opposing bottom surface and four side surfaces that extend between the top surface and the bottom surface,a main body formed from a plurality of dielectric layers and a plurality of internal electrode layers alternately arranged,external terminals electrically connected to the internal electrode layers wherein a first external terminal is disposed along the top surface and a second external terminal is disposed along the bottom surface,wherein the internal electrode layer includes a first electrode electrically connected to the first external terminal and a second counter electrode electrically connected to the second external terminal, wherein the first electrode includes a central portion extending from the first external terminal toward the second external terminal and wherein the central portion extends 40% to less than 100% a distance from the first external terminal to the second external terminal.2. The multilayer ...

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Номер записи: 81
26-09-2019 дата публикации

MONOLITHIC MICROWAVE INTEGRATED CIRCUIT (MMIC) COOLING STRUCTURE

Номер: US20190295918A1
Автор: Gupta Anurag, Trulli Susan C.
Принадлежит: Raytheon Company

A Monolithic Integrated Circuit (MMIC) cooling structure having a heat spreader thermally comprising a anisotropic material, such material having anisotropic heat conducting properties for conducing heat therethrough along a preferred plane, a surface of the MMIC being thermally coupled to the heat spreader, the preferred plane intersecting the surface of the MMIC; and, a thermally conductive base having a side portion thermally coupled to the heat spreader, the side portion being disposed in a plane intersecting the preferred plane. 1. A cooling structure , comprising:a heat generating electric component;a heat spreader comprising thermally anisotropic material, such material having anisotropic heat conducting properties for conducing heat therethrough along preferred plane, a surface of the a heat generating electric component being thermally coupled to the heat spreader, the preferred plane intersecting the surface of the heat generating electric component; and,a thermally conductive base having a side portion thermally coupled to the heat spreader, the side portion being disposed in a plane intersecting the preferred plane.2. The cooling structure recited in including a second heat generating electric component claim 1 , a surface of the second heat generating electric component being thermally coupled to the heat spreader claim 1 , the preferred plane intersecting the second surface of the second heat generating electric component.3. The cooling structure recited in wherein the thermally anisotropic material is encapsulated within a thermally conductive material.4. The structure recited in wherein the thermally anisotropic material including a heat conducting bonding layer for bonding the thermally anisotropic material to a thermally conductive encapsulation material.5. The cooling structure recited in wherein the thermally anisotropic material is bonded to a thermally conductive encapsulation material using temperature and pressure.6. The cooling structure ...

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Номер записи: 82
24-09-2020 дата публикации

SEMICONDUCTOR PACKAGE

Номер: US20200303314A1
Автор: KANG Myung Sam, Kim Moon II, KO Young Gwan, Park Yong Jin
Принадлежит: SAMSUNG ELECTRONICS CO., LTD.

A semiconductor package includes a semiconductor chip having connection pads on one surface thereof, a first encapsulant covering at least portions of the semiconductor chip, and a connection structure disposed on the one surface of the semiconductor chip and including one or more redistribution layers electrically connected to the connection pads. A wiring structure is disposed on one surface of the first encapsulant opposing another surface of the first encapsulant facing towards the connection structure. The wiring structure has a passive component embedded therein, and includes one or more wiring layers electrically connected to the passive component. The one or more redistribution layers and the one or more wiring layers are electrically connected to each other. 1. A semiconductor package comprising:a semiconductor chip having connection pads on one surface thereof;a first encapsulant covering at least portions of the semiconductor chip;a connection structure disposed on the one surface of the semiconductor chip and including one or more redistribution layers electrically connected to the connection pads;a wiring structure disposed on one surface of the first encapsulant opposing another surface of the first encapsulant facing towards the connection structure, the wiring structure having a passive component embedded therein and including one or more wiring layers electrically connected to the passive component, andan electrical connection member electrically connected to the one or more redistribution layers and the one or more wiring layers, a second frame disposed on the first encapsulant, having a second through part, and including one or more core wiring layers, the passive component being disposed in the second through part,', 'a second encapsulant covering at least portions of each of the second frame and the passive component,', 'a backside wiring layer disposed on the second encapsulant,', 'first wiring vias electrically connecting the backside wiring ...

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Номер записи: 83
24-09-2020 дата публикации

POWER INTEGRATED MODULE

Номер: US20200303326A1
Автор: Chen Yan, LIANG Le, XIN Xiaoni, ZENG Jianhong
Принадлежит: DELTA ELECTRONICS (SHANGHAI) CO., LTD

A power integrated module, including at least one first bridge formed in a chip, wherein the first bridge includes: a first upper bridge switch, formed by a plurality of first sub switches formed in the chip connected in parallel, and including a first, a second and a control end; a first lower bridge switch, formed by a plurality of second sub switches formed in the chip connected in parallel, and including a first, a second and a control end; a first electrode, connected to the first end of the first upper bridge switch; a second electrode, connected to the second end of the first lower bridge switch; and a third electrode, connected to the second end of the first upper bridge switch and the first end of the first lower bridge switch, wherein the first, the second and the third electrode are bar-type electrodes arranged side by side. 1. A power integrated module , comprising at least one first bridge formed in a chip , wherein the first bridge comprises:a first upper bridge switch, comprising a first end, a second end and a control end;a first lower bridge switch, comprising a first end, a second end and a control end;a first electrode, electrically connected to the first end of the first upper bridge switch:a second electrode, electrically connected to the second end of the first lower bridge switch; anda third electrode, electrically connected to the second end of the first upper bridge switch and the first end of the first lower bridge switch,wherein the first electrode, the second electrode and the third electrode are bar-type electrodes located above the first upper bridge switch and the first lower bridge switch, andthe power integrated module further comprises at least one second bridge formed in the chip, and the second bridge comprises:a second upper bridge switch, comprising a first end, a second end and a control end;a second lower bridge switch, comprising a first end, a second end and a control end;a fourth electrode, electrically connected to the ...

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Номер записи: 84
03-10-2019 дата публикации

CAPACITOR DIE EMBEDDED IN PACKAGE SUBSTRATE FOR PROVIDING CAPACITANCE TO SURFACE MOUNTED DIE

Номер: US20190304935A1
Автор: Collins Andrew, Sharan Sujit, Xie Jianyong
Принадлежит:

A package substrate is disclosed. The package substrate includes a die package in the package substrate located at least partially underneath a location of a power delivery interface in a die that is coupled to the surface of the package substrate. Connection terminals are accessible on a surface of the die package to provide connection to the die that is coupled to the surface of the package substrate. Metal-insulator-metal layers inside the die package are coupled to the connection terminals. 1. A package substrate , comprising:a capacitor die embedded in the package substrate at least partially underneath a location of power delivery interface circuitry in a surface mounted die;connection terminals accessible at a surface of the die embedded in the package substrate to provide connection to the surface mounted die; andmetal-insulator-metal layers inside the die embedded in the package substrate coupled to the connection terminals.2. The package substrate of claim 1 , wherein the surface mount die comprises an integrated circuit die claim 1 , an FPGA or an ASIC.3. The package substrate of claim 1 , wherein the capacitor die is in front side build-up layers of the package substrate.4. The package substrate of claim 1 , wherein the capacitor die includes a straight and vertical wiring path to the surface mounted die.5. The package substrate of claim 1 , wherein the embedded MIM capacitor die supports at least two power domains.6. The package substrate of claim 1 , wherein the capacitor die occupies two or less levels of the package substrate.7. The package substrate of claim 1 , wherein the capacitor die is in a core of the package substrate.8. The package substrate of claim 1 , wherein the surface mounted die is surrounded by other surface mounted die that are coupled to the surface mounted die by EMIB connectors.9. A package substrate claim 1 , comprising:package interconnects;dielectric layers;metal layers; andan embedded capacitor die in the package substrate ...

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Номер записи: 85
01-11-2018 дата публикации

HIGH PERFORMANCE INTEGRATED RF PASSIVES USING DUAL LITHOGRAPHY PROCESS

Номер: US20180315690A1
Автор: Aleksov Aleksandar, Bharath Krishna, EID Feras, Elsherbini Adel A., Jiao Meizi, Kamgaing Telesphor, Lambert William J., Manusharow Mathew J., NAD Suddhasattwa, RAWLINGS Brandon M., Sankman Robert L., Soto Gonzalez Javier
Принадлежит:

Embodiments of the invention include an electrical package and methods of forming the package. In one embodiment, a transformer may be formed in the electrical package. The transformer may include a first conductive loop that is formed over a first dielectric layer. A thin dielectric spacer material may be used to separate the first conductive loop from a second conductive loop that is formed in the package. Additional embodiments of the invention include forming a capacitor formed in the electrical package. For example, the capacitor may include a first capacitor plate that is formed over a first dielectric layer. A thin dielectric spacer material may be used to separate the first capacitor plate form a second capacitor plate that is formed in the package. The thin dielectric spacer material in the transformer and capacitor allow for increased coupling factors and capacitance density in electrical components. 1. A transformer formed in an electrical package comprising:a first dielectric layer;a first conductive loop formed over a surface of the first dielectric layer;a dielectric spacer formed over the first conductive loop; anda second conductive loop separated from the first conductive loop by the dielectric spacer layer.2. The transformer of claim 1 , wherein the second conductive loop is formed above the first conductive loop.3. The transformer of claim 2 , wherein the first conductive loop and the second conductive loop are formed in a single routing layer of the electrical package.4. The transformer of claim 2 , wherein the dielectric spacer layer is former only over a top surface of the first conductive loop.5. The transformer of claim 1 , wherein the second conductive loop is formed over the first dielectric layer claim 1 , and wherein a sidewall surface of the first conductive loop is separated from a sidewall surface of the second conductive loop by the dielectric spacer.6. The transformer of claim 5 , wherein the dielectric spacer includes a cap layer ...

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Номер записи: 86
09-11-2017 дата публикации

CIRCUIT BOARD WITH MEASURE AGAINST HIGH FREQUENCY NOISE

Номер: US20170323861A1
Автор: ISHIWATA Yu
Принадлежит: MURATA MANUFACTURING CO., LTD.

A circuit board with a measure against high frequency noise includes: an interconnect substrate having an interconnect pattern to which an IC which is a source of high frequency noise is electrically connected; a pair of lands provided on a mounting surface of the interconnect substrate; and a chip component having a body composed of a magnetic body (i.e., ferrite) in a rectangular parallelepiped, and a pair of external electrodes provided at opposite ends of the body, the pair of external electrodes being connected to the pair of lands, the body being disposed on the interconnect pattern, as observed in a direction perpendicular to the mounting surface. 1. A circuit board with a measure against high frequency noise comprising:an interconnect substrate having an interconnect pattern to which an integrated circuit is electrically connected;a pair of lands provided on a mounting surface of the interconnect substrate; anda chip component having a body composed of a magnetic body in a rectangular parallelepiped, and a pair of external electrodes provided at opposite ends of the body,the pair of external electrodes being connected to the pair of lands,the body being disposed on the interconnect pattern, as observed in a direction perpendicular to the mounting surface.2. The circuit board with a measure against high frequency noise according to claim 1 , wherein the magnetic body is ferrite.3. The circuit board with a measure against high frequency noise according to claim 2 , wherein the ferrite is hexagonal ferrite.4. The circuit board with a measure against high frequency noise according to claim 1 , wherein:the interconnect pattern is provided on the mounting surface; andthe body is disposed at a location covering a portion of the interconnect pattern.5. The circuit board with a measure against high frequency noise according to claim 1 , wherein:the interconnect substrate is a multilayer interconnect substrate;the interconnect pattern is provided in an interior of the ...

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Номер записи: 87
09-11-2017 дата публикации

Multiple Band Multiple Mode Transceiver Front End Flip-Chip Architecture and Circuitry with Integrated Power Amplifiers

Номер: US20170324432A1
Автор: Gorbachov Oleksandr, Zhang Lisette L.
Принадлежит:

An integrated circuit architecture and circuitry is defined by a die structure with a plurality of exposed conductive pads arranged in a grid of rows and columns. The die structure has a first operating frequency region with a first transmit and receive chain, and a second operating frequency region with a second transmit chain and a second receive chain. There is a shared region of the die structure defined by an overlapping segment of the first operating frequency region and the second operating frequency region with a shared power supply input conductive pad connected to the first transmit chain, the second transmit chain, the first receive chain, and the second receive chain, and a shared power detection output conductive pad connected to the first transmit chain and the second transmit chain. 1. An integrated circuit architecture defined by a die structure with a plurality of exposed conductive pads arranged in a grid of rows and columns , the integrated circuit architecture comprising:a first operating frequency region of the die structure including a first transmit chain with at least one first operating frequency power amplifier and a first receive chain including at least one first operating frequency low noise amplifier;a second operating frequency region of the die structure including a second transmit chain with at least one second operating frequency power amplifier and a second receive chain including at least one second operating frequency low noise amplifier; anda shared region of the die structure defined by an overlapping segment of the first operating frequency region and the second operating frequency region, the shared region including at least one of a shared power input conductive pad connected to the first transmit chain, the second transmit chain, the first receive chain, and the second receive chain, and a shared power detection output conductive pad connected to the first transmit chain and the second transmit chain.2. The integrated ...

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Номер записи: 88
01-12-2016 дата публикации

Impedance matching configuration

Номер: US20160351513A1
Автор: Heeres Rob Mathijs, Van Der Zanden Josephus, Volokhine Iouri, ZHU Yi
Принадлежит:

A package is provided. The package comprises a die and an impedance matching network. The die has a first terminal and a second terminal. The impedance matching network is coupled to the second terminal and comprises a first inductor and a first capacitor. The first inductor comprises first bond wire connections coupled between the second terminal and a first bond pad on the die, and second bond wire connections coupled between the first bond pad and a second bond pad coupled to the first capacitor. 1. A package comprising:an integrated circuit die having a first terminal and a second terminal;a first package lead coupled to the first terminal;a second package lead coupled to the second terminal; andan impedance matching network coupled to the second terminal and comprising a first inductor and a first capacitor, wherein the first capacitor is an integrated capacitor arranged on the integrated circuit die;wherein the first inductor comprises first bond wire connections coupled between the second terminal and a first bond pad on the die, and second bond wire connections coupled between the first bond pad and a second bond pad coupled to the first capacitor;wherein the first bond wire connections and the second bond wire connections are adjacently arranged;wherein the first bond pad is arranged on the die in between the first package lead and the second terminal.2. The package of claim 1 , wherein the first bond wire connections and the second bond wire connections are configured such that during operation the instantaneous currents carried by these respective connections flow in opposite directions.3. The package of claim 1 , wherein the first and second bond wire connections are over the surface of the die.4. The package of claim 1 , wherein the first and second bond wire connections are orientated substantially along an axis defined by the first terminal and the second terminal.5. The package of claim 1 , wherein the first bond pad is disposed in a first bond pad ...

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Номер записи: 89
24-12-2015 дата публикации

METHOD OF DENSITY-CONTROLLED FLOORPLAN DESIGN FOR INTEGRATED CIRCUITS AND INTEGRATED CIRCUITS

Номер: US20150370946A1
Автор: CHANG Chih-Chiang, CHOU WEN-SHEN, Hsieh Chung-Peng, Peng Yung-Chow, Yang Chung-Chieh
Принадлежит:

A method of density-controlled floorplan design for integrated circuits having a plurality of blocks includes positioning decoupling capacitor (DCAP) cells at least partially around a pattern density sensitive block. The method also includes changing at least a portion of a pattern density insensitive block adjacent to the pattern density sensitive block according to at least one pattern density rule. 1. A method of density-controlled floorplan design for integrated circuits having a plurality of blocks , comprising:positioning decoupling capacitor (DCAP) cells at least partially around a pattern density sensitive block; andchanging at least a portion of a pattern density insensitive block adjacent to the pattern density sensitive block according to at least one pattern density rule.2. The method of wherein the portion of the pattern density insensitive block is repositioned closer to the pattern density sensitive block.3. The method of wherein pattern density of the portion of the pattern density insensitive block is changed.4. The method of wherein the portion of the pattern density insensitive block is repositioned closer to the pattern density sensitive block and pattern density of the portion of the pattern density insensitive block is changed.5. The method of wherein the at least one pattern density rule specifies one of a minimum claim 1 , a maximum or predetermined pattern density between the pattern density sensitive block and the pattern density insensitive block.6. The method of wherein the at least one pattern density rule specifies a maximum pattern density change per unit distance.7. The method of wherein the at least one pattern density rule specifies a maximum pattern density change per unit distance.8. A system having a processor configured to execute instructions to perform a method of density-controlled floorplan design for integrated circuits having a plurality of blocks claim 6 , comprising:positioning decoupling capacitor (DCAP) cells at least ...

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Номер записи: 90
19-11-2020 дата публикации

ELECTRONIC PACKAGE WITH ROTATED SEMICONDUCTOR DIE

Номер: US20200365515A1
Автор: HSU CHIH-JUNG, Lin Yi-Jou, PENG I-Hsuan, Su Yao-Chun
Принадлежит:

An electronic package configured to operate at Gigabit-per-second (Gbps) data rates is disclosed. The electronic package includes a package substrate of a rectangular shape. A chip package having a first high-speed interface circuit die is mounted on a top surface of the package substrate. The chip package is rotated relative to the package substrate above a vertical axis that is orthogonal to the top surface through about 45 degrees. The first high-speed interface circuit die includes a first Serializer/Deserializer (SerDes) circuit block. 1. An electronic package , comprising:a package substrate of a rectangular shape;a chip package comprising a first high-speed interface circuit die, mounted on a top surface of the package substrate, wherein the chip package is rotated relative to the package substrate above a vertical axis that is orthogonal to the top surface through a rotation offset angle; anda metal ring mounted on the top surface of the package substrate.2. The electronic package according to claim 1 , wherein the rotation offset angle is between 30 and 75 degrees.3. The electronic package according to claim 1 , wherein the rotation offset angle is about 45 degrees.4. The electronic package according to claim 1 , wherein the top surface of the package substrate is partitioned into four quadrants by two orthogonal axes in a two-dimensional plane.5. The electronic package according to claim 4 , wherein the first high-speed interface circuit die comprises a first edge directly facing a vertex of the package substrate claim 4 , wherein a first row of input/output (I/O) pads is disposed along the first edge.6. The electronic package according to claim 5 , wherein the first high-speed interface circuit die comprises a second edge that is perpendicular to the first edge claim 5 , wherein a second row of input/output (I/O) pads is disposed along the second edge.7. The electronic package according to claim 6 , wherein a first group of solder balls is arranged along ...

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Номер записи: 91
26-11-2020 дата публикации

Decoupling capacitance arrangements for integrated circuit devices

Номер: US20200373260A1
Автор: Gregory M. Daly, Rich Tat An, William Paul Hovis
Принадлежит: Microsoft Technology Licensing LLC

Integrated circuit device carriers and packaging assemblies which have attached decoupling capacitance are discussed herein. In one example, an assembly includes a package assembly comprising a carrier circuit board and an integrated circuit device coupled to a first side of the carrier circuit board. The assembly includes decoupling capacitors for the integrated circuit device are coupled to a second side of the carrier circuit board opposite from at least a portion of a footprint of the integrated circuit device on the carrier circuit board. A motherboard can be coupled to the package assembly and have at least one motherboard substrate layer facing the decoupling capacitors.

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Номер записи: 92
19-12-2019 дата публикации

ROTATED METAL-OXIDE-METAL (RTMOM) CAPACITOR

Номер: US20190385947A1
Автор: Bao Junjing, Li Xia, Tao Gengming, YANG Bin
Принадлежит:

A capacitor includes a first set of conductive fingers having a first conductive pitch at a first interconnect layer and arranged in a first unidirectional routing. The capacitor further includes a second set of conductive fingers having a second conductive pitch at a second interconnect layer and arranged in a second unidirectional routing that is orthogonal to the first unidirectional routing. The first conductive pitch is different from the second conductive pitch. A first set of through finger vias electrically couples the first set of conductive fingers of the first interconnect layer to the second set of conductive fingers of the second interconnect layer. A third set of conductive fingers at a third conductive layer are parallel to, but offset from, the first set of conductive fingers. A second set of through finger vias electrically couples the third set of conductive fingers to the second set of conductive fingers. 1. A capacitor , comprising:a first set of conductive fingers having a first conductive pitch at a first interconnect layer and arranged in a first unidirectional routing;a second set of conductive fingers having a second conductive pitch at a second interconnect layer and arranged in a second unidirectional routing that is orthogonal to the first unidirectional routing, the first conductive pitch different from the second conductive pitch;a first set of through finger vias electrically coupling the first set of conductive fingers of the first interconnect layer to the second set of conductive fingers of the second interconnect layer;a third set of conductive fingers at a third conductive layer, the third set of conductive fingers parallel to the first set of conductive fingers, but offset from the first set of conductive fingers; anda second set of through finger vias electrically couples the third set of conductive fingers to the second set of conductive fingers.2. The capacitor of claim 1 , in which the first set of conductive fingers is ...

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Номер записи: 93
26-12-2019 дата публикации

ULTRA-LOW PROFILE PACKAGE SHIELDING TECHNIQUE USING MAGNETIC AND CONDUCTIVE LAYERS FOR INTEGRATED SWITCHING VOLTAGE REGULATOR

Номер: US20190393165A1
Автор: Chen Chung-Hao J., Han Dong-Ho, Hsu Hao-Han, Lee Jaejin, Radhakrishnan Kaladhar
Принадлежит:

Semiconductor packages and a method of forming a semiconductor package are described. The semiconductor package has a foundation layer, a conductive layer formed in the foundation layer, and a magnetic layer formed between the conductive and the foundation layer. The conductive layer and the magnetic layer are coupled to form a low-profile inductor shield. The semiconductor package also has a dielectric layer formed between the magnetic and foundation layer. The foundation layer is mounted between a motherboard and a semiconductor die, where the foundation layer is attached to the motherboard with solder balls. Accordingly, the low-profile inductor shield may include a z-height that is less than a z-height of the solder balls. The low-profile inductor shield may have solder pads that are coupled to the conductive layer. The foundation layer may include at least one of voltage regulator and inductor, where the inductor is located above the low-profile inductor shield. 1. A semiconductor package , comprising:a foundation layer;a conductive layer formed in the foundation layer; anda magnetic layer formed between the conductive layer and the foundation layer, wherein the conductive layer and the magnetic layer are coupled to form a low-profile inductor shield.2. The semiconductor package of claim 1 , further comprising a dielectric layer formed between the magnetic layer and the foundation layer.3. The semiconductor package of claim 1 , wherein the low-profile inductor shield includes one or more solder pads that are coupled to the conductive layer.4. The semiconductor package of claim 1 , wherein the foundation layer further includes at least one of a voltage regulator and an inductor claim 1 , and wherein the inductor is located above the low-profile inductor shield.5. The semiconductor package of claim 1 , wherein the foundation layer further includes one or more vias and a ground via claim 1 , and wherein the conductive layer is coupled to the one or more vias and ...

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Номер записи: 94
26-12-2019 дата публикации

ON-CHIP POWER SUPPLY NOISE SUPPRESSION THROUGH HYPERABRUPT JUNCTION VARACTORS

Номер: US20190393360A1
Автор: Pathak Divya, Savidis Ioannis
Принадлежит: DREXEL UNIVERSITY

The increasing power density and, therefore, current consumption of high performance integrated circuits (ICs) results in increased challenges in the design of a reliable and efficient on-chip power delivery network. In particular, meeting the stringent on-chip impedance of the IC requires circuit and system techniques to mitigate high frequency noise that results due to resonance between the package inductance and the onchip capacitance. In this paper, a novel circuit technique is proposed to suppress high frequency noise through the use of a hyperabrupt junction tuning varactor diode as a decoupling capacitor for noise critical functional blocks. With the proposed circuit technique, the voltage droops and overshoots on the onchip power distribution network are suppressed by up to 60% as compared to MIM or deep trench decoupling capacitors of the same capacitance. In addition, there is no added latency to react to power supply noise and there is no degradation to circuit performance as compared to existing techniques in commercial products and literature. 1. A reverse biased P-N junction diode acting as a voltage-controlled capacitor , wherein an applied reverse bias voltage controls a thickness of a depletion region , which in turn determines a capacitance of the P-N junction.2. The reverse biased P-N junction of claim 1 , wherein the capacitance of the P-N junction is inversely proportional to the thickness of the depletion region.3. The reverse biased P-N junction diode of claim 1 , wherein the P-N junction diodes are manufactured with a controlled doping profile that enhances a variation of the junction capacitance with the applied reverse bias voltage.4. The reverse biased P-N junction diode of claim 1 , wherein the diodes are varactor diodes that includes a junction with a doped P-side.5. The reverse P-N junction diode of claim 1 , wherein variation in a doping concentration on an N-side of the P-N junction sets a capacitance range of the P-N junction diode ...

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Номер записи: 95
31-12-2020 дата публикации

THROUGH-BOARD POWER CONTROL ARRANGEMENTS FOR INTEGRATED CIRCUIT DEVICES

Номер: US20200411494A1
Автор: An Rich Tat, Blankenburg Garrett Douglas, Daly Gregory M., Hernandez Mojica Andres Felipe, Hovis William Paul
Принадлежит:

Power control and decoupling capacitance arrangements for integrated circuit devices are discussed herein. In one example, an assembly includes a first circuit assembly comprising a first circuit board coupled to an integrated circuit device, wherein the first circuit board is coupled to first surface of a system circuit board. The assembly also includes a second circuit assembly comprising a second circuit board having one or more voltage adjustment units configured to supply at least one input voltage to the integrated circuit device, wherein the second circuit board is coupled to a second surface of the system circuit board and positioned at least partially under a footprint of the integrated circuit device with respect to the system circuit board. 1. An assembly , comprising:a first circuit assembly comprising a first circuit board coupled to an integrated circuit device, wherein the first circuit board is coupled to first surface of a system circuit board; anda second circuit assembly comprising a second circuit board having one or more voltage adjustment units configured to supply at least one input voltage to the integrated circuit device, wherein the second circuit board is coupled to a second surface of the system circuit board and positioned at least partially under a footprint of the integrated circuit device with respect to the system circuit board.2. The assembly of claim 1 , comprising:the second circuit assembly comprising decoupling capacitance for the at least one input voltage of the integrated circuit device.3. The assembly of claim 2 , comprising:an integrated device coupled to the second circuit board and comprising:the one or more voltage adjustment units; andsemiconductor capacitance elements that provide the decoupling capacitance for the at least one supply voltage of the integrated circuit device.4. The assembly of claim 1 , wherein the one or more voltage adjustment units are configured to receive at least a supply voltage and convert the ...

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Номер записи: 96
31-12-2020 дата публикации

THROUGH-BOARD DECOUPLING CAPACITANCE ARRANGEMENTS FOR INTEGRATED CIRCUIT DEVICES

Номер: US20200411495A1
Автор: An Rich Tat, Blankenburg Garrett Douglas, Daly Gregory M., Hernandez Mojica Andres Felipe, Hovis William Paul
Принадлежит:

Decoupling capacitance arrangements for integrated circuit devices are discussed herein. In one example, an assembly includes a first circuit assembly comprising a first circuit board coupled to an integrated circuit device, where the first circuit board is coupled to first surface of a system circuit board. The assembly includes a second circuit assembly comprising a second circuit board having decoupling capacitance for the integrated circuit device, where the second circuit board is coupled to a second surface of the system circuit board and positioned at least partially under a footprint of the integrated circuit device with respect to the system circuit board. 1. An assembly , comprising:a first circuit assembly comprising a first circuit board coupled to an integrated circuit device, wherein the first circuit board is coupled to first surface of a system circuit board; anda second circuit assembly comprising a second circuit board having decoupling capacitance for the integrated circuit device, wherein the second circuit board is coupled to a second surface of the system circuit board and positioned at least partially under a footprint of the integrated circuit device with respect to the system circuit board.2. The assembly of claim 1 , comprising:the second circuit assembly comprising an integrated capacitance array coupled to the second circuit board and comprising semiconductor capacitance elements providing the decoupling capacitance for at least one supply voltage of the integrated circuit device.3. The assembly of claim 2 , wherein the integrated circuit device comprises a first minimum feature size claim 2 , and wherein the integrated capacitance array comprises a second minimum feature size larger than the first minimum feature size.4. The assembly of claim 1 , comprising:the second circuit assembly comprising a plurality of discrete capacitors coupled to the second circuit board providing the decoupling capacitance for at least one supply voltage of ...

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Номер записи: 97
31-12-2020 дата публикации

Semiconductor devices

Номер: US20200411507A1
Автор: Gunwoo Lee, Gwangmin Lee, Han-Kyung Kim, HyoJoon AN, Hyungwoo Yu, Jaewoo Yang, Sang-Min Noh, Seungkwon Lee
Принадлежит: SAMSUNG ELECTRONICS CO LTD

A semiconductor device includes a substrate that includes a first region and a second region; a switching transistor on the first region of the substrate, an interlayer dielectric layer that covers the switching transistor and is on the second region of the substrate, a cell contact that penetrates the interlayer dielectric layer on the first region of the substrate and is in contact with the switching transistor, and a first dummy contact, a second dummy contact, and a third dummy contact that penetrate the interlayer dielectric layer on the second region of the substrate in a vertical direction and adjacent to each other in a first horizontal direction. The first and second dummy contacts constitute opposing electrodes of a first decoupling capacitor. The second and third dummy contacts constitute opposing electrodes of a second decoupling capacitor. The first to third dummy contacts are electrically isolated from the substrate.

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Номер записи: 98
10-11-2022 дата публикации

Output-integrated transistor amplifier device packages incorporating internal connections

Номер: US20220360230A1
Автор: Basim Noori, Haedong Jang, Jeremy Fisher, Jonathan Chang, Marvin Marbell, Michael Lefevre, Qianli MU
Принадлежит: Cree Inc, Wolfspeed Inc

A semiconductor device package includes a plurality of input leads and an output lead, a plurality of transistor amplifier dies having inputs respectively coupled to the plurality of input leads, and a combination circuit configured to combine output signals received from the plurality of transistor amplifier dies and output a combined signal to the output lead.

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Номер записи: 99
17-11-2022 дата публикации

THREE DIMENSIONAL METAL INSULATOR METAL CAPACITOR STRUCTURE

Номер: US20220367608A1
Автор: Huang Yen-Chieh, Yeong Sai-Hooi, YU Chia-Ta
Принадлежит: Taiwan Semiconductor Manufacturing Co., Ltd.

The present disclosure relates to a semiconductor device and a manufacturing method, and more particularly to a 3D metal insulator metal (MIM) capacitor structure with an increased capacitance per unit area in a semiconductor structure. The MIM structure includes a substrate, an oxide layer formed over the substrate, and a first metal layer formed over the oxide layer. The first metal layer includes a plurality of mandrels formed on a surface of the first metal layer. The MIM structure also includes a dielectric layer formed over the first metal layer and the plurality of mandrels, a second metal layer formed over on the dielectric layer, and one or more interconnect structures electrically connected to the first and second metal layers.

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Номер записи: 100