Method for Aligning Micro-Electronic Components

Alignment of a first micro-electronic component to a receiving surface of a second micro-electronic component is realized by a capillary force-induced self-alignment, combined with an electrostatic alignment. The latter is accomplished by providing at least one first electrical conductor line along the periphery of the first component, and at least one second electrical conductor along the periphery of the location on the receiving surface of the second component onto which the component is to be placed. The contact areas surrounded by the conductor lines are covered with a wetting layer. The electrical conductor lines may be embedded in a strip of anti-wetting material that runs along the peripheries to create a wettability contrast. The wettability contrast helps to maintain a drop of alignment liquid between the contact areas so as to obtain self-alignment by capillary force. By applying appropriate charges on the conductor lines, electrostatic self-alignment is realized, which improves ...

Chip package and manufacturing method thereof

EMIB 칩 상호접속을 위한 방법 및 프로세스

... 집적 회로(IC)를 IC 패키지 기판에 부착하기 위한 방법은, IC 다이의 본드 패드 상에 솔더 범프를 형성하는 단계와, IC 패키지 기판의 본드 패드 상에 솔더 웨이팅 돌출부를 형성하는 단계와, IC 패키지 기판의 솔더 웨이팅 돌출부에 IC 다이의 솔더 범프를 본딩하는 단계를 포함한다.

반도체 패키지

... 반도체 패키지를 제공한다. 반도체 패키지는, 기판 패드를 포함하는 회로 기판, 회로 기판과 마주하며 이격되어 배치되며, 칩 패드를 포함하는 반도체 칩 및 회로 기판 및 반도체 칩을 전기적으로 연결하는 연결 패턴을 포함한다. 반도체 칩은, 상기 반도체 칩 내에, 반도체 칩의 상면에 대하여 수직하게 배치되는 다수의 제1 회로 패턴들과, 칩 패드 및 제1 회로 패턴들을 전기적으로 연결하는 제1 비아를 포함한다. 칩 패드는, 연결 패턴이 접촉되는 제1 영역 및 제1 영역의 외각의 제2 영역을 포함하되, 제1 비아는 상기 제2 영역에 연결된다.

CMOS SENSORS AND METHODS OF FORMING THE SAME

CMOS sensors and methods of forming the same are disclosed. The CMOS sensor includes a semiconductor substrate, a plurality of dielectric patterns, a first conductive element and a second conductive element. The semiconductor substrate has a pixel region and a circuit region. The dielectric patterns are disposed between the first portion and the second portion, wherein top surfaces of the plurality of dielectric patterns are lower than top surfaces of the first and second portions. The first conductive element is disposed below the plurality of dielectric patterns. The second conductive element inserts between the plurality of dielectric patterns to electrically connect the first conductive element. 1. A CMOS sensor , comprising:a semiconductor substrate having a pixel region and a circuit region, comprising a first portion and a second portion separately disposed in the circuit region;a plurality of dielectric patterns between the first portion and the second portion, wherein top surfaces of the plurality of dielectric patterns are lower than top surfaces of the first and second portions;a first conductive element, disposed below the plurality of dielectric patterns; anda second conductive element, inserting between the plurality of dielectric patterns to electrically connect the first conductive element.2. The CMOS sensor of claim 1 , wherein the first portion and the second portion surround the plurality of dielectric patterns and the second conductive element.3. The CMOS sensor of claim 1 , wherein a top surface of the second conductive element is lower than the top surfaces of the first and second portions.4. The CMOS sensor of claim 1 , wherein the second conductive element covers a portion of the top surfaces of the plurality of dielectric patterns and inserts into gaps between the plurality of dielectric patterns.5. The CMOS sensor of claim 1 , further comprising a dummy pattern between the plurality of dielectric patterns and the first portion and between ...

PACKAGING DEVICES AND METHODS OF MANUFACTURE THEREOF

SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME

The present disclosure provides a semiconductor device. The semiconductor device includes a first die and a conductive layer. The first die is to be bonded with, in a direction, a second die external to the semiconductor device. The conductive layer, between the first die and the second die in the direction, has a reference ground.

Concentric bump design for the alignment in die stacking

An integrated circuit structure includes an alignment bump and an active electrical connector. The alignment bump includes a first non-solder metallic bump. The first non-solder metallic bump forms a ring encircling an opening therein. The active electrical connector includes a second non-solder metallic bump. A surface of the first non-solder metallic bump and a surface of the second non-solder metallic bump are substantially coplanar with each other.

METHOD AND PROCESS FOR EMIB CHIP INTERCONNECTIONS

A method for attaching an integrated circuit (IC) to an IC package substrate includes forming a solder bump on a bond pad of an IC die, forming a solder-wetting protrusion on a bond pad of an IC package substrate, and bonding the solder bump of the IC die to the solder-wetting protrusion of the IC package substrate. 125-. (canceled)26. A method for attaching an integrated circuit (IC) to an IC package substrate , the method comprising:forming a solder bump on a bond pad of an IC die;forming a solder-wetting protrusion on a bond pad of an IC package substrate; andbonding the solder bump of the IC die to the solder-wetting protrusion of the IC package substrate.27. The method of claim 26 , wherein forming a solder-wetting protrusion on the bond pad of the IC package substrate includes laser direct deposition of the solder-wetting protrusion onto the bond pad of the IC package substrate.28. The method of claim 27 , wherein laser direct deposition of the solder-wetting protrusion includes:arranging a film of solder-wetting material opposite the bond pad of the IC package substrate; andapplying laser energy to the film of solder-wetting material to transfer the solder-wetting material to the bond pad of the IC package substrate.29. The method of claim 27 , wherein laser direct deposition of the solder-wetting protrusion includes:arranging, opposite the bond pad of the IC package substrate, a film having solder-wetting material on one side and a transparent material on the other side, and applying laser energy to the transparent side of the film.30. The method of claim 28 , wherein arranging a film of solder-wetting material includes arranging the film of solder-wetting material opposite a plurality of bond pads of one or more IC package substrates claim 28 , and wherein applying laser energy includes scanning a laser energy source to positions on the film of solder-wetting material opposite the plurality of bond pads and applying pulses of laser energy to the film of ...

REDUCED PARASITIC CAPACITANCE IN BONDED STRUCTURES

Bonded structures having conductive features and isolation features are disclosed. In one example, a bonded structure can include a first element including a first insulating layer and at least two first conductive features disposed in the first insulating layer. The bonded structure can also include a second element including a second insulating layer and at least two second conductive features disposed in the second insulating substrate. The first element can be directly bonded to the second element with the at least two first conductive features aligned with the at least two second conductive features. The bonded structure can also include an isolation feature in the second insulating layer and between the at least two second conductive features. The isolation feature can have a dielectric constant lower than a dielectric constant of the second insulating layer.

Packaging devices and methods of manufacture thereof

Packaging devices and methods of manufacture thereof for semiconductor devices are disclosed. In some embodiments, a packaging device includes a contact pad disposed over a substrate, and a passivation layer disposed over the substrate and a first portion of the contact pad. A second portion of the contact pad is exposed. A post passivation interconnect (PPI) line is disposed over the passivation layer and is coupled to the second portion of the contact pad. A PPI pad is disposed over the passivation layer. A transition element is disposed over the passivation layer and is coupled between the PPI line and the PPI pad. The transition element includes a hollow region.

SEMICONDUCTOR DEVICE

A semiconductor device includes a single-layered dielectric layer, a conductive line, a conductive via and a conductive pad. The conductive line and the conductive via are disposed in the single-layered dielectric layer. The conductive pad is extended into the single-layered dielectric layer to electrically connected to the conductive line.

Concentric Bump Design for the Alignment in Die Stacking

An integrated circuit structure includes an alignment bump and an active electrical connector. The alignment bump includes a first non-solder metallic bump. The first non-solder metallic bump forms a ring encircling an opening therein. The active electrical connector includes a second non-solder metallic bump. A surface of the first non-solder metallic bump and a surface of the second non-solder metallic bump are substantially coplanar with each other. 1. A method comprising:forming an Under-Bump Metallurgy (UBM) layer;forming a first non-solder metallic bump over the UBM layer, wherein the first non-solder metallic bump is a solid bump;forming a second non-solder metallic bump over the UBM layer, wherein the second non-solder metallic bump forms a ring with an opening therein;forming a first solder region overlapping the first non-solder metallic bump;forming a second solder region overlapping the second non-solder metallic bump, wherein the second solder region encircles the opening;removing portions of the UBM layer misaligned from the first non-solder metallic bump and the second non-solder metallic bump; andreflowing the first solder region and the second solder region to form a first solder region and a second solder region, respectively.2. The method of claim 1 , wherein the first non-solder metallic bump claim 1 , the second non-solder metallic bump claim 1 , the first solder region claim 1 , and the the second solder region are formed using a same mask layer.3. The method of claim 1 , wherein after the reflowing claim 1 , the first solder region has a first rounded top surface claim 1 , the second solder region has a second rounded top surface claim 1 , and wherein the first rounded top surface has a first top end lower than a second top end of the second rounded top surface.4. The method of further comprising:placing a second package component, wherein a first electrical connector of the second package component is placed overlying and in contact with the ...

SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING SAME

A semiconductor package includes; a first semiconductor chip and a second semiconductor chip stacked on the first semiconductor chip. The first semiconductor chip includes; a first substrate, a first bonding pad on a first surface of the first substrate, and a first passivation layer on the first surface of the first substrate exposing at least a portion of the first bonding pad. The second semiconductor chip includes; a second substrate, a second insulation layer on a front surface of the second substrate, a second bonding pad on the second insulation layer, a first alignment key pattern on the second insulation layer, and a second passivation layer on the second insulation layer, covering at least a portion of the first alignment key pattern, and exposing at least a portion of the second bonding pad, wherein the first bonding pad and the second bonding pad are directly bonded, and the first passivation layer and the second passivation layer are directly bonded.

CMOS sensors and methods of forming the same

CMOS sensors and methods of forming the same are disclosed. The CMOS sensor includes a semiconductor substrate, a dielectric layer, an interconnect, a bonding pad and a dummy pattern. The semiconductor substrate has a pixel region and a circuit region. The dielectric layer is surrounded by the semiconductor substrate in the circuit region. The interconnect is disposed over the dielectric layer in the circuit region. The bonding pad is disposed in the dielectric layer and electrically connects the interconnect in the circuit region. The dummy pattern is disposed in the dielectric layer and surrounds the bonding pad in the circuit region.

CMOS SENSORS AND METHODS OF FORMING THE SAME

PACKAGING DEVICES AND METHODS OF MANUFACTURE THEREOF

SEMICONDUCTOR STRUCTURE AND METHOD FOR PREPARING SAME

A semiconductor structure includes: a substrate, a conductive pattern layer, a support layer and a re-distribution layer. The conductive pattern layer is arranged on the substrate. The support layer covers the conductive pattern layer and is provided with a via hole. The re-distribution layer is arranged on the support, and the re-distribution layer includes a test pad at least located in the via hole. The test pad includes a plurality of test contact portions and a plurality of recesses that are arranged alternately and connected mutually, and the recess is in corresponding contact with a portion of the conductive pattern layer in the via hole.

Packaging devices and methods of manufacture thereof

Packaging devices and methods of manufacture thereof for semiconductor devices are disclosed. In some embodiments, a packaging device includes a contact pad disposed over a substrate, and a passivation layer disposed over the substrate and a first portion of the contact pad. A second portion of the contact pad is exposed. A post passivation interconnect (PPI) line is disposed over the passivation layer and is coupled to the second portion of the contact pad. A PPI pad is disposed over the passivation layer. A transition element is disposed over the passivation layer and is coupled between the PPI line and the PPI pad. The transition element includes a hollow region.

Packaging Devices and Methods of Manufacture Thereof

Packaging devices and methods of manufacture thereof for semiconductor devices are disclosed. In some embodiments, a packaging device includes a contact pad disposed over a substrate, and a passivation layer disposed over the substrate and a first portion of the contact pad, a second portion of the contact pad being exposed. A post passivation interconnect (PPI) line is disposed over the passivation layer and is coupled to the second portion of the contact pad. A PPI pad is disposed over the passivation layer and is coupled to the PPI line. An insulating material is disposed over the PPI line, the PPI pad being exposed. The insulating material is spaced apart from an edge portion of the PPI pad by a predetermined distance.

Packaging Devices and Methods of Manufacture Thereof

Packaging devices and methods of manufacture thereof for semiconductor devices are disclosed. In some embodiments, a packaging device includes a contact pad disposed over a substrate, and a passivation layer disposed over the substrate and a first portion of the contact pad. A post passivation interconnect (PPI) line is disposed over the passivation layer and is coupled to a second portion of the contact pad. A PPI pad is disposed over the passivation layer. A transition element is disposed over the passivation layer and is coupled between the PPI line and the PPI pad. The transition element comprises a first side and a second side coupled to the first side. The first side and the second side of the transition element are non-tangential to the PPI pad. 1. A method of manufacturing a packaging device , the method comprising:forming a plurality of contact pads over a substrate;forming a passivation layer over the substrate and the plurality of contact pads;etching an opening in the passivation layer to expose a first portion of each of the plurality of contact pads, wherein after the etching, a second portion of each of the plurality of contact pads remains covered by the passivation layer;forming a plurality of post passivation interconnect (PPI) lines over the passivation layer, a respective one of the plurality of PPI lines being coupled to the first portion of a respective one of the plurality of contact pads;forming a plurality of a PPI pads over the passivation layer, a respective one of the plurality of PPI pads being coupled to a respective one of the plurality of PPI lines, the plurality of PPI pads being arranged in an array; andforming a plurality of transition elements disposed over the passivation layer wherein each of the transition elements comprises a first side and a second side coupled to the first side, wherein the first sides and the second sides of the transition elements are non-tangential to the plurality of PPI pads, and wherein respective ones ...

Packaging devices and methods of manufacture thereof

Packaging devices and methods of manufacture thereof for semiconductor devices are disclosed. In some embodiments, a packaging device includes a contact pad disposed over a substrate, and a passivation layer disposed over the substrate and a first portion of the contact pad, a second portion of the contact pad being exposed. A post passivation interconnect (PPI) line is disposed over the passivation layer and is coupled to the second portion of the contact pad. A PPI pad is disposed over the passivation layer and is coupled to the PPI line. An insulating material is disposed over the PPI line, the PPI pad being exposed. The insulating material is spaced apart from an edge portion of the PPI pad by a predetermined distance.

Semiconductor Package

EMIB 칩 상호접속을 위한 방법, 전자 어셈블리 및 장치

... 집적 회로(IC)를 IC 패키지 기판에 부착하기 위한 방법은, IC 다이의 본드 패드 상에 솔더 범프를 형성하는 단계와, IC 패키지 기판의 본드 패드 상에 솔더 웨이팅 돌출부를 형성하는 단계와, IC 패키지 기판의 솔더 웨이팅 돌출부에 IC 다이의 솔더 범프를 본딩하는 단계를 포함한다.

Packaging devices

Packaging Devices and Methods of Manufacture Thereof

Packaging devices and methods of manufacture thereof for semiconductor devices are disclosed. In some embodiments, a packaging device includes a contact pad disposed over a substrate, and a passivation layer disposed over the substrate and a first portion of the contact pad. A second portion of the contact pad is exposed. A post passivation interconnect (PPI) line is disposed over the passivation layer and is coupled to the second portion of the contact pad. A PPI pad is disposed over the passivation layer. A transition element is disposed over the passivation layer and is coupled between the PPI line and the PPI pad. The transition element includes a hollow region.

Method for aligning micro-electronic components

Alignment of a first micro-electronic component to a receiving surface of a second micro-electronic component is realized by a capillary force-induced self-alignment, combined with an electrostatic alignment. The latter is accomplished by providing at least one first electrical conductor line along the periphery of the first component, and at least one second electrical conductor along the periphery of the location on the receiving surface of the second component onto which the component is to be placed. The contact areas surrounded by the conductor lines are covered with a wetting layer. The electrical conductor lines may be embedded in a strip of anti-wetting material that runs along the peripheries to create a wettability contrast. The wettability contrast helps to maintain a drop of alignment liquid between the contact areas so as to obtain self-alignment by capillary force. By applying appropriate charges on the conductor lines, electrostatic self-alignment is realized, which improves ...

Method and process for EMIB-chip interconnect

Stress Relieving Structure for Semiconductor Device

A semiconductor device includes a semiconductor body, a stress relieving layer or layer stack disposed over at least part of the semiconductor body, the stress relieving layer or layer stack comprising a plurality of openings which yield a patterned surface topography for the stress relieving layer or layer stack, and a metal layer or layer stack formed on the stress relieving layer or layer stack and occupying the plurality of openings in the stress relieving layer or layer stack. The patterned surface topography of the stress relieving layer or layer stack is transferred to a surface of the metal layer or layer stack facing away from the semiconductor body. The stress relieving layer or layer stack has a different elastic modulus than the metal layer or layer stack over a temperature range.

Chip package and manufacturing method thereof

A chip package includes a substrate, an isolation layer, a redistribution layer, a passivation layer, a first conductive layer, a second conductive layer, and a conductive structure. The isolation layer is located on the substrate. The redistribution layer is located on the isolation layer. The passivation layer is located on the isolation layer and the redistribution layer. The passivation layer has an opening, a wall surface that surrounds the opening, and a surface that faces away from the isolation layer. A portion of the redistribution layer is exposed through the opening. The first conductive layer is located on the redistribution layer that is in the opening, and extends to the wall surface and the surface of the passivation layer. The second conductive layer covers the first conductive layer. The conductive structure is located on the second conductive layer and protrudes from the passivation layer.

Electronic component, electronic apparatus, and method of manufacturing electronic apparatus

An electronic component includes a substrate configured to include a first portion that first thermal conductivity, and have a first surface and a second surface opposite to the first surface; a second portion configured to be formed inside the first portion, and have second thermal conductivity lower than the first thermal conductivity; a first terminal configured to be formed to correspond to the second portion on a side of the first surface; and a second terminal configured to be formed on a side of the second surface.

Concentric bump design for the alignment in die stacking

An integrated circuit structure includes an alignment bump and an active electrical connector. The alignment bump includes a first non-solder metallic bump. The first non-solder metallic bump forms a ring encircling an opening therein. The active electrical connector includes a second non-solder metallic bump. A surface of the first non-solder metallic bump and a surface of the second non-solder metallic bump are substantially coplanar with each other.

Stress Relieving Structure for Semiconductor Device

A semiconductor device includes a semiconductor body, a stress relieving layer or layer stack disposed over at least part of the semiconductor body, the stress relieving layer or layer stack comprising a plurality of openings which yield a patterned surface topography for the stress relieving layer or layer stack, and a metal layer or layer stack formed on the stress relieving layer or layer stack and occupying the plurality of openings in the stress relieving layer or layer stack. The patterned surface topography of the stress relieving layer or layer stack is transferred to a surface of the metal layer or layer stack facing away from the semiconductor body. The stress relieving layer or layer stack has a different elastic modulus than the metal layer or layer stack over a temperature range. 1. A semiconductor device , comprising:a semiconductor body;a stress relieving layer or layer stack disposed over at least part of the semiconductor body, the stress relieving layer or layer stack comprising a plurality of openings which yield a patterned surface topography for the stress relieving layer or layer stack; anda metal layer or layer stack formed on the stress relieving layer or layer stack and occupying the plurality of openings in the stress relieving layer or layer stack,wherein the patterned surface topography of the stress relieving layer or layer stack is transferred to a surface of the metal layer or layer stack facing away from the semiconductor body,wherein the stress relieving layer or layer stack has a different elastic modulus than the metal layer or layer stack over a temperature range.2. The semiconductor device of claim 1 , wherein the stress relieving layer or layer stack comprises a material selected from the group consisting of a polymer claim 1 , an imide claim 1 , an alloy of aluminum and copper claim 1 , an oxide claim 1 , a nitride claim 1 , silicon nitride claim 1 , oxynitride claim 1 , a nitride-based ceramic claim 1 , and SiCOH.3. The ...

Semiconductor device and manufacturing method thereof

A semiconductor device has a mounting structure in which the top surface of a semiconductor chip (1) is electrically connected to an electroconductive member (4) via a deformation-absorbing layer (2a) and a bonding layer (3a), and the bottom surface is electrically connected to an electroconductive member (5) via a deformation-absorbing layer (2b) and a bonding layer (3b). The deformation-absorbing layers (2a, 2b) are each configured from a nanostructure layer (7) disposed in the middle of the thickness direction, and two plate layers (6, 8) on either side of the nanostructure layer (7). The nanostructure layer (7) has a structure in which a plurality of nanostructure bodies (9) 1 [mu]m or less in size are arranged in a planar configuration, and heat stress caused by the differences in heat deformation between the different members constituting the semiconductor device is absorbed by the deformation of the nanostructure bodies (9).

METHOD AND PROCESS FOR EMIB CHIP INTERCONNECTIONS

Semiconductor package

Provided is a semiconductor package including a circuit substrate including a substrate pad, a semiconductor chip spaced apart from and facing the circuit substrate, the semiconductor chip including a chip pad, and a connection pattern electrically connecting the circuit substrate with the semiconductor chip. The semiconductor chip may include a plurality of first circuit patterns extending substantially perpendicular toward a top surface of the semiconductor chip and at least one first via electrically connecting the chip pad to the first circuit patterns. The chip pad may include a first region in contact with the connection pattern and a second region outside the first region, and the first via may be connected to the second region of the chip pad.

BONDING PAD STRUCTURE, SEMICONDUCTOR STRUCTURE, SEMICONDUCTOR PACKAGE STRUCTURE AND METHOD FOR PREPARING SAME

A bonding pad structure includes a bonding pad layer, and an expansion stagnating block that is at least wrapped by the bonding pad layer partially. The expansion stagnating block is subjected to high-temperature tempering treatment. A semiconductor structure, a semiconductor package structure and a method for preparing the same are also provided. 1. A bonding pad structure , comprising a bonding pad layer , and an expansion stagnating block that is at least wrapped by the bonding pad layer partially , the expansion stagnating block being subjected to A high-temperature tempering treatment.2. The bonding pad structure of claim 1 , wherein an isolation layer is arranged between the bonding pad layer and the expansion stagnating block.3. The bonding pad structure of claim 1 , wherein the bonding pad layer comprises a bonding pad top layer and a bonding pad bottom layer that are arranged in a stacked manner claim 1 , the bonding pad top layer is arranged on a side of a bonding pad close to a bonding surface claim 1 , the bonding pad bottom layer and the bonding pad top layer are integrated as a whole claim 1 , and projection of the bonding pad bottom layer on the bonding surface is positioned in projection of the bonding pad top layer on the bonding surface.4. The bonding pad structure of claim 3 , wherein an area of an end of the bonding pad layer close to the bonding surface is greater than an area of an end of the bonding pad layer far away from the bonding surface.5. The bonding pad structure of claim 1 , wherein the bonding pad layer is a metal block.6. A semiconductor package structure comprising a semiconductor substrate provided with the bonding pad structure of .7. The semiconductor package structure of claim 6 , wherein the semiconductor substrate comprises a substrate layer far away from a bonding surface claim 6 , and a dielectric layer and a dielectric surface layer that are arranged on the substrate layer sequentially claim 6 , the bonding pad structure ...

For aligning a microelectronic assembly

Electronic component, electronic apparatus, and method of manufacturing electronic apparatus

Semiconductor Device and Manufacturing Method Thereof

A semiconductor device has a packaging structure in which a top surface of a semiconductor chip 1 is electrically connected to a conductive member 4 through a deformation absorption layer 2a and a joining layer 3a and a bottom surface thereof is electrically connected to a conductive member 5 through a deformation absorption layer 2b and a joining layer 3b. Each of the deformation absorption layers 2a and 2b includes a nano-structure layer 7 arranged at a center of a thickness direction and plate layers 6 and 8 of two layers with the nano-structure layer 7 therebetween. The nano-structure layer 7 has a structure in which a plurality of nano-structures 9 having a size of 1 m or less are two-dimensionally arranged and thermal stress due to a thermal deformation difference of each member forming the semiconductor device is absorbed by deformation of the nano-structures 9.

Semiconductor device

A semiconductor device includes a substrate, a dielectric layer, a plurality of dielectric patterns and a conductive pad. The substrate includes a first surface and a second surface opposite to the first surface. The dielectric layer is disposed at the first surface of the substrate, and the substrate is disposed between the dielectric layer and the second surface of the substrate. The dielectric patterns are disposed on the dielectric layer and between the first surface and the second surface of the substrate. The conductive pad is inserted between the plurality of dielectric patterns and extended into the dielectric layer.

SEMICONDUCTOR DEVICE

A semiconductor device includes a substrate, a dielectric layer, a plurality of dielectric patterns and a conductive pad. The substrate includes a first surface and a second surface opposite to the first surface. The dielectric layer is disposed at the first surface of the substrate, and the substrate is disposed between the dielectric layer and the second surface of the substrate. The dielectric patterns are disposed on the dielectric layer and between the first surface and the second surface of the substrate. The conductive pad is inserted between the plurality of dielectric patterns and extended into the dielectric layer. 1. A semiconductor device , comprising:a substrate comprising a first surface and a second surface opposite to the first surface;a dielectric layer at the first surface of the substrate, the substrate being disposed between the dielectric layer and the second surface of the substrate;{'b': ['116', '132', '110', '110', '110'], 'i': ['a', 'b'], '#text': 'a plurality of dielectric patterns () on the dielectric layer () and between the first surface () and the second surface () of the substrate (); and'}{'b': ['152', '116', '132'], '#text': 'a conductive pad (), inserted between the plurality of dielectric patterns () and extended into the dielectric layer ().'}2. The semiconductor device of claim 1 , wherein an interface between the dielectric layer and the plurality of dielectric patterns is substantially coplanar with the first surface of the substrate.3. The semiconductor device of claim 1 , wherein the plurality of dielectric patterns are separated from the substrate by a lateral distance.4. The semiconductor device of claim 1 , wherein the substrate comprises a first portion and a second portion separated from each other claim 1 , and the plurality of dielectric patterns are disposed between the first portion and the second portion.5. The semiconductor device of further comprising a dummy pattern between the plurality of dielectric patterns ...

SEMICONDUCTOR PACKAGES

A semiconductor package includes a plurality of semiconductor chips. At least one of the semiconductor chips includes a semiconductor substrate including a semiconductor layer and a passivation layer having a third surface, a backside pad on the third surface, and a through-via penetrating through the semiconductor substrate. The backside pad includes an electrode pad portion, on the third surface, and a dam structure protruding on one side of the electrode pad portion and surrounding a side surface of the through-via. The dam structure is spaced apart from the side surface of the through-via. 1. A semiconductor package comprising:a plurality of semiconductor chips electrically connected to each other and stacked in a first direction, a semiconductor substrate including a semiconductor layer having a first surface and a second surface that are opposite each other;', 'a passivation layer on the first surface and having a third surface that is opposite the first surface;', 'a circuit structure on the second surface;', 'a frontside pad on the circuit structure;', 'a backside pad on the third surface; and', 'a through-via in the semiconductor substrate and extending between the second surface and the third surface to be electrically connected to the backside pad and the frontside pad,, 'wherein at least one of the plurality of semiconductor chips includeswherein the backside pad includes an electrode pad portion, on the third surface, and a dam structure protruding toward the first surface on one side of the electrode pad portion and surrounding a side surface of the through-via, andwherein the dam structure is spaced apart from the side surface of the through-via.2. The semiconductor package of claim 1 ,wherein the dam structure penetrates the third surface of the passivation layer,wherein a ratio of a height of the dam structure in the first direction to a maximum thickness of the passivation layer is within a range of about 0.5:1 to about 0.8:1,wherein the through- ...

Packaging devices and methods of manufacture thereof

Packaging devices and methods of manufacture thereof for semiconductor devices are disclosed. In some embodiments, a packaging device includes a contact pad disposed over a substrate, and a passivation layer disposed over the substrate and a first portion of the contact pad. A post passivation interconnect (PPI) line is disposed over the passivation layer and is coupled to a second portion of the contact pad. A PPI pad is disposed over the passivation layer. A transition element is disposed over the passivation layer and is coupled between the PPI line and the PPI pad. The transition element comprises a first side and a second side coupled to the first side. The first side and the second side of the transition element are non-tangential to the PPI pad.

Semiconductor device with stress relief structure

WAFER LEVEL PACKAGE WITH POLYMER LAYER DELAMINATION PREVENTION DESIGN AND METHOD OF FORMING THE SAME

A package structure is provided, including a substrate, a first passivation layer, a metallization layer, a second passivation layer, and a polymer layer. The first passivation layer is formed over the substrate. The metallization layer is conformally formed on the first passivation layer. The second passivation layer is conformally formed on the first passivation layer and the metallization layer. A step structure is formed on the top surface of the second passivation layer, and includes at least one lower part that is lower than the other parts of the step structure. The polymer layer is formed over the second passivation layer. A portion of the polymer layer extends into the lower part of the step structure to engage with the step structure.

ELECTRONIC COMPONENT, ELECTRONIC APPARATUS, AND METHOD OF MANUFACTURING ELECTRONIC APPARATUS

An electronic component includes a substrate configured to include a first portion that first thermal conductivity, and have a first surface and a second surface opposite to the first surface;a second portion configured to be formed inside the first portion, and have second thermal conductivity lower than the first thermal conductivity;a first terminal configured to be formed to correspond to the second portion on a side of the first surface; and a second terminal configured to be formed on a side of the second surface.

CMOS sensors and methods of forming the same

本發明實施例提供一種互補金屬氧化物半導體感測器，包括半導體基底、介電層、內連線、接合墊以及虛設圖案。所述半導體基底具有畫素區和電路區。所述介電層被所述電路區中的所述半導體基底環繞。所述內連線設置在所述電路區中的所述介電層上。所述接合墊設置在所述電路區中的所述介電層中且電連接至所述內連線。所述虛設圖案設置在所述電路區中的所述介電層中且環繞所述接合墊。

Wafer-level chip-scale package with redistribution layer

A Wafer-level chip scale package (WLCSP) includes a semiconductor structure and a first bonding pad formed over a portion of the semiconductor structure. The WLCSP further includes a passivation layer formed over the semiconductor structure and the first bonding pad, exposing portions of the first bonding pad. The WLCSP further includes a conductive redistribution layer formed over the passivation layer and the portions of the first bonding pad exposed by the passivation layer. The WLCSP further includes a planarization layer formed over the passivation layer and the conductive redistribution layer, exposing a portion of the conductive redistribution layer. The WLCSP further includes an under-bump-metallurgy (UBM) layer formed over the planarization layer and a conductive bump formed over the UBM layer.

Semiconductor packages

A semiconductor package includes a plurality of semiconductor chips. At least one of the semiconductor chips includes a semiconductor substrate including a semiconductor layer and a passivation layer having a third surface, a backside pad on the third surface, and a through-via penetrating through the semiconductor substrate. The backside pad includes an electrode pad portion, on the third surface, and a dam structure protruding on one side of the electrode pad portion and surrounding a side surface of the through-via. The dam structure is spaced apart from the side surface of the through-via.

Semiconductor device and method of forming the same

Semiconductor device and method of forming the same

The present disclosure provides a semiconductor device. The semiconductor device includes a first die and a conductive layer. The first die is to be bonded with, in a direction, a second die external to the semiconductor device. The conductive layer, between the first die and the second die in the direction, has a reference ground.

WAFER LEVEL CHIP SCALE PACKAGE, METHOD OF MANUFACTURING THE SAME, AND SEMICONDUCTOR CHIP MODULE INCLUDING THE WAFER LEVEL CHIP SCALE PACKAGE

Provided are a wafer level chip scale package in which a redistribution process is applied at a wafer level, a manufacturing method thereof, and a semiconductor chip module including the wafer level chip scale package. The wafer level chip scale package includes a semiconductor chip having a bonding pad, a first insulating layer disposed on the semiconductor chip so as to expose the bonding pad, a redistribution line disposed on the exposed bonding pad and the first insulating layer, a sacrificial layer disposed below a redistribution pad of the redistribution line, a second insulating layer disposed on the redistribution line so as to expose the redistribution pad and including a crack inducement hole disposed beside the sacrificial layer, and an external connection terminal attached to the redistribution pad.

Cmos sensors and methods of forming the same

Electronic component, electronic apparatus, and method of manufacturing electronic apparatus

An electronic component includes a substrate configured to include a first portion that first thermal conductivity, and have a first surface and a second surface opposite to the first surface; a second portion configured to be formed inside the first portion, and have second thermal conductivity lower than the first thermal conductivity; a first terminal configured to be formed to correspond to the second portion on a side of the first surface; and a second terminal configured to be formed on a side of the second surface.

REDISTRIBUTION LAYER (RDL) STRUCTURE, SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

The present disclosure provides a redistribution layer (RDL) structure, a semiconductor device and manufacturing method thereof. The semiconductor device comprising an RDL structure that may include a substrate, a first conductive layer, a reinforcement layer and, and a second conductive layer. The first conductive layer may be formed on the substrate and has a first bond pad area. The reinforcement layer may be formed on a surface of the first conductive layer facing away from the substrate and located in the first bond pad area. The second conductive layer may be formed on the reinforcement layer and an area of the first conductive layer not covered by the reinforcement layer. The reinforcement layer has a material strength greater than those of the first conductive layer and the second conductive layer. The semiconductor device and the manufacturing method provided by the present disclosure may improve the performance of the semiconductor device. 1. A redistribution layer (RDL) structure , comprising:a substrate;a first conductive layer formed on the substrate and having a first bond pad area;a reinforcement layer formed on a surface of the first conductive layer not adjacent to the substrate and located in the first bond pad area; anda second conductive layer formed on the reinforcement layer and an area of the first conductive layer not covered by the reinforcement layer,wherein the reinforcement layer has a material strength greater than those of the first conductive layer and the second conductive layer and the reinforcement layer is conductive.2. The RDL structure according to claim 1 , wherein the reinforcement layer has at least one first through via claim 1 , and the second conductive layer fills the at least one first through via and is connected to the first conductive layer.3. The RDL structure according to claim 2 , wherein the at least one first through via comprises a plurality of first through vias distributed at intervals along an annular track.4. ...

Packaging Devices and Methods of Manufacture Thereof

Packaging devices and methods of manufacture thereof for semiconductor devices are disclosed. In some embodiments, a packaging device includes a contact pad disposed over a substrate, and a passivation layer disposed over the substrate and a first portion of the contact pad. A post passivation interconnect (PPI) line is disposed over the passivation layer and is coupled to a second portion of the contact pad. A PPI pad is disposed over the passivation layer. A transition element is disposed over the passivation layer and is coupled between the PPI line and the PPI pad. The transition element comprises a first side and a second side coupled to the first side. The first side and the second side of the transition element are non-tangential to the PPI pad. 1. A device comprising:an array of connector pads, respective connector pads being electrically connected to respective conductive lines by way of respective transition elements, wherein the array has a neutral point associated with it; andat least one transition element in the array connecting a respective connector pad to a respective conductive line, the at least one transition element including a first side and a second side coupled to the first side at an apex, wherein the first side and the second side of the at least one transition element are non-tangential to the respective pad, and wherein the apex points toward the neutral point of the array.2. The device of claim 1 , wherein the transition element further includes a curved outer edge substantially aligned with an outer edge of the respective connector pad.3. The device of claim 1 , wherein the transition element further includes a hollow region.4. The device of claim 3 , wherein the hollow region comprises a shape selected from the group consisting of a circle claim 3 , an oval claim 3 , a triangle claim 3 , a triangle with a curved side or a curved corner claim 3 , a rectangle claim 3 , a rectangle with a curved side or a curved corner claim 3 , a square ...

Method and process for emib chip interconnections

A method for attaching an integrated circuit (IC) to an IC package substrate includes forming a solder bump on a bond pad of an IC die, forming a solder-wetting protrusion on a bond pad of an IC package substrate, and bonding the solder bump of the IC die to the solder-wetting protrusion of the IC package substrate.

Packaging devices

Packaging devices and methods of manufacture thereof for semiconductor devices are disclosed. In some embodiments, a packaging device includes a contact pad disposed over a substrate, and a passivation layer disposed over the substrate and a first portion of the contact pad. A second portion of the contact pad is exposed. A post passivation interconnect (PPI) line is disposed over the passivation layer and is coupled to the second portion of the contact pad. A PPI pad is disposed over the passivation layer. A transition element is disposed over the passivation layer and is coupled between the PPI line and the PPI pad. The transition element includes a hollow region.

Electronic component and method for producing the same

An aspect of the invention is an electronic component including a semiconductor substrate 11 that has an electrode pad 12 , a first resin layer 14 and a third resin layer 15 that are located above the semiconductor substrate, a second resin layer 16 that is formed such that at least portions of the second resin layer are located on the first resin layer and the third resin layer, a resin projection 17 that includes the first to third resin layers and is higher than the first resin layer, and a wiring layer 24 that is electrically connected to the electrode pad and lies above the resin projection.

WAFER-LEVEL CHIP-SCALE PACKAGE WITH REDISTRIBUTION LAYER

Packaging devices and methods of manufacture thereof

Packaging devices and methods of manufacture thereof for semiconductor devices are disclosed. In some embodiments, a packaging device includes a contact pad disposed over a substrate, and a passivation layer disposed over the substrate and a first portion of the contact pad, a second portion of the contact pad being exposed. A post passivation interconnect (PPI) line is disposed over the passivation layer and is coupled to the second portion of the contact pad. A PPI pad is disposed over the passivation layer and is coupled to the PPI line. An insulating material is disposed over the PPI line, the PPI pad being exposed. The insulating material is spaced apart from an edge portion of the PPI pad by a predetermined distance.

SEMICONDUCTOR PACKAGES

A method of manufacturing a semiconductor package includes: forming through-vias extending from a front side of a semiconductor substrate into the substrate; forming, on the front side of the semiconductor substrate, a circuit structure including a wiring structure electrically connected to the through-vias; removing a portion of the semiconductor substrate so that at least a portion of each of the through-vias protrudes to a rear side of the semiconductor substrate; forming a passivation layer covering the protruding portion of each of the through-vias; forming trenches recessed along a periphery of a corresponding one of the through-vias; removing a portion of the passivation layer so that one end of each of the through-vias is exposed to the upper surface of the passivation layer; and forming backside pads including a dam structure in each of the trenches, the dam structure being spaced apart from the corresponding one of the through-vias.

CMOS sensors and methods of forming the same

CMOS sensors and methods of forming the same are disclosed. The CMOS sensor includes a semiconductor substrate, a plurality of dielectric patterns, a first conductive element and a second conductive element. The semiconductor substrate has a pixel region and a circuit region. The dielectric patterns are disposed between the first portion and the second portion, wherein top surfaces of the plurality of dielectric patterns are lower than top surfaces of the first and second portions. The first conductive element is disposed below the plurality of dielectric patterns. The second conductive element inserts between the plurality of dielectric patterns to electrically connect the first conductive element.

Semiconductor device and method of forming the same

The present disclosure provides a semiconductor device. The semiconductor device includes a first die and a conductive layer. The first die is to be bonded with, in a direction, a second die external to the semiconductor device. The conductive layer, between the first die and the second die in the direction, has a reference ground.

WAFER-LEVEL CHIP-SCALE PACKAGE WITH REDISTRIBUTION LAYER

A Wafer-level chip scale package (WLCSP) includes a semiconductor structure and a first bonding pad formed over a portion of the semiconductor structure. The WLCSP further includes a passivation layer formed over the semiconductor structure and the first bonding pad, exposing portions of the first bonding pad. The WLCSP further includes a conductive redistribution layer formed over the passivation layer and the portions of the first bonding pad exposed by the passivation layer. The WLCSP further includes a planarization layer formed over the passivation layer and the conductive redistribution layer, exposing a portion of the conductive redistribution layer. The WLCSP further includes an under-bump-metallurgy (UBM) layer formed over the planarization layer and a conductive bump formed over the UBM layer. 1. A wafer-level chip-scale package , comprising:a semiconductor structure;a first bonding pad formed over a portion of the semiconductor structure;a passivation layer formed over the semiconductor structure and the first bonding pad, wherein the passivation layer exposes a plurality of portions of the first bonding pad;a conductive redistribution layer formed over the passivation layer and the portions of the first bonding pad exposed by the passivation layer;a planarization layer formed over the passivation layer and the conductive redistribution layer, exposing a portion of the conductive redistribution layer;an under-bump-metallurgy (UBM) layer formed over the planarization layer and the portion of the conductive redistribution layer exposed by the planarization layer; anda conductive bump formed over the UBM layer.2. The Wafer-level chip-scale package claimed in claim 1 , wherein the passivation layer formed over the semiconductor structure and the first bonding pad has a flat top surface.3. The Wafer-level chip-scale package claimed in claim 1 , wherein the conductive redistribution layer formed over the portions of the first bonding pad exposed by the ...

Method and process for emib chip interconnections

CHIP PACKAGE AND MANUFACTURING METHOD THEREOF

A chip package includes a substrate, an isolation layer, a redistribution layer, a passivation layer, a first conductive layer, a second conductive layer, and a conductive structure. The isolation layer is located on the substrate. The redistribution layer is located on the isolation layer. The passivation layer is located on the isolation layer and the redistribution layer. The passivation layer has an opening, a wall surface that surrounds the opening, and a surface that faces away from the isolation layer. A portion of the redistribution layer is exposed through the opening. The first conductive layer is located on the redistribution layer that is in the opening, and extends to the wall surface and the surface of the passivation layer. The second conductive layer covers the first conductive layer. The conductive structure is located on the second conductive layer and protrudes from the passivation layer. 1. A chip package , comprising:a substrate;an isolation layer located on the substrate;a redistribution layer located on the isolation layer;a passivation layer located on the isolation layer and the redistribution layer, the passivation layer having an opening, a wall surface that surrounds the opening, and a surface that faces away from the isolation layer, wherein a portion of the redistribution layer is exposed through the opening;a first conductive layer located on the redistribution layer that is in the opening, wherein the first conductive layer extends to the wall surface and the surface of the passivation layer;a second conductive layer covering the first conductive layer; anda conductive structure located on the second conductive layer and protruding from the passivation layer.2. The chip package of claim 1 , wherein the redistribution layer is made of a material comprising aluminum.3. The chip package of claim 1 , wherein the first conductive layer is made of a material comprising aluminum or a titanium-tungsten alloy.4. The chip package of claim 1 , ...

Packaging devices and methods of manufacture thereof

Packaging devices and methods of manufacture thereof for semiconductor devices are disclosed. In some embodiments, a packaging device includes a contact pad disposed over a substrate, and a passivation layer disposed over the substrate and a first portion of the contact pad. A post passivation interconnect (PPI) line is disposed over the passivation layer and is coupled to a second portion of the contact pad. A PPI pad is disposed over the passivation layer. A transition element is disposed over the passivation layer and is coupled between the PPI line and the PPI pad. The transition element comprises a first side and a second side coupled to the first side. The first side and the second side of the transition element are non-tangential to the PPI pad.

Packaging Devices and Methods of Manufacture Thereof

Packaging devices and methods of manufacture thereof for semiconductor devices are disclosed. In some embodiments, a packaging device includes a contact pad disposed over a substrate, and a passivation layer disposed over the substrate and a first portion of the contact pad. A post passivation interconnect (PPI) line is disposed over the passivation layer and is coupled to a second portion of the contact pad. A PPI pad is disposed over the passivation layer. A transition element is disposed over the passivation layer and is coupled between the PPI line and the PPI pad. The transition element comprises a first side and a second side coupled to the first side. The first side and the second side of the transition element are non-tangential to the PPI pad. 1. A packaging device , comprising:a contact pad disposed over a substrate;a passivation layer disposed over the substrate and a first portion of the contact pad;a post passivation interconnect (PPI) line disposed over the passivation layer and coupled to a second portion of the contact pad;a PPI pad disposed over the passivation layer; anda transition element disposed over the passivation layer and coupled between the PPI line and the PPI pad, wherein the transition element comprises a first side and a second side coupled to the first side, and wherein the first side and the second side of the transition element are non-tangential to the PPI pad.2. The packaging device according to claim 1 , wherein an angle between the first side and the second side of the transition element comprises about 70 degrees proximate the PPI line.3. The packaging device according to claim 1 , wherein the transition element comprises a hollow region.4. The packaging device according to claim 3 , wherein the hollow region comprises a shape selected from the group consisting essentially of: a circle claim 3 , an oval claim 3 , a triangle claim 3 , a triangle with a curved side or a curved corner claim 3 , a rectangle claim 3 , a rectangle ...

Wafer-level chip-scale package and a method for forming it

This disclosure relates to a Wafer-level chip scale package and a method for forming it, wherein the Wafer-level chip scale package comprises: a semiconductor structure; a first bonding pad formed over a portion of the semiconductor structure; a passivation layer formed over the semiconductor structure and the first bonding pad, wherein the passivation layer exposes a plurality of portions of the first bonding pad; a conductive redistribution layer formed over the passivation layer and the portions of the first bonding pad exposed by the passivation layer; a planarization layer formed over the passivation layer and the conductive redistribution layer, exposing a portion of the conductive redistribution layer; an under-bump-metallurgy (UBM) layer formed over the planarization layer and the portion of the conductive redistribution layer exposed by the planarization layer; and a conductive bump formed over the UBM layer. Therefore, this disclosure can provide a WLCSP with a reduced size.

Wafer level chip scale package, method of manufacturing the same, and semiconductor chip module including the wafer level chip scale package

Provided are a wafer level chip scale package in which a redistribution process is applied at a wafer level, a manufacturing method thereof, and a semiconductor chip module including the wafer level chip scale package. The wafer level chip scale package includes a semiconductor chip having a bonding pad, a first insulating layer disposed on the semiconductor chip so as to expose the bonding pad, a redistribution line disposed on the exposed bonding pad and the first insulating layer, a sacrificial layer disposed below a redistribution pad of the redistribution line, a second insulating layer disposed on the redistribution line so as to expose the redistribution pad and including a crack inducement hole disposed beside the sacrificial layer, and an external connection terminal attached to the redistribution pad.

Stress relieving structure for semiconductor device

A semiconductor device includes a semiconductor body, a stress relieving layer or layer stack disposed over at least part of the semiconductor body, the stress relieving layer or layer stack comprising a plurality of openings which yield a patterned surface topography for the stress relieving layer or layer stack, and a metal layer or layer stack formed on the stress relieving layer or layer stack and occupying the plurality of openings in the stress relieving layer or layer stack. The patterned surface topography of the stress relieving layer or layer stack is transferred to a surface of the metal layer or layer stack facing away from the semiconductor body. The stress relieving layer or layer stack has a different elastic modulus than the metal layer or layer stack over a temperature range.

Packaging devices and methods of manufacture thereof

Packaging devices and methods of manufacture thereof for semiconductor devices are disclosed. In some embodiments, a packaging device includes a contact pad disposed over a substrate, and a passivation layer disposed over the substrate and a first portion of the contact pad. A post passivation interconnect (PPI) line is disposed over the passivation layer and is coupled to a second portion of the contact pad. A PPI pad is disposed over the passivation layer. A transition element is disposed over the passivation layer and is coupled between the PPI line and the PPI pad. The transition element comprises a first side and a second side coupled to the first side. The first side and the second side of the transition element are non-tangential to the PPI pad.

Packaging Devices and Methods of Manufacture Thereof

Packaging devices and methods of manufacture thereof for semiconductor devices are disclosed. In some embodiments, a packaging device includes a contact pad disposed over a substrate, and a passivation layer disposed over the substrate and a first portion of the contact pad. A second portion of the contact pad is exposed. A post passivation interconnect (PPI) line is disposed over the passivation layer and is coupled to the second portion of the contact pad. A PPI pad is disposed over the passivation layer. A transition element is disposed over the passivation layer and is coupled between the PPI line and the PPI pad. The transition element includes a hollow region.

ELECTRONIC COMPONENT AND METHOD FOR PRODUCING THE SAME

An aspect of the invention is an electronic component including a semiconductor substrate 11 that has an electrode pad 12, a first resin layer 14 and a third resin layer 15 that are located above the semiconductor substrate, a second resin layer 16 that is formed such that at least portions of the second resin layer are located on the first resin layer and the third resin layer, a resin projection 17 that includes the first to third resin layers and is higher than the first resin layer, and a wiring layer 24 that is electrically connected to the electrode pad and lies above the resin projection.

Packaging Devices and Methods of Manufacture Thereof

Packaging devices and methods of manufacture thereof for semiconductor devices are disclosed. In some embodiments, a packaging device includes a contact pad disposed over a substrate, and a passivation layer disposed over the substrate and a first portion of the contact pad, a second portion of the contact pad being exposed. A post passivation interconnect (PPI) line is disposed over the passivation layer and is coupled to the second portion of the contact pad. A PPI pad is disposed over the passivation layer and is coupled to the PPI line. An insulating material is disposed over the PPI line, the PPI pad being exposed. The insulating material is spaced apart from an edge portion of the PPI pad by a predetermined distance.

Redistribution layer (RDL) structure, semiconductor device and manufacturing method thereof

The present disclosure provides a redistribution layer (RDL) structure, a semiconductor device and manufacturing method thereof. The semiconductor device comprising an RDL structure that may include a substrate, a first conductive layer, a reinforcement layer and, and a second conductive layer. The first conductive layer may be formed on the substrate and has a first bond pad area. The reinforcement layer may be formed on a surface of the first conductive layer facing away from the substrate and located in the first bond pad area. The second conductive layer may be formed on the reinforcement layer and an area of the first conductive layer not covered by the reinforcement layer. The reinforcement layer has a material strength greater than those of the first conductive layer and the second conductive layer.

Method for aligning micro-electronic components

Alignment of a first micro-electronic component to a receiving surface of a second micro-electronic component is realized by a capillary force-induced self-alignment, combined with an electrostatic alignment. The latter is accomplished by providing at least one first electrical conductor line along the periphery of the first component, and at least one second electrical conductor along the periphery of the location on the receiving surface of the second component onto which the component is to be placed. The contact areas surrounded by the conductor lines are covered with a wetting layer. The electrical conductor lines may be embedded in a strip of anti-wetting material that runs along the peripheries to create a wettability contrast. The wettability contrast helps to maintain a drop of alignment liquid between the contact areas so as to obtain self-alignment by capillary force. By applying appropriate charges on the conductor lines, electrostatic self-alignment is realized, which improves ...

CMOS SENSORS AND METHODS OF FORMING THE SAME

CMOS sensors and methods of forming the same are disclosed. The CMOS sensor includes a semiconductor substrate, a dielectric layer, an interconnect, a bonding pad and a dummy pattern. The semiconductor substrate has a pixel region and a circuit region. The dielectric layer is surrounded by the semiconductor substrate in the circuit region. The interconnect is disposed over the dielectric layer in the circuit region. The bonding pad is disposed in the dielectric layer and electrically connects the interconnect in the circuit region. The dummy pattern is disposed in the dielectric layer and surrounds the bonding pad in the circuit region. 1. A CMOS sensor , comprising:a semiconductor substrate having a pixel region and a circuit region;a dielectric layer surrounded by the semiconductor substrate in the circuit region;an interconnect over the dielectric layer in the circuit region;a bonding pad disposed in the dielectric layer and electrically connecting the interconnect in the circuit region; anda dummy pattern disposed in the dielectric layer and surrounding the bonding pad in the circuit region, wherein a top surface of the dummy pattern is higher than a top surface of the bonding pad.2. The CMOS sensor of claim 1 , wherein the semiconductor substrate is not disposed between the bonding pad and the interconnect.3. The CMOS sensor of claim 1 , wherein the bonding pad and the dummy pattern are surrounded by the semiconductor substrate.4. The CMOS sensor of claim 1 , wherein the dummy pattern is disposed between the semiconductor substrate and the bonding pad.5. The CMOS sensor of claim 1 , wherein the dummy pattern is ring-shaped.6. The CMOS sensor of claim 1 , wherein a material of the dummy pattern and a material of the bonding pad are the same.7. The CMOS sensor of claim 1 , wherein the bonding pad and the dummy pattern are separated by a distance.8. A CMOS sensor claim 1 , comprising:a patterned semiconductor substrate;a patterned dielectric layer exposed by the ...

Method and process for EMIB chip interconnections

Semiconductor package

Provided is a semiconductor package including a circuit substrate including a substrate pad, a semiconductor chip spaced apart from and facing the circuit substrate, the semiconductor chip including a chip pad, and a connection pattern electrically connecting the circuit substrate with the semiconductor chip. The semiconductor chip may include a plurality of first circuit patterns extending substantially perpendicular toward a top surface of the semiconductor chip and at least one first via electrically connecting the chip pad to the first circuit patterns. The chip pad may include a first region in contact with the connection pattern and a second region outside the first region, and the first via may be connected to the second region of the chip pad.

Bump Structure and Method of Forming Same

An embodiment bump on trace (BOT) structure includes a contact element supported by an integrated circuit, an under bump metallurgy (UBM) feature electrically coupled to the contact element, a metal bump on the under bump metallurgy feature, and a substrate trace on a substrate, the substrate trace coupled to the metal bump through a solder joint and intermetallic compounds, a ratio of a first cross sectional area of the intermetallic compounds to a second cross sectional area of the solder joint greater than forty percent.

Metal Bump and Method of Manufacturing Same

An embodiment bump structure includes a contact element formed on a substrate, a passivation layer overlying the substrate, the passivation layer having a passivation opening exposing the contact element a polyimide layer overlying the passivation layer, the polyimide layer having a polyimide opening exposing the contact element an under bump metallurgy (UMB) feature electrically coupled to the contact element, the under bump metallurgy feature having a UBM width, and a copper pillar on the under bump metallurgy feature, a distal end of the copper pillar having a pillar width, the UBM width greater than the pillar width.

PACKAGE STRUCTURE AND METHOD OF FORMING THE SAME

A package structure includes a first dielectric layer, a first semiconductor device over the first dielectric layer, a first redistribution line in the first dielectric layer, a second dielectric layer over the first semiconductor device, a second semiconductor device over the second dielectric layer, a second redistribution line in the second dielectric layer, a conductive through-via over the first dielectric layer and electrically connected to the first redistribution line, a conductive ball over the conductive through-via and electrically connected to the second redistribution line, and a molding material. The molding material surrounds the first semiconductor device, the conductive through-via, and the conductive ball, wherein a top of the conductive ball is higher than a top of the molding material. 1. A package structure , comprising:a first dielectric layer;a first semiconductor device over the first dielectric layer;a first redistribution line in the first dielectric layer;a second dielectric layer over the first semiconductor device;a second semiconductor device over the second dielectric layer;a second redistribution line in the second dielectric layer;a conductive through-via over the first dielectric layer and electrically connected to the first redistribution line;a conductive ball over the conductive through-via and electrically connected to the second redistribution line; anda molding material surrounding the first semiconductor device, the conductive through-via, and the conductive ball, wherein a top of the conductive ball is higher than a top of the molding material.2. The package structure of claim 1 , wherein a bottom of the conductive ball is lower than the top of the molding material.3. The package structure of claim 1 , wherein the molding material has a portion vertically overlapping the first semiconductor device.4. The package structure of claim 1 , wherein the top of the molding material is higher than a top of the first semiconductor ...

SEMICONDUCTOR PACKAGE AND METHOD OF FORMING THE SAME

The present disclosure provides a semiconductor package, including a substrate, an active region in the substrate, an interconnecting layer over the active region, a conductive pad over the interconnecting layer, surrounded by a dielectric layer. At least two discrete regions of the conductive pad are free from coverage of the dielectric layer. A method of manufacturing the semiconductor package is also disclosed. 1. A semiconductor package , comprising:a substrate;an active region in the substrate;an interconnecting layer over the active region;a conductive pad over the interconnecting layer, surrounded by a dielectric layer, wherein at least two discrete regions of the conductive pad are free from coverage of the dielectric layer: anda conductive bump over the conductive pad and the dielectric layer, the conductive bump comprises at least two protrusions separated by the dielectric layer.2. The semiconductor package of claim 1 , wherein the dielectric layer comprises:a passivation layer having a portion at a same level with the conductive pad; anda polymer layer stacking over the passivation layer.3. The semiconductor package of claim 1 , wherein the conductive bump being in contact with the conductive pad at the at least two discrete regions.4. The semiconductor package of claim 1 , further comprising:an under bump metallurgy (UBM) layer over the conductive pad and the dielectric layer, the UBM layer being in contact with the conductive pad at the at least two discrete regions, wherein the protrusions of the conductive bump are in contact with the UBM layer over the at least two discrete regions of the conductive pad.5. The semiconductor package of claim 1 , wherein the at least two discrete regions comprise different sizes from a top view perspective.6. The semiconductor package of claim 3 , further comprising:a solder bump at an opposite end of the conductive bump contacting the conductive pad; anda package substrate connected to the solder bump.7. The ...

SEMICONDUCTOR PACKAGE

The present disclosure provides a semiconductor package including a semiconductor chip and a package substrate. The semiconductor chip includes a substrate, a plurality of conductive pads in the substrate, and a plurality of conductive bumps. Each of the conductive bumps is over corresponding conductive pad. At least one of the conductive bumps proximity to an edge of the semiconductor chip is in contact with at least two discrete regions of the corresponding conductive pad. The package substrate has a concave surface facing the semiconductor chip and joining the semiconductor chip through the plurality of conductive bumps. 1. A semiconductor package , comprising: a substrate;', 'a plurality of conductive pads in the substrate; and', 'a plurality of conductive bumps, each over corresponding conductive pad, at least one of the conductive bumps proximity to an edge of the semiconductor chip being in contact with at least two discrete regions of the corresponding conductive pad; and, 'a semiconductor chip, comprisinga package substrate having a concave surface facing the semiconductor chip and joining the semiconductor chip through the plurality of conductive bumps.2. The semiconductor package of claim 1 , wherein one of the at least two discrete regions closer to a center of the semiconductor chip is larger than another one of the at least two discrete regions closer to the edge of the semiconductor chip.3. The semiconductor package of claim 1 , wherein the conductive pads having at least two discrete regions are ellipses from top view perspective.4. The semiconductor package of claim 3 , wherein the two discrete regions are on a major axis of each of the conductive pads from top view perspective.5. The semiconductor package of claim 1 , further comprising:an active region in the substrate; andan interconnecting layer over the active region and in contact with a bottom of each of the conductive pads.6. The semiconductor package of claim 5 , further comprising a ...

CONDUCTIVE CONTACTS HAVING VARYING WIDTHS AND METHOD OF MANUFACTURING SAME

A bump structure includes a contact element formed on a substrate and a passivation layer overlying the substrate. The passivation layer includes a passivation opening exposing the contact element. The bump structure also includes a polyimide layer overlying the passivation layer and an under bump metallurgy (UBM) feature electrically coupled to the contact element. The polyimide layer has a polyimide opening exposing the contact element, and the under bump metallurgy feature has a UBM width. The bump structure further includes a copper pillar on the under bump metallurgy feature. A distal end of the copper pillar has a pillar width, and the UBM width is greater than the pillar width. 1. A method comprising:forming a contact element over a substrate;forming one or more insulating layers over the contact element;patterning an opening in the one or more insulating layers to expose the contact element;electrically coupling an under bump metallurgy (UBM) feature with the contact element; andforming a conductive pillar on an opposing side of the UBM feature as the contact element, wherein the conductive pillar continuously decreases in diameter from a top surface of the UBM feature to a top surface of the conductive pillar, and wherein sidewalls of the conductive pillar are non-perpendicular to a major surface of the substrate.2. The method of further comprising disposing a solder joint on the top surface of the conductive pillar.3. The method of further comprising bonding the solder joint to a substrate trace of a semiconductor device.4. The method of claim 2 , wherein a distance between the conductive pillar and an adjacent conductive pillar measured at the UBM feature is less than a distance between the conductive pillar and the adjacent conductive pillar measured at a surface of the conductive pillar distal to the UBM feature.5. The method of claim 1 , wherein electrically coupling the UBM feature comprises disposing at least a portion of the UBM feature in the ...

DISPLAY DEVICE AND METHOD FOR MANUFACTURING DISPLAY DEVICE

A display panel comprising a display substrate having a display area and a pad area disposed around the display area. A connection wire is disposed on the pad area of the display substrate. A signal wire is disposed on the connection wire. A supporter is disposed between the display substrate and the connection wire. The connection wire directly contacts the supporter. 1. A display panel comprising:a display substrate having a display area and a pad area disposed around the display area;a connection wire disposed on the pad area of the display substrate;a signal wire disposed on the connection wire; anda supporter disposed between the display substrate and the connection wire,wherein the connection wire directly contacts the supporter.2. The display panel of claim 1 , wherein:a planar size of the connection wire is greater than a planar size of the supporter; andthe connection wire covers the supporter.3. The display panel of claim 2 , wherein:a planar size of the signal wire is greater than the planar size of the connection wire; andthe signal wire directly contacts the connection wire.4. The display panel of claim 1 , further comprising an insulating layer disposed between the display substrate and the signal wire claim 1 ,wherein the insulating layer covers a side surface of the connection wire and exposes an upper surface thereof.5. The display panel of claim 4 , wherein the signal wire directly contacts an upper surface of the insulating layer.6. The display panel of claim 1 , wherein a cross-sectional shape of the supporter includes a trapezoidal shape claim 1 , a triangular shape claim 1 , a pentagonal shape claim 1 , a semicircular shape claim 1 , a semi-elliptical shape claim 1 , and/or a quadrangular shape.7. The display panel of claim 1 , wherein the supporter includes a plurality of patterns extending along a long-side direction of the signal wire andspaced apart from each other along a short-side direction of the signal wire.8. The display panel of ...

DISPLAY APPARATUS

A display apparatus includes a substrate including a display region and a non-display region, a display element layer, a pad group, a touch electrode layer, and a touch insulating layer. The display element layer includes display elements provided in the display region in a plan view. The pad group may include output pads provided on substrate and provided in the non-display region in the plan view. The touch electrode layer is provided on the display element layer. The touch insulating layer is provided on the display element layer and contacts the touch electrode layer. An intaglio pattern is provided in the touch insulating layer overlapped with the non-display region, and the intaglio pattern is not overlapped with the pad group. 1. A display apparatus , comprising:a display panel comprising a substrate comprising a display region and a non-display region adjacent to the display region, an intermediate insulation layer which defines an opening overlapping the non-display region and disposed on the substrate, a pixel disposed in the display region, and a pad group connected to the pixel and overlapping the opening;a driving circuit chip connected to the pad group and overlapping the opening; anda touch sensor including a touch insulating layer disposed on the display panel and a touch electrode layer;wherein the touch insulating layer comprises an intaglio pattern overlapping a portion of the driving circuit chip and passing through the touch insulating layer.2. The display apparatus of claim 1 , wherein the pad group comprises output pads arranged in a first direction and input pads spaced apart from the output pads in a second direction intersecting the first direction and arranged in the first direction claim 1 ,wherein the touch insulating layer comprises touch openings exposing the output pads and the input pads.3. The display apparatus of claim 2 , further comprising a test circuit disposed between the out pads and input pads and connected to the out pads ...

DISPLAY DEVICE

A display device is disclosed. According to one aspect of the present invention, provided is a display device comprising a display panel having a first display area and a second display area on the outside of the first display area, wherein the display panel comprises: a first substrate which includes a main pixel unit disposed in the first display area and having main pixels, and a GIP unit disposed in the second display area and generating a gate signal; and a second substrate which is bonded to the first substrate and includes an auxiliary pixel unit disposed in the second display area and having auxiliary pixels, the GIP unit supplying the gate signal to the main pixels and the auxiliary pixels. 1. A display device comprising:a display panel having a first display area and a second display area on the outside of the first display area,wherein the display panel includes,a first substrate which includes a main pixel unit disposed in the first display area and having main pixels, and a GIP unit disposed in the second display area and generating a gate signal; anda second substrate which is bonded to the first substrate, and includes an auxiliary pixel unit disposed in the second display area and having auxiliary pixels, andwherein the GIP unit supplies the gate signal to the main pixels and the auxiliary pixels.2. The display device of claim 1 , wherein the auxiliary pixel unit overlaps with the GIP unit.3. The display device of claim 2 , wherein the main pixels include a main transistor and an organic light emitting diode connected to the main transistor claim 2 , andthe auxiliary pixels include an auxiliary transistor and an inorganic light emitting diode connected to the auxiliary transistor.4. The display device of claim 1 , wherein pixels on the same row among the main pixels and the auxiliary pixels are applied with the gate signal of the same sequence number.5. The display device of claim 1 , wherein the main pixel unit and the GIP unit are disposed on a ...

Methods and Apparatus for Package with Interposers

Methods and apparatus for an interposer with dams used in packaging dies are disclosed. An interposer may comprise a metal layer above a substrate. A plurality of dams may be formed above the metal layer around each corner of the metal layer. Dams may be formed on both sides of the interposer substrate. A dam surrounds an area where connectors such as solder balls may be located to connect to other packages. A non-conductive dam may be formed above the dam. An underfill may be formed under the package connected to the connector, above the metal layer, and contained within the area surrounded by the dams at the corner, so that the connectors are well protected by the underfill. Such dams may be further formed on a printed circuit board as well.

Method for preparing a semiconductor device with spacer over sidewall of bonding pad

The present application provides a method for preparing a semiconductor device, include the following steps: forming a source/drain (S/D) region in a semiconductor substrate; forming a bonding pad over the semiconductor substrate; forming a first spacer over a sidewall of the bonding pad; forming a first passivation layer covering the bonding pad and the first spacer; and forming a conductive bump over the first passivation layer, wherein the conductive bump penetrates through the first passivation layer to electrically connect to the bonding pad and the S/D region.

Semiconductor composite layer structure and semiconductor packaging structure having the same thereof

A semiconductor composite layer structure disposed on a substrate having an electronic circuit structure and a first conductive layer is disclosed. The semiconductor composite layer structure comprises a plurality of dielectric layers, a first wetting layer, a stiff layer and a second wetting layer. The dielectric layers are disposed on the substrate separately. The first wetting layer is disposed on the dielectric layer and the substrate between the dielectric layers. The stiff layer is disposed on the first wetting layer. The second wetting layer is disposed on stiff layer, for contacting with a second conductive layer.

DISPLAY APPARATUS

A display apparatus includes a substrate including a display region and a non-display region, a display element layer, a pad group, a touch electrode layer, and a touch insulating layer. The display element layer includes display elements provided in the display region in a plan view. The pad group may include output pads provided on substrate and provided in the non-display region in the plan view. The touch electrode layer is provided on the display element layer. The touch insulating layer is provided on the display element layer and contacts the touch electrode layer. An intaglio pattern is provided in the touch insulating layer overlapped with the non-display region, and the intaglio pattern is not overlapped with the pad group. 1. A display apparatus , comprising:a substrate including a display region and a non-display region adjacent to the display region;an insulating layer disposed on the substrate;a display element layer disposed on the insulating layer, the display element layer comprising display elements disposed in the display region in a plan view;a pad group including output pads electrically connected to the display elements and disposed in the non-display region in the plan view;an intermediate insulating layer which is disposed between the insulating layer and the display element layer and overlapping the display region and the non-display region, the intermediate insulating layer defining an opening exposing the pad group;a touch electrode layer disposed on the display element layer and overlapping the display region; anda touch insulating layer disposed on the display element layer, the touch insulating layer covering the touch electrode layer and defining a first intaglio pattern overlapping the opening,wherein the intaglio pattern is located between the output pads and the intermediate insulating layer in the plan view.2. The display apparatus of claim 1 , further comprising an interlayered insulating layer disposed between the insulation ...

Semiconductor package and manufacturing method thereof

A semiconductor package and a method of making a semiconductor package. As non-limiting examples, various aspects of this disclosure provide various semiconductor packages, and methods of making thereof, that comprise a conductive layer that comprises an anchor portion extending through at least one dielectric layer.

DISPLAY APPARATUS

A display apparatus includes a substrate including a display region and a non-display region, a display element layer, a pad group, a touch electrode layer, and a touch insulating layer. The display element layer includes display elements provided in the display region in a plan view. The pad group may include output pads provided on substrate and provided in the non-display region in the plan view. The touch electrode layer is provided on the display element layer. The touch insulating layer is provided on the display element layer and contacts the touch electrode layer. An intaglio pattern is provided in the touch insulating layer overlapped with the non-display region, and the intaglio pattern is not overlapped with the pad group. 1. A display apparatus , comprising:a substrate including a display region and a non-display region adjacent to the display region;an insulating layer disposed on the substrate;a display element layer disposed on the insulating layer, the display element layer comprising display elements disposed in the display region in a plan view;a pad group including output pads electrically connected to the display elements and disposed in the non-display region in the plan view;an intermediate insulating layer which is disposed between the insulating layer and the display element layer and overlapping the display region and the non-display region, the intermediate insulating layer defining an opening exposing the pad group;a touch electrode layer disposed on the display element layer and comprising a touch electrode layer overlapping the display region; anda touch insulating layer disposed on the display element layer, the touch insulating layer covering the touch electrode layer and defining a first intaglio pattern overlapping the opening,wherein the intaglio pattern is located between the output pads and the intermediate insulating layer in the plan view.2. The display apparatus of claim 1 , further comprising an interlayered insulating layer ...

Packaged Semiconductor Devices and Methods of Packaging Thereof

Packaging methods for semiconductor devices and methods of packaging thereof are disclosed. In some embodiments, a device includes a packaging apparatus and contact pads disposed on the packaging apparatus. The contact pads are arranged in an array of rows and columns. The contact pads include first contact pads proximate a perimeter region of the packaging apparatus and second contact pads disposed in an interior region of the packaging apparatus. A dam structure that is continuous is disposed around the second contact pads. The contact pads comprise a mounting region for a semiconductor device.

DISPLAY APPARATUS

A display apparatus includes a substrate including a display region and a non-display region, a display element layer, a pad group, a touch electrode layer, and a touch insulating layer. The display element layer includes display elements provided in the display region in a plan view. The pad group may include output pads provided on substrate and provided in the non-display region in the plan view. The touch electrode layer is provided on the display element layer. The touch insulating layer is provided on the display element layer and contacts the touch electrode layer. An intaglio pattern is provided in the touch insulating layer overlapped with the non-display region, and the intaglio pattern is not overlapped with the pad group. 1. A display apparatus , comprising:a substrate including a display region and a non-display region outside the display region;signal lines disposed on the substrate;a display element layer disposed on the signal lines, the display element layer comprising display elements disposed in the display region in a plan view;a pad group including output pads electrically connected to the signal lines and disposed in the non-display region in the plan view;an intermediate insulating layer which is disposed between the signal lines and the display element layer and exposes the output pads;a touch electrode layer disposed on the display element layer; anda touch insulating layer disposed on the display element layer, the touch insulating layer contacting the touch electrode layer and defining an intaglio pattern in the non-display region in the plan view,wherein the intaglio pattern is located between the output pads and the intermediate insulating layer in the plan view.2. The display apparatus of claim 1 , further comprising an interlayered insulating layer claim 1 ,wherein the signal lines comprise a first conductive layer and a second conductive layer on the first conductive layer,the interlayered insulating layer is disposed between the ...

LARGE SCALE INTEGRATED CIRCUIT CHIP AND LARGE SCALE INTEGRATED CIRCUIT WAFER

A large scale integrated circuit chip includes a semiconductor circuit having a multilayered wiring structure, a metal guard ring surrounding the semiconductor circuit, and a plurality of external connection terminals, on a semiconductor circuit. The plurality of external connection terminals connect to an uppermost-layer wiring of the multilayered wiring structure and are exposed on a surface of the large scale integrated circuit chip. A predetermined external connection terminal conducts to a predetermined wiring through a conductive via within the guard ring and conducts to a conductive piece through another conductive via outside the guard ring. One side of the external connection terminal extending over the guard ring connects to the conductive piece, and the other side of the external connection terminal connects to the uppermost-layer wiring within the guard ring. Thus, a cutout part is not necessary in the guard ring. 1. A large scale integrated circuit chip comprising:a semiconductor substrate;a semiconductor circuit formed above the semiconductor substrate and having a vertically multilayered wiring structure;a metal guard ring formed above the semiconductor substrate and surrounding the semiconductor circuit; anda plurality of external connection terminals connecting to a predetermined wiring of the multilayered wiring structure of the semiconductor circuit and exposed on a surface of the large scale integrated circuit chip,wherein a predetermined external connection terminal among the plurality of external connection terminals conducts to the predetermined wiring through a conductive via within the guard ring and conducts to a conductive piece through another conductive via outside the guard ring, andwherein the conductive piece is a piece of a test lead-out wiring and is a wiring having a cut surface that is exposed by dicing.2. The large scale integrated circuit chip according to claim 1 , wherein the external connection terminals are made of a noble ...

PACKAGE STRUCTURE AND METHOD OF FORMING PACKAGE STRUCTURE

A package structure includes a first dielectric layer, a first semiconductor device, a first redistribution line, a second dielectric layer, a second semiconductor device, a second redistribution line, a first conductive feature, and a first molding material. The first semiconductor device is over the first dielectric layer. The first redistribution line is in the first dielectric layer and is electrically connected to the first semiconductor device. The second dielectric layer is over the first semiconductor device. The second semiconductor device is over the second dielectric layer. The second redistribution line is in the second dielectric layer and is electrically connected to the second semiconductor device. The first conductive feature electrically connects the first redistribution line and the second redistribution line. The first molding material molds the first semiconductor device and the first conductive feature. 1. A package structure , comprising:a first dielectric layer;a first semiconductor device over the first dielectric layer;a first redistribution line in the first dielectric layer and electrically connected to the first semiconductor device;a second dielectric layer over the first semiconductor device;a second semiconductor device over the second dielectric layer;a second redistribution line in the second dielectric layer and electrically connected to the second semiconductor device;a first conductive feature electrically connecting the first redistribution line and the second redistribution line; anda first molding material molding the first semiconductor device and the first conductive feature.2. The package structure of claim 1 , wherein the first conductive feature comprises a conductive bump electrically connected to the second redistribution line.3. The package structure of claim 1 , wherein the first conductive feature comprises a conductive through-via electrically connected to the first redistribution line.4. The package structure of ...

Semiconductor structure and manufacturing method thereof

The present disclosure provides a semiconductor structure, including a substrate, a conductive pad, a passivation layer, a recess, a bump pad, and a conductive bump. The conductive pad is disposed over the substrate. The passivation layer is disposed over the substrate and partially covers the conductive pad. The recess extends through the passivation layer and extends at least partially into the conductive pad. The bump pad is disposed over the passivation layer and within the recess; and the conductive bump is disposed over the bump pad. A method of manufacturing the semiconductor structure is also provided.

SEMICONDUCTOR DEVICE ENCAPSULATED BY MOLDING MATERIAL ATTACHED TO REDISTRIBUTION LAYER

A package structure includes a first dielectric layer, a first semiconductor device over the first dielectric layer, a first redistribution line in the first dielectric layer, a second dielectric layer over the first semiconductor device, a second semiconductor device over the second dielectric layer, a second redistribution line in the second dielectric layer, a conductive through-via over the first dielectric layer and electrically connected to the first redistribution line, a conductive ball over the conductive through-via and electrically connected to the second redistribution line, and a molding material. The molding material surrounds the first semiconductor device, the conductive through-via, and the conductive ball, wherein a top of the conductive ball is higher than a top of the molding material.

IMPROVED METHOD OF MAKING A STRUCTURE FOR THE ASSEMBLY OF MICROELECTRONIC DEVICES

L'invention concerne la réalisation d'un dispositif microélectronique comprenant un substrat comportant au moins un plot conducteur ledit plot étant doté d'une face inférieure reposant sur le substrat et d'une face supérieure opposée à ladite face inférieure, ladite face supérieure dudit plot étant recouverte d'un empilement formé d'une couche conductrice et d'une couche de protection diélectrique comportant une ouverture dite première ouverture en regard dudit du plot et dévoilant ladite couche conductrice, au moins un bloc isolant (120a, 120b) étant agencé sur une zone périphérique de ladite face supérieure dudit plot, ledit bloc de isolant (120a, 120b) ayant une section transversale formant un contour fermé et comportant une ouverture dite deuxième ouverture, un pilier conducteur (130a, 130b) étant situé au centre dudit contour dans ladite deuxième ouverture. The invention relates to the production of a microelectronic device comprising a substrate comprising at least one conductive pad, said pad being provided with a lower face resting on the substrate and with an upper face opposite to said lower face, said upper face of said being covered with a stack formed of a conductive layer and a dielectric protection layer comprising an opening called the first opening facing said pad and revealing said conductive layer, at least one insulating block (120a, 120b) being arranged on a peripheral zone of said upper face of said pad, said insulating block (120a, 120b) having a cross section forming a closed contour and comprising an opening called a second opening, a conductive pillar (130a, 130b) being located at the center of said contour in said second opening.

IMPROVED METHOD OF MAKING A STRUCTURE FOR THE ASSEMBLY OF MICROELECTRONIC DEVICES

L'invention concerne la réalisation d'un dispositif microélectronique comprenant un substrat comportant au moins un plot conducteur ledit plot étant doté d'une face inférieure reposant sur le substrat et d'une face supérieure opposée à ladite face inférieure, ladite face supérieure dudit plot étant recouverte d'un empilement formé d'une couche conductrice et d'une couche de protection diélectrique comportant une ouverture dite première ouverture en regard dudit du plot et dévoilant ladite couche conductrice, au moins un bloc isolant (120a, 120b) étant agencé sur une zone périphérique de ladite face supérieure dudit plot, ledit bloc de isolant (120a, 120b) ayant une section transversale formant un contour fermé et comportant une ouverture dite deuxième ouverture, un pilier conducteur (130a, 130b) étant situé au centre dudit contour dans ladite deuxième ouverture.

Method and process for emib chip interconnections

A method for attaching an integrated circuit (IC) to an IC package substrate includes forming a solder bump on a bond pad of an IC die, forming a solder-wetting protrusion on a bond pad of an IC package substrate, and bonding the solder bump of the IC die to the solder-wetting protrusion of the IC package substrate.

Display apparatus

표시 장치는 표시 영역과 비표시 영역을 포함하는 기판, 표시 소자층, 패드 그룹, 터치 전극층, 및 터치 절연층을 포함한다. 상기 표시 소자층은 평면상에서 상기 표시 영역 내에 배치된 표시 소자들을 포함한다. 상기 패드 그룹은 기판 상에 배치되고, 평면상에서 상기 비표시 영역 내에 배치된 출력 패드들을 포함한다. 상기 터치 전극층은 상기 표시 소자층 상에 배치다. 상기 터치 절연층은 상기 표시 소자층 상에 배치되고, 상기 터치 전극층에 접촉한다. 상기 비표시 영역과 중첩하는 상기 터치 절연층에는 음각 패턴이 제공되고, 상기 음각 패턴은 상기 패드 그룹과 비중첩한다.

Metal bump and method of manufacturing same

本发明提供了一种凸块结构的实施例，包括：形成在衬底上的接触元件；覆盖衬底的钝化层，钝化层具有露出接触元件的钝化开口；覆盖钝化层的聚酰亚胺层，聚酰亚胺层具有露出接触元件的聚酰亚胺开口；电连接至接触元件的凸块下金属化层（UBM）部件，凸块下金属化层部件具有UBM宽度；以及位于凸块下金属化层部件上的铜柱，铜柱的远端具有铜柱宽度，并且UMB宽度大于铜柱宽度。本发明还提供了一种形成凸块结构的方法。

Bump structure and forming the same

本發明提供一種凸塊結構，包括：一凸塊下方金屬化(UBM)特徵結構位於一基板之上；一銅柱位於該凸塊下方金屬化(UBM)特徵結構之上，其中該銅柱具有一梯形彎曲化剖面(taping curved profile)；一金屬蓋設置於該銅柱之上；以及一焊料特徵結構設置於該金屬蓋之上。

Redistribution layer (rdl) structure, semiconductor device and manufacturing method thereof

The present disclosure provides a redistribution layer (RDL) structure, a semiconductor device and manufacturing method thereof. The semiconductor device comprises an RDL structure that may include a substrate, a first conductive layer, a reinforcement layer and a second conductive layer. The first conductive layer may be formed on the substrate and has a first bond pad area. The reinforcement layer may be formed on a surface of the first conductive layer facing away from the substrate and located in the first bond pad area. The second conductive layer may be formed on the reinforcement layer and an area of the first conductive layer not covered by the reinforcement layer. The reinforcement layer has a material strength greater than those of the first conductive layer and the second conductive layer. The semiconductor device and the manufacturing method provided by the present disclosure may improve the performance of the semiconductor device.

Display apparatus

A display apparatus includes a substrate including a display region and a non-display region, a display element layer, a pad group, a touch electrode layer, and a touch insulating layer. The display element layer includes display elements provided in the display region in a plan view. The pad group may include output pads provided on substrate and provided in the non-display region in the plan view. The touch electrode layer is provided on the display element layer. The touch insulating layer is provided on the display element layer and contacts the touch electrode layer. An intaglio pattern is provided in the touch insulating layer overlapped with the non-display region, and the intaglio pattern is not overlapped with the pad group.

Semiconductor device and method for manufacturing the same technical field

A semiconductor device includes a semiconductor element arranged to form integrated circuitry, a plurality of electrode pads formed on the side of the integrated circuitry formation surface of the in semiconductor element, bump electrodes for external connection electrically connected to the electrode pads through a conductive layer, and a stress relaxation layer formed between the integrated circuitry formation surface and electrode pads on one hand and the bump electrodes and conductive layer on the other hand, the stress relaxation layer being adhered thereto, wherein more than one third of the stress relaxation layer from a surface thereof is cut away for removal and wherein the stress relaxation layer is subdivided into a plurality of regions.

Method and process for emib chip interconnections

Method for producing a flip-chip structure for assembling microelectronic devices comprising an insulating block for guiding a connecting element and corresponding device

The method involves forming stack and protective dielectric layer having first opening, on microelectronic device. An insulating block (120a,120b) comprising second opening is formed on peripheral region above upper surface of conductive pad. A conductive pillar (130a,130b) is formed in openings. The height of conductive pillar and insulating block are provided, such that void space is maintained between top of conductive pillar and mouth region of second opening. A protective dielectric layer and the conductive layer are etched using insulating block as protective mask. An independent claim is included for a connecting microelectronic device.

Semiconductor structure and manufacturing method thereof

本发明公开了一种半导体结构及其制造方法，半导体结构包括接合的第一部件及第二部件。第一部件包括第一介电层、第一导电结构及第一填充材料层。第一导电结构位于第一介电层中且包括第一导电线及其上的第一导电衬垫。第一填充材料层位于第一导电线上且围绕第一导电衬垫。第二部件包括第二介电层、第二导电结构及第二填充材料层。将第二介电层接合至第一介电层。第二导电结构位于第二介电层中，且包括接合至第一导电衬垫的第二导电衬垫。第二填充材料层围绕第二导电衬垫且与第二导电衬垫上的第二导电线接触。本发明的半导体结构的填充材料层围绕导电衬垫，能吸收来自导电结构膨胀而产生的应力。

Semiconductor device and method for manufacturing semiconductor device

【課題】樹脂材料部分の収縮による影響を抑制するのに適した半導体装置、および半導体装置の製造方法を提供する。【解決手段】第１および第２絶縁層３１，３３を形成する工程を備え、第１絶縁層３１を形成する工程では、第１電極２１の周縁部２１１と主面とに跨って配置された第１環状部３１０を形成し、第２絶縁層３３を形成する工程は、第１環状部３１０と重なる環状をなし、かつ樹脂材料からなる第２環状部３３０を配置するステップと、第２環状部３３０を加熱するステップと、を含み、第１環状部３１０の外端境界線３１１と第２環状部３３０の外端境界線３３１との方向ｙにおける距離Ｄ１は、方向ｘの中央よりも外端境界線３３２寄りの端部において大とされ、第１環状部３１０の外端境界線３１２と第２環状部３３０の外端境界線３３２との方向ｘにおける距離Ｄ２は、方向ｙの中央よりも外端境界線３３１寄りの端部において大とされる。【選択図】図１７

Display device

Semiconductor package

본 발명의 일 실시예는, 복수의 반도체 칩들 중 적어도 하나의 반도체 칩은, 반도체 층 및 제3 면을 갖는 패시베이션층을 포함하는 반도체 기판, 제3 면 상에 배치되는 후면 패드, 및 반도체 기판을 관통하는 관통 비아를 포함하고, 후면 패드는 제3 면 상에 배치되는 전극 패드부 및 전극 패드부의 일측에서 돌출되며 관통 비아의 측면을 둘러싸는 댐(dam) 구조를 포함하고, 댐 구조는 관통 비아의 측면과 이격되는 반도체 패키지를 제공한다.

Semiconductor device and semiconductor device manufacturing method

【課題】半導体装置の特性を向上させる。【解決手段】配線Ｍ１上に形成され、開口部ＯＡ１を有する保護膜ＰＲＯ１と、開口部ＯＡ１内に形成されためっき膜ＯＰＭ１とを有するように半導体装置を構成する。そして、開口部ＯＡ１の側面には、スリットＳＬが設けられ、このスリットＳＬ内にもめっき膜ＯＰＭ１が配置されている。このように、開口部ＯＡ１の側面に、スリットＳＬを設け、その内部にもめっき膜ＯＰＭ１を成長させることにより、以降のめっき膜の形成時において、めっき液の侵入経路が長くなる。このため、配線（パッド領域ＰＤ）Ｍ１に腐食部が生じにくくなる。また、腐食部が生じた場合でも、スリットＳＬの部分が、配線（パッド領域ＰＤ）Ｍ１より先に犠牲となって腐食するため、配線（パッド領域ＰＤ）Ｍ１まで腐食部が進行することを抑制することができる。【選択図】図１

Encapsulating structure

封装结构包括第一介电层、第一半导体装置、第一重分布线、第二介电层、第二半导体装置、第二重分布线、第一导电件及第一模制材料。第一半导体装置在第一介电层上方。第一重分布线在第一介电层中且电连接至第一半导体装置。第二介电层在第一半导体装置上方。第二半导体装置在第二介电层上方。第二重分布线在第二介电层中且电连接至第二半导体装置。第一导电件电连接第一重分布线与第二重分布线。第一模制材料模制第一半导体装置及第一导电件。

Semiconductor device and fabricating method thereof

A semiconductor device and a fabrication method thereof are provided. An electrically conductive elastic member is formed on a semiconductor die, and a conductive bump is formed on the elastic member. Accordingly, since the conductive bump is formed on the elastic member, or to protrude from a top surface of the elastic member, the height and thus diameter of the conductive bump is reduced allowing a fine pitch to be realized. Further, the elastic member is elastic and thus mitigates external impacts from being transferred from the conductive bump to the semiconductor die.

Electrical apparatus having electrical pattern capable of preventing solder bridge

본 발명은 솔더 브릿지를 억제할 수 있는 전기적 패턴을 갖는 전기적 장치에 관한 것으로, 기판 상에 배열된 복수개의 전기적 패턴을 포함한다. 상기 전기적 패턴은, 솔더볼이 접속되는 패드; 상기 패드의 일측으로부터 연장되어 전기적 신호를 상기 패드로 전달하는 전기적 트레이스, 상기 패드의 다른 일측으로부터 연장된 제1 더미 트레이스, 및 상기 제1 더미 트레이스를 상기 전기적 트레이스를 연결하는 제1 연결선을 포함한다. 상기 제1 더미 트레이스는 상기 패드를 사이에 두고 상기 전기적 트레이스를 일직선상으로 마주보지 않는다. The present invention relates to an electrical device having an electrical pattern capable of suppressing solder bridges, comprising a plurality of electrical patterns arranged on a substrate. The electrical pattern may include a pad to which a solder ball is connected; an electrical trace extending from one side of the pad to transmit an electrical signal to the pad, a first dummy trace extending from the other side of the pad, and a first connection line connecting the first dummy trace to the electrical trace . The first dummy trace does not face the electrical trace in a straight line with the pad interposed therebetween.

Cmos sensors and methods of forming the same

CMOS 센서 및 그 형성 방법이 개시된다. CMOS 센서는 반도체 기판, 유전체 층, 상호접속부, 본딩 패드 및 더미 패턴을 포함한다. 반도체 기판은 화소 영역 및 회로 영역을 가진다. 유전체 층은 회로 영역에서 반도체 기판에 의해 둘러싸인다. 상호접속부는 회로 영역 내의 유전체 층 위에 배치된다. 본딩 패드는 유전체 층 내에 배치되고, 회로 영역의 상호접속부를 전기적으로 접속시킨다. 더미 패턴은 유전체 층 내에 배치되고, 회로 영역 내의 본딩 패드를 둘러싼다.

Semiconductor package and method of fabricating the same

A semiconductor package including a first semiconductor die, a second semiconductor die, a first insulating encapsulation, a dielectric layer structure, a conductor structure and a second insulating encapsulation is provided. The first semiconductor die includes a first semiconductor substrate and a through silicon via (TSV) extending from a first side to a second side of the semiconductor substrate. The second semiconductor die is disposed on the first side of the semiconductor substrate. The first insulating encapsulation on the second semiconductor die encapsulates the first semiconductor die. A terminal of the TSV is coplanar with a surface of the first insulating encapsulation. The dielectric layer structure covers the first semiconductor die and the first insulating encapsulation. The conductor structure extends through the dielectric layer structure and contacts with the through silicon via. The second insulating encapsulation contacts with the second semiconductor die, the first insulting encapsulation, and the dielectric layer structure.

Semiconductor devices having crack-inhibiting structures

Semiconductor devices having metallization structures including crack-inhibiting structures, and associated systems and methods, are disclosed herein. In one embodiment, a semiconductor device includes a metallization structure formed over a semiconductor substrate. The metallization structure can include a bond pad electrically coupled to the semiconductor substrate via one or more layers of conductive material, and an insulating material—such as a low-κ dielectric material—at least partially around the conductive material. The metallization structure can further include a crack-inhibiting structure positioned beneath the bond pad between the bond pad and the semiconductor substrate. The crack-inhibiting structure can include a barrier member extending vertically from the bond pad toward the semiconductor substrate and configured to inhibit crack propagation through the insulating material.

Display device

提供了一种显示装置。所述显示装置包括：基底，包括显示区域和非显示区域；信号线；显示元件层；垫组；中间绝缘层；触摸电极层；以及触摸绝缘层。信号线设置在基底上。显示元件层设置在信号线上并且包括在平面图中设置在显示区域中的显示元件。垫组可以包括输出垫，所述输出垫设置在基底上并且在平面图中设置在非显示区域中。中间绝缘层设置在信号线与显示元件层之间并且暴露输出垫。触摸电极层设置在显示元件层上。触摸绝缘层设置在显示元件层上并接触触摸电极层，并且在平面图中限定位于非显示区域中的凹版图案。凹版图案在平面图中位于输出垫和中间绝缘层之间。

Bonded assemblies with pre-deposited polymer balls on demarcated areas and methods of forming such bonded assemblies

A method of forming a bonded assembly is described. A liquid-based dispersion of fine polymer balls (< 50 μm diameter) is applied to a first substrate (16) having a plurality of demarcated areas (14) of width less than five ball diameters. The balls (12) are urged into registration through an electrical, chemical or physical stimulus, and the liquid from the dispersion is removed to leave the polymer balls in the demarcated areas. The first substrate is aligned with respect to a second substrate (18) and pressed together to partially compress the polymer balls. The geometry of the assembly is fixed by bonding the assembly. In preferred embodiments the balls (12) have a diameter of between 2-6 μm and they are urged into place using electrophoresis and surface tension. The polymer balls may be coated in Au and In and placed as individual balls on the substrate.

Semiconductor package and method of fabricating the same

A semiconductor package including a first semiconductor die, a second semiconductor die, a first insulating encapsulation, a dielectric layer structure, a conductor structure and a second insulating encapsulation is provided. The first semiconductor die includes a first semiconductor substrate and a through silicon via (TSV) extending from a first side to a second side of the semiconductor substrate. The second semiconductor die is disposed on the first side of the semiconductor substrate. The first insulating encapsulation on the second semiconductor die encapsulates the first semiconductor die. A terminal of the TSV is coplanar with a surface of the first insulating encapsulation. The dielectric layer structure covers the first semiconductor die and the first insulating encapsulation. The conductor structure extends through the dielectric layer structure and contacts with the through silicon via. The second insulating encapsulation contacts with the second semiconductor die, the first insulting encapsulation, and the dielectric layer structure.

显示面板以及包括其的显示装置

本发明公开一种显示面板以及包括其的显示装置。显示面板可以包括：基板，包括显示区域以及位于显示区域的周边的焊盘区域；多个像素，配置于基板上的显示区域；以及多个焊盘，配置于基板上的焊盘区域并与多个像素电连接。多个焊盘各自可以包括：第一导电层；第一凸出部，配置于第一导电层上；第二凸出部，配置于第一导电层上并具有小于第一凸出部的厚度的厚度；以及第二导电层，配置于第一导电层上并覆盖第一凸出部以及第二凸出部各自的上面。

Solderless interconnection structure and method of forming same

An embodiment bump on trace (BOT) structure includes a contact element supported by an integrated circuit, an under bump metallurgy (UBM) feature electrically coupled to the contact element, a metal ladder bump mounted on the under bump metallurgy feature, the metal ladder bump having a first tapering profile, and a substrate trace mounted on a substrate, the substrate trace having a second tapering profile and coupled to the metal ladder bump through direct metal-to-metal bonding. An embodiment chip-to-chip structure may be fabricated in a similar fashion.

백라이트 유닛 및 이를 포함하는 디스플레이 장치

본 개시의 실시예들은, 백라이트 유닛 및 이를 포함하는 디스플레이 장치에 관한 것으로서, 더욱 상세하게는, 유리 기판 상에 배치되고 다수의 행과 다수의 열에 배치된 다수의 광원, 유리 기판 상에 배치되고 서로 이격된 제1 및 제2 트랜지스터를 포함하며, 하나의 제1 트랜지스터와 하나의 제2 트랜지스터 각각은 두 개의 행과 두 개의 열이 교차하는 지점에 배치된 다수의 광원들과 미 중첩하도록 배치됨으로써, 화상 품위가 우수한 백라이트 유닛 및 이를 포함하는 디스플레이 장치를 제공할 수 있다.

Polyimide profile control

A structure includes a controlled polyimide profile. A method for forming such a structure includes depositing, on a substrate, a photoresist containing polyimide and performing a first anneal at a first temperature. The method further includes exposing the photoresist to a radiation source through a photomask having a pattern associated with a shape of a polyimide opening. The method further includes performing a second anneal at a second temperature and removing a portion of the photoresist to form the polyimide opening. The method further includes performing a third anneal at a third temperature and cleaning the polyimide opening by ashing.

Redistribution layer (rdl) structure and method of manufacturing the same

Provided is a redistribution layer (RDL) structure including a substrate, a pad, a dielectric layer, a self-aligned structure, a conductive layer, and a conductive connector. The pad is disposed on the substrate. The dielectric layer is disposed on the substrate and exposes a portion of the pad. The self-aligned structure is disposed on the dielectric layer. The conductive layer extends from the pad to conformally cover a surface of the self-aligned structure. The conductive connector is disposed on the self-aligned structure. A method of manufacturing the RDL structure is also provided.

半導體封裝及其製造方法

本發明揭示半導體封裝以及製造半導體封裝的方法。作為非限制性的範例，本揭示的各種態樣提供各種半導體封裝以及製造半導體封裝的各種方法，其包括導體層，導體層包括延伸經由至少一個介電層的錨定部分。

Electrical component with component interconnection element

An electrical component including a substrate, a first dielectric layer on the substrate, a redistribution layer pad on the first dielectric layer, and a component interconnection element on the redistribution layer pad so that the component interconnection element fills an opening in the second dielectric layer. The opening includes at least one protrusion between the component interconnection element solder ball metallization and the redistribution layer pad.

晶片级封装和方法

一种铜柱凸块半导体封装方法将形成在铜柱凸块下方的有机绝缘层仅图案化到围绕铜柱凸块和在铜柱凸块附近的区域。通常为薄膜聚合物层的有机绝缘层用作铜柱凸块的阻挡层，以在铜柱倒装芯片接合工艺期间保护半导体晶片。铜柱凸块半导体封装方法限制了施加有机绝缘层的区域，以减少由有机绝缘层引入到半导体晶片的应力。在另一个实施例中，一种铜柱凸块半导体封装方法将形成在铜柱凸块下方的有机绝缘层图案化到围绕铜柱凸块并沿着再分布层的路径的区域，而不使用大的且连续的有机绝缘层。

Electrical component with component interconnection element

An electrical component including a substrate, a first dielectric layer on the substrate, a redistribution layer pad on the first dielectric layer, and a component interconnection element on the redistribution layer pad so that the component interconnection element fills an opening in the second dielectric layer. The opening includes at least one protrusion between the component interconnection element solder ball metallization and the redistribution layer pad.

인터포저, 이의 제조 방법, 및 이를 가지는 반도체 패키지

본 발명에 따른 인터포저는, 서로 반대되는 제1 면과 제2 면을 가지는 베이스층, 베이스층의 제1 면 상의 배선 구조물, 베이스층의 제2 면 상에 배치되고 제1 수직 레벨에 위치하는 하면 및 제1 수직 레벨보다 높은 제2 수직 레벨에 위치하는 저면을 가지는 패드 리세스를 가지는 인터포저 보호층, 일부분이 인터포저 보호층의 패드 리세스를 채우고 나머지 부분이 인터포저 보호층의 외측으로 돌출되는 인터포저 패드, 및 베이스층 및 인터포저 보호층을 관통하여 인터포저 패드 내로 연장되고 배선 구조물과 인터포저 패드를 전기적으로 연결하는 인터포저 관통 전극을 포함한다.

CMOS-Sensoren und Verfahren zur Bildung derselben

CMOS-Sensor, umfassend:ein Halbleitersubstrat (110), das eine Pixelregion (112) und eine Schaltkreisregion (114) aufweist;eine dielektrische Lage (122), die durch das Halbleitersubstrat (110) in der Schaltkreisregion (114) umgeben ist;eine Verbindung (130) über der dielektrischen Lage (122) in der Schaltkreisregion (114);ein Bonding-Pad (152), das in der dielektrischen Lage (122) angeordnet ist und die Verbindung (130) in der Schaltkreisregion (114) elektrisch verbindet; undeine Dummystruktur (154), die in der dielektrischen Lage (122) angeordnet ist und das Bonding-Pad (152) in der Schaltkreisregion (114) umgibt.

Semiconductor device with spacer over sidewall of bonding pad and method for preparing the same

The present application provides a semiconductor device and a method for preparing the semiconductor device. The semiconductor device includes a bonding pad disposed over a semiconductor substrate, and a first spacer disposed over a sidewall of the bonding pad. The semiconductor device also includes a first passivation layer covering the bonding pad and the first spacer, and a conductive bump disposed over the first passivation layer. The conductive bump is electrically connected to a source/drain region in the semiconductor substrate through the bonding pad.

显示装置

提供了一种显示装置。所述显示装置包括：基底，包括显示区域和非显示区域；信号线；显示元件层；垫组；中间绝缘层；触摸电极层；以及触摸绝缘层。信号线设置在基底上。显示元件层设置在信号线上并且包括在平面图中设置在显示区域中的显示元件。垫组可以包括输出垫，所述输出垫设置在基底上并且在平面图中设置在非显示区域中。中间绝缘层设置在信号线与显示元件层之间并且暴露输出垫。触摸电极层设置在显示元件层上。触摸绝缘层设置在显示元件层上并接触触摸电极层，并且在平面图中限定位于非显示区域中的凹版图案。凹版图案在平面图中位于输出垫和中间绝缘层之间。

Packaged Semiconductor Devices And Methods of Packaging Thereof

Packaging methods for semiconductor devices and methods of packaging thereof are disclosed. In some embodiments, a device includes a packaging apparatus and contact pads disposed on the packaging apparatus. The contact pads are arranged in an array of rows and columns. The contact pads include first contact pads proximate a perimeter region of the packaging apparatus and second contact pads disposed in an interior region of the packaging apparatus. A dam structure that is continuous is disposed around the second contact pads. The contact pads comprise a mounting region for a semiconductor device.

半导体器件、半导体部件和制造半导体器件的方法

半导体器件、半导体部件和制造半导体器件的方法。在实施例中，半导体器件包括半导体本体，该半导体本体包括第一主表面、与第一主表面相对的第二主表面和至少一个晶体管器件结构，布置在第一主表面上的源极焊盘和栅极焊盘，耦合到另外的器件结构的漏极焊盘和至少一个另外的接触焊盘。漏极焊盘和至少一个另外的接触焊盘布置在第二主表面上。

Display device and method for manufacturing display device

Semiconductor devices having crack-inhibiting structures

Semiconductor devices having metallization structures including crack-inhibiting structures, and associated systems and methods, are disclosed herein. In one embodiment, a semiconductor device includes a metallization structure formed over a semiconductor substrate. The metallization structure can include a bond pad electrically coupled to the semiconductor substrate via one or more layers of conductive material, and an insulating material—such as a low-κ dielectric material—at least partially around the conductive material. The metallization structure can further include a crack-inhibiting structure positioned beneath the bond pad between the bond pad and the semiconductor substrate. The crack-inhibiting structure can include a barrier member extending vertically from the bond pad toward the semiconductor substrate and configured to inhibit crack propagation through the insulating material.

Semiconductor Device and Method of Manufacture

A semiconductor device and method of manufacture are presented in which a first pad and a second pad are formed adjacent to each other. A first set of dummy pads is manufactured between the first pad and the second pad and bonding pads are formed in electrical connection to the first pad and the second pad.

显示装置

提供了一种显示装置。所述显示装置包括：基底，包括显示区域和与显示区域相邻的非显示区域；像素，设置在显示区域中，并且连接到数据线；输出垫线，连接到像素；输出垫，连接到输出垫线；驱动电路芯片，设置在非显示区域中；封装层，覆盖像素；以及触摸传感器，设置在封装层上，并且触摸传感器包括触摸绝缘层和触摸电极层，触摸绝缘层包括通过穿透触摸绝缘层限定的第一凹版图案，其中，输出垫线穿过第一凹版图案连接到输出垫。

Front end of line interconnect structures and associated systems and methods

Systems and methods for a semiconductor device having a front-end-of-line interconnect structure are provided. The semiconductor device may include a dielectric material having a backside formed on a front side of a semiconductor or silicon substrate material and a front side, and a conducting material on the front side of the dielectric material. The conducting material may have a line portion and an interconnect structure electrically coupled to the line portion and separated from the front side of the substrate material by the dielectric material. The interconnect structure has a backside defining a contact surface. The semiconductor device may further include a semiconductor die proximate the front side of the dielectric material, an insulating material encasing at least a portion of the semiconductor die, and an opening through which the active contact surface at the backside of the interconnect structure is exposed for electrical connection.

반도체 패키지

반도체 패키지를 제공한다. 반도체 패키지는, 기판 패드를 포함하는 회로 기판, 회로 기판과 마주하며 이격되어 배치되며, 칩 패드를 포함하는 반도체 칩 및 회로 기판 및 반도체 칩을 전기적으로 연결하는 연결 패턴을 포함한다. 반도체 칩은, 상기 반도체 칩 내에, 반도체 칩의 상면에 대하여 수직하게 배치되는 다수의 제1 회로 패턴들과, 칩 패드 및 제1 회로 패턴들을 전기적으로 연결하는 제1 비아를 포함한다. 칩 패드는, 연결 패턴이 접촉되는 제1 영역 및 제1 영역의 외각의 제2 영역을 포함하되, 제1 비아는 상기 제2 영역에 연결된다.

Semiconductor device encapsulated by molding material attached to redistribution layer

A package structure includes a first dielectric layer, a first semiconductor device over the first dielectric layer, a first redistribution line in the first dielectric layer, a second dielectric layer over the first semiconductor device, a second semiconductor device over the second dielectric layer, a second redistribution line in the second dielectric layer, a conductive through-via over the first dielectric layer and electrically connected to the first redistribution line, a conductive ball over the conductive through-via and electrically connected to the second redistribution line, and a molding material. The molding material surrounds the first semiconductor device, the conductive through-via, and the conductive ball, wherein a top of the conductive ball is higher than a top of the molding material.

Semiconductor package

The present disclosure provides a semiconductor package including a semiconductor chip and a package substrate. The semiconductor chip includes a substrate, a plurality of conductive pads in the substrate, and a plurality of conductive bumps. Each of the conductive bumps is over corresponding conductive pad. At least one of the conductive bumps proximity to an edge of the semiconductor chip is in contact with at least two discrete regions of the corresponding conductive pad. The package substrate has a concave surface facing the semiconductor chip and joining the semiconductor chip through the plurality of conductive bumps.

Wafer level package and method

A copper pillar bump semiconductor packaging method patterns an organic insulation layer formed under the copper pillar bumps to areas surrounding and in the vicinity of the copper pillar bumps only. The organic insulation layer, typically a thin film polymer layer, acts as a barrier layer for the copper pillar bumps to protect the semiconductor wafer during the copper pillar flip chip bonding process. The copper pillar bump semiconductor packaging method limits the areas where the organic insulation layer is applied to reduce the stress introduced to the semiconductor wafer by the organic insulation layer. In another embodiment, a copper pillar bump semiconductor packaging method patterns an organic insulation layer formed under the copper pillar bumps to areas surrounding the copper pillar bumps and along the path of a redistribution layer without using a large and continuous organic insulation layer.

Wafer level package and method

A copper pillar bump semiconductor packaging method patterns an organic insulation layer formed under the copper pillar bumps to areas surrounding and in the vicinity of the copper pillar bumps only. The organic insulation layer, typically a thin film polymer layer, acts as a barrier layer for the copper pillar bumps to protect the semiconductor wafer during the copper pillar flip chip bonding process. The copper pillar bump semiconductor packaging method limits the areas where the organic insulation layer is applied to reduce the stress introduced to the semiconductor wafer by the organic insulation layer. In another embodiment, a copper pillar bump semiconductor packaging method patterns an organic insulation layer formed under the copper pillar bumps to areas surrounding the copper pillar bumps and along the path of a redistribution layer without using a large and continuous organic insulation layer.

半导体装置

实施方式提供一种能够确保各晶片间的接合强度及导通性的半导体装置。实施方式的半导体装置具有第1晶片、第1配线层、第1绝缘层、第1电极、第2晶片、第2配线层、第2绝缘层、第2电极和第1层。第1电极具有第1面、第2面、第3面及第4面。第2电极具有第5面、第6面、第7面、第2侧面及第8面。第1层设于第4面与第1绝缘层中的将第4面包围的部分之间，从第3面在第1方向上远离而设置。

Bonded assemblies with pre-deposited polymer balls on demarcated areas and methods of forming such bonded assemblies

Front end of line interconnect structures and associated systems and methods

Systems and methods for a semiconductor device having a front-end-of-line interconnect structure are provided. The semiconductor device may include a dielectric material having a backside formed on a front side of a semiconductor or silicon substrate material and a front side, and a conducting material on the front side of the dielectric material. The conducting material may have a line portion and an interconnect structure electrically coupled to the line portion and separated from the front side of the substrate material by the dielectric material. The interconnect structure has a backside defining a contact surface. The semiconductor device may further include a semiconductor die proximate the front side of the dielectric material, an insulating material encasing at least a portion of the semiconductor die, and an opening through which the active contact surface at the backside of the interconnect structure is exposed for electrical connection.