Interconnect structure comprising fine pitch backside metal redistribution lines combined with vias

A 3D interconnect structure and method of manufacture are described in which metal redistribution layers (RDLs) are integrated with through-silicon vias (TSVs) and using a “plate through resist” type process flow. A silicon nitride or silicon carbide passivation layer may be provided between the thinned device wafer back side and the RDLs to provide a hermetic barrier and polish stop layer during the process flow.

INTERCONNECT STRUCTURE COMPRISING FINE PITCH BACKSIDE METAL REDISTRIBUTION LINES COMBINED WITH VIAS

금속 재분포 층들(RDL들)이 TSV들과 통합되고 "레지스트를 통한 도금" 유형의 공정 흐름을 이용하는 3D 상호접속 구조 및 제조 방법이 기술된다. 이 공정 흐름 동안 기밀 장벽 및 연마 정지 층을 제공하기 위해서 실리콘 질화물 또는 실리콘 탄화물 패시베이션 층이 박화 장치 웨이퍼 후면측과 RDL들 사이에 제공될 수 있다. Metal redistribution layers (RDLs) are integrated with TSVs and a 3D interconnect structure and manufacturing method using a “plating through resist” type process flow is described. A silicon nitride or silicon carbide passivation layer may be provided between the thinner wafer backside and the RDLs to provide an airtight barrier and abrasive stop layer during this process flow.

ELECTROLESS NICKEL AND GOLD PLATING IN SEMICONDUCTOR DEVICE

A described example semiconductor device includes a passivation layer (230) formed over a semiconductor substrate (210) and a portion of a metal contact pad (220). Nickel is deposited over the passivation layer and metal contact pad and gold is deposited over the nickel using an ENIG electroless plating process. The nickel includes a first non-porous nickel region (layer 250A) free of porous nickel at an interface (180) of the nickel with the passivation layer and at a junction (290) of the nickel with the passivation layer and metal contact pad. The nickel also includes a porous nickel region (layer 270) over the first nickel layer (250A). A gold region (layer 260) is over the porous nickel layer (270). A second non-porous nickel region (layer 250B) may be between the porous nickel region and the gold region. A gold-rich nickel region (275) may be between the porous nickel region and the gold region. Relative thicknesses of the deposited nickel and the deposited gold are chosen to prevent corrosion of the nickel layer from reaching the device layer during the electroless gold plating process.

Barrierestrukturen zwischen externen elektrischen Anschlussteilen

Eine Struktur umfasst ein Die-Substrat; eine Passivierungsschicht auf dem Die-Substrat; eine erste und eine zweite Verbindungsstruktur auf der Passivierungsschicht; und eine Barriere auf der Passivierungsschicht, mindestens der ersten oder der zweiten Verbindungsstruktur oder einer Kombination daraus. Die erste und die zweite Verbindungsstruktur umfassen einen ersten und einen zweiten Via-Abschnitt durch die Passivierungsschicht zu einem ersten bzw. einem zweiten leitenden Merkmal des Die-Substrats. Die erste und die zweite Verbindungsstruktur umfassen weiter ein erstes bzw. ein zweites Pad und ein erstes bzw. ein zweites Übergangselement auf einer Oberfläche der Passivierungsschicht zwischen dem ersten und dem zweiten Via-Abschnitt und dem ersten und dem zweiten Pad. Die Barriere ist zwischen dem ersten Pad und dem zweiten Pad angeordnet. Die Barriere umgibt mindestens das erste Pad oder das zweiten Pad nicht vollständig.

Method for manufacture of wire bondable and solderable surfaces on noble metal electrodes

The present invention relates to a method for manufacture of wire bondable and solderable surfaces on noble metal electrodes. The noble metal electrodes are activated by depositing a seed layer of palladium or a palladium alloy layer by electroless plating at 60 to 90° C. Next, an intermediate layer is deposited onto the seed layer followed by deposition of the wire bondable and/or solderable surface finish layer(s) onto the intermediate layer. This method is particularly suitable in the production of optoelectronic devices such as light emitting diodes (LEDs).

ELECTROLESS PLATING A NICKLE LAYER AND A GOLD LAYER IN A SEMICONDUCTOR DEVICE

A method and resulting device for maintaining non-porous nickel layer at a nickel/passivation interface of a semiconductor device in a nickel/gold electroless plating process. The method can include determining a thickness of a gold layer of the semiconductor device; determining an electroless plating rate and plating time of the gold layer to reach the determined thickness; determining a thickness of nickel under the gold layer to maintain the non-porous nickel layer at the nickel/passivation interface at a termination of an electroless gold plating process; and following the determinations, sequentially electroless plating of each of the nickel layer and gold layer on the device layer to the determined thicknesses.

METHOD FOR SELF-ALIGNED SOLDER REFLOW BONDING AND DEVICES OBTAINED THEREOF

A method for producing a stack of semiconductor devices and the stacked device obtained thereof are disclosed. In one aspect, the method includes providing a first semiconductor device comprising a dielectric layer with a hole, the hole lined with a metal layer and partially filled with solder material. The method also includes providing a second semiconductor device with a compliant layer having a metal protrusion through the compliant layer, the protrusion capped with a capping layer. The method further includes mounting the devices by landing the metal protrusion in the hole, where the compliant layer is spaced from the dielectric layer. The method includes thereafter reflowing the solder material, thereby bonding the devices such that the compliant layer is contacting the dielectric layer.

Robuste Intermetallische-Verbindung-Schicht-Grenzfläche für ein Gehäuse in einer Gehäuseeinbettung

Ausführungsformen können ein eingebettetes Gehäuse mit einer Diffusionsbarriereschicht betreffen, die zwischen einem Kupfer(Cu)-Pad und einer Lötkugel innerhalb des eingebetteten Gehäuses platziert ist. Während des Lotaufschmelzprozesses wird eine Intermetallische-Verbindung(IMC)-Schicht erzeugt, die nicht mit dem Cu in Kontakt kommt, so dass anschließende hohe Temperaturen, die auf das eingebettete Gehäuse angewandt werden, möglicherweise nicht bewirken, dass das Cu durch Diffusion verbraucht wird. Andere Ausführungsformen können beschrieben und/oder beansprucht werden.

Power device and power device module

According to example embodiments of inventive concepts, a power device includes a semiconductor structure having a first surface facing a second surface, an upper electrode, and a lower electrode. The upper electrode may include a first contact layer that is on the first surface of the semiconductor structure, and a first bonding pad layer that is on the first contact layer and is formed of a metal containing nickel (Ni). The lower electrode may include a second contact layer that is under the second surface of the semiconductor structure, and a second bonding pad layer that is under the second contact layer and is formed of a metal containing Ni.

POWER DEVICE AND POWER DEVICE MODULE

According to example embodiments of inventive concepts, a power device includes a semiconductor structure having a first surface facing a second surface, an upper electrode, and a lower electrode. The upper electrode may include a first contact layer that is on the first surface of the semiconductor structure, and a first bonding pad layer that is on the first contact layer and is formed of a metal containing nickel (Ni). The lower electrode may include a second contact layer that is under the second surface of the semiconductor structure, and a second bonding pad layer that is under the second contact layer and is formed of a metal containing Ni.

Acoustic wave resonator and method for manufacturing the same

An acoustic wave resonator includes: a substrate; a resonating portion formed on a first surface of the substrate; a metal pad connected to the resonating portion through a via hole formed in the substrate; and a protective layer disposed on a second surface of the substrate and including a plurality of layers, wherein the plurality of layers includes an internal protective layer directly in contact with the second surface of the substrate and formed of an insulating material including an adhesion that is stronger than an adhesion of other layers, among the plurality of layers.

전력 소자 모듈 및 그 제조 방법

본 개시는 전력 소자 및 전력 소자 모듈에 관한 것으로, 보다 구체적으로는 향상된 전기적 연결을 위한 전극을 갖는 전력 소자, 이를 포함하는 전력 소자 모듈에 대한 것이다. 본 발명의 일 실시예에 따르면, 서로 마주하는 제1면과 제2면을 갖는 반도체 구조체; 상기 제1면 상에 마련된 제1접촉층, 상기 제1접촉층 상에 마련되며 니켈(Ni)을 포함하는 금속으로 이루어진 제1본딩 패드층을 포함하는 상부 전극; 및 상기 제2면 상에 마련된 제2접촉층, 상기 제2접촉층 상에 마련된 니켈(Ni)을 포함하는 금속으로 이루어진 제2본딩 패드층을 포함하는 하부 전극;을 포함하는 전력 소자를 제공한다.

Method of fabricating bump structure

本发明揭示一种半导体装置及其制造方法。该制造方法包括：提供具有一金属垫区的一半导体基底；在该半导体基底上形成一封盖(encapsulating)层，其中该封盖层具有一开口露出该金属垫区的一部分；在该封盖层的该开口内露出的该金属垫区的该部分上形成一凸块下金属层(under-bump？metallurgy,UBM)；在该凸块下金属层上形成一凸块(bump)层，以填入该封盖层的该开口且延伸至该封盖层的一上表面；自该封盖层的该上表面去除该凸块层；去除该封盖层的该上表面，直至该凸块层的一顶部突出于该封盖层；以及进行一缓冲工艺，以轻微研磨该半导体基底，使该封盖层的厚度达到最终目标厚度。本发明可避免UBM底切问题。

Semiconductor device and method for fabricating the same

Method for forming stacked metal contact in electrical communication with aluminum wiring in semiconductor wafer of integrated circuit

A method for forming a stacked metal contact in electrical communication with aluminum wiring in a semiconductor wafer of an integrated circuit is disclosed. The method includes the steps of: forming at least one passivation layer on a surface of the semiconductor wafer of the integrated circuit, where an aluminum wiring is embedded; forming a patterned terminal via opening through the passivation layer to expose the aluminum wiring; removing a portion of the aluminum wiring from the patterned terminal via opening by chemical etching and forming a thin zinc film on an etched surface at the same time; forming a nickel film stacked on the zinc film; and; and forming a metal stack in the patterned terminal via opening and/or at least a portion of the passivation layer by chemical plating or metal plating.

Interconnect structure comprising fine pitch backside metal redistribution lines combined with vias

NANO COPPER PASTE AND FILM FOR SINTERED DIE ATTACH AND SIMILAR APPLICATIONS

Repackaged integrated circuit and assembly method

A packaged integrated circuit for operating reliably at elevated temperatures is provided. The packaged integrated circuit includes a reconditioned die, which includes a fully functional semiconductor die that has been previously extracted from a different packaged integrated circuit. The packaged integrated circuit also includes a hermetic package comprising a base and a lid and a plurality of bond wires. The reconditioned die is placed into a cavity in the base. After the reconditioned die is placed into the cavity, the plurality of bond wires are bonded between pads of the reconditioned die and package leads of the hermetic package base or downbonds. After bonding the plurality of bond wires, the lid is sealed to the base. 1. A packaged integrated circuit for operating reliably at elevated temperatures , comprising:a reconditioned die, wherein the reconditioned die comprises a fully functional semiconductor die that has been previously extracted from a different packaged integrated circuit;a hermetic package comprising a base and a lid; anda plurality of bond wires;wherein the reconditioned die is placed into a cavity in the base, wherein after the reconditioned die is placed into the cavity, the plurality of bond wires are bonded between pads of the reconditioned die and package leads of the hermetic package base or downbonds, wherein after bonding the plurality of bond wires, the lid is sealed to the base.2. The packaged integrated circuit as recited in claim 1 , wherein a low halide content die attach adhesive is applied to the cavity prior to placing the reconditioned die in the cavity claim 1 , wherein the low-halide content die attach adhesive bonds the reconditioned die to the base.3. The packaged integrated circuit as recited in claim 1 , wherein the reconditioned die comprises a modified extracted die with reconditioned die pads claim 1 , wherein a modified extracted die is an extracted die with ball bonds and bond wires removed claim 1 , wherein ...

Interconnect structure comprising fine pitch backside metal redistribution lines combined with vias

A 3D interconnect structure and method of manufacture are described in which metal redistribution layers (RDLs) are integrated with through-silicon vias (TSVs) and using a "plate through resist" type process flow. A silicon nitride or silicon carbide passivation layer may be provided between the thinned device wafer back side and the RDLs to provide a hermetic barrier and polish stop layer during the process flow.

Repackaged integrated circuit and assembly method

A packaged integrated circuit for operating reliably at elevated temperatures is provided. The packaged integrated circuit includes a reconditioned die, which includes a fully functional semiconductor die that has been previously extracted from a different packaged integrated circuit. The packaged integrated circuit also includes a hermetic package comprising a base and a lid and a plurality of bond wires. The reconditioned die is placed into a cavity in the base. After the reconditioned die is placed into the cavity, the plurality of bond wires are bonded between pads of the reconditioned die and package leads of the hermetic package base or downbonds. After bonding the plurality of bond wires, the lid is sealed to the base.

Post-passivation interconnect structure and method of forming the same

A semiconductor device includes a conductive layer formed on the surface of a post-passivation interconnect (PPI) structure by an immersion tin process. A polymer layer is formed on the conductive layer and patterned with an opening to expose a portion of the conductive layer. A solder bump is then formed in the opening of the polymer layer to electrically connect to the PPI structure.

UNDER-BUMP METALLIZATION (UBM) STRUCTURE AND METHOD OF FORMING THE SAME

An under-bump metallization (UBM) structure in a semiconductor device includes a copper layer, a nickel layer, and a CuNiSn intermetallic compound (IMC) layer between the copper layer and the nickel layer.

Electroless plating of porous and non-porous nickel layers, and gold layer in semiconductor device

A method for maintaining non-porous nickel layer at a nickel/passivation interface of a semiconductor device in a nickel/gold electroless plating process. The method can include sequentially electroless plating of each of the nickel layer and gold layer on the device layer to pre-determined thicknesses to prevent corrosion of the nickel layer from reaching the device layer during the electroless gold plating process.

Remapped Packaged Extracted Die

A remapped extracted die is provided. The remapped extracted die includes an extracted die removed from a previous integrated circuit package. The extracted die includes a plurality of original bond pads having locations that do not correspond to desired pin assignments of a new package base and an interposer, bonded to the extracted die. The interposer includes first bond pads configured to receive new bond wires from the plurality of original bond pads, and second bond pads corresponding to desired pin assignments of the new package base, each individually electrically coupled to one of the first bond pads and configured to receive new bond wires from package leads or downbonds of the new package base. 1. A remapped extracted die , comprising:an extracted die removed from a previous integrated circuit package, the extracted die comprising a plurality of original bond pads having locations that do not correspond to desired pin assignments of a new package base; and first bond pads configured to receive new bond wires from the plurality of original bond pads; and', 'second bond pads corresponding to desired pin assignments of the new package base, each individually electrically coupled to one of the first bond pads and configured to receive new bond wires from package leads or downbonds of the new package base., 'an interposer, bonded to the extracted die, comprising2. The remapped extracted die of claim 1 , wherein locations that do not correspond to desired pin assignments of a new package base comprises bond pad locations for new bond wires that cross other new bond wires if the extracted die is bonded to the new package base without the interposer.3. The remapped extracted die of claim 1 , wherein a pinout of the previous integrated circuit package is different than a pinout of the new package base.4. A packaged integrated circuit claim 1 , comprising:an extracted die removed from a previous packaged integrated circuit;a new package base, comprising package ...

COPPER PILLAR BUMP AND FLIP CHIP PACKAGE USING SAME

Electrically conductive pillars with a solder cap are formed on a substrate with an electroplating process. A flip-chip die having solder wettable pads is attached to the substrate with the conductive pillars contacting the solder wettable pads.

Verfahren zum Bearbeiten eines Halbleiterwerkstücks und ein Halbleiterwerkstück

Ein Verfahren (200) zum Bearbeiten eines Halbleiterbauelements gemäß verschiedenen Ausführungsformen kann aufweisen: Abscheiden einer ersten Metallisierungsschicht über einem Halbleiterwerkstück (202); Strukturieren der ersten Metallisierungsschicht (204); und Abscheiden einer zweiten Metallisierungsschicht über der strukturierten ersten Metallisierungsschicht, wobei das Abscheiden der zweiten Metallisierungsschicht einen stromlosen Abscheidungsprozess aufweist, der ein Eintauchen der strukturierten ersten Metallisierungsschicht in einen Metallelektrolyt aufweist (206).

Barrierestrukturen zwischen externen elektrischen Anschlussteilen und entprechendes Verfahren

Struktur, die Folgendes aufweist:ein Die-Substrat (20);eine Passivierungsschicht (22a) auf dem Die-Substrat (20), wobei eine distale Oberfläche der Passivierungsschicht (22a) sich in einem Abstand von dem Die-Substrat (20) befindet;eine erste Verbindungsstruktur (24) auf der Passivierungsschicht (22a), wobei die erste Verbindungsstruktur (24) einen ersten Via-Abschnitt (54) durch die Passivierungsschicht (22a) zu einem ersten leitenden Merkmal des Die-Substrats (20) aufweist, wobei die erste Verbindungsstruktur (24) weiter ein erstes Pad (58) und ein erstes Übergangselement (56) auf der distalen Oberfläche der Passivierungsschicht (22a) zwischen dem ersten Via-Abschnitt (54) und dem ersten Pad (58) aufweist;eine zweite Verbindungsstruktur (24) auf der Passivierungsschicht (22a), wobei die zweite Verbindungsstruktur (24) einen zweiten Via-Abschnitt (54) durch die Passivierungsschicht (22a) zu einem zweiten leitenden Merkmal des Die-Substrats (20) aufweist, wobei die zweite Verbindungsstruktur ...

Wire bond pad system and method

To reduce the RF losses associated with high RF loss plating, such as, for example, Ni/Pd/Au plating, the solder mask is reconfigured to prevent the edges and sidewalls of the wire-bond areas from being plated in some embodiments. Leaving the edges and sidewalls of the wire-bond areas free from high RF loss plating, such as Ni/Pd/Au plating, provides a path for the RF current to flow around the high resistivity material, which reduces the RF signal loss associated with the high resistivity plating material.

Radio frequency integrated circuit module

To reduce radio frequency losses during operation of a radio frequency integrated circuit module, the radio frequency integrated circuit module is fabricated such that at least one of an edge of the wirebond pad on the copper trace and a sidewall of the copper trace is free from high-resistivity plating material. The unplated portion provides a path for the radio frequency current to flow around the high-resistivity material.

Semiconductor device having under-bump metallization (ubm) structure and method of forming the same

Copper pillar bump and flip chip package using same

Electrically conductive pillars with a solder cap are formed on a substrate with an electroplating process. A flip-chip die having solder wettable pads is attached to the substrate with the conductive pillars contacting the solder wettable pads.

Method for manufacture of wire bondable and solderable surfaces on noble metal electrodes

METHOD OF FABRICATING BUMP STRUCTURE

A method for fabricating bump structure forms an under-bump metallurgy (UBM) layer in an opening of an encapsulating layer, and then forms a bump layer on the UBM layer within the opening of the encapsulating layer. After removing excess material of the bump layer from the upper surface of the encapsulating layer, the encapsulating layer is removed till a top portion of the bump layer protrudes from the upper surface of the encapsulating layer.

ELECTROLESS NICKEL AND GOLD PLATING IN SEMICONDUCTOR DEVICE

A described example semiconductor device includes a passivation layer (230) formed over a semiconductor substrate (210) and a portion of a metal contact pad (220). Nickel is deposited over the passivation layer and metal contact pad and gold is deposited over the nickel using an ENIG electroless plating process. The nickel includes a first non-porous nickel region (layer 250A) free of porous nickel at an interface (180) of the nickel with the passivation layer and at a junction (290) of the nickel with the passivation layer and metal contact pad. The nickel also includes a porous nickel region (layer 270) over the first nickel layer (250A). A gold region (layer 260) is over the porous nickel layer (270). A second non-porous nickel region (layer 250B) may be between the porous nickel region and the gold region. A gold-rich nickel region (275) may be between the porous nickel region and the gold region. Relative thicknesses of the deposited nickel and the deposited gold are chosen to prevent corrosion of the nickel layer from reaching the device layer during the electroless gold plating process.

METHOD OF FORMING POST-PASSIVATION INTERCONNECT STRUCTURE

A method includes coating a passivation layer overlying a semiconductor substrate and forming an interconnect layer overlying the passivation layer. The interconnect layer includes a line region and a landing pad region. The method further includes forming a metallic layer including tin on a surface of the interconnect layer using an immersion process, forming a protective layer on the metallic layer, and exposing a portion of the metallic layer on the landing pad region of the interconnect layer through the protective layer. 1. A method , comprising:coating a passivation layer overlying a semiconductor substrate;forming an interconnect layer overlying the passivation layer, wherein the interconnect layer comprises a line region and a landing pad region;forming a metallic layer comprising tin on a surface of the interconnect layer using an immersion process;forming a protective layer on the metallic layer; andexposing a portion of the metallic layer on the landing pad region of the interconnect layer through the protective layer.2. The method of claim 1 , further comprising forming a solder bump on the exposed portion of the metallic layer.3. The method of claim 2 , further comprising forming an intermetallic compound layer comprising tin and copper between the interconnect layer and the solder bump.4. The method of claim 2 , further comprising performing a thermal reflowing process on the solder bump.5. The method of claim 1 , further comprising forming an intermetallic compound layer comprising tin and copper between the interconnect layer and the protective layer.6. The method of claim 1 , wherein forming the protective layer on the metallic layer comprises forming the protective layer including a polymer.7. The method of claim 1 , wherein forming the interconnect layer overlying the passivation layer comprises forming the interconnect layer comprising copper or a copper alloy.8. The method of claim 2 , further comprising attaching the solder bump to a conductive ...

Under-bump metallization (ubm) structure and method of forming the same

An under-bump metallization (UBM) structure in a semiconductor device includes a copper layer, a nickel layer, and a Cu-Ni-Sn intermetallic compound (IMC) layer between the copper layer and the nickel layer.

SEMICONDUCTOR DEVICE HAVING UNDER-BUMP METALLIZATION (UBM) STRUCTURE AND METHOD OF FORMING THE SAME

A semiconductor device comprises a semiconductor substrate, an under-bump metallization (UBM) structure overlying the semiconductor substrate, and a solder bump overlying and electrically connected to the UBM structure. The UBM structure comprises a first metallization layer comprising a first metal, a second metallization layer comprising a second metal different from the first metal, and a first intermetallic compound (IMC) layer between the first metallization layer and the second metallization layer, the first IMC layer comprising the first metal and the second metal.

Under-bump metallization (UBM) structure and method of forming the same

An under-bump metallization (UBM) structure in a semiconductor device includes a copper layer, a nickel layer, and a Cu-Ni-Sn intermetallic compound (IMC) layer between the copper layer and the nickel layer.

GALLIUM ARSENIDE DEVICES WITH COPPER BACKSIDE FOR DIRECT DIE SOLDER ATTACH

Systems, apparatuses, and methods related to the design, fabrication, and manufacture of gallium arsenide (GaAs) integrated circuits are disclosed. Copper can be used as the contact material for a GaAs integrated circuit. Metallization of the wafer and through-wafer vias can be achieved through copper plating processes disclosed herein. Direct die solder (DDS) attach can be achieved by use of electroless nickel plating of the copper contact layer followed by a palladium flash. GaAs integrated circuits can be singulated, packaged, and incorporated into various electronic devices.

STRUCTURES AND METHODS FOR CAPACITIVE ISOLATION DEVICES

Described examples include a packaged device including a first object and a second object spaced from each other by a gap, each object having a first surface and an opposite second surface, the first surfaces of the first object and the second object including first terminals. A structure includes at least two conductors embedded in a dielectric casing consolidating a configuration and organization of the at least two conductors, the at least two conductors having end portions un-embedded by the dielectric casing. An end portion of at least one of the at least two conductors is electrically connected to a first terminal of the first object, and an opposite end portion of the at least one of the at least two conductors is electrically connected to a respective first terminal of the second object, the at least two conductors electrically connecting the first object and the second object.

Structures and methods for capacitive isolation devices

Barrier Structures Between External Electrical Connectors

A structure includes a die substrate; a passivation layer on the die substrate; first and second interconnect structures on the passivation layer; and a barrier on the passivation layer, at least one of the first or second interconnect structures, or a combination thereof. The first and second interconnect structures comprise first and second via portions through the passivation layer to first and second conductive features of the die substrate, respectively. The first and second interconnect structures further comprise first and second pads, respectively, and first and second transition elements on a surface of the passivation layer between the first and second via portion and the first and second pad, respectively. The barrier is disposed between the first pad and the second pad. The barrier does not fully encircle at least one of the first pad or the second pad.

Semiconductor device and method for fabricating the same

SEMICONDUCTOR DEVICE HAVING UNDER-BUMP METALLIZATION (UBM) STRUCTURE AND METHOD OF FORMING THE SAME

A semiconductor device comprises a semiconductor substrate, an under-bump metallization (UBM) structure overlying the semiconductor substrate, and a solder bump overlying and electrically connected to the UBM structure. The UBM structure comprises a copper-containing metallization layer, a nickel-containing metallization layer, and a first intermetallic compound (IMC) layer between the copper-containing metallization layer and the nickel-containing metallization layer. The first IMC layer is in direct contact with the copper-containing metallization layer and the nickel-containing metallization layer.

Zwischenverbindungsstruktur umfassend Metall-Rückseiten-Umverteilungsleitungen mit sehr kleinem Teilungsabstand kombiniert mit Durchkontaktierungen

Eine 3D-Zwischenverbindungsstruktur und ein Herstellungsverfahren sind beschrieben, in denen Metall-Umverteilungsschichten (RDLs) mit Silizium-Durchkontaktierungen (TSVs) integriert sind und unter Verwendung eines Verfahrensablaufs der Durchkontaktierungs-Resist-Art. Eine Siliziumnitrid- oder Siliziumcarbid-Passivierungsschicht kann zwischen der Rückseite des ausgedünnten Vorrichtungswafers und den RDLs bereitgestellt sein, um während des Verfahrensablaufs eine hermetische Barriere- und Polierstoppschicht bereitzustellen.

Semiconductor structure and mothod of forming the same

Under-bump metallization (ubm) structure and method of forming the same

Barrier structures between external electrical connectors

A structure includes a die substrate; a passivation layer on the die substrate; first and second interconnect structures on the passivation layer; and a barrier on the passivation layer, at least one of the first or second interconnect structures, or a combination thereof. The first and second interconnect structures comprise first and second via portions through the passivation layer to first and second conductive features of the die substrate, respectively. The first and second interconnect structures further comprise first and second pads, respectively, and first and second transition elements on a surface of the passivation layer between the first and second via portion and the first and second pad, respectively. The barrier is disposed between the first pad and the second pad. The barrier does not fully encircle at least one of the first pad or the second pad.

The method of forming the bump structure

一种形成凸块结构的方法，包括：通过化学镀工艺在顶部金属层上形成金属化层；在金属化层上方形成聚合物层；在聚合物层上形成开口以暴露金属化层；以及在暴露的金属化层上方形成焊料凸块，以与顶部金属层电接触。

Power Device and Power Device Module

비아들과 조합되는 미세 피치 후면측 금속 재분포 라인들을 포함하는 상호접속 구조

... 금속 재분포 층들(RDL들)이 TSV들과 통합되고 "레지스트를 통한 도금" 유형의 공정 흐름을 이용하는 3D 상호접속 구조 및 제조 방법이 기술된다. 이 공정 흐름 동안 기밀 장벽 및 연마 정지 층을 제공하기 위해서 실리콘 질화물 또는 실리콘 탄화물 패시베이션 층이 박화 장치 웨이퍼 후면측과 RDL들 사이에 제공될 수 있다.

Semiconductor device having under-bump metallization (UBM) structure and method of forming the same

A semiconductor device comprises a semiconductor substrate, an under-bump metallization (UBM) structure overlying the semiconductor substrate, and a solder bump overlying and electrically connected to the UBM structure. The UBM structure comprises a copper-containing metallization layer, a nickel-containing metallization layer, and a first intermetallic compound (IMC) layer between the copper-containing metallization layer and the nickel-containing metallization layer. The first IMC layer is in direct contact with the copper-containing metallization layer and the nickel-containing metallization layer.

METHOD OF FORMING BUMP STRUCTURE

A method of forming a bump structure includes forming a metallization layer on a top metal layer by electroless plating process, forming a polymer layer over the metallization layer; forming an opening on the polymer layer to expose the metallization layer, and forming a solder bump over the exposed metallization layer to make electrical contact with the top metal layer.

Method of making a semiconductor chip assembly with a carved bumped terminal

A method of making a semiconductor chip assembly includes providing a metal base, a routing line, a bumped terminal and a metal filler, then mechanically attaching a semiconductor chip to the metal base, the routing line, the bumped terminal and the metal filler, then forming an encapsulant, then etching the metal base to expose the bumped terminal, and then grinding the bumped terminal to expose the metal filler.

Repackaged integrated circuit assembly method

A method is provided. The method includes one or more of extracting a die from an original packaged integrated circuit, modifying the extracted die, reconditioning the modified extracted die, placing the reconditioned die into a cavity of a hermetic package base, bonding a plurality of bond wires between reconditioned die pads of the reconditioned die to leads of the hermetic package base or downbonds to create an assembled hermetic package base, and sealing a hermetic package lid to the assembled hermetic package base to create a new packaged integrated circuit. Modifying the extracted die includes removing the one or more ball bonds on the one or more die pads. Reconditioning the modified extracted die includes adding a sequence of metallic layers to bare die pads of the modified extracted die. The extracted die is a fully functional semiconductor die with one or more ball bonds on one or more die pads of the extracted die.

Under-bump metallization (ubm) structure and method of forming the same

Method of forming post-passivation interconnect structure

A method includes coating a passivation layer overlying a semiconductor substrate and forming an interconnect layer overlying the passivation layer. The interconnect layer includes a line region and a landing pad region. The method further includes forming a metallic layer including tin on a surface of the interconnect layer using an immersion process, forming a protective layer on the metallic layer, and exposing a portion of the metallic layer on the landing pad region of the interconnect layer through the protective layer.

Gallium arsenide devices with copper backside for direct die solder attach

Systems, apparatuses, and methods related to the design, fabrication, and manufacture of gallium arsenide (GaAs) integrated circuits are disclosed. Copper can be used as the contact material for a GaAs integrated circuit. Metallization of the wafer and through-wafer vias can be achieved through copper plating processes disclosed herein. Direct die solder (DDS) attach can be achieved by use of electroless nickel plating of the copper contact layer followed by a palladium flash. GaAs integrated circuits can be singulated, packaged, and incorporated into various electronic devices.

Method of forming bump structure

A method of forming a bump structure includes forming a metallization layer on a top metal layer by electroless plating process, forming a polymer layer over the metallization layer; forming an opening on the polymer layer to expose the metallization layer, and forming a solder bump over the exposed metallization layer to make electrical contact with the top metal layer.

Method for manufacture of wire bondable and solderable surfaces on noble metal electrodes

The present invention relates to a method for manufacture of wire bondable and solderable surfaces on noble metal electrodes. The noble metal electrodes are activated by depositing a seed layer of palladium or a palladium alloy layer by electroless plating at 60 to 90 DEG C. Next, an intermediate layer is deposited onto the seed layer followed by deposition of the wire bondable and/or solderable surface finish layer(s) onto the intermediate layer. This method is particularly suitable in the production of optoelectronic devices such as light emitting diodes (LEDs).

Wire bond pad system and method

To reduce the RF losses associated with high RF loss plating, such as, for example, Ni/Pd/Au plating, the solder mask is reconfigured to prevent the edges and sidewalls of the wire-bond areas from being plated in some embodiments. Leaving the edges and sidewalls of the wire-bond areas free from high RF loss plating, such as Ni/Pd/Au plating, provides a path for the RF current to flow around the high resistivity material, which reduces the RF signal loss associated with the high resistivity plating material.

Method of fabricating bump structure

A method for fabricating bump structure forms an under-bump metallurgy (UBM) layer in an opening of an encapsulating layer, and then forms a bump layer on the UBM layer within the opening of the encapsulating layer. After removing excess material of the bump layer from the upper surface of the encapsulating layer, the encapsulating layer is removed till a top portion of the bump layer protrudes from the upper surface of the encapsulating layer.

Methods to fabricate a radio frequency integrated circuit

To reduce radio frequency (RF) losses during operation of a radio frequency integrated circuit (RFIC) module, the RFIC module is fabricated such that at least one of an edge of the wirebond pad on the copper trace and a sidewall of the copper trace is free from high-resistivity plating material. The unplated portion provides a path for the RF current to flow around the high-resistivity material, which reduces the RF signal loss associated with the high resistivity plating material.

WIRE BOND PAD SYSTEM AND METHOD

To reduce the RF losses associated with high RF loss plating, such as, for example, Ni/Pd/Au plating, the solder mask is reconfigured to prevent the edges and sidewalls of the wire-bond areas from being plated in some embodiments. Leaving the edges and sidewalls of the wire-bond areas free from high RF loss plating, such as Ni/Pd/Au plating, provides a path for the RF current to flow around the high resistivity material, which reduces the RF signal loss associated with the high resistivity plating material.

Direct die solder of gallium arsenide integrated circuit dies and methods of manufacturing gallium arsenide wafers

Electronic devices, and methods of manufacturing the electronic devices, utilizing direct die soldering of GaAs integrated circuit dies. In some embodiments, the GaAs integrated circuit die can have a footprint approximately the same size as a die attach pad. Further, the GaAs integrated circuit die can self-align with the die attach pad after reflow of any solder layer used to attach the die.

Electroless nickel and gold plating in semiconductor device

一种所描述的实例半导体装置包含在半导体衬底(210)及金属接触垫(220)的一部分上形成的钝化层(230)。使用ENIG无电镀敷工艺，将镍沉积于所述钝化层及金属接触垫上，且将金沉积于所述镍上。所述镍包含在所述镍与所述钝化层的界面(180)处及在所述镍与所述钝化层及金属接触垫的结(290)处的无多孔镍的第一无孔镍区域(层250A)。所述镍还包含在第一镍层(250A)上的多孔镍区域(层270)。金区域(层260)在多孔镍层(270)上。第二无孔镍区域(层250B)可在所述多孔镍区域与所述金区域之间。富含金的镍区域(275)可在所述多孔镍区域与所述金区域之间。对所沉积镍与所沉积金的相对厚度进行选择以防止在无电金镀敷工艺期间镍层的腐蚀到达装置层。

Semiconductor device and manufacturing method thereof

A method for fabricating bump structure forms an under-bump metallurgy (UBM) layer in an opening of an encapsulating layer, and then forms a bump layer on the UBM layer within the opening of the encapsulating layer. After removing excess material of the bump layer from the upper surface of the encapsulating layer, the encapsulating layer is removed till a top portion of the bump layer protrudes from the upper surface of the encapsulating layer. The UBM undercut issue is eliminated.

Semiconductor device and method of making a semiconductor device

In semiconductor device jin Dufu electroless nickel and

Barrier Structures Between External Electrical Connectors

A structure includes a die substrate; a passivation layer on the die substrate; first and second interconnect structures on the passivation layer; and a barrier on the passivation layer, at least one of the first or second interconnect structures, or a combination thereof. The first and second interconnect structures comprise first and second via portions through the passivation layer to first and second conductive features of the die substrate, respectively. The first and second interconnect structures further comprise first and second pads, respectively, and first and second transition elements on a surface of the passivation layer between the first and second via portion and the first and second pad, respectively. The barrier is disposed between the first pad and the second pad. The barrier does not fully encircle at least one of the first pad or the second pad.

Semiconductor structure and mothod of forming the same

A structure includes a die substrate; a passivation layer on the die substrate; first and second interconnect structures on the passivation layer; and a barrier on the passivation layer, at least one of the first or second interconnect structures, or a combination thereof. The first and second interconnect structures comprise first and second via portions through the passivation layer to first and second conductive features of the die substrate, respectively. The first and second interconnect structures further comprise first and second pads, respectively, and first and second transition elements on a surface of the passivation layer between the first and second via portion and the first and second pad, respectively. The barrier is disposed between the first pad and the second pad. The barrier does not fully encircle at least one of the first pad or the second pad.

Nano copper paste and film for sintered die attach and similar applications

A sintering powder comprising copper particles, wherein: the particles are at least partially coated with a capping agent, and the particles exhibit a D10 of greater than or equal to 100 nm and a D90 of less than or equal to 500 nm.

Repackaged integrated circuit assembly method

A method is provided. The method includes one or more of extracting a die from an original packaged integrated circuit, modifying the extracted die, reconditioning the modified extracted die, placing the reconditioned die into a cavity of a hermetic package base, bonding a plurality of bond wires between reconditioned die pads of the reconditioned die to leads of the hermetic package base or downbonds to create an assembled hermetic package base, and sealing a hermetic package lid to the assembled hermetic package base to create a new packaged integrated circuit. Modifying the extracted die includes removing the one or more ball bonds on the one or more die pads. Reconditioning the modified extracted die includes adding a sequence of metallic layers to bare die pads of the modified extracted die. The extracted die is a fully functional semiconductor die with one or more ball bonds on one or more die pads of the extracted die. 1. A method , comprising:extracting a die from an original packaged integrated circuit, wherein the extracted die is a fully functional semiconductor die with one or more ball bonds on one or more die pads of the extracted die;modifying the extracted die, comprising removing the one or more ball bonds on the one or more die pads; 'adding a sequence of metallic layers to bare die pads of the modified extracted die;', 'reconditioning the modified extracted die, comprisingplacing the reconditioned die into a cavity of a hermetic package base;bonding a plurality of bond wires between reconditioned die pads of the reconditioned die to leads of the hermetic package base or downbonds to create an assembled hermetic package base; andsealing a hermetic package lid to the assembled hermetic package base to create a new packaged integrated circuit.2. The method as recited in claim 1 , wherein bare die pads of the modified extracted die comprises all metallic and chemical residue claim 1 , all ball bonds claim 1 , and all bond wires removed from all die ...

Wire bond pad system and method

Semiconductor device and method for fabricating the same

A semiconductor device includes a conductive layer formed on the surface of a post-passivation interconnect (PPI) structure by an immersion tin process. A polymer layer is formed on the conductive layer and patterned with an opening to expose a portion of the conductive layer. A solder bump is then formed in the opening of the polymer layer to electrically connect to the PPI structure.

Method for self-aligned solder reflow bonding and devices obtained thereof

A method for producing a stack of semiconductor devices and the stacked device obtained thereof are disclosed. In one aspect, the method includes providing a first semiconductor device comprising a dielectric layer with a hole, the hole lined with a metal layer and partially filled with solder material. The method also includes providing a second semiconductor device with a compliant layer having a metal protrusion through the compliant layer, the protrusion capped with a capping layer. The method further includes mounting the devices by landing the metal protrusion in the hole, where the compliant layer is spaced from the dielectric layer. The method includes thereafter reflowing the solder material, thereby bonding the devices such that the compliant layer is contacting the dielectric layer.

In the noble metal on the electrodes can be wire bonding and welding method on the surface of

Interconnect structure comprising fine pitch backside metal redistribution lines combined with vias

Wire bond pad system and method

To reduce the RF losses associated with high RF loss plating, such as, for example, Ni/Pd/Au plating, the solder mask is reconfigured to prevent the edges and sidewalls of the wire-bond areas from being plated in some embodiments. Leaving the edges and sidewalls of the wire-bond areas free from high RF loss plating, such as Ni/Pd/Au plating, provides a path for the RF current to flow around the high resistivity material, which reduces the RF signal loss associated with the high resistivity plating material.

Barrier structures between external electrical connectors

A structure includes a die substrate; a passivation layer on the die substrate; first and second interconnect structures on the passivation layer; and a barrier on the passivation layer, at least one of the first or second interconnect structures, or a combination thereof. The first and second interconnect structures comprise first and second via portions through the passivation layer to first and second conductive features of the die substrate, respectively. The first and second interconnect structures further comprise first and second pads, respectively, and first and second transition elements on a surface of the passivation layer between the first and second via portion and the first and second pad, respectively. The barrier is disposed between the first pad and the second pad. The barrier does not fully encircle at least one of the first pad or the second pad.

Method for Processing Semiconductor Workpiece and Semiconductor Workpiece

Barrier structures between external electrical connectors

A structure includes a die substrate; a passivation layer on the die substrate; first and second interconnect structures on the passivation layer; and a barrier on the passivation layer, at least one of the first or second interconnect structures, or a combination thereof. The first and second interconnect structures comprise first and second via portions through the passivation layer to first and second conductive features of the die substrate, respectively. The first and second interconnect structures further comprise first and second pads, respectively, and first and second transition elements on a surface of the passivation layer between the first and second via portion and the first and second pad, respectively. The barrier is disposed between the first pad and the second pad. The barrier does not fully encircle at least one of the first pad or the second pad.

Post-passivation interconnect structure and method of forming the same

A semiconductor device includes a conductive layer formed on the surface of a post-passivation interconnect (PPI) structure by an immersion tin process. A polymer layer is formed on the conductive layer and patterned with an opening to expose a portion of the conductive layer. A solder bump is then formed in the opening of the polymer layer to electrically connect to the PPI structure.

Semiconductor device and method for fabricating the same

SEMICONDUCTOR DEVICE AND METHOD OF MAKING A SEMICONDUCTOR DEVICE

A semiconductor device and a method of making the same. The device includes a semiconductor substrate having a major surface, one or more contacts located on the major surface and an encapsulant covering at least the major surface. A peripheral edge of each contact defines a contact area on the major surface. The device also includes one or more bond pads located outside the encapsulant. Each bond pad is electrically connected to a respective contact located on the major surface of the substrate by a respective metal filled via that passes through the encapsulant. A sidewall of each respective metal filled via, at the point at which it meets the respective contact, falls inside the contact area defined by the respective contact when viewed from above the major surface of the substrate, whereby none of the metal filling each respective via extends outside the contact area of each respective contact.

Wire bond pad system and method

SYSTEMS AND METHODS TO FABRICATE A RADIO FREQUENCY INTEGRATED CIRCUIT

To reduce radio frequency (RF) losses during operation of a radio frequency integrated circuit (RFIC) module, the RFIC module is fabricated such that at least one of an edge of the wirebond pad on the copper trace and a sidewall of the copper trace is free from high-resistivity plating material. The unplated portion provides a path for the RF current to flow around the high-resistivity material, which reduces the RF signal loss associated with the high resistivity plating material.

Acoustic wave resonator and method of manufacturing the acoustic wave resonator

Remapped packaged extracted die

A remapped extracted die is provided. The remapped extracted die includes an extracted die removed from a previous integrated circuit package. The extracted die includes a plurality of original bond pads having locations that do not correspond to desired pin assignments of a new package base and an interposer, bonded to the extracted die. The interposer includes first bond pads configured to receive new bond wires from the plurality of original bond pads, and second bond pads corresponding to desired pin assignments of the new package base, each individually electrically coupled to one of the first bond pads and configured to receive new bond wires from package leads or downbonds of the new package base.

Method for processing a semiconductor workpiece and semiconductor workpiece

A method for processing a semiconductor device in accordance with various embodiments may include: depositing a first metallization layer over a semiconductor workpiece; patterning the first metallization layer; and depositing a second metallization layer over the patterned first metallization layer, wherein depositing the second metallization layer includes an electroless deposition process including immersing the patterned first metallization layer in a metal electrolyte.

INTERCONNECT ASSEMBLIES AND METHODS OF MAKING AND USING SAME

The various embodiments of the present invention provide fine pitch, chip-to-substrate hybrid interconnect assemblies, as well as methods of making and using the assemblies. The hybrid assemblies generally include a semiconductor having a die pad disposed thereon, a substrate having a substrate pad disposed thereon, and a polymer layer disposed between the surface of the die pad and the surface of the substrate pad. In addition, at least a portion of the surface of the die pad is metallically bonded to at least a portion of the surface of the substrate pad and at least a portion of the surface of the die pad is chemically bonded to at least a portion of the surface of the substrate pad.

Method of fabricating bump structure and bump structure

A method of forming a semiconductor device includes forming an under-bump metallurgy (UBM) layer overlying a portion of a metal pad region within an opening of an encapsulating layer over a semiconductor substrate, and forming a bump layer overlying the UBM layer to fill the opening of the encapsulating layer. A removal process is initiated on an upper surface of the encapsulating layer and a coplanar top surface of the bump layer to remove the upper surface of the encapsulating layer until a top portion of the bump layer protrudes from the encapsulating layer.

SYSTEMS AND METHODS TO FABRICATE A RADIO FREQUENCY INTEGRATED CIRCUIT

To reduce radio frequency losses during operation of a radio frequency integrated circuit module, the radio frequency integrated circuit module is fabricated such that at least one of an edge of the wirebond pad on the copper trace and a sidewall of the copper trace is free from high-resistivity plating material. The unplated portion provides a path for the radio frequency current to flow around the high-resistivity material, which reduces the radio frequency signal loss associated with the high resistivity plating material.

Semiconductor device and method of making a semiconductor device

A semiconductor device and a method of making the same. The device includes a semiconductor substrate having a major surface, one or more contacts located on the major surface and an encapsulant covering at least the major surface. A peripheral edge of each contact defines a contact area on the major surface. The device also includes one or more bond pads located outside the encapsulant. Each bond pad is electrically connected to a respective contact located on the major surface of the substrate by a respective metal filled via that passes through the encapsulant. A sidewall of each respective metal filled via, at the point at which it meets the respective contact, falls inside the contact area defined by the respective contact when viewed from above the major surface of the substrate, whereby none of the metal filling each respective via extends outside the contact area of each respective contact.

Semiconductor device having under-bump metallization (UBM) structure and method of forming the same

A semiconductor device comprises a semiconductor substrate, an under-bump metallization (UBM) structure overlying the semiconductor substrate, and a solder bump overlying and electrically connected to the UBM structure. The UBM structure comprises a first metallization layer comprising a first metal, a second metallization layer comprising a second metal different from the first metal, and a first intermetallic compound (IMC) layer between the first metallization layer and the second metallization layer, the first IMC layer comprising the first metal and the second metal.

Bump metallization (UBM) structure with the bottom of the semiconductor device and method for forming the same

Post-passivation interconnect structure and method of forming the same

一种半导体器件包括：导电层，该导电层通过浸镀锡工艺形成于钝化后互连(PPI)结构的表面上；聚合物层，该聚合物层形成于导电层上并且经图案化具有暴露出一部分导电层的开口；以及焊料凸块，该焊料凸块形成于聚合物层的开口中以电连接至PPI结构。本发明提供了钝化后互连结构及其形成方法。

SEMICONDUCTOR DEVICE HAVING UNDER-BUMP METALLIZATION (UBM) STRUCTURE AND METHOD OF FORMING THE SAME

A semiconductor device has a UBM (under-bump metallization) structure underlying and electrically connected to a solder bump. The UBM structure has a first metallization layer with a first cross-sectional dimension d1, a second metallization layer with a second cross-sectional dimension d2 formed on the first metallization layer, and a third metallization layer with a third cross-sectional dimension d3 formed on the second metallization layer, in which d1 is greater than d3, and d3 is greater than d2.

NANO COPPER PASTE AND FILM FOR SINTERED DIE ATTACH AND SIMILAR APPLICATIONS

A sintering powder comprising copper particles, wherein: the particles are at least partially coated with a capping agent, and the particles exhibit a D10 of greater than or equal to 100 nm and a D90 of less than or equal to 2000 nm.

半導体デバイスにおける無電解ニッケルおよび金めっき

Post-passivation interconnect structure and method of forming the same

A semiconductor device includes a conductive layer formed on the surface of a post-passivation interconnect (PPI) structure by an immersion tin process. A polymer layer is formed on the conductive layer and patterned with an opening to expose a portion of the conductive layer. A solder bump is then formed in the opening of the polymer layer to electrically connect to the PPI structure.

SYSTEMS AND METHODS TO FABRICATE A RADIO FREQUENCY INTEGRATED CIRCUIT

To reduce radio frequency (RF) losses during operation of a radio frequency integrated circuit (RFIC) module, the RFIC module is fabricated such that at least one of an edge of the wirebond pad on the copper trace and a sidewall of the copper trace is free from high-resistivity plating material. The unplated portion provides a path for the RF current to flow around the high-resistivity material, which reduces the RF signal loss associated with the high resistivity plating material. 1. A method to fabricate a radio frequency integrated circuit (RFIC) module , the method comprising:plating a nickel layer over a portion of a top surface of a copper trace, the copper trace including at least a sidewall and formed on a substrate;plating a palladium layer over the nickel layer; andplating a gold layer over the palladium layer, the nickel, palladium, and gold layers forming a wire bonding pad that covers a plated portion of the copper trace leaving an unplated portion of the copper trace that is substantially parallel to the wire bonding pad along the sidewall, the unplated portion forming an unplated path along the copper trace and configured to conduct radio frequency (RF) current during operation of the RFIC module and reduce RF power loss.2. The method of wherein the nickel layer is between about 1 micron and about 10 microns.3. The method of wherein the palladium layer is between about 0.01 microns and about 1 micron.4. The method of wherein the gold layer is between about 0.01 microns and about 1 micron.5. The method of wherein the unplated portion of the copper trace is free from the nickel claim 1 , palladium claim 1 , and gold layers.6. The method of further comprising expanding a width of the copper trace to accommodate the wire bonding pad such that at least the sidewall of the copper trace is free from the nickel claim 1 , palladium claim 1 , and gold layers to maintain the unplated path on the copper trace to conduct the RF current.7. The method of further ...

Integrated circuit package using polymer-solder ball structures and forming methods

A conductive polymer-solder ball structure is provided. The conductive polymer-solder ball structure includes a wafer having at least one metal pad providing an electrical conductive path to a substrate layer, a conductive polymer pad located directly on the wafer over the at least one metal pad, an electrolessly plated layer located on a surface of the conductive polymer pad, and a solder ball located on a surface of the electrolessly plated layer.

Acoustic wave resonator and method of manufacturing acoustic wave resonator

本公开提供一种声波谐振器及制造声波谐振器的方法。所述声波谐振器包括：基板；谐振部，形成在所述基板的第一表面上；金属焊盘，通过形成在所述基板中的通路孔连接到所述谐振部；及保护层，设置在所述基板的第二表面上并且包括多个层，其中，所述多个层包括内保护层，所述内保护层直接接触所述基板的所述第二表面，并且由具有比所述多个层中的其他层的粘附力强的粘附力的绝缘材料形成。

Barrier Structures Between External Electrical Connectors

A structure includes a die substrate; a passivation layer on the die substrate; first and second interconnect structures on the passivation layer; and a barrier on the passivation layer, at least one of the first or second interconnect structures, or a combination thereof. The first and second interconnect structures comprise first and second via portions through the passivation layer to first and second conductive features of the die substrate, respectively. The first and second interconnect structures further comprise first and second pads, respectively, and first and second transition elements on a surface of the passivation layer between the first and second via portion and the first and second pad, respectively. The barrier is disposed between the first pad and the second pad. The barrier does not fully encircle at least one of the first pad or the second pad.

Method for manufacture of wire bondable and solderable surfaces on noble metal electrodes

The present invention relates to a method for manufacture of wire bondable and solderable surfaces on noble metal electrodes. The noble metal electrodes are activated by depositing a seed layer of palladium or a palladium alloy layer by electroless plating at 60 to 90 °C. Next, an intermediate layer is deposited onto the seed layer followed by deposition of the wire bondable and/or solderable surface finish layer(s) onto the intermediate layer. This method is particularly suitable in the production of optoelectronic devices such as light emitting diodes (LEDs).

Semiconductor device and method of making a semiconductor device

A semiconductor device and a method of making the same. The device includes a semiconductor substrate having a major surface, one or more contacts located on the major surface and an encapsulant covering at least the major surface. A peripheral edge of each contact defines a contact area on the major surface. The device also includes one or more bond pads located outside the encapsulant. Each bond pad is electrically connected to a respective contact located on the major surface of the substrate by a respective metal filled via that passes through the encapsulant. A sidewall of each respective metal filled via, at the point at which it meets the respective contact, falls inside the contact area defined by the respective contact when viewed from above the major surface of the substrate, whereby none of the metal filling each respective via extends outside the contact area of each respective contact.

Method for manufacture of wire bondable and solderable surfaces on noble metal electrodes

本发明涉及一种在贵金属电极上制造可线接合和可焊接表面的方法。所述贵金属电极是通过在60℃到90℃下无电电镀来沉积钯或钯合金层的晶种层而被活化。接着，将中间层沉积到所述晶种层上，然后将可线接合和/或可焊接表面处理层沉积到所述中间层上。这一方法尤其适用于生产光电子装置，如发光二极管LED。

Nanocopper pastes and films for sintered die attach and similar applications

구리 입자를 포함하는 소결 분말로서, 입자는 캡핑제로 적어도 부분적으로 코팅되며, 입자는 100 nm 이상의 D10 및 2000 nm 이하의 D90을 나타낸다. A sintered powder comprising copper particles, wherein the particles are at least partially coated with a capping agent, and the particles exhibit a D10 of 100 nm or more and a D90 of 2000 nm or less.

Nano copper paste and film for sintered die attach and similar applications

A sintering powder comprising copper particles, wherein: the particles are at least partially coated with a capping agent, and the particles exhibit a D10 of greater than or equal to 100 nm and a D90 of less than or equal to 2000 nm.

焼結ダイアタッチ及び類似した用途のためのナノ銅ペースト及びフィルム

Zwischenverbindungsstruktur umfassend Metall-Rückseiten-Umverteilungsleitungen mit sehr kleinem Teilungsabstand kombiniert mit Durchkontaktierungen

Zwischenverbindungsvorrichtung, umfassend:ein Halbleitersubstrat (100), das eine vordere (102) und eine hintere Oberfläche (104) aufweist;eine Durchkontaktierung (142), die sich von der vorderen Oberfläche (102) zu der hinteren Oberfläche (104) erstreckt;eine Umverteilungsschicht, RDL (144), die über der hinteren Oberfläche (104) und der Durchkontaktierung (142) ausgebildet ist;eine erste Passivierungsschicht (146), die eine seitliche Oberfläche der RDL (144) direkt berührt, wobei die erste Passivierungsschicht (146) vertikal zu der Durchkontaktierung (142) ausgerichtet ist, undeine Barriereschicht (171) zwischen der RDL (144) und der Durchkontaktierung (142); undeine Saatschicht (170) zwischen der Barriereschicht (171) und der RDL (144), wobei die Saatschicht (170) und die RDL (144) ein leitendes Material umfassen;worin die Barriereschicht (171) und die Saatschicht (170) vertikal zu der Durchkontaktierung (142) ausgerichtet sind.

Nano copper paste and film for sintered die attach and similar applications

A sintering powder comprising copper particles, wherein: the particles are at least partially coated with a capping agent, and the particles exhibit a D10 of greater than or equal to 100 nm and a D90 of less than or equal to 2000 nm.

半導体デバイスにおける無電解ニッケルおよび金めっき

説明した例の半導体デバイスは、半導体基板及び金属コンタクトパッドの上に形成される不活性化層を含む。ＥＮＩＧ無電解めっきプロセスを用いて不活性化層及び金属コンタクトパッドの上にニッケルが、ニッケルの上に金が堆積される。ニッケルは、ニッケルの不活性化層とのインタフェースに及びニッケルの不活性化層及び金属コンタクトパッドとの接合に多孔質ニッケルのない第１非多孔質ニッケル領域（２５０Ａ）を含み、第１ニッケル層の上の多孔質ニッケル領域（２７０）も含む。多孔質ニッケル層の上に金領域（２６０）がある。第２非多孔質ニッケル領域（２５０Ｂ）が多孔質ニッケル領域と金領域との間にあってもよい。金リッチ・ニッケル領域（２７５）が、多孔質ニッケル領域と金領域との間にあってもよい。堆積されるニッケル及び堆積される金の相対的厚さは、無電解金めっきプロセス中にニッケル層の腐食がデバイス層に達しないように選択される。

用于烧结管芯附接和类似应用的纳米铜膏和膜

本发明公开了一种包含铜颗粒的烧结粉末，其中：该颗粒至少部分地涂覆有包覆剂，并且该颗粒表现出大于或等于100nm的D10和小于或等于2000nm的D90。

用于电容性隔离器件的结构和方法

所描述的示例包括封装器件(100)，封装器件(100)包括彼此间隔开间隙(110)的第一物体(101)和第二物体(102)。每个物体具有第一表面(101a、102a)和相对的第二表面(101c、102c)。第一表面(101a、102a)包括第一端子(101b、102b)。结构(120)包括嵌入在电介质壳体(130)中的至少两个导体(121)，电介质壳体巩固至少两个导体(121)的构造和组织。至少两个导体(121)具有未被电介质壳体(130)嵌入的端部部分。至少两个导体(121)中的至少一个的端部部分电连接到第一物体(101)的第一端子(101b)，并且至少两个导体(121)中的至少一个的相对的端部部分电连接到第二物体(102)的相应的第一端子(102b)。至少两个导体(121)电连接第一物体(101)和第二物体(102)。