Conductor structure for three-dimensional semiconductor device

A three-dimensional semiconductor device using redundant bonding-conductor structures to make inter-level electrical connections between multiple semiconductor chips is disclosed. A first chip, or other semiconductor substrate, forms a first active area on its upper surface, and a second chip or other semiconductor substrate forms a second active area on its upper surface. According to the present invention, when the second chip has been mounted above the first chip, either face-up or face-down, the first active area is coupled to the second active area by at least one redundant bonding-conductor structure. In one embodiment, each redundant bonding-conductor structure includes at least one via portion that extends completely through the second chip to perform this function. In another, the redundant bonding-conductor structure extends downward to the top level interconnect. The present invention also includes a method for making such a device.

CONTACT STRUCTURES WITH POROUS NETWORKS FOR SOLDER CONNECTIONS, AND METHODS OF FABRICATING SAME

A contact pad includes a solder-wettable porous network (310) which wicks the molten solder (130) and thus restricts the lateral spread of the solder, thus preventing solder bridging between adjacent contact pads.

Method for permanent connection of two metal surfaces

METHOD FOR PERMANENTLY CONNECTING TWO METAL SURFACES

Adhesion between Post-Passivation Interconnect Structure and Polymer

An embodiment integrated circuit structure includes a substrate, a metal pad over the substrate, a post-passivation interconnect (PPI) structure over the substrate and electronically connected to the metal pad, a thin oxide film layer directly over a top surface of the PPI structure, and a polymer layer over the thin oxide film layer and PPI structure.

Contact structures with porous networks for solder connections, and methods of fabricating same

A contact pad includes a solder-wettable porous network ( 310 ) which wicks the molten solder ( 130 ) and thus restricts the lateral spread of the solder, thus preventing solder bridging between adjacent contact pads.

BONDED NANOFLUIDIC DEVICE CHIP STACKS

A method of producing a bonded chip stack is described. A first nanofluidic device chip having a first through-wafer via is formed. A second nanofluidic device chip having a second through-wafer via is formed. The first nanofluidic device chip and the second nanofluidic device chip are washed with a detergent solution. A first surface of the first nanofluidic device chip and a second surface of the second nanofluidic device chip are activated by treating the first surface and the second surface with an activation solution. The first nanofluidic device chip and the second nanofluidic device chip are arranged in a stack. The first through-wafer via is aligned with the second through-wafer via in a substantially straight line. The stack of first and second nanofluidic device chips is subjected to annealing conditions.

BONDING STRUCTURES OF SEMICONDUCTOR DEVICES

A semiconductor device is provided that includes a bond pad, an insulating layer, and a bonding structure. The bond pad is in a dielectric layer and the insulating layer is over the bond pad; the insulating layer having an opening over the bond pad formed therein. The bonding structure electrically couples the bond pad in the opening. The bonding structure has a height that at least extends to an upper surface of the insulating layer. 1. A semiconductor device comprising:a bond pad in a dielectric layer;a passivation layer over the dielectric layer and the bond pad;an insulating layer over the passivation layer; anda bonding structure through the passivation layer and the insulating layer, wherein the bonding structure has a height that at least extends to an upper surface of the insulating layer and is electrically coupled with the bond pad.2. The semiconductor device of claim 1 , wherein the bonding structure has a first width defined by an opening in the passivation layer and a second width defined by an opening in the insulating layer claim 1 , the first width being narrower than the second width.3. The semiconductor device of claim 2 , wherein the first width is less than the width of the bond pad.4. The semiconductor device of claim 1 , wherein the bond pad and the bonding structure comprise the same conductive material.5. The semiconductor device of claim 4 , wherein the conductive material is copper.6. The semiconductor device of claim 1 , further comprises a bonding wire directly over the bond pad.7. The semiconductor device of claim 6 , wherein the bonding wire comprises a same conductive material as the bonding structure.8. The semiconductor device of claim 1 , wherein the bonding structure abuts upon the bond pad.9. The semiconductor device of claim 8 , wherein the bonding structure has an upper surface that is substantially coplanar with the upper surface of the insulating layer.10. The semiconductor device of claim 1 , further comprises a dielectric ...

METHOD FOR PERMANENT CONNECTION OF TWO METAL SURFACES

A process for the production of a permanent, electrically conductive connection between a first metal surface of a first substrate and a second metal surface of a second substrate, wherein a permanent, electrically conductive connection is produced, at least primarily, by substitution diffusion between metal ions and/or metal atoms of the two metal surfaces. 1. A process for producing a permanent , electrically conductive connection between a first metal surface of a first substrate and a second metal surface of a second substrate wherein said process does not include a soldering process , said process comprising the following steps:conditioning first and second metal surfaces by producing near surface layers with surface defects, said surface defects produced by application of metallic nanoparticles,aligning said first metal surface relative to said second metal surface, andconnecting the first and second metal surfaces,wherein, during the conditioning, aligning, and connecting steps, a process temperature of at most 300° C. is not exceeded,wherein the connecting step produces a permanent, electrically conductive connection—produced at least primarily by substitution diffusion between similar metal ions and/or metal atoms of the two metal surfaces.2. The process according to claim 1 , wherein the first and/or second metal surfaces have a layer thickness S<5 nm.3. The process according to claim 1 , wherein the conditioning step comprises a step of optimizing a surface roughness of at least one of the metal surfaces.4. A process for producing a permanent claim 1 , electrically conductive connection between a first surface comprising metallic and non-metallic regions of a first substrate and a second surface comprising metallic and non-metallic regions of a second substrate claim 1 , the process comprising the following steps:conditioning the first and/or second surfaces in such a way that, when the surfaces are connected, a permanent, electrically conductive ...

Method for permanent connection of two metal surfaces

本发明涉及用于永久连接两个金属表面的方法。本发明涉及用于在第一衬底的第一金属表面和第二衬底的第二金属表面之间制造永久的导电连接的方法，具有如下方法步骤：通过产生表面缺陷处理第一和第二金属表面，使得在连接金属表面时制造至少主要由于在两个金属表面的金属离子和/或金属原子之间的置换扩散而产生的永久的导电键合，定向和键合第一和第二金属表面，其中应用热处理，使得发生第一和第二金属表面的近表面层的构造的再组织。

Method for permanent connection of two metal surfaces

The invention relates to a process for the production of a permanent, electrically conductive connection between a first metal surface of a first substrate and a second metal surface of a second substrate with the following method steps, in particular the course of the method: Conditioning of the first and second metal surfaces in such a way that in a connection of the metal surfaces, in particular in a time period of a few minutes after the conditioning, a permanent, electrically conductive connection-produced at least primarily by substitution diffusion between in particular similar, preferably identical, metal ions and/or metal atoms of the two metal surfaces-can be produced, Orientation and connection of the first and second metal surfaces, whereby during the conditioning, orientation and connection, a process temperature of at most 300 DEG C, in particular at most 260 DEG C, preferably 230 DEG C, even more preferably 200 DEG C, especially preferably at most 180 DEG C, and ideally at ...

METHOD FOR PERMANENT CONNECTION OF TWO METAL SURFACES

Method for permanently connecting two metal surfaces

CONTACT STRUCTURES WITH POROUS NETWORKS FOR SOLDER CONNECTIONS, AND METHODS OF FABRICATING SAME

A contact pad includes a solder-wettable porous network ( 310 ) which wicks the molten solder ( 130 ) and thus restricts the lateral spread of the solder, thus preventing solder bridging between adjacent contact pads.

Method for fabricating semiconductor devices having high-precision gaps

本发明提供一种具精确间隙的微机电晶圆结构及其制作方法，该制作方法包括以下步骤。首先，提供一第一晶圆，第一晶圆具有一第一表面。接着，于该第一表面的形成至少两个以上具有不同掺杂浓度或不同掺杂物的掺杂区，以使每一该掺杂区具有不同的氧化速率。再来，对第一晶圆进行热氧化，以使不同的掺杂区上形成不同厚度的氧化层。之后，提供一第二晶圆。然后，将第二晶圆与第一晶圆相结合。本发明的有益效果是可以制造出成本较低、电容间极板具精确间隙的微机电晶圆结构。

Method for permanent connection of two metal surfaces

A process for the production of a permanent, electrically conductive connection between a first metal surface of a first substrate and a second metal surface of a second substrate, wherein a permanent, electrically conductive connection is produced, at least primarily, by substitution diffusion between metal ions and/or metal atoms of the two metal surfaces.

Adhesion between post-passivation interconnect structure and polymer

An embodiment integrated circuit structure includes a substrate, a metal pad over the substrate, a post-passivation interconnect (PPI) structure over the substrate and electronically connected to the metal pad, a thin oxide film layer directly over a top surface of the PPI structure, and a polymer layer over the thin oxide film layer and PPI structure.

Contact structures with porous networks for solder connections, and methods of fabricating same

A contact pad includes a solder-wettable porous network (310) which wicks the molten solder (130) and thus restricts the lateral spread of the solder, thus preventing solder bridging between adjacent contact pads.

Method for permanent connection of two metal surfaces

A process for the production of a permanent, electrically conductive connection between a first metal surface of a first substrate and a second metal surface of a second substrate, wherein a permanent, electrically conductive connection is produced, at least primarily, by substitution diffusion between metal ions and/or metal atoms of the two metal surfaces.

For permanent connection of the method of the surface of the two metal

Bonded nanofluidic device chip stacks

A method of producing a bonded chip stack is described. A first nanofluidic device chip having a first through-wafer via is formed. A second nanofluidic device chip having a second through-wafer via is formed. The first nanofluidic device chip and the second nanofluidic device chip are washed with a detergent solution. A first surface of the first nanofluidic device chip and a second surface of the second nanofluidic device chip are activated by treating the first surface and the second surface with an activation solution. The first nanofluidic device chip and the second nanofluidic device chip are arranged in a stack. The first through-wafer via is aligned with the second through-wafer via in a substantially straight line. The stack of first and second nanofluidic device chips is subjected to annealing conditions.

Three-dimensional semiconductor device

A three-dimensional semiconductor device using redundant bonding-conductor structures to make inter-level electrical connections between multiple semiconductor chips is disclosed. A first chip, or other semiconductor substrate, forms a first active area on its upper surface, and a second chip or other semiconductor substrate forms a second active area on its upper surface. According to the present invention, when the second chip has been mounted above the first chip, either face-up or face-down, the first active area is coupled to the second active area by at least one redundant bonding-conductor structure. In one embodiment, each redundant bonding-conductor structure includes at least one via portion that extends completely through the second chip to perform this function. In another, the redundant bonding-conductor structure extends downward to the top level interconnect. The present invention also includes a method for making such a device.

MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE

A method for manufacturing a semiconductor device of the present invention is provided including the steps of forming a first conductive layer over a substrate; forming a second conductive layer containing a conductive particle and resin over the first conductive layer; and increasing an area where the first conductive layer and the second conductive layer are in contact with each other by irradiating the second conductive layer with a laser beam. By including the step of laser beam irradiation, the portion where the first conductive layer and the second conductive layer are in contact with each other can be increased and defective electrical connection between the first conductive layer and the second conductive layer can be improved.

Manufacturing method of semiconductor device

A method for manufacturing a semiconductor device of the present invention is provided including the steps of forming a first conductive layer over a substrate; forming a second conductive layer containing a conductive particle and resin over the first conductive layer; and increasing an area where the first conductive layer and the second conductive layer are in contact with each other by irradiating the second conductive layer with a laser beam. By including the step of laser beam irradiation, the portion where the first conductive layer and the second conductive layer are in contact with each other can be increased and defective electrical connection between the first conductive layer and the second conductive layer can be improved.

Bonding Structures of Integrated Circuit Devices and Method Forming the Same

A method includes forming a conductive pad over an interconnect structure of a wafer, forming a capping layer over the conductive pad, forming a dielectric layer covering the capping layer, and etching the dielectric layer to form an opening in the dielectric layer. The capping layer is exposed to the opening. A wet-cleaning process is then performed on the wafer. During the wet-cleaning process, a top surface of the capping layer is exposed to a chemical solution used for performing the wet-cleaning process. The method further includes depositing a conductive diffusion barrier extending into the opening, and depositing a conductive material over the conductive diffusion barrier.

METHOD FOR PERMANENTLY CONNECTING TWO METAL SURFACES

METHOD FOR PERMANENT CONNECTION OF TWO METAL SURFACES

Method for Permanent Connection of Two Metal Surfaces AbstractThe invention relates to a process for the production of a permanent, electrically conductive connection between a first metal surface of a first substrate and a second metal surface of a second substrate with the following method steps, in particular the course of the method:Conditioning of the first and second metal surfaces in such a way that in a connection of the metal surfaces, in particular in a time period of a fewminutes after the conditioning, a pennanent, electrically conductive connection - produced at least primarily by substitution diffusion between in particular similar, preferably identical, metal ions and/or metal atoms of the two metal surfaces can be produced,-Orientation and connection of the first and second metal surfaces, whereby during the conditioning, orientation and connection, a process temperature of at most 300°C, in particular at most 260°C, preferably 230°C, even more preferably 200°C, especially ...

Three-Dimensional Semiconductor Device

A three-dimensional semiconductor device using redundant bonding-conductor structures to make inter-level electrical connections between multiple semiconductor chips is disclosed. A first chip, or other semiconductor substrate, forms a first active area on its upper surface, and a second chip or other semiconductor substrate forms a second active area on its upper surface. According to the present invention, when the second chip has been mounted above the first chip, either face-up or face-down, the first active area is coupled to the second active area by at least one redundant bonding-conductor structure. In one embodiment, each redundant bonding-conductor structure includes at least one via portion that extends completely through the second chip to perform this function. In another, the redundant bonding-conductor structure extends downward to the top level interconnect. The present invention also includes a method for making such a device.

Bonding structures of integrated circuit devices and method forming the same

A method includes forming a conductive pad over an interconnect structure of a wafer, forming a capping layer over the conductive pad, forming a dielectric layer covering the capping layer, and etching the dielectric layer to form an opening in the dielectric layer. The capping layer is exposed to the opening. A wet-cleaning process is then performed on the wafer. During the wet-cleaning process, a top surface of the capping layer is exposed to a chemical solution used for performing the wet-cleaning process. The method further includes depositing a conductive diffusion barrier extending into the opening, and depositing a conductive material over the conductive diffusion barrier.

METHOD FOR PERMANENT CONNECTION OF TWO METAL SURFACES

A process for the production of a permanent, electrically conductive connection between a first metal surface of a first substrate and a second metal surface of a second substrate, wherein a permanent, electrically conductive connection is produced, at least primarily, by substitution diffusion between metal ions and/or metal atoms of the two metal surfaces.

Bonding structures of semiconductor devices

A semiconductor device is provided that includes a bond pad, an insulating layer, and a bonding structure. The bond pad is in a dielectric layer and the insulating layer is over the bond pad; the insulating layer having an opening over the bond pad formed therein. The bonding structure electrically couples the bond pad in the opening. The bonding structure has a height that at least extends to an upper surface of the insulating layer.

Method for permanent connection of two metal surfaces

The invention relates to a process for the production of a permanent, electrically conductive connection between a first metal surface of a first substrate and a second metal surface of a second substrate with the following method steps, in particular the course of the method: Conditioning of the first and second metal surfaces in such a way that in a connection of the metal surfaces, in particular in a time period of a few minutes after the conditioning, a permanent, electrically conductive connection produced at least primarily by substitution diffusion between in particular similar, preferably identical, metal ions and/or metal atoms of the two metal surfaces-can be produced, Orientation and connection of the first and second metal surfaces, whereby during the conditioning, orientation and connection, a process temperature of at most 300 DEG C, in particular at most 260 DEG C, preferably 230 DEG C, even more preferably 200 DEG C, especially preferably at most 180 DEG C, and ideally at ...

BONDING STRUCTURES OF INTEGRATED CIRCUIT DEVICES AND METHOD FORMING THE SAME

A method includes forming a conductive pad over an interconnect structure of a wafer, forming a capping layer over the conductive pad, forming a dielectric layer covering the capping layer, and etching the dielectric layer to form an opening in the dielectric layer. The capping layer is exposed to the opening. A wet-cleaning process is then performed on the wafer. During the wet-cleaning process, a top surface of the capping layer is exposed to a chemical solution used for performing the wet-cleaning process. The method further includes depositing a conductive diffusion barrier extending into the opening, and depositing a conductive material over the conductive diffusion barrier.

Method for permanently connecting two metal surfaces

Method for permanent connection of two metal surfaces

The invention relates to a process for the production of a permanent, electrically conductive connection between a first metal surface of a first substrate and a second metal surface of a second substrate with the following method steps, in particular the course of the method: Conditioning of the first and second metal surfaces in such a way that in a connection of the metal surfaces, in particular in a time period of a few minutes after the conditioning, a permanent, electrically conductive connection-produced at least primarily by substitution diffusion between in particular similar, preferably identical, metal ions and/or metal atoms of the two metal surfaces-can be produced, Orientation and connection of the first and second metal surfaces, whereby during the conditioning, orientation and connection, a process temperature of at most 300 DEG C, in particular at most 260 DEG C, preferably 230 DEG C, even more preferably 200 DEG C, especially preferably at most 180 DEG C, and ideally at ...

Method for permanent connection of two metal surfaces

The invention relates to a process for the production of a permanent, electrically conductive connection between a first metal surface of a first substrate and a second metal surface of a second substrate with the following method steps, in particular the course of the method: Conditioning of the first and second metal surfaces in such a way that in a connection of the metal surfaces, in particular in a time period of a few minutes after the conditioning, a permanent, electrically conductive connection-produced at least primarily by substitution diffusion between in particular similar, preferably identical, metal ions and/or metal atoms of the two metal surfaces-can be produced, Orientation and connection of the first and second metal surfaces, whereby during the conditioning, orientation and connection, a process temperature of at most 300 DEG C, in particular at most 260 DEG C, preferably 230 DEG C, even more preferably 200 DEG C, especially preferably at most 180 DEG C, and ideally at ...

METHOD FOR PERMANENT CONNECTION OF TWO METAL SURFACES

Method for Permanent Connection of Two Metal Surfaces AbstractThe invention relates to a process for the production of a permanent, electrically conductive connection between a first metal surface of a first substrate and a second metal surface of a second substrate with the following method steps, in particular the course of the method:Conditioning of the first and second metal surfaces in such a way that in a connection of the metal surfaces, in particular in a time period of a fewminutes after the conditioning, a permanent, electrically conductive connection - produced at least primarily by substitution diffusion between in particular similar, preferably identical, metal ions and/or metal atoms of the two metal surfaces can be produced,Orientation and connection of the first and second metal surfaces, whereby during the conditioning, orientation and connection, a process temperature of at most 300°C, in particular at most 260°C, preferably 230°C, even more preferably 200°C, especially ...

Three-dimensional semiconductor device

A three-dimensional semiconductor device using redundant bonding-conductor structures to make inter-level electrical connections between multiple semiconductor chips. A first chip, or other semiconductor substrate, forms a first active area on its upper surface, and a second chip or other semiconductor substrate forms a second active area on its upper surface. According to the present invention, when the second chip has been mounted above the first chip, either face-up or face-down, the first active area is coupled to the second active area by at least one redundant bonding-conductor structure. In one embodiment, each redundant bonding-conductor structure includes at least one via portion that extends completely through the second chip to perform this function. In another, the redundant bonding-conductor structure extends downward to the top level interconnect. The present invention also includes a method for making such a device.

MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE

METHOD FOR PERMANENT CONNECTION OF TWO METAL SURFACES

No Available Figure] ...

For permanent connection of the two metal surface method

Manufacturing method of semiconductor device

A method for manufacturing a semiconductor device of the present invention is provided including the steps of forming a first conductive layer over a substrate; forming a second conductive layer containing a conductive particle and resin over the first conductive layer; and increasing an area where the first conductive layer and the second conductive layer are in contact with each other by irradiating the second conductive layer with a laser beam. By including the step of laser beam irradiation, the portion where the first conductive layer and the second conductive layer are in contact with each other can be increased and defective electrical connection between the first conductive layer and the second conductive layer can be improved.

Contact structures with porous networks for solder connections, and methods of fabricating same

A contact pad includes a solder-wettable porous network (310) which wicks the molten solder (130) and thus restricts the lateral spread of the solder, thus preventing solder bridging between adjacent contact pads.

Method for permanent connection of two metal surfaces

The invention relates to a process for the production of a permanent, electrically conductive connection between a first metal surface of a first substrate and a second metal surface of a second substrate with the following method steps, in particular the course of the method: Conditioning of the first and second metal surfaces in such a way that in a connection of the metal surfaces, in particular in a time period of a few minutes after the conditioning, a permanent, electrically conductive connection-produced at least primarily by substitution diffusion between in particular similar, preferably identical, metal ions and/or metal atoms of the two metal surfaces-can be produced, Orientation and connection of the first and second metal surfaces, whereby during the conditioning, orientation and connection, a process temperature of at most 300 DEG C, in particular at most 260 DEG C, preferably 230 DEG C, even more preferably 200 DEG C, especially preferably at most 180 DEG C, and ideally at ...

METHOD FOR PERMANENT CONNECTION OF TWO METAL SURFACES

METHOD FOR PERMANENT CONNECTION OF TWO METAL SURFACES

Method for Permanent Connection of Two Metal Surfaces AbstractThe invention relates to a process for the production of a permanent, electrically conductive connection between a first metal surface of a first substrate and a second metal surface of a second substrate with the following method steps, in particular the course of the method:Conditioning of the first and second metal surfaces in such a way that in a connection of the metal surfaces, in particular in a time period of a fewminutes after the conditioning, a permanent, electrically conductive connection - produced at least primarily by substitution diffusion between in particular similar, preferably identical, metal ions and/or metal atoms of the two metal surfaces can be produced,Orientation and connection of the first and second metal surfaces, whereby during the conditioning, orientation and connection, a process temperature of at most 300°C, in particular at most 260°C, preferably 230°C, even more preferably 200°C, especially ...

Method for permanent connection of two metal surfaces

Method for permanent connection of two metal surfaces

Three-Dimensional Semiconductor Device

A three-dimensional semiconductor device using redundant bonding-conductor structures to make inter-level electrical connections between multiple semiconductor chips is disclosed. A first chip, or other semiconductor substrate, forms a first active area on its upper surface, and a second chip or other semiconductor substrate forms a second active area on its upper surface. According to the present invention, when the second chip has been mounted above the first chip, either face-up or face-down, the first active area is coupled to the second active area by at least one redundant bonding-conductor structure. In one embodiment, each redundant bonding-conductor structure includes at least one via portion that extends completely through the second chip to perform this function. In another, the redundant bonding-conductor structure extends downward to the top level interconnect. The present invention also includes a method for making such a device.

Manufacturing method of semiconductor device

A method for manufacturing a semiconductor device of the present invention is provided including the steps of forming a first conductive layer over a substrate; forming a second conductive layer containing a conductive particle and resin over the first conductive layer; and increasing an area where the first conductive layer and the second conductive layer are in contact with each other by irradiating the second conductive layer with a laser beam. By including the step of laser beam irradiation, the portion where the first conductive layer and the second conductive layer are in contact with each other can be increased and defective electrical connection between the first conductive layer and the second conductive layer can be improved.

METHOD FOR PERMANENT CONNECTION OF TWO METAL SURFACES

Method for permanent connection of two metal surfaces

Micro-eletromechanical wafer structure having accurate gap and manufacturing method thereof

本發明提供一種具精確間隙之微機電晶圓結構及其製作方法，該製作方法包括以下步驟。首先，提供一第一晶圓，第一晶圓具有一第一表面。接著，於該第一表面的形成至少兩個以上具不同摻雜濃度或不同摻雜物的摻雜區，以使每一該摻雜區具有不同的氧化速率。再來，對第一晶圓進行熱氧化，以使不同的摻雜區上形成不同厚度的氧化層。之後，提供一第二晶圓。然後，將第二晶圓與第一晶圓相結合。

Method for permanent connection of two metal surfaces

Micro-eletromechanical wafer structure having accurate gap and manufacturing method thereof

Method for permanent connection of two metal surfaces

Method for manufacturing semiconductor device

Method for permanently connecting two metal surfaces

Semiconductor package, packaging substrate and fabrication method thereof

A packaging substrate and a semiconductor package using the packaging substrate are provided. The packaging substrate includes: a substrate body having a die attach area, a circuit layer formed around the die attach area and having a plurality of conductive traces each having a wire bonding pad, and a surface treatment layer formed on the wire bonding pads. Therein, only one of the conductive traces is connected to an electroplating line so as to prevent cross-talk that otherwise occurs between conductive traces due to too many electroplating lines in the prior art.

FABRICATION METHOD OF PACKAGING SUBSTRATE

A packaging substrate and a semiconductor package using the packaging substrate are provided. The packaging substrate includes: a substrate body having a die attach area, a circuit layer formed around the die attach area and having a plurality of conductive traces each having a wire bonding pad, and a surface treatment layer formed on the wire bonding pads. Therein, only one of the conductive traces is connected to an electroplating line so as to prevent cross-talk that otherwise occurs between conductive traces due to too many electroplating lines in the prior art. 114-. (canceled)15. A fabrication method of a packaging substrate , comprising the steps of:providing a substrate body having a die attach area and a circuit layer formed around the die attach area, wherein the circuit layer has a plurality of conductive traces each having a first end positioned adjacent to the die attach area and an apposing second end positioned away from the die attach area, each of the first ends has a wire bonding pad, the second end of at least one of the conductive traces at at least one side of the die attach area is connected to an electroplating line, and the electroplating lines and the wire bonding pads at the same side of the die attach area are different in number;forming a conductive layer at an edge of the die attach area between the die attach area and the circuit layer, and electrically connecting the conductive layer to the conductive traces;performing an electroplating process through the conductive layer and the electroplating line so as to form a surface treatment layer on the wire bonding pads; andremoving the conductive layer.16. The package of claim 15 , wherein each of the wire bonding pads is connected to an extending line so as to be connected to the conductive layer.17. The method of claim 15 , wherein the conductive layer is removed by laser claim 15 , a chemical solution or a scraper.18. The method of claim 15 , further comprising forming an adhesive layer ...

DEVICE FOR CONTROLLING TRAPPED IONS AND METHOD OF MANUFACTURING THE SAME

A device for controlling trapped ions includes a first semiconductor substrate. A second semiconductor substrate is disposed over the first semiconductor substrate. At least one ion trap is configured to trap ions in a space between the first semiconductor substrate and the second semiconductor substrate. A spacer is disposed between the first semiconductor substrate and the second semiconductor substrate, the spacer including an electrical interconnect which electrically connects a first metal layer structure of the first semiconductor substrate to a second metal layer structure of the second semiconductor substrate. 1. A device for controlling trapped ions , the device comprising:a first semiconductor substrate;a second semiconductor substrate disposed over the first semiconductor substrate;at least one ion trap configured to trap ions in a space between the first semiconductor substrate and the second semiconductor substrate; anda spacer disposed between the first semiconductor substrate and the second semiconductor substrate, the spacer comprising an electrical interconnect which electrically connects a first metal layer structure of the first semiconductor substrate to a second metal layer structure of the second semiconductor substrate.2. The device of claim 1 , wherein:the first metal layer structure comprises first contact pads and first electrodes, the first electrodes forming part of the at least one ion trap; and{'claim-text': ['second contact pads of the second metal layer structure; and/or', 'second electrodes of the second metal layer structure, the second electrodes forming part of the at least one ion trap.'], '#text': 'the electrical interconnect electrically connects first contact pads to:'}3. The device of claim 1 , wherein the spacer comprises a printed circuit board.4. The device of claim 3 , wherein the printed circuit board is provided with vias forming the electrical interconnect.5. The device of claim 3 , wherein the printed circuit board ...

Method for Contacting and Rewiring an Electronic Component Embedded into a Printed Circuit Board

A method for contacting and rewiring an electronic component embedded in a PCB in the following manner is disclosed. A first permanent resist layer is applied to one contact side of the PCB. The first permanent resist layer is structured to produce exposures in the area of contacts of the electronic component. A second permanent resist layer is applied onto the structured first permanent resist layer. The second permanent resist layer is structured to expose the exposures in the area of the contacts and to produce exposures in line with the desired conductor tracks. The exposures are chemically coated with copper the copper is electric-plated to the exposures. Excess copper in the areas between the exposures is removed.

PACKAGE STRUCTURE

A package structure includes a chip, a selective-electroplating epoxy compound, a patterned circuit layer and a plurality of conductive vias. The chip includes a plurality of solder pads, an active surface and a back surface opposite to the active surface. The solder pads are disposed on the active surface. The selective-electroplating epoxy compound covers the chip and includes non-conductive metal complex. The patterned circuit layer is disposed directly on a surface of the selective-electroplating epoxy compound. The conductive vias are disposed directly at the selective-electroplating epoxy compound to electrically connect the solder pads and the patterned circuit layer. 1. A package structure , comprising:a first chip, comprising a plurality of first solder pads, an active surface, and a back surface opposite to the active surface, wherein the first solder pads are disposed on the active surface;a first selective-electroplating epoxy compound, covering the active surface of the first chip and the first solder pads on the active surface and comprising non-conductive metal complex;a first patterned circuit layer, directly disposed on a surface of the first selective-electroplating epoxy compound, wherein the first selective-electroplating epoxy compound exposes an upper surface of the patterned circuit layer, and the upper surface is lower than or coplanar with the surface of the first selective-electroplating epoxy compound; anda plurality of first conductive vias, disposed in the first selective-electroplating epoxy compound to electrically connect the first solder pads to the first patterned circuit layer.2. The package structure as claimed in claim 1 , wherein the non-conductive metal complex comprises a palladium claim 1 , chromium claim 1 , or copper complex.3. The package structure as claimed in claim 1 , wherein the first selective-electroplating epoxy compound is adapted to be selective irradiated by laser to selectively metalize the non-conductive metal ...

fabricating method of Organic light emitting display device

본 발명은 유기 전계 발광 표시장치의 제조 방법에 관한 것으로, 더욱 상세하게는, 프릿에 레이저를 조사하는 공정을 실시할 때 구비되는 마스크에 화소 영역에 대응하는 패턴부를 이중으로 형성하여, 열에 의한 화소 영역의 손상을 최소화할 수 있는 유기 전계 발광 표시장치의 제조 방법에 관한 것이다. 본 발명에 따른 유기 전계 발광 표시장치의 제조 방법은 적어도 하나의 유기 발광 다이오드가 형성된 화소 영역 및 상기 화소 영역의 외연에 형성되는 비화소 영역을 포함하는 제 1 기판과, 상기 제 1 기판의 상기 화소 영역을 포함한 일 영역에 합착 되는 제 2 기판을 포함하여 구성되는 유기 전계 발광 표시장치의 제조 방법에 있어서, 상기 제 2 기판의 일 영역 상에 프릿을 도포한 후 소정의 온도로 소성하는 단계, 상기 제 1 기판과 상기 제 2 기판을 합착하는 단계, 레이저가 투과되는 투과부와, 상기 투과부와의 접촉면에 적어도 이중으로 형성된 패턴부로 구성되는 마스크를 배열하는 단계 및 상기 마스크를 통해 상기 프릿에 국부적으로 레이저를 조사하여 상기 제 1 기판과 상기 제 2 기판을 접착시키는 단계를 포함한다. BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing an organic light emitting display device, and more particularly, to a pixel provided by a column formed by double forming a pattern portion corresponding to a pixel region in a mask provided when a laser is irradiated to a frit. The present invention relates to a method of manufacturing an organic light emitting display device which can minimize damage of an area. A method of manufacturing an organic light emitting display device according to the present invention includes a first substrate including a pixel region in which at least one organic light emitting diode is formed and a non-pixel region formed on an outer edge of the pixel region, and the pixel of the first substrate. A method of manufacturing an organic light emitting display device including a second substrate bonded to a region including a region, the method comprising: baking a frit on a region of the second substrate and then firing at a predetermined temperature; Bonding the first substrate to the second substrate, arranging a mask consisting of a transmission portion through which the laser passes, and a pattern portion formed at least in duplicate on the contact surface with the transmission portion, and locally lasering the frit through the mask Irradiating and bonding the first substrate and the second substrate. 패턴부, 투과부, 마스크, ...

Stereolithography Device Using Laser Pick-UP Unit and Method for Forming Structure Using the Device

본 발명에 의한 광조형 장치는, 용기에 수용되어 있는 광 경화성 수지에 레이저를 주사하여 구조물을 성형하는 광조형 장치로서, An optical shaping device according to the present invention is an optical shaping device for forming a structure by scanning a laser to a photocurable resin contained in a container, 상기 광 경화성 수지에 주사하는 레이저를 생성하는 레이저 다이오드와, 반사되는 레이저를 검출하는 광 검출기와, 상기 광 경화성 수지에 대한 레이저의 초점을 맺는 초점 렌즈를 포함하는 광 픽업 유니트와, An optical pickup unit including a laser diode for generating a laser to scan the photocurable resin, a photodetector for detecting the reflected laser, and a focus lens for focusing the laser on the photocurable resin; 상기 광 픽업 유니트를 제1 축 및 제2 축으로 이동 가능하게 지지하는 제1 스테이지와, A first stage for movably supporting the optical pickup unit on a first axis and a second axis; 상기 광 경화성 수지 내에 배치되어 그 상부에 위치하는 광 경화성 수지가 상기 레이저의 주사에 의해 성형 될 수 있도록 하는 성형 보조 부재와, A molding auxiliary member disposed in the photocurable resin and configured to allow the photocurable resin to be formed by scanning the laser; 상기 성형 보조 부재를 제3 축으로 이동 가능하게 지지하는 제2 스테이지를 포함한다. And a second stage for movably supporting the shaping auxiliary member in a third axis. 광조형, 광 픽업 유니트, 구조물, 광 경화성 수지 Optical molding, optical pickup unit, structure, photocurable resin

Pillar bump formed using spot-laser

A pillar bump, such as a copper pillar bump, is formed on an integrated circuit chip by applying a metallic powder over a conductive pad on a surface of the chip. The metallic powder is selectively spot-lasered to form the pillar bump. Any remaining unsolidified metallic powder may be removed from the surface of the chip. This process may be repeated to increase the bump height. Further, a solder cap may be formed on an outer surface of the pillar bump.

Method of manufacturing organic light emitting display device

A method for fabricating an organic light emitting display device is provided to melt a frit sufficiently by irradiating a laser beam with a wider width than the width of the frit. An organic light emitting device including a first electrode, an organic thin film layer and a second electrode is formed on a pixel region of a first substrate(200) which is divided into the pixel region and a non-pixel region. A frit(320) is formed along the peripheral part of a second substrate corresponding to the non-pixel region. The second substrate is arranged on the first substrate in order to overlap the pixel region and the non-pixel region partially. The first substrate and the second substrate are bonded by irradiating a laser beam with a wider width than the width of the frit.

Conductive buffer layers for semiconductor die assemblies and associated systems and methods

반도체 다이 어셈블리를 위한 전도성 버퍼층 및 관련 시스템 및 방법이 개시된다. 실시예에서, 반도체 다이 어셈블리는 서로 직접 접합된 제1 및 제2 반도체 다이들을 포함한다. 제1 반도체 다이는 제1 구리 패드를 포함하고, 제2 반도체 다이는 제2 구리 패드를 포함한다. 제1 및 제2 구리 패드들은 제1 반도체 다이와 제2 반도체 다이 사이의 인터커넥트를 형성하고, 인터커넥트는 제1 구리 패드와 제2 구리 패드 사이에 전도성 버퍼 물질을 포함하며, 전도성 버퍼 물질은 전도성 입자들의 집합체들을 포함한다. 일부 실시예들에서, 제1 및 제2 구리 패드들은 연접하지 않고, 전도성 버퍼 물질을 통해 서로 전기적으로 연결된다. 일부 실시예들에서, 전도성 버퍼 물질은 전도성 입자들의 집합체들이 전도성 버퍼층에 가해지는 압력에 반응하여 함께 압축되도록 다공성일 수 있다.

Solar cell and method of manufacturing the same

The present invention provides a solar cell including a metal electrode, an antireflection film, and a semiconductor substrate, in which a portion where the antireflection film is present and a portion where the antireflection film is absent are intermingled between the bottom of the metal electrode formed at the side of a light-receiving surface and the substrate, and the mean area percentage of the portion where the antireflection film is absent is 10% or more and 80% or less relative to the area of the bottom of the metal electrode. The present invention also provides a method of manufacturing a solar cell including a metal electrode, an antireflection film, and a semiconductor substrate, the method including a removal step of partially removing the antireflection film formed on the semiconductor substrate by irradiating with a laser beam having a wavelength of 380 nm or more and 500 nm or less.

Silicon carbide devices and methods of making the same

Eine Halbleitervorrichtung umfasst eine Siliziumcarbidschicht, eine auf der Siliziumcarbidschicht angeordnete Metallcarbidschicht und eine direkt auf der Metallcarbidschicht angeordnete Lotschicht.

Manufacturing method of SOI substrate and manufacturing method of semiconductor device

A manufacturing method of an SOI substrate which possesses a base substrate having low heat resistance and a very thin semiconductor layer having high planarity is demonstrated. The method includes: implanting hydrogen ions into a semiconductor substrate to form an ion implantation layer; bonding the semiconductor substrate and a base substrate such as a glass substrate, placing a bonding layer therebetween; heating the substrates bonded to each other to separate the semiconductor substrate from the base substrate, leaving a thin semiconductor layer over the base substrate; irradiating the surface of the thin semiconductor layer with laser light to improve the planarity and recover the crystallinity of the thin semiconductor layer; and thinning the thin semiconductor layer. This method allows the formation of an SOI substrate which has a single-crystalline semiconductor layer with a thickness of 100 nm or less over a base substrate.

Solar cells and their manufacturing methods

Manufacturing method of SOI substrate and manufacturing method of semiconductor device

A manufacturing method of an SOI substrate which possesses a base substrate having low heat resistance and a very thin semiconductor layer having high planarity is demonstrated. The method includes: implanting hydrogen ions into a semiconductor substrate to form an ion implantation layer; bonding the semiconductor substrate and a base substrate such as a glass substrate, placing a bonding layer therebetween; heating the substrates bonded to each other to separate the semiconductor substrate from the base substrate, leaving a thin semiconductor layer over the base substrate; irradiating the surface of the thin semiconductor layer with laser light to improve the planarity and recover the crystallinity of the thin semiconductor layer; and thinning the thin semiconductor layer. This method allows the formation of an SOI substrate which has a single-crystalline semiconductor layer with a thickness of 100 nm or less over a base substrate.

The electronic component electrical connection that will be embedded in printed circuit board and the method for rewiring

本发明涉及用于将嵌入在印制电路板(2)中的电子构件(1)电连接和重新接线的方法，其特征在于以下步骤：将第一永久抗蚀层(9)施加至该印制电路板(2)的一接点侧(8)，将该第一永久抗蚀层(9)结构化以在该电子构件(1)的接点(7)的范围内产生凹处(10)，将第二永久抗蚀层(11)施加至该已结构化的第一永久抗蚀层(9)上，将该第二永久抗蚀层(11)结构化以将在该些接点(7)的范围内的凹处(10)露出，并产生符合所期望的导电轨道(15)的露出处(12)，向该些露出处(10、12)以铜作化学涂层，流电地以铜填充该些露出处(10、12)，并将在该些凹处(10、12)之间的区域中的多余的铜去除。

Method for permanently connecting two metal surfaces

Die Erfindung betrifft ein Verfahren zur Herstellung einer permanenten, elektrisch leitfähigen Verbindung zwischen einer ersten, metallische und nichtmetallische Regionen aufweisenden Oberfläche eines ersten Substrats und einer zweiten, metallische und nichtmetallische Regionen aufweisenden Oberfläche eines zweiten Substrats mit folgenden Verfahrensschritten: - Bearbeitung der ersten und zweiten Oberfläche derart, dass bei einer Verbindung der Oberflächen eine permanente, zumindest überwiegend durch Substitutionsdiffusion zwischen Metallionen und/oder Metallatomen der metallischen Regionen der Oberflächen erzeugte, elektrisch leitfähige Verbindung hergestellt wird, - Ausrichtung und Verbindung der ersten und zweiten Oberfläche, wobei während der Bearbeitung, Ausrichtung und Verbindung eine Prozesstemperatur von maximal 300°C nicht überschritten wird. The invention relates to a method for producing a permanent, electrically conductive connection between a first, metallic and non-metallic regions surface of a first substrate and a second, metallic and non-metallic regions having surface of a second substrate with the following process steps: Processing of the first and second surfaces in such a way that, upon connection of the surfaces, a permanent, electrically conductive connection is produced, at least predominantly by substitution diffusion between metal ions and / or metal atoms of the metallic regions of the surfaces; - Alignment and connection of the first and second surface, wherein a maximum process temperature of 300 ° C is not exceeded during machining, alignment and connection.

Method for permanently connecting two metal surfaces

Package structure and manufacture method thereof

本发明提供一种封装结构以及封装结构的制作方法，所述封装结构包括第一芯片、第一可选择性电镀环氧树脂、第一图案化线路层以及复数个第一导通孔。第一芯片包括复数个第一焊垫、主动表面以及相对主动表面的背面，第一焊垫设置在主动表面上。第一可选择性电镀环氧树脂，覆盖第一芯片并包含非导电的金属复合物。第一图案化线路层直接设置在第一可选择性电镀环氧树脂的表面上。第一导通孔直接设置于第一可选择性电镀环氧树脂，以电性连接第一焊垫至第一图案化线路层。一种封装结构的制作方法也被提出。本发明处理步骤简单，且具有较大的线路设计弹性。

Method for permanently connecting two metal surfaces

The method involves processing metal surfaces of two respective substrates by production of adjacent-surface layers with defects. The adjacent-surface layers are produced by implanting ions of gas and/or deposition of an inferior metal layer and/or application of metallic nanoparticles. A permanent, electrically conductive connection is produced predominantly by substitution diffusion between metal ions and/or metal atoms of the metal surfaces during a connection of the metal surfaces. The metal surfaces are oriented and connected at maximum process temperature of 300 degree Celsius.

CARBON CONTROLLED OHMSCH CONTACT LAYER FOR A OHMSH REAR CONTACT ON A SILICON CARBIDE POWER SEMICONDUCTOR DEVICE

Eine Halbleiterleistungsvorrichtung kann eine Siliciumcarbidschicht (SiC-Schicht) einschließen, die eine aktive Leistungsvorrichtung aufweist, die auf einer ersten Oberfläche davon gebildet wird. Eine ohmsche Kontaktschicht kann auf einer zweiten gegenüberliegenden Oberfläche der SiC-Schicht gebildet werden, wobei die ohmsche Kontaktschicht Nickelsilizid (NiSix) mit einem ersten Silizidgebiet, das ein erstes Präzipitat aus nicht umgesetztem Kohlenstoff enthält, einschließt, das zwischen der SiC-Schicht und einem zweiten Silizidgebiet angeordnet ist. Das zweite Silizidgebiet kann zwischen dem ersten Silizidgebiet und einem dritten Silizidgebiet angeordnet sein und kann eine Mischung aus einem ersten Präzipitat aus Refraktärmetallcarbid und einem zweiten Präzipitat aus nicht umgesetztem Kohlenstoff einschließen. Das dritte Silizidgebiet kann ein zweites Präzipitat aus Refraktärmetallcarbid enthalten. Eine Lotschicht kann auf der ohmschen Kontaktschicht gebildet werden, wobei das dritte Silizidgebiet zwischen dem zweiten Silizidgebiet und der Lotschicht angeordnet ist. A semiconductor power device may include a silicon carbide (SiC) layer having an active power device formed on a first surface thereof. An ohmic contact layer may be formed on a second opposite surface of the SiC layer, the ohmic contact layer including nickel silicide (NiSix) with a first silicide region containing a first precipitate of unreacted carbon that is between the SiC layer and a second Silicide area is arranged. The second silicide region may be located between the first silicide region and a third silicide region and may include a mixture of a first precipitate of refractory metal carbide and a second precipitate of unreacted carbon. The third silicide region can contain a second precipitate of refractory metal carbide. A solder layer can be formed on the ohmic contact layer, the third silicide region being arranged between the second silicide region and the solder layer.

Connection electrode and method for manufacturing connection electrode

This connection electrode comprises: a metal film (40); a metal film (50); a mixed layer (45); and a UBM (80). The metal film (50) is formed on the metal film (40), and the UBM (80) is formed on the metal film (50). The mixed layer (45) is a layer in which metal particles (P40) forming the metal film (40) and metal particles (P50) forming the metal film (50) are mixed. When viewed in a first direction in which the metal film (40) and the metal film (50) are arranged, at least a portion of the mixed layer (45) is formed in a first region (Re1) that overlaps a bonding surface between the UBM (80) and the metal film (50).

Method for permanently connecting two metal surfaces

Die Erfindung betrifft ein Verfahren zur Herstellung einer permanenten, elektrisch leitfähigen Verbindung zwischen einer ersten Metalloberfläche eines ersten Substrats und einer zweiten Metalloberfläche eines zweiten Substrats mit folgenden Verfahrensschritten, insbesondere Verfahrensablauf: - Bearbeitung der ersten und zweiten Metalloberfläche derart, dass bei einer Verbindung der Metalloberflächen, insbesondere in einem Zeitraum von wenigen Minuten nach der Bearbeitung, eine permanente, zumindest überwiegend durch Substitutionsdiffusion zwischen, insbesondere gleichartigen, vorzugsweise gleichen, Metallionen und/oder Metallatomen der beiden Metalloberflächen erzeugte, elektrisch leitfähige Verbindung herstellbar ist, - Ausrichtung und Verbindung der ersten und zweiten Metalloberfläche, wobei während der Bearbeitung, Ausrichtung und Verbindung eine Prozesstemperatur von maximal 300°C, insbesondere maximal 260°C, vorzugsweise 230°C, noch bevorzugter 200°C, besonders bevorzugt maximal 180°C, idealerweise maximal 160°C, nicht überschritten wird.

A method of fabricating a memory with a stacked integrated circuit chip

Verfahren zum Herstellen eines Speichers mit einem gestapelten integrierten Schaltungschip, wobei mehrere erste Lötstellen vom ersten integrierten Schaltungschip entfernt werden, woraufhin auf dem ersten integrierten Schaltungschip Variationsisolierschichten ausgebildet werden. Anschließend werden mehrere Metallaufnahmeabschnitte durch Laserstrahl auf den Variationsisolierschichten ausgebildet. Dann werden mehrere leitfähige Chipstrukturen auf den Metallaufnahmeabschnitten ausgebildet. Daraufhin werden mehrere Lötstellen auf den leitfähigen Chipstrukturen ausgebildet, wobei ein zweiter integrierter Schaltungschip auf den leitfähigen Chipstrukturen bereitgestellt wird. Die Lötstellen des zweiten integrierten Schaltungschip sind mit dem leitfähigen Chipstrukturen so verbunden, dass sich ein gestapelter integrierter Schaltungschip ergibt, der schließlich mit einer Speichersubstrat-Baueinheit verbunden wird, um einen Speicher mit dem gestapelten integrierten Schaltungschip zu bilden. A method of fabricating a memory with a stacked integrated circuit chip, wherein a plurality of first solder pads are removed from the first integrated circuit chip, whereupon variation isolation layers are formed on the first integrated circuit chip. Subsequently, a plurality of metal receiving portions are formed by laser beam on the variation insulating layers. Then, a plurality of conductive chip patterns are formed on the metal receiving portions. Subsequently, a plurality of solder joints are formed on the conductive chip structures, wherein a second integrated circuit chip is provided on the conductive chip structures. The solder pads of the second integrated circuit chip are connected to the conductive chip structures to form a stacked integrated circuit chip that is finally connected to a memory substrate package to form a memory with the stacked integrated circuit chip.

Additive Manufacturing of a Frontside or Backside Interconnect of a Semiconductor Die

A method for fabricating a semiconductor die package includes: providing a semiconductor transistor die, the semiconductor transistor die having a first contact pad on a first lower main face and/or a second contact pad on an upper main face; fabricating a frontside electrical conductor onto the second contact pad and a backside electrical conductor onto the first contact pad; and applying an encapsulant covering the semiconductor die and at least a portion of the electrical conductor, wherein the frontside electrical conductor and/or the backside electrical conductor is fabricated by laser-assisted structuring of a metallic structure.

Semiconductor device

A semiconductor device according to an embodiment includes a semiconductor layer, a metal layer, and a bonding layer provided between the semiconductor layer and the metal layer, the bonding layer including a plurality of silver particles, and the bonding layer including a region containing gold existing between the plurality of silver particles.

Bondstrukturen von integrierten schaltungsvorrichtungen und verfahren zu deren bildung

Verfahren (200) umfassend: Bilden (202) eines leitfähigen Pads (32) über einer Interconnect-Struktur (6) eines Wafers; Bilden (202) einer Abdeckschicht (34) über dem leitfähigen Pad (32); Abscheiden (212) einer Seitenwandabdeckschicht (40), die sich auf Seitenwänden des leitfähigen Pads (32) und der Abdeckschicht (34) erstreckt; nach dem Abscheiden der Seitenwandabdeckschicht, Bilden (214) einer Dielektrikumschicht (44, 46), die die Abdeckschicht (34) bedeckt; Ätzen (216) der Dielektrikumschicht (44, 46), um eine Öffnung (52A) in der Dielektrikumschicht zu bilden, wobei die Abdeckschicht (34) durch die Öffnung (52A) freigelegt wird; Ausführen eines Nassreinigungsprozesses (218) auf den Wafer, wobei während des Nassreinigungsprozesses eine obere Fläche der Abdeckschicht (34) einer chemischen Lösung ausgesetzt wird, die zum Durchführen des Nassreinigungsprozesses verwendet wird; Abscheiden (222) einer leitfähigen Diffusionssperre (54), die sich in die Öffnung (52A) erstreckt; und Abscheiden (224) eines leitfähigen Materials (56) über der leitfähigen Diffusionssperre (54); wobei das Abscheiden (212) der Seitenwandabdeckschicht (40) ein Abscheiden eines weiteren leitfähigen Materials umfasst.

Bondstrukturen von integrierten schaltungsvorrichtungen und verfahren zu deren bildung

Ein Verfahren umfasst das Bilden eines leitfähigen Pads über einer Interconnect-Struktur eines Wafers, das Bilden einer Abdeckschicht über dem leitfähigen Pad, das Bilden einer Dielektrikumschicht, die die Abdeckschicht bedeckt, und das Ätzen der Dielektrikumschicht, um eine Öffnung in der Dielektrikumschicht zu bilden. Die Abdeckschicht ist durch die Öffnung freigelegt. Dann wird ein Nassreinigungsprozess auf den Wafer ausgeführt. Während des Nassreinigungsprozesses wird eine obere Fläche der Abdeckschicht einer chemischen Lösung ausgesetzt, die zur Ausführung des Nassreinigungsprozesses verwendet wird. Das Verfahren umfasst ferner das Abscheiden einer leitfähigen Diffusionssperre, die sich in die Öffnung hinein erstreckt, und das Abscheiden eines leitfähigen Materials über der leitfähigen Diffusionssperre.

Semiconductor device

A semiconductor device according to an embodiment includes a semiconductor layer, a metal layer, and a bonding layer provided between the semiconductor layer and the metal layer, the bonding layer including a plurality of silver particles, and the bonding layer including a region containing gold existing between the plurality of silver particles.

Semiconductor device and method for manufacturing semiconductor device

A semiconductor device includes: a foundation layer that is provided on a substrate and is electrically conductive; a nickel layer provided on the foundation layer; and a solder provided on the nickel layer, the nickel layer having a first region on a side of the foundation layer and a second region on a side of the solder, the second region being harder than the first region.

Conductive buffer layers for semiconductor die assemblies and associated systems and methods

Conductive buffer layers for semiconductor die assemblies, and associated systems and methods are disclosed. In an embodiment, a semiconductor die assembly includes first and second semiconductor dies directly bonded to each other. The first semiconductor die includes a first copper pad and the second semiconductor die includes a second copper pad. The first and second copper pads form an interconnect between the first and second semiconductor dies, and the interconnect includes a conductive buffer material between the first and second copper pads, where the conductive buffer material includes aggregates of conductive particles. In some embodiments, the first and second copper pads are not conjoined but electrically connected to each other through the conductive buffer material. In some embodiments, the conductive buffer material is porous such that the aggregates of conductive particles can be compressed together in response to the pressure applied to the conductive buffer layer.

半導體晶粒、半導體晶粒總成以及其形成方法

本發明揭示用於半導體晶粒總成之導電緩衝層以及其相關聯系統及方法。在一實施例中，一種半導體晶粒總成包括直接接合至彼此之第一半導體晶粒及第二半導體晶粒。該第一半導體晶粒包括一第一銅墊且該第二半導體晶粒包括一第二銅墊。該第一銅墊及該第二銅墊形成該第一半導體晶粒與該第二半導體晶粒之間的一互連件，且該互連件包括處於該第一銅墊與該第二銅墊之間的一導電緩衝材料，其中該導電緩衝材料包括導電粒子聚集體。在一些實施例中，該第一銅墊及該第二銅墊不結合，但藉由該導電緩衝材料彼此電連接。在一些實施例中，該導電緩衝材料係多孔的，使得該等導電粒子聚集體可回應於施加至該導電緩衝層之壓力而被壓縮在一起。

半导体管芯的前侧或背侧互连的附加制造

一种用于制造半导体管芯封装的方法(100)，该方法包括：(110)提供半导体晶体管管芯，该半导体晶体管管芯可能地包括在第一下主面上的第一接触焊盘和/或在上主面上的第二接触焊盘；(120)向所述第二接触焊盘上制造前侧电导体，并且可能地向所述第一接触焊盘上制造背侧电导体；以及(130)施加覆盖所述半导体管芯以及所述前侧电导体的至少一部分的包封体，其中，所述前侧电导体和/或所述背侧电导体是通过金属结构的激光辅助结构化来制造的。

Semiconductor die package

A semiconductor die package includes a semiconductor transistor die having a contact pad on an upper main face. The semiconductor die package also includes an electrical conductor disposed on the contact pad and fabricated by laser-assisted structuring of a metallic material, and an encapsulant covering the semiconductor die and at least a portion of the electrical conductor.

封装件结构、封装基板结构及其制法

一种封装件结构、封装基板结构及其制法，该封装基板结构包括：具有置晶区的基板本体、设于该置晶区外围且具有打线垫的线路层、以及形成于打线垫上的表面处理层，该线路层具有多个导电迹线，且仅于其中一导电迹线具有电镀线。借以避免过多电镀线影响各该导电迹线的信号传递，所以可避免发生串音现象。

封装件结构、封装基板结构及其制法

一种封装件结构、封装基板结构及其制法，该封装基板结构包括：具有置晶区的基板本体、设于该置晶区外围且具有打线垫的线路层、以及形成于打线垫上的表面处理层，该线路层具有多个导电迹线，且仅于其中一导电迹线具有电镀线。借以避免过多电镀线影响各该导电迹线的信号传递，所以可避免发生串音现象。

다이 본딩 패드들 및 그 형성 방법들

실시예에서, 디바이스는: 반도체 기판의 활성 표면 위의 유전체 층; 유전체 층 내에 있고, 불균일한 그레인 배향을 갖는 제1 구리 층을 포함하는 도전성 비아; 및 도전성 비아 위에 그리고 유전체 층 내에 있는 본딩 패드를 포함하고, 본딩 패드는 균일한 그레인 배향을 갖는 제2 구리 층을 포함하며, 본딩 패드의 상부면은 유전체 층의 상부면과 동일 평면 상에 있다.

半導體裝置及其形成方法

在一實施例中，一種裝置包括介電層、導電通孔以及接合墊。介電層位於半導體基板的主動面上方。導電通孔位於介電層中，且導電通孔包括第一銅層，具有非均勻晶向。接合墊位於導電通孔上方和介電層中，且接合墊包括第二銅層，具有均勻晶向，接合墊的頂表面與介電層的頂表面共面。

Metal bump structure and manufacturing method thereof and driving substrate

A manufacturing method of a metal bump structure is provided. A driving base is provided. At least one pad and an insulating layer are formed on the driving base. The pad is formed on an arrangement surface of the driving base and has an upper surface. The insulating layer covers the arrangement surface of the driving base and the pad, and exposes a part of the upper surface of the pad. A patterned metal layer is formed on the upper surface of the pad exposed by the insulating layer, and extends to cover a part of the insulating layer. An electro-less plating process is performed to form at least one metal bump on the patterned metal layer. A first extension direction of the metal bump is perpendicular to a second extension direction of the driving base.

用於在碳化矽功率半導體裝置上之背側歐姆接觸的受碳控制之歐姆接觸層

一種半導體功率裝置可包括碳化矽(SiC)層，該SiC層具有形成在該SiC層之第一表面上之主動功率裝置。歐姆接觸層可在該SiC層之第二相對表面上形成，該歐姆接觸層包括矽化鎳(NiSix)，其中含有第一未反應碳沉澱物的第一矽化物區域設置在該SiC層與第二矽化物區域之間。該第二矽化物區域可設置在該第一矽化物區域與第三矽化物區域之間，且該第二矽化物區域可包括第一耐火金屬碳化物沉澱物與第二未反應碳沉澱物的混合物。該第三矽化物區域可含有第二耐火金屬碳化物沉澱物。焊料金屬層可形成在該歐姆接觸層上，其中該第三矽化物區域設置在該第二矽化物區域與該焊料金屬層之間。

具有堆疊式積體電路晶片之記憶體製作方法

一種具有堆疊式積體電路晶片之記憶體製作方法。首先，將複數個第一焊接結構自第一積體電路晶片上移除。接著，在第一積體電路晶片上形成變異絕緣層。接下來，藉由雷射光束使變異絕緣層形成複數個金屬設置部。之後，在金屬設置部形成複數個晶片導電結構。之後，在晶片導電結構形成複數個焊接結構，並提供一設有複數個焊接結構之第二積體電路晶片。使第二積體電路晶片之焊接結構連結於晶片導電結構，藉以形成一堆疊式積體電路晶片。最後，將堆疊式積體電路晶片連結於一記憶體基板組件，藉以形成一具有堆疊式積體電路晶片之記憶體。

Semiconductor device

A semiconductor device according to an embodiment includes a semiconductor layer, a metal layer, and a bonding layer provided between the semiconductor layer and the metal layer, the bonding layer including a plurality of silver particles, and the bonding layer including a region containing gold existing between the plurality of silver particles.

Die Bonding Pads and Methods of Forming the Same

In an embodiment, a device includes: a dielectric layer over an active surface of a semiconductor substrate; a conductive via in the dielectric layer, the conductive via including a first copper layer having a non-uniform grain orientation; and a bonding pad over the conductive via and in the dielectric layer, the bonding pad including a second copper layer having a uniform grain orientation, a top surface of the bonding pad being coplanar with a top surface of the dielectric layer.

Conductive buffer layers for semiconductor die assemblies and associated systems and methods

Conductive buffer layers for semiconductor die assemblies, and associated systems and methods are disclosed. In an embodiment, a semiconductor die assembly includes first and second semiconductor dies directly bonded to each other. The first semiconductor die includes a first copper pad and the second semiconductor die includes a second copper pad. The first and second copper pads form an interconnect between the first and second semiconductor dies, and the interconnect includes a conductive buffer material between the first and second copper pads, where the conductive buffer material includes aggregates of conductive particles. In some embodiments, the first and second copper pads are not conjoined but electrically connected to each other through the conductive buffer material. In some embodiments, the conductive buffer material is porous such that the aggregates of conductive particles can be compressed together in response to the pressure applied to the conductive buffer layer.

半導体装置及び半導体装置の製造方法

【課題】低コストで、半田の拡散を抑制し、かつストレスを緩和することが可能な半導体装置及び半導体装置の製造方法を提供すること。 【解決手段】本発明は、基板１０上に設けられた下地層１２と、無電解メッキ法により下地層１２上に設けられたＮｉ層１６と、Ｎｉ層１６上に設けられた半田ボール２０と、を具備し、Ｎｉ層１６の半田ボール２０側の領域である第２領域１６ｂは、Ｎｉ層１６の下地層１２側の領域である第１領域１６ａに比べて硬い半導体装置、及び半導体装置の製造方法である。 【選択図】図１

Semiconductor device and method for manufacturing semiconductor device

A semiconductor device includes: a foundation layer that is provided on a substrate and is electrically conductive; a nickel layer provided on the foundation layer; and a solder provided on the nickel layer, the nickel layer having a first region on a side of the foundation layer and a second region on a side of the solder, the second region being harder than the first region.

连接电极及连接电极的制造方法

连接电极具备金属膜(40)、金属膜(50)、混合层(45)及UBM(80)。金属膜(50)形成在金属膜(40)上，UBM(80)形成在金属膜(50)上。混合层(45)是形成金属膜(40)的金属颗粒(P40)与形成金属膜(50)的金属颗粒(P50)混合的层。在沿金属膜(40)及金属膜(50)排列的第一方向观察时，混合层(45)的至少一部分形成在与UBM(80)和金属膜(50)的接合面重叠的第一区域(Re1)。

Die-bondpads und verfahren zu deren herstellung

Bei einer Ausführungsform weist eine Vorrichtung Folgendes auf: eine dielektrische Schicht über einer aktiven Seite eines Halbleitersubstrats; eine leitfähige Durchkontaktierung in der dielektrischen Schicht, wobei die leitfähige Durchkontaktierung eine erste Kupferschicht mit einer ungleichmäßigen Kornorientierung aufweist; und ein Bondpad über der leitfähigen Durchkontaktierung und in der dielektrischen Schicht, wobei das Bondpad eine zweite Kupferschicht mit einer gleichmäßigen Kornorientierung aufweist und eine Oberseite des Bondpads mit einer Oberseite der dielektrischen Schicht koplanar ist.

Device for controlling trapped ions

A device for trapping ions includes: a substrate having a metal layer structure; and at least one ion trap configured to trap ions in a space over the substrate. The metal layer structure is a multi-layer metal structure that includes: a top metal layer having one or more electrodes forming part of the at least one ion trap; a redistribution metal layer having wiring for connecting the one or more electrodes; a first insulating layer arranged between the top metal layer and the redistribution layer and having one or more voids; and one or more connection elements arranged in the one or more voids that connect the wiring from the redistribution metal layer with the one or more electrodes in the top metal layer.

Device for controlling trapped ions and method of manufacturing the same

A device for controlling trapped ions includes a first semiconductor substrate. A second semiconductor substrate is disposed over the first semiconductor substrate. At least one ion trap is configured to trap ions in a space between the first semiconductor substrate and the second semiconductor substrate. A spacer is disposed between the first semiconductor substrate and the second semiconductor substrate, the spacer including an electrical interconnect which electrically connects a first metal layer structure of the first semiconductor substrate to a second metal layer structure of the second semiconductor substrate.

투명 전극 박막의 직접 패터닝 방법 및 이를 이용한 박막 회수 방법

본 발명에 따라서 기판 상의 투명 전극 직접 패터닝 방법이 제공되는데, 상기 방법은 (a) 기판을 준비하는 단계와; (b) 상기 기판의 일면에 투명 전극층을 형성하는 단계와; (c) 상기 투명 전극층의 광파장에 대한 투과율 스펙트럼을 분석하는 단계와; (d) 상기 투과율 스펙트럼과 관련하여, 광흡수성을 나타내는 파장 대역 및 펄스 폭을 갖는 펄스 레이저를 사용자가 원하는 임의의 형태의 패턴으로 된 공간적 광 변조기를 통해 통과시켜, 상기 투명 전극층에 조사함으로써, 상기 공간적 광 변조기의 패턴에 대응되는 패턴을 상기 투명 전극층에 형성하는 투명 전극층 패터닝 단계로서, 상기 펄스 레이저 조사로 인한 급속 열팽창에 의해 상기 투명 전극층에 열탄성력을 야기하고, 이 열탄성력에 의해 상기 투명 전극층 일부가 기판으로부터 분리되어, 상기 패턴을 형성하는 것인, 투명 전극층 패터닝 단계를 포함하는 것을 특징으로 한다.

金屬凸塊結構及其製作方法與驅動基板

一種金屬凸塊結構的製作方法。提供一驅動基材。驅動基材上已形成有至少一接墊以及一絕緣層。接墊形成於驅動基材的一配置面上且具有一上表面。絕緣層覆蓋驅動基材的配置面與接墊且暴露出接墊的部分上表面。形成一圖案化金屬層於絕緣層所暴露出的接墊的上表面上且延伸覆蓋部分絕緣層。進行一化學鍍程序，以於圖案化金屬層上形成至少一金屬凸塊。金屬凸塊的一第一延伸方向垂直於驅動基材的一第二延伸方向。

유기 전계 발광 소자의 패턴 결함 수정방법

본 발명의 유기 전계 발광 소자의 패턴 결함 수정방법은, 기판 상에 패턴을 형성하는 단계; 기판 상에 집속이온빔(FIB)장비를 배치하고, 집속이온빔(FIB)장비의 이온현미경(SIM)을 이용하여 패턴 상에 발생한 결함을 관측하여 이미지를 추출하는 단계; 추출된 이미지로부터 오차 정보 데이터를 형성하는 단계; 및 집속이온빔(FIB)장비에 오차 정보 데이터를 입력하고, 집속이온빔 에칭공정을 실시하여 패턴 상에 발생한 결함을 제거하는 단계를 포함한다. 집속이온빔(FIB)공정, 오차 정보 데이터

In einem kunststoffkörper eingebettetes funktionselement und verfahren zur elektrischen kontaktierung eines in einem kunststoffkörper eingebetteten funktionselements

Die Anmeldung betrifft ein Verfahren zur Herstellung einer elektrischen Kontaktierung für ein gehäustes Funktionselement, mit folgenden Schritten: Bereitstellen eines mit einer Ausnehmung (10-2) versehenen Kunststoffsubstrats (10c), wobei in der Ausnehmung (10-2) des Kunststoffsubstrats (10c) das Funktionselement (12) platziert ist; und zumindest teilweises Umgeben des in der Ausnehmung (10-2) platzierten Funktionselements mit einem Vergusskunststoffmaterial (10d), um das in dem Kunststoffkörper zumindest teilweise eingebettete Funktionselement (12) zu erhalten, wobei in dem auf- oder eingebrachten Vergusskunststoffmaterial zumindest in einem Randbereich, der sich von der Oberfläche des Kunststoffkörpers (10) bis zu der zumindest einen Kontaktfläche (14, 16) erstreckt, ferner eine unter Einfluss elektromagnetischer Strahlung eine metallische Eigenschaft annehmende Materialkomponente vorhanden ist; Freilegen von zumindest einem Teilbereich der zumindest einen Kontaktfläche durch das Material des Kunststoffkörpers (10) hindurch; und Erzeugen einer Leiterbahnstruktur (26, 28), die sich von der zumindest einen Kontaktfläche des Funktionselements (12) zu einem zugeordneten Kontaktbereich (26-1) an der Oberfläche (10-1) des Kunststoffkörpers (10) erstreckt, durch lokales elektromagnetisches Bestrahlen der Oberfläche des mit der Materialkomponente versehenen Kunststoffkörpers im Bereich der zu erzeugenden Leiterbahnstruktur (26, 28).

用于控制俘获的离子的装置及其制造方法

本公开涉及用于控制俘获的离子的装置及其制造方法。一种控制俘获的离子的装置包括第一半导体衬底。第二半导体衬底设置在第一半导体衬底上方。至少一个离子阱在第一半导体衬底和第二半导体衬底之间的空间中被配置成俘获离子。在第一半导体衬底和第二半导体衬底之间设置间隔物，该间隔物包括将第一半导体衬底的第一金属层结构电连接到第二半导体衬底的第二金属层结构的电互连。

封裝件結構、封裝基板結構及其製法

一種封裝基板結構，係包括：具有置晶區之基板本體、設於該置晶區外圍且具有打線墊的線路層、以及形成於打線墊上之表面處理層，該線路層具有複數導電跡線，且僅於其中一導電跡線具有電鍍線。藉以避免過多電鍍線影響各該導電跡線之訊號傳遞，故可避免發生串音現象。本發明復提供該封裝基板結構之製法與封裝件結構。

集成电路器件的接合结构及其形成方法

一种方法，包括：形成位于晶圆的互连结构上方的导电焊盘，形成位于导电焊盘上方的覆盖层，形成覆盖覆盖层的介电层，以及蚀刻介电层，以形成位于介电层中的开口。覆盖层暴露至开口。然后实施湿式清洁工艺至晶圆上。在湿式清洁工艺期间，覆盖层的顶面暴露至用于实施湿式清洁工艺的化学溶液。该方法还包括沉积延伸进入开口的导电的扩散势垒，以及沉积位于导电的扩散势垒上方的导电材料。本申请的实施例提供了集成电路器件的接合结构及其形成方法。

有机发光显示装置及其制造

本发明公开了一种有机发光显示装置的制造方法，该方法通过照射激光束使玻璃料能够充分地熔化，照射激光束的方式为通过调整激光束功率使得激光束的宽度可大于玻璃料的宽度。这种有机发光显示装置的制造方法包括以下步骤：a)在划分为像素区和非像素区的第一基底的像素区上形成包括第一电极、有机薄膜和第二电极的有机发光元件；b)沿着第二基底的对应于非像素区的周围形成玻璃料；c)将第二基底布置在第一基底的上面上，以使第二基底叠置在像素区和部分非像素区上；d)通过从第二基底的后表面用宽度大于玻璃料宽度的激光束照射使第一基底和第二基底粘附。

半导体功率器件及其制备方法

本发明题为“用于碳化硅功率半导体器件上的背侧欧姆接触的碳受控欧姆接触层”。本发明公开了一种半导体功率器件，所述半导体功率器件可包括在其第一表面上形成有有源功率器件的碳化硅SiC层。可在所述SiC层的第二相对表面上形成欧姆接触层，所述欧姆接触层包括具有第一硅化物区域的硅化镍NiSix，所述第一硅化物区域包含第一未反应的碳的析出物并且设置在所述SiC层与第二硅化物区域之间。所述第二硅化物区域可设置在所述第一硅化物区域与第三硅化物区域之间，并且可包含第一难熔金属碳化物的析出物和第二未反应的碳的析出物的混合物。所述第三硅化物区域可包含第二难熔金属碳化物的析出物。可在所述欧姆接触层上形成焊料金属层，其中所述第三硅化物区域设置在所述第二硅化物区域与所述焊料金属层之间。

用于半导体裸片组合件的导电缓冲层以及相关联的系统和方法

公开用于半导体裸片组合件的导电缓冲层以及相关联的系统和方法。在实施例中，半导体裸片组合件包含直接接合到彼此的第一半导体裸片和第二半导体裸片。所述第一半导体裸片包含第一铜垫且所述第二半导体裸片包含第二铜垫。所述第一铜垫和第二铜垫形成所述第一半导体裸片和第二半导体裸片之间的互连件，且所述互连件包含处于在所述第一铜垫和第二铜垫之间的导电缓冲材料，其中所述导电缓冲材料包含导电粒子聚合体。在一些实施例中，所述第一铜垫和第二铜垫不相连但通过所述导电缓冲材料彼此电连接。在一些实施例中，所述导电缓冲材料是多孔的以使得所述导电粒子聚合体可响应于施加到所述导电缓冲层的所述压力而被压缩在一起。

集成电路器件的接合结构及其形成方法

一种方法，包括：形成位于晶圆的互连结构上方的导电焊盘，形成位于导电焊盘上方的覆盖层，形成覆盖覆盖层的介电层，以及蚀刻介电层，以形成位于介电层中的开口。覆盖层暴露至开口。然后实施湿式清洁工艺至晶圆上。在湿式清洁工艺期间，覆盖层的顶面暴露至用于实施湿式清洁工艺的化学溶液。该方法还包括沉积延伸进入开口的导电的扩散势垒，以及沉积位于导电的扩散势垒上方的导电材料。本申请的实施例提供了集成电路器件的接合结构及其形成方法。

用于控制俘获的离子的装置及其制造方法

本公开涉及用于控制俘获的离子的装置及其制造方法。一种控制俘获的离子的装置包括第一半导体衬底。第二半导体衬底设置在第一半导体衬底上方。至少一个离子阱在第一半导体衬底和第二半导体衬底之间的空间中被配置成俘获离子。在第一半导体衬底和第二半导体衬底之间设置间隔物，该间隔物包括将第一半导体衬底的第一金属层结构电连接到第二半导体衬底的第二金属层结构的电互连。

半导体装置

本发明的实施方式的半导体装置具备半导体层、金属层及接合层，所述接合层设置于半导体层与金属层之间且包含多个银粒子和存在于多个银粒子之间的含有金的区域。

半导体管芯的前侧或背侧互连的附加制造

一种用于制造半导体管芯封装的方法(100)，该方法包括：(110)提供半导体晶体管管芯，该半导体晶体管管芯可能地包括在第一下主面上的第一接触焊盘和/或在上主面上的第二接触焊盘；(120)向所述第二接触焊盘上制造前侧电导体，并且可能地向所述第一接触焊盘上制造背侧电导体；以及(130)施加覆盖所述半导体管芯以及所述前侧电导体的至少一部分的包封体，其中，所述前侧电导体和/或所述背侧电导体是通过金属结构的激光辅助结构化来制造的。

连接电极及连接电极的制造方法

连接电极具备金属膜(40)、金属膜(50)、混合层(45)及UBM(80)。金属膜(50)形成在金属膜(40)上，UBM(80)形成在金属膜(50)上。混合层(45)是形成金属膜(40)的金属颗粒(P40)与形成金属膜(50)的金属颗粒(P50)混合的层。在沿金属膜(40)及金属膜(50)排列的第一方向观察时，混合层(45)的至少一部分形成在与UBM(80)和金属膜(50)的接合面重叠的第一区域(Re1)。

Bonding structures of integrated circuit devices and method forming the same

A method includes forming a conductive pad over an interconnect structure of a wafer, forming a capping layer over the conductive pad, forming a dielectric layer covering the capping layer, and etching the dielectric layer to form an opening in the dielectric layer. The capping layer is exposed to the opening. A wet-cleaning process is then performed on the wafer. During the wet-cleaning process, a top surface of the capping layer is exposed to a chemical solution used for performing the wet-cleaning process. The method further includes depositing a conductive diffusion barrier extending into the opening, and depositing a conductive material over the conductive diffusion barrier.

반도체 패키지 내 기판에 전력 단자를 연결하는 방법

본 개시내용의 구현예에 따른 전력 반도체 장치를 제조하는 방법은, 히트싱크 상부에 배치된 기판을 제공하는 단계, 기판의 상부 표면에 반도체 다이를 전기적으로 연결하는 단계, 기판의 상부에 얇은 금속층을 배치하는 단계, 상기 얇은 금속층의 상부에 단자를 배치하는 단계, 및 레이저 빔을 단자의 상부 표면으로 향하게 하여 단자와 기판을 연결하는 복수의 용접 연결부를 생성하고, 상기 용접 연결부는 간극으로 분리되며, 용접 작업 중에 발생하는 열이 얇은 금속층을 용융시키고, 얇은 금속층의 용융물이 상기 간극으로 유입되는, 용접 작업을 수행하는 단계를 포함할 수 있다.

具有可激光活化模制化合物的半导体封装

本发明提供了模制封装和对应制造方法的实施例。在模制封装的实施例中，所述模制封装包括具有多个激光活化区的可激光活化模制化合物，所述多个激光活化区镀覆有导电材料，以在可激光活化模制化合物的第一侧处形成金属焊盘和/或金属迹线。嵌入可激光活化模制化合物中的半导体管芯具有多个管芯焊盘。互连将半导体管芯的多个管芯焊盘电连接到可激光活化模制化合物的第一侧处的金属焊盘和/或金属迹线。

用于碳化硅功率半导体器件上的背侧欧姆接触的碳受控欧姆接触层

本发明题为“用于碳化硅功率半导体器件上的背侧欧姆接触的碳受控欧姆接触层”。本发明公开了一种半导体功率器件，所述半导体功率器件可包括在其第一表面上形成有有源功率器件的碳化硅SiC层。可在所述SiC层的第二相对表面上形成欧姆接触层，所述欧姆接触层包括具有第一硅化物区域的硅化镍NiSix，所述第一硅化物区域包含第一未反应的碳的析出物并且设置在所述SiC层与第二硅化物区域之间。所述第二硅化物区域可设置在所述第一硅化物区域与第三硅化物区域之间，并且可包含第一难熔金属碳化物的析出物和第二未反应的碳的析出物的混合物。所述第三硅化物区域可包含第二难熔金属碳化物的析出物。可在所述欧姆接触层上形成焊料金属层，其中所述第三硅化物区域设置在所述第二硅化物区域与所述焊料金属层之间。

Semiconductor device

A semiconductor device according to an embodiment includes a semiconductor layer, a metal layer, and a bonding layer provided between the semiconductor layer and the metal layer, the bonding layer including a plurality of silver particles, and the bonding layer including a region containing gold existing between the plurality of silver particles.

Method for manufacturing memory having stacked integrated circuit chip

A method for manufacturing a memory having at least one stacked integrated circuit chip is firstly to remove a plurality of transitional weld structures from a first IC chip. A varied insulation layer is then formed on the first IC chip. The varied insulation layer is then processed by a laser beam to form a plurality of metal-disposed portions. A plurality of chip-conductive structures are then formed on the metal-disposed portions. A plurality of manufactured weld structures is formed on the chip conductive structures. A second IC chip having a plurality of original weld structures is then provided to the first IC chip. The original weld structures of the second IC chip are connected to the chip conductive structures of the first IC chip to form a stacked IC chip. The stacked IC chip is then mounted onto a memory substrate component to form a memory having the stacked IC chip.

Bonding structures of integrated circuit devices and method forming the same

A method includes forming a conductive pad over an interconnect structure of a wafer, forming a capping layer over the conductive pad, forming a dielectric layer covering the capping layer, and etching the dielectric layer to form an opening in the dielectric layer. The capping layer is exposed to the opening. A wet-cleaning process is then performed on the wafer. During the wet-cleaning process, a top surface of the capping layer is exposed to a chemical solution used for performing the wet-cleaning process. The method further includes depositing a conductive diffusion barrier extending into the opening, and depositing a conductive material over the conductive diffusion barrier.