NANOSTRUCTURE BARRIER FOR COPPER WIRE BONDING

A nanostructure barrier for copper wire bonding includes metal grains and inter-grain metal between the metal grains. The nanostructure barrier includes a first metal selected from nickel or cobalt, and a second metal selected from tungsten or molybdenum. A concentration of the second metal is higher in the inter-grain metal than in the metal grains. The nanostructure barrier may be on a copper core wire to provide a coated bond wire. The nanostructure barrier may be on a bond pad to form a coated bond pad. A method of plating the nanostructure barrier using reverse pulse plating is disclosed. A wire bonding method using the coated bond wire is disclosed.

Method of packaging and interconnection of integrated circuits

A semiconductor chip packaging on a flexible substrate is disclosed. The chip and the flexible substrate are provided with corresponding raised and indented micron-scale contact pads with the indented contact pads partially filled with a liquid amalgam. After low temperature amalgam curing, the chip and the substrate form a flexible substrate IC packaging with high conductivity, controllable interface layer thickness, micron-scale contact density and low process temperature. Adhesion between the chip and the substrate can be further enhanced by coating other areas with non-conducting adhesive.

Method of packaging and interconnection of integrated circuits

A semiconductor chip packaging on a flexible substrate is disclosed. The chip and the flexible substrate are provided with corresponding raised and indented micron-scale contact pads with the indented contact pads partially filled with a liquid amalgam. After low temperature amalgam curing, the chip and the substrate form a flexible substrate IC packaging with high conductivity, controllable interface layer thickness, micron-scale contact density and low process temperature. Adhesion between the chip and the substrate can be further enhanced by coating other areas with non-conducting adhesive.

Method of packaging and interconnection of integrated circuits

A semiconductor chip packaging on a flexible substrate is disclosed. The chip and the flexible substrate are provided with corresponding raised and indented micron-scale contact pads with the indented contact pads partially filled with a liquid amalgam. After low temperature amalgam curing, the chip and the substrate form a flexible substrate IC packaging with high conductivity, controllable interface layer thickness, micron-scale contact density and low process temperature. Adhesion between the chip and the substrate can be further enhanced by coating other areas with non-conducting adhesive.

Method of packaging and interconnection of integrated circuits

A semiconductor chip packaging on a flexible substrate is disclosed. The chip and the flexible substrate are provided with corresponding raised and indented micron-scale contact pads with the indented contact pads partially filled with a liquid amalgam. After low temperature amalgam curing, the chip and the substrate form a flexible substrate IC packaging with high conductivity, controllable interface layer thickness, micron-scale contact density and low process temperature. Adhesion between the chip and the substrate can be further enhanced by coating other areas with non-conducting adhesive.

NANOSTRUCTURE BARRIER FOR COPPER WIRE BONDING

A nanostructure barrier for copper wire bonding includes metal grains and inter-grain metal between the metal grains. The nanostructure barrier includes a first metal selected from nickel or cobalt, and a second metal selected from tungsten or molybdenum. A concentration of the second metal is higher in the inter-grain metal than in the metal grains. The nanostructure barrier may be on a copper core wire to provide a coated bond wire. The nanostructure barrier may be on a bond pad to form a coated bond pad. A method of plating the nanostructure barrier using reverse pulse plating is disclosed. A wire bonding method using the coated bond wire is disclosed.

Nanostructure barrier for copper wire bonding

A nanostructure barrier for copper wire bonding includes metal grains and inter-grain metal between the metal grains. The nanostructure barrier includes a first metal selected from nickel or cobalt, and a second metal selected from tungsten or molybdenum. A concentration of the second metal is higher in the inter-grain metal than in the metal grains. The nanostructure barrier may be on a copper core wire to provide a coated bond wire. The nanostructure barrier may be on a bond pad to form a coated bond pad. A method of plating the nanostructure barrier using reverse pulse plating is disclosed. A wire bonding method using the coated bond wire is disclosed.

Nanostructure barrier for copper wire bonding

A nanostructure barrier for copper wire bonding includes metal grains and inter-grain metal between the metal grains. The nanostructure barrier includes a first metal selected from nickel or cobalt, and a second metal selected from tungsten or molybdenum. A concentration of the second metal is higher in the inter-grain metal than in the metal grains. The nanostructure barrier may be on a copper core wire to provide a coated bond wire. The nanostructure barrier may be on a bond pad to form a coated bond pad. A method of plating the nanostructure barrier using reverse pulse plating is disclosed. A wire bonding method using the coated bond wire is disclosed.

Method of packaging and interconnection of integrated circuits

A semiconductor chip packaging on a flexible substrate is disclosed. The chip and the flexible substrate are provided with corresponding raised and indented micron-scale contact pads with the indented contact pads partially filled with a liquid amalgam. After low temperature amalgam curing, the chip and the substrate form a flexible substrate IC packaging with high conductivity, controllable interface layer thickness, micron-scale contact density and low process temperature. Adhesion between the chip and the substrate can be further enhanced by coating other areas with non-conducting adhesive.

Improved adhesive bonding composition and method of use

A method of and system for adhesive bonding. The method and system a) treat a surface of an element to be bonded to provide an adherent structure including one or more rubber compounds on the surface; b) place a polymerizable adhesive composition, including at least one photoinitiator and at least one energy converting material, in contact with the adherent structure and two or more components to be bonded to form an assembly, c) irradiated the assembly with radiation at a first wavelength, capable of conversion by the at least one energy converting material, to a second wavelength capable of activating the at least one photoinitiator to produce from the polymerizable adhesive composition a cured adhesive composition; and d) adhesively join the two or more components by way of the adherent structure and the cured adhesive composition.

Hybrid backside thermal structures for enhanced ic packages

An integrated circuit (IC) die structure comprises a substrate material comprising silicon. Integrated circuitry is over a first side of the substrate material. A composite layer is in direct contact with a second side of the substrate material. The second side is opposite the first side. The composite layer comprises a first constituent material associated with a first linear coefficient of thermal expansion (CTE), and a first thermal conductivity exceeding that of the substrate. The composite layer also comprises a second constituent material associated with a second CTE that is lower than the first, and a second thermal conductivity exceeding that of the substrate.

Dielectric and metallic nanowire bond layers

In some examples, an electronic device comprises a first component having a surface, a second component having a surface, and a bond layer positioned between the surfaces of the first and second components to couple the first and second components to each other. The bond layer includes a set of metallic nanowires and a dielectric portion. The dielectric portion comprises a polymer matrix and dielectric nanoparticles.

ADHESIVE BONDING COMPOSITION AND METHOD OF USE

A method of and system for adhesive bonding by a) providing a polymerizable adhesive composition on a surface of an element to be bonded to form an assembly; b) irradiating the assembly with radiation at a first wavelength capable of vulcanization of bonds in the polymerizable adhesive composition by activation of sulfur-containing compound with at least one selected from x-ray, e-beam, visible, or infrared light to thereby generate ultraviolet light in the polymerizable adhesive composition; and c) adhesively joining two or more components together by way of the polymerizable adhesive composition. 1: A method of adhesive bonding comprising:a) providing a polymerizable adhesive composition on a surface of an element to be bonded to form an assembly, wherein said polymerizable adhesive composition includes an organic vehicle comprising in part a monomer forming a thermoset resin;b) irradiating the assembly with radiation at a first wavelength capable of vulcanization of bonds in the polymerizable adhesive composition by activation of sulfur-containing compound with at least one-ray, e-beam, visible, or infrared light to thereby generate ultraviolet light in the polymerizable adhesive composition; andc) adhesively joining two or more components together by way of the polymerizable adhesive composition.2: The method of claim 1 , wherein irradiating comprises severing bonds in the adhesive composition to promote said vulcanization.3: The method of claim 1 , wherein irradiating comprises irradiating at least one energy converting material in the polymerizable adhesive composition.4: The method of claim 3 , wherein said at least one energy converting material is a downconverting material.5: The method of claim 4 , wherein said downconverting material comprises inorganic particulates selected from the group consisting of metal oxides; metal sulfides; doped metal oxides; and mixed metal chalcogenides.6: The method of claim 4 , wherein said downconverting material comprises ...

ADHESIVE BONDING COMPOSITION AND METHOD OF USE

A method of and system for adhesive bonding by a) providing a polymerizable adhesive composition on a surface of an element to be bonded to form an assembly; b) irradiating the assembly with radiation at a first wavelength capable of vulcanization of bonds in the polymerizable adhesive composition by activation of sulfur-containing compound with at least one selected from x-ray, e-beam, visible, or infrared light to thereby generate ultraviolet light in the polymerizable adhesive composition; and c) adhesively joining two or more components together by way of the polymerizable adhesive composition, and a curable polymer for use therein. 1. A curable polymer comprising:a polymerizable adhesive composition; andsaid polymerizable adhesive composition including a sulfur-containing compound, and capable of being cured by vulcanization of bonds in the polymerizable adhesive composition upon exposure to at least one of x-rays, e-beam, or IR flux.2. The curable polymer of claim 1 , further comprising an energy converting material comprising at least one of a downconverting material and an up converting material.3. The curable polymer of claim 2 , wherein the energy converting material comprises a downconverting material.4. The curable polymer of claim 2 , wherein the energy converting material comprises an upconverting material.5. The curable polymer of claim 1 , further comprising a primer for application to said surface of the element to be bonded.6. The curable polymer of claim 3 , wherein said downconverting material comprises inorganic particulates selected from the group consisting of: metal oxides; metal sulfides; doped metal oxides; and mixed metal chalcogenides.7. The curable polymer of claim 3 , wherein said downconverting material comprises at least one of YO claim 3 , YOS claim 3 , NaYF claim 3 , NaYbF claim 3 , YAG claim 3 , YAP claim 3 , NdO claim 3 , LaF claim 3 , LaCl claim 3 , LaO claim 3 , TiO claim 3 , LuPO claim 3 , YVO claim 3 , YbF claim 3 , YF claim 3 ...

Adhesive bonding composition and method of use

A method of and system for adhesive bonding. The method and system a) treat a surface of an element to be bonded to provide an adherent structure including one or more rubber compounds on the surface; b) place a polymerizable adhesive composition, including at least one photoinitiator and at least one energy converting material, in contact with the adherent structure and two or more components to be bonded to form an assembly, c) irradiated the assembly with radiation at a first wavelength, capable of conversion by the at least one energy converting material, to a second wavelength capable of activating the at least one photoinitiator to produce from the polymerizable adhesive composition a cured adhesive composition; and d) adhesively join the two or more components by way of the adherent structure and the cured adhesive composition.

Improved adhesive bonding composition and method of use

Improved adhesive bonding composition and method of use

A method of and system for adhesive bonding. The method and system a) treat a surface of an element to be bonded to provide an adherent structure including one or more rubber compounds on the surface; b) place a polymerizable adhesive composition, including at least one photoinitiator and at least one energy converting material, in contact with the adherent structure and two or more components to be bonded to form an assembly, c) irradiated the assembly with radiation at a first wavelength, capable of conversion by the at least one energy converting material, to a second wavelength capable of activating the at least one photoinitiator to produce from the polymerizable adhesive composition a cured adhesive composition; and d) adhesively join the two or more components by way of the adherent structure and the cured adhesive composition.

Adhesive bonding composition and method of use

A method of and system for adhesive bonding by a) providing a polymerizable adhesive composition on a surface of an element to be bonded to form an assembly; b) irradiating the assembly with radiation at a first wavelength capable of vulcanization of bonds in the polymerizable adhesive composition by activation of sulfur-containing compound with at least one selected from x-ray, e-beam, visible, or infrared light to thereby generate ultraviolet light in the polymerizable adhesive composition; and c) adhesively joining two or more components together by way of the polymerizable adhesive composition.

Semiconductor device and manufacturing method thereof

EMI 차폐층 및/또는 EMI 차폐 와이어를 갖는 반도체 장치 및 그 제조 방법이 제공된다. 예시적인 실시예에서, 반도체 장치는 반도체 다이, 반도체 다이를 차폐하는 EMI 차폐층 및 EMI 차폐층을 인캡슐레이팅하는 인캡슐레이팅 부분을 포함한다. 다른 예시적인 실시예에서, 반도체 장치는 EMI 차폐층으로부터 연장되어 반도체 다이를 차폐하는 EMI 차폐 와이어를 더 포함한다.

Semiconductor device

本发明提供一种半导体装置，其包括：半导体晶粒，包括第一表面、与所述第一表面相对的第二表面、形成在所述第一表面和所述第二表面之间的第三表面以及形成在所述第二表面上的多个互连结构；EMI屏蔽层，其包括屏蔽所述半导体晶粒的所述第一表面的第一导电层和屏蔽所述半导体晶粒的所述第三表面的第二导电层；基板，其电连接到所述半导体晶粒的所述多个互连结构；以及囊封部分，其囊封所述EMI屏蔽层和所述基板。

Dielectric and metallic nanowire bond layers

In some examples, an electronic device comprises a first component having a surface, a second component having a surface, and a bond layer positioned between the surfaces of the first and second components to couple the first and second components to each other. The bond layer includes a set of metallic nanowires and a dielectric portion. The dielectric portion comprises a polymer matrix and dielectric nanoparticles.

用于铜引线接合的纳米结构阻挡层

本发明的名称为用于铜引线接合的纳米结构阻挡层。用于铜引线接合的纳米结构阻挡层(110)包括金属晶粒(114)和在金属晶粒(114)之间的晶粒间金属(116)。纳米结构阻挡层(110)包括选自镍或钴的第一金属，和选自钨或钼的第二金属。晶粒间金属(116)中第二金属的浓度高于金属晶粒(114)中第二金属的浓度。纳米结构阻挡层(110)可以在铜芯引线(100)上以提供涂布的接合引线。纳米结构阻挡层(110)可以在接合垫上以形成涂布的接合垫。公开了使用反向脉冲电镀来电镀纳米结构阻挡层(110)的方法。公开了使用涂布的接合引线的引线接合方法。

반도체 메모리 장치의 제조방법

본 기술은 제1 얼라인 마크와 제1 구조를 포함하는 제1 기판을 가공하는 단계, 제2 얼라인 마크와 제2 구조를 포함하는 제2 기판을 가공하는 단계, 및 상기 제1 구조 및 상기 제2 구조가 서로 마주하도록 상기 제1 기판과 상기 제2 기판을 정렬하는 단계, 및 상기 제1 얼라인 마크와 상기 제2 얼라인 마크를 이용하여 상기 제1 구조와 상기 제2 구조 사이의 정렬을 제어하는 반도체 메모리 장치의 제조방법을 포함한다.

Manufacturing method of a semiconductor memory device

A method of manufacturing a semiconductor memory device includes processing a first substrate including a first align mark and a first structure, processing a second substrate including a second align mark and a second structure, orientating the first substrate and the second substrate such that the first structure and the second structure face each other, and controlling alignment between the first structure and the second structure by using the first align mark and the second align mark to couple the first structure with the second structure.

半导体存储器装置的制造方法

半导体存储器装置的制造方法。一种制造半导体存储器装置的方法包括：处理包括第一对准标记和第一结构的第一基板；处理包括第二对准标记和第二结构的第二基板；将第一基板和第二基板定向为使得第一结构和第二结构彼此面对；以及通过使用第一对准标记和第二对准标记控制第一结构和第二结构之间的对准，以将第一结构与第二结构联接。

Nanoparticle backside die adhesion layer

In described examples, a microelectronic device includes a microelectronic die with a die attach surface. The microelectronic device further includes a nanoparticle layer coupled to the die attach surface. The nanoparticle layer may be in direct contact with the die attach surface, or may be coupled to the die attach surface through an intermediate layer, such as an adhesion layer or a contact metal layer. The nanoparticle layer includes nanoparticles having adjacent nanoparticles adhered to each other. The microelectronic die is attached to a package substrate by a die attach material. The die attach material extends into the nanoparticle layer and contacts at least a portion of the nanoparticles.

半導體裝置及其製造方法

本發明提供了具有EMI屏蔽層及/或EMI屏蔽線的半導體裝置及其製造方法。在示例性實施例中，半導體裝置包括半導體晶粒、屏蔽半導體晶粒的EMI屏蔽層和囊封EMI屏蔽層的囊封部分。在另一個示例實施例中，半導體裝置還包括從EMI屏蔽層延伸且屏蔽半導體晶粒的EMI屏蔽線。

반도체 장치 및 그 제조 방법

EMI 차폐층 및/또는 EMI 차폐 와이어를 갖는 반도체 장치 및 그 제조 방법이 제공된다. 예시적인 실시예에서, 반도체 장치는 반도체 다이, 반도체 다이를 차폐하는 EMI 차폐층 및 EMI 차폐층을 인캡슐레이팅하는 인캡슐레이팅 부분을 포함한다. 다른 예시적인 실시예에서, 반도체 장치는 EMI 차폐층으로부터 연장되어 반도체 다이를 차폐하는 EMI 차폐 와이어를 더 포함한다.

Hybrid backside thermal structures for enhanced IC packages

An integrated circuit (IC) die structure comprises a substrate material comprising silicon. Integrated circuitry is over a first side of the substrate material. A composite layer is in direct contact with a second side of the substrate material. The second side is opposite the first side. The composite layer comprises a first constituent material associated with a first linear coefficient of thermal expansion (CTE), and a first thermal conductivity exceeding that of the substrate. The composite layer also comprises a second constituent material associated with a second CTE that is lower than the first, and a second thermal conductivity exceeding that of the substrate.

Manufacturing method of a semiconductor memory device

A method of manufacturing a semiconductor memory device includes processing a first substrate including a first align mark and a first structure, processing a second substrate including a second align mark and a second structure, orientating the first substrate and the second substrate such that the first structure and the second structure face each other, and controlling alignment between the first structure and the second structure by using the first align mark and the second align mark to couple the first structure with the second structure.

Halbleiteranordnung mit einem schaltbaren halbleiterelement und verfahren zur herstellung derselben

Die Erfindung betrifft eine Halbleiteranordnung (2) mit einem schaltbaren Halbleiterelement (4), welches zumindest ein Steuerkontakt (6) mit einer Steuerkontakt-Kontaktfläche (12) und zumindest einen Lastkontakt (8) mit einer Lastkontakt-Kontaktfläche (14), welche größer als die Steuerkontakt-Kontaktfläche (12) ist, aufweist. Um eine höhere Lebensdauer der Halbleiteranordnung (2) zu erreichen, wird vorgeschlagen, dass ein elektrisch isolierender Werkstoff auf einen an die Steuerkontakt-Kontaktfläche (12) angrenzenden Bereich (34) der Lastkontakt-Kontaktfläche (14) mittels eines additiven Verfahrens zur Ausbildung einer elektrisch isolierenden Schicht (26) aufgebracht ist, wobei ein metallischer Werkstoff mittels eines thermischen Spritzverfahrens auf die Steuerkontakt-Kontaktfläche (12) und die elektrisch isolierende Schicht (26) zur Ausbildung eines metallischen Steuer-Kontaktierungselements (22) mit einer Steuer-Kontaktierungselement-Kontaktfläche (24), welche größer als die Steuerkontakt-Kontaktfläche (12) ist, aufgebracht ist, wobei das Steuer-Kontaktierungselement (22) die Lastkontakt-Kontaktfläche (14) teilweise überlappt.

Manufacturing method of a semiconductor memory device

A method of manufacturing a semiconductor memory device includes processing a first substrate including a first align mark and a first structure, processing a second substrate including a second align mark and a second structure, orientating the first substrate and the second substrate such that the first structure and the second structure face each other, and controlling alignment between the first structure and the second structure by using the first align mark and the second align mark to couple the first structure with the second structure.

Manufacturing method of a semiconductor memory device

A method of manufacturing a semiconductor memory device includes processing a first substrate including a first align mark and a first structure, processing a second substrate including a second align mark and a second structure, orientating the first substrate and the second substrate such that the first structure and the second structure face each other, and controlling alignment between the first structure and the second structure by using the first align mark and the second align mark to couple the first structure with the second structure.

Manufacturing method of a semiconductor memory device

A method of manufacturing a semiconductor memory device includes processing a first substrate including a first align mark and a first structure, processing a second substrate including a second align mark and a second structure, orientating the first substrate and the second substrate such that the first structure and the second structure face each other, and controlling alignment between the first structure and the second structure by using the first align mark and the second align mark to couple the first structure with the second structure.

半导体存储器装置的制造方法

半导体存储器装置的制造方法。一种制造半导体存储器装置的方法包括：处理包括第一对准标记和第一结构的第一基板；处理包括第二对准标记和第二结构的第二基板；将第一基板和第二基板定向为使得第一结构和第二结构彼此面对；以及通过使用第一对准标记和第二对准标记控制第一结构和第二结构之间的对准，以将第一结构与第二结构联接。

Manufacturing method of a semiconductor memory device

A method of manufacturing a semiconductor memory device includes processing a first substrate including a first align mark and a first structure, processing a second substrate including a second align mark and a second structure, orientating the first substrate and the second substrate such that the first structure and the second structure face each other, and controlling alignment between the first structure and the second structure by using the first align mark and the second align mark to couple the first structure with the second structure.

Nanoparticle backside die adhesion layer

In described examples, a microelectronic device includes a microelectronic die (102) with a die attach surface (104). The microelectronic device further includes a nanoparticle layer (112) coupled to the die attach surface (104). The nanoparticle layer (112) may be in direct contact with the die attach surface (104), or may be coupled to the die attach surface (104) through an intermediate layer (110), such as an adhesion layer or a contact metal layer. The nanoparticle layer (112) includes nanoparticles (114) having adjacent nanoparticles (114) adhered to each other. The microelectronic die is attached to a package substrate (116) by a die attach material (124). The die attach material (124) extends into the nanoparticle layer (112) and contacts at least a portion of the nanoparticles (114).

Hybrid backside thermal structures for enhanced ic packages

An integrated circuit (IC) die structure comprises a substrate material comprising silicon. Integrated circuitry is over a first side of the substrate material. A composite layer is in direct contact with a second side of the substrate material. The second side is opposite the first side. The composite layer comprises a first constituent material associated with a first linear coefficient of thermal expansion (CTE), and a first thermal conductivity exceeding that of the substrate. The composite layer also comprises a second constituent material associated with a second CTE that is lower than the first, and a second thermal conductivity exceeding that of the substrate.

Halbleiteranordnung mit einem schaltbaren halbleiterelement und verfahren zur herstellung derselben

Die Erfindung betrifft eine Halbleiteranordnung (2) mit einem schaltbaren Halbleiterelement (4), welches zumindest ein Steuerkontakt (6) mit einer Steuerkontakt-Kontaktfläche (12) und zumindest einen Lastkontakt (8) mit einer Lastkontakt-Kontaktfläche (14), welche größer als die Steuerkontakt-Kontaktfläche (12) ist, aufweist. Um eine höhere Lebensdauer der Halbleiteranordnung (2) zu erreichen, wird vorgeschlagen, dass ein elektrisch isolierender Werkstoff auf einen an die Steuerkontakt-Kontaktfläche (12) angrenzenden Bereich (34) der Lastkontakt-Kontaktfläche (14) mittels eines additiven Verfahrens zur Ausbildung einer elektrisch isolierenden Schicht (26) aufgebracht ist, wobei ein metallischer Werkstoff mittels eines thermischen Spritzverfahrens auf die Steuerkontakt-Kontaktfläche (12) und die elektrisch isolierende Schicht (26) zur Ausbildung eines metallischen Steuer-Kontaktierungselements (22) mit einer Steuer-Kontaktierungselement-Kontaktfläche (24), welche größer als die Steuerkontakt-Kontaktfläche (12) ist, aufgebracht ist, wobei das Steuer-Kontaktierungselement (22) die Lastkontakt-Kontaktfläche (14) teilweise überlappt.

Improved adhesive bonding composition and method of use

半导体存储器装置的制造方法

半导体存储器装置的制造方法。一种制造半导体存储器装置的方法包括：处理包括第一对准标记和第一结构的第一基板；处理包括第二对准标记和第二结构的第二基板；将第一基板和第二基板定向为使得第一结构和第二结构彼此面对；以及通过使用第一对准标记和第二对准标记控制第一结构和第二结构之间的对准，以将第一结构与第二结构联接。

用于铜引线接合的纳米结构阻挡层

本发明的名称为用于铜引线接合的纳米结构阻挡层。用于铜引线接合的纳米结构阻挡层(110)包括金属晶粒(114)和在金属晶粒(114)之间的晶粒间金属(116)。纳米结构阻挡层(110)包括选自镍或钴的第一金属，和选自钨或钼的第二金属。晶粒间金属(116)中第二金属的浓度高于金属晶粒(114)中第二金属的浓度。纳米结构阻挡层(110)可以在铜芯引线(100)上以提供涂布的接合引线。纳米结构阻挡层(110)可以在接合垫上以形成涂布的接合垫。公开了使用反向脉冲电镀来电镀纳米结构阻挡层(110)的方法。公开了使用涂布的接合引线的引线接合方法。

Electronic devices with semiconductor die attached with sintered metallic layers, and methods of formation of such devices

An electronic device includes a semiconductor die having a lower surface, a sintered metallic layer underlying the lower surface of the semiconductor die, a conductive layer underlying the sintered metallic layer, and a conductive substrate underlying the conductive layer.

Electronic devices with semiconductor die coupled to a thermally conductive substrate

An electronic device includes a semiconductor die having a lower surface, a sintered metallic layer underlying the lower surface of the semiconductor die, a thermally conductive flow layer underlying the sintered metallic layer, and a thermally conductive substrate underlying the thermally conductive flow layer.