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Небесная энциклопедия

Космические корабли и станции, автоматические КА и методы их проектирования, бортовые комплексы управления, системы и средства жизнеобеспечения, особенности технологии производства ракетно-космических систем

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Мониторинг СМИ

Мониторинг СМИ и социальных сетей. Сканирование интернета, новостных сайтов, специализированных контентных площадок на базе мессенджеров. Гибкие настройки фильтров и первоначальных источников.

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Поддерживает ввод нескольких поисковых фраз (по одной на строку). При поиске обеспечивает поддержку морфологии русского и английского языка
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Применить Всего найдено 23496. Отображено 100.
05-01-2012 дата публикации

Method for manufacture of integrated circuit package system with protected conductive layers for pads

Номер: US20120003830A1
Автор: Haijing Cao, Qing Zhang, Yaojian Lin
Принадлежит: Individual

A method for manufacture of an integrated circuit package system includes: providing an integrated circuit die having a contact pad; forming a protection cover over the contact pad; forming a passivation layer having a first opening over the protection cover with the first opening exposing the protection cover; developing a conductive layer over the passivation layer; forming a pad opening in the protection cover for exposing the contact pad having the conductive layer partially removed; and an interconnect directly on the contact pad and only adjacent to the protection cover and the passivation layer.

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Номер записи: 1
12-01-2012 дата публикации

Wiring board and method for manufacturing the same

Номер: US20120006592A1
Автор: Makoto Terui, Shigeru Yamada, Shinji OUCHI, Yoshinori Shizuno
Принадлежит: Ibiden Co Ltd

A wiring board including a first insulation layer, a conductive pattern formed on the first insulation layer, a second insulation layer formed on the conductive pattern and the first insulation layer and having an opening portion exposing at least a portion of the conductive pattern, and a connection conductor formed in the opening portion of the second insulation layer such that the connection conductor is positioned on the portion of the conductive pattern. The connection conductor has a tip portion which protrudes from a surface of the second insulation layer and which has a tapered side surface tapering toward an end of the tip portion.

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Номер записи: 2
12-01-2012 дата публикации

Method of forming cu pillar capped by barrier layer

Номер: US20120007231A1
Автор: Wei Sen CHANG
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

A nickel barrier layer is formed on an upper sidewall surface of a Cu pillar. A mask layer with an opening for defining the Cu pillar window has an upper portion and a lower portion. The upper portion of the mask layer is removed after the formation of the Cu pillar so as to expose the upper sidewall surface of the Cu pillar. The nickel barrier layer is then deposited on the exposed sidewall surface of the Cu pillar followed by removing and the lower portion of the mask layer.

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Номер записи: 3
12-01-2012 дата публикации

Microelectronic packages with dual or multiple-etched flip-chip connectors

Номер: US20120007232A1
Автор: Belgacem Haba
Принадлежит: TESSERA RESEARCH LLC

A packaged microelectronic element includes a microelectronic element having a front surface and a plurality of first solid metal posts extending away from the front surface. A substrate has a major surface and a plurality of conductive elements exposed at the major surface and joined to the first solid metal posts. In particular examples, the conductive elements can be bond pads or can be second posts having top surfaces and edge surfaces extending at substantial angles away therefrom. Each first solid metal post includes a base region adjacent the microelectronic element and a tip region remote from the microelectronic element, the base region and tip region having respective concave circumferential surfaces. Each first solid metal post has a horizontal dimension which is a first function of vertical location in the base region and which is a second function of vertical location in the tip region.

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Номер записи: 4
12-01-2012 дата публикации

Redistribution layers for microfeature workpieces, and associated systems and methods

Номер: US20120007256A1
Автор: David Pratt
Принадлежит: Micron Technology Inc

Redistribution layers for microfeature workpieces, and associated systems and methods are disclosed. One method for processing a microfeature workpiece system includes positioning a pre-formed redistribution layer as a unit proximate to and spaced apart from a microfeature workpiece having an operable microfeature device. The method can further include attaching the redistribution layer to the microfeature workpiece and electrically coupling the redistribution layer to the operable microfeature device.

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Номер записи: 5
19-01-2012 дата публикации

Interconnections for flip-chip using lead-free solders and having reaction barrier layers

Номер: US20120012642A1
Автор: Balaram Ghosal, Da-Yuan Shih, Donna S. Zupanski-Nielsen, Henry A. Nye, III, Keith E. Fogel, Paul A. Lauro, Stephen Kilpatrick, Sung K. Kang
Принадлежит: International Business Machines Corp

An interconnection structure suitable for flip-chip attachment of microelectronic device chips to packages, comprising a two, three or four layer ball-limiting composition including an adhesion/reaction barrier layer, and having a solder wettable layer reactive with components of a tin-containing lead free solder, so that the solderable layer can be totally consumed during soldering, but a barrier layer remains after being placed in contact with the lead free solder during soldering. One or more lead-free solder balls is selectively situated on the solder wetting layer, the lead-free solder balls comprising tin as a predominant component and one or more alloying components. With a two-layer ball-limiting composition comprising an adhesion/reaction barrier layer, wherein the adhesion/reaction barrier layer serves both as an adhesion layer and a reaction barrier layer, the adhesion/reaction barrier layer can be comprised of a material selected from the group consisting of Zr and ZrN

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Номер записи: 6
19-01-2012 дата публикации

Methods of forming semiconductor chip underfill anchors

Номер: US20120012987A1
Автор: Neil McLellan, Roden R. Topacio
Принадлежит: Individual

Various semiconductor chips and methods of making the same are disclosed. In one aspect, a method of manufacturing is provided that includes forming a first opening in an insulating layer applied to a side of a semiconductor chip. The first opening does not extend through to the side. A second opening is formed in the insulating layer that exposes a portion of the side.

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Номер записи: 7
19-01-2012 дата публикации

Conductive Sidewall for Microbumps

Номер: US20120012998A1
Автор: Arvind Chandrasekaran, Christine S. Hay-Riege, Shiqun Gu
Принадлежит: Qualcomm Inc

Electromigration in microbump connections causes voids in the microbumps, which reduces the lifetime of an integrated circuit containing the microbump. Electromigration lifetime may be increased in microbumps by forming a copper shell around the solder. The copper shell of one microbump contacts the copper shell of a second microbump to enclose the solder of the microbump connection. The copper shell allows higher current densities through the microbump. Thus, smaller microbumps may be manufactured on a smaller pitch without suffering failure from electromigration. Additionally, the copper shell reduces shorting or bridging between microbump connections on a substrate.

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Номер записи: 8
02-02-2012 дата публикации

Chip having a driving integrated circuit

Номер: US20120025372A1
Автор: Pao-Yun Tang, Wei-Hao Sun
Принадлежит: Hannstar Display Corp

A chip having a bump layout suitable for the chip on glass technology and a driving IC includes a plurality of first bumps and a plurality of second bumps for electrically connecting to a glass substrate of a displayer. The first and second bumps are disposed on a surface of the chip and near two opposite long sides of the chip respectively. The ratio of the total contacting area of the first bumps to that of the second bumps is between 0.8 and 1.2. Thus, a pressure applied on the chip and the glass substrate of the displayer for connection can be uniformly exerted all over the chip, and the stability of the connection is therefore improved.

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Номер записи: 9
09-02-2012 дата публикации

Semiconductor device and method of manufacturing the same

Номер: US20120032323A1
Автор: Akihiro Osaki, Atsushi Ishii, Masahiko Fujisawa, Masahiro Matsumoto
Принадлежит: Renesas Electronics Corp

A preferred aim of the invention is to provide technique for improving reliability of semiconductor devices when using a low-dielectric-constant film having a lower dielectric constant than a silicon oxide film to a part of an interlayer insulating film. More specifically, to achieve the preferred aim, an interlayer insulating film IL 1 forming a first fine layer is formed of a middle-Young's-modulus film, and thus it is possible to separate an integrated high-Young's-modulus layer (a semiconductor substrate 1 S and a contact interlayer insulating film CIL) and an interlayer insulating film (a low-Young's-modulus film; a low-dielectric-constant film) IL 2 forming a second fine layer not to let them directly contact with each other, and stress can be diverged. As a result, film exfoliation of the interlayer insulating film IL 2 formed of a low-Young's-modulus film can be prevented and thus reliability of semiconductor devices can be improved.

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Номер записи: 10
09-02-2012 дата публикации

Semiconductor device

Номер: US20120032325A1
Автор: Osamu Miyata, Shingo Higuchi
Принадлежит: ROHM CO LTD

There is provided a semiconductor device with which stress can be prevented from locally concentrating on an external connecting terminal on a post and thus damages of the external connecting terminal can be prevented. The semiconductor device includes a semiconductor chip, a sealing resin layer stacked on a surface of the semiconductor chip, and the post which penetrates the sealing resin layer in a stacking direction of the semiconductor chip and the sealing resin layer, protrudes from the sealing resin layer, and has a periphery of the protruding portion opposedly in contact with a surface of the sealing resin layer in the stacking direction.

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Номер записи: 11
09-02-2012 дата публикации

Semiconductor Device and Power Supply Unit Utilizing the Same

Номер: US20120032713A1
Автор: Atsushi Kitagawa
Принадлежит: ROHM CO LTD

A semiconductor device has pluralities of grid array terminals forming a grid array structure, e.g. a BGA structure, in which the output end of a built-in switch circuit is connected to multiple terminals of the grid array structure, thereby reducing the current that flows through each of the multiple terminals below a permissible level and minimizing the heat due to contact resistances of the multiple terminals in contact with the IC socket of the semiconductor device. Each pair of nearest neighbors of the multiple terminals is interposed by at least one further array terminal. The multiple terminals are all located at the outermost peripheral terminal positions of the grid array structure. Thus, the heat generated in the respective multiple terminals connected to the switch circuit is reduced, thereby minimizing the possibility of hazardous melting of the terminals.

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Номер записи: 12
16-02-2012 дата публикации

Composite Electronic Circuit Assembly

Номер: US20120039004A1
Автор: Alain Artieri
Принадлежит: ST Ericsson Grenoble SAS, St Ericsson SA

A composite electronic circuit assembly comprises two MOS or CMOS circuit dice ( 100, 200 ) superimposed inside a package. Different modules of the circuit assembly are distributed between the two dice based on the digital, analog, or hybrid nature of said modules. Such a distribution makes it possible to group together the digital modules of the circuit assembly in one of the die and the analog or hybrid modules in the other die. The production cost, development time, and electrical energy consumption of the circuit assembly may thus be reduced.

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Номер записи: 13
23-02-2012 дата публикации

Mechanisms for forming copper pillar bumps using patterned anodes

Номер: US20120043654A1
Автор: Chih-Wei Lin, Chung-Shi Liu, Ming-Da Cheng, Wen-Hsiung LU
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

The mechanisms of preparing bump structures described by using patterned anodes may simplify bump-making process, reduce manufacturing cost, and improve thickness uniformity within die and across the wafer. In addition, the mechanisms described above allow forming bumps with different heights to allow bumps to be integrated with elements on a substrate with different heights. Bumps with different heights expand the application of copper post bumps to enable further chip integration.

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Номер записи: 14
01-03-2012 дата публикации

Conductive connection structure with stress reduction arrangement for a semiconductor device, and related fabrication method

Номер: US20120049343A1
Автор: Frank Kuechenmeister, Lei Fu, Michael Su, Thomas Schulze
Принадлежит: Advanced Micro Devices Inc, Globalfoundries Inc

A semiconductor device disclosed herein includes a conductive connection structure having a stepped profile that serves as a stress relief feature. The conductive connection structure includes a stress buffer arrangement for a contact pad. The stress buffer arrangement has a stepped via that terminates at the contact pad, and the stepped via has a plurality of inwardly sloped and concentric sections in a stacked orientation. The connection structure also includes underbump metallization overlying at least a portion of the contact pad and lining the stepped via, and a conductive connection element coupled to the underbump metallization. The conductive connection element fills the lined recess.

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Номер записи: 15
15-03-2012 дата публикации

Semiconductor chip with redundant thru-silicon-vias

Номер: US20120061821A1
Автор: Bryan Black, Gamal Refai-Ahmed, Joe Siegel, Michael Z. Su, Seth Prejean
Принадлежит: Advanced Micro Devices Inc, ATI TECHNOLOGIES ULC

A semiconductor chip with conductive vias and a method of manufacturing the same are disclosed. The method includes forming a first plurality of conductive vias in a layer of a first semiconductor chip. The first plurality of conductive vias includes first ends and second ends. A first conductor pad is formed in ohmic contact with the first ends of the first plurality of conductive vias.

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Номер записи: 16
15-03-2012 дата публикации

Semiconductor device having pad structure with stress buffer layer

Номер: US20120061823A1
Автор: Chao-Wen Shih, Shang-Yun Hou, Shin-puu Jeng, Tzu-Wei Chiu, Tzuan-Horng LIU, Wei-Cheng Wu
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

A semiconductor device has a pad structure with a ring-shaped stress buffer layer between a metal pad and an under-bump metallization (UBM) layer. The stress buffer layer is formed of a dielectric layer with a dielectric constant less than 3.5, a polymer layer, or an aluminum layer. The stress buffer layer is a circular ring, a square ring, an octagonal ring, or any other geometric ring.

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Номер записи: 17
15-03-2012 дата публикации

Semiconductor chip, stacked chip semiconductor package including the same, and fabricating method thereof

Номер: US20120061834A1
Автор: Tae Min Kang
Принадлежит: Hynix Semiconductor Inc

A semiconductor chip includes a silicon wafer formed with a via hole, a metal wire disposed in the via hole, and a filler that exposes a part of an upper portion of the metal wire while filing the via hole.

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Номер записи: 18
15-03-2012 дата публикации

Semiconductor chip device with polymeric filler trench

Номер: US20120061852A1
Автор: Bryan Black, Gamal Refai-Ahmed, Michael Z. Su
Принадлежит: Advanced Micro Devices Inc, ATI TECHNOLOGIES ULC

A method of manufacturing is provided that includes providing a semiconductor chip with an insulating layer. The insulating layer includes a trench. A second semiconductor chip is stacked on the first semiconductor chip to leave a gap. A polymeric filler is placed in the gap wherein a portion of the polymeric filler is drawn into the trench.

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Номер записи: 19
15-03-2012 дата публикации

Method of manufacture of integrated circuit packaging system with stacked integrated circuit

Номер: US20120064668A1
Автор: Henry Descalzo Bathan, Jairus Legaspi Pisigan, Zigmund Ramirez Camacho
Принадлежит: Individual

A method of manufacture of an integrated circuit packaging system includes: forming a base lead having an outer protrusion and an inner protrusion with a recess in between; forming a stack lead having an elongated portion; mounting a base integrated circuit over the inner protrusion or under the elongated portion; mounting the stack lead over the base lead and the base integrated circuit; connecting a stack integrated circuit and the stack lead with the stack integrated circuit over the base integrated circuit; and encapsulating at least a portion of both the base integrated circuit and the stack integrated circuit with the base lead and the stack lead exposed.

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Номер записи: 20
22-03-2012 дата публикации

Integrated circuit packaging system with stack interconnect and method of manufacture thereof

Номер: US20120068319A1
Автор: Daesik Choi, Oh Han Kim, SangMi Park
Принадлежит: Individual

A method of manufacture of an integrated circuit packaging system includes: forming a connection carrier having base device pads and base interconnect pads on a carrier top side of the connection carrier; connecting a base integrated circuit to the base device pads and mounted over the carrier top side; mounting base vertical interconnects directly on the base interconnect pads; attaching a base package substrate to the base integrated circuit and directly on the base vertical interconnects; forming a base encapsulation on the base package substrate, the base device pads, and the base interconnect pads; and removing a portion of the connection carrier with the base device pads and the base interconnect pads partially exposed opposite the base package substrate.

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Номер записи: 21
22-03-2012 дата публикации

Integrated circuit packaging system with active surface heat removal and method of manufacture thereof

Номер: US20120068328A1
Автор: Hin Hwa Goh, KANG Chen, Rui Huang, Xusheng Bao, Yung Kuan Hsiao
Принадлежит: Individual

A method of manufacture of an integrated circuit packaging system includes: providing an interconnect structure having a structure bottom side, a structure top side, and a cavity, the structure bottom side electrically connected to the structure top side; mounting an integrated circuit entirely within the cavity, the integrated circuit having an active side coplanar with the structure top side; forming an encapsulation partially covering the interconnect structure and the integrated circuit, the encapsulation having an encapsulation top side coplanar with the structure top side and the active side; forming a top re-passivation layer over the structure top side and the encapsulation; and mounting a heat sink over the top re-passivation layer for removing heat from the active side.

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Номер записи: 22
22-03-2012 дата публикации

Microsprings Partially Embedded In A Laminate Structure And Methods For Producing Same

Номер: US20120068331A1
Автор: Eric Peeters, Eugene M. Chow
Принадлежит: Palo Alto Research Center Inc

At least one microspring has applied thereover a laminate structure to provide: mechanical protection during handling and wafer processing, a spring spacer layer, strengthening of the anchor between spring and substrate, provision of a gap stop during spring deflection, and moisture and contaminant protection. A fully-formed laminate structure may be applied over the microspring structure or a partly-formed laminate structure may be applied over the microspring structure then cured or hardened. The tip portion of the microspring may protrude through the laminate structure and be exposed for contact or may be buried within the contact structure. The laminate structure may remain in place in the final microspring structure or be removed in whole or in part. The laminate structure may be photolithographically patternable material, patterned and etched to remove some or all of the structure, forming for example additional structural elements such as a gap stop for the microspring.

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Номер записи: 23
22-03-2012 дата публикации

Semiconductor device and manufacturing method thereof

Номер: US20120068334A1
Автор: Hirokazu Ezawa, Soichi Yamashita, Tatsuo Migita
Принадлежит: Toshiba Corp

Semiconductor devices of embodiments include a plurality of solder bumps electrically connected on a plurality of electrode pads disposed on a semiconductor substrate in parallel at a pitch of 40 μm or less via under bump metals. The ratio of the diameter (the top diameter) of the portion of each solder bump most away from the semiconductor substrate and the diameter (the bottom diameter) of the bottom side of each solder bump is 1:1 to 1:4.

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Номер записи: 24
22-03-2012 дата публикации

Semiconductor device and method of manufacturing the same

Номер: US20120069530A1
Автор: Kazushige Kanda, Satoshi Inoue, Yuui Shimizu
Принадлежит: Toshiba Corp

According to one embodiment, a semiconductor device includes a stacked chip includes semiconductor chips which are stacked, the semiconductor chips comprises semiconductor substrates and through electrodes formed in the semiconductor substrates, respectively, the through electrodes being electrically connected, and deactivating circuits provided in the semiconductor chips, respectively, and configured to deactivate a failed semiconductor chip.

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Номер записи: 25
29-03-2012 дата публикации

Methods of fabricating package stack structure and method of mounting package stack structure on system board

Номер: US20120074586A1
Автор: Eun-Jin Choi, Sun-Kyoung SEO
Принадлежит: SAMSUNG ELECTRONICS CO LTD

A package stack structure includes a lower semiconductor chip on a lower package substrate having a plurality of lower via plug lands, a lower package having a lower molding compound surrounding a portion of a top surface of the lower package substrate and side surfaces of the lower semiconductor chip, an upper semiconductor chip on an upper package substrate having a plurality of upper via plug lands, an upper package having an upper molding compound covering the upper semiconductor chip, via plugs vertically penetrating the lower molding compound, the via plugs connecting the lower and upper via plug lands, respectively, and a fastening element and an air space between a top surface of the lower molding compound and a bottom surface of the upper package substrate.

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Номер записи: 26
12-04-2012 дата публикации

Chip stacked structure

Номер: US20120086119A1
Автор: Ming-Che Wu
Принадлежит: Universal Global Scientific Industrial Co Ltd, Universal Scientific Industrial Shanghai Co Ltd

A chip stacked structure is provided. The chip stacked structure includes a first die and a second die stacked on the first die. The first die has a plurality of connection structures each which has a through hole, a connection pad and a solder bump. The connection pad has a terminal connected to the through hole. The solder bump is disposed on the connection pad and located around the through hole. The second die has a plurality of through holes which are aligned and bonded to the solder bump respectively. The chip stacked structure may simplify the process and improve the process yield rate.

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Номер записи: 27
12-04-2012 дата публикации

Semiconductor assembly and semiconductor package including a solder channel

Номер: US20120086123A1
Автор: Jeong-Woo Park, Moon-Gi Cho, Sun-Hee Park, Ui-Hyoung Lee
Принадлежит: SAMSUNG ELECTRONICS CO LTD

Semiconductor packages connecting a semiconductor chip to an external device by bumps are provided. The semiconductor packages may include a connection pad on a semiconductor chip, a connecting bump on and configured to be electrically connected to the connection pad and a supporting bump on the semiconductor chip and configured to be electrically isolated from the connection pad. The connection bump may include a first pillar and a first solder ball and the supporting bump may include a second pillar and a second solder ball. The semiconductor packages may further include a solder channel in the second pillar configured to allow a portion of the second solder ball to extend into the solder channel along a predetermined direction.

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Номер записи: 28
19-04-2012 дата публикации

Semiconductor device, method for forming the same, and data processing system

Номер: US20120091520A1
Автор: Nobuyuki Nakamura
Принадлежит: Elpida Memory Inc

A semiconductor device includes a semiconductor substrate, a first interlayer insulating film over the semiconductor substrate, a first interconnect over the first interlayer insulating film, and a via plug penetrating the semiconductor substrate and the first interlayer insulating film. The via plug is coupled to the first interconnect.

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Номер записи: 29
19-04-2012 дата публикации

Microelectronic assemblies having compliancy and methods therefor

Номер: US20120091582A1
Автор: Belgacem Haba, David Ovrutsky, Guilian Gao, Vage Oganesian
Принадлежит: Tessera LLC

A microelectronic assembly is disclosed that includes a semiconductor wafer with contacts, compliant bumps of dielectric material overlying the first surface of the semiconductor wafer, and a dielectric layer overlying the first surface of the semiconductor wafer and edges of the compliant bumps. The compliant bumps have planar top surfaces which are accessible through the dielectric layer. Conductive traces may be electrically connected with contacts and extend therefrom to overlie the planar top surfaces of the compliant bumps. Conductive elements may overlie the planar top surfaces in contact with the conductive traces.

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Номер записи: 30
19-04-2012 дата публикации

Pass-through 3d interconnect for microelectronic dies and associated systems and methods

Номер: US20120094443A1
Автор: David S. Pratt, Dewali Ray, Kyle K. Kirby
Принадлежит: Micron Technology Inc

Pass-through 3D interconnects and microelectronic dies and systems of stacked dies that include such interconnects are disclosed herein. In one embodiment, a system of stacked dies includes a first microelectronic die having a substrate, a metal substrate pad, and a first integrated circuit electrically coupled to the substrate pad. A pass-through 3D interconnect extends between front and back sides of the substrate, including through the substrate pad. The pass-through interconnect is electrically isolated from the substrate pad and electrically coupled to a second integrated circuit of a second microelectronic die attached to the back side of the substrate. In another embodiment, the first integrated circuit is a first memory device and the second integrated circuit is a second memory device, and the system uses the pass-through interconnect as part of an independent communication path to the second memory device.

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Номер записи: 31
26-04-2012 дата публикации

Conductive feature for semiconductor substrate and method of manufacture

Номер: US20120098121A1
Автор: Hsien-Wei Chen, Ying-Ju Chen
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

A conductive feature on a semiconductor component is disclosed. A first passivation layer is formed over a substrate. A bond pad is formed over the first passivation layer. A second passivation layer overlies the first passivation layer and the bond pad. The second passivation layer has a first opening overlying the bond pad and a plurality of second openings exposing a top surface of the first passivation layer. A buffer layer overlies the second passivation layer and fills the plurality of second openings. The buffer layer has a third opening overlapping the first opening and together exposes a portion the bond pad. The combined first opening and third opening has sidewalls. An under bump metallurgy (UBM) layer overlies the sidewalls of the combined first opening and third opening, and contacts the exposed portion of the bond pad. A conductive feature overlies the UBM layer.

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Номер записи: 32
03-05-2012 дата публикации

Chip-on-chip structure and manufacturing method therof

Номер: US20120104597A1
Автор: Junji Yoshikawa, Tatsuji Ishiduka, Tsutomu Kojima
Принадлежит: Toshiba Corp

According to an embodiment, a chip-on-chip structure includes a first chip, a second chip, the first chip and the second chip being opposite to each other, a first electrode terminal, a second electrode terminal, a bump and a protecting material. The first electrode terminal is provided on the surface of the first chip at the side of the second chip. The second electrode terminal is provided on the surface of the second chip at the side of the first chip. The bump electrically connects the first electrode terminal and the second electrode terminal. The protecting material is formed around the bump between the first chip and the second chip. The protecting material includes a layer made of a material having heat-sensitive adhesive property.

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Номер записи: 33
10-05-2012 дата публикации

Method for manufacturing a semiconductor device having a refractory metal containing film

Номер: US20120115324A1
Автор: Mari Watanabe, Toshiyuki Takewaki
Принадлежит: Renesas Electronics Corp

A semiconductor device and a method for manufacturing the same of the present invention in which the semiconductor device is provided with a fuse structure or an electrode pad structure, suppress the copper blowing-out from a copper containing metal film. The semiconductor device comprises a silicon substrate, SiO 2 film provided on the silicon substrate, copper films embedded in the SiO 2 film, TiN films covering an upper face of a boundary region between an upper face of copper films and the copper films, and the SiO 2 film, and SiON films covering an upper face of the TiN films.

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Номер записи: 34
24-05-2012 дата публикации

Package carrier

Номер: US20120125669A1
Автор: Chau-Jie Zhan, Jing-Yao Chang, Tao-Chih Chang, Tsung-Fu Tsai
Принадлежит: Industrial Technology Research Institute ITRI

A package carrier including a substrate, at least an under bump metallurgic (UBM) layer and at least a conductive bump is provided. The substrate has a conductive structure and at least a pad connected with the conductive structure. A region of the pad connected with the conductive structure is a signal source region. The UBM layer is disposed on the pad and includes a first conductive pattern and a second conductive pattern. A side wall of the second conductive pattern is directly connected to a side wall of the first conductive pattern, and the second conductive pattern is disposed close to the signal source region. The conductivity of the second conductive pattern is smaller than the conductivity of the first conductive pattern. The conductive bump is disposed on the UBM layer.

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Номер записи: 35
24-05-2012 дата публикации

Method of manufacturing semiconductor device

Номер: US20120129335A1
Автор: Hiroyuki Yoda, Masamitsu Ikumo, Yoshito Akutagawa
Принадлежит: Fujitsu Semiconductor Ltd

A method of manufacturing a semiconductor device including the following steps: forming an insulator layer over a first conductor over a semiconductor substrate; forming a barrier layer to coat the surface of the insulator layer; forming a second conductor over the barrier layer; melting the second conductor in an atmosphere containing either hydrogen or carboxylic acid in a condition that the surface of the insulator layer over the first conductor is coated with the barrier layer; and removing the barrier layer partially from the surface of the insulator layer with the second conductor as a mask.

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Номер записи: 36
24-05-2012 дата публикации

Structures and methods for improving solder bump connections in semiconductor devices

Номер: US20120129336A1
Автор: Anthony K. Stamper, Daniel C. Edelstein, Felix P. Anderson, Thomas L. McDevitt, William Cote
Принадлежит: International Business Machines Corp

Structures with improved solder bump connections and methods of fabricating such structures are provided herein. The structure includes a trench formed in a dielectric layer which has at least a portion thereof devoid of a fluorine boundary layer. The structure further includes a copper wire in the trench having at least a bottom portion thereof in contact with the non-fluoride boundary layer of the trench. A lead free solder bump is in electrical contact with the copper wire.

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Номер записи: 37
31-05-2012 дата публикации

Tsv substrate structure and the stacked assembly thereof

Номер: US20120133030A1
Автор: Cha-Hsin Lin, Chung-Chih Wang, Pei-Jer Tzeng, Tzu-Kun Ku
Принадлежит: Industrial Technology Research Institute ITRI

The disclosure provides a TSV substrate structure and the stacked assembly of a plurality of the substrate structures, the TSV substrate structure including: a substrate comprising a first surface, a corresponding second surface, and a TSV communicating the first surface with the second surface through the substrate; and a conductor unit completely filling the TSV, the conductor unit comprising a conductor body which has a first and a second ends corresponding to the first and second surfaces of the substrate, respectively.

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Номер записи: 38
31-05-2012 дата публикации

Semiconductor device

Номер: US20120133058A1
Автор: Kunihiro Komiya
Принадлежит: ROHM CO LTD

The semiconductor device has the CSP structure, and includes: a plurality of electrode pads formed on a semiconductor integrated circuit in order to input/output signals from/to exterior; solder bumps for making external lead electrodes; and rewiring. The solder bumps are arranged in two rows along the periphery of the semiconductor device. The electrode pads are arranged inside the outermost solder bumps so as to be interposed between the two rows of solder bumps. Each trace of the rewiring is extended from an electrode pad, and is connected to any one of the outermost solder bumps or any one of the inner solder bumps.

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Номер записи: 39
31-05-2012 дата публикации

Mechanisms for resistivity measurement of bump structures

Номер: US20120133379A1
Автор: Feynmann CHU, Jeff Wang, Mill-Jer Wang, Pi-Huang Lee, You-Hua Chou
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

The embodiments described above provide mechanisms for bump resistivity measurement. By using designated bumps on one or more corners of dies, the resistivity of bumps may be measured without damaging devices and without a customized probing card. In addition, bump resistivity may be collected across the entire wafer. The collected resistivity data may be used to monitor the stability and/or health of processes used to form bumps and their underlying layers.

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Номер записи: 40
31-05-2012 дата публикации

Semiconductor Structures and Method for Fabricating the Same

Номер: US20120135201A1
Автор: Ching-Hung Ko, Mu-Jia Liu, Tsung-Chieh Chang
Принадлежит: Himax Technologies Ltd

A semiconductor structure is provided. The semiconductor structure includes a first substrate, a second substrate opposite to the first substrate, a plurality of spacers disposed between the first substrate and the second substrate, and an adhesive material bonded with the first substrate and the second substrate within the two adjacent spacers. The invention also provides a method for fabricating the semiconductor structure.

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Номер записи: 41
14-06-2012 дата публикации

Bonding pad structure and integrated circuit comprising a plurality of bonding pad structures

Номер: US20120146215A1
Автор: Chih-Hung Lu, Yu-Ju Yang
Принадлежит: ILI Techonology Corp

A bonding pad structure positioned on an integrated circuit includes a connecting pad, an insulation layer and a gold bump. The connecting pad is formed on the integrated circuit. The insulation layer is formed on the connecting pad, where the insulation layer has only one opening and a shape of the opening includes at least a bend. The gold bump is formed on the insulation layer, where the gold bump is electrically connected to the connecting pad through the opening of the insulation layer.

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Номер записи: 42
14-06-2012 дата публикации

Semiconductor Device and Method of Manufacture Thereof

Номер: US20120146231A1
Автор: Ludwig Heitzer, Thorsten Meyer
Принадлежит: INFINEON TECHNOLOGIES AG

A semiconductor device and a method of making a semiconductor device are disclosed. The semiconductor device comprises a redistribution layer arranged over a chip, the redistribution layer comprising a first redistribution line. The semiconductor further comprises an isolation layer disposed over the redistribution layer, the isolation layer having a first opening forming a first pad area and a first interconnect located in the first opening and in contact with the first redistribution line. The redistribution line in the first pad area is arranged orthogonal to a first direction to a neutral point of the semiconductor device.

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Номер записи: 43
14-06-2012 дата публикации

Method for Manufacturing Heat Dissipation Bulk of Semiconductor Device

Номер: US20120149138A1
Автор: Chun-Liang Lin, Kuan-Chun Chen, Yan-Kuin Su
Принадлежит: National Cheng Kung University NCKU

A method for manufacturing a heat dissipation bulk of a semiconductor device including the following steps is described. An electrically conductive layer is formed to cover a surface of a temporary substrate. At least one semiconductor chip is connected to the electrically conductive layer by at least one metal bump, wherein the at least one metal bump is located between the at least one semiconductor chip and the electrically conductive layer. A metal substrate is formed on the electrically conductive layer, wherein the metal substrate fills up a gap between the at least one semiconductor chip and the electrically conductive layer. The temporary substrate is removed.

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Номер записи: 44
21-06-2012 дата публикации

Tsv for 3d packaging of semiconductor device and fabrication method thereof

Номер: US20120153496A1
Автор: Chang-woo Lee, Jae-hak Lee, Joon-Yub Song, Tae-Ho Ha
Принадлежит: Korea Institute of Machinery and Materials KIMM

The present invention relates to a through silicon via (TSV) for 3D packaging to integrate a semiconductor device and a method for manufacturing the same, and more particularly, to a through silicon via (TSV) for 3D packaging of a semiconductor device that is capable of improving production efficiency, having very high electric conductivity, and minimizing electrical signal delay, without using a carrier wafer by self-aligning substrates in a low temperature state and sequentially bonding a plurality of semiconductor dies (or semiconductor chips), and a method of manufacturing the same.

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Номер записи: 45
21-06-2012 дата публикации

Semiconductor chip assembly and method for making same

Номер: US20120155055A1
Автор: Belgacem Haba, Hiroaki Sato, Ilyas Mohammed, Kiyoaki Hashimoto, Norihito Masuda, Philip Damberg, Teck-Gyu Kang, Wei-Shun Wang, Yoshikuni Nakadaira
Принадлежит: Tessera LLC

A microelectronic assembly may include a substrate including a rigid dielectric layer having electrically conductive elements, a microelectronic element having a plurality of contacts exposed at a face thereof, and conductive vias extending through a compliant dielectric layer overlying the rigid dielectric layer. The vias electrically connect the substrate contacts respectively to the conductive elements, and the substrate contacts are joined respectively to the contacts of the microelectronic element. The vias, compliant layer and substrate contacts are adapted to appreciably relieve stress at the substrate contacts associated with differential thermal contact and expansion of the assembly.

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Номер записи: 46
05-07-2012 дата публикации

Low cost thermally enhanced hybrid bga and method of manufacturing the same

Номер: US20120168929A1
Автор: Kim-yong Goh
Принадлежит: STMICROELECTRONICS PTE LTD

A semiconductor package is formed having a substrate juxtaposed on at least two sides of a semiconductor die. Both the substrate and the semiconductor die are affixed to a conductive layer that draws heat generated during use of the semiconductor package away from the semiconductor die and the substrate. There are also electrical contacts affixed to the substrate and the semiconductor die. The electrical contacts facilitate electrical connection between the semiconductor die, the substrate, and any external devices or components making use of the semiconductor die. The substrate, semiconductor die, and at least a portion of some of the electrical contacts are enclosed by an encapsulating layer insulating the components. Portions of the electrical contacts not enclosed by the encapsulating layer are affixed to an outside device, such as a printed circuit board.

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Номер записи: 47
12-07-2012 дата публикации

Test Contact System For Testing Integrated Circuits With Packages Having An Array Of Signal and Power Contacts

Номер: US20120176151A1
Автор: Brian K. Warwick, Jeffrey C. Sherry, Patrick J. Alladio, Russell F. Oberg
Принадлежит: Johnstech International Corp

A test fixture ( 120 ) is disclosed for electrically testing a device under test ( 130 ) by forming a plurality of temporary mechanical and electrical connections between terminals ( 131 ) on the device under test ( 130 ) and contact pads ( 161 ) on the load board ( 160 ). The test fixture ( 120 ) has a replaceable membrane ( 150 ) that includes vias ( 151 ), with each via ( 151 ) being associated with a terminal ( 131 ) on the device under test ( 130 ) and a contact pad ( 161 ) on the load board ( 160 ). In some cases, each via ( 151 ) has an electrically conducting wall for conducting current between the terminal ( 131 ) and the contact pad ( 161 ). In some cases, each via ( 151 ) includes a spring ( 152 ) that provides a mechanical resisting force to the terminal ( 131 ) when the device under test ( 130 ) is engaged with the test fixture ( 120 ).

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Номер записи: 48
19-07-2012 дата публикации

Packaging substrate with conductive structure

Номер: US20120181688A1
Автор: Shih-Ping Hsu
Принадлежит: Individual

A packaging substrate with conductive structure is provided, including a substrate body having at least one conductive pad on a surface thereof, a stress buffer metal layer disposed on the conductive pad and a thickness of the stress buffer metal layer being 1-20 μm, a solder resist layer disposed on the substrate body and having at least one opening therein for correspondingly exposing a portion of top surface of the stress buffer metal layer, a metal post disposed on a central portion of the surface of the stress buffer metal layer, and a solder bump covering the surfaces of the metal post. Therefore, a highly reliable conductive structure is provided, by using the stress buffer metal layer to release thermal stresses, and using the metal post and the solder bump to increase the height of the conductive structure.

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Номер записи: 49
19-07-2012 дата публикации

Semiconductor Device and Method of Forming Bond Wires and Stud Bumps in Recessed Region of Peripheral Area around the Device for Electrical Interconnection to Other Devices

Номер: US20120181689A1
Автор: Byung Tai Do, Linda Pei Ee CHUA, Reza A. Pagaila
Принадлежит: Stats Chippac Pte Ltd

A semiconductor wafer contains a plurality of semiconductor die each having a peripheral area around the die. A recessed region with angled or vertical sidewall is formed in the peripheral area. A conductive layer is formed in the recessed region. A first stud bump is formed over a contact pad of the semiconductor die. A second stud bump is formed over the first conductive layer within the recessed region. A bond wire is formed between the first and second stud bumps. A third stud bump is formed over the bond wire and first stud bump. A dicing channel partially formed through the peripheral area. The semiconductor wafer undergoes backgrinding to the dicing channel to singulate the semiconductor wafer and separate the semiconductor die. The semiconductor die can be disposed in a semiconductor package with other components and electrically interconnected through the bond wire and stud bumps.

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Номер записи: 50
26-07-2012 дата публикации

Structures for improving current carrying capability of interconnects and methods of fabricating the same

Номер: US20120187558A1
Автор: Charles L. Arvin, Harry D. Cox, Krystyna W. Semkow, Raschid J. Bezama, Timothy D. Sullivan, Timothy H. Daubenspeck
Принадлежит: International Business Machines Corp

Interconnect structures and methods of fabricating the same are provided. The interconnect structures provide highly reliable copper interconnect structures for improving current carrying capabilities (e.g., current spreading). The structure includes an under bump metallurgy formed in a trench. The under bump metallurgy includes at least: an adhesion layer; a plated barrier layer; and a plated conductive metal layer provided between the adhesion layer and the plated barrier layer. The structure further includes a solder bump formed on the under bump metallurgy.

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Номер записи: 51
26-07-2012 дата публикации

Direct Edge Connection for Multi-Chip Integrated Circuits

Номер: US20120187577A1
Автор: James L. Speidell, John U. Knickerbocker, Matthew J. Farinelli, Peter A. Gruber, Sherif A. Goma, Steven A. Cordes
Принадлежит: International Business Machines Corp

The present invention allows for direct chip-to-chip connections using the shortest possible signal path.

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Номер записи: 52
02-08-2012 дата публикации

Semiconductor device and method of fabricating the same

Номер: US20120193779A1
Автор: Chung-Sun Lee, Hyun-jung SONG, Jung-Hwan Kim, Sun-pil Youn, Tae-Hong Min
Принадлежит: SAMSUNG ELECTRONICS CO LTD

A stack of semiconductor chips, a semiconductor device, and a method of manufacturing are disclosed. The stack of semiconductor chips may comprise a first chip of the stack, a second chip of the stack over the first chip, conductive bumps, a homogeneous integral underfill material, and a molding material. The conductive bumps may extend between an upper surface of the first chip and a lower surface of the second chip. The homogeneous integral underfill material may be interposed between the first chip and the second chip, encapsulate the conductive bumps, and extend along sidewalls of the second chip. The homogeneous integral underfill material may have an upper surface extending in a direction parallel to an upper surface of the second chip and located adjacent the upper surface of the second chip. The molding material may be on outer side surfaces of the homogeneous integral underfill material above the upper surface of the first chip, wherein, in view of a first cross sectional profile, the molding material is separated from sidewalls of the second chip by the homogeneous integral underfill material such that the molding material does not contact sidewalls of the second chip.

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Номер записи: 53
02-08-2012 дата публикации

Customized rf mems capacitor array using redistribution layer

Номер: US20120193781A1
Автор: Jonathan Hale Hammond, Julio Costa, Thomas Scott Morris
Принадлежит: RF Micro Devices Inc

Disclosed is a method for fabricating a customized micro-electromechanical systems (MEMS) integrated circuit using at least one redistribution layer. The method includes steps of providing a substrate on which MEMS components are fabricated and coupling predetermined ones of the MEMS components via the redistribution traces.

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Номер записи: 54
02-08-2012 дата публикации

Solder, soldering method, and semiconductor device

Номер: US20120193800A1
Автор: Keisuke Uenishi, Nobuhiro Imaizumi, Seiki Sakuyama, Tetsuhiro Nakanishi, Toshiya Akamatsu
Принадлежит: Fujitsu Ltd

A solder includes Sn (tin), Bi (bismuth) and Zn (zinc), wherein the solder has a Zn content of 0.01% by weight to 0.1% by weight.

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Номер записи: 55
02-08-2012 дата публикации

Ohmic connection using widened connection zones in a portable electronic object

Номер: US20120193804A1
Автор: Yannick Grasset
Принадлежит: RFIDEAL

The invention relates to portable electronic objects comprising an integrated circuit chip, and a mounting having two connection terminals for a circuit, as well as to a method for manufacturing such objects. The invention is characterized in that the chip is provided, on the active surface thereof, with two widened connection zones, in particular connection plates, said connection plates being positioned opposite said terminals and electrically connected, by ohmic contact, to the latter, and in that the surface defined by the connection plates, at the surface of the active integrated circuit having said plates, is greater than ½ of the surface of said surface. The invention can be used, in particular, for RFID objects.

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Номер записи: 56
02-08-2012 дата публикации

Chip package structure

Номер: US20120196438A1
Автор: Sung-Chuan MA, Tse-Ming CHU
Принадлежит: Individual

The formation of the conductive wire of a chip package consists of a plurality of steps. Coat a first dielectric layer on the pad-mounting surface and a slot is formed on each bonding pad correspondingly. Then coat a second dielectric layer and produce a wiring slot corresponding to each bonding pad and the slot thereof. Next each wiring slot is filled with electrically conductive metal so as to form a conductive wire. Later Coat a third dielectric layer and a corresponding slot is formed on one end of each conductive wire while this slot is filled with electrically conductive metal to form a solder point. The above steps can further be repeated so as to form an upper-layer and a lower-layer conductive wire. Thereby precision of the chip package, use efficiency of the wafer and yield rate of manufacturing processes are all improved.

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Номер записи: 57
09-08-2012 дата публикации

Semiconductor device and method of fabricating the semiconductor device

Номер: US20120199981A1
Автор: Ho-geon Song, Jae-hyun PHEE, Ju-Il Choi, Se-young Jeong
Принадлежит: SAMSUNG ELECTRONICS CO LTD

A semiconductor device includes a first device including a first substrate and a first external connection terminal for connecting outside the first device; a second device stacked on the first device, the second device including a second substrate and a second external connection terminal for connecting outside the second device; an adhesive pattern disposed between the first device and second device, the adhesive pattern disposed in locations other than locations where the first external connection terminal and second external connection terminal are disposed, and the adhesive pattern causing the first device and second device, when stacked, to be spaced apart by a predetermined distance; and a plated layer disposed between and electrically and physically connecting the first external connection terminal and the second external connection terminal.

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Номер записи: 58
16-08-2012 дата публикации

Semiconductor Device and Method of Forming Narrow Interconnect Sites on Substrate with Elongated Mask Openings

Номер: US20120208326A9
Автор: Rajendra D. Pendse
Принадлежит: Stats Chippac Pte Ltd

A semiconductor device has a semiconductor die with a plurality of bumps formed over a surface of the semiconductor die. A plurality of conductive traces is formed over a surface of the substrate with interconnect sites. A masking layer is formed over the surface of the substrate. The masking layer has a plurality of parallel elongated openings each exposing at least two of the conductive traces and permitting a flow of bump material along a length of the plurality of conductive traces within the plurality of elongated openings while preventing the flow of bump material past a boundary of the plurality of elongated openings. One of the conductive traces passes beneath at least two of the elongated openings. The bumps are bonded to the interconnect sites so that the bumps cover a top surface and side surface of the interconnect sites. An encapsulant is deposited around the bumps between the semiconductor die and substrate.

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Номер записи: 59
23-08-2012 дата публикации

Device mounting board and method of manufacturing the same, semiconductor module, and mobile device

Номер: US20120211269A1
Автор: Kouichi Saitou, Toshiya Shimizu
Принадлежит: Sanyo Electric Co Ltd

A device mounting board includes: an insulating resin layer; a wiring layer formed on one of the principal surfaces of the insulating resin layer; a protection layer covering the insulating resin layer and the wiring layer; a protruding electrode electrically connected to the wiring layer, the protruding electrode protruding from the wiring layer toward the insulating resin layer and penetrating through the insulating resin layer; a wiring-layer-side convex portion protruding from the wiring layer toward the insulating resin layer and having the top end thereof located inside the insulating resin layer; and a resin-layer-side convex portion protruding from the protection layer toward the insulating resin layer and having the top end thereof located inside the insulating resin layer.

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Номер записи: 60
23-08-2012 дата публикации

Electroconductive bonding material, method for bonding conductor, and method for manufacturing semiconductor device

Номер: US20120211549A1
Автор: Kuniko Ishikawa, Masayuki Kitajima, Takashi Kubota, Takatoyo Yamakami
Принадлежит: Fujitsu Ltd

An electro-conductive bonding material includes: metal components of a high-melting-point metal particle that have a first melting point or higher; a middle-melting-point metal particle that has a second melting point which is first temperature or higher, and second temperature or lower, the second temperature is lower than the first melting point and higher than the first temperature; and a low-melting-point metal particle that has a third melting point or lower, the third melting point is lower than the first temperature.

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Номер записи: 61
23-08-2012 дата публикации

Chip package with plank stack of semiconductor dies

Номер: US20120211878A1
Автор: Bruce M. Guenin, Darko R. Popovic, David C. Douglas, Ivan Shubin, Jing Shi, John A. Harada, Matthew D. Giere, Theresa Y. Sze
Принадлежит: Oracle International Corp

In a chip package, semiconductor dies in a vertical stack of semiconductor dies or chips (which is referred to as a ‘plank stack’) are separated by a mechanical spacer (such as a filler material or an adhesive). Moreover, the chip package includes a substrate at a right angle to the plank stack, which is electrically coupled to the semiconductor dies along an edge of the plank stack. In particular, electrical pads proximate to a surface of the substrate (which are along a stacking direction of the plank stack) are electrically coupled to pads that are proximate to edges of the semiconductor dies by an intervening conductive material, such as: solder, stud bumps, plated traces, wire bonds, spring connectors, a conductive adhesive and/or an anisotropic conducting film. Note that the chip package may facilitate high-bandwidth communication of signals between the semiconductor dies and the substrate.

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Номер записи: 62
30-08-2012 дата публикации

Bonded Semiconductor Structure With Pyramid-Shaped Alignment Openings and Projections

Номер: US20120217610A1
Автор: Luu Nguyen, Peter J. Hopper, Peter Johnson, Peter Smeys
Принадлежит: National Semiconductor Corp

A bonded semiconductor structure is formed in a method that first forms a female semiconductor structure with pyramid-shaped openings and a male semiconductor structure with pyramid-shaped projections, and then inserts the projections into the openings to align the male semiconductor structure to the female semiconductor structure for bonding.

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Номер записи: 63
30-08-2012 дата публикации

Semiconductor Device and Method of Forming Bond Wires Between Semiconductor Die Contact Pads and Conductive TOV in Peripheral Area Around Semiconductor Die

Номер: US20120217643A1
Автор: Byung Tai Do, Dioscoro A. Merilo, Reza A. Pagaila
Принадлежит: Stats Chippac Pte Ltd

A semiconductor wafer has a plurality of semiconductor die with contact pads. An organic material is deposited in a peripheral region around the semiconductor die. A portion of the organic material is removed to form a plurality of vias. A conductive material is deposited in the vias to form conductive TOV. The conductive TOV can be recessed with respect to a surface of the semiconductor die. Bond wires are formed between the contact pads and conductive TOV. The bond wires can be bridged in multiple sections across the semiconductor die between the conductive TOV and contact pads. An insulating layer is formed over the bond wires and semiconductor die. The semiconductor wafer is singulated through the conductive TOV or organic material between the conductive TOV to separate the semiconductor die. A plurality of semiconductor die can be stacked and electrically connected through the bond wires and conductive TOV.

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Номер записи: 64
30-08-2012 дата публикации

Semiconductor devices and methods of manufacturing semiconductor devices

Номер: US20120217652A1
Автор: David S. Pratt
Принадлежит: Micron Technology Inc

Semiconductor devices and methods of manufacturing semiconductor devices. One example of a method of fabricating a semiconductor device comprises forming a conductive feature extending through a semiconductor substrate such that the conductive feature has a first end and a second end opposite the first end, and wherein the second end projects outwardly from a surface of the substrate. The method can further include forming a dielectric layer over the surface of the substrate and the second end of the conductive feature such that the dielectric layer has an original thickness. The method can also include removing a portion of the dielectric layer to an intermediate depth less than the original thickness such that at least a portion of the second end of the conductive feature is exposed.

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Номер записи: 65
30-08-2012 дата публикации

Semiconductor device and noise suppressing method

Номер: US20120217653A1
Автор: Hisashi Ishida, Koichi Takemura
Принадлежит: NEC Corp

A first semiconductor chip ( 200 ) is mounted on a second semiconductor chip ( 100 ). The first semiconductor chip ( 200 ) has a first conductor pattern ( 222 ). The second semiconductor chip ( 100 ) has a second conductor pattern ( 122 ). The second conductor pattern ( 122 ) is formed at a region overlapping the first conductor pattern ( 222 ) in a plan view. At least one element selected from a group consisting of the first conductor pattern ( 222 ) and the second conductor pattern ( 122 ) has a repetitive structure.

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Номер записи: 66
30-08-2012 дата публикации

Vertical ballast technology for power hbt device

Номер: US20120218047A1
Автор: Julio Costa, Michael Carroll
Принадлежит: RF Micro Devices Inc

Power amplification devices are disclosed having a vertical ballast configuration to prevent thermal runaway in at least one stack of bipolar transistors formed on a semiconductor substrate. To provide a negative feedback to prevent thermal runaway in the bipolar transistors, a conductive layer is formed over and coupled to the stack. A resistivity of the conductive layer provides an effective resistance that prevents thermal runaway in the bipolar transistors. The vertical placement of the conductive layer allows for vertical heat dissipation and thus provides ballasting without concentrating heat.

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Номер записи: 67
06-09-2012 дата публикации

Etching liquid for etching silicon substrate rear surface in through silicon via process and method for manufacturing semiconductor chip having through silicon via using the etching liquid

Номер: US20120225563A1
Автор: Ryuji Sotoaka, Yoshiko Fujioto
Принадлежит: Mitsubishi Gas Chemical Co Inc

Disclosed are an etching liquid which is used for etching a silicon substrate rear surface in a through silicon via process, etches only a silicon substrate without etching a connecting plug composed of a metal such as copper, tungsten, etc., or polysilicon or the like, and has an excellent etching rate; and a method for manufacturing a semiconductor chip having a through silicon via using the same. The etching liquid is an etching liquid for etching a silicon substrate rear surface in a through silicon via process containing potassium hydroxide, hydroxylamine, and water; and the method for manufacturing a semiconductor chip includes a silicon substrate rear surface etching step using the etching liquid.

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Номер записи: 68
13-09-2012 дата публикации

Semiconductor device and manufacturing method of the same

Номер: US20120228762A1
Автор: Hiroshi Watabe, Masatoshi Fukuda
Принадлежит: Toshiba Corp

A semiconductor device, includes: a wiring substrate, a stacked body mounted on the wiring substrate, an underfill layer filled into gaps between respective semiconductor chips of the stacked body; and a molding body made up of a molding resin covered and formed at outside of the stacked body and so on. The underfill layer is made up of a cured product of a resin material containing an amine-based curing agent, and the cured product has a Tg of 65° C. or more and 100° C. or less.

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Номер записи: 69
27-09-2012 дата публикации

Apparatuses and methods to enhance passivation and ild reliability

Номер: US20120241952A1
Автор: Bob Sankman, Richard J. Harries, Sudarashan V. Rangaraj
Принадлежит: Individual

Some embodiments of the present invention include apparatuses and methods relating to processing and packaging microelectronic devices that reduce stresses on and limit or eliminate crack propagation in the devices.

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Номер записи: 70
11-10-2012 дата публикации

Solder ball contact susceptible to lower stress

Номер: US20120256313A1
Автор: Luc Guerin, Mario J. Interrante, Michael J. Shapiro, Thuy Tran-Quinn, Van T. Truong
Принадлежит: International Business Machines Corp

A solder ball contact and a method of making a solder ball contact includes: a first insulating layer with a via formed on an integrated circuit (IC) chip and a metal pad; an under bump metallurgy (UBM) structure disposed within the via and on a portion of the first insulating layer, surrounding the via; a second insulating layer formed on an upper surface of an outer portion of the UBM structure that is centered on the via; and a solder ball that fills the via and is disposed above an upper surface of an inner portion of the UBM structure that contacts the via, in which the UBM structure that underlies the solder ball is of a greater diameter than the solder ball.

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Номер записи: 71
18-10-2012 дата публикации

Wafer Level Packaging of Electronic Devices

Номер: US20120261697A1
Автор: Israel Petronius, Mordehai MARGALIT
Принадлежит: VIAGAN Ltd

Aspects of the invention include an electronic device comprising a first contact point; a metal pad disposed to provide electrical connection to the first contact point; a substrate comprising a first face and a second face opposing the first face of the substrate, the first face of the substrate adjacent a face of the electronic device; and a VIA passing through the substrate from the second face of the substrate to the metal pad, the VIA exhibiting: a pass through extending through the substrate from the first face to the second face; a metal layer disposed within the pass through arranged to provide electrical connectivity to the metal pad from an area adjacent the second face of the substrate; and an electrically insulating first passivation layer disposed between the metal layer and the substrate arranged to provide electrical insulation between the substrate and the metal layer.

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Номер записи: 72
18-10-2012 дата публикации

Test structure and methodology for three-dimensional semiconductor structures

Номер: US20120262197A1
Автор: Christopher M. Durham, Donald L. Wheater, Jerome L. Cann, Kerry Bernstein, Paul D. Kartschoke, Peter J. Klim
Принадлежит: International Business Machines Corp

A plurality of peripheral test structure substrate (PTSS) through vias is formed within a peripheral test structure substrate. A peripheral test structure layer and at least one functional layer are formed on one side of the plurality of the PTSS through vias. The other side of the plurality of the PTSS through vias is exposed throughout fabrication of the peripheral test structure layer and the at least one functional layer to provide access points for testing functionality of the various layers throughout the manufacturing sequence. C4 bonding may be performed after manufacture of all of the at least one functional layer is completed. A 3D assembly carrier or a C4 carrier substrate is not required since the peripheral test structure substrate has sufficient mechanical strength to support the peripheral test structure layer and the at least one functional layer.

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Номер записи: 73
25-10-2012 дата публикации

Sensor mounted in flip-chip technology on a substrate

Номер: US20120267731A1
Автор: Felix Mayer, Franziska Brem, Markus Graf, Werner Hunziker
Принадлежит: Individual

The sensor assembly comprises a substrate ( 1 ), such as a flexible printed circuit board, and a sensor chip ( 2 ) flip-chip mounted to the substrate ( 1 ), with a first side ( 3 ) of the sensor chip ( 2 ) facing the substrate ( 1 ). A sensing area ( 4 ) and contact pads ( 5 ) are integrated on the first side ( 3 ) of the sensor chip ( 2 ) and located in a chamber ( 17 ) between the substrate ( 1 ) and the sensor chip ( 2 ). Chamber ( 17 ) is bordered along at least two sides by a dam ( 16 ). Underfill ( 18 ) and/or solder flux is arranged between the sensor chip ( 2 ) and the substrate ( 1 ), and the dam ( 16 ) prevents the underfill from entering the chamber ( 17 ). An opening ( 19 ) extends from the chamber to the environment and is located between the substrate ( 1 ) and the sensor chip ( 2 ) or extends through the sensor chip ( 2 ).

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Номер записи: 74
01-11-2012 дата публикации

Semiconductor Device and Method of Making a Semiconductor Device

Номер: US20120273935A1
Автор: Beng Keh See, Chin Wei Ronnie Tan, Horst Theuss, Kathleen Ong, Kian Pin Queck, Stefan Martens, Tze Yang Hin, Ulrich Krumbein
Принадлежит: INFINEON TECHNOLOGIES AG

A semiconductor device and a method of manufacturing a semiconductor device are disclosed. An embodiment comprises forming a bump on a die, the bump having a solder top, melting the solder top by pressing the solder top directly on a contact pad of a support substrate, and forming a contact between the die and the support substrate.

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Номер записи: 75
01-11-2012 дата публикации

Method for manufacturing semiconductor device

Номер: US20120276736A1
Автор: Naoki Idani
Принадлежит: Fujitsu Semiconductor Ltd

An oxide film is formed on an inner surface of a via hole in which a through electrode is to be formed, and thereafter a Cu film is embedded in the via hole. When an excess Cu film formed on a first interlayer insulating film is removed by a CMP method, the oxide film is also polished and reduced in thickness. Using the oxide film reduced in thickness as a hard mask, a wiring trench is formed in the first interlayer insulating film. At this time, the oxide film is further reduced in thickness. After a conductive material is embedded in the wiring trench, an excess conductive material is removed by polishing. At this time, the remaining oxide film is removed entirely by the polishing.

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Номер записи: 76
08-11-2012 дата публикации

Electrode arrays and methods of fabricating the same using printing plates to arrange particles in an array

Номер: US20120282771A1
Автор: Heiko Wolf, Laurent Malaquin, Tobias Kraus
Принадлежит: International Business Machines Corp

Electrode arrays and methods of fabricating the same using a printing plate to arrange conductive particles in alignment with an array of electrodes are provided. In one embodiment, a semiconductor device comprises: a semiconductor topography comprising an array of electrodes disposed upon a semiconductor substrate; a dielectric layer residing upon the semiconductor topography; and at least one conductive particle disposed in or on the dielectric layer in alignment with at least one of the array of electrodes.

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Номер записи: 77
15-11-2012 дата публикации

Semiconductor device

Номер: US20120286426A1
Автор: Ki Young Kim
Принадлежит: Hynix Semiconductor Inc

A semiconductor device includes a first structural body having first electrode pads; a second structural body disposed in a face-up type over the first structural body in such a way as to expose the first electrode pads, and having first connection members with at least two protrusions; and a third structural body disposed in a face-down type over the second structural body, and having second connection members with at least two protrusions, on a surface thereof facing the second structural body, wherein some of the protrusions of the second connection members are electrically connected with the exposed first electrode pads, and at least one of remaining protrusions of the second connection members is electrically connected with the first connection members.

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Номер записи: 78
22-11-2012 дата публикации

Microelectronic devices having conductive through via electrodes insulated by gap regions

Номер: US20120292782A1
Автор: Byung Lyul Park, Gilheyun CHOI, Ho-Jin Lee, Hyunsoo Chung, SeYoung JEONG
Принадлежит: SAMSUNG ELECTRONICS CO LTD

A microelectronic device includes a substrate having a trench extending therethrough between an active surface thereof and an inactive surface thereof opposite the active surface, a conductive via electrode extending through the substrate between sidewalls of the trench, and an insulating layer extending along the inactive surface of the substrate outside the trench and extending at least partially into the trench. The insulating layer defines a gap region in the trench that separates the substrate and the via electrode. Related devices and methods of fabrication are also discussed.

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Номер записи: 79
29-11-2012 дата публикации

Stacked wafer level package having a reduced size

Номер: US20120299169A1
Автор: Jong Hoon Kim, Min Suk Suh, Seung Hyun Lee, Seung Taek Yang, Tae Min Kang
Принадлежит: SK hynix Inc

A stacked wafer level package includes a first semiconductor chip having a first bonding pad and a second semiconductor chip having a second bonding pad. Both bonding pads of the semiconductor chips face the same direction. The second semiconductor chip is disposed in parallel to the first semiconductor chip. A third semiconductor chip is disposed over the first and second semiconductor chips acting as a supporting substrate. The third semiconductor chip has a third bonding pad that is exposed between the first and the second semiconductor chips upon attachment. Finally, a redistribution structure is electrically connected to the first, second, and third bonding pads.

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Номер записи: 80
29-11-2012 дата публикации

Pad structure, circuit carrier and integrated circuit chip

Номер: US20120299192A1
Автор: Yeh-Chi Hsu, Yu-Kai Chen
Принадлежит: Via Technologies Inc

A pad structure is suitable for a circuit carrier or an integrated circuit chip. The pad structure includes an inner pad, a conductive via and an outer pad. The conductive via connects the inner pad. The outer pad connects the conductive via and further connects a conductive ball or a conductive bump. The outer diameter of the outer pad is greater than the outer diameter of the inner pad.

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Номер записи: 81
13-12-2012 дата публикации

Semiconductor device structures

Номер: US20120313248A1
Автор: Mark E. Tuttle
Принадлежит: Micron Technology Inc

The present invention relates to methods for forming through-wafer interconnects in semiconductor substrates and the resulting structures. In one embodiment, a method for forming a through-wafer interconnect includes providing a substrate having a pad on a surface thereof, depositing a passivation layer over the pad and the surface of the substrate, and forming an aperture through the passivation layer and the pad using a substantially continuous process. An insulative layer is deposited in the aperture followed by a conductive layer and a conductive fill. In another embodiment of the invention, a semiconductor device is formed including a first interconnect structure that extends through a conductive pad and is electrically coupled with the conductive pad while a second interconnect structure is formed through another conductive pad while being electrically isolated therefrom. Semiconductor devices and assemblies produced with the methods are also disclosed.

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Номер записи: 82
13-12-2012 дата публикации

Layered chip package and method of manufacturing same

Номер: US20120313260A1
Автор: Atsushi Iijima, Hiroshi Ikejima, Hiroyuki Ito, Yoshitaka Sasaki
Принадлежит: Headway Technologies Inc, SAE Magnetics HK Ltd

A layered chip package includes a main body and wiring. The main body includes: a main part having a top surface and a bottom surface and including three or more layer portions stacked on one another; a plurality of first terminals disposed on the top surface of the main part; and a plurality of second terminals disposed on the bottom surface of the main part. Each layer portion includes a semiconductor chip having first and second surfaces, and a plurality of electrodes electrically connected to the wiring. The plurality of electrodes are disposed on a side of the first surface of the semiconductor chip. A first layer portion located closest to the top surface of the main part and a second layer portion located closest to the bottom surface of the main part are arranged so that the second surfaces of their respective semiconductor chips face toward each other. The plurality of first terminals are formed by using the plurality of electrodes of the first layer portion. The plurality of second terminals are formed by using the plurality of electrodes of the second layer portion.

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Номер записи: 83
20-12-2012 дата публикации

Metal Bump Formation

Номер: US20120322255A1
Автор: Chih-Wei Lin, Chung-Shi Liu, Hsiu-Jen Lin, Ming-Da Cheng, Tzong-Hann Yang, Wen-Hsiung LU, Yi-Wen WU, Zheng-Yi Lim
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

A system and method for forming metal bumps is provided. An embodiment comprises attaching conductive material to a carrier medium and then contacting the conductive material to conductive regions of a substrate. Portions of the conductive material are then bonded to the conductive regions using a bonding process to form conductive caps on the conductive regions, and residual conductive material and the carrier medium are removed. A reflow process is used to reflow the conductive caps into conductive bumps.

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Номер записи: 84
27-12-2012 дата публикации

Through wafer vias and method of making same

Номер: US20120329219A1
Автор: Alvin Jose Joseph, Anthony Kendall Stamper, Hanyi Ding
Принадлежит: International Business Machines Corp

A method of forming and structure for through wafer vias and signal transmission lines formed of through wafer vias. The method of forming through wafer vias includes forming an array of through wafer vias comprising at least one electrically conductive through wafer via and at least one electrically non-conductive through wafer via through a semiconductor substrate having a top surface and an opposite bottom surface, each through wafer via of the array of through wafer vias extending from the top surface of the substrate to the bottom surface of the substrate.

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Номер записи: 85
03-01-2013 дата публикации

Method of manufacturing semiconductor device

Номер: US20130001274A1
Автор: Jumpei Konno, Kazunori Hasegawa, Michiaki Sugiyama, Nobuhiro Kinoshita, Takafumi Nishita
Принадлежит: Renesas Electronics Corp

To improve reliability of a semiconductor device, in a flip-chip bonding step, a solder material that is attached to a tip end surface of a projecting electrode in advance and a solder material that is applied in advance over a terminal (bonding lead) are heated and thereby integrated and electrically connected to each other. The terminal includes a wide part (a first portion) with a first width W 1 and a narrow part (a second portion) with a second width W 2. When the solder material is heated, the thickness of the solder material arranged over the narrow part becomes smaller than the thickness of the solder material arranged in the wide part. Then, in the flip-chip bonding step, a projecting electrode is arranged over the narrow part and bonded onto the narrow part. Thus, the amount of protrusion of the solder material can be reduced.

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Номер записи: 86
03-01-2013 дата публикации

Bump-on-trace (bot) structures

Номер: US20130001778A1
Автор: Han-Ping Pu, Tin-Hao Kuo, Yu-feng Chen, Yuh Chern Shieh
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

A bump-on-trace (BOT) structure is described. The BOT structure includes a first work piece with a metal trace on a surface of the first work piece, wherein the metal trace has a first axis. The BOT structure further includes a second work piece with an elongated metal bump, wherein the elongated metal bump has a second axis, wherein the second axis is at a non-zero angle from the first axis. The BOT structure further includes a metal bump, wherein the metal bump electrically connects the metal trace and the elongated metal bump. A package having a BOT structure and a method of forming the BOT structure are also described.

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Номер записи: 87
10-01-2013 дата публикации

Semiconductor chip and flip-chip package comprising the same

Номер: US20130009286A1
Автор: Hwan-Sik Lim, Jong-ho Lee, Moon-Gi Cho, Sun-Hee Park, Young-Lyong KIM
Принадлежит: SAMSUNG ELECTRONICS CO LTD

A semiconductor chip includes stress-relief to mitigate the effects of differences in coefficients of thermal expansion (CTE) between a printed circuit board (PCB) and a semiconductor chip and a flip-chip package including the semiconductor chip. The semiconductor chip includes a stress-relief buffer coupling a bump and a semiconductor chip pad.

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Номер записи: 88
17-01-2013 дата публикации

Semiconductor Device with Solder Bump Formed on High Topography Plated Cu Pads

Номер: US20130015575A1
Автор: Haijing Cao, Qing Zhang, Yaojian Lin
Принадлежит: Stats Chippac Pte Ltd

A semiconductor device has a first conductive layer formed over a substrate. A first insulating layer is formed over the substrate and first conductive layer. A second conductive layer is formed over the first conductive layer and first insulating layer. A second insulating layer is formed over the first insulating layer and second conductive layer. The second insulating layer has a sidewall between a surface of the second insulating material and surface of the second conductive layer. A protective layer is formed over the second insulating layer and surface of the second conductive layer. The protective layer follows a contour of the surface and sidewall of the second insulating layer and second conductive layer. A bump is formed over the surface of the second conductive layer and a portion of the protective layer adjacent to the second insulating layer. The protective layer protects the second insulating layer.

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Номер записи: 89
17-01-2013 дата публикации

Solder Bump with Inner Core Pillar in Semiconductor Package

Номер: US20130015576A1
Автор: Yaojian Lin
Принадлежит: Stats Chippac Pte Ltd

A flip chip semiconductor package has a substrate with a plurality of active devices. A contact pad is formed on the substrate in electrical contact with the plurality of active devices. A passivation layer, second barrier layer, and adhesion layer are formed between the substrate and an intermediate conductive layer. The intermediate conductive layer is in electrical contact with the contact pad. A copper inner core pillar is formed by plating over the intermediate conductive layer. The inner core pillar has a rectangular, cylindrical, toroidal, or hollow cylinder form factor. A solder bump is formed around the inner core pillar by plating solder material and reflowing the solder material to form the solder bump. A first barrier layer and wetting layer are formed between the inner core pillar and solder bump. The solder bump is in electrical contact with the intermediate conductive layer.

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Номер записи: 90
17-01-2013 дата публикации

Interconnection and assembly of three-dimensional chip packages

Номер: US20130015578A1
Автор: Ashok V. Krishnamoorthy, Hiren D. Thacker, Ivan Shubin, John E. Cunningham
Принадлежит: Oracle International Corp

In a chip package, semiconductor dies in a vertical stack of semiconductor dies or chips (which is referred to as a ‘plank stack’) are aligned by positive features that are mechanically coupled to negative features recessed below the surfaces of adjacent semiconductor dies. Moreover, the chip package includes an interposer plate at approximately a right angle to the plank stack, which is electrically coupled to the semiconductor dies along an edge of the plank stack. In particular, electrical pads proximate to a surface of the interposer plate (which are along a stacking direction of the plank stack) are electrically coupled to pads that are proximate to edges of the semiconductor dies by an intervening conductive material, such as solder balls or spring connectors. Note that the chip package may facilitate high-bandwidth communication of signals between the semiconductor dies and the interposer plate.

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Номер записи: 91
31-01-2013 дата публикации

Semiconductor device, semiconductor device unit, and semiconductor device production method

Номер: US20130026629A1
Автор: Sumiaki Nakano
Принадлежит: Panasonic Corp

An example of a semiconductor device according to the present invention includes: a protective film ( 1 ) which has an opening to expose a part of the surface of an electrode pad ( 4 ) and covers the surface of the electrode pad ( 4 ) excluding the opening; and a bump ( 6 ) which is electrically connected with the electrode pad ( 4 ) through the opening of the protective film ( 1 ) and has a part exposed outside within the area of the electrode pad ( 4 ), wherein probe marks ( 7 ) are formed by a probe brought into contact with the electrode pad ( 4 ) for electrical characteristic inspection, and the probe marks ( 7 ) are positioned within a region where the protective film ( 1 ) is formed and are covered by the protective film ( 1 ).

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Номер записи: 92
31-01-2013 дата публикации

Integrated circuit package including a direct connect pad, a blind via, and a bond pad electrically coupled to the direct connect pad

Номер: US20130026642A1
Автор: Kenneth Robert Rhyner, Peter R. Harper
Принадлежит: Texas Instruments Inc

An integrated circuit package including a semiconductor die and a flexible circuit (flex circuit), and a method for forming the integrated circuit package. The flex circuit can include a direct connect pad which is not electrically coupled to an active trace, a blind via electrically coupled to the direct connect pad, and a semiconductor die having a bond pad which is electrically coupled to the direct connect pad using a conductor. The bond pad, the conductor, the direct connect pad, and the blind via can all be vertically aligned, each with the other.

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Номер записи: 93
31-01-2013 дата публикации

TCE Compensation for Package Substrates for Reduced Die Warpage Assembly

Номер: US20130029457A1
Автор: Margaret Simmons-Matthews
Принадлежит: Texas Instruments Inc

A method for assembling die packages includes attaching contacts on a first side of a plurality of first die to substrate pads on a top surface of a composite carrier. The composite carrier includes a package substrate including at least one embedded metal layer having its bottom surface secured to a semiconductor wafer. The composite carrier minimizes effects of the CTE mismatch between the die and the package substrate during assembly reduces warpage of the die. After the attaching, the semiconductor wafer is removed from the package substrate. Electrically conductive connectors are attached to the bottom surface of the package substrate, and the package substrate is sawed to form a plurality of singulated die packages.

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Номер записи: 94
31-01-2013 дата публикации

Method of manufacturing semiconductor device

Номер: US20130029475A1
Автор: Takeo Tsukamoto
Принадлежит: Elpida Memory Inc

A method of manufacturing a semiconductor device comprises: forming a protective film so as to cover at least a side edge of a substrate; forming a trench, which is annular in shape when viewed oppositely to a first principal surface of the substrate, on the first principal surface by etching using a photoresist pattern; and forming an insulating film so as to fill the trench, to form an insulating ring.

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Номер записи: 95
07-02-2013 дата публикации

Integrated Inductor

Номер: US20130032923A1
Автор: Chen-Shien Chen, Ching-Wen Hsiao, Mirng-Ji Lii, Tsung-Ding Wang, Yen-Liang Lin
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

A system and method for providing an integrated inductor with a high Quality factor (Q) is provided. An embodiment comprises a magnetic core that is in a center of a conductive spiral. The magnetic core increases the inductance of the integrated inductor to allow the inductor to be used in applications such as a RF choke. The magnetic core may be formed in the same manner and time as an underbump metallization.

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Номер записи: 96
14-02-2013 дата публикации

Through Silicon Via Layout

Номер: US20130040453A1
Автор: Chen-Shien Chen, Ming-Fa Chen
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

A system and method for forming under bump metallization layers that reduces the overall footprint of UBMs, through silicon vias, and trace lines is disclosed. A preferred embodiment comprises forming an under bump metallization layer over a plurality of through silicon vias, whereas the UBM is connected to only a portion of the total number of through silicon vias over which it is located. The trace lines connected to the through silicon vias may additionally be formed beneath the UBM to save even more space on the surface of the die.

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Номер записи: 97
21-02-2013 дата публикации

Package-on-package structures

Номер: US20130043587A1
Автор: Huahung Kao, Shiann-Ming Liou
Принадлежит: MARVELL WORLD TRADE LTD

Embodiments of the present disclosure provide a package on package arrangement comprising a bottom package and a second package. The first package includes a substrate layer including (i) a top side and (ii) a bottom side that is opposite to the top side. Further, the top side defines a substantially flat surface. The first package also includes a die coupled to the bottom side of the substrate layer. The second package includes a plurality of rows of solder balls, and the second package is attached to the substantially flat surface of the substrate layer via the plurality of rows of solder balls.

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Номер записи: 98
21-02-2013 дата публикации

Dram repair architecture for wide i/o dram based 2.5d/3d system chips

Номер: US20130044554A1
Автор: Sandeep Kumar Goel, Tze-Chiang HUANG
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

A 2.5D or 3D repair architecture includes a logic die, and a memory die. In the 2.5D architecture, the logic die and memory die are mounted on an interposer. In the 3D architecture, the memory die is mounted on the logic die. The logic has a control logic wrapped with a processor wrapper. The processor wrapper enables testing components of the control logic. The control logic further comprises a wide input/output controller, a built-in-repair analyzer (BIRA), and a repair controller. A method utilizing the repair architecture provides for repairing failed columns and rows of a memory device.

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Номер записи: 99
28-02-2013 дата публикации

Semiconductor Device and Method of Manufacturing a Semiconductor Device Including Grinding Steps

Номер: US20130049205A1
Автор: David O'Sullivan, Klaus Reingruber, Thorsten Meyer
Принадлежит: Intel Mobile Communications GmbH

A method of manufacturing a device includes providing a semiconductor chip having a first face and a second face opposite to the first face with a contact pad arranged on the first face. The semiconductor chip is placed on a carrier with the first face facing the carrier. The semiconductor chip is encapsulated with an encapsulation material. The carrier is removed and the semiconductor material is removed from the second face of the first semiconductor chip without removing encapsulation material at the same time.

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Номер записи: 100