Solder-coated ball and method for manufacturing same

Stacking semiconductor devices, particularly memory chips

High density packaging of semiconductor devices on an interconnection substrate is achieved by stacking bare semiconductor devices atop one another so that an edge portion of a semiconductor device extends beyond the semiconductor device that it is stacked atop. Elongate interconnection elements extend from the bottommost one of the semiconductor devices, and from the exposed edge portions of the semiconductor devices stacked atop the bottommost semiconductor device. Free-ends of the elongate interconnection elements make electrical contact with terminals of an interconnection substrate, such as a PCB. The elongate interconnection elements extending from each of the semiconductor devices are sized so as to reach the terminals of the PCB, which may be plated through holes. The elongate interconnection elements are suitably resilient contact structures, and may be composite interconnection elements comprising a relatively soft core (e.g., a gold wire) and a relatively hard overcoat (e.g., ...

Flip chip assembly and process with sintering material on metal bumps

A method is disclosed of fabricating a microelectronic package comprising a substrate overlying the front face of a microelectronic element. A plurality of metal bumps project from conductive elements of the substrate towards the microelectronic element, the metal bumps having first ends extending from the conductive elements, second ends remote from the conductive elements, and lateral surfaces extending between the first and second ends. The metal bumps can be wire bonds having first and second ends attached to a same conductive pad of the substrate. A conductive matrix material contacts at least portions of the lateral surfaces of respective ones of the metal bumps and joins the metal bumps with contacts of the microelectronic element.

ELECTROCONDUCTIVE BONDING MATERIAL, METHOD FOR BONDING CONDUCTOR, AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE

An electro-conductive bonding material includes: metal components of a high-melting-point metal particle that have a first melting point or higher; a middle-melting-point metal particle that has a second melting point which is first temperature or higher, and second temperature or lower, the second temperature is lower than the first melting point and higher than the first temperature; and a low-melting-point metal particle that has a third melting point or lower, the third melting point is lower than the first temperature.

Stacked semiconductor devices, particularly memory chips

Electroconductive bonding material comprising three types of metal particles with different melting points and its use for bonding an electronic component to a substrate

An electro-conductive bonding material (20,30) includes: high-melting-point metal particles with a component having a first melting point, middle-melting-point metal particles having a second melting point, lower than the first melting point, low-melting-point metal particles having a third melting point, lower than the second melting point and preferably a flux. The high-melting-point metal particles include Au, Ag, Cu, Au-plated Cu, Sn-Bi-plated Cu and Ag-plated Cu particles. The middle-melting-point metal particles include Sn-Bi and Sn-Bi-Ag particles. The low-melting-point metal particles include Sn-Bi-ln and Sn-Bi-Ga particles. The electro-conductive bonding material (20,30) is used for bonding a substrate (6) and an electronic component (8). A method for bonding comprises supplying the electro-conductive bonding material (e.g. by paste printing) to any one of an electrode (7) of a substrate (6) and a terminal of an electronic component (8) (e.g. an Au bump (9)), heating the supplied ...

SOLDER-COATED BALL AND METHOD FOR MANUFACTURING SAME

Visibility event navigation method and system

A method of visibility event navigation includes receiving, via processing circuitry of a client device, a first visibility event packet from a server, the first visibility event packet including information representing 3D surface elements of an environmental model that are occluded from a first viewcell and not occluded from a second viewcell, the first and second viewcells representing spatial regions of a specified navigational route within a real environment modeled by the environmental model. The method also includes acquiring, surface information representing the visible surfaces of the real environment at a sensor and determining, a position in the real environment by matching the surface information to the visibility event packet information. The method further includes transmitting, the position from the client device to the server and receiving a second visibility event packet from the server if the at least one position is within the specified navigational route.

Semiconductor device and method of forming bump structure with insulating buffer layer to reduce stress on semiconductor wafer

A semiconductor wafer has a plurality of semiconductor die with contact pads for electrical interconnect. An insulating layer is formed over the semiconductor wafer. A bump structure is formed over the contact pads. The bump structure has a buffer layer formed over the insulating layer and contact pad. A portion of the buffer layer is removed to expose the contact pad and an outer portion of the insulating layer. A UBM layer is formed over the buffer layer and contact pad. The UBM layer follows a contour of the buffer layer and contact pad. A ring-shaped conductive pillar is formed over the UBM layer using a patterned photoresist layer filled with electrically conductive material. A conductive barrier layer is formed over the ring-shaped conductive pillar. A bump is formed over the conductive barrier layer. The buffer layer reduces thermal and mechanical stress on the bump and contact pad.

SEMICONDUCTOR PACKAGE

Disclosed is a semiconductor package including a package substrate, a semiconductor chip mounted on the package substrate, a connection solder pattern between the package substrate and the semiconductor chip, and a dummy bump between the package substrate and the semiconductor chip and spaced apart from the connection solder pattern. The connection solder pattern includes a first intermetallic compound layer, a connection solder layer, and a second intermetallic compound layer. The dummy bump includes a dummy pillar and a dummy solder pattern. A thickness of the dummy solder pattern is less than a thickness of the connection solder pattern. A melting point of the dummy solder pattern is greater than that of the connection solder layer.

Multi-chip package and manufacturing method thereof

A multi-chip package and a manufacturing method thereof are provided. The multi-chip package includes: an interposer including a wiring structure and an interposer via electrically connected to the wiring structure; a plurality of semiconductor chips located on a first surface of the interposer and electrically connected to each other through the interposer; an encapsulant located on the first surface of the interposer and encapsulating at least a portion of the plurality of semiconductor chips; and a redistribution circuit structure located on a second surface of the interposer opposite to the first surface, wherein the plurality of semiconductor chips are electrically connected to the redistribution circuit structure through at least the interposer.

Method for forming metal bumps

A method for forming metal bumps is disclosed. The steps of the method include supplying a substrate containing a plurality of pads; forming a first photoresist layer on the substrate, herein the first photoresist layer covers the pads; performing a planarization step to remove a portion of the first photoresist layer so as to expose the pads; forming a conductive layer on the first photoresist layer and the pads; electroplating a metal layer on the conductive layer; forming a patterned second photoresist layer on the metal layer; a portion of the metal layer and the conductive layer which are not covered by the patterned second photoresist layer is removed by using the patterned second photoresist layer as a mask; removing the patterned second photoresist layer; and forming a solder mask on the substrate, herein the solder mask has a plurality of openings to expose the metal layer located on the pads.

PRE-PACKAGE AND METHODS OF MANUFACTURING SEMICONDUCTOR PACKAGE AND ELECTRONIC DEVICE USING THE SAME

Methods of fabricating semiconductor packages are provided. One of the methods includes forming a protection layer including metal on a first surface of a substrate to cover a semiconductor device disposed on the first surface of the substrate, attaching a support substrate to the protection layer by using an adhesive member, processing a second surface of the substrate opposite to the protection layer to remove a part of the substrate, and detaching the support substrate from the substrate.

MECHANISMS FOR FORMING POST-PASSIVATION INTERCONNECT STRUCTURE

Embodiments of mechanisms for forming a semiconductor device are provided. The semiconductor device includes a contact pad over a substrate. The semiconductor device also includes a passivation layer over the substrate and a first portion of the contact pad, and a second portion of the contact pad is exposed through an opening. The semiconductor device further includes a post-passivation interconnect layer over the passivation layer and coupled to the second portion of the contact pad. In addition, the semiconductor device includes a bump over the post-passivation interconnect layer and outside of the opening. The semiconductor device also includes a diffusion barrier layer physically insulating the bump from the post-passivation interconnect layer while electrically connecting the bump to the post-passivation interconnect layer.

EXPANDED HEAD PILLAR FOR BUMP BONDS

A microelectronic device has a bump bond structure including an electrically conductive pillar with an expanded head, and solder on the expanded head. The electrically conductive pillar includes a column extending from an I/O pad to the expanded head. The expanded head extends laterally past the column on at least one side of the electrically conductive pillar. In one aspect, the expanded head may have a rounded side profile with a radius approximately equal to a thickness of the expanded head, and a flat top surface. In another aspect, the expanded head may extend past the column by different lateral distances in different lateral directions. In a further aspect, the expanded head may have two connection areas for making electrical connections to two separate nodes. Methods for forming the microelectronic device are disclosed.

SEMICONDUCTOR DEVICE ASSEMBLY INTERCONNECTION PILLARS AND ASSOCIATED METHODS

In some embodiments, an interconnection structure can electrically and physically couple a first semiconductor die and a second semiconductor die. The interconnection structure can include a first portion at the first semiconductor die and a second portion at the second semiconductor die. The first portion can include a first conductive pillar with a concave bonding surface, a first annular barrier layer, and a first annular solder layer. The first annular barrier layer can surround a sidewall of the first conductive pillar, and the first annular solder layer can surround the first barrier layer. The second portion can include a second conductive pillar having a convex bonding surface, the convex bonding surface coupled to the concave bonding surface. The second interconnection structure can further include a second annular solder layer surrounding a second annular barrier layer surrounding the second conductive pillar.

Spring element electrical contact and methods

CONDUCTIVE CONNECTING MEMBER AND MANUFACTURING METHOD OF SAME

A conductive connecting member formed on a bonded face of an electrode terminal of a semiconductor or an electrode terminal of a circuit board, the conductive connecting member comprising a porous body formed in such manner that a conductive paste containing metal fine particles (P) having mean primary particle diameter from 10 to 500 nm and an organic solvent (S), or a conductive paste containing the metal fine particles (P) and an organic dispersion medium (D) comprising the organic solvent (S) and an organic binder (R) is heating-treated so as for the metal fine particles (P) to be bonded, the porous body being formed by bonded metal fine particles (P) having mean primary particle diameter from 10 to 500 nm, a porosity thereof being from 5 to 35 volume%, and mean pore diameter being from 1 to 200 nm.

SOLDER-COATED BALL AND METHOD FOR MANUFACTURING SAME

본 발명에 의한 실시 형태의 땜납 피복 볼(10A)은, 볼 형상의 코어(11)와, 코어(11)를 피복하도록 형성된 땜납층(12)을 갖고, 땜납층(12)은 Sn과 Bi를 함유하고, Bi 함유율이 45 질량% 이상 65 질량% 이하이고, 또한 Bi 함유율은 안쪽에서 높고 바깥쪽에서 낮다. 다른 땜납 피복 볼(10B)은 코어(11)와 땜납층(12) 사이에 Ni 도금층(13)을 더 갖는다. The solder coated ball 10A of the embodiment of the present invention has a ball core 11 and a solder layer 12 formed to cover the core 11. The solder layer 12 includes Sn and Bi , The Bi content is 45 mass% or more and 65 mass% or less, and the Bi content is high in the inside and low in the outside. Another solder coated ball 10B further has a Ni plating layer 13 between the core 11 and the solder layer 12. [

Semiconductor device and manufacturing method thereof

半导体器件及其制造方法。一种半导体器件包括：半导体芯片，其具有通过钝化层暴露的焊盘；凸块柱，其形成在与焊盘相邻的钝化层上方但不与焊盘交叠。半导体芯片还具有焊料层，该焊料层包括焊料凸块部分和焊料焊脚部分，该焊料凸块部分形成在凸块柱上方，该焊料焊脚部分形成在凸块柱的面向焊盘的一侧以覆盖焊盘，并且该焊料焊脚部分将凸块柱与焊盘电联接。

METAL COATING FOR INDIUM BUMP BONDING

A process of efficient metal bump bonding with relatively low temperatures, preferably lower than the melting point of indium, is described. To obtain a lower processing temperature (preferred embodiments have a melting point of < 100°C), a metal or alloy layer (138) is deposited on the indium bump (134) surface. Preferably, the material is chosen such that the metal or alloy forms a passivation layer that is more resistant to oxidation than the underlying indium material. The passivation material is also preferably chosen to form a low melting temperature alloy with indium at the indium bump (134) surface. This is typically accomplished by diffusion of the passivation material into the indium to form a diffusion layer alloy. Various metals, including Ga, Bi, Sn, Pb and Cd, can be used to form a binary to quaternary low melting point alloy with indium. In addition, diffusion of metal such as Sn, Sn-Zn into Ga-In alloy; Sn, Cd, Pb-Sn into Bi-In alloy; Cd, Zn, Pb, Pb-Cd into Sn-In alloy can help adjust the melting point of the alloy.

SOLDER-COATED BALL AND METHOD FOR MANUFACTURING SAME

A solder-coated ball (10A) according to one embodiment of the present invention has a ball-shaped core (11) and a solder layer (12) formed so as to coat the core (11), the solder layer (12) includes Sn and Bi, the Bi content is 45 mass% to 65 mass%, and the Bi content is high on the inside and low on the outside. Another solder-coated ball (10B) further has a Ni plating layer (13) between the core (11) and the solder layer (12).

Method for forming metal bumps

A method for forming metal bumps is disclosed. Steps of the method include supplying a substrate containing a plurality of pads; forming a first photoresist layer on the substrate, herein the first photoresist layer covers the pads; performing a planarization step to remove a portion of the first photoresist layer so as to expose the pads; forming a conductive layer on the first photoresist layer and the pads; electroplating a metal layer on the conductive layer; forming a patterned second photoresist layer on the metal layer; a portion of the metal layer and the conductive layer which are not covered by the patterned second photoresist layer is removed by using the patterned second photoresist layer as a mask; removing the patterned second photoresist layer; and forming a solder mask on the substrate, wherein the solder mask has a plurality of openings to expose the metal layer located on the pads.

Semiconductor element, method for manufacturing the same, and mounting structure having the semiconductor element mounted thereon

A semiconductor element that is excellent in both mechanical reliability and electrical reliability and a mounting structure for the semiconductor element are provided. The semiconductor element includes: a substrate; an electrically conductive layer on the substrate; a protective layer having an opening on the electrically conductive layer; a barrier metal layer in contact with the electrically conductive layer in the opening; and an electrically conductive bump on the barrier metal layer. The barrier metal layer contains phosphorus and has a phosphorus-rich portion that has a higher phosphorus content than the remaining portion has. The phosphorus-rich portion is located in the surface of the barrier metal layer facing the electrically conductive bump, and the thickness thereof in the periphery of the region where the electrically conductive bump is formed is larger than at the center of the region.

Sintered conductive matrix material on wire bond

A method is disclosed of fabricating a microelectronic package comprising a substrate overlying the front face of a microelectronic element. A plurality of metal bumps project from conductive elements of the substrate towards the microelectronic element, the metal bumps having first ends extending from the conductive elements, second ends remote from the conductive elements, and lateral surfaces extending between the first and second ends. The metal bumps can be wire bonds having first and second ends attached to a same conductive pad of the substrate. A conductive matrix material contacts at least portions of the lateral surfaces of respective ones of the metal bumps and joins the metal bumps with contacts of the microelectronic element.

CONDUCTIVE CONNECTING MEMBER AND MANUFACTURING METHOD OF SAME

Disclosed is a conductive connecting member such as a conductive bump composed of a porous metallic body having an excellent heat cycle, and a conductive die-bond unit and the like. A conductive connecting member formed at a joint surface of a semiconductor element electrode terminal or a circuit substrate electrode terminal, wherein the conductive connecting member is a porous metallic body formed by joining together fine metallic particles by heat-treating a conductive paste that includes fine metallic particles (P) of a mean primary particle diameter of 10 - 500 nm, an organic solvent (S), or an organic dispersing medium (D) composed of an organic solvent (S) and an organic binder (R). Porosity of the fine metallic particles is in a range of 10 - 500 nm; and an average pore size existing between the fine metallic particles is in a range of 1 - 200 nm.

Solder bump structure for flip chip package and method for manufacturing the same

A solder bump structure may have a metal stud formed on a chip pad of a semiconductor chip. Surfaces of the metal stud may be plated with a solder. The metal stud may be located on a substrate pad of the substrate. The substrate pad may have a pre-solder applied thereto. After a solder reflow, the solder bump may have a concave shape.

CONDUCTIVE BONDING MATERIAL AND A CONDUCTOR JOINING METHOD CAPABLE OF EFFECTIVELY JOINING SUBSTRATES AND ELECTRONIC COMPONENTS AT LOW TEMPERATURES OF UNDER 150 °C

PURPOSE: A conductive bonding material and a conductor joining method are provided to remain components having a low melting point after a primary thermal treatment because the conductive bonding material contains metal components having three-stepped melting points. CONSTITUTION: A conductive bonding material(20) comprises metal particles(21) having a high melting point over a first melting point, metal particles(22) having a middle melting point, and metal particles(23) having a low melting point. The metal particles having the middle melting point have a second melting point which is over a first temperature and under a second temperature being lower than the first melting point. The metal particles having the low melting point have a third melting point under the first temperature. The high melting point is over 150 °C, the middle melting point is within 80-139 °C, and the low melting point is under 79 °C. COPYRIGHT KIPO 2012 ...

CONCAVE SOLDER BUMP STRUCTURE OF FLIP CHIP PACKAGE FOR ACQUIRING FINE PITCH REGARDLESS OF SIZE OF SOLDER BUMP AND MANUFACTURING METHOD THEREOF

PURPOSE: A solder bump structure and manufacturing method thereof are provided to embody a flip chip package with fine pitch regardless of the size of a solder bump and the distance between solder bumps by forming the solder bump like a concave type structure. CONSTITUTION: A solder bump structure includes a semiconductor chip(10) with a plurality of chip pads(12), a substrate(20) with a plurality of substrate pads(22) corresponding to the chip pads, and a plurality of solder bumps(70) between the chip pads and the substrate pads. Each solder bump is formed like a concave type structure. The solder bump structure further includes a metal pillar(60) in the solder bump and a lower bump metal film(16) between the solder bump and the chip pad. © KIPO 2006 ...

Integrated circuit chip with pyramid or cone-shaped conductive pads for flexible C4 connections and a method of forming the integrated circuit chip

Disclosed is a chip and method of forming the chip with improved conductive pads that allow for flexible C4 connections with a chip carrier or with another integrated circuit chip. The pads have a three-dimensional geometric shape (e.g., a pyramid or cone shape) with a base adjacent to the surface of the chip, a vertex opposite the base and, optionally, mushroom-shaped cap atop the vertex. Each pad can include a single layer of conductive material or multiple layers of conductive material (e.g., a wetting layer stacked above a non-wetting layer). The pads can be left exposed to allow for subsequent connection to corresponding solder bumps on a chip carrier or a second chip. Alternatively, solder balls can be positioned on the conductive pads to allow for subsequent connection to corresponding solder-paste filled openings on a chip carrier or a second chip.

Method for forming metal bumps

A method for forming metal bumps is disclosed. Steps of the method include supplying a substrate containing a plurality of pads; forming a first photoresist layer on the substrate, herein the first photoresist layer covers the pads; performing a planarization step to remove a portion of the first photoresist layer so as to expose the pads; forming a conductive layer on the first photoresist layer and the pads; electroplating a metal layer on the conductive layer; forming a patterned second photoresist layer on the metal layer; a portion of the metal layer and the conductive layer which are not covered by the patterned second photoresist layer is removed by using the patterned second photoresist layer as a mask; removing the patterned second photoresist layer; and forming a solder mask on the substrate, wherein the solder mask has a plurality of openings to expose the metal layer located on the pads.

Polymer layer on metal core for plurality of bumps connected to conductive pads

A semiconductor chip, a display device or an electronic device includes a substrate, one or more conductive pads disposed on the substrate, and one or more bumps electrically connected to the one or more conductive pads, in which the one or more bumps includes a metal core, a polymer layer disposed over a surface of the metal core, and a conductive coating layer disposed over a surface of the polymer layer and electrically connected to the one or more conductive pads.

Mechanisms for forming post-passivation interconnect structure

Mechanisms for forming a semiconductor device are provided. The semiconductor device includes a contact pad over a substrate. The semiconductor device also includes a passivation layer over the substrate and a first portion of the contact pad, and a second portion of the contact pad is exposed through an opening. The semiconductor device further includes a post-passivation interconnect layer over the passivation layer and coupled to the second portion of the contact pad. In addition, the semiconductor device includes a bump over the post-passivation interconnect layer and outside of the opening. The semiconductor device also includes a diffusion barrier layer physically insulating the bump from the post-passivation interconnect layer while electrically connecting the bump to the post-passivation interconnect layer.

Solder-coated ball and method for manufacturing same

A solder-coated ball (10A) according to one embodiment of the present invention has a ball-shaped core (11) and a solder layer (12) formed so as to coat the core (11), the solder layer (12) includes Sn and Bi, the Bi content is 45 mass% to 65 mass%, and the Bi content is high on the inside and low on the outside. Another solder-coated ball (10B) further has a Ni plating layer (13) between the core (11) and the solder layer (12).

Pre-package and methods of manufacturing semiconductor package and electronic device using the same

Methods of fabricating semiconductor packages are provided. One of the methods includes forming a protection layer including metal on a first surface of a substrate to cover a semiconductor device disposed on the first surface of the substrate, attaching a support substrate to the protection layer by using an adhesive member, processing a second surface of the substrate opposite to the protection layer to remove a part of the substrate, and detaching the support substrate from the substrate.

Integrated circuit device

집적회로 소자는 기판 위에 형성된 층간절연막과, 층간절연막 위에 형성된 배선층과, 배선층에 접촉하는 일단을 가지고 층간절연막 및 기판을 관통하는 비아홀의 내부로부터 비아홀의 외부까지 일체로 연장되어 있는 TSV 콘택 패턴을 포함한다. The integrated circuit device includes an interlayer insulating film formed on the substrate, a wiring layer formed on the interlayer insulating film, and a TSV contact pattern extending integrally from the inside of the via hole passing through the interlayer insulating film and the substrate to the outside of the via hole, do.

Light-Emitting Device and Displayer

The disclosure provides a light-emitting device and a displayer. Herein, the light-emitting device includes a substrate, a light-emitting chip, a first light-transmitting layer, a second light-transmitting layer and a nano coating. The light transmittance of the second light-transmitting layer is greater than the light transmittance of the first light-transmitting layer. A reference surface corresponding to the light-emitting chip is arranged above the substrate, and the reference surface is higher than the bottom surface of the light-emitting chip and not higher than the top surface of the light-emitting chip. The first light-transmitting layer covers the surface of the light-emitting chip below the reference surface, and the second light-transmitting layer covers the surface of the light-emitting chip above the reference surface. The nano coating covers the outer surface of the first light-transmitting layer, the outer surface of the second light-transmitting layer and the side surface of the substrate.

Forming Method for Concave Solder Bump Structure of Flip Chip Package

본 발명은 플립 칩 패키지의 오목형 솔더 범프 구조 형성 방법에 관한 것으로서, 가운데가 오목한 오목형 솔더 범프 구조는 칩과 기판 사이의 언더필 공정이 가능할 만큼의 범프 높이를 가지면서 솔더 범프의 크기나 솔더 범프간 거리의 영향을 받지 않으므로 미세 피치의 플립 칩 패키지를 구현할 수 있다. 본 발명에 따르면, 반도체 칩의 칩 패드 위에 금속 기둥을 형성하고 금속 기둥의 표면에 솔더를 도금한 후, 솔더가 미리 도포된 기판의 기판 패드 위에 솔더가 도금된 금속 기둥을 위치시키고 솔더를 리플로우하면, 용융 솔더의 표면 장력에 의하여 가운데가 오목한 형태의 오목형 솔더 범프가 형성된다. The present invention relates to a method of forming a concave solder bump structure of a flip chip package, wherein the concave concave solder bump structure in the center has a bump height sufficient to allow an underfill process between the chip and the substrate, and the size of the solder bumps or the solder bumps. Since it is not affected by the distance, a fine pitch flip chip package can be implemented. According to the present invention, after forming a metal pillar on the chip pad of the semiconductor chip and plating the solder on the surface of the metal pillar, the solder-plated metal pillar is placed on the substrate pad of the solder-coated substrate and the solder is reflowed. The concave solder bumps having a concave shape in the middle are formed by the surface tension of the molten solder. 플립 칩(flip chip), 솔더 범프(solder bump), 언더필(underfill), 미세 피치(fine pitch), 표면 장력(surface tension) Flip chip, solder bump, underfill, fine pitch, surface tension

SEMICONDUCTOR ELEMENT, SEMICONDUCTOR ELEMENT MANUFACTURING METHOD, AND MOUNTING STRUCTURE HAVING SEMICONDUCTOR ELEMENT MOUNTED THEREON

Provided is a semiconductor element which excels in both mechanical reliability and electrical reliability. A structure having such semiconductor element mounted thereon is also provided. The semiconductor element is provided with a substrate; a conductive layer arranged on the substrate; a protection layer having an opening section arranged on the conductive layer; a barrier metal layer bonded on the conductive layer at the opening section; and a conductive bump formed on the barrier metal layer. The barrier metal layer contains phosphorus, and includes a phosphorus-rich portion where the phosphorus content is higher than that at other portion. The phosphorus-rich portion is positioned on the surface on the conductive bump side, and has a thickness at the periphery of the conductive bump forming region more than that of the center portion of the forming region.

CONDUCTIVE CONNECTING MEMBER AND MANUFACTURING METHOD OF SAME

STACKED SEMICONDUCTOR DEVICES, PARTICULARLY MEMORY CHIPS

High density packaging of semiconductor devices on an interconnection substrate is achieved by stacking bare semiconductor devices (402, 404, 406, 408) atop one another so that an edge portion of a semiconductor device extends beyond the semiconductor device that it is stacked atop. Elongate interconnection elements (422, 424, 426, 428) extend from the bottommost one of the semiconductor devices, and from the exposed edge portions of the semiconductor devices stacked atop the bottommost semiconductor device. Free-ends of the elongate interconnection elements make electrical contact with terminals of an interconnection substrate (430), such as a PCB. The elongate interconnection elements extending from each of the semiconductor devices are sized so as to reach the terminals of the PCB, which may be plated through holes (432, 434, 436, 438). The elongate interconnection elements are suitably resilient contact structures, and may be composite interconnection elements comprising a relatively ...

VISIBILITY EVENT NAVIGATION METHOD AND SYSTEM

A method of visibility event navigation includes receiving, via processing circuitry of a client device, a first visibility event packet from a server, the first visibility event packet including information representing 3D surface elements of an environmental model that are occluded from a first viewcell and not occluded from a second viewcell, the first and second viewcells representing spatial regions of a specified navigational route within a real environment modeled by the environmental model. The method also includes acquiring, surface information representing the visible surfaces of the real environment at a sensor and determining, a position in the real environment by matching the surface information to the visibility event packet information. The method further includes transmitting, the position from the client device to the server and receiving a second visibility event packet from the server if the at least one position is within the specified navigational route. 1receiving, via processing circuitry of a client device, at least one visibility event packet of the one or more visibility event packets from the server;detecting, via the circuitry, surface information representing one or more visible surfaces of the real environment at a sensor in communication with the client device;calculating, via the circuitry, at least one position of the client device in the real environment by matching the surface information to the visibility event packet information corresponding to a first visibility event packet of the one or more visibility event packets;transmitting, via the circuitry, the at least one position from the client device to the server; andreceiving, via the circuitry, at least one second visibility event packet of the one or more visibility event packets when the at least one position is within the navigational route at the client device from the server.. A method of visibility event navigation, including one or more visibility event packets located ...

Semiconductor device and method for manufacturing the same

一種半導體裝置包括：半導體晶片，其具有透過鈍化層暴露的襯墊；凸塊柱，其形成在與所述襯墊相鄰的所述鈍化層上方但不與所述襯墊交疊。所述半導體晶片還具有焊料層，該焊料層包括焊料凸塊部分和焊料焊腳部分，該焊料凸塊部分形成在所述凸塊柱上方，該焊料焊腳部分形成在所述凸塊柱的面向所述襯墊的一側以覆蓋所述襯墊，並且該焊料焊腳部分將所述凸塊柱與所述襯墊電連接。

METAL COATING FOR INDIUM BUMP BONDING

A process of efficient metal bump bonding with relatively low temperatures, preferably lower than the melting point of indium, is described. To obtain a lower processing temperature (preferred embodiments have a melting point of < 100°C), a metal or alloy layer (138) is deposited on the indium bump (134) surface. Preferably, the material is chosen such that the metal or alloy forms a passivation layer that is more resistant to oxidation than the underlying indium material. The passivation material is also preferably chosen to form a low melting temperature alloy with indium at the indium bump (134) surface. This is typically accomplished by diffusion of the passivation material into the indium to form a diffusion layer alloy. Various metals, including Ga, Bi, Sn, Pb and Cd, can be used to form a binary to quaternary low melting point alloy with indium. In addition, diffusion of metal such as Sn, Sn-Zn into Ga-In alloy; Sn, Cd, Pb-Sn into Bi-In alloy; Cd, Zn, Pb, Pb-Cd into Sn-In alloy can ...

Solder bump structure for flip chip package and method for manufacturing the same

A solder bump structure may have a metal stud formed on a chip pad of a semiconductor chip. Surfaces of the metal stud may be plated with a solder. The metal stud may be located on a substrate pad of the substrate. The substrate pad may have a pre-solder applied thereto. After a solder reflow, the solder bump may have a concave shape.

Semiconductor element, semiconductor element manufacturing method, and mounting structure having semiconductor element mounted thereon

Semiconductor device with gold bumps, and method and apparatus of producing the same

A semiconductor device comprises a semiconductor element having electrodes and metal bumps are attached to the electrodes. The metal bumps include copper cores and gold surface layers covering the cores. In addition, the metal bumps may include gold bump elements and solder bump elements connected together.

Semiconductor Element, Method for Manufacturing the Same, and Mounting Structure Having the Semiconductor Element Mounted Thereon

A semiconductor element that is excellent in both mechanical reliability and electrical reliability and a mounting structure for the semiconductor element are provided. The semiconductor element includes: a substrate; an electrically conductive layer on the substrate; a protective layer having an opening on the electrically conductive layer; a barrier metal layer in contact with the electrically conductive layer in the opening; and an electrically conductive bump on the barrier metal layer. The barrier metal layer contains phosphorus and has a phosphorus-rich portion that has a higher phosphorus content than the remaining portion has. The phosphorus-rich portion is located in the surface of the barrier metal layer facing the electrically conductive bump, and the thickness thereof in the periphery of the region where the electrically conductive bump is formed is larger than at the center of the region.

Solder-coated ball and method for manufacturing same

Semiconductor device with gold bumps, and method and apparatus of producing the same

A semiconductor device comprises a semiconductor element having electrodes and metal bumps are attached to the electrodes. The metal bumps include copper cores and gold surface layers covering the cores. In addition, the metal bumps may include gold bump elements and solder bump elements connected together.

Integrated circuit device

Core material, semiconductor package, and forming method of bump electrode

A core material includes a core 12 and a solder plating layer 16 of an (Sn-Bi)-based solder alloy made of Sn and Bi covered on a surface of the core. Bi in the solder plating layer 16 is distributed in the solder plating layer at a concentration ratio in a predetermined range of, for example, 91.7% to 106.7%. Bi in the solder plating layer is homogeneous, and thus, a Bi concentration ratio is in a predetermined range over the entire range including an inner circumference side and an outer circumference side in the solder plating layer. Therefore, any situation does not occur in which the inner circumference side is earlier melted than the outer circumference side and a volume expansion difference occurs between the inner circumference side and the outer circumference side, and thus, the core material is flicked off. Since the whole of the solder plating layer is almost homogeneously melted, positional shift of the core material due to a shift in the melting timing does not occur, and thus ...

SPRING ELEMENT ELECTRICAL CONTACT AND METHODS

Spring elements (540) for use as electrical contacts are fabricated by shaping a relatively soft core (112, 122) and overcoating the shaped core (702) with a relatively hard material (114, 124). Additional overcoat layers may be applied to enhance the electrical characteristics of the resulting spring element (540). The spring elements (540) are fabricated from an elongate element (602) which is shaped to exhibit a plurality of spring element cores linked end-to-end, which are then overcoated. The resulting spring elements (540) may then be attached to electronic components (708) by automated machinery (620). An external shaping tool is disclosed, which is particularly useful for shaping a plurality of linked and separable spring elements (540) which are inherently springy (i.e., formed of a relatively hard material).

Method for forming metal bumps

A method for forming metal bumps is disclosed. Steps of the method include supplying a substrate containing a plurality of pads; forming a first photoresist layer on the substrate, herein the first photoresist layer covers the pads; performing a planarization step to remove a portion of the first photoresist layer so as to expose the pads; forming a conductive layer on the first photoresist layer and the pads; electroplating a metal layer on the conductive layer; forming a patterned second photoresist layer on the metal layer; a portion of the metal layer and the conductive layer which are not covered by the patterned second photoresist layer is removed by using the patterned second photoresist layer as a mask; removing the patterned second photoresist layer; and forming a solder mask on the substrate, wherein the solder mask has a plurality of openings to expose the metal layer located on the pads.

Electroconductive bonding material comprising three types of metal particles with different melting points and its use for bonding an electronic component to a substrate

An electro-conductive bonding material (20,30) includes: high-melting-point metal particles with a component having a first melting point, middle-melting-point metal particles having a second melting point, lower than the first melting point, low-melting-point metal particles having a third melting point, lower than the second melting point and preferably a flux. The high-melting-point metal particles include Au, Ag, Cu, Au-plated Cu, Sn-Bi-plated Cu and Ag-plated Cu particles. The middle-melting-point metal particles include Sn-Bi and Sn-Bi-Ag particles. The low-melting-point metal particles include Sn-Bi-ln and Sn-Bi-Ga particles. The electro-conductive bonding material (20,30) is used for bonding a substrate (6) and an electronic component (8). A method for bonding comprises supplying the electro-conductive bonding material (e.g. by paste printing) to any one of an electrode (7) of a substrate (6) and a terminal of an electronic component (8) (e.g. an Au bump (9)), heating the supplied ...

Semiconductor device with gold bumps, and method and apparatus of producing the same

A semiconductor device includes a semiconductor element having electrodes and metal bumps are attached to the electrodes. The metal bumps include copper cores and gold surface layers covering the cores. In addition, the metal bumps may include gold bump elements and solder bump elements connected together.

Bump electrode, board which has bump electrodes, and method for manufacturing the board

A bump electrode is formed on an electrode pad using a Cu core ball in which a core material is covered with solder plating, and a board which has bump electrodes such as semiconductor chip or printed circuit board mounts such a bump electrode. Flux is coated on a substrate and the bump electrodes are then mounted on the electrode pad. In a step of heating the electrode pad and the Cu core ball to melt the solder plating, a heating rate of the substrate is set to have not less than 0.01° C./sec and less than 0.3.

Solder bump structure for flip chip package and method for manufacturing the same

A solder bump structure may have a metal stud formed on a chip pad of a semiconductor chip. Surfaces of the metal stud may be plated with a solder. The metal stud may be located on a substrate pad of the substrate. The substrate pad may have a pre-solder applied thereto. After a solder reflow, the solder bump may have a concave shape.

MULTI-CHIP PACKAGE AND MANUFACTURING METHOD THEREOF

A multi-chip package and a manufacturing method thereof are provided. The multi-chip package includes: an interposer including a wiring structure and an interposer via electrically connected to the wiring structure; a plurality of semiconductor chips located on a first surface of the interposer and electrically connected to each other through the interposer; an encapsulant located on the first surface of the interposer and encapsulating at least a portion of the plurality of semiconductor chips; and a redistribution circuit structure located on a second surface of the interposer opposite to the first surface, wherein the plurality of semiconductor chips are electrically connected to the redistribution circuit structure through at least the interposer.

Flip chip assembly and process with sintering material on metal bumps

A microelectronic package includes a substrate overlying the front face of a microelectronic element. A plurality of metal bumps can project from conductive elements of the substrate towards the microelectronic element, the metal bumps having first ends extending from the conductive elements, second ends remote from the conductive elements, and lateral surfaces extending between the first and second ends. A conductive matrix material can contact the second ends and at least portions of the lateral surfaces of respective ones of the metal bumps and join the metal bumps with contacts of the microelectronic element.

Mechanisms for Forming Post-Passivation Interconnect Structure

Mechanisms for forming a semiconductor device are provided. The semiconductor device includes a contact pad over a substrate. The semiconductor device also includes a passivation layer over the substrate and a first portion of the contact pad, and a second portion of the contact pad is exposed through an opening. The semiconductor device further includes a post-passivation interconnect layer over the passivation layer and coupled to the second portion of the contact pad. In addition, the semiconductor device includes a bump over the post-passivation interconnect layer and outside of the opening. The semiconductor device also includes a diffusion barrier layer physically insulating the bump from the post-passivation interconnect layer while electrically connecting the bump to the post-passivation interconnect layer.

VISIBILITY EVENT NAVIGATION METHOD AND SYSTEM

A method of visibility event navigation includes receiving, via processing circuitry of a client device, a first visibility event packet from a server, the first visibility event packet including information representing 3D surface elements of an environmental model that are occluded from a first viewcell and not occluded from a second viewcell, the first and second viewcells representing spatial regions of a specified navigational route within a real environment modeled by the environmental model. The method also includes acquiring, surface information representing the visible surfaces of the real environment at a sensor and determining, a position in the real environment by matching the surface information to the visibility event packet information. The method further includes transmitting, the position from the client device to the server and receiving a second visibility event packet from the server if the at least one position is within the specified navigational route.

PACKAGE STRUCTURE AND METHOD FOR CONNECTING COMPONENTS

A package structure and a method for connecting components are provided, in which the package includes a first substrate including a first wiring and at least one first contact connecting to the first wiring; a second substrate including a second wiring and at least one second contact connecting to the second wiring, the at least one first contact and the at least one second contact partially physically contacting with each other or partially chemically interface reactive contacting with each other; and at least one third contact surrounding the at least one first contact and the at least one second contact. The first substrate and the second substrate are electrically connected with each other at least through the at least one first contact and the at least one second contact.

ALLOY DIFFUSION BARRIER LAYER

A microelectronic device includes a reflow structure. The reflow structure has a copper-containing member and a solder member, and a barrier layer between them. The barrier layer has metal grains, with a diffusion barrier filler between the metal grains. The metal grains include at least a first metal and a second metal, each selected from nickel, cobalt, lanthanum, and cerium, with each having a concentration in the metal grains of at least 10 weight percent. The diffusion barrier filler includes at least a third metal, selected from tungsten and molybdenum. A combined concentration of tungsten and molybdenum in the diffusion barrier filler is higher than in the metal grains to provide a desired resistance to diffusion of copper. The barrier layer includes 2 weight percent to 15 weight percent of the combined concentration of tungsten, and molybdenum. A bump bond structure and a lead frame package are disclosed. 1. A microelectronic device , comprising:a bond pad electrically connected to a semiconductor die;copper on the bond pad; at least 10 weight percent of a first metal selected from the group consisting of nickel, cobalt, lanthanum, and cerium;', 'at least 10 weight percent of a second metal, different from the first metal, selected from the group consisting of nickel, cobalt, lanthanum, and cerium; and', 'at least 2 weight percent of a third metal selected from the group consisting of tungsten and molybdenum; and, 'a layer on the copper, the layer includingsolder on the layer.2. The microelectronic device of claim 1 , wherein the third metal is in between the grains of the first metal or the grains of the second metal.3. The microelectronic device of claim 1 , wherein the third metal is in between the grains of the first metal and the grains of the second metal.4. The microelectronic device of further comprising intermetallic compounds between the solder and the layer.5. The microelectronic device of claim 1 , wherein a combined concentration of tungsten and ...

CORE MATERIAL, SEMICONDUCTOR PACKAGE, AND FORMING METHOD OF BUMP ELECTRODE

Solder-coated ball and method for manufacturing same

A solder-coated ball(10A) according to an embodiment of the present invention includes a spherical core(11) and a solder layer(12) which has been formed to coat the core(11). The solder layer(12) includes Sn and Bi and has a Bi content of 45 mass% to 65 mass%, which is relatively high in its inside portion and relatively low in its outside portion. Another solder-coated ball(10B) further includes a Ni-plated layer 13 between the core 11 and the solder layer 12.

Semiconductor device with gold bumps, and method and apparatus of producing the same

A semiconductor device comprises a semiconductor element having electrodes and metal bumps are attached to the electrodes. The metal bumps include copper cores and gold surface layers covering the cores. In addition, the metal bumps may include gold bump elements and solder bump elements connected together.

Stacking semiconductor devices, particularly memory chips

High density packaging of semiconductor devices on an interconnection substrate is achieved by stacking bare semiconductor devices atop one another so that an edge portion of a semiconductor device extends beyond the semiconductor device that it is stacked atop. Elongate interconnection elements extend from the bottommost one of the semiconductor devices, and from the exposed edge portions of the semiconductor devices stacked atop the bottommost semiconductor device. Free-ends of the elongate interconnection elements make electrical contact with terminals of an interconnection substrate, such as a PCB. The elongate interconnection elements extending from each of the semiconductor devices are sized so as to reach the terminals of the PCB, which may be plated through holes. The elongate interconnection elements are suitably resilient contact structures, and may be composite interconnection elements comprising a relatively soft core (e.g., a gold wire) and a relatively hard overcoat (e.g., ...

FLIP CHIP ASSEMBLY AND PROCESS WITH SINTERING MATERIAL ON METAL BUMPS

A microelectronic package includes a substrate overlying the front face of a microelectronic element. A plurality of metal bumps can project from conductive elements of the substrate towards the microelectronic element, the metal bumps having first ends extending from the conductive elements, second ends remote from the conductive elements, and lateral surfaces extending between the first and second ends. A conductive matrix material can contact the second ends and at least portions of the lateral surfaces of respective ones of the metal bumps and join the metal bumps with contacts of the microelectronic element.

Semiconductor package including bump

A semiconductor device includes a semiconductor chip having a pad which is exposed through a passivation layer, a bump pillar formed over the passivation layer adjacent to the pad, but not overlapping with the pad. The semiconductor chip also has a solder layer including a solder bump portion which is formed over the bump pillar and a solder fillet portion which is formed at one side of the bump pillar facing the pad to cover the pad and electrically couples the bump pillar and the pad.

Mechanisms for Forming Post-Passivation Interconnect Structure

Mechanisms for forming a semiconductor device are provided. The semiconductor device includes a contact pad over a substrate. The semiconductor device also includes a passivation layer over the substrate and a first portion of the contact pad, and a second portion of the contact pad is exposed through an opening. The semiconductor device further includes a post-passivation interconnect layer over the passivation layer and coupled to the second portion of the contact pad. In addition, the semiconductor device includes a bump over the post-passivation interconnect layer and outside of the opening. The semiconductor device also includes a diffusion barrier layer physically insulating the bump from the post-passivation interconnect layer while electrically connecting the bump to the post-passivation interconnect layer. 1. A device comprising:a substrate comprising a contact pad;a first dielectric layer on the substrate and the contact pad;a post-passivation interconnect layer having a first portion and a second portion, the first portion extending through the first dielectric layer to contact the contact pad, the second portion extending along a major surface of the first dielectric layer;a first diffusion barrier on the first portion and the second portion of the post-passivation interconnect layer, the first diffusion barrier comprising a plurality of conductive layers;a conductive bump on the first diffusion barrier, the conductive bump being laterally offset from the first portion of the post-passivation interconnect layer; anda molding compound layer on the first diffusion barrier, the molding compound layer surrounding a bottom portion of the conductive bump, a topmost surface of the molding compound layer being disposed at a level between a topmost point of the conductive bump and a topmost surface of the first diffusion barrier.2. The device of further comprising:a second dielectric layer disposed between the first dielectric layer and the second portion of the ...

Core material, semiconductor package, and forming method of bump electrode

A core material including a core and a solder plating layer of a (Sn—Bi)-based solder alloy made of Sn and Bi on a surface of the core. Bi in the solder plating layer is distributed in the solder plating layer at a concentration ratio in a predetermined range of, for example, 91.7% to 106.7%. Bi in the solder plating layer is homogeneous, and thus, a Bi concentration ratio is in a predetermined range over the entire solder plating layer including an inner circumference side and an outer circumference side in the solder plating layer.

Integrated circuit chip with pyramid or cone-shaped conductive pads for flexible C4 connections and a method of forming the integrated circuit chip

Disclosed is a chip and method of forming the chip with improved conductive pads that allow for flexible C4 connections with a chip carrier or with another integrated circuit chip. The pads have a three-dimensional geometric shape (e.g., a pyramid or cone shape) with a base adjacent to the surface of the chip, a vertex opposite the base and, optionally, mushroom-shaped cap atop the vertex. Each pad can include a single layer of conductive material or multiple layers of conductive material (e.g., a wetting layer stacked above a non-wetting layer). The pads can be left exposed to allow for subsequent connection to corresponding solder bumps on a chip carrier or a second chip. Alternatively, solder balls can be positioned on the conductive pads to allow for subsequent connection to corresponding solder-paste filled openings on a chip carrier or a second chip.

Package structure and method for connecting components

A package structure and a method for connecting components are provided, in which the package includes a first substrate including a first wiring and at least one first contact connecting to the first wiring; a second substrate including a second wiring and at least one second contact connecting to the second wiring, the at least one first contact and the at least one second contact partially physically contacting with each other or partially chemically interface reactive contacting with each other; and at least one third contact surrounding the at least one first contact and the at least one second contact. The first substrate and the second substrate are electrically connected with each other at least through the at least one first contact and the at least one second contact.

Packaging structure and assembly connection method

Alloy diffusion barrier layer

Electroconductive bonding material, method for bonding conductor, and method for manufacturing semiconductor device

An electro-conductive bonding material includes: metal components of a high-melting-point metal particle that have a first melting point or higher; a middle-melting-point metal particle that has a second melting point which is first temperature or higher, and second temperature or lower, the second temperature is lower than the first melting point and higher than the first temperature; and a low-melting-point metal particle that has a third melting point or lower, the third melting point is lower than the first temperature.

PRE-PACKAGE AND METHODS OF MANUFACTURING SEMICONDUCTOR PACKAGE AND ELECTRONIC DEVICE USING THE SAME

Methods of fabricating semiconductor packages are provided. One of the methods includes forming a protection layer including metal on a first surface of a substrate to cover a semiconductor device disposed on the first surface of the substrate, attaching a support substrate to the protection layer by using an adhesive member, processing a second surface of the substrate opposite to the protection layer to remove a part of the substrate, and detaching the support substrate from the substrate.

SEMICONDUCTOR PACKAGE INCLUDING BUMP

A semiconductor device includes a semiconductor chip having a pad which is exposed through a passivation layer, a bump pillar formed over the passivation layer adjacent to the pad, but not overlapping with the pad. The semiconductor chip also has a solder layer including a solder bump portion which is formed over the bump pillar and a solder fillet portion which is formed at one side of the bump pillar facing the pad to cover the pad and electrically couples the bump pillar and the pad.

VISIBILITY EVENT NAVIGATION METHOD AND SYSTEM

A method of visibility event navigation includes receiving, via processing circuitry of a client device, a first visibility event packet from a server, the first visibility event packet including information representing 3D surface elements of an environmental model that are occluded from a first viewcell and not occluded from a second viewcell, the first and second viewcells representing spatial regions of a specified navigational route within a real environment modeled by the environmental model. The method also includes acquiring, surface information representing the visible surfaces of the real environment at a sensor and determining, a position in the real environment by matching the surface information to the visibility event packet information. The method further includes transmitting, the position from the client device to the server and receiving a second visibility event packet from the server if the at least one position is within the specified navigational route. 1receiving, via processing circuitry of a client device, at least one visibility event packet of the one or more visibility event packets from the server;detecting, via the circuitry, surface information representing one or more visible surfaces of the real environment at a sensor in communication with the client device;calculating, via the circuitry, at least one position of the client device in the real environment by matching the surface information to the visibility event packet information corresponding to a first visibility event packet of the one or more visibility event packets;transmitting, via the circuitry, the at least one position from the client device to the server; andreceiving, via the circuitry, at least one second visibility event packet of the one or more visibility event packets when the at least one position is within the navigational route at the client device from the server.. A method of visibility event navigation, including one or more visibility event packets located ...

Expanded head pillar for bump bonds

A microelectronic device has a bump bond structure including an electrically conductive pillar with an expanded head, and solder on the expanded head. The electrically conductive pillar includes a column extending from an I/O pad to the expanded head. The expanded head extends laterally past the column on at least one side of the electrically conductive pillar. In one aspect, the expanded head may have a rounded side profile with a radius approximately equal to a thickness of the expanded head, and a flat top surface. In another aspect, the expanded head may extend past the column by different lateral distances in different lateral directions. In a further aspect, the expanded head may have two connection areas for making electrical connections to two separate nodes. Methods for forming the microelectronic device are disclosed.

Mechanisms for forming post-passivation interconnect structure

Embodiments of mechanisms for forming a semiconductor device are provided. The semiconductor device includes a contact pad over a substrate. The semiconductor device also includes a passivation layer over the substrate and a first portion of the contact pad, and a second portion of the contact pad is exposed through an opening. The semiconductor device further includes a post-passivation interconnect layer over the passivation layer and coupled to the second portion of the contact pad. In addition, the semiconductor device includes a bump over the post-passivation interconnect layer and outside of the opening. The semiconductor device also includes a diffusion barrier layer physically insulating the bump from the post-passivation interconnect layer while electrically connecting the bump to the post-passivation interconnect layer.

The bump electrodes, the bump electrodes substrate and manufacturing method thereof

Integrated circuit devices including through-silicon-vias having integral contact pads

An integrated circuit device including an interlayer insulating layer on a substrate, a wire layer on the interlayer insulating layer, and a through-silicon-via (TSV) contact pattern having an end contacting the wire layer and integrally extending from inside of a via hole formed through the interlayer insulating layer and the substrate to outside of the via hole.

Semiconductor Device and Method of Forming Bump Structure with Insulating Buffer Layer to Reduce Stress on Semiconductor Wafer

A semiconductor wafer has a plurality of semiconductor die with contact pads for electrical interconnect. An insulating layer is formed over the semiconductor wafer. A bump structure is formed over the contact pads. The bump structure has a buffer layer formed over the insulating layer and contact pad. A portion of the buffer layer is removed to expose the contact pad and an outer portion of the insulating layer. A UBM layer is formed over the buffer layer and contact pad. The UBM layer follows a contour of the buffer layer and contact pad. A ring-shaped conductive pillar is formed over the UBM layer using a patterned photoresist layer filled with electrically conductive material. A conductive barrier layer is formed over the ring-shaped conductive pillar. A bump is formed over the conductive barrier layer. The buffer layer reduces thermal and mechanical stress on the bump and contact pad.

Semiconductor element, semiconductor element manufacturing method, and mounting structure having semiconductor element mounted thereon

Provided is a semiconductor element which excels in both mechanical reliability and electrical reliability. A structure having such semiconductor element mounted thereon is also provided. The semiconductor element is provided with a substrate; a conductive layer arranged on the substrate; a protection layer having an opening section arranged on the conductive layer; a barrier metal layer bonded on the conductive layer at the opening section; and a conductive bump formed on the barrier metal layer. The barrier metal layer contains phosphorus, and includes a phosphorus-rich portion where the phosphorus content is higher than that at other portion. The phosphorus-rich portion is positioned on the surface on the conductive bump side, and has a thickness at the periphery of the conductive bump forming region more than that of the center portion of the forming region.

Semiconductor device with a heterogeneous solder joint and method for fabricating the same

A method for fabricating a semiconductor device with a heterogeneous solder joint includes: providing a semiconductor die; providing a coupled element; and soldering the semiconductor die to the coupled element with a first solder joint. The first solder joint includes: a solder material including a first metal composition; and a coating including a second metal composition, different from the first metal composition, the coating at least partially covering the solder material. The second metal composition has a greater stiffness and/or a higher melting point than the first metal composition.

Bump electrode, board which has bump electrodes and method for manufacturing the board

The present invention is to arrange the center of a Cu ball which is a core layer of a bump electrode on an electrode pad at the center of a shell of a coated solder on a horizontal cross section with high reproducibility. With respect to a melting process of being equipped with a bump electrode (30) processed with solder (14) on a Cu ball (13) which is a core layer, and being bonded to a surface of an electrode pad (12), of mounting the bump electrode (30) on the electrode pad (12) after being applied with flux (16), and of melting a solder plating (24) as the electrode pad (12) and the Cu ball are heated, a heating rate of a substrate (11) where the electrode pad (12) and the Cu core ball are mounted is configured to be in a range of 0.01 [DEG C/sec] or more to 0.3 [DEG C/sec] or less.

SEMICONDUCTOR DEVICE WITH A HETEROGENEOUS SOLDER JOINT AND METHOD FOR FABRICATING THE SAME

A method for fabricating a semiconductor device with a heterogeneous solder joint includes: providing a semiconductor die; providing a coupled element; and soldering the semiconductor die to the coupled element with a first solder joint. The first solder joint includes: a solder material including a first metal composition; and a coating including a second metal composition, different from the first metal composition, the coating at least partially covering the solder material. The second metal composition has a greater stiffness and/or a higher melting point than the first metal composition. 1. A method for fabricating a semiconductor device with a heterogeneous solder joint , the method comprising:providing a semiconductor die;providing a coupled element; and a solder material comprising a first metal composition; and', 'a coating comprising a second metal composition, different from the first metal composition, the coating at least partially covering the solder material,', 'wherein the second metal composition has a greater stiffness and/or a higher melting point than the first metal composition., 'soldering the semiconductor die to the coupled element with a first solder joint, the first solder joint comprising2. The method of claim 1 , wherein the solder material is covered with a coating precursor prior to soldering the semiconductor die to the coupled element claim 1 , and wherein soldering the semiconductor die to the coupled element further comprises converting the coating precursor into the coating.3. The method of claim 2 , further comprising:depositing the solder material on the semiconductor die or on the coupled element; andafterwards covering the deposited solder material with the coating precursor.4. The method of claim 3 , wherein soldering the semiconductor die to the coupled element comprises heating the deposited solder material to melt the deposited solder material claim 3 , and wherein the act of heating the deposited solder material forms the ...

EXPANDED HEAD PILLAR FOR BUMP BONDS

A microelectronic device has a bump bond structure including an electrically conductive pillar with an expanded head, and solder on the expanded head. The electrically conductive pillar includes a column extending from an I/O pad to the expanded head. The expanded head extends laterally past the column on at least one side of the electrically conductive pillar. In one aspect, the expanded head may have a rounded side profile with a radius approximately equal to a thickness of the expanded head, and a flat top surface. In another aspect, the expanded head may extend past the column by different lateral distances in different lateral directions. In a further aspect, the expanded head may have two connection areas for making electrical connections to two separate nodes. Methods for forming the microelectronic device are disclosed. 1. A device comprising:an I/O pad of a substrate;a column on the I/O pad; anda head on the column and extending on all lateral sides of the column, a portion of a surface of the head, aligned with the column in a cross-sectional view of the device, is substantially parallel to a surface of the substrate.2. The device of claim 1 , wherein a plane along the portion of a surface of the head is parallel to a plane along a surface of the head adjacent to the column.3. The device of claim 1 , wherein the head has a rounded side profile with a radius that is approximately equal to the thickness of the head.4. The device of further comprising solder on the head.5. The device of further comprising a barrier layer between the surface of the head and the solder.6. The device of claim 5 , wherein the barrier layer impacts formation of intermetallic compounds between a material of the head and solder.7. The device of claim 1 , wherein the head extends past the column on all lateral sides of the column by a lateral distance that is approximately equal to a vertical thickness of the head.8. The device of further comprising a seed layer between the column ...

Solder bump structure for flip chip package and method for manufacturing the same

A solder bump structure may have a metal stud formed on a chip pad of a semiconductor chip. Surfaces of the metal stud may be plated with a solder. The metal stud may be located on a substrate pad of the substrate. The substrate pad may have a pre-solder applied thereto. After a solder reflow, the solder bump may have a concave shape.

SEMICONDUCTOR COMPONENT, SEMICONDUCTOR-MOUNTED PRODUCT INCLUDING THE COMPONENT, AND METHOD OF PRODUCING THE PRODUCT

A semiconductor component includes a semiconductor package having a mountable face, a bump, and a coating part. The bump is made of first solder and is formed on the mountable face. The coating part formed of a first composition containing solder powder made of second solder, a flux component, and a first thermosetting resin binder coats the top end of the bump. 1. A semiconductor component comprising:a semiconductor package having a mountable face;a bump made of first solder, and formed on the mountable face; anda coating part coating a top end of the bump and composed of a first composition containing solder powder made of second solder, a flux component, and a first thermosetting resin binder.2. The semiconductor component according to claim 1 ,wherein the coating part continuously coats the top end of the bump and at least a part of a side surface of the bump, andwherein an end of the coating part at the side surface of the bump is closer to the mountable face than a position at a height of 40% of a height of the bump from the top end of the bump as a reference.3. The semiconductor component according to claim 2 ,wherein a region of the coating part that coats the to end of the bump is 5 μm or greater in thickness, and thicker than a region that coats the side surface of the bump.4. The semiconductor component according to claim 1 ,wherein the bump is one of a plurality of bumps,wherein the plurality of bumps are formed on the mountable face of the semiconductor package,wherein the coating parts are provided on respective surfaces of the bumps, andwherein the coating parts are separated from one another.5. The semiconductor component according to claim 1 , further comprising an auxiliary coating part coating at least a region of the bump claim 1 , the region being exposed from the coating part claim 1 , and composed of a second composition that contains a second thermosetting resin binder and free from solder powder.6. The semiconductor component according to ...

Semiconductor chip, display panel, and electronic device

A semiconductor chip, a display device or an electronic device includes a substrate, one or more conductive pads disposed on the substrate, and one or more bumps electrically connected to the one or more conductive pads, in which the one or more bumps includes a metal core, a polymer layer disposed over a surface of the metal core, and a conductive coating layer disposed over a surface of the polymer layer and electrically connected to the one or more conductive pads.

Hybrid bonding structures, semiconductor devices having the same, and methods of manufacturing the semiconductor devices

Provided are a hybrid bonding structure, a solder paste composition, a semiconductor device, and a method of manufacturing the semiconductor device. The hybrid bonding structure includes a solder ball and a solder paste bonded to the solder ball. The solder paste includes a transient liquid phase. The transient liquid phase includes a core and a shell on a surface of the core. A melting point of the shell may be lower than a melting point of the core. The core and the shell are configured to form an intermetallic compound in response to the transient liquid phase at least partially being at a temperature that is within a temperature range of about 20° C. to about 190° C.

Alloy diffusion barrier layer

A microelectronic device includes a reflow structure. The reflow structure has a copper-containing member and a solder member, and a barrier layer between them. The barrier layer has metal grains, with a diffusion barrier filler between the metal grains. The metal grains include at least a first metal and a second metal, each selected from nickel, cobalt, lanthanum, and cerium, with each having a concentration in the metal grains of at least 10 weight percent. The diffusion barrier filler includes at least a third metal, selected from tungsten and molybdenum. A combined concentration of tungsten and molybdenum in the diffusion barrier filler is higher than in the metal grains to provide a desired resistance to diffusion of copper. The barrier layer includes 2 weight percent to 15 weight percent of the combined concentration of tungsten, and molybdenum. A bump bond structure and a lead frame package are disclosed.

VISIBILITY EVENT NAVIGATION METHOD AND SYSTEM

A method of visibility event navigation includes receiving, via processing circuitry of a client device, a first visibility event packet from a server, the first visibility event packet including information representing 3D surface elements of an environmental model that are occluded from a first viewcell and not occluded from a second viewcell, the first and second viewcells representing spatial regions of a specified navigational route within a real environment modeled by the environmental model. The method also includes acquiring, surface information representing the visible surfaces of the real environment at a sensor and determining, a position in the real environment by matching the surface information to the visibility event packet information. The method further includes transmitting, the position from the client device to the server and receiving a second visibility event packet from the server if the at least one position is within the specified navigational route. 1receiving, via processing circuitry of a client device, at least one visibility event packet of the one or more visibility event packets from the server;detecting, via the circuitry, surface information representing one or more visible surfaces of the real environment at a sensor in communication with the client device;calculating, via the circuitry, at least one position of the client device in the real environment by matching the surface information to the visibility event packet information corresponding to a first visibility event packet of the one or more visibility event packets;transmitting, via the circuitry, the at least one position from the client device to the server; andreceiving, via the circuitry, at least one second visibility event packet of the one or more visibility event packets when the at least one position is within the navigational route at the client device from the server.. A method of visibility event navigation, including one or more visibility event packets located ...

Nuclear material, semiconductor package and bump electrode forming method

이 핵재료는 Sn과 Bi를 포함하는 (Sn-Bi)계 땜납 합금을 핵(12)의 표면에 도금 피막한 핵재료에 있어서, 땜납 도금층(16) 중의 Bi는 소정 범위의 농도비로 땜납 도금층 중에 분포하고 있는 핵재료이고, Bi의 농도비는 91.7 내지 106.7％의 소정 범위 내에서 땜납 도금층 중에 분포하고 있는 핵재료이다. 땜납 도금층 중의 Bi는 균질이므로, 땜납 도금층 중의 내주측, 외주측을 포함하여 그 전체 영역에 걸쳐서 Bi 농도비가 소정 범위 내에 있다. 이로 인해, 내주측이 외주측보다 빠르게 용융하고, 내주측과 외주측에서 체적 팽창차가 발생하여 핵재료가 튀어 날아가는 사태는 발생하지 않는다. 또한 땜납 도금층 전체가 거의 균일하게 용융하기 때문에, 용융 타이밍의 어긋남에 의해 발생한다고 생각되는 핵재료의 위치 어긋남은 발생하지 않으므로, 위치 어긋남 등에 수반하는 전극간의 단락 등의 우려는 없다.

Mechanisms for forming post-passivation interconnect structure

Mechanisms for forming a semiconductor device are provided. The semiconductor device includes a contact pad over a substrate. The semiconductor device also includes a passivation layer over the substrate and a first portion of the contact pad, and a second portion of the contact pad is exposed through an opening. The semiconductor device further includes a post-passivation interconnect layer over the passivation layer and coupled to the second portion of the contact pad. In addition, the semiconductor device includes a bump over the post-passivation interconnect layer and outside of the opening. The semiconductor device also includes a diffusion barrier layer physically insulating the bump from the post-passivation interconnect layer while electrically connecting the bump to the post-passivation interconnect layer.

SEMI-CONDUCTOR DEVICE WITH HETEROGENIC SOLDER JOINT AND METHOD OF MANUFACTURING IT

Verfahren zum Herstellen einer Halbleitervorrichtung mit einer heterogenen Lötstelle, umfassend: Bereitstellen eines Halbleiterchips, Bereitstellen eines gekoppelten Elements, und Löten des Halbleiterchips an das gekoppelte Element mit einer ersten Lötstelle, wobei die erste Lötstelle umfasst: ein Lötmaterial, das eine erste Metallzusammensetzung umfasst, und eine Beschichtung, die eine zweite Metallzusammensetzung umfasst, die sich von der ersten Metallzusammensetzung unterscheidet, wobei die Beschichtung das Lötmaterial zumindest teilweise bedeckt, wobei die zweite Metallzusammensetzung eine größere Steifigkeit und/oder einen höheren Schmelzpunkt als die erste Metallzusammensetzung aufweist. A method of manufacturing a semiconductor device having a heterogeneous solder joint, comprising: providing a semiconductor chip, providing a coupled element, and soldering the semiconductor chip to the coupled element with a first solder joint, the first solder joint comprising: a solder material comprising a first metal composition, and a coating comprising a second metal composition different from the first metal composition, the coating at least partially covering the brazing material, the second metal composition having a greater rigidity and / or a higher melting point than the first metal composition.

Electroconductive bonding material and method for bonding conductor

본 발명은 도전성 접합 재료를 기판의 전극에 공급하면서 용착시키는 도전성 접합 재료 공급 공정, 및 전자 부품의 단자에 도전성 접합 재료를 한번 용융시켜서 전사하는 전사 공정을 선택할 수 있고, 기판과 전자 부품을 150 ℃ 이하의 저온에서 효율적으로 접합할 수 있는 도전성 접합 재료 및 도체의 접합 방법, 및 반도체 장치의 제조 방법을 제공하는 것을 목적으로 한다. 융점 150 ℃ 이상의 고융점 금속 입자와, 융점 80 ℃ 이상 139 ℃ 이하의 중융점 금속 입자와, 융점 79 ℃ 이하의 저융점 금속 입자로 이루어지는 금속 성분을 함유하는 도전성 접합 재료에 있어서, 상기 금속 성분이 고융점 금속 입자 표면에, 중융점 금속 입자로 형성된 중융점 금속층과, 저융점 금속 입자로 형성된 저융점 금속층을 이 순서로 갖는 다층 금속 입자인 양태 등이 바람직하다.

バンプボンドのための拡張ヘッドピラー

Interconnect structures with polymer core

Embodiments of the present disclosure are directed towards techniques and configurations of interconnect structures having a polymer core in integrated circuit (IC) package assemblies. In one embodiment, an apparatus includes a first die having a plurality of transistor devices disposed on an active side of the first die and a plurality of interconnect structures electrically coupled with the first die, wherein individual interconnect structures of the plurality of interconnect structures have a polymer core, and an electrically conductive material disposed on the polymer core, the electrically conductive material being configured to route electrical signals between the transistor devices of the first die and a second die. Other embodiments may be described and/or claimed.

반도체 칩, 표시패널 및 전자장치

본 발명의 실시예에 의한 반도체 칩은, 기판과, 상기 기판 상에 위치된 적어도 하나의 도전성 패드와, 상기 도전성 패드에 전기적으로 연결되는 적어도 하나의 범프를 구비하며, 상기 범프는, 메탈 코어와, 상기 메탈 코어의 표면을 감싸는 폴리머막과, 상기 폴리머막의 표면을 감싸며 상기 도전성 패드에 전기적으로 연결되는 도전피막을 포함한다.

预封装件和制造半导体封装件的方法以及电子装置

本发明提供了制造半导体封装件的方法。所述方法包括步骤：在衬底的第一表面上形成包括金属的保护层，以覆盖设置在衬底的第一表面上的半导体器件；利用粘合构件将支承衬底附着至保护层；处理与保护层相对的衬底的第二表面，以去除衬底的一部分；以及将支承衬底从衬底拆卸。

Alloy diffusion barrier layer

A microelectronic device (100) includes a reflow structure (110). The reflow structure (110) has a copper-containing member (114) and a solder member (118), and a barrier layer (116) between them. The barrier layer (116) has metal grains (120), with a diffusion barrier filler (122) between the metal grains (120). The metal grains (120) include at least a first metal and a second metal, each selected from nickel, cobalt, lanthanum, and cerium, with each having a concentration in the metal grains of at least 10 weight percent. The diffusion barrier filler (122) includes at least a third metal, selected from tungsten and molybdenum. A combined concentration of tungsten and molybdenum in the diffusion barrier filler (122) is higher than in the metal grains (120) to provide a desired resistance to diffusion of copper. The barrier layer (116) includes 2 weight percent to 15 weight percent of the combined concentration of tungsten, and molybdenum.

具有异质焊接接合部的半导体器件及其制造方法

一种用于制造具有异质焊接接合部的半导体器件的方法包括：提供半导体裸片，提供耦合元件，以及用第一焊接接合部将半导体裸片焊接到耦合元件，第一焊接接合部包括：包括第一金属成分的焊料材料以及包括不同于第一金属成分的第二金属成分的涂层，所述涂层至少部分地覆盖焊料材料，其中，第二金属成分比第一金属成分具有更大的刚度和/或更高的熔点。

Expanded head pillar for bump bonds

A microelectronic device (100) has a bump bond structure (108) including an electrically conductive pillar (109) with an expanded head (111), and solder (112) on the expanded head (111). The electrically conductive pillar (109) includes a column (110) extending from an I/O pad (103) to the expanded head (111). The expanded head (111) extends laterally past the column (110) on at least one side of the electrically conductive pillar (109). In one aspect, the expanded head (111) may have a rounded side profile with a radius approximately equal to a thickness of the expanded head (111), and a flat top surface. In another aspect, the expanded head (111) may extend past the column (110) by different lateral distances in different lateral directions. In a further aspect, the expanded head (111) may have two connection areas for making electrical connections to two separate nodes.

Expanded head pillar for bump bonds

合金拡散障壁層

マイクロ電子デバイス（１００）がリフロー構造（１１０）を含む。リフロー構造（１１０）は、銅含有部材（１１４）、はんだ部材（１１８）、及びそれらの間の障壁層（１１６）を有する。障壁層（１１６）は金属粒子（１２０）を有し、金属粒子（１２０）間に拡散障壁充填材（１２２）を備える。金属粒子（１２０）は、少なくとも第１の金属及び第２の金属を含み、第１の金属及び第２の金属は各々、ニッケル、コバルト、ランタン、及びセリウムから選択され、金属粒子における濃度が少なくとも１０重量パーセントである。拡散障壁充填材（１２２）は、タングステン及びモリブデンから選択される少なくとも第３の金属を含む。拡散障壁充填材（１２２）におけるタングステン及びモリブデンの組み合わせ濃度は、銅の拡散に対する所望の抵抗を提供するために、金属粒子（１２０）内よりも高い。障壁層（１１６）は、２重量パーセント〜１５重量パーセントのタングステン及びモリブデンの混合濃度を含む。

半导体器件及其制造方法

半导体器件及其制造方法。一种半导体器件包括：半导体芯片，其具有通过钝化层暴露的焊盘；凸块柱，其形成在与焊盘相邻的钝化层上方但不与焊盘交叠。半导体芯片还具有焊料层，该焊料层包括焊料凸块部分和焊料焊脚部分，该焊料凸块部分形成在凸块柱上方，该焊料焊脚部分形成在凸块柱的面向焊盘的一侧以覆盖焊盘，并且该焊料焊脚部分将凸块柱与焊盘电联接。

用于凸块接合的扩大头柱

本发明涉及一种微电子装置(100)，其具有凸块接合结构(108)，所述凸块接合结构(108)包含具有扩大头(111)的导电柱(109)及所述扩大头(111)上的焊料(112)。所述导电柱(109)包含从I/O垫(103)延伸到所述扩大头(111)的柱体(110)。所述扩大头(111)在所述导电柱(109)的至少一个侧上横向延伸超过所述柱体(110)。在一个方面中，所述扩大头(111)可具有圆角侧轮廓及平坦顶面，所述圆角侧轮廓具有约等于所述扩大头(111)的厚度的半径。在另一方面中，所述扩大头(111)可在不同横向方向上延伸超过所述柱体(110)达不同横向距离。在另一方面中，所述扩大头(111)可具有用于形成到两个单独节点的电连接的两个连接区。

高共面度的电子元件及其制作方法

一种高共面度的电子元件，包含一主体，其具有一功能电路与一安装面、一具有第一面积的第一电极设置在该安装面上、以及一具有第二面积的第二电极设置在该安装面上，其中该第一面积大于该第二面积，且该第一电极与该第二电极包含一导电层以及至少一第一电镀层覆盖在该导电层上，且该第一电极的导电层厚度小于该第二电极的导电层厚度，且该第一电极的第一电镀层厚度大于该第二电极的第一电镀层厚度。

Electronic component with high coplanarity and method of manufacturing the same

An electronic component with high coplanarity, including a body with a functional circuit and a mounting plane, a first electrode with a first area deposited on the mounting plane, and a second electrode with a second area deposited on the mounting plane, wherein the first area is larger than the second area, and the first electrode and the second electrode includes a conductive layer and at least one first plating layer over the conductive layer, and a thickness of the conductive layer of the first electrode is smaller than a thickness of the conductive layer of the second electrode, and a thickness of the first plating layer of the first electrode is larger than a thickness of the first plating layer of the second electrode.

高共面度的電子元件及其製作方法

一種高共面度的電子元件，包含一主體，其具有一功能電路與一安裝面、一具有第一面積的第一電極設置在該安裝面上、以及一具有第二面積的第二電極設置在該安裝面上，其中該第一面積大於該第二面積，且該第一電極與該第二電極包含一導電層以及至少一第一電鍍層覆蓋在該導電層上，且該第一電極的導電層厚度小於該第二電極的導電層厚度，且該第一電極的第一電鍍層厚度大於該第二電極的第一電鍍層厚度。

合金扩散阻挡层

一种微电子装置(100)包括回流结构(110)。回流结构(110)具有含铜构件(114)和焊料构件(118)以及在它们之间的阻挡层(116)。阻挡层(116)具有金属颗粒(120)，和在金属颗粒(120)之间的扩散阻挡填料(122)。金属颗粒(120)至少包含第一金属和第二金属，该第一金属和第二金属各自选自镍、钴、镧和铈，其中该第一金属和第二金属各自在金属颗粒中的浓度为至少10重量％。扩散阻挡填料(122)至少包含第三金属，该第三金属选自钨和钼。钨和钼在扩散阻挡填料(122)中的组合浓度高于在金属颗粒(120)中的组合浓度，以提供期望的铜扩散阻力。阻挡层(116)包含的钨和钼的组合浓度为2重量％至15重量％。

Semiconductor Device and Method of Forming Bump Structure with Insulating Buffer Layer to Reduce Stress on Semiconductor Wafer

A semiconductor wafer has a plurality of semiconductor die with contact pads for electrical interconnect. An insulating layer is formed over the semiconductor wafer. A bump structure is formed over the contact pads. The bump structure has a buffer layer formed over the insulating layer and contact pad. A portion of the buffer layer is removed to expose the contact pad and an outer portion of the insulating layer. A UBM layer is formed over the buffer layer and contact pad. The UBM layer follows a contour of the buffer layer and contact pad. A ring-shaped conductive pillar is formed over the UBM layer using a patterned photoresist layer filled with electrically conductive material. A conductive barrier layer is formed over the ring-shaped conductive pillar. A bump is formed over the conductive barrier layer. The buffer layer reduces thermal and mechanical stress on the bump and contact pad.

高共面度的电子元件及其制作方法

一种高共面度的电子元件，包含一主体，其具有一功能电路与一安装面、一具有第一面积的第一电极设置在该安装面上、以及一具有第二面积的第二电极设置在该安装面上，其中该第一面积大于该第二面积，且该第一电极与该第二电极包含一导电层以及至少一第一电镀层覆盖在该导电层上，且该第一电极的导电层厚度小于该第二电极的导电层厚度，且该第一电极的第一电镀层厚度大于该第二电极的第一电镀层厚度。

混合接合结构、焊膏组成物、半导体器件及其制造方法

提供了混合接合结构、焊膏组成物、半导体器件和制造该半导体器件的方法。该混合接合结构包括焊球和接合到焊球的焊膏。焊膏包括瞬间液相。瞬间液相包括核和在核的表面上的壳。壳的熔点可以低于核的熔点。核和壳配置为响应于瞬间液相至少部分地处于在约20℃至约190℃的温度范围内的温度而形成金属间化合物。

具有异质焊接接合部的半导体器件及其制造方法

一种用于制造具有异质焊接接合部的半导体器件的方法包括：提供半导体裸片，提供耦合元件，以及用第一焊接接合部将半导体裸片焊接到耦合元件，第一焊接接合部包括：包括第一金属成分的焊料材料以及包括不同于第一金属成分的第二金属成分的涂层，所述涂层至少部分地覆盖焊料材料，其中，第二金属成分比第一金属成分具有更大的刚度和/或更高的熔点。

多芯片封装件及其制造方法

本发明公开一种多芯片封装件及其制造方法。多芯片封装件包括：中介层，包括布线结构与电连接至布线结构的中介通路；多个半导体芯片，位于中介层的第一表面上且经由中介层而彼此电连接；包封体，位于中介层的第一表面上且包封多个半导体芯片的至少部分；以及重配置线路结构，位于中介层的与第一表面相对的第二表面上，其中所述多个半导体芯片至少经由所述中介层而电连接至所述重配置线路结构。

用于凸块接合的扩大头柱

本发明涉及一种微电子装置(100)，其具有凸块接合结构(108)，所述凸块接合结构(108)包含具有扩大头(111)的导电柱(109)及所述扩大头(111)上的焊料(112)。所述导电柱(109)包含从I/O垫(103)延伸到所述扩大头(111)的柱体(110)。所述扩大头(111)在所述导电柱(109)的至少一个侧上横向延伸超过所述柱体(110)。在一个方面中，所述扩大头(111)可具有圆角侧轮廓及平坦顶面，所述圆角侧轮廓具有约等于所述扩大头(111)的厚度的半径。在另一方面中，所述扩大头(111)可在不同横向方向上延伸超过所述柱体(110)达不同横向距离。在另一方面中，所述扩大头(111)可具有用于形成到两个单独节点的电连接的两个连接区。

合金扩散阻挡层

一种微电子装置(100)包括回流结构(110)。回流结构(110)具有含铜构件(114)和焊料构件(118)以及在它们之间的阻挡层(116)。阻挡层(116)具有金属颗粒(120)，和在金属颗粒(120)之间的扩散阻挡填料(122)。金属颗粒(120)至少包含第一金属和第二金属，该第一金属和第二金属各自选自镍、钴、镧和铈，其中该第一金属和第二金属各自在金属颗粒中的浓度为至少10重量％。扩散阻挡填料(122)至少包含第三金属，该第三金属选自钨和钼。钨和钼在扩散阻挡填料(122)中的组合浓度高于在金属颗粒(120)中的组合浓度，以提供期望的铜扩散阻力。阻挡层(116)包含的钨和钼的组合浓度为2重量％至15重量％。

封装结构及组件连接的方法

本揭露公开一种封装结构及组件连接的方法，其中所述封装结构包括第一基底，所述第一基底包含第一线路与连接至所述第一线路的至少一第一接点；第二基底，所述第二基底包含第二线路与连接至所述第二线路的至少一第二接点，所述至少一第一接点与所述至少一第二接点彼此部分物理性接触或彼此部分化学性界面反应接触；以及至少一第三接点，所述至少一第三接点包围所述至少一第一接点与所述至少一第二接点，且所述第一基底至少通过所述至少一第一接点与所述至少一第二接点与所述第二基底电连接。

Semiconductor device and method of forming bump structure with insulating buffer layer to reduce stress on semiconductor wafer

A semiconductor wafer has a plurality of semiconductor die with contact pads for electrical interconnect. An insulating layer is formed over the semiconductor wafer. A bump structure is formed over the contact pads. The bump structure has a buffer layer formed over the insulating layer and contact pad. A portion of the buffer layer is removed to expose the contact pad and an outer portion of the insulating layer. A UBM layer is formed over the buffer layer and contact pad. The UBM layer follows a contour of the buffer layer and contact pad. A ring-shaped conductive pillar is formed over the UBM layer using a patterned photoresist layer filled with electrically conductive material. A conductive barrier layer is formed over the ring-shaped conductive pillar. A bump is formed over the conductive barrier layer. The buffer layer reduces thermal and mechanical stress on the bump and contact pad.

Pre-package and methods of manufacturing semiconductor package and electronic device using the same

Methods of fabricating semiconductor packages are provided. One of the methods includes forming a protection layer including metal on a first surface of a substrate to cover a semiconductor device disposed on the first surface of the substrate, attaching a support substrate to the protection layer by using an adhesive member, processing a second surface of the substrate opposite to the protection layer to remove a part of the substrate, and detaching the support substrate from the substrate.

Light-emitting device and displayer

The disclosure provides a light-emitting device and a displayer. Herein, the light-emitting device includes a substrate, a light-emitting chip, a first light-transmitting layer, a second light-transmitting layer and a nano coating. The light transmittance of the second light-transmitting layer is greater than the light transmittance of the first light-transmitting layer. A reference surface corresponding to the light-emitting chip is arranged above the substrate, and the reference surface is higher than the bottom surface of the light-emitting chip and not higher than the top surface of the light-emitting chip. The first light-transmitting layer covers the surface of the light-emitting chip below the reference surface, and the second light-transmitting layer covers the surface of the light-emitting chip above the reference surface. The nano coating covers the outer surface of the first light-transmitting layer, the outer surface of the second light-transmitting layer and the side surface of the substrate.

半导体器件及其制造方法

半导体器件及其制造方法。一种半导体器件包括：半导体芯片，其具有通过钝化层暴露的焊盘；凸块柱，其形成在与焊盘相邻的钝化层上方但不与焊盘交叠。半导体芯片还具有焊料层，该焊料层包括焊料凸块部分和焊料焊脚部分，该焊料凸块部分形成在凸块柱上方，该焊料焊脚部分形成在凸块柱的面向焊盘的一侧以覆盖焊盘，并且该焊料焊脚部分将凸块柱与焊盘电联接。

Flip chip assembly and process with sintering material on metal bumps

A method is disclosed of fabricating a microelectronic package comprising a substrate overlying the front face of a microelectronic element. A plurality of metal bumps project from conductive elements of the substrate towards the microelectronic element, the metal bumps having first ends extending from the conductive elements, second ends remote from the conductive elements, and lateral surfaces extending between the first and second ends. The metal bumps can be wire bonds having first and second ends attached to a same conductive pad of the substrate. A conductive matrix material contacts at least portions of the lateral surfaces of respective ones of the metal bumps and joins the metal bumps with contacts of the microelectronic element.