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Небесная энциклопедия

Космические корабли и станции, автоматические КА и методы их проектирования, бортовые комплексы управления, системы и средства жизнеобеспечения, особенности технологии производства ракетно-космических систем

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Мониторинг СМИ

Мониторинг СМИ и социальных сетей. Сканирование интернета, новостных сайтов, специализированных контентных площадок на базе мессенджеров. Гибкие настройки фильтров и первоначальных источников.

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Применить Всего найдено 78956. Отображено 100.
05-01-2012 дата публикации

Active energy ray-curable pressure-sensitive adhesive for re-release and dicing die-bonding film

Номер: US20120003470A1
Автор: Chie Kitano, Hironao OTAKE, Katsuhiko Kamiya, Masatsugu KOSO, Mika Okada, Shuhei Murata, Takeshi Matsumura, Tomokazu Takahashi
Принадлежит: Nitto Denko Corp

Provided is an active energy ray-curable pressure-sensitive adhesive for re-release, which has a small influence on an environment or a human body, can be easily handled, can largely change its pressure-sensitive adhesiveness before and after irradiation with an active energy ray, and can express high pressure-sensitive adhesiveness before the irradiation with the active energy ray and express high releasability after the irradiation with the active energy ray. The active energy ray-curable pressure-sensitive adhesive for re-release includes an active energy ray-curable polymer (P), in which the polymer (P) includes one of a polymer obtained by causing a carboxyl group-containing polymer (P3) and an oxazoline group-containing monomer (m3) to react with each other, and a polymer obtained by causing an oxazoline group-containing polymer (P4) and a carboxyl group-containing monomer (m2) to react with each other.

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Номер записи: 1
11-07-2017 дата публикации

Выводная рамка мощной интегральной микросхемы

Номер: RU0000172495U1
Автор: Александр Владимирович Минин, Евгений Викторович Абашин, Константин Львович Афанасьев, Николай Александрович Брюхно
Принадлежит: Закрытое акционерное общество "ГРУППА КРЕМНИЙ ЭЛ"

Использование: для создания выводных рамок мощных интегральных схем. Сущность полезной модели заключается в том, что выводная рамка мощной интегральной микросхемы содержит теплорастекатель с участком присоединения кристалла с рифлением, и траверсы для присоединения гибких выводов, рифление теплорастекателя выполено виде сетки из канавок, расположенных в двух взаимоперпендикулярных направлениях с шагомпричем:где- наибольший диаметр гибкого вывода, соединяющий контактную площадку с теплорастекателем,наименьший линейный размер кристалла. Технический результат: обеспечение возможности повышения качества мощной микросхемы. 2 ил. Ц 1 172495 ко РОССИЙСКАЯ ФЕДЕРАЦИЯ (19) ФЕДЕРАЛЬНАЯ СЛУЖБА ПО ИНТЕЛЛЕКТУАЛЬНОЙ СОБСТВЕННОСТИ 27; 22, 7 р», 77 8? аа) ил < < $ >< оо п РЦ ‘’ (50) МПК НО. 23/495 (2006.01) (12) ОПИСАНИЕ ПОЛЕЗНОЙ МОДЕЛИ К ПАТЕНТУ (21)(22) Заявка: 2017109009, 17.03.2017 (24) Дата начала отсчета срока действия патента: 17.03.2017 Дата регистрации: 11.07.2017 Приоритет(ы): (22) Дата подачи заявки: 17.03.2017 (45) Опубликовано: 11.07.2017 Бюл. № 20 Адрес для переписки: 241037, г. Брянск, ул. Красноармейская, 103, ЗАО "ГРУППА КРЕМНИЙ ЭЛ", Технический отдел (72) Автор(ы): Абашин Евгений Викторович (КО), Афанасьев Константин Львович (КО), Брюхно Николай Александрович (КО), Минин Александр Владимирович (КО) (73) Патентообладатель(и): Закрытое акционерное общество "ГРУ1ИТА КРЕМНИЙ ЭЛ" (ВО) (56) Список документов, цитированных в отчете о поиске: ВО 2040075 С1, 20.07.1995. ВЧ 2222074 СТ, 20.01.2004. ВО 2193260 СТ, 20.11.2002. 05 5299091 АТ, 29.03.1994. 05 5633528 А1, 27.05.1997 . (54) ВЫВОДНАЯ РАМКА МОЩНОЙ ИНТЕГРАЛЬНОЙ МИКРОСХЕМЫ (57) Реферат: Использование: для создания выводных рамок мощных интегральных схем. Сущность полезной модели заключается в том, что выводная рамка мощной интегральной микросхемы содержит теплорастекатель с участком присоединения кристалла с рифлением, и траверсы для присоединения гибких выводов, рифление теплорастекателя выполено виде сетки из канавок, ...

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Номер записи: 2
12-01-2012 дата публикации

Method for molecular adhesion bonding with compensation for radial misalignment

Номер: US20120006463A1
Автор: Gweltaz Gaudin
Принадлежит: Soitec SA

A method for bonding a first wafer on a second wafer by molecular adhesion, where the wafers have an initial radial misalignment between them. The method includes bringing the two wafers into contact so as to initiate the propagation of a bonding wave between the two wafers while a predefined bonding curvature is imposed on at least one of the two wafers during the contacting step as a function of the initial radial misalignment.

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Номер записи: 3
12-01-2012 дата публикации

Wiring board and method for manufacturing the same

Номер: US20120006592A1
Автор: Makoto Terui, Shigeru Yamada, Shinji OUCHI, Yoshinori Shizuno
Принадлежит: Ibiden Co Ltd

A wiring board including a first insulation layer, a conductive pattern formed on the first insulation layer, a second insulation layer formed on the conductive pattern and the first insulation layer and having an opening portion exposing at least a portion of the conductive pattern, and a connection conductor formed in the opening portion of the second insulation layer such that the connection conductor is positioned on the portion of the conductive pattern. The connection conductor has a tip portion which protrudes from a surface of the second insulation layer and which has a tapered side surface tapering toward an end of the tip portion.

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Номер записи: 4
12-01-2012 дата публикации

Method for Reducing Chip Warpage

Номер: US20120007220A1
Автор: Chun-Ren Cheng, Jiou-Kang Lee, Jung-Huei Peng, Shang-Ying Tsai, Ting-Hau Wu
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

A method of forming an integrated circuit structure including providing a wafer comprising a front surface and a back surface, wherein the wafer comprises a chip; forming an opening extending from the back surface into the chip; filling an organic material in the opening, wherein substantially no portion of the organic material is outside of the opening and on the back surface of the wafer; and baking the organic material to cause a contraction of the organic material.

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Номер записи: 5
12-01-2012 дата публикации

Semiconductor device

Номер: US20120007224A1
Автор: Hajime Hasebe, Tadatoshi Danno, Yukihiro Satou
Принадлежит: Hitachi Hokkai Semiconductor Ltd, Renesas Electronics Corp

In a non-leaded type semiconductor device, a tab, tab suspension leads, and other leads are exposed to one surface of a seal member. A semiconductor element is positioned within the seal member and fixed to a surface of the tab with an adhesive. The tab is formed larger than the semiconductor element so that outer peripheral edges of the tab are positioned outside outer peripheral edges of the semiconductor element. A groove is formed in the tab surface portion positioned between the area to which the semiconductor element is fixed and wire connection areas to which the wires are connected, the groove being formed so as to surround the semiconductor element fixing area, thereby preventing peeling-off between the tab to which the semiconductor element is fixed and the resin which constitutes the package.

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Номер записи: 6
12-01-2012 дата публикации

Microelectronic packages with dual or multiple-etched flip-chip connectors

Номер: US20120007232A1
Автор: Belgacem Haba
Принадлежит: TESSERA RESEARCH LLC

A packaged microelectronic element includes a microelectronic element having a front surface and a plurality of first solid metal posts extending away from the front surface. A substrate has a major surface and a plurality of conductive elements exposed at the major surface and joined to the first solid metal posts. In particular examples, the conductive elements can be bond pads or can be second posts having top surfaces and edge surfaces extending at substantial angles away therefrom. Each first solid metal post includes a base region adjacent the microelectronic element and a tip region remote from the microelectronic element, the base region and tip region having respective concave circumferential surfaces. Each first solid metal post has a horizontal dimension which is a first function of vertical location in the base region and which is a second function of vertical location in the tip region.

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Номер записи: 7
12-01-2012 дата публикации

Semiconductor device and package

Номер: US20120007236A1
Автор: Jin Ho Bae
Принадлежит: Hynix Semiconductor Inc

A semiconductor device includes a semiconductor substrate having an upper surface, a lower surface, a first side and a second side, wherein the lower surface has a slope so that the first side is thicker than the second side, and a circuit pattern including a bonding pad on the upper surface of the semiconductor substrate.

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Номер записи: 8
12-01-2012 дата публикации

Resin-Encapsulated Semiconductor Device

Номер: US20120007247A1
Автор: Motoharu Haga, Shoji Yasunaga, Yasumasa Kasuya
Принадлежит: ROHM CO LTD

A resin-sealed semiconductor device includes a semiconductor chip including a silicon substrate; a die pad on which the semiconductor chip is secured via a solder layer; a sealing resin layer sealing the semiconductor chip; and lead terminals connected electrically with the semiconductor chip. One end portion of the lead terminals is covered by the sealing resin layer. The die pad and the lead terminals are formed of copper and a copper alloy, and the die pad is formed with a thickness larger than a thickness of the lead terminals, which is a thickness of 0.25 mm or more.

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Номер записи: 9
12-01-2012 дата публикации

Power semiconductor module and fabrication method

Номер: US20120009733A1
Автор: Eladio Clemente Delgado, Ernest Wayne Balch, Kevin Matthew Durocher, Paul Alan McConnelee, Raymond Albert Fillion, Richard Alfred Beaupre, Stephen Daley Arthur
Принадлежит: General Electric Co

A power semiconductor module includes: an interconnect layer including an electrical conductor patterned on a dielectric layer, the electrical conductor including a power coupling portion having a thickness sufficient to carry power currents and a control coupling portion having a thickness thinner than that of the power coupling portion; and a semiconductor power device physically coupled to the interconnect layer and electrically coupled to the power coupling portion of the electrical conductor.

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Номер записи: 10
19-01-2012 дата публикации

Conductive Sidewall for Microbumps

Номер: US20120012998A1
Автор: Arvind Chandrasekaran, Christine S. Hay-Riege, Shiqun Gu
Принадлежит: Qualcomm Inc

Electromigration in microbump connections causes voids in the microbumps, which reduces the lifetime of an integrated circuit containing the microbump. Electromigration lifetime may be increased in microbumps by forming a copper shell around the solder. The copper shell of one microbump contacts the copper shell of a second microbump to enclose the solder of the microbump connection. The copper shell allows higher current densities through the microbump. Thus, smaller microbumps may be manufactured on a smaller pitch without suffering failure from electromigration. Additionally, the copper shell reduces shorting or bridging between microbump connections on a substrate.

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Номер записи: 11
19-01-2012 дата публикации

Semiconductor-encapsulating adhesive, semiconductor-encapsulating film-form adhesive, method for producing semiconductor device, and semiconductor device

Номер: US20120012999A1
Автор: Kazutaka Honda, Tetsuya Enomoto, Yuuki Nakamura
Принадлежит: Hitachi Chemical Co Ltd

The present invention relates to a semiconductor-encapsulating adhesive, a semiconductor-encapsulating film-form adhesive, a method for producing a semiconductor device, and a semiconductor device. The present invention provides a semiconductor-encapsulating adhesive comprising (a) an epoxy resin, and (b) a compound formed of an organic acid reactive with an epoxy resin and a curing accelerator.

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Номер записи: 12
19-01-2012 дата публикации

Stacked semiconductor package and method of fabricating the same

Номер: US20120013026A1
Автор: Won-Gil HAN
Принадлежит: SAMSUNG ELECTRONICS CO LTD

A stacked semiconductor package and an electronic system, the stacked semiconductor package including a plurality of semiconductor chips, a set of the semiconductor chips being stacked such that an extension region of a top surface of each semiconductor chip of the set extends beyond an end of a semiconductor chip stacked thereon to form a plurality of extension regions; and a plurality of protection layers on the extension regions and on an uppermost semiconductor chip of the plurality of semiconductor chips.

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Номер записи: 13
19-01-2012 дата публикации

Stacked microelectronic packages having at least two stacked microelectronic elements adjacent one another

Номер: US20120013028A1
Автор: Belgacem Haba, Ilyas Mohammed
Принадлежит: Tessera LLC

A microelectronic assembly includes first and second microelectronic elements. Each of the microelectronic elements has oppositely-facing first and second surfaces and edges bounding the surfaces. The first microelectronic element is disposed on the second microelectronic element with the second surface of the first microelectronic element facing toward the first surface of the second microelectronic element. The first microelectronic element preferably extends beyond at least one edge of the second microelectronic element and the second microelectronic element preferably extends beyond at least one edge of the first microelectronic element. A first edge of the first microelectronic element has a length that is smaller than a first edge of the second microelectronic element. A second edge of the first microelectronic element has a length that is greater than the second edge of the second microelectronic element.

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Номер записи: 14
26-01-2012 дата публикации

Substrate for semiconductor element, method for manufacturing substrate for semiconductor element, and semiconductor device

Номер: US20120018867A1
Автор: Junko Toda, Susumu Maniwa, Takehito Tsukamoto
Принадлежит: Toppan Printing Co Ltd

Provided is a manufacturing method of a semiconductor element substrate including: a step of forming a first photoresist pattern on a first surface of a metallic plate, to form a semiconductor element mounting part, a semiconductor element electrode connection terminal, a wiring, an outer frame part, and a slit; a step of forming a second photoresist pattern on the second surface of the metallic plate; a step of forming the slit by half etching to connect the metallic chip with a four corners of the outer frame part; a step of forming a plurality of concaved parts on the second surface of the metallic plate; a step of forming a resin layer by injecting a resin to the plurality of concaved parts; and a step of etching the first surface of the metallic plate and forming the semiconductor element electrode connection terminal and the outer frame.

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Номер записи: 15
02-02-2012 дата публикации

Laminated semiconductor substrate, laminated chip package and method of manufacturing the same

Номер: US20120025354A1
Автор: Atsushi Iijima, Hiroyuki Ito, Yoshitaka Sasaki
Принадлежит: Headway Technologies Inc, SAE Magnetics HK Ltd

In a laminated semiconductor substrate, a plurality of semiconductor substrates are laminated. Each of the semiconductor substrate has a plurality of scribe-groove parts formed along scribe lines. Further, each of the semiconductor substrate has a plurality of device regions insulated from each other and has a semiconductor device formed therein. Further, an uppermost substrate and a lowermost substrate have an electromagnetic shielding layer formed using a ferromagnetic body. The electromagnetic shielding layer is formed in a shielding region except the extending zone. The extending zone is set a part which the wiring electrode crosses, in a peripheral edge part of the device region.

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Номер записи: 16
02-02-2012 дата публикации

Chip package and fabricating method thereof

Номер: US20120025387A1
Автор: Kuo-Ching Chang, Tzu-Han Lin, Wu-Cheng Kuo
Принадлежит: Individual

A chip package and a fabrication method thereof are provided. The chip package includes a substrate and a chip disposed over the substrate. A solder layer is disposed between the chip and the substrate. A conductive pad is disposed between the solder layer and the substrate, wherein the conductive pad includes a first portion disposed under the solder layer, a second portion disposed away from the first portion and a connective portion disposed between the first portion and the second portion. The connective portion has a width which is narrower than a width of the first portion along a first direction perpendicular to a second direction extending from the first portion to the connective portion.

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Номер записи: 17
02-02-2012 дата публикации

Power Semiconductor Module, Method for Producing a Power Semiconductor Module and a Housing Element for a Power Semiconductor Module

Номер: US20120025393A1
Автор: Andre Roehrig, Olaf Kirsch, Peter Kanschat, Thilo Stolze
Принадлежит: INFINEON TECHNOLOGIES AG

A power semiconductor module includes a housing element into which one or more connecting lugs are inserted. Each connecting lug has a foot region on the topside of which one or more bonding connections can be produced. In order to fix the foot regions, press-on elements are provided, which press against the end of the connecting lug.

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Номер записи: 18
02-02-2012 дата публикации

Film for flip chip type semiconductor back surface, dicing tape-integrated film for semiconductor back surface, process for producing semiconductor device, and flip chip type semiconductor device

Номер: US20120025400A1
Автор: Fumiteru Asai, Goji Shiga, Naohide Takamoto, Yusuke Komoto
Принадлежит: Nitto Denko Corp

The present invention relates to a film for flip chip type semiconductor back surface to be formed on a back surface of a semiconductor element flip chip-connected onto an adherend, in which the film for flip chip type semiconductor back surface before thermal curing has, at the thermal curing thereof, a volume contraction ratio within a range of 23° C. to 165° C. of 100 ppm/° C. to 400 ppm/° C.

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Номер записи: 19
02-02-2012 дата публикации

Method and electrostatic transfer stamp for transferring semiconductor dice using electrostatic transfer printing techniques

Номер: US20120027557A1
Автор: Ian Ashdown, Ingo Speier
Принадлежит: Cooledge Lighting Inc

A transfer stamp that can be charged with a spatial pattern of electrostatic charge for picking up selected semiconductor dice from a host substrate and transferring them to a target substrate. The stamp may be bulk charged and then selectively discharged using irradiation through a patterned mask. The technique may also be used to electrostatically transfer selected semiconductor dice from a host substrate to a target substrate.

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Номер записи: 20
02-02-2012 дата публикации

Methods of operating electronic devices, and methods of providing electronic devices

Номер: US20120028582A1
Автор: Patrick W. Tandy
Принадлежит: Round Rock Research LLC

Some embodiments include a method disposing an integrated circuit die within a housing, the integrated circuit die having integrated circuitry formed thereon, the integrated circuitry including first transponder circuitry configured to transmit and receive radio frequency signals, wherein the integrated circuit die is void of external electrical connections for anything except power supply external connections; and disposing second transponder circuitry, discrete from the first transponder circuitry, within the housing, the second transponder circuitry being configured to transmit and receive radio frequency signals, wherein the first and second transponder circuitry are configured to establish wireless communication between one another within the housing, the second transponder circuitry being disposed within 24 inches of the first transponder circuitry within the housing.

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Номер записи: 21
09-02-2012 дата публикации

Gas delivery system for reducing oxidation in wire bonding operations

Номер: US20120031877A1
Автор: Gary S. Gillotti, Peter J. Van Emmerik, Stanley Szczesniak
Принадлежит: Kulicke and Soffa Industries Inc

A wire bonding machine is provided. The wire bonding machine includes a bonding tool and an electrode for forming a free air ball on an end of a wire extending through the bonding tool where the free air ball is formed at a free air ball formation area of the wire bonding machine. The wire bonding machine also includes a bond site area for holding a semiconductor device during a wire bonding operation. The wire bonding machine also includes a gas delivery mechanism configured to provide a cover gas to: (1) the bond site area whereby the cover gas is ejected through at least one aperture of the gas delivery mechanism to the bond site area, and (2) the free air ball formation area.

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Номер записи: 22
09-02-2012 дата публикации

Packaged light emitting diodes including phosphor coating and phosphor coating systems

Номер: US20120032220A1
Автор: Mitchell Jackson, Nathaniel O. Cannon
Принадлежит: Cree Inc

Light emitting structures are disclosed that can include a semiconductor light emitting diode (LED) that includes a p-n junction active layer. A first layer can include a binder material having a thickness that is less than about 1000 μm, wherein the first layer is directly on the LED. A second layer can include phosphor particles, where the second layer can have a thickness that is less than about 1000 μm and can be directly on the first layer so that the first layer is between the LED and the second layer.

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Номер записи: 23
09-02-2012 дата публикации

Semiconductor device and method for producing such a device

Номер: US20120032295A1
Автор: Carsten Von Koblinski, Francisco Javier Santos Rodriguez, Friedrich Kroener
Принадлежит: INFINEON TECHNOLOGIES AG

A semiconductor device and method for producing such a device is disclosed. One embodiment provides a semiconductor functional wafer having a first and second main surface. Component production processes are performed for producing a component functional region at the first main surface, wherein the component production processes produce an end state that is stable up to at least a first temperature. A carrier substrate is fitted to the first main surface. Access openings are produced to the first main surface. At least one further component production process is performed for producing patterned component functional regions at the first main surface of the functional wafer in the access openings. The end state produced in this process is stable up to a second temperature, which is less than the first temperature.

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Номер записи: 24
09-02-2012 дата публикации

Integrated circuit packaging system with die paddle and method of manufacture thereof

Номер: US20120032315A1
Автор: Arnel Senosa Trasporto, Byung Tai Do, Linda Pei Ee CHUA
Принадлежит: Individual

A method of manufacture of an integrated circuit packaging system includes: providing a package paddle having a single integral structure with a paddle central portion surrounded by a paddle peripheral portion; forming a terminal adjacent the package paddle; mounting an integrated circuit over the paddle central portion; and forming an encapsulation over the integrated circuit and the terminal, the encapsulation free of delamination with the encapsulation directly on the paddle peripheral portion.

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Номер записи: 25
09-02-2012 дата публикации

Semiconductor device

Номер: US20120032325A1
Автор: Osamu Miyata, Shingo Higuchi
Принадлежит: ROHM CO LTD

There is provided a semiconductor device with which stress can be prevented from locally concentrating on an external connecting terminal on a post and thus damages of the external connecting terminal can be prevented. The semiconductor device includes a semiconductor chip, a sealing resin layer stacked on a surface of the semiconductor chip, and the post which penetrates the sealing resin layer in a stacking direction of the semiconductor chip and the sealing resin layer, protrudes from the sealing resin layer, and has a periphery of the protruding portion opposedly in contact with a surface of the sealing resin layer in the stacking direction.

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Номер записи: 26
09-02-2012 дата публикации

Circuit substrate and manufacturing method thereof and package structure and manufacturing method thereof

Номер: US20120032331A1
Автор: Chih-Cheng LEE
Принадлежит: Advanced Semiconductor Engineering Inc

A circuit substrate includes the following elements. A conductive layer and a dielectric layer are disposed on an inner circuit structure in sequence, and a plurality of conductive blind vias are embedded in the dielectric layer and connected to a portion of the conductive layer. A plating seed layer is disposed between each of the first blind vias and the first conductive layer. Another conductive layer is disposed on the dielectric layer, wherein a portion of the another conductive layer is electrically connected to the conductive layer through the conductive blind vias. A third plating seed layer is disposed between the third conductive layer and each of the first blind vias and on the first dielectric layer.

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Номер записи: 27
16-02-2012 дата публикации

Surface-modified silicate luminophores

Номер: US20120037850A1
Автор: Chung Hoon Lee, Detlef Starick, Gundula Roth, Walter Tews
Принадлежит: Litec LLL GmbH, Seoul Semiconductor Co Ltd

A surface-modified silicate luminophore includes a silicate luminophore and a coating includes at least one of (a) a fluorinated coating including a fluorinated inorganic agent, a fluorinated organic agent, or a combination of fluorinated inorganic and organic agents, the fluorinated coating generating hydrophobic surface sites and (b) a combination of the fluorinated coating and at least one moisture barrier layer. The moisture barrier layer includes MgO, Al 2 O 3 , Y 2 O 3 , La 2 O 3 , Gd 2 O 3 , Lu 2 O 3 , and SiO 2 or the corresponding precursors, and the coating is disposed on the surface of the silicate luminophore.

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Номер записи: 28
16-02-2012 дата публикации

Light emitting diode

Номер: US20120037939A1
Автор: Youji Urano
Принадлежит: Panasonic Corp, Panasonic Electric Works Co Ltd

A light emitting diode comprises a LED chip, a package in which the LED chip is housed, and a connection electrode electrically connected to an element electrode with which the LED chip is provided. The package is a laminated body comprising at least a submount substrate and a frame body, and the LED chip is fixedly-mounted on one surface of the submount substrate, and the frame body is laminated on the one surface of the submount substrate and is provided with a through-hole in which the LED chip is stored. The connection electrode is formed on at least either the one surface of the submount substrate or one surface of the frame body facing toward a light irradiation direction, while being exposed in the light irradiation direction. Therefore, the light emitting diode can improve both heat dissipation performance and density of LED placement together.

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Номер записи: 29
16-02-2012 дата публикации

Method for molecular adhesion bonding at low pressure

Номер: US20120038027A1
Автор: Marcel Broekaart
Принадлежит: Soitec SA

The present invention relates to a method for molecular adhesion bonding between at least a first wafer and a second wafer involving aligning the first and second wafers, placing the first and second wafers in an environment having a first pressure (P 1 ) greater than a predetermined threshold pressure; bringing the first wafer and the second wafer into alignment and contact; and initiating the propagation of a bonding wave between the first and second wafer after the wafers are aligned and in contact by reducing the pressure within the environment to a second pressure (P 2 ) below the threshold pressure. The invention also relates to the three-dimensional composite structure that is obtained by the described method of adhesion bonding.

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Номер записи: 30
16-02-2012 дата публикации

Stitch bump stacking design for overall package size reduction for multiple stack

Номер: US20120038059A1
Автор: Foong Yue Ho, Kevin Guan, Koo Eng LUON, Lai Nguk Chin, Sally Foong, Wong Kwet Nam
Принадлежит: Individual

A method for die stacking is disclosed. In one embodiment a first die is formed overlying a substrate. A first wire is bonded to the first die and to a bond finger of the substrate, wherein the first wire is bonded to the bond finger with a first bond. A first stitch bump is formed overlying the first stitch bond, wherein the first stitch bump is formed from a molten ball of conductive material. A second die is formed overlying the first die. A second wire is bonded to the second die and to the first stitch bump, wherein the second wire is bonded to the first stitch bump with a second bond.

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Номер записи: 31
23-02-2012 дата публикации

Image Sensor Package with Dual Substrates and the Method of the Same

Номер: US20120043635A1
Автор: Wen-Kun Yang
Принадлежит: King Dragon International Inc

The image sensor package with dual substrates comprises a first substrate with a die receiving opening and a plurality of first through hole penetrated through the first substrate; a second substrate with a die opening window and a plurality of second through hole penetrated through the second substrate, formed on the first substrate. A part of the second wiring pattern is coupled to a part of the third wiring pattern; an image die having conductive pads and sensing array received within the die receiving opening and the sensing array being exposed by the die opening window; and a through hole conductive material refilled into the plurality of second through hole, some of the plurality of second through hole coupling to the conductive pads of the image sensor.

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Номер записи: 32
23-02-2012 дата публикации

Packaging Integrated Circuits

Номер: US20120043650A1
Автор: Liang Kng Ian Koh, Richard Mangapul Sinaga
Принадлежит: INFINEON TECHNOLOGIES AG

An integrated circuit 15 is placed onto a lead frame 101 having lead fingers 109 of substantially constant thickness along their length. Wires are formed from the lead fingers 109 to corresponding electrical contacts the integrated circuit. Following the wire bonding process, the thickness of the tips of the lead fingers 109 is reduced by a laser process, to form tips of reduced thickness desirable for a subsequent moulding operation. Thus, at the time of the wire bonding the tips of the fingers 109 need not have a gap beneath them, so that more secure wire bonds to the lead fingers 109 can be formed.

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Номер записи: 33
23-02-2012 дата публикации

Mechanisms for forming copper pillar bumps using patterned anodes

Номер: US20120043654A1
Автор: Chih-Wei Lin, Chung-Shi Liu, Ming-Da Cheng, Wen-Hsiung LU
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

The mechanisms of preparing bump structures described by using patterned anodes may simplify bump-making process, reduce manufacturing cost, and improve thickness uniformity within die and across the wafer. In addition, the mechanisms described above allow forming bumps with different heights to allow bumps to be integrated with elements on a substrate with different heights. Bumps with different heights expand the application of copper post bumps to enable further chip integration.

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Номер записи: 34
01-03-2012 дата публикации

Bumpless build-up layer package with pre-stacked microelectronic devices

Номер: US20120049382A1
Автор: Pramod Malatkar
Принадлежит: Intel Corp

The present disclosure relates to the field of integrated circuit package design and, more particularly, to packages using a bumpless build-up layer (BBUL) designs. Embodiments of the present description relate to the field of fabricating microelectronic packages, wherein a first microelectronic device having through-silicon vias may be stacked with a second microelectronic device and used in a bumpless build-up layer package.

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Номер записи: 35
01-03-2012 дата публикации

Serially interconnected vertical-cavity surface emitting laser arrays

Номер: US20120051384A1
Автор: Chad Shin-deh Wang, Jonathan C. Geske, Michael MacDougal
Принадлежит: Aerius Photonics LLC

Vertical Cavity Surface Emitting Laser (VCSEL) arrays with vias for electrical connection are disclosed. A Vertical Cavity Surface Emitting Laser (VCSEL) array in accordance with one or more embodiments of the present invention comprises a plurality of first mirrors, a plurality of second mirrors, a plurality of active regions, coupled between the plurality of first mirrors and the plurality of second mirrors, and a heatsink, thermally and mechanically coupled to the second mirror opposite the plurality of active regions, wherein an electrical path to at least one of the plurality of second mirrors is made through a via formed through a depth of the plurality of second mirrors, and a plurality of VCSELs in the VCSEL array are connected in series.

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Номер записи: 36
01-03-2012 дата публикации

Process for assembling two parts of a circuit

Номер: US20120052629A1
Автор: Patrick Lamontagne, Perceval Coudrain, Yacine Felk
Принадлежит: STMICROELECTRONICS SA

A three-dimensional integrated structure is fabricated by assembling at least two parts together, wherein each part contains at least one metallic line covered with a covering region and having a free side. A cavity is formed in the covering region of each part, that cavity opening onto the metallic line. The two parts are joined together with the free sides facing each other and the cavities in each covering region aligned with each other. The metallic lines are then electrically joined to each other through an electromigration of the metal within at least one of the metallic lines, the electromigrated material filling the aligned cavities.

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Номер записи: 37
08-03-2012 дата публикации

Multi-chip package with offset die stacking

Номер: US20120056335A1
Автор: Peter B. Gillingham
Принадлежит: Mosaid Technologies Inc

A semiconductor device has a plurality of stacked semiconductor dice mounted on a substrate. Each die has similar dimensions. Each die has a first plurality of bonding pads arranged along a bonding edge of the die. A first group of the dice are mounted to the substrate with the bonding edge oriented in a first direction. A second group of the dice are mounted to the substrate with the bonding edge oriented in a second direction opposite the first direction. Each die is laterally offset in the second direction relative to the remaining dice by a respective lateral offset distance such that the bonding pads of each die are not disposed between the substrate and any portion of the remaining dice in a direction perpendicular to the substrate. A plurality of bonding wires connects the bonding pads to the substrate. A method of manufacturing a semiconductor device is also disclosed.

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Номер записи: 38
15-03-2012 дата публикации

Power Semiconductor Chip Package

Номер: US20120061812A1
Автор: Ralf Otremba
Принадлежит: INFINEON TECHNOLOGIES AG

A device includes a vertical power semiconductor chip having an epitaxial layer and a bulk semiconductor layer. A first contact pad is arranged on a first main face of the power semiconductor chip and a second contact pad is arranged on a second main face of the power semiconductor chip opposite to the first main face. The device further comprises an electrically conducting carrier attached to the second contact pad.

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Номер записи: 39
15-03-2012 дата публикации

Semiconductor device and manufacturing method of the same

Номер: US20120061817A1
Автор: Mamoru SHISHIDO, Noriyuki Takahashi
Принадлежит: Renesas Electronics Corp

A semiconductor chip is mounted on a heat sink disposed inside a through-hole of a wiring board, electrodes of the semiconductor chip and connecting terminals of the wiring board are connected by bonding wires, a sealing resin is formed to cover the semiconductor chip and the bonding wires, and solder balls are formed on the lower surface of the wiring board, thereby constituting the semiconductor device. The heat sink is thicker than the wiring board. The heat sink has a protruded portion protruding to outside from the side surface of the heat sink, the protruded portion is located on the upper surface of the wiring board outside the through-hole, and the lower surface of the protruded portion contacts to the upper surface of the wiring board. When the semiconductor device is manufactured, the heat sink is inserted from the upper surface side of the wiring board.

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Номер записи: 40
15-03-2012 дата публикации

Semiconductor chip device with polymeric filler trench

Номер: US20120061852A1
Автор: Bryan Black, Gamal Refai-Ahmed, Michael Z. Su
Принадлежит: Advanced Micro Devices Inc, ATI TECHNOLOGIES ULC

A method of manufacturing is provided that includes providing a semiconductor chip with an insulating layer. The insulating layer includes a trench. A second semiconductor chip is stacked on the first semiconductor chip to leave a gap. A polymeric filler is placed in the gap wherein a portion of the polymeric filler is drawn into the trench.

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Номер записи: 41
15-03-2012 дата публикации

Semiconductor package integrated with conformal shield and antenna

Номер: US20120062439A1
Автор: Chi-Hong Chan, Kuo-Hsien Liao, Shih Fuyu
Принадлежит: Advanced Semiconductor Engineering Inc

A semiconductor package integrated with conformal shield and antenna is provided. The semiconductor package includes a semiconductor element, an electromagnetic interference shielding element, a dielectric structure, an antenna element and an antenna signal feeding element. The electromagnetic interference shielding element includes an electromagnetic interference shielding film and a grounding element, wherein the electromagnetic interference shielding film covers the semiconductor element and the grounding element is electrically connected to the electromagnetic interference shielding layer and a grounding segment of the semiconductor element. The dielectric structure covers a part of the electromagnetic interference shielding element and has an upper surface. The antenna element is formed adjacent to the upper surface of the dielectric structure. The antenna signal feeding element passing through the dielectric structure electrically connects the antenna element and the semiconductor element.

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Номер записи: 42
15-03-2012 дата публикации

Manufacturing method of substrate for a semiconductor package, manufacturing method of semiconductor package, substrate for a semiconductor package and semiconductor package

Номер: US20120064666A1
Автор: Shigeru Hosomomi, Yoichiro Hamada
Принадлежит: SUMITOMO METAL MINING CO LTD

A manufacturing method of a substrate for a semiconductor package includes a resist layer forming step to form a resist layer on a surface of a conductive substrate; an exposure step to expose the resist layer using a glass mask with a mask pattern including a transmission area, a light shielding area, and an intermediate transmission area, wherein transmittance of the intermediate transmission area is lower than that of the transmission area and is higher than that of the light shielding area; a development step to form a resist pattern including a hollow with a side shape including a slope part decreasing in hollow circumference as the hollow circumference approaches the substrate; and a plating step to plate on an exposed area to form a metal layer with a side shape including a slope part decreasing in circumference as the circumference approaches the substrate.

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Номер записи: 43
15-03-2012 дата публикации

Method of manufacture of integrated circuit packaging system with stacked integrated circuit

Номер: US20120064668A1
Автор: Henry Descalzo Bathan, Jairus Legaspi Pisigan, Zigmund Ramirez Camacho
Принадлежит: Individual

A method of manufacture of an integrated circuit packaging system includes: forming a base lead having an outer protrusion and an inner protrusion with a recess in between; forming a stack lead having an elongated portion; mounting a base integrated circuit over the inner protrusion or under the elongated portion; mounting the stack lead over the base lead and the base integrated circuit; connecting a stack integrated circuit and the stack lead with the stack integrated circuit over the base integrated circuit; and encapsulating at least a portion of both the base integrated circuit and the stack integrated circuit with the base lead and the stack lead exposed.

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Номер записи: 44
15-03-2012 дата публикации

Method of making a semiconductor chip assembly with a post/base heat spreader and a substrate using grinding

Номер: US20120064672A1
Автор: Charles W.C. Lin, Chia-Chung Wang
Принадлежит: Individual

A method of making a semiconductor chip assembly includes providing a post and a base, mounting an adhesive on the base including inserting the post through an opening in the adhesive, mounting a substrate on the adhesive including inserting the post into an aperture in the substrate, then flowing the adhesive between the post and the substrate in the aperture, solidifying the adhesive, then grinding the post and the adhesive, then mounting a semiconductor device on a heat spreader that includes the post and the base, electrically connecting the semiconductor device to the substrate and thermally connecting the semiconductor device to the heat spreader.

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Номер записи: 45
22-03-2012 дата публикации

Package substrate unit and method for manufacturing package substrate unit

Номер: US20120067635A1
Автор: Hideaki Yoshimura, Hitoshi Suzuki, Hnin Nway San Nang, Kazuya Arai, Kei Fukui, Shinpei Ikegami, Yasuhito Takahashi
Принадлежит: Fujitsu Ltd

A semiconductor chip mounting layer of a package substrate unit includes an insulation layer, a conductive seed metal layer formed on the top surface of the insulation layer, conductive pads formed on the top surface of the conductive seed metal layer, metal posts formed substantially in the central portion on the top surface of the conductive pads, and a solder resist layer that is formed to surround the conductive pads and the metal posts.

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Номер записи: 46
22-03-2012 дата публикации

Integrated circuit packaging system with stack interconnect and method of manufacture thereof

Номер: US20120068319A1
Автор: Daesik Choi, Oh Han Kim, SangMi Park
Принадлежит: Individual

A method of manufacture of an integrated circuit packaging system includes: forming a connection carrier having base device pads and base interconnect pads on a carrier top side of the connection carrier; connecting a base integrated circuit to the base device pads and mounted over the carrier top side; mounting base vertical interconnects directly on the base interconnect pads; attaching a base package substrate to the base integrated circuit and directly on the base vertical interconnects; forming a base encapsulation on the base package substrate, the base device pads, and the base interconnect pads; and removing a portion of the connection carrier with the base device pads and the base interconnect pads partially exposed opposite the base package substrate.

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Номер записи: 47
22-03-2012 дата публикации

Integrated Power Converter Package With Die Stacking

Номер: US20120068320A1
Автор: Eric Yang, Hunt Hang Jiang, Jinghai Zhou
Принадлежит: Monolithic Power Systems Inc

An integrated circuit for implementing a switch-mode power converter is disclosed. The integrated circuit comprises at least a first semiconductor die having an electrically quiet surface, a second semiconductor die for controlling the operation of said first semiconductor die stacked on said first semiconductor die having said electrically quiet surface and a lead frame structure for supporting said first semiconductor die and electrically coupling said first and second semiconductor dies to external circuitry.

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Номер записи: 48
22-03-2012 дата публикации

Substrate bonding with metal germanium silicon material

Номер: US20120068325A1
Автор: Alex P. Pamatat, Ruben B. Montez
Принадлежит: FREESCALE SEMICONDUCTOR INC

In one embodiment, a semiconductor structure including a first substrate, a semiconductor device on the first substrate, a second substrate, and a conductive bond between the first substrate and the second substrate that surrounds the semiconductor device to seal the semiconductor device between the first substrate and the second substrate. The conductive bond comprises metal, silicon, and germanium. A percentage by atomic weight of silicon in the conductive bond is greater than 5%.

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Номер записи: 49
22-03-2012 дата публикации

Microsprings Partially Embedded In A Laminate Structure And Methods For Producing Same

Номер: US20120068331A1
Автор: Eric Peeters, Eugene M. Chow
Принадлежит: Palo Alto Research Center Inc

At least one microspring has applied thereover a laminate structure to provide: mechanical protection during handling and wafer processing, a spring spacer layer, strengthening of the anchor between spring and substrate, provision of a gap stop during spring deflection, and moisture and contaminant protection. A fully-formed laminate structure may be applied over the microspring structure or a partly-formed laminate structure may be applied over the microspring structure then cured or hardened. The tip portion of the microspring may protrude through the laminate structure and be exposed for contact or may be buried within the contact structure. The laminate structure may remain in place in the final microspring structure or be removed in whole or in part. The laminate structure may be photolithographically patternable material, patterned and etched to remove some or all of the structure, forming for example additional structural elements such as a gap stop for the microspring.

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Номер записи: 50
29-03-2012 дата публикации

Method and system for minimizing carrier stress of a semiconductor device

Номер: US20120074568A1
Автор: Joachim Mahler, Khalil Hosseini, Manfred Mengel, Oliver EICHINGER
Принадлежит: INFINEON TECHNOLOGIES AG

A method and a system for minimizing carrier stress of a semiconductor device are provided. In one embodiment, a semiconductor device is provided comprising a carrier comprising a mesh coated with a metallic material, and a semiconductor chip disposed over the carrier.

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Номер записи: 51
29-03-2012 дата публикации

Integrated circuit packaging system with warpage control and method of manufacture thereof

Номер: US20120074588A1
Автор: Hin Hwa Goh, KANG Chen, Rui Huang, Xusheng Bao, Yung Kuan Hsiao
Принадлежит: Individual

A method of manufacture of an integrated circuit packaging system includes: providing an integrated circuit device having chip interconnects; applying an attachment layer directly on the integrated circuit device; attaching a device stiffener to the integrated circuit device with the attachment layer; attaching a chip carrier to the chip interconnects with the device stiffener attached to the integrated circuit device for controlling warpage of the integrated circuit device to prevent the warpage from causing some of the chip interconnects to separate from the chip carrier during attachment of the chip interconnects to the chip carrier; and applying an underfill between the chip carrier and the integrated circuit device for controlling connectivity of all the chip interconnects to the chip carrier.

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Номер записи: 52
05-04-2012 дата публикации

Semiconductor die package including low stress configuration

Номер: US20120083071A1
Автор: Maria Clemens Y. Quinones, Maria Cristina B. Estacio
Принадлежит: Individual

A semiconductor die package. The semiconductor die package comprises a semiconductor die and a molded clip structure comprising a clip structure and a first molding material covering at least a portion of the clip structure. The first molding material exposes an outer surface of the clip structure. The clip structure is electrically coupled to the semiconductor die. The semiconductor die package further comprises a leadframe structure comprising a die attach pad and a plurality of leads extending from the die attach pad. The semiconductor die is on the die attach pad of the leadframe structure. A second molding material covers at least a portion of the semiconductor die and the leadframe structure. The semiconductor die package also includes a heat slug and a thermally conductive material coupling the heat slug to the exposed surface of the clip structure.

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Номер записи: 53
12-04-2012 дата публикации

Electrode connection method, electrode connection structure, conductive adhesive used therefor, and electronic device

Номер: US20120085580A1
Автор: Kyouichirou Nakatsugi, Masamichi Yamamoto, Yasuhiro Okuda
Принадлежит: Sumitomo Electric Industries Ltd

By connecting together connecting electrodes having an organic film serving as an oxidation-preventing film using a conductive adhesive, the manufacturing process can be simplified, and a highly reliable connection structure can be constructed at low cost. An electrode connection method, in which a first connecting electrode 2 and a second connecting electrode 10 are connected together through a conductive adhesive 9 that is interposed between the electrodes, includes an organic film formation step in which an organic film 6 is formed on at least a surface of the first connecting electrode, and an electrode connection step in which the first connecting electrode and the second connecting electrode are connected together through the conductive adhesive. In the electrode connection step, by allowing an organic film decomposing component mixed in the conductive adhesive to act on the organic film, the organic film is decomposed, and thus connection between the connecting electrodes is performed.

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Номер записи: 54
12-04-2012 дата публикации

Semiconductor device and test system for the semiconductor device

Номер: US20120086003A1
Автор: Sung-Kyu Park
Принадлежит: SAMSUNG ELECTRONICS CO LTD

A semiconductor package including a stress mitigation unit that mitigates stress to the semiconductor chip. The semiconductor package includes a substrate, a semiconductor chip on the substrate, an encapsulation member formed on the substrate and covering the first semiconductor chip, and the stress mitigation unit mitigating stress from a circumference of the first semiconductor chip to the first semiconductor chip. The stress mitigation unit includes at least one groove formed in the encapsulation member.

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Номер записи: 55
12-04-2012 дата публикации

Led package, and mold and method of manufacturing the same

Номер: US20120086031A1
Автор: Chih-Hsun Ke, Shiun-Wei Chan
Принадлежит: Advanced Optoelectronic Technology Inc

The present disclosure provides a light emitting diode (LED) package, which includes a first substrate with electrodes disposed on a top thereof and a second substrate with an LED chip disposed on a top thereof. The LED chip is connected with the electrodes via wires. A first package layer is disposed on the top of the first substrate to cover the wires and electrodes. A fluorescent layer is disposed on the top of the second substrate to cover the LED chip. The present disclosure also provides a mold and a method of manufacturing the LED package.

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Номер записи: 56
12-04-2012 дата публикации

Package systems and manufacturing methods thereof

Номер: US20120086126A1
Автор: Chia-Pao SHU, Chun-Wen Cheng, Kuei-Sung CHANG
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

A package system includes a first substrate and a second substrate. The second substrate is electrically coupled with the first substrate. The second substrate includes at least one first opening. At least one electrical bonding material is disposed between the first substrate and the second substrate. A first portion of the at least one electrical bonding material is at least partially filled in the at least one first opening.

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Номер записи: 57
12-04-2012 дата публикации

Package systems and manufacturing methods thereof

Номер: US20120086127A1
Автор: Chia-Pao SHU, Chun-Wen Cheng, Hsin-Ting HUANG, Jung-Huei Peng, Kuei-Sung CHANG, Shang-Ying Tsai
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

A package system includes a first substrate. A second substrate is electrically coupled with the first substrate. At least one electrical bonding material is disposed between the first substrate and the second substrate. The at least one electrical bonding material includes a eutectic bonding material. The eutectic bonding material includes a metallic material and a semiconductor material. The metallic material is disposed adjacent to a surface of the first substrate. The metallic material includes a first pad and at least one first guard ring around the first pad.

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Номер записи: 58
12-04-2012 дата публикации

Integrated circuit tampering protection and reverse engineering prevention coatings and methods

Номер: US20120088338A1
Автор: Alan P. Boone, Nathan P. Lower, Ross K. Wilcoxon
Принадлежит: ROCKWELL COLLINS INC

A method of protecting an electronics package is discussed along with devices formed by the method. The method involves providing at least one electronic component that requires protecting from tampering and/or reverse engineering. Further, the method includes mixing into a liquid glass material at least one of high durability micro-particles or high-durability nano-particles, to form a coating material. Further still, the method includes depositing the coating material onto the electronic component and curing the coating material deposited.

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Номер записи: 59
19-04-2012 дата публикации

Semiconductor chip assembly with bump/base/ledge heat spreader, dual adhesives and cavity in bump

Номер: US20120091493A1
Автор: Charles W.C. Lin, Chia-Chung Wang
Принадлежит: Bridge Semiconductor Corp

A semiconductor chip assembly includes a semiconductor device, a heat spreader, a conductive trace and dual adhesives. The heat spreader includes a bump, a base and a ledge. The conductive trace includes a pad and a terminal. The semiconductor device is mounted on the bump in a cavity in the bump, is electrically connected to the conductive trace and is thermally connected to the heat spreader. The bump extends into an opening in the first adhesive and is aligned with and spaced from an opening in the second adhesive. The base and the ledge extend laterally from the bump. The first adhesive is sandwiched between the base and the ledge, the second adhesive is sandwiched between the conductive trace and the ledge and the ledge is sandwiched between the adhesives. The conductive trace is located outside the cavity and provides signal routing between the pad and the terminal.

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Номер записи: 60
19-04-2012 дата публикации

Method of die bonding onto dispensed adhesives

Номер: US20120094440A1
Автор: Kui Kam Lam, Kwok Kee Chung, Kwok Kiu CHAN, Yen Hsi Tang
Принадлежит: ASM Assembly Automation Ltd

A method of bonding semiconductor dice onto a substrate first uses an optical assembly to perform pattern recognition of a die bonding section of the substrate in which multiple die pads are located so as to identify positions of the multiple die pads simultaneously during such pattern recognition step. After pattern recognition of the said die bonding section, an adhesive is dispensed with an adhesive dispenser onto at least one of the die pads located in the die bonding section. While the adhesive dispenser is dispensing the adhesive to further die pads located in the die bonding section, a pick-and-place arm concurrently bonds a die onto each die pad where the adhesive has already been dispensed.

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Номер записи: 61
26-04-2012 дата публикации

Atomic layer deposition encapsulation for power amplifiers in rf circuits

Номер: US20120097970A1
Автор: Jayanti Jaganatha Rao, John Robert Siomkos, Merrill Albert Hatcher, JR.
Принадлежит: RF Micro Devices Inc

Power amplifiers and methods of coating a protective film of alumina (Al 2 O 3 ) on the power amplifiers are disclosed herein. The protective film is applied through an atomic layer deposition (ALD) process. The ALD process can deposit very thin layers of alumina on the surface of the power amplifier in a precisely controlled manner. Thus, the ALD process can form a uniform film that is substantially free of free of pin-holes and voids.

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Номер записи: 62
26-04-2012 дата публикации

Power/ground layout for chips

Номер: US20120098127A1
Автор: Albert Wu, Chuan-Cheng Cheng, Chung Chyung Han, Sehat Sutardja, Shuhua Yu, Weidan Li
Принадлежит: MARVELL WORLD TRADE LTD

Embodiments of the present disclosure provide a chip that comprises a base metal layer formed over a first semiconductor die and a first metal layer formed over the base metal layer. The first metal layer includes a plurality of islands configured to route at least one of (i) a ground signal or (ii) a power signal in the chip. The chip further comprises a second metal layer formed over the first metal layer. The second metal layer includes a plurality of islands configured to route at least one of (i) the ground signal or (ii) the power signal in the chip.

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Номер записи: 63
03-05-2012 дата публикации

Semiconductor package device with a heat dissipation structure and the packaging method thereof

Номер: US20120104581A1
Автор: Chia-Feng Yeh, Chung-Hwa Wu, Shao-Kang Hung
Принадлежит: Global Unichip Corp

The present invention provide a heat dissipation structure on the active surface of the die to increase the performance of the heat conduction in longitude direction of the semiconductor package device, so that the heat dissipating performance can be improved when the semiconductor package device is associated with the exterior heat dissipation mechanism.

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Номер записи: 64
03-05-2012 дата публикации

Chip-on-chip structure and manufacturing method therof

Номер: US20120104597A1
Автор: Junji Yoshikawa, Tatsuji Ishiduka, Tsutomu Kojima
Принадлежит: Toshiba Corp

According to an embodiment, a chip-on-chip structure includes a first chip, a second chip, the first chip and the second chip being opposite to each other, a first electrode terminal, a second electrode terminal, a bump and a protecting material. The first electrode terminal is provided on the surface of the first chip at the side of the second chip. The second electrode terminal is provided on the surface of the second chip at the side of the first chip. The bump electrically connects the first electrode terminal and the second electrode terminal. The protecting material is formed around the bump between the first chip and the second chip. The protecting material includes a layer made of a material having heat-sensitive adhesive property.

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Номер записи: 65
03-05-2012 дата публикации

Semiconductor module

Номер: US20120104631A1
Автор: Nam-Seog Kim, Seung-Duk Baek, Sun-Won Kang, Tae-Gyeong Chung, Young-hee Song
Принадлежит: Individual

A semiconductor module may include a circuit substrate with a first die on the circuit substrate and a second die on the first die. The first die may include at least one first data input/output pad on a first peripheral portion of the first die and at least one first control/address pad on a third peripheral portion, the third peripheral portion being separate from the first peripheral portion of the first die. The second die may include at least one second data input/output pad on a second peripheral portion and at least one second control/address pad on a fourth peripheral portion. The second peripheral portion of the second die is not overlapped with the first peripheral portion of the first die in plan view. The fourth peripheral portion of the second die overlaps at least a portion of the third peripheral portion of the first die.

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Номер записи: 66
03-05-2012 дата публикации

Method for manufacturing semiconductor device

Номер: US20120108013A1
Автор: Atsushi Fujisawa, Hiroshi Fujii
Принадлежит: Renesas Electronics Corp

In QFN packages for vehicles which are required to have high reliability, the side surface of leads is mostly covered with lead-to-lead resin protrusions, which prevent smooth formation of solder fillets during reflow mounting. When the lead-to-lead protrusions are mechanically removed using a punching die, there is a high possibility of causing cracks of the main body of the package or terminal deformation. When a spacing is provided between the punching die and the main body of the package in order to avoid such damages, a resin residue is produced to hinder complete removal of this lead-to-lead resin protrusion. The present invention provides a method for manufacturing semiconductor device of a QFN type package using multiple leadframes having a dam bar for tying external end portions of a plurality of leads. This method includes a step of removing a sealing resin filled between the circumference of a mold cavity and the dam bar by using laser and then carrying out surface treatment, for example, solder plating.

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Номер записи: 67
10-05-2012 дата публикации

Electronic element unit and reinforcing adhesive agent

Номер: US20120111617A1
Автор: Koji Motomura, Seiichi Yoshinaga, Tadahiko Sakai
Принадлежит: Panasonic Corp

It is an object of the present invention to provide an electronic element unit and a reinforcing adhesive agent in which a bonding strength can be improved between an electronic element and a circuit board and a repairing work can be carried out without giving a thermal damage to the electronic element or the circuit board. In an electronic element unit ( 1 ) including an electronic element ( 2 ) having a plurality of connecting terminals ( 12 ) on a lower surface thereof, a circuit board ( 3 ) having a plurality of electrodes ( 22 ) corresponding to the connecting terminals ( 12 ) on an upper surface thereof. The connecting terminals ( 12 ) and the electrodes ( 22 ) are connected by solder bumps ( 23 ), and the electronic element ( 2 ) and the circuit board ( 3 ) are partly bond by a resin bond part ( 24 ) made of a thermosetting material of a thermosetting resin, and a metal powder ( 25 ) is included in the resin bond parts ( 24 ) in a dispersed state. The metal powder ( 25 ) has a melting point lower than a temperature at which the resin bond parts ( 24 ) are heated when a work (a repairing work) is carried out for removing the electronic element ( 2 ) from the circuit board ( 3 ).

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Номер записи: 68
17-05-2012 дата публикации

Underfill method and chip package

Номер: US20120119353A1
Автор: Michael A. Gaynes, Rajneesh Kumar, Steve Ostrander, Thomas E. Lombardi
Принадлежит: International Business Machines Corp

A method of fabricating a chip package is provided. The chip package includes a laminate, a chip and conductive elements interposed between the chip and the laminate by which signals are transmitted among the chip and the laminate. The method includes dispensing a first underfill in a space defined between opposing faces of the chip and the laminate and dispensing a second underfill at least at a portion of an edge of the chip, the second underfill including a high aspect ratio material.

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Номер записи: 69
17-05-2012 дата публикации

Integrated circuit packaging system with connection structure and method of manufacture thereof

Номер: US20120119360A1
Автор: DeokKyung Yang, In Sang Yoon, Jaehyun Lee, Ki Youn Jang, KyungHoon Lee, Seong Won Park, Sungeun Park, YoungChul KIM
Принадлежит: Stats Chippac Pte Ltd

A method of manufacture of an integrated circuit packaging system includes: providing a substrate; attaching a connection post to the substrate, the connection post having a post top and a post side; mounting an integrated circuit die on the substrate, the integrated circuit die having a top die surface; and forming a package body on the substrate, the connection post, and the integrated circuit die.

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Номер записи: 70
17-05-2012 дата публикации

Electric part package and manufacturing method thereof

Номер: US20120119379A1
Автор: Kenta Uchiyama, Masahiro Kyozuka, Naoyuki Koizumi
Принадлежит: Shinko Electric Industries Co Ltd

A disclosed electric part package includes a supporting member that includes a first area in which an electric part is arranged, and a second area in which a first opening is positioned, the second area being isolated from the first area; a resin part provided on the supporting member thereby to cover the electric part arranged in the first area, the resin part including an electric terminal exposed in the first opening of the supporting member; and a wiring structure provided on the resin part, the wiring structure being electrically connected to the electric part and the electric terminal of the resin part.

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Номер записи: 71
24-05-2012 дата публикации

Connecting and Bonding Adjacent Layers with Nanostructures

Номер: US20120125537A1
Автор: Andrzej Brud, Mohammad Shafiqul Kabir
Принадлежит: Smoltek AB

An apparatus, comprising two conductive surfaces or layers and a nanostructure assembly bonded to the two conductive surfaces or layers to create electrical or thermal connections between the two conductive surfaces or layers, and a method of making same.

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Номер записи: 72
24-05-2012 дата публикации

Copper conductor film and manufacturing method thereof, conductive substrate and manufacturing method thereof, copper conductor wiring and manufacturing method thereof, and treatment solution

Номер: US20120125659A1
Автор: Hideo Nakako, Katsuyuki Masuda, Kazunori Yamamoto, Shunya Yokozawa, Yasushi Kumashiro, Yoshinori Ejiri, Youichi Machii
Принадлежит: Hitachi Chemical Co Ltd

Provided are a copper conductor film and manufacturing method thereof, and patterned copper conductor wiring, which have superior conductivity and wiring pattern formation, and with which there is no decrease in insulation between circuits, even at narrow wiring widths and narrow inter-wiring spacing. Disclosed are a copper conductor film and manufacturing method thereof in which a copper-based particle-containing layer, which contains both a metal having catalytic activity toward a reducing agent and copper oxide, is treated using a treatment solution that contains a reagent that ionizes or complexes copper oxide and a reducing agent that reduces copper ions or copper complex to form metallic copper in a single solution, and patterned copper conductor wiring that is obtained by patterning a copper-based particle-containing layer using printing and by said patterned particle-containing layer being treated by a treatment method using a solution that contains both a reagent that ionizes or complexes copper oxide and a reducing agent that reduces copper ions or copper complexes to form metallic copper in a single solution.

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Номер записи: 73
24-05-2012 дата публикации

Package carrier

Номер: US20120125669A1
Автор: Chau-Jie Zhan, Jing-Yao Chang, Tao-Chih Chang, Tsung-Fu Tsai
Принадлежит: Industrial Technology Research Institute ITRI

A package carrier including a substrate, at least an under bump metallurgic (UBM) layer and at least a conductive bump is provided. The substrate has a conductive structure and at least a pad connected with the conductive structure. A region of the pad connected with the conductive structure is a signal source region. The UBM layer is disposed on the pad and includes a first conductive pattern and a second conductive pattern. A side wall of the second conductive pattern is directly connected to a side wall of the first conductive pattern, and the second conductive pattern is disposed close to the signal source region. The conductivity of the second conductive pattern is smaller than the conductivity of the first conductive pattern. The conductive bump is disposed on the UBM layer.

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Номер записи: 74
24-05-2012 дата публикации

Method for semiconductor leadframes in low volume and rapid turnaround

Номер: US20120126385A1
Автор: Sreenivasan K. Koduri
Принадлежит: Texas Instruments Inc

A leadframe for a QFN/SON semiconductor device comprising a strip of a first metal as the leadframe core with a plurality of leads and a pad. a layer of a second metal over both surfaces of the strip. There are sidewalls normal to the surfaces. The first metal exposed at the sidewalls and at portions of a surface of the pad.

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Номер записи: 75
24-05-2012 дата публикации

System comprising a semiconductor device and structure

Номер: US20120129301A1
Автор: Brian Cronquist, Deepak C. Sekar, Israel Beinglass, Paul Lim, Ze&#39;ev Wurman, Zvi Or-Bach
Принадлежит: Monolithic 3D Inc

A method of manufacturing a semiconductor device, the method including, providing a first monocrystalline layer including semiconductor regions, overlaying the first monocrystalline layer with an isolation layer, transferring a second monocrystalline layer comprising semiconductor regions to overlay the isolation layer, wherein the first monocrystalline layer and the second monocrystalline layer are formed from substantially different crystal materials; and subsequently etching the second monocrystalline layer as part of forming at least one transistor in the second monocrystalline layer.

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Номер записи: 76
31-05-2012 дата публикации

Cerium and Europium Doped Phosphor Compositions and Light Emitting Devices Including the Same

Номер: US20120132857A1
Автор: Ronan P. Le Toquin
Принадлежит: Individual

Compounds of Formula I, which include both cerium and europium, may be useful as phosphors in solid state light emitting devices. Light emitting devices including such phosphors may emit warm white light.

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Номер записи: 77
31-05-2012 дата публикации

Tsv substrate structure and the stacked assembly thereof

Номер: US20120133030A1
Автор: Cha-Hsin Lin, Chung-Chih Wang, Pei-Jer Tzeng, Tzu-Kun Ku
Принадлежит: Industrial Technology Research Institute ITRI

The disclosure provides a TSV substrate structure and the stacked assembly of a plurality of the substrate structures, the TSV substrate structure including: a substrate comprising a first surface, a corresponding second surface, and a TSV communicating the first surface with the second surface through the substrate; and a conductor unit completely filling the TSV, the conductor unit comprising a conductor body which has a first and a second ends corresponding to the first and second surfaces of the substrate, respectively.

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Номер записи: 78
31-05-2012 дата публикации

Semiconductor Structures and Method for Fabricating the Same

Номер: US20120135201A1
Автор: Ching-Hung Ko, Mu-Jia Liu, Tsung-Chieh Chang
Принадлежит: Himax Technologies Ltd

A semiconductor structure is provided. The semiconductor structure includes a first substrate, a second substrate opposite to the first substrate, a plurality of spacers disposed between the first substrate and the second substrate, and an adhesive material bonded with the first substrate and the second substrate within the two adjacent spacers. The invention also provides a method for fabricating the semiconductor structure.

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Номер записи: 79
07-06-2012 дата публикации

Semiconductor Device

Номер: US20120139130A1
Автор: Masaki Shiraishi, Nobuyoshi Matsuura, Tomoaki Uno, Yukihiro Satou
Принадлежит: Renesas Electronics Corp

The present invention provides a non-insulated type DC-DC converter having a circuit in which a power MOS•FET for a high side switch and a power MOS•FET for a low side switch are connected in series. In the non-insulated type DC-DC converter, the power transistor for the high side switch, the power transistor for the low side switch, and driver circuits that drive these are respectively constituted by different semiconductor chips. The three semiconductor chips are accommodated in one package, and the semiconductor chip including the power transistor for the high side switch, and the semiconductor chip including the driver circuits are disposed so as to approach each other.

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Номер записи: 80
14-06-2012 дата публикации

Brace for long wire bond

Номер: US20120145446A1
Автор: Hanmin Zhang, Jie Yang, Qingchin He
Принадлежит: FREESCALE SEMICONDUCTOR INC

An electrical connection includes a first wire bonded to adjacent bond pads proximate to an edge of a die and a second wire having one end bonded to a die bond pad distal to the die edge and a second end bonded to a lead finger of a lead frame or a connection pad of a substrate. The second wire crosses and is supported by the first wire. The first wire acts as a brace that prevents the second wire from touching the edge of the die. The first wire also prevents the second wire from excessive lateral movement during encapsulation.

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Номер записи: 81
14-06-2012 дата публикации

Integrated circuit mounting system with paddle interlock and method of manufacture thereof

Номер: US20120146192A1
Автор: Arnel Senosa Trasporto, Byung Joon Han, Byung Tai Do, Henry Descalzo Bathan
Принадлежит: Individual

A method of manufacture of an integrated circuit mounting system includes: providing a die paddle with a component side having a die mount area and a recess with more than one geometric shape; applying an adhesive on the die mount area and in a portion of the recess; and mounting an integrated circuit device with an inactive side directly on the adhesive.

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Номер записи: 82
14-06-2012 дата публикации

Bonding pad structure and integrated circuit comprising a plurality of bonding pad structures

Номер: US20120146215A1
Автор: Chih-Hung Lu, Yu-Ju Yang
Принадлежит: ILI Techonology Corp

A bonding pad structure positioned on an integrated circuit includes a connecting pad, an insulation layer and a gold bump. The connecting pad is formed on the integrated circuit. The insulation layer is formed on the connecting pad, where the insulation layer has only one opening and a shape of the opening includes at least a bend. The gold bump is formed on the insulation layer, where the gold bump is electrically connected to the connecting pad through the opening of the insulation layer.

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Номер записи: 83
14-06-2012 дата публикации

Method for Manufacturing Heat Dissipation Bulk of Semiconductor Device

Номер: US20120149138A1
Автор: Chun-Liang Lin, Kuan-Chun Chen, Yan-Kuin Su
Принадлежит: National Cheng Kung University NCKU

A method for manufacturing a heat dissipation bulk of a semiconductor device including the following steps is described. An electrically conductive layer is formed to cover a surface of a temporary substrate. At least one semiconductor chip is connected to the electrically conductive layer by at least one metal bump, wherein the at least one metal bump is located between the at least one semiconductor chip and the electrically conductive layer. A metal substrate is formed on the electrically conductive layer, wherein the metal substrate fills up a gap between the at least one semiconductor chip and the electrically conductive layer. The temporary substrate is removed.

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Номер записи: 84
21-06-2012 дата публикации

Semiconductor component, semiconductor wafer component, manufacturing method of semiconductor component, and manufacturing method of joining structure

Номер: US20120153461A1
Автор: Akio Furusawa, Hidetoshi Kitaura, Shigeaki Sakatani, Taichi Nakamura, Takahiro Matsuo
Принадлежит: Panasonic Corp

A semiconductor component of the present invention includes a semiconductor element and a joining layer formed on one surface of the semiconductor element and consisting of a joining material containing Bi as an essential ingredient, and projecting sections are formed on a surface of the joining layer on a side opposite to a surface in contact with the semiconductor element. By joining the semiconductor component to an electrode arranged so as to face the joining layer, the generation of a void can be suppressed.

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Номер записи: 85
21-06-2012 дата публикации

Tsv for 3d packaging of semiconductor device and fabrication method thereof

Номер: US20120153496A1
Автор: Chang-woo Lee, Jae-hak Lee, Joon-Yub Song, Tae-Ho Ha
Принадлежит: Korea Institute of Machinery and Materials KIMM

The present invention relates to a through silicon via (TSV) for 3D packaging to integrate a semiconductor device and a method for manufacturing the same, and more particularly, to a through silicon via (TSV) for 3D packaging of a semiconductor device that is capable of improving production efficiency, having very high electric conductivity, and minimizing electrical signal delay, without using a carrier wafer by self-aligning substrates in a low temperature state and sequentially bonding a plurality of semiconductor dies (or semiconductor chips), and a method of manufacturing the same.

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Номер записи: 86
21-06-2012 дата публикации

Semiconductor package and manufacturing method therefor

Номер: US20120153509A1
Автор: Akihiko Tateiwa, Masahiro Kyozuka, Toru Hizume
Принадлежит: Shinko Electric Industries Co Ltd

According to one embodiment, there is provided a semiconductor package including: a semiconductor chip; a resin portion formed to cover the semiconductor chip; a wiring structure formed on the resin portion and electrically connected to the semiconductor chip; and a warpage preventing member provided above the resin portion to have a thermal expansion coefficient closer to that of the semiconductor chip than to that of the wiring structure.

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Номер записи: 87
21-06-2012 дата публикации

Flexible circuit board and manufacturing method thereof

Номер: US20120155038A1
Автор: Masaki Fujiwara, Steven Roy Droes, Yasumori Fukushima
Принадлежит: Sharp Corp

The present invention provides a high-performance flexible circuit board having excellent flexibility, a fine wiring pattern, and fine electric contacts, and a manufacturing method thereof. In a flexible circuit board ( 20 ), a second insulating layer ( 24 ) made of an inorganic material is positioned between a wiring layer ( 25 ) and a first insulating layer ( 23 ) made of an inorganic material.

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Номер записи: 88
21-06-2012 дата публикации

Semiconductor chip assembly and method for making same

Номер: US20120155055A1
Автор: Belgacem Haba, Hiroaki Sato, Ilyas Mohammed, Kiyoaki Hashimoto, Norihito Masuda, Philip Damberg, Teck-Gyu Kang, Wei-Shun Wang, Yoshikuni Nakadaira
Принадлежит: Tessera LLC

A microelectronic assembly may include a substrate including a rigid dielectric layer having electrically conductive elements, a microelectronic element having a plurality of contacts exposed at a face thereof, and conductive vias extending through a compliant dielectric layer overlying the rigid dielectric layer. The vias electrically connect the substrate contacts respectively to the conductive elements, and the substrate contacts are joined respectively to the contacts of the microelectronic element. The vias, compliant layer and substrate contacts are adapted to appreciably relieve stress at the substrate contacts associated with differential thermal contact and expansion of the assembly.

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Номер записи: 89
28-06-2012 дата публикации

Chip scale surface mounted semiconductor device package and process of manufacture

Номер: US20120161307A1
Автор: Tao Feng
Принадлежит: ALPHA AND OMEGA SEMICONDUCTOR INC

A semiconductor device package die and method of manufacture are disclosed. The device package die may comprise a device substrate having one or more front electrodes located on a front surface of the device substrate and electrically connected to one or more corresponding device regions formed within the device substrate proximate the front surface. A back conductive layer is formed on a back surface of the device substrate. The back conductive layer is electrically connected to a device region formed within the device substrate proximate a back surface of the device substrate. One or more conductive extensions are formed on one or more corresponding sidewalls of the device substrate in electrical contact with the back conductive layer, and extend to a portion of the front surface of the device substrate. A support substrate is bonded to the back surface of the device substrate.

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Номер записи: 90
28-06-2012 дата публикации

Trap Rich Layer for Semiconductor Devices

Номер: US20120161310A1
Автор: Chris BRINDLE, Michael A. Stuber, Stuart B. Molin
Принадлежит: IO Semiconductor Inc

An integrated circuit chip is formed with an active layer and a trap rich layer. The active layer is formed with an active device layer and a metal interconnect layer. The trap rich layer is formed above the active layer. In some embodiments, the active layer is included in a semiconductor wafer, and the trap rich layer is included in a handle wafer.

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Номер записи: 91
28-06-2012 дата публикации

Semiconductor device and assembling method thereof

Номер: US20120161336A1
Автор: Chau-Jie Zhan, Su-Tsai Lu, Yu-Min Lin
Принадлежит: Industrial Technology Research Institute ITRI

A semiconductor device and an assembling method thereof are provided. The semiconductor device includes a chip, a carrier, a plurality of first conductive elements and a plurality of second conductive elements. The chip has a plurality of first pads. The carrier has a plurality of second pads. The second pads correspond to the first pads. Each first conductive element is disposed between one of the first pads and one of the second pads. Each second conductive element is disposed between one of the first pads and one of the second pads. A volume ratio of intermetallic compound of the second conductive elements is greater than a volume ratio of intermetallic compound of the first conductive elements.

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Номер записи: 92
28-06-2012 дата публикации

Bond package and approach therefor

Номер: US20120162958A1
Автор: Michael Rother
Принадлежит: NXP BV

Lead-free or substantially lead-free structures and related methods are implemented for manufacturing electronic circuits. In accordance with various example embodiments, circuit components are joined using a copper-tin (Cu—Sn) alloy, which is melted and used to form a Cu—Sn compound having a higher melting point than the Cu—Sn alloy and both physically and electrically coupling circuit components together.

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Номер записи: 93
28-06-2012 дата публикации

Light source with tunable cri

Номер: US20120162979A1
Автор: Bit Tie Chan, Keat Chuan Ng, Kheng Leng Tan
Принадлежит: Avago Technologies ECBU IP Singapore Pte Ltd

A light-emitting device with at least two light-emitting dies encapsulated with two different types of the wavelength-converting materials is disclosed. Each of the wavelength-converting materials is configured to produce a visible light from a narrow band light near UV region produced by the light-emitting dies, but with different correlated color temperatures (CCT) and different spectral contents. The combination of the two visible light forms the desired visible white light. The Color rendering index of the light-emitting device is tunable by adjusting the supply current to the light-emitting dies. In another embodiment, a light module with tunable CRI for an illumination system is disclosed.

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Номер записи: 94
28-06-2012 дата публикации

Method of manufacturing semiconductor device including plural semiconductor chips stacked together

Номер: US20120164788A1
Автор: Akira Ide
Принадлежит: Elpida Memory Inc

Such a method is disclosed that includes preparing first and second semiconductor chips, the first semiconductor chip including a first electrode formed on one surface thereof and a second electrode formed on the other surface thereof so as to overlap the first electrode as viewed from a stacking direction, and the second semiconductor chip including a third electrode formed on one surface thereof and a fourth electrode formed on the other surface thereof so as not to overlap the third electrode as viewed from the stacking direction, and stacking the first and second semiconductor chips in the stacking direction so that the second electrode is connected to the third electrode by using a bonding tool including a concave at a position corresponding to the fourth electrode.

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Номер записи: 95
05-07-2012 дата публикации

Semiconductor package and method of fabricating the same

Номер: US20120168919A1
Автор: Joo-yang Eom, Joon-Seo Son
Принадлежит: Individual

A semiconductor package and a method of manufacturing the same, and more particularly, to a package of a power module semiconductor and a method of manufacturing the same. The semiconductor package includes a substrate including a plurality of conductive patterns spaced apart from one another; a plurality of semiconductor chips disposed on the conductive patterns; a connecting member for electrically connecting the conductive patterns to each other, for electrically connecting the semiconductor chips to each other, or for electrically connecting the conductive pattern and the semiconductor chip; and a sealing member for covering the substrate, the semiconductor chips, and the connecting member, wherein a lower surface of the substrate and an upper surface of the connecting member are exposed to the outside by the sealing member.

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Номер записи: 96
05-07-2012 дата публикации

Semiconductor device

Номер: US20120168927A1
Автор: Shingo Itoh
Принадлежит: Sumitomo Bakelite Co Ltd

A semiconductor device is configured that two or more semiconductor elements are stacked and mount on a lead frame, the aforementioned lead frame is electrically joined to the semiconductor element with a wire, and the semiconductor element, the wire and an electric junction are encapsulated with a cured product of an epoxy resin composition for encapsulating semiconductor device, and that the epoxy resin composition for encapsulating semiconductor device contains (A) an epoxy resin; (B) a curing agent; and (C) an inorganic filler, and that the (C) inorganic filler contains particles having particle diameter of equal to or smaller than two-thirds of a thinnest filled thickness at a rate of equal to or higher than 99.9% by mass.

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Номер записи: 97
05-07-2012 дата публикации

Substrate bonding method and semiconductor device

Номер: US20120168954A1
Автор: Toshihiro Seko
Принадлежит: Stanley Electric Co Ltd

A first Sn absorption layer is formed on a principal surface of a first substrate, the first Sn absorption layer being made of metal absorbing Sn from AuSn alloy and lowering a relative proportion of Sn in the AuSn alloy. A second Sn absorption layer is formed on a principal surface of a second substrate, the second Sn absorption layer being made of metal absorbing Sn from AuSn alloy and lowering a relative proportion of Sn in the AuSn alloy. A solder layer made of AuSn alloy is formed at least on one Sn absorption layer of the first and second Sn absorption layers. The first and second substrates are bonded together by melting the solder layer in a state that the first and second substrates are in contact with each other, with the principal surfaces of the first and second substrates facing each other.

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Номер записи: 98
05-07-2012 дата публикации

Hybrid bonding interface for 3-dimensional chip integration

Номер: US20120171818A1
Автор: Karl W. Barth, Kevin S. Petrarca, Ricardo A. Donaton, Shahab Siddiqui, Spyridon Galis
Принадлежит: International Business Machines Corp

Each of a first substrate and a second substrate includes a surface having a diffusion resistant dielectric material such as silicon nitride. Recessed regions are formed in the diffusion resistant dielectric material and filled with a bondable dielectric material. The patterns of the metal pads and bondable dielectric material portions in the first and second substrates can have a mirror symmetry. The first and second substrates are brought into physical contact and bonded employing contacts between metal pads and contacts between the bondable dielectric material portions. Through-substrate-via (TSV) structures are formed through bonded dielectric material portions. The interface between each pair of bonded dielectric material portions located around a TSV structure is encapsulated by two diffusion resistant dielectric material layers so that diffusion of metal at a bonding interface is contained within each pair of bonded dielectric material portions.

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Номер записи: 99
12-07-2012 дата публикации

Methods And Materials Useful For Chip Stacking, Chip And Wafer Bonding

Номер: US20120175721A1
Автор: Andrew Bell, Chris Apanius, Hendra Ng, Phil Neal, Robert A. Shick, Wei Zhang
Принадлежит: PROMERUS LLC

Materials, and methods that use such materials, that are useful for forming chip stacks, chip and wafer bonding and wafer thinning are disclosed. Such methods and materials provide strong bonds while also being readily removed with little or no residues.

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Номер записи: 100