Connection components with rows of lead bond sections

A connection component for a microelectronic element includes a sheet-like support structure having top and bottom surfaces which extend in horizontal directions. The support structure includes a central region and a periphery surrounding the central region with terminals mounted on the central region of the support structure and exposed at the top surface thereof. A plurality of leads extend on the support structure with each lead having a terminal section connected to one of the terminals and attached to the bottom surface, a bond region and a horizontally curved section between the bond region and the terminal region. The bond regions of the leads are disposed side-by-side in one or more rows adjacent the periphery of the support structure. After the bond regions of the leads have been bonded to contacts of a microelectronic element, the support structure of the connection component is moveable upwardly so as to bend the curved sections of the leads.

HYBRIDIZATION TO-FACE TWO MICROELECTRONIC COMPONENTS USING ANNEAL UV

Ce procédé de fabrication d'un dispositif microélectronique comportant un premier composant (12) hybridé à un second composant (14) au moyen d'interconnexions électriques, consiste : ▪ à réaliser des premier et second composants (12, 14), le second composant (14) étant transparent à un rayonnement ultraviolet au moins au droit d'emplacements prévus pour les interconnexions ; ▪ à former des éléments d'interconnexion (22) comprenant de l'oxyde de cuivre sur le second composant (14) aux emplacements prévus pour les interconnexions; ▪ à reporter les premier et second composants (12, 14) l'un sur l'autre ; et ▪ à appliquer un rayonnement ultraviolet au travers le second composant (14) sur les éléments comprenant de l'oxyde de cuivre de manière à mettre en œuvre un recuit ultraviolet transformant l'oxyde de cuivre en cuivre.

스택되는 다이들의 위치들을 제어하는 기술

... 조립 부품(100) 및 조립 부품을 이용하여 칩 패키지를 조립하는 기술이 설명된다. 이 칩 패키지는 수직 방향으로 스택 내에 배열되는 반도체 다이들(310-1 내지 310-N)의 세트를 포함하는데, 반도체 다이들은 수직 스택의 일 측에 계단형 테라스(112-1)를 정의하도록 수평 방향에서 서로 오프셋된다. 또한, 칩 패키지는 조립 부품(100)을 이용하여 조립될 수 있다. 특히, 조립 부품은 대략 칩 패키지의 계단형 테라스를 대략 미러링하는 계단형 테라스들(112-1, 112-2)의 쌍을 포함할 수 있고, 이 경사형 테라스들의 쌍은 칩 패키지의 조립 동안 수직 스택으로 반도체 다이들의 세트를 배치하는 조립 도구에 대해 수직 위치 레퍼런스를 제공한다.

RAMP-STACK CHIP PACKAGE WITH STATIC BENDS

COMPLIANT SPRING INTERPOSER FOR WAFER LEVEL THREE DIMENSIONAL (3D) INTEGRATION AND METHOD OF MANUFACTURING

The present invention is an apparatus for integrating multiple devices. The apparatus includes a substrate having a first via and a second via, a semiconductor chip positioned on a top portion of the substrate and positioned between the first via and the second via, first and second bumps positioned on the semiconductor chip, and an interposer wafer having a first interposer spring assembly and a second interposer spring assembly, the first interposer spring assembly having a first interposer spring and a first electrical connection attached to the first interposer spring, and the second interposer spring assembly having a second interposer spring and a second electrical connection attached to the second interposer spring.

HYBRIDIZATION FACE-TO-FACE TWO MICROELECTRONIC COMPONENTS USING ANNEALING UV

Technique for controlling positions of stacked dies

Technique for controlling positions of stacked dies

An assembly component and a technique for assembling a chip package using the assembly component are described. This chip package includes a set of semiconductor dies that are arranged in a stack in a vertical direction, which are offset from each other in a horizontal direction to define a stepped terrace at one side of the vertical stack. Moreover, the chip package may be assembled using the assembly component. In particular, the assembly component may include a pair of stepped terraces that approximately mirror the stepped terrace of the chip package and which provide vertical position references for an assembly tool that positions the set of semiconductor dies in the vertical stack during assembly of the chip package.

RAMP-STACK CHIP PACKAGE WITH STATIC BENDS

A ramp-stack chip package is described. This chip package includes a vertical stack of semiconductor dies or chips that are offset from each other in a horizontal direction, thereby defining a terrace with exposed pads. A high-bandwidth ramp component, which is positioned approximately parallel to the terrace, is electrically and mechanically coupled to the exposed pads. For example, the ramp component may be coupled to the semiconductor dies using: solder, microsprings and/or an anisotropic conducting film. Furthermore, each of the semiconductor dies includes a static bend so that an end segment of each of the semiconductor dies is parallel to the direction and is mechanically coupled to the ramp component. These end segments may facilitate high-bandwidth communication of signals between the chips and the ramp component, for example, via proximity communication.

RAMP-STACK CHIP PACKAGE WITH STATIC BENDS

Microelectronic element bonding with deformation of leads in rows

A method of making a microelectronic assembly includes bonding a plurality of lead connection sections arranged in a row to contacts of a microelectronic element such as a semiconductor chip having contacts in rows at the periphery of the chip. The leads have terminal sections secured to a dielectric support structure, and horizontally curved sections between the terminal regions and bond regions. After bonding, the dielectric support structure is lifted upwardly relative to the chip, so as to bend the leads into a vertically-extensive orientation. Partial straightening of the original horizontal curvature allows each lead to stretch and accommodate the vertical movement.

MULTI-CHIP PROGRAMMABLE LOGIC DEVICE HAVING CONFIGURABLE LOGIC CIRCUITRY AND CONFIGURATION DATA STORAGE ON DIFFERENT DICE

The circuitry of a programmable logic device (for example, an FPGA) includes a configurable logic portion and a configuration memory. The configuration memory stores configuration data that configures the configurable logic portion to realize a user-defined circuit. The configurable logic portion is disposed on a first die whereas the configuration memory is disposed on a second die. The second die is bonded to the first die in stacked relation. Each bit of configuration data passes from the second die to the first die through a pair of micropads. One micropad of the pair is disposed on the first die and the other micropad of the pair is disposed on the second die. When the first die and second die are brought together in face-to-face relation, the two micropads form an electrical connection through which the configuration data bit passes from the second die to the first die.

AREA ARRAY SEMICONDUCTOR DEVICE PACKAGE INTERCONNECT STRUCTURE WITH OPTIONAL PACKAGE-TO-PACKAGE OR FLEXIBLE CIRCUIT TO PACKAGE CONNECTION

An area array integrated circuit (IC) package for an IC device. The IC package includes a first substrate with conductive traces electrically coupled to the IC device. An interconnect assembly having a first surface is mechanically coupled to the first substrate. The interconnect assembly includes a plurality of contact members electrically coupled to the conductive traces on the first substrate. A second substrate is mechanically coupled to a second surface of the interconnect assembly so that the first substrate, the interconnect assembly, and the second substrate substantially surround the IC device. The second substrate includes conductive traces that are electrically coupled to the contact members in the interconnect assembly.

RAMP-STACK CHIP PACKAGE WITH STATIC BENDS

A ramp-stack chip package is described. This chip package includes a vertical stack of semiconductor dies or chips that are offset from each other in a horizontal direction, thereby defining a terrace with exposed pads. A high-bandwidth ramp component, which is positioned approximately parallel to the terrace, is electrically and mechanically coupled to the exposed pads. For example, the ramp component may be coupled to the semiconductor dies using: solder, microsprings and/or an anisotropic conducting film. Furthermore, each of the semiconductor dies includes a static bend so that an end segment of each of the semiconductor dies is parallel to the direction and is mechanically coupled to the ramp component. These end segments may facilitate high-bandwidth communication of signals between the chips and the ramp component, for example, via proximity communication.

고정 벤드를 구비한 램프 스택 칩 패키지

... 램프 스택 칩 패키지가 설명된다. 이 칩 패키지는 수평 방향으로 서로 오프셋된 반도체 다이 또는 칩들의 수직 스택을 포함하며, 이로써 노출된 패드를 구비한 테라스(terrace)를 정의한다. 테라스에 대략 평행하게 위치하는 고대역폭 램프 컴포넌트는 노출된 패드에 전기적으로 및 기계적으로 결합된다. 예를 들어, 램프 컴포넌트는 솔더(solder), 마이크로스프링(microspring), 및/또는 이방성 도전 필름(anisotropic conducting film)을 사용하여 반도체 다이들에 결합될 수 있다. 또한, 반도체 다이 각각은 반도체 다이 각각의 엔드 세그먼트가 그 방향에 평행하며, 램프 컴포넌트에 기계적으로 결합되도록 고정 벤드를 포함한다. 이들 엔드 세그먼트는 예를 들어, 근접 통신(proximity communication)을 통해 칩들과 램프 컴포넌트 사이의 신호의 고대역폭 통신을 용이하게 할 수 있다.

The slope of the static bending part of a stack chip package

Systems, methods and devices for inter-substrate coupling

Inter-substrate coupling and alignment using liquid droplets can include electrical and plasmon modalities. For example, a set of droplets can be placed on a bottom substrate. A top substrate can be placed upon the droplets, which uses the droplets to align the substrates. Using the droplets in a capacitive or plasmon coupling modality, information or power can be transferred between the substrates using the droplets.

KONTAKTIERUNGSSYSTEM FUER 2-POLIGE ELEKTRONISCHE BAUELEMENTE, INSBESONDERE HALBLEITERBAUELEMENTE

Microsprings partially embedded in a laminate structure and methods for producing same

At least one microspring has applied thereover a laminate structure to provide: mechanical protection during handling and wafer processing, a spring spacer layer, strengthening of the anchor between spring and substrate, provision of a gap stop during spring deflection, and moisture and contaminant protection. A fully-formed laminate structure may be applied over the microspring structure or a partly-formed laminate structure may be applied over the microspring structure then cured or hardened. The tip portion of the microspring may protrude through the laminate structure and be exposed for contact or may be buried within the contact structure. The laminate structure may remain in place in the final microspring structure or be removed in whole or in part. The laminate structure may be photolithographically patternable material, patterned and etched to remove some or all of the structure, forming for example additional structural elements such as a gap stop for the microspring.

MULTI-CHIP PROGRAMMABLE LOGIC DEVICE HAVING CONFIGURABLE LOGIC CIRCUITRY AND CONFIGURATION DATA STORAGE ON DIFFERENT DICE

The circuitry of a programmable logic device (for example, an FPGA) includes a configurable logic portion and a configuration memory. The configuration memory stores configuration data that configures the configurable logic portion to realize a user-defined circuit. The configurable logic portion is disposed on a first die whereas the configuration memory is disposed on a second die. The second die is bonded to the first die in stacked relation. Each bit of configuration data passes from the second die to the first die through a pair of micropads. One micropad of the pair is disposed on the first die and the other micropad of the pair is disposed on the second die. When the first die and second die are brought together in face-to-face relation, the two micropads form an electrical connection through which the configuration data bit passes from the second die to the first die.

MICROELECTRONIC CONTACT STRUCTURE AND METHOD OF MAKING SAME

Spring contact elements are fabricated by depositing at least one layer of metallic material into openings defined on a sacrificial substrate. The openings may be within the surface of the substrate, or in one or more layers deposited on the surface of the sacrificial substrate. Each spring contact element has a base end portion, a contact end portion, and a central body portion. The contact end portion is offset in the z-axis (at a different height) than the central body portion. The base end portion is preferably offset in an opposite direction along the z-axis from the central body portion. In this manner, a plurality of spring contact elements are fabricated in a prescribed spatial relationship with one another on the sacrificial substrate. The spring contact elements are suitably mounted by their base end portions to corresponding terminals on an electronic component, such as a space transformer or a semiconductor device, whereupon the sacrificial substrate is removed so that the contact ...

Ramp-stack chip package with static bends

A ramp-stack chip package is described. This chip package includes a vertical stack of semiconductor dies or chips that are offset from each other in a horizontal direction, thereby defining a terrace with exposed pads. A high-bandwidth ramp component, which is positioned approximately parallel to the terrace, is electrically and mechanically coupled to the exposed pads. For example, the ramp component may be coupled to the semiconductor dies using: solder, microsprings and/or an anisotropic conducting film. Furthermore, each of the semiconductor dies includes a static bend so that an end segment of each of the semiconductor dies is parallel to the direction and is mechanically coupled to the ramp component. These end segments may facilitate high-bandwidth communication of signals between the chips and the ramp component, for example, via proximity communication.

METHOD OF MOUNTING SEMICONDUCTOR PELLET

PURPOSE: To enable the correction of an inverted semiconductor pellet through magnetic field, by making one electrode of the pellet of a magnetic substance layer before a glass tube containing the pellet is put in a sealing jig and heated so that the tube and the pellet are integrated with each other. CONSTITUTION: A bump electrode 7 of Ag is provided on one of the obverse and reverse sides of a semiconductor pellet 5 and an electrode 8 is provided on the other side. The electrode 8 is made of a magnetic laminated layer of Cr, Ni and Ag. Lead members 3, 4 for a heat sink, which have slug leads 1, 2, are inserted into a glass tube 6. The tube is then put in a housing section 16 provided in a sealing jig 17 of graphite or the like. The jig 17 is electrically heated so that a projection 9 for holding the pellet 5 down is made on the inside surface of the tube 6 and the pellet and the tube are integrated with each other. An electromagnet 19 is provided on the lead 1 projecting from the jig ...

Electrical connector

An electrical connector for electrically connecting a first electronic element to a second electronic element includes an insulating body and multiple conductors. The insulating body has multiple accommodating holes. Each conductor is accommodated in a corresponding accommodating hole. Each conductor has an elastic insulator and low melting point liquid metal wrapping a surface of the elastic insulator, such that a continuous conducting path is formed by the liquid metal between the first electronic element and the second electronic element.

KONTAKTIERUNGSSYSTEM FUER 2-POLIGE ELEKTRONISCHE BAUELEMENTE, INSBESONDERE HALBLEITERBAUELEMENTE.

Systems, methods and devices for inter-substrate coupling

Inter-substrate coupling and alignment using liquid droplets can include electrical and plasmon modalities. For example, a set of droplets can be placed on a bottom substrate. A top substrate can be placed upon the droplets, which uses the droplets to align the substrates. Using the droplets in a capacitive or plasmon coupling modality, information or power can be transferred between the substrates using the droplets.

Multi-chip programmable logic device having configurable logic circuitry and configuration data storage on different dice

The circuitry of a programmable logic device (for example, an FPGA) includes a configurable logic portion and a configuration memory. The configuration memory stores configuration data that configures the configurable logic portion to realize a user-defined circuit. The configurable logic portion is disposed on a first die whereas the configuration memory is disposed on a second die. The second die is bonded to the first die in stacked relation. Each bit of configuration data passes from the second die to the first die through a pair of micropads. One micropad of the pair is disposed on the first die and the other micropad of the pair is disposed on the second die. When the first die and second die are brought together in face-to-face relation, the two micropads form an electrical connection through which the configuration data bit passes from the second die to the first die.

Compliant spring interposer for wafer level three dimensional (3D) integration and method of manufacturing

The present invention is an apparatus for integrating multiple devices. The apparatus includes a substrate having a first via and a second via, a semiconductor chip positioned on a top portion of the substrate and positioned between the first via and the second via, first and second bumps positioned on the semiconductor chip, and an interposer wafer having a first interposer spring assembly and a second interposer spring assembly, the first interposer spring assembly having a first interposer spring and a first electrical connection attached to the first interposer spring, and the second interposer spring assembly having a second interposer spring and a second electrical connection attached to the second interposer spring.

MICRO SPRING WHICH IS PARTLY BURIED WITHIN A LAMINATE STRUCTURE AND A MANUFACTURING METHOD THEREOF

PURPOSE: A micro spring and a manufacturing method thereof are provided to bury a fixed part inside of a laminate structure by forming a fixed part and a free part on the micro spring, thereby preventing mechanical damage. CONSTITUTION: One or more micro springs(12) are formed on a substrate. The micro spring comprises a fixed unit and a free part(14). The fixed part(16) is attached on the substrate. The fixed part is buried within a laminate structure. The laminate structure(30) comprises the micro spring which is partly buried within the laminate structure. COPYRIGHT KIPO 2012 ...

Microsprings partially embedded in a laminate structure

DETECTION DEVICE AND METHOD FOR MANUFACTURING THE SAME

A method for manufacturing a detection device includes the steps of providing bonding bumps on at least one of a light-receiving element array and a read-out circuit multiplexer, fixing a bump height adjusting member for adjusting the heights of the bumps to the light-receiving element array and/or the read-out circuit multiplexer on which the bumps are provided, and pressing a flat plate on the tops of the bumps and deforming the bumps until the flat plate comes in contact with the end of the bump height adjusting member.

Microsprings Partially Embedded In A Laminate Structure And Methods For Producing Same

At least one microspring has applied thereover a laminate structure to provide: mechanical protection during handling and wafer processing, a spring spacer layer, strengthening of the anchor between spring and substrate, provision of a gap stop during spring deflection, and moisture and contaminant protection. A fully-formed laminate structure may be applied over the microspring structure or a partly-formed laminate structure may be applied over the microspring structure then cured or hardened. The tip portion of the microspring may protrude through the laminate structure and be exposed for contact or may be buried within the contact structure. The laminate structure may remain in place in the final microspring structure or be removed in whole or in part. The laminate structure may be photolithographically patternable material, patterned and etched to remove some or all of the structure, forming for example additional structural elements such as a gap stop for the microspring.

Technique for controlling positions of stacked dies

Microelectronic contact structure

Spring contact elements are fabricated by depositing at least one layer of metallic material into openings defined on a sacrificial substrate. The openings may be within the surface of the substrate, or in one or more layers deposited on the surface of the sacrificial substrate. Each spring contact element has a base end portion, a contact end portion, and a central body portion. The contact end portion is offset in the z-axis (at a different height) than the central body portion. The base end portion is preferably offset in an opposite direction along the z-axis from the central body portion. In this manner, a plurality of spring contact elements are fabricated in a prescribed spatial relationship with one another on the sacrificial substrate. The spring contact elements are suitably mounted by their base end portions to corresponding terminals on an electronic component, such as a space transformer or a semiconductor device, whereupon the sacrificial substrate is removed so that the contact ...

Ramp-stack chip package with static bends

A ramp-stack chip package is described. This chip package includes a vertical stack of semiconductor dies or chips that are offset from each other in a horizontal direction, thereby defining a terrace with exposed pads. A high-bandwidth ramp component, which is positioned approximately parallel to the terrace, is electrically and mechanically coupled to the exposed pads. For example, the ramp component may be coupled to the semiconductor dies using: solder, microsprings and/or an anisotropic conducting film. Furthermore, each of the semiconductor dies includes a static bend so that an end segment of each of the semiconductor dies is parallel to the direction and is mechanically coupled to the ramp component. These end segments may facilitate high-bandwidth communication of signals between the chips and the ramp component, for example, via proximity communication.

Interposer with microspring contacts and methods of making and using same

An interposer including stress-engineered nonplanar microsprings may provide interconnection of bonding pads of electronic structures disposed above and below the interposer. The lateral offset between an anchor portion of a microspring disposed for contact at a bottom surface of the interposer and the tip of the microspring located in a free portion of the microspring for contact and deflection over a top surface of the interposer permits the interconnection of devices having different bonding pad pitches. Microspring contacts at the free portion permit temporary interconnection of devices, while solder applied over the free portion permit permanent connection of devices to the interposer.

FLIP-CHIP HYBRIDISATION OF TWO MICROELECTRONIC COMPONENTS USING A UV ANNEAL

This process for fabricating a microelectronic device comprising a first component (12) hybridised with a second component (14) by means of electrical interconnects consists in: producing first and second components (12, 14), the second component (14) being transparent to ultraviolet radiation at least in line with locations provided for the interconnects; forming interconnecting elements (22) comprising copper oxide on the second component (14) in the locations provided for the interconnects; placing the first and second components (12, 14) one on the other; and applying ultraviolet radiation, through the second component (14), to the elements comprising copper oxide so as to implement an ultraviolet anneal converting the copper oxide into copper.

Microelectronic element bonding with deformation of leads in rows

A method of making a microelectronic assembly includes bonding a plurality of lead connection sections arranged in a row to contacts of a microelectronic element such as a semiconductor chip having contacts in rows at the periphery of the chip. The leads have terminal sections secured to a dielectric support structure, and horizontally curved sections between the terminal regions and bond regions. After bonding, the dielectric support structure is lifted upwardly relative to the chip, so as to bend the leads into a vertically-extensive orientation. Partial straightening of the original horizontal curvature allows each lead to stretch and accommodate the vertical movement.

MICRO-COMPONENT WITH ANTI-STICTION STRUCTURES, AS WELL AS A DISPENSING METHOD USING THE SAME

Interposer with microspring contacts and structure

Method of producing an interposer with microspring contacts

An interposer including stress-engineered nonplanar microsprings may provide interconnection of bonding pads of electronic structures disposed above and below the interposer. The lateral offset between an anchor portion of a microspring disposed for contact at a bottom surface of the interposer and the tip of the microspring located in a free portion of the microspring for contact and deflection over a top surface of the interposer permits the interconnection of devices having different bonding pad pitches. Microspring contacts at the free portion permit temporary interconnection of devices, while solder applied over the free portion permit permanent connection of devices to the interposer.

Interposer with microspring contacts

An interposer including stress-engineered nonplanar microsprings may provide interconnection of bonding pads of electronic structures disposed above and below the interposer. The lateral offset between an anchor portion of a microspring disposed for contact at a bottom surface of the interposer and the tip of the microspring located in a free portion of the microspring for contact and deflection over a top surface of the interposer permits the interconnection of devices having different bonding pad pitches. Microspring contacts at the free portion permit temporary interconnection of devices, while solder applied over the free portion permit permanent connection of devices to the interposer.

Die attached leveling control by metal stopper bumps

In some embodiments, the present disclosure relates to an integrated chip (IC), including a substrate, a first die disposed over the substrate, a metal wire attached to a frontside of the first die, and a first plurality of die stopper bumps disposed along a backside of the first die and configured to control an angle of operation of the first die. The first plurality of die stopper bumps directly contacts a backside surface of the first die.

DEVICE FOR CONTACTING BIPOLAR ELECTRONIC CIRCUIT ELEMENT ANDPARTICULARLY SEMICONDUCTOR CIRCUIT ELEMENT

Semiconductor package with semiconductor die directly attached to lead frame and method

In one embodiment, a semiconductor package includes a semiconductor die having conductive pads. A lead frame is directly connected to the conductive pads using an electrochemically formed layer or a conductive adhesive layer thereby facilitating an electrical connection between the conductive pads of the semiconductor die and the lead frame without using separate wire bonds or conductive bumps.

Contacting system for bipolar electronic circuit elements, more particularly semiconductor circuit elements

In a contacting system for bipolar electronic circuit elements, more particularly semiconductor circuit elements, in which a circuit element body provided on at least one of two major surfaces located opposite each other with a thick, pressure-contact layer is held under pressure between two contact bodies interconnected by a housing, more particularly a soft glass housing. The risk of contact interruptions with frequent temperature variations in a range of from 0 DEG to 300 DEG C. is eliminated in that the thick pressure contact layers are subdivided into several contact blocks, preferably three or four, which are mutually separated and arranged beside each other. The surface of the contact blocks facing the contact bodies may be coated with a connection layer, which serves to establish during sealing into a soft glass envelope a connection by soldering or diffusion welding between the contact blocks and the contact bodies.

RAMP-STACK CHIP PACKAGE WITH STATIC BENDS

A ramp-stack chip package is described. This chip package includes a vertical stack of semiconductor dies or chips that are offset from each other in a horizontal direction, thereby defining a terrace with exposed pads. A high-bandwidth ramp component, which is positioned approximately parallel to the terrace, is electrically and mechanically coupled to the exposed pads. For example, the ramp component may be coupled to the semiconductor dies using: solder, microsprings and/or an anisotropic conducting film. Furthermore, each of the semiconductor dies includes a static bend so that an end segment of each of the semiconductor dies is parallel to the direction and is mechanically coupled to the ramp component. These end segments may facilitate high-bandwidth communication of signals between the chips and the ramp component, for example, via proximity communication.

Micro-component anti-stiction structures

A micro-component comprises a component substrate having a first side and an opposing second side. Fenders project from the first and second sides of the component substrate and include first-side fenders extending from the first side and a second-side fender extending from the second side of the component substrate. At least two of the first-side fenders have a non-conductive surface and are disposed closer to a corner of the component substrate than to a center of the component substrate.

Microsprings at least partially embedded in a laminate structure and methods for producing same

At least one microspring has applied thereover a laminate structure to provide: mechanical protection during handling and wafer processing, a spring spacer layer, strengthening of the anchor between spring and substrate, provision of a gap stop during spring deflection, and moisture and contaminant protection. A fully-formed laminate structure may be applied over the microspring structure or a partly-formed laminate structure may be applied over the microspring structure then cured or hardened. The tip portion of the microspring may protrude through the laminate structure and be exposed for contact or may be buried within the contact structure. The laminate structure may remain in place in the final microspring structure or be removed in whole or in part. The laminate structure may be photolithographically patternable material, patterned and etched to remove some or all of the structures, forming for example additional structural elements such as a gap stop for the microspring.

Connection components with rows of lead bond sections

A connection component for a microelectronic element includes a sheet-like support structure having top and bottom surfaces which extend in horizontal directions. The support structure includes a central region and a periphery surrounding the central region with terminals mounted on the central region of the support structure and exposed at the top surface thereof. A plurality of leads extend on the support structure with each lead having a terminal section connected to one of the terminals and attached to the bottom surface, a bond region and a horizontally curved section between the bond region and the terminal region. The bond regions of the leads are disposed side-by-side in one or more rows adjacent the periphery of the support structure. After the bond regions of the leads have been bonded to contacts of a microelectronic element, the support structure of the connection component is moveable upwardly so as to bend the curved sections of the leads.

SEMICONDUCTOR PACKAGE WITH SEMICONDUCTOR DIE DIRECTLY ATTACHED TO LEAD FRAME AND METHOD

In one embodiment, a semiconductor package includes a semiconductor die having conductive pads. A lead frame is directly connected to the conductive pads using an electrochemically formed layer or a conductive adhesive layer thereby facilitating an electrical connection between the conductive pads of the semiconductor die and the lead frame without using separate wire bonds or conductive bumps.

COMPLIANT SPRING INTERPOSER FOR WAFER LEVEL THREE DIMENSIONAL (3D) INTEGRATION AND METHOD OF MANUFACTURING

The present invention is an apparatus for integrating multiple devices. The apparatus includes a substrate having a first via and a second via, a semiconductor chip positioned on a top portion of the substrate and positioned between the first via and the second via, first and second bumps positioned on the semiconductor chip, and an interposer wafer having a first interposer spring assembly and a second interposer spring assembly, the first interposer spring assembly having a first interposer spring and a first electrical connection attached to the first interposer spring, and the second interposer spring assembly having a second interposer spring and a second electrical connection attached to the second interposer spring.

Detection device and method for manufacturing the same

A method for manufacturing a detection device includes the steps of providing bonding bumps on at least one of a light-receiving element array and a read-out circuit multiplexer, fixing a bump height adjusting member for adjusting the heights of the bumps to the light-receiving element array and/or the read-out circuit multiplexer on which the bumps are provided, and pressing a flat plate on the tops of the bumps and deforming the bumps until the flat plate comes in contact with the end of the bump height adjusting member.

Technique for controlling positions of stacked dies

An assembly component and a technique for assembling a chip package using the assembly component are described. This chip package includes a set of semiconductor dies that are arranged in a stack in a vertical direction, which are offset from each other in a horizontal direction to define a stepped terrace at one side of the vertical stack. Moreover, the chip package may be assembled using the assembly component. In particular, the assembly component may include a pair of stepped terraces that approximately mirror the stepped terrace of the chip package and which provide vertical position references for an assembly tool that positions the set of semiconductor dies in the vertical stack during assembly of the chip package.

Semiconductor package with semiconductor die directly attached to lead frame and method

Compliant spring interposer for wafer level three dimensional (3D) integration and method of manufacturing

The present invention is an apparatus for integrating multiple devices. The apparatus includes a substrate having a first via and a second via, a semiconductor chip positioned on a top portion of the substrate and positioned between the first via and the second via, first and second bumps positioned on the semiconductor chip, and an interposer wafer having a first interposer spring assembly and a second interposer spring assembly, the first interposer spring assembly having a first interposer spring and a first electrical connection attached to the first interposer spring, and the second interposer spring assembly having a second interposer spring and a second electrical connection attached to the second interposer spring.

Chip package, electronic computing device and method for communicating a signal

Microelectronic element bonding with deformation of leads in rows

A method of making a microelectronic assembly includes bonding a plurality of lead connection sections arranged in a row to contacts of a microelectronic element such as a semiconductor chip having contacts in rows at the periphery of the chip. The leads have terminal sections secured to a dielectric support structure, and horizontally curved sections between the terminal regions and bond regions. After bonding, the dielectric support structure is lifted upwardly relative to the chip, so as to bend the leads into a vertically-extensive orientation. Partial straightening of the original horizontal curvature allows each lead to stretch and accommodate the vertical movement.

Flip-chip hybridisation of two microelectronic components using a UV anneal

A method of manufacturing a microelectronic device including a first component hybridized with a second component via electric interconnects, involves the steps of: (i) forming the first and second components, the second component being transparent to ultraviolet radiation at least in line with locations provided for the interconnects; (ii) forming interconnection elements including copper oxide on the second component at the locations provided for the interconnects; (iii) placing the first and second components on each other; and (iv) applying the ultraviolet radiation through the second component on the elements including copper oxide to implement an ultraviolet anneal converting copper oxide into copper.

Systems, methods and devices for inter-substrate coupling

Inter-substrate coupling and alignment using liquid droplets can include electrical and plasmon modalities. For example, a set of droplets can be placed on a bottom substrate. A top substrate can be placed upon the droplets, which uses the droplets to align the substrates. Using the droplets in a capacitive or plasmon coupling modality, information or power can be transferred between the substrates using the droplets.

Interposer with microspring contacts and methods of making and using same

An interposer including stress-engineered nonplanar microsprings may provide interconnection of bonding pads of electronic structures disposed above and below the interposer. The lateral offset between an anchor portion of a microspring disposed for contact at a bottom surface of the interposer and the tip of the microspring located in a free portion of the microspring for contact and deflection over a top surface of the interposer permits the interconnection of devices having different bonding pad pitches. Microspring contacts at the free portion permit temporary interconnection of devices, while solder applied over the free portion permit permanent connection of devices to the interposer.

Variable width resilient conductive contact structures

Interconnect assemblies having resilient contact elements and methods for making these assemblies. In one aspect, the interconnect assembly includes a substrate and a resilient electrical contact element disposed on the substrate. A first portion of the resilient contact structure is disposed on the substrate and a second portion extends away from the substrate and is capable of moving from a first position to a second position under the application of a force. A stop structure is disposed on the surface of the substrate and on a surface of the first portion of the resilient contact structure. According to another aspect of the present invention, a beam portion of the resilient contact structure has a substantially triangular shape.

Multi-chip programmable logic device having configurable logic circuitry and configuration data storage on different dice

The circuitry of a programmable logic device (for example, an FPGA) includes a configurable logic portion and a configuration memory. The configuration memory stores configuration data that configures the configurable logic portion to realize a user-defined circuit. The configurable logic portion is disposed on a first die whereas the configuration memory is disposed on a second die. The second die is bonded to the first die in stacked relation. Each bit of configuration data passes from the second die to the first die through a pair of micropads. One micropad of the pair is disposed on the first die and the other micropad of the pair is disposed on the second die. When the first die and second die are brought together in face-to-face relation, the two micropads form an electrical connection through which the configuration data bit passes from the second die to the first die.

TECHNIQUE FOR CONTROLLING POSITIONS OF STACKED DIES

An assembly component and a technique for assembling a chip package using the assembly component are described. This chip package includes a set of semiconductor dies that are arranged in a stack in a vertical direction, which are offset from each other in a horizontal direction to define a stepped terrace at one side of the vertical stack. Moreover, the chip package may be assembled using the assembly component. In particular, the assembly component may include a pair of stepped terraces that approximately mirror the stepped terrace of the chip package and which provide vertical position references for an assembly tool that positions the set of semiconductor dies in the vertical stack during assembly of the chip package.

Area array semiconductor device package interconnect structure with optional package-to-package or flexible circuit to package connection

An area array integrated circuit (IC) package for an IC device. The IC package includes a first substrate with conductive traces electrically coupled to the IC device. An interconnect assembly having a first surface is mechanically coupled to the first substrate. The interconnect assembly includes a plurality of contact members electrically coupled to the conductive traces on the first substrate. A second substrate is mechanically coupled to a second surface of the interconnect assembly so that the first substrate, the interconnect assembly, and the second substrate substantially surround the IC device. The second substrate includes conductive traces that are electrically coupled to the contact members in the interconnect assembly.

DIE ATTACHED LEVELING CONTROL BY METAL STOPPER BUMPS

In some embodiments, the present disclosure relates to an integrated chip (IC), including a substrate, a first die disposed over the substrate, a metal wire attached to a frontside of the first die, and a first plurality of die stopper bumps disposed along a backside of the first die and configured to control an angle of operation of the first die. The first plurality of die stopper bumps directly contacts a backside surface of the first die.

ELECTRICAL CONNECTOR

An electrical connector for electrically connecting a first electronic element to a second electronic element includes an insulating body and multiple conductors. The insulating body has multiple accommodating holes. Each conductor is accommodated in a corresponding accommodating hole. Each conductor has an elastic insulator and low melting point liquid metal wrapping a surface of the elastic insulator, such that a continuous conducting path is formed by the liquid metal between the first electronic element and the second electronic element.

Electric connector

DIE ATTACHED LEVELING CONTROL BY METAL STOPPER BUMPS

In some embodiments, the present disclosure relates to an integrated chip including a substrate and a first die disposed over the substrate. A first plurality of die stopper bumps are disposed along a backside of the first die. The first plurality of die stopper bumps directly contact the backside of the first die, and the first plurality of die stopper bumps are arranged as a plurality of groups of die stopper bumps. A plurality of adhesive structures are also present. Each of the plurality of adhesive structures surrounds a corresponding group of the plurality of groups of die stopper bumps.

Multi-chip programmable logic device having configurable logic circuitry and configuration data storage on different dice

The circuitry of a programmable logic device (for example, an FPGA) includes a configurable logic portion and a configuration memory. The configuration memory stores configuration data that configures the configurable logic portion to realize a user-defined circuit. The configurable logic portion is disposed on a first die whereas the configuration memory is disposed on a second die. The second die is bonded to the first die in stacked relation. Each bit of configuration data passes from the second die to the first die through a pair of micropads. One micropad of the pair is disposed on the first die and the other micropad of the pair is disposed on the second die. When the first die and second die are brought together in face-to-face relation, the two micropads form an electrical connection through which the configuration data bit passes from the second die to the first die.

DETECTION DEVICE AND MANUFACTURING METHOD THEREOF

PROBLEM TO BE SOLVED: To provide a detection device that has good economical efficiency and also has high bonding yield while lowering a defective pixel rate, and a manufacturing method thereof. SOLUTION: The manufacturing method of the detection device includes the steps of: providing bumps 9b and 92b for bonding on at least one of a light receiving element array 50 and a multiplexer 70 of a readout circuit; fixing a bump height adjusting member 21 for adjusting a bump height to the light receiving element array and/or the readout circuit provided with the bumps; and pressing a flat plate 41 from tips of the bumps to deform the bumps until the flat plate abuts against the tip of the bump height adjusting member. COPYRIGHT: (C)2010,JPO&INPIT ...

Ramp-stack chip package with static bends

A ramp-stack chip package is described. This chip package includes a vertical stack of semiconductor dies or chips that are offset from each other in a horizontal direction, thereby defining a terrace with exposed pads. A high-bandwidth ramp component, which is positioned approximately parallel to the terrace, is electrically and mechanically coupled to the exposed pads. For example, the ramp component may be coupled to the semiconductor dies using: solder, microsprings and/or an anisotropic conducting film. Furthermore, each of the semiconductor dies includes a static bend so that an end segment of each of the semiconductor dies is parallel to the direction and is mechanically coupled to the ramp component. These end segments may facilitate high-bandwidth communication of signals between the chips and the ramp component, for example, via proximity communication.

For control of the position of the stacking bare chip technology

MICROSPRING AT LEAST PARTIALLY EMBEDDED IN LAMINATE STRUCTURE, AND MANUFACTURING METHOD THEREOF

PROBLEM TO BE SOLVED: To provide a microspring at least partially embedded in a laminate structure and manufacturing method thereof to provide the followings: mechanical protection during handling and wafer processing; strengthening of the anchor between spring and substrate; provision of a gap stop during spring deflection; and moisture and contaminant protection. SOLUTION: The laminate structure 30 is provided on at least one microspring 32 and then hardened. Here, the laminate structure 30 may be a fully-formed laminate structure or a partly-formed laminate structure applied over the microspring 32. The tip portion of the microspring may protrude through the laminate structure and be exposed for contact or may be buried within the contact structure. The laminate structure may be photolithographically patternable material, patterned and etched to remove some or all of the structure, forming for example other structural elements 10 such as a gap stop for the microspring. COPYRIGHT: (C) ...

Semiconductor-encapsulating adhesive, semiconductor-encapsulating film-form adhesive, method for producing semiconductor device, and semiconductor device

The present invention relates to a semiconductor-encapsulating adhesive, a semiconductor-encapsulating film-form adhesive, a method for producing a semiconductor device, and a semiconductor device. The present invention provides a semiconductor-encapsulating adhesive comprising (a) an epoxy resin, and (b) a compound formed of an organic acid reactive with an epoxy resin and a curing accelerator.

Integrated circuit tampering protection and reverse engineering prevention coatings and methods

A method of protecting an electronics package is discussed along with devices formed by the method. The method involves providing at least one electronic component that requires protecting from tampering and/or reverse engineering. Further, the method includes mixing into a liquid glass material at least one of high durability micro-particles or high-durability nano-particles, to form a coating material. Further still, the method includes depositing the coating material onto the electronic component and curing the coating material deposited.

Electronic element unit and reinforcing adhesive agent

It is an object of the present invention to provide an electronic element unit and a reinforcing adhesive agent in which a bonding strength can be improved between an electronic element and a circuit board and a repairing work can be carried out without giving a thermal damage to the electronic element or the circuit board. In an electronic element unit ( 1 ) including an electronic element ( 2 ) having a plurality of connecting terminals ( 12 ) on a lower surface thereof, a circuit board ( 3 ) having a plurality of electrodes ( 22 ) corresponding to the connecting terminals ( 12 ) on an upper surface thereof. The connecting terminals ( 12 ) and the electrodes ( 22 ) are connected by solder bumps ( 23 ), and the electronic element ( 2 ) and the circuit board ( 3 ) are partly bond by a resin bond part ( 24 ) made of a thermosetting material of a thermosetting resin, and a metal powder ( 25 ) is included in the resin bond parts ( 24 ) in a dispersed state. The metal powder ( 25 ) has a melting point lower than a temperature at which the resin bond parts ( 24 ) are heated when a work (a repairing work) is carried out for removing the electronic element ( 2 ) from the circuit board ( 3 ).

Tsv substrate structure and the stacked assembly thereof

The disclosure provides a TSV substrate structure and the stacked assembly of a plurality of the substrate structures, the TSV substrate structure including: a substrate comprising a first surface, a corresponding second surface, and a TSV communicating the first surface with the second surface through the substrate; and a conductor unit completely filling the TSV, the conductor unit comprising a conductor body which has a first and a second ends corresponding to the first and second surfaces of the substrate, respectively.

Semiconductor device and assembling method thereof

A semiconductor device and an assembling method thereof are provided. The semiconductor device includes a chip, a carrier, a plurality of first conductive elements and a plurality of second conductive elements. The chip has a plurality of first pads. The carrier has a plurality of second pads. The second pads correspond to the first pads. Each first conductive element is disposed between one of the first pads and one of the second pads. Each second conductive element is disposed between one of the first pads and one of the second pads. A volume ratio of intermetallic compound of the second conductive elements is greater than a volume ratio of intermetallic compound of the first conductive elements.

Direct Edge Connection for Multi-Chip Integrated Circuits

The present invention allows for direct chip-to-chip connections using the shortest possible signal path.

Ohmic connection using widened connection zones in a portable electronic object

The invention relates to portable electronic objects comprising an integrated circuit chip, and a mounting having two connection terminals for a circuit, as well as to a method for manufacturing such objects. The invention is characterized in that the chip is provided, on the active surface thereof, with two widened connection zones, in particular connection plates, said connection plates being positioned opposite said terminals and electrically connected, by ohmic contact, to the latter, and in that the surface defined by the connection plates, at the surface of the active integrated circuit having said plates, is greater than ½ of the surface of said surface. The invention can be used, in particular, for RFID objects.

Semiconductor device and method of fabricating the semiconductor device

A semiconductor device includes a first device including a first substrate and a first external connection terminal for connecting outside the first device; a second device stacked on the first device, the second device including a second substrate and a second external connection terminal for connecting outside the second device; an adhesive pattern disposed between the first device and second device, the adhesive pattern disposed in locations other than locations where the first external connection terminal and second external connection terminal are disposed, and the adhesive pattern causing the first device and second device, when stacked, to be spaced apart by a predetermined distance; and a plated layer disposed between and electrically and physically connecting the first external connection terminal and the second external connection terminal.

Chip package with plank stack of semiconductor dies

In a chip package, semiconductor dies in a vertical stack of semiconductor dies or chips (which is referred to as a ‘plank stack’) are separated by a mechanical spacer (such as a filler material or an adhesive). Moreover, the chip package includes a substrate at a right angle to the plank stack, which is electrically coupled to the semiconductor dies along an edge of the plank stack. In particular, electrical pads proximate to a surface of the substrate (which are along a stacking direction of the plank stack) are electrically coupled to pads that are proximate to edges of the semiconductor dies by an intervening conductive material, such as: solder, stud bumps, plated traces, wire bonds, spring connectors, a conductive adhesive and/or an anisotropic conducting film. Note that the chip package may facilitate high-bandwidth communication of signals between the semiconductor dies and the substrate.

Integrated circuit package system with removable backing element having plated terminal leads and method of manufacture thereof

A method of manufacture of an integrated circuit package system includes: attaching a first die to a first die pad; connecting electrically a second die to the first die through a die interconnect positioned between the first die and the second die; connecting a first lead adjacent the first die pad to the first die; connecting a second lead to the second die, the second lead opposing the first lead and adjacent the second die; and providing a molding material around the first die, the second die, the die interconnect, the first lead and the second lead, with a portion of the first lead exposed.

Contact Metal for Hybridization and Related Methods

A contact structure for interconnecting a first substrate to an indium interconnect structure on a second substrate. The contact structure comprises a diffusive layer and a non-oxidizing layer, with a thickness of less than approximately 150 nm, positioned on the diffusive layer for alignment with the indium interconnect.

Adhesive film for semiconductor device, film for backside of flip-chip semiconductor, and dicing tape-integrated film for backside of semiconductor

Provided is an adhesive film for a semiconductor device that is capable of having the same physical properties as these at the time of manufacture even after it is stored for a long time. The adhesive film for a semiconductor device of the present invention contains a thermosetting resin, and in which the amount of reaction heat generated in a temperature range of ±80° C. of a reaction heat peak temperature measured by a differential scanning calorimeter after the adhesive film is stored at 25° C. for 4 weeks is 0.8 to 1 time the amount of reaction heat generated before storage.

Semiconductor device, electronic device, and semiconductor device manufacturing method

A semiconductor device, includes: a connection member including a first pad formed on a principal surface thereof; a semiconductor chip including a circuit-formed surface on witch a second pad is formed, the chip mounted on the connection member so that the circuit-formed surface faces the principal surface; and a solder bump that connects the first and second pads and is made of metal containing Bi and Sn, wherein the bump includes a first interface-layer formed adjacent to the second pad, a second interface-layer formed adjacent to the first pad, a first intermediate region formed adjacent to either one of the interface-layers, and a second intermediate region formed adjacent to the other one of the interface-layers and formed adjacent to the first intermediate region; Bi-concentration in the first intermediate region is higher than a Sn-concentration; and a Sn-concentration in the second intermediate region is higher than a Bi-concentration.

System in package process flow

A method comprises connecting a substrate having a plurality of integrated circuit (IC) dies to a package substrate, so that the package substrate extends beyond at least two edges of the substrate, leaving first and second edge portions of the package substrate having exposed contacts. The first and second edge portions meet at a first corner of the package substrate. At least a first upper die package is placed over the substrate, so that first and second edge portions of the first upper die package extend beyond the at least two edges of the substrate. Pads on the first and second edge portions of the first upper die package are connected to the contacts of the first and second edge portions of the package substrate.

Packaging Process Tools and Systems, and Packaging Methods for Semiconductor Devices

Packaging process tools and systems, and packaging methods for semiconductor devices are disclosed. In one embodiment, a packaging process tool for semiconductor devices includes a mechanical structure for supporting package substrates or integrated circuit die during a packaging process for the integrated circuit die. The mechanical structure includes a low thermal conductivity material disposed thereon.

Method of processing solder bump by vacuum annealing

A method includes vacuum annealing on a substrate having at least one solder bump to reduce voids at an interface of the at least one solder bump. A die is mounted over the substrate.

Semiconductor device and method for manufacturing the same

A semiconductor device includes a first semiconductor chip including a first surface and a plurality of first electrodes disposed on the first surface; a second semiconductor chip including a second surface which faces the first surface, a plurality of second electrodes each of which includes at least one end disposed on the second surface, and a plurality of first protrusions each of which surrounds the one end of each of the second electrodes on an electrode by electrode basis; a plurality of conductive joint materials each of which joins a third electrode included in the first electrodes to the one end of an electrode which faces the third electrode among the second electrodes; and a plurality of first underfill resins each of which is disposed inside one of the first protrusions and covers one of the conductive joint materials on a material by material basis.

Bump Structure and Method of Forming Same

An embodiment bump on trace (BOT) structure includes a contact element supported by an integrated circuit, an under bump metallurgy (UBM) feature electrically coupled to the contact element, a metal bump on the under bump metallurgy feature, and a substrate trace on a substrate, the substrate trace coupled to the metal bump through a solder joint and intermetallic compounds, a ratio of a first cross sectional area of the intermetallic compounds to a second cross sectional area of the solder joint greater than forty percent.

Metal Bump and Method of Manufacturing Same

An embodiment bump structure includes a contact element formed on a substrate, a passivation layer overlying the substrate, the passivation layer having a passivation opening exposing the contact element a polyimide layer overlying the passivation layer, the polyimide layer having a polyimide opening exposing the contact element an under bump metallurgy (UMB) feature electrically coupled to the contact element, the under bump metallurgy feature having a UBM width, and a copper pillar on the under bump metallurgy feature, a distal end of the copper pillar having a pillar width, the UBM width greater than the pillar width.

Fixed-array anisotropic conductive film using conductive particles with block copolymer coating

Structures and manufacturing processes of an ACF array and more particularly a non-random particles are transferred to the array of microcavities of predetermined configuration, shape and dimension. The manufacturing process includes fluidic filling of conductive particles surface-treated with a block copolymer composition onto a substrate or carrier web comprising a predetermined array of microcavities. The thus prepared filled conductive microcavity array is then over-coated or laminated with an adhesive film.

ENHANCED CLEANING FOR WATER-SOLUBLE FLUX SOLDERING

An approach to provide an electronic assembly process that includes receiving at least one electronic assembly after a solder reflow process using a Sn-containing solder and a water-soluble flux. The approach includes baking the at least one electronic assembly in an oxygen containing environment and, then cleaning the at least one electronic assembly in an aqueous cleaning process. 1. A method for an electronic assembly process comprising:receiving at least one electronic assembly after a solder reflow process using a Sn-containing solder and a water-soluble flux;baking the at least one electronic assembly in an oxygen containing environment, andcleaning the at least one electronic assembly in an aqueous cleaning process.2. The method of claim 1 , further comprising baking the at least one electronic assembly in the oxygen containing environment within a range of temperatures from 40° Celsius to 180° Celsius.3. The method of claim 1 , further comprising baking the at least one electronic assembly in the oxygen containing environment for at least one of 60° Celsius for thirty minutes and 120° Celsius for three hours.4. The method of claim 1 , further comprising baking the at least one electronic assembly for a range of temperatures from 60° Celsius to 120° Celsius for a corresponding range of bake times from thirty minutes to three hours.5. The method of claim 1 , further comprising baking the at least one electronic assembly in an oxygen containing environment for a time less than thirty minutes with a baking temperature more than 120° Celsius.6. The method of claim 1 , further comprising baking the at least one electronic assembly in an oxygen containing environment for a time more than one hundred and eighty minutes with a baking temperature less than 60° Celsius.7. The method of claim 1 , wherein the water-soluble flux is any suitable water-soluble flux used in an electronic packaging assembly.8. The method of claim 1 , further comprises the water-soluble flux ...

Method and apparatus for manufacturing array device

A method for manufacturing an array device includes a placing step of providing a plurality of elements in an array on a first surface of a substrate, an element separating step of separating a plurality of element chips from one another so that each element chip includes one or more elements, an inspecting step of inspecting the plurality of elements, a removing step of removing any element chip of the plurality of element chips from the surface of the substrate on the basis of a result of the inspecting step, and a mounting step of, after the removing step, mounting an element of at least the elements other than an element of the element chip thus removed onto a mounting substrate by transfer from the substrate, the mounting substrate being different from the substrate.

Bonding apparatus and bonding method

[Solution] A bonding device 10 for thermally bonding an electronic component 100 to a substrate 110 or to another electronic component via an adhesive material 112, the bonding device being provided with: a bonding tool 40 comprising a bonding distal-end portion 42 which includes a bonding surface 44 and tapered side surfaces 46 formed in a tapering shape becoming narrower toward the bonding surface 44, the bonding surface 44 having a first suction hole 50 for suction-attaching the electronic component 100 via an individual piece of a porous sheet 130, the tapered side surfaces 46 having second suction holes 52, 54 for suction-attaching the porous sheet 130; and a bonding control unit 30 which controls the first suction hole 50 and the second suction holes 52, 54 independently from each other.

COMPONENT MOUNTING SYSTEM, RESIN SHAPING DEVICE, RESIN PLACING DEVICE, COMPONENT MOUNTING METHOD, AND RESIN SHAPING METHOD

A chip mounting system () includes: a chip supplying unit () for supplying a chip (CP); a stage () for holding a substrate (WT) in an orientation in which a mounting face (WTf) for mounting the chip (CP) faces vertically downward (−Z direction); a head (H) for holding the chip (CP) from the vertically downward direction (−Z direction); and a head drive unit () for, by causing vertically upward (+Z direction) movement of the head (H) holding the chip (CP), causes the head (H) to approach the stage () to mount the chip (CP) on the mounting face (WTf) of the substrate (WT). 1. A component mounting system for mounting a component on a substrate , the mounting system comprising:a component supplying unit configured to supply the component;a substrate holding unit configured to hold the substrate in an orientation such that a mounting face for mounting the component on the substrate is facing vertically downward;a head configured to hold the component from vertically below; anda head drive unit that, by causing vertically upward movement of the head holding the component, causes the head to approach the substrate holding unit to mount the component on the mounting face of the substrate.2. The component mounting system according to claim 1 , wherein the component supplying unit comprises (i) a sheet holding unit configured to hold a dicing substrate such that a sheet is positioned vertically upward of the dicing substrate claim 1 , the dicing substrate being the substrate diced and attached to the sheet claim 1 , and (ii) a picking mechanism configured to the component included in the dicing substrate by pick out vertically downward from vertically above the sheet.3. The component mounting system according to claim 1 , wherein the component mounting system further comprises a component conveying unit configured to convey the component supplied from the component supplying unit to a receiving position for the head to receive the component.4. The component mounting system ...

Semiconductor Device Package and Method

In an embodiment, a method includes: stacking a plurality of first dies to form a device stack; revealing testing pads of a topmost die of the device stack; testing the device stack using the testing pads of the topmost die; and after testing the device stack, forming bonding pads in the topmost die, the bonding pads being different from the testing pads.

3D Packaging Method for Semiconductor Components

The present disclosure relates to a method for bonding semiconductor components. A semiconductor component comprising microbumps on a planar bonding surface is prepared for bonding by applying a photosensitive polymer layer on the bonding surface. The average thickness of the initial polymer layer in between the microbumps is similar to the average height of the microbumps. In a lithography process, the polymer is removed from the upper surface of the microbumps and from areas around the microbumps. The polymer is heated to a temperature at which the polymer flows, resulting in a polymer layer that closely adjoins the microbumps, without exceeding the microbump height. The closely adjoining polymer layer may have a degree of planarity substantially similar to a planarized layer.

Electronic apparatus and method for fabricating the same

An electronic apparatus includes a first electronic part with a first terminal, a second electronic part with a second terminal opposite the first terminal, and a joining portion which joins the first terminal and the second terminal. The joining portion contains a pole-like compound extending in a direction in which the first terminal and the second terminal are opposite to each other. The joining portion contains the pole-like compound, so the strength of the joining portion is improved. When the first terminal and the second terminal are joined, the temperature of one of the first electronic part and the second electronic part is made higher than that of the other. A joining material is cooled and solidified in this state. By doing so, the pole-like compound is formed.

Semiconductor Device and Method

In an embodiment, a device includes: a first reflective structure including first doped layers of a semiconductive material, alternating ones of the first doped layers being doped with a p-type dopant; a second reflective structure including second doped layers of the semiconductive material, alternating ones of the second doped layers being doped with a n-type dopant; an emitting semiconductor region disposed between the first reflective structure and the second reflective structure; a contact pad on the second reflective structure, a work function of the contact pad being less than a work function of the second reflective structure; a bonding layer on the contact pad, a work function of the bonding layer being greater than the work function of the second reflective structure; and a conductive connector on the bonding layer.

MOUNTING DEVICE AND MOUNTING METHOD

A mounting device includes a thermocompression bonding head, a pressure reduction mechanism, and a resin sheet feed mechanism. The thermocompression bonding head is configured to heat a semiconductor chip while holding the semiconductor chip and to bond the semiconductor chip to a joined piece by compression. The thermocompression bonding head has a suction hole in a face that holds the semiconductor chip. The pressure reduction mechanism communicates with the suction hole and is configured to reduce pressure inside the suction hole. The resin sheet feed mechanism is configured to supply a resin sheet between the thermocompression bonding head and the semiconductor chip. An electrode that protrudes from a top face of the semiconductor chip is bonded by thermocompression after being embedded in the resin sheet. 1. A mounting device with which a semiconductor chip that has electrodes on top and bottom faces is bonded by thermocompression to a joined piece that is disposed on a lower side of the semiconductor chip and has an electrode on a top face , in a state in which a thermosetting adhesive is interposed between the semiconductor chip and the joined piece , the mounting device comprising:a thermocompression bonding head configured to heat the semiconductor chip while holding the semiconductor chip and to bond the semiconductor chip to the joined piece by compression, the thermocompression bonding head having a suction hole in a face that holds the semiconductor chip;a pressure reduction mechanism communicating with the suction hole and configured to reduce pressure inside the suction hole; anda resin sheet feed mechanism configured to supply a resin sheet between the thermocompression bonding head and the semiconductor chip,the electrode protruding from the top face of the semiconductor chip being bonded by thermocompression after being embedded in the resin sheet.2. The mounting device according to claim 1 , further comprisinga controller configured to set a ...

Substrate with embedded stacked through-silicon via die

A substrate with an embedded stacked through-silicon via die is described. For example, an apparatus includes a first die and a second die. The second die has one or more through-silicon vias disposed therein (TSV die). The first die is electrically coupled to the TSV die through the one or more through-silicon vias. The apparatus also includes a coreless substrate. Both the first die and the TSV die are embedded in the coreless substrate.

Bonding Package Components Through Plating

A method includes aligning a first electrical connector of a first package component to a second electrical connector of a second package component. With the first electrical connector aligned to the second electrical connector, a metal layer is plated on the first and the second electrical connectors. The metal layer bonds the first electrical connector to the second electrical connector.

ANISOTROPIC CONDUCTIVE FILM AND CONNECTED STRUCTURE

Anisotropic conductive films, each including an insulating adhesive layer and conductive particles insulating adhesive layer in a lattice-like manner. Among center distances between an arbitrary conductive particle and conductive particles adjacent to the conductive particle, the shortest distance to the conductive particle is a first center distance; the next shortest distance is a second center distance. These center distances are 1.5 to 5 times the conductive particles' diameter. The arbitrary conductive particle, conductive particle spaced apart from the conductive particle by the first center distance, conductive particle spaced apart from the conductive particle by first center distance or second center distance form an acute triangle. Regarding this acute triangle, an acute angle formed between a straight line orthogonal to a first array direction passing through the conductive particles and second array direction passing through conductive particles being 18 to 35°. These anisotropic conductive films have stable connection reliability in COG connection, 1when among center distances between an arbitrary conductive particle and conductive particles adjacent to the conductive particle, a shortest distance to the arbitrary conductive particle is defined as a first center distance, and a next shortest distance is defined as a second center distance,the first center distance and the second center distance are each 1.5 to 5 times a particle diameter of the conductive particles, and{'sub': 0', '1', '0', '2', '0', '0', '1', '1', '2, 'regarding an acute triangle formed by an arbitrary conductive particle P, a conductive particle Pspaced apart from the arbitrary conductive particle Pby the first center distance, and a conductive particle Pspaced apart from the arbitrary conductive particle Pby the first center distance or the second center distance, an acute angle a formed between a straight line orthogonal to a direction (hereinafter, referred to as a first array ...

Wiring board, electronic apparatus, and method for manufacturing electronic apparatus

A wiring board includes a substrate, an electrode on a surface of the substrate, a wall surface in a ring shape surrounding an outer circumference of the electrode, an upper end of the wall surface is located at a position higher than a surface of the electrode, and a protrusion at the upper end of the wall surface, the protrusion protruding with respect to the wall surface inward of a ring shape defined by the wall surface.

SEMICONDUCTOR DEVICE, ELECTRONIC DEVICE, AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD

A semiconductor device, includes: a connection member including a first pad formed on a principal surface thereof; a semiconductor chip including a circuit-formed surface on which a second pad is formed, the chip mounted on the connection member so that the circuit-formed surface faces the principal surface; and a solder bump that connects the first and second pads and is made of metal containing Bi and Sn, wherein the bump includes a first interface-layer formed adjacent to the second pad, a second interface-layer formed adjacent to the first pad, a first intermediate region formed adjacent to either one of the interface-layers, and a second intermediate region formed adjacent to the other one of the interface-layers and formed adjacent to the first intermediate region; Bi-concentration in the first intermediate region is higher than a Sn-concentration; and a Sn-concentration in the second intermediate region is higher than a Bi-concentration. 110-. (canceled)11. A semiconductor device manufacturing method , comprising:forming a first connection pad on a first principal surface of a first connection member;forming a second connection pad on a circuit-formed surface of a fast semiconductor chip on which a semiconductor integrated circuit is formed;placing the fast semiconductor chip on the first connection member in such a manner that the circuit-formed surface faces the first principal surface and the first connection pad contacts the second connection pad through a solder bump containing a Sn—Bi alloy;reflowing the solder bump for joining the first connection pad and the second connection pad; andapplying a direct current after the joining between the first connection pad and the second connection pads using either one of the first or second connection pad as an anode and using the other one of the first and second connection pads as cathode, so as to concentrate Bi in the solder bump into a neighborhood of the anode and to concentrate Sn in the solder bump into a ...

INTERCONNECTION JOINTS HAVING VARIABLE VOLUMES IN PACKAGE STRUCTURES AND METHODS OF FORMATION THEREOF

An embodiment method includes analyzing warpage characteristics of a first package component and a second package component and forming a plurality of solder paste elements on the first package component. A volume of each of the plurality of solder paste elements is based on the warpage characteristics of the first package component and the second package component. The method further includes aligning a plurality of connectors disposed on the second package component to the plurality of solder paste elements on the first package component and bonding the second package component to the first package component by reflowing the plurality of connectors and the plurality of solder paste elements. 1. A method comprising:analyzing warpage characteristics of a first package component and a second package component;forming a plurality of solder paste elements on the first package component, wherein a volume of each of the plurality of solder paste elements is based on the warpage characteristics of the first package component and the second package component, and wherein a first volume of a first one of the plurality of solder paste elements is different from a second volume of a second one of the plurality of solder paste elements;aligning a plurality of connectors disposed on the second package component to the plurality of solder paste elements on the first package component; andbonding the second package component to the first package component by reflowing the plurality of connectors and the plurality of solder paste elements.2. The method of claim 1 , wherein forming the plurality of solder paste elements comprises a stencil printing process using a stencil comprising a plurality of through-holes.3. The method of claim 2 , further comprising selecting a size for each of the plurality of through-holes based on the warpage characteristics of the first package component and the second package component.4. The method of wherein analyzing the warpage characteristics of ...

SYSTEMS AND METHODS FOR BONDING SEMICONDUCTOR ELEMENTS

A method of ultrasonically bonding semiconductor elements includes the steps of: (a) aligning surfaces of a plurality of first conductive structures of a first semiconductor element to respective surfaces of a plurality of second conductive structures of a second semiconductor element; (b) ultrasonically forming tack bonds between ones of the first conductive structures and respective ones of the second conductive structures; and (c) forming completed bonds between the first conductive structures and the second conductive structures. 1. A bonding system comprising:a support structure for supporting a first semiconductor element, the first semiconductor element including a plurality of first conductive structures;a bonding tool for carrying a second semiconductor element including a plurality of second conductive structures, and for applying ultrasonic energy to the second semiconductor element to form tack bonds between ones of the plurality of second conductive structures and corresponding ones of the plurality of first conductive structures.2. The bonding system of wherein claim 1 , after forming the tack bonds claim 1 , the bonding tool is configured to form completed bonds between the ones of the plurality of second conductive structures and corresponding ones of the plurality of first conductive structures.3. The bonding system of wherein the bonding tool is a heated bonding tool claim 2 , and the bonding tool applies heat to the second semiconductor element for forming the completed bonds.4. The bonding system of further comprising a second bonding tool claim 1 , wherein claim 1 , after forming the tack bonds by the bonding tool claim 1 , the second bonding tool is configured to form completed bonds between the ones of the plurality of second conductive structures and corresponding ones of the plurality of first conductive structures.5. The bonding system of wherein the second bonding tool is a heated bonding tool claim 4 , and the second bonding tool applies ...

Reinforcing resin composition, electronic component, method for manufacturing electronic component, mounting structure, and method for manufacturing mounting structure

A reinforcing resin composition includes an epoxy resin (A), a phenolic resin (B), and a benzoxazine compound (C).

Use of rfid chip as assembly facilitator

A method of assembling RFID components together while using an RFID chip that heats internally in order to assemble that RFID chip and another RFID component such as an antenna is followed while producing RFID assemblies or RFID devices. This RFID chip is associated with a member that has an electrical characteristic to develop heat internal of this RFID chip. An uncured adhesive is positioned between at least a portion of the RFID chip and a portion of the other RFID component. Action of the RFID chip internal member heats the RFID chip, heat emanating to the adhesive, resulting in adhesive curing into a cured adhesive joint attaching together the RFID chip and the other RFID component. This assembly is capable of being achieved without an external source of heat or pressure applied to the adhesive. Temperature monitoring is available to assess heat development in connection with threshold temperature designation.

Bump structural designs to minimize package defects

A method of forming a chip package includes providing a chip with a plurality of first bumps, wherein the plurality of first bumps has a first height. The method further includes providing a substrate with a plurality of second bumps, wherein the plurality of second bumps has a second height. The method further includes bonding the plurality of first bumps to the plurality of second bumps to form a first bump structure of the chip package, wherein the first bump structure has a standoff, wherein a ratio of a sum of the first height and the second height to the standoff is equal to or greater than about 0.6 and less than 1.

CHIP CARRIER AND METHOD THEREOF

A method may include providing a chip carrier having a chip supporting region to support a chip, and a chip contacting region having at least one contact pad, the chip carrier being thinner in the chip contacting region such that a first thickness of the chip carrier at the at least one contact pad is smaller than a second thickness of the chip carrier in the chip supporting region. A disposing of the chip, having at least one contact protrusion, over the chip carrier, such that the at least one contact protrusion is arranged over the at least one contact pad may be included. In addition, a pressing of the chip against the chip carrier such that the at least one contact protrusion extends at least partially into the chip contacting region and is electrically contacted to the at least one contact pad may be included. 1. A method , comprising: a chip supporting region configured to support a chip, and', 'a chip contacting region having at least one contact pad configured to electrically contact the chip,', 'the chip carrier being thinner in the chip contacting region such that a first thickness of the chip carrier at the at least one contact pad is smaller than a second thickness of the chip carrier in the chip supporting region;, 'providing a chip carrier, the chip carrier including'}disposing the chip including at least one contact protrusion over the chip carrier, such that the at least one contact protrusion is arranged over the at least one contact pad; andpressing the chip against the chip carrier such that the at least one contact protrusion extends at least partially into the chip contacting region and is electrically contacted to the at least one contact pad.2. The method of claim 1 ,wherein pressing the chip against the chip carrier includes displacing the at least one contact pad by deforming the chip carrier to form a recess for receiving the at least one contact protrusion.3. The method of claim 1 ,wherein pressing the chip against the chip carrier is ...

FLIP-CHIP ELECTRONIC DEVICE WITH CARRIER HAVING HEAT DISSIPATION ELEMENTS FREE OF SOLDER MASK

A solution relating to electronic devices of flip-chip type is provided, which includes at least one chip carrier having a carrier surface, the carrier(s) including one or more contact elements of electrically conductive material on the carrier surface, at least one integrated circuit chip having a chip surface, the chip(s) including one or more terminals of electrically conductive material on the chip surface each one facing a corresponding contact element, solder material soldering each terminal to the corresponding contact element, and a restrain structure around the contact elements for restraining the solder material during a soldering of the terminals to the contact elements. The carrier includes one or more heat dissipation elements of thermally conductive material on the carrier surface facing the chip surface displaced from the terminals, the dissipation elements being free of any solder mask. 1. An electronic device of a flip-chip type comprising:at least one chip carrier having a carrier surface, the at least one chip carrier comprising one or more contact elements of electrically conductive material on the carrier surface;at least one integrated circuit chip having a chip surface, the at least one integrated circuit chip comprising one or more terminals of electrically conductive material on the chip surface each one facing a corresponding contact element;solder material soldering each terminal to the corresponding contact element, and a restrain structure around the contact elements for restraining the solder material during a soldering of the terminals to the contact elements; andwherein the at least one chip carrier comprises one or more heat dissipation elements of thermally conductive material on the carrier surface facing the chip surface displaced from the terminals, the dissipation elements being free of any solder mask.2. The electronic device according to claim 1 , wherein the contact elements and the dissipation elements are portions of a ...

STRESS SENSOR FOR A SEMICONDUCTOR DEVICE

In a particular embodiment, an apparatus includes a stress sensor located on a first side of a semiconductor device. The apparatus further includes circuitry located on a second side of the semiconductor device. The stress sensor is configured to detect stress at the semiconductor device. In another particular embodiment, a method includes receiving data from a stress sensor located on a first side of a packaged semiconductor device. The packaged semiconductor device includes circuitry located on a second side of the packaged semiconductor device. The data indicates stress detected by the stress sensor. The method further includes performing a test associated with the packaged semiconductor device based on the data. 1. An apparatus comprising:a stress sensor located on a first side of a semiconductor device; andcircuitry located on a second side of the semiconductor device,wherein the stress sensor is configured to detect stress at the semiconductor device.2. The apparatus of claim 1 , wherein the stress sensor is configured to detect stress imposed on the circuitry.3. The apparatus of claim 2 , wherein the circuitry comprises an analog circuit.4. The apparatus of claim 1 , further comprising a package claim 1 , wherein the semiconductor device claim 1 , the stress sensor claim 1 , and the circuitry are integrated within the package.5. The apparatus of claim 4 , further comprising a second semiconductor device that is integrated within the package claim 4 , wherein the stress sensor is configured to detect stress imposed on the semiconductor device by the second semiconductor device.6. The apparatus of claim 1 , further comprising a connector formed on the second side of the semiconductor device claim 1 , the connector configured to couple the second side of the semiconductor device to a substrate via a flip chip process during an assembly process that connects the semiconductor device to the substrate.7. The apparatus of claim 6 , wherein the connector comprises a ...

STAMP WITH STRUCTURED POSTS

A stamp for micro-transfer printing includes a body and one or more posts extending from the body. At least one of the posts has a non-planar surface contour on the distal end of the post having a size, shape, or size and shape that accommodates a non-planar contact surface of a micro-transfer printable device. 1. A system for micro-transfer printing , comprising:an array of micro-transfer printable devices formed on or in a source substrate, each micro-transfer printable device having a non-planar contact surface; and a body; and', 'an array of posts extending from the body, wherein each post in the array of posts has a non-planar surface contour on the distal end of the post having at least one of a size and shape that corresponds to the non-planar contact surface of the micro-transfer printable device while picking up and transferring the micro-transfer printable device to the destination substrate with the micro-transfer printing stamp., 'a micro-transfer printing stamp for micro-transfer printing the micro-transfer printable devices from the source substrate to a destination substrate, the micro-transfer printing stamp comprising2. (canceled)3. The system of claim 1 , wherein the non-planar contact surface of each micro-transfer printable device comprises a three-dimensional surface.4. The system of claim 1 , wherein the non-planar contact surface of each micro-transfer printable device comprises one or more recesses.5. The system of claim 1 , wherein the non-planar contact surface of each micro-transfer printable device comprises a structured surface with minimum height variation across the surface of at least 10 nm or a maximum height variation of 20 μm.6. The system of claim 1 , wherein the non-planar contact surface of each micro-transfer printable device comprises a structured surface with a minimum height variation across the surface of at least 5 percent of the post height or a maximum height variation across the surface of less than or equal to 50 ...

LIGHT ENGINE ARRAY

The invention discloses a light engine array having at least an anode and a cathode comprising: a first type semiconductor layer; an active layer; and a second type semiconductor layer; a cathode electrode has a conductive metal layer in electrical contact with a portion of the first type semiconductor layer, and the second type semiconductor layer to form a short circuit structure in a common cathode region; and an anode electrode has the conductive metal layer and coupled to a portion of the first type semiconductor layer; wherein, the anode electrode is electrically isolated with the active layer and the second type semiconductor layer in a sub-pixel region. 1. A light engine array having at least an anode and a cathode comprising:a first type semiconductor layer;an active layer; anda second type semiconductor layer;a cathode electrode has a conductive metal layer in electrical contact with a portion of the first type semiconductor layer, and the second type semiconductor layer to form a short circuit structure in a common cathode region; andan anode electrode has the conductive metal layer and coupled to a portion of the first type semiconductor layer;wherein, the anode electrode is electrically isolated with the active layer and the second type semiconductor layer in a sub-pixel region.2. The light engine array according to claim 1 , further comprising:the surface of the cathode electrode and the surface of the anode electrode have substantial same level in the sub-pixel region and the common cathode region.3. The light engine array according to claim 1 , further comprising:a dam array coupled to the second type semiconductor layer in a street region to provide a uniform current spreading.4. The light engine array according to claim 1 , further comprising:a distributed Bragg reflector (DBR) formed on the bottom of the first type semiconductor layer to narrow an emitting light spectrum width to increase gamut of a display.5. The light engine array according to ...

FINGERPRINT SENSOR DEVICE AND METHOD

A fingerprint sensor package and method are provided. Embodiments include a sensor and a sensor surface material encapsulated within the fingerprint sensor package. An array of electrodes of the sensor are electrically connected using through vias that are located either in the sensor, in connection blocks separated from the sensor, or through connection blocks, or else connected through other connections such as wire bonds. A high voltage die is attached in order to increase the sensitivity of the fingerprint sensor.

SEMICONDUCTOR DEVICE ASSEMBLY WITH GRADED MODULUS UNDERFILL AND ASSOCIATED METHODS AND SYSTEMS

Underfill materials with graded moduli for semiconductor device assemblies, and associated methods and systems are disclosed. In one embodiment, the underfill material between a semiconductor die and a package substrate includes a matrix material, first filler particles with a first size distribution, and second filler particles with a second size distribution different than the first size distribution. Centrifugal force may be applied to the underfill material to arrange the first and second filler particles such that the underfill material may form a first region having a first elastic modulus and a second region having a second elastic modulus different than the first elastic modulus. Once the underfill material is cured, portions of conductive pillars coupling the semiconductor die with the package substrate may be surrounded by the first region, and conductive pads of the package substrate may be surrounded by the second region.

Process for manufacturing a surface-mount semiconductor device, and corresponding semiconductor device

A process for manufacturing surface-mount semiconductor devices, in particular of the Quad-Flat No-Leads Multi-Row type, comprising providing a metal leadframe, in particular a copper leadframe, which includes a plurality of pads, each of which is designed to receive the body of the device, the pads being separated from adjacent pads by one or more rows of wire-bonding contacting areas, outermost rows from among the one or more rows of wire-bonding contacting areas identifying, together with outermost rows corresponding to the adjacent pads, separation regions.

BRIDGE SUPPORT STRUCTURE

A module including a first semiconductor device, a second semiconductor device, a bridge support structure and a base substrate. The semiconductor devices each having first bonding pads having a first solder joined with the base substrate and the semiconductor devices each having second and third bonding pads joined to second and third bonding pads on the bridge support structure by a second solder and a third solder, respectively, on the second and third bonding pads; the semiconductor devices positioned adjacent to each other such that the bridge support structure joins to both of the semiconductor devices by the second and third solders wherein the third bonding pads are larger than the second bonding pads and the third bonding pads are at a larger pitch than the second bonding pads. 1. A module assembly comprising:a first semiconductor device, a second semiconductor device, a bridge support structure and a base substrate;the first semiconductor device and the second semiconductor device each having first bonding pads having a first solder joined with the base substrate and the first semiconductor device and the second semiconductor device each having second and third bonding pads joined to second and third bonding pads on the bridge support structure by a second solder and a third solder, respectively, on the second and third bonding pads wherein a composition of the second solder is different from a composition of the third solder;the first semiconductor device and the second semiconductor device positioned adjacent to each other such that the bridge support structure joins to both of the first semiconductor device and the second semiconductor device by the second and third solders wherein the third bonding pads are larger than the second bonding pads and the third bonding pads are at a larger pitch than the second bonding pads.2. The module assembly of wherein the bridge support structure is external to the first semiconductor device claim 1 , the second ...

SYSTEM AND METHODS FOR PRODUCING MODULAR STACKED INTEGRATED CIRCUITS

A system according to some examples herein includes a base chip which may include a plurality of attachment slots for attaching dies thereto. One or more of the attachment slots may be programmable attachment slots. The base chip may further include circuitry for interconnecting the dies attached to the base chip. For example, the base chip may include a plurality of cross bar switches, each of which is associated with respective ones of the plurality of attachment slots. The base chip may further include a configuration block, which is adapted to receive and transmit test signals for determining electrically connected signal lines of one or more attachment slots when one or more dies are attached to the base chip and which is further adapted to receive configuration data for programming signal (including power and ground) channels of the cross bar switches. 1. A system comprising: a plurality of attachment slots for attaching dies thereto;', 'a plurality of cross bar switches, each of the plurality of cross bar switches associated with respective ones of the plurality of attachment slots; and', 'a test and configuration block configured to receive and transmit test signals for determining electrically connected signal lines of one or more attachment slots when one or more dies are attached to the base chip and further configured to receive configuration data for programming one or more of the cross bar switches., 'a base chip including2. The system of claim 1 , wherein the test and configuration block comprises circuitry configured to generate the test signals for determining connectivity between metal contacts of the base chip and metal contacts of a die attached to the base chip.3. The system of claim 1 , wherein the test and configuration block comprises circuitry configured to determine connectivity between metal contacts of the base chip and metal contacts of a die attached to the base chip claim 1 , the metal contacts of the die having a different size or ...

Chip carrier, a device and a method

According to various embodiments, a chip carrier may include: a chip supporting region configured to support a chip; a chip contacting region including at least one contact pad for electrically contacting the chip; wherein the chip carrier is thinned in the chip contacting region such that a first thickness of the chip carrier at the at least one contact pad is smaller than a second thickness of the chip carrier in the chip supporting region.

Anisotropic conductive film structures

Anisotropic conductive film (ACF) structures and manufacturing methods for forming the same are described. The manufacturing methods include preventing clusters of conductive particles from forming between adjacent bonding pads and that are associated with electrical shorting of ACF structures. In some embodiments, the methods involve use of multiple layered ACF materials that include a non-electrically conductive layer that reduces the likelihood of formation of conductive particle clusters between bonding pads. In some embodiment, the methods include the use of ultraviolet sensitive ACF material combined with lithography techniques that eliminate conductive particles from between neighboring bonding pads. In some embodiments, the methods involve the use of insulation spacers that block conductive particles from entering between bonding pads. Any suitable combination of the described methods can be used.

Semiconductor device and production method therefor

An object of the invention is to provide a method for producing a conductive member having low electrical resistance, and the conductive member is obtained using a low-cost stable conductive material composition that does not contain an adhesive. A method for producing a semiconductor device in which silver or silver oxide provided on a surface of a base and silver or silver oxide provided on a surface of a semiconductor element are bonded, includes the steps of arranging a semiconductor element on a base such that silver or silver oxide provided on a surface of the semiconductor element is in contact with silver or silver oxide provided on a surface of the base, and bonding the semiconductor element and the base by applying heat having a temperature of 200 to 900° C. to the semiconductor device and the base.

CHIP PACKAGE STRUCTURE AND METHOD FOR FORMING THE SAME

A method for forming a chip package structure is provided. The method includes providing a wiring substrate. The method includes sequentially forming a nickel-containing layer and a gold-containing layer over the first pad. The method includes forming a conductive protection layer covering the gold-containing layer over the nickel-containing layer. The method includes bonding a chip to the wiring substrate through a conductive bump and a flux layer surrounding the conductive bump. The conductive bump is between the second pad and the chip. The method includes removing the flux layer while the conductive protection layer covers the nickel-containing layer. 1. A method for forming a chip package structure , comprising:providing a wiring substrate comprising a substrate, a first pad, a second pad, and an insulating layer, wherein the first pad and the second pad are respectively over a first surface and a second surface of the substrate, the insulating layer is over the first surface and partially covers the first pad, and the first pad is wider than the second pad;sequentially forming a nickel-containing layer and a gold-containing layer over the first pad;forming a conductive protection layer covering the gold-containing layer over the nickel-containing layer, wherein the conductive protection layer, the gold-containing layer, and the nickel-containing layer are made of different materials, and a first distance between a first top surface of the insulating layer and a second top surface of the first pad is greater than a second distance between a third top surface of the conductive protection layer and the second top surface;bonding a chip to the wiring substrate through a first conductive bump and a first flux layer surrounding the first conductive bump, wherein the first conductive bump is between and connected to the second pad and the chip; andremoving the first flux layer while the conductive protection layer covers the nickel-containing layer.2. The method for ...

CHIP PACKAGE STRUCTURE

A chip package structure is provided. The chip package structure includes a substrate. The chip package structure includes a chip over the substrate. The chip package structure includes a first bump and a first dummy bump between the chip and the substrate. The first bump is electrically connected between the chip and the substrate, the first dummy bump is electrically insulated from the substrate, the first dummy bump is between the first bump and a corner of the chip, and the first dummy bump is wider than the first bump. 1. A chip package structure , comprising:a substrate;a chip over the substrate; anda first bump and a first dummy bump between the chip and the substrate, wherein the first bump is electrically connected between the chip and the substrate, the first dummy bump is electrically insulated from the substrate, the first dummy bump is between the first bump and a corner of the chip, and the first dummy bump is wider than the first bump.2. The chip package structure as claimed in claim 1 , wherein the first dummy bump has a first strip portion and a second strip portion claim 1 , and the first strip portion is not parallel to the second strip portion.3. The chip package structure as claimed in claim 2 , wherein the chip has a first edge and a second edge claim 2 , the first edge and the second edge meet at the corner of the chip claim 2 , and the first strip portion is substantially parallel to the first edge.4. The chip package structure as claimed in claim 3 , wherein the second strip portion is substantially parallel to the second edge.5. The chip package structure as claimed in claim 1 , further comprising:an underfill layer between the chip and the substrate and between the first dummy bump and the substrate.6. The chip package structure as claimed in claim 1 , further comprising:a second bump between the first bump and the substrate; anda second dummy bump between the chip and the substrate, wherein the second dummy bump is connected to the ...

Methods and Apparatus for Package on Package Devices

Package on package (PoP) devices and methods of packaging semiconductor dies are disclosed. A PoP device is formed by connecting a top package and a bottom package together using a plurality of PoP connectors on the bottom package connected to corresponding connectors of the top package. The PoP device further comprises a plurality of dummy connectors contained in the bottom package and not connected to any corresponding connector in the top package. 1. A device comprising:a first substrate;a first die attached to a first surface of the first substrate;a second substrate attached to the first substrate, the first die being interposed between the first substrate and the second substrate;one or more signaling connectors interposed between the first substrate and the second substrate; andone or more dummy connectors interposed between the first substrate and the second substrate, the one or more dummy connectors not passing electrical signals between the first substrate and the second substrate, the one or more dummy connectors being connected to only one of first substrate and the second substrate.2. The device of claim 1 , further comprising one or more intermediate connectors electrically coupling the one or more signaling connectors to the second substrate.3. The device of claim 2 , wherein the one or more intermediate connectors comprise solder balls.4. The device of claim 1 , further comprising an encapsulant claim 1 , wherein the first die is exposed through the encapsulant.5. The device of claim 4 , wherein the encapsulant encircles the one or more dummy connectors and the one or more signaling connectors.6. The device of claim 1 , further comprising an encapsulant claim 1 , wherein the encapsulant covers an upper surface of the first die.7. The device of claim 1 , wherein a first dummy connector of the one or more dummy connectors is of a different size from a first signaling connector of the one or more signaling connectors.8. The device of claim 1 , wherein ...

MICRO-SELECTIVE SINTERING LASER SYSTEMS AND METHODS THEREOF

A microscale selective laser sintering (μ-SLS) that improves the minimum feature-size resolution of metal additively manufactured parts by up to two orders of magnitude, while still maintaining the throughput of traditional additive manufacturing processes. The microscale selective laser sintering includes, in some embodiments, ultra-fast lasers, a micro-mirror based optical system, nanoscale powders, and a precision spreader mechanism. The micro-SLS system is capable of achieving build rates of at least 1 cm/hr while achieving a feature-size resolution of approximately 1 μm. In some embodiments, the exemplified systems and methods facilitate a direct write, microscale selective laser sintering μ-SLS system that is configured to write 3D metal structures having features sizes down to approximately 1 μm scale on rigid or flexible substrates. The exemplified systems and methods may operate on a variety of material including, for example, polymers, dielectrics, semiconductors, and metals. 1. A system for additively producing a three-dimensional workpiece , the system comprising:an electromagnetic radiation source configured to coherently and intermittently emit an electromagnetic radiation beam; anda lens assembly having a plurality of micro-mirrors, collectively, forming a matrixed mirror array, each micro-mirror being configured to selectively direct the emitted electromagnetic radiation beam to a focus point on a sintering plane comprising a layer of particles to form one or a plurality of sintered layers, wherein each sintered layer is successively produced, in a layer-by-layer manner, to form the three-dimensional workpiece.2. The system of claim 1 , wherein the plurality of micro-mirrors direct the plurality of emitted electromagnetic radiation beams onto an area spanning a maximum cross-sectional profile of the three-dimensional workpiece.3. The system of claim 1 , comprising:a slot die coater, the slot die coater being configured to dispense a solvent having ...

Electronic device package and method for manufacturing the same

An electronic device package includes a circuit layer, a first semiconductor die, a second semiconductor die, a plurality of first conductive structures and a second conductive structure. The first semiconductor die is disposed on the circuit layer. The second semiconductor die is disposed on the first semiconductor die, and has an active surface toward the circuit layer. The first conductive structures are disposed between a first region of the second semiconductor die and the first semiconductor die, and electrically connecting the first semiconductor die to the second semiconductor die. The second conductive structure is disposed between a second region of the second semiconductor die and the circuit layer, and electrically connecting the circuit layer to the second semiconductor die.

Semiconductor Device and Method of Forming a POP Device with Embedded Vertical Interconnect Units

A semiconductor device has a substrate. A plurality of conductive vias is formed through the substrate. A conductive layer is formed over the substrate. An insulating layer is formed over conductive layer. A portion of the substrate is removed to expose the conductive vias. A plurality of vertical interconnect structures is formed over the substrate. A first semiconductor die is disposed over the substrate. A height of the vertical interconnect structures is less than a height of the first semiconductor die. An encapsulant is deposited over the first semiconductor die and the vertical interconnect structures. A first portion of the encapsulant is removed from over the first semiconductor die while leaving a second portion of the encapsulant over the vertical interconnect structures. The second portion of the encapsulant is removed to expose the vertical interconnect structures. A second semiconductor die is disposed over the first semiconductor die. 1. A semiconductor device , comprising:a substrate including a conductive via formed through the substrate;a modular interconnect unit including a vertical interconnect structure disposed over the substrate;a first semiconductor die disposed over the substrate adjacent to the modular interconnect unit; andan encapsulant deposited around the first semiconductor die and over modular interconnect unit with an opening in the encapsulant extending to the modular interconnect unit.2. The semiconductor device of claim 1 , further including a second semiconductor die disposed over the first semiconductor die with a bump of the second semiconductor die within the opening of the encapsulant to contact the vertical interconnect structure.3. The semiconductor device of claim 1 , further including a first interconnect structure disposed between the substrate and modular interconnect unit.4. The semiconductor device of claim 3 , further including a second interconnect structure disposed between the first interconnect structure and ...

Method and apparatus for manufacturing a semiconductor device including a plurality of semiconductor chips connected with bumps

A method for manufacturing a semiconductor device including a plurality of semiconductor chips includes steps of placing, on a first semiconductor chip, a second semiconductor chip, such that a plurality of bumps is located between the first semiconductor chip and the second semiconductor chip, determining a distance between the first semiconductor chip and the second semiconductor chip, and determining whether or not the distance is within a predetermined range and stopping placement of additional chips if the distance is determined to be outside the predetermined range.

APPARATUS FOR BONDING SEMICONDUCTOR CHIPS

A semiconductor chip bonding apparatus includes a bonding head to adsorptively pick up a semiconductor chip, a bonding stage supporting a substrate, the semiconductor chip to be bonded to the substrate on the bonding stage, a first camera to capture an image of the semiconductor chip and to obtain positional information regarding the semiconductor chip, a second camera to capture an image of the substrate and to obtain positional information regarding the substrate, a correction device structure at a first side surface of the bonding stage, the correction device structure including a correction substrate and at least one correction chip, and a bonding controller to control pick up of the at least one correction chip by the bonding head, mounting of the at least one correction chip on the correction substrate, and correcting of a bonding position. 1. A semiconductor chip bonding apparatus , comprising:a bonding head to adsorptively pick up a semiconductor chip;a bonding stage supporting a substrate, the semiconductor chip to be bonded to the substrate on the bonding stage;a first camera to capture an image of the semiconductor chip and to obtain positional information regarding the semiconductor chip;a second camera to capture an image of the substrate and to obtain positional information regarding the substrate;a correction device structure at a first side surface of the bonding stage, the correction device structure including a correction substrate and at least one correction chip; anda bonding controller to control pick up of the at least one correction chip by the bonding head, mounting of the at least one correction chip on the correction substrate, and correcting of a bonding position.2. The apparatus as claimed in claim 1 , wherein the correction device structure further comprises:a fixing unit, the at least one correction chip and the correction substrate being positioned on and fixed to the fixing unit; anda body unit connected to one side of the bonding ...

Apparatus and method for manufacturing semiconductor device

A manufacturing apparatus of a semiconductor device includes a stage, a head unit configured to face the stage, a driving unit configured to move the head unit towards and away from the stage, a heating unit configured to heat the head unit, and a control unit configured to control the driving unit to move the head unit away from the stage when the heating unit heats the head unit.

SEMICONDUCTOR PACKAGE STRUCTURE AND METHOD FOR MANUFACTURING THE SAME

A semiconductor package structure includes a semiconductor die surface having a narrower pitch region and a wider pitch region adjacent to the narrower pitch region, a plurality of first type conductive pillars in the narrower pith region, each of the first type conductive pillars having a copper-copper interface, and a plurality of second type conductive pillars in the wider pitch region, each of the second type conductive pillars having a copper-solder interface. A method for manufacturing the semiconductor package structure described herein is also disclosed. 1. A semiconductor package structure , comprising:a first carrier having a first surface, the first surface comprising a first region and a second region;a second carrier having a second surface opposing the first surface, the second surface comprising a third region corresponding to the first region and a fourth region corresponding to the second region;a plurality of first type conductive pillars between the first region of the first surface and the third region of the second surface; anda plurality of second type conductive pillars between the second region of the first surface and the fourth region of the second surface;wherein a contact resistance of each of the first type conductive pillars is lower than a contact resistance of each of the second type conductive pillars.2. The semiconductor package structure of claim 1 , wherein each of the plurality of first type conductive pillars comprises a copper-copper interface.3. The semiconductor package structure of claim 2 , wherein each of the plurality of second type conductive pillars comprises a copper-solder interface.4. The semiconductor package structure of claim 1 , wherein a pitch of the first type conductive pillars in the first region is smaller than a pitch of the second type conductive pillars in the second region.5. The semiconductor package structure of claim 4 , wherein the pitch of the first type conductive pillars in the first region is ...

Wafer level integration including design/co-design, structure process, equipment stress management and thermal management

A multi-layer wafer and method of manufacturing such wafer are provided. The method comprises applying at least one stress compensating polymer layer to at least one of two heterogeneous wafers and low temperature bonding the two heterogeneous wafers to bond the stress compensating polymer layer to the other of the two heterogeneous wafers to form a multi-layer wafer pair. The multi-layer wafer comprises two heterogeneous wafers, at least one of the heterogeneous wafers having a stress compensating polymer layer. The two heterogeneous wafers are low temperature bonded together to bond the stress compensating polymer layer to the other of the two heterogeneous wafers.

BONDING METHOD AND BONDED BODY

A bonding method of a first member and a second member includes: forming a first wire bonding bump () on a first electrode () arranged in the first member; forming a second wire bonding bump () on a second electrode arranged in the second member; and flattening a tip section of the second wire bonding bump to form a bump flat surface (). The tip section () of the first wire bonding bump and the bump flat surface () are pressure bonded to each other. 18-. (canceled)9. A bonding method comprising:forming a first wire bonding bump on a first electrode arranged in a first member;forming a second wire bonding bump on a second electrode arranged in a second member;flattening a tip section of the second wire bonding bump to form a bump flat surface; andpressure bonding the tip section of the first wire bonding bump and the bump flat surface.10. The bonding method according to claim 9 , wherein the tip section of the first wire bonding bump is not flattened before the pressure bonding.11. The bonding method according to claim 9 , wherein the flattening includes flattening the tip section of the second wire bonding bump by bringing the tip section of the second wire bonding bump in contact with a flat surface of a pushing member claim 9 , andwherein the flat surface of the pushing member is a surface of a silicon board.12. The bonding method according to claim 9 , further comprising:heating the second wire bonding bump such that the second wire bonding bump becomes hotter than the first wire bonding bump,wherein the pressure bonding includes pressure bonding the tip section of the first wire bonding bump and the bump flat surface of the second wire bonding bump softened by the heating.13. The bonding method according to claim 9 , further comprising:forming a third wire bonding bump on a third electrode arranged in the first member,wherein the tip section of the first wire bonding bump formed in the forming the first wire bonding bump and the tip section of the third wire ...

INTERCONNECT BUMP STRUCTURES FOR PHOTO DETECTORS

A method of assembling a photodetector assembly includes depositing bumps on a read out integrated circuit (ROIC) without depositing bumps on a photodiode array (PDA). The method includes assembling the PDA and ROIC together wherein each bump electrically interconnects the ROIC with a respective contact of the PDA. A photodetector assembly includes a PDA. A ROIC is assembled to the PDA, wherein the ROIC is electrically interconnected with the PDA through a plurality of electrically conductive bumps. Each bump is confined within a respective pocket between the ROIC and a respective contact of the PDA. The disclosed methods can enable focal plane array manufacturers to achieve low-cost production of ultra-fine pitch, large format imaging arrays. 1. A photodetector assembly comprising:a photodiode array (PDA); anda read out integrated circuit (ROIC) assembled to the PDA, wherein the ROIC is electrically interconnected with the PDA through a plurality of electrically conductive bumps, wherein each bump is confined within a respective pocket between the ROIC and a respective contact of the PDA.2. The assembly as recited in claim 1 , wherein each respective pocket is laterally bounded by edges of:a passivation layer of the ROIC, anda sidewall passivation layer of the PDA.3. The assembly as recited in claim 2 , wherein the sidewall passivation layer of the PDA includes an outer surface sub-layer that includes potassium.4. The assembly as recited in claim 1 , wherein the electrically conductive bumps include indium.5. The assembly as recited in claim 1 , wherein each bump has a dimension in a direction from the ROIC toward the PDA of as low as 1 μm or less.6. The assembly as recited in claim 1 , wherein the PDA has a pixel pitch size of 10 μm or less claim 1 , wherein each bump electrically connects one pixel pitch of the PDA to the ROIC.7. The assembly as recited in claim 1 , wherein each bump electrically connects one pixel of the PDA to the ROIC claim 1 , and wherein ...

Chip handling and electronic component integration

Small size chip handling and electronic component integration are accomplished using handle fixturing to transfer die or other electronic components from a full area array to a targeted array. Area array dicing of a thinned device wafer on a handle wafer/panel may be followed by selective or non-selective de-bonding of targeted die or electronic components from the handle wafer and optional attachment to a carrier such as a transfer head or tape. Alignment fiducials may facilitate precision alignment of the transfer head or tape to the device wafer and subsequently to the targeted array. Alternatively, the dies or other electronic elements are transferred selectively from either a carrier or the device wafer to the targeted array.

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

Even when a stiffener is omitted, the semiconductor device which can prevent the generation of twist and distortion of a wiring substrate is obtained. 1. A method of manufacturing a semiconductor device , comprising:(a) preparing a semiconductor chip having a main surface over which a plurality of pad electrodes are formed,wherein a plurality of metal bumps are formed on the plurality of pad electrodes, respectively;(b) mounting the semiconductor chip to a first main surface of a wiring substrate such that the main surface of the semiconductor chip faces to the first main surface of the wiring substrate and electrically connecting the plurality of pad electrodes of the semiconductor chip to a plurality of parts of wirings of the wiring substrate via the plurality of metal bumps, respectively;{'sub': '2', '(c) after the step (b), supplying Oplasma the semiconductor chip and the wiring substrate; and'}(d) after the step (c), pouring an under-filling resin between the main surface of the semiconductor chip and the first main surface of the wiring substrate.2. The method of manufacturing a semiconductor device according to claim 1 ,wherein, the step (b), each of the plurality of metal bumps of the semiconductor chip is electrically connected to each of the plurality of parts of the wirings of the wiring substrate in a state of being melted the plurality of metal bumps without flux.3. The method of manufacturing a semiconductor device according to claim 1 ,wherein an organic resin film is formed over the main surface of the semiconductor chip and first main surface of the wiring substrate. This Application is a Continuation Application of U.S. Ser. No. 14/338,175 filed Jul. 22, 2014; which is a Continuation of U.S. Ser. No. 14/044,497 filed Oct. 2, 2013 now U.S. Pat. No. 8,822,269; which is a Divisional of U.S. Ser. No. 13/863,241 filed Apr. 15, 2013, now U.S. Pat. No. 8,581,410; which is a Continuation of U.S. Ser. No. 13/648,876 filed Oct. 10, 2012 now U.S. Pat. No. 8, ...

Laser reflow apparatus and method for electronic components with micron-class thickness

Provided is a laser reflow apparatus for reflowing electronic components on a substrate disposed on a stage, the apparatus including: a laser emission unit comprised of a plurality of laser modules for emitting a laser beam having a flat top output profile in at least one section of the substrate on which the electronic components are disposed; a camera unit comprising at least one camera module for capturing a reflowing process of the electronic components performed by the laser beam; and a laser output control unit configured to generate a control signal for independently controlling the respective laser modules of the laser emission unit based on a signal output from the camera unit and apply the control signal to the laser emission unit.

METHOD FOR MANUFACTURING ELECTRONIC PACKAGE

The present disclosure provides a method for manufacturing an electronic package, with an electronic component bonded to a carrier structure by means of solder tips formed on conductive bumps, wherein the solder tips do not require a reflow process to be in contact with the carrier structure, thereby allowing the conductive bumps to have an adequate amount of solder tips formed thereon and thus precluding problems such as cracking and collapsing of the solder tips. 1. A method for manufacturing an electronic package , comprising:providing an electronic component and a carrier structure, with a plurality of conductive bumps formed on the electronic component and a solder tip formed on each of the conductive bumps; andbonding the electronic component to the carrier structure via the solder tips with the solder tips being brought into contact with the carrier structure and free from going through a reflow process.2. The method of claim 1 , wherein the electronic component is a semiconductor chip.3. The method of claim 1 , wherein the electronic component is a flip chip semiconductor chip.4. The method of claim 1 , further comprising claim 1 , before the solder tips are brought into contact with the carrier structure claim 1 , pre-heating the carrier structure to allow the carrier structure to become warped.5. The method of claim 4 , further comprising claim 4 , after the solder tips are brought into contact with the carrier structure claim 4 , performing a cooling process.6. (canceled)7. The method of claim 1 , further comprising claim 1 , after the solder tips are brought into contact with the carrier structure claim 1 , heating the electronic component to allow the solder tips to become melted.8. The method of claim 1 , wherein at least one of the conductive bumps and the solder tips is formed by electroplating.9. The method of claim 1 , wherein at least one of the conductive bumps and the solder tips is formed by screen printing.10. The method of claim 1 , wherein ...

Micro-transfer printing with volatile adhesive layer

A method of making a micro-transfer printed structure includes providing a destination substrate and a source substrate having one or more micro-transfer printable components. A layer of volatile adhesive is formed over the destination substrate and one or more components are micro-transfer printed from the source substrate onto the volatile adhesive layer at a non-evaporable temperature of the volatile adhesive layer. The volatile adhesive layer is then heated to an evaporation temperature to evaporate at least a portion of the volatile adhesive after micro-transfer printing. In certain embodiments, a micro-transfer printed structure includes a destination substrate having one or more metal contacts and one or more micro-transfer printable components having one or more component contacts disposed on the destination substrate with the metal contact aligned with the component contact. The metal contact can form an intermetallic bond with the component contact.

Thermocompression bonding of electronic components

A method for producing an electronic module includes providing a first substrate including at least one first electrical contacting surface, an electronic component including at least one second electrical contacting surface, and a first material layer made of a thermoplastic material including at least one recess extending through the material layer. The first substrate, the electronic component and the first material layer are arranged with the first material layer disposed between the first substrate and the electronic component, and the at least one first electrical contacting surface, the at least one second electrical contacting surface and the at least one recess aligned relative to one another. The first substrate, the electronic component and the material layer are thermocompression bonded. A joint formed between the at least one first electrical contacting surface and the at least one second electrical contacting surface is surrounded or enclosed by the first material layer.

Semiconductor device

A semiconductor device is provided. The semiconductor device can be manufactured with a reduced cost. The semiconductor device ( 1 D) includes, a substrate ( 100 D), which includes a main surface ( 101 D) and a recess ( 108 D) depressed from the main surface ( 101 D), and includes a semiconductor material; a wiring layer ( 200 D) in which at least a portion thereof is formed on the substrate ( 100 D); one or more first elements ( 370 D) accommodated in the recess ( 108 D); a sealing resin ( 400 D) covering at least a portion of the one or more first elements ( 370 D) and filled in the recess ( 108 D); and a plurality of columnar conductive portions ( 230 D) penetrating through the sealing resin ( 400 D) in the depth direction of the recess ( 108 D), and respectively connected with the portion of the wiring layer ( 200 D) that is formed at the recess ( 108 D).

Semiconductor packages

A semiconductor package includes a first substrate, a first flow channel and a second flow channel. The first flow channel is on the first substrate. The second flow channel is on the first substrate and in fluid communication with the first flow channel. The second flow channel is spaced from an inlet and an outlet of the first flow channel. The first flow channel and the second flow channel constitute a bonding region of the first substrate.

System and method to enhance solder joint reliability

A reliability cover that is disposed over at least one of an integrated circuit package and a Si die of the integrated circuit package is disclosed. The integrated circuit package is mountable to a printed circuit board via a plurality of solder balls. The reliability cover is configured to reduce a difference in a coefficient of thermal expansion between the integrated circuit package and the printed circuit board, and between the Si die and a substrate of the integrated circuit package by a threshold value.

MULTI-LAYER STAMP

A stamp for micro-transfer printing includes a support having a support stiffness and a support coefficient of thermal expansion (CTE). A pedestal layer is formed on the support, the pedestal layer having a pedestal layer stiffness that is less than the support stiffness and a pedestal layer coefficient of thermal expansion (CTE) that is different from the support coefficient of thermal expansion (CTE). A stamp layer is formed on the pedestal layer, the stamp layer having a body and one or more protrusions extending from the body in a direction away from the pedestal layer. The stamp layer has a stamp layer stiffness that is less than the support stiffness and a stamp layer coefficient of thermal expansion that is different from the support coefficient of thermal expansion. 1. A stamp for micro-transfer printing , comprising:a support having a support stiffness and a support coefficient of thermal expansion (CTE);a pedestal layer formed on the support, the pedestal layer having a pedestal layer stiffness that is less than the support stiffness and a pedestal layer coefficient of thermal expansion (CTE) that is different from the support coefficient of thermal expansion (CTE); anda stamp layer formed on the pedestal layer, the stamp layer having a body and one or more protrusions extending from the body in a direction away from the pedestal layer, the stamp layer having a stamp layer stiffness that is less than the support stiffness and a stamp layer coefficient of thermal expansion that is different from the support coefficient of thermal expansion.2. The stamp of claim 1 , wherein the pedestal layer is made of the same material as the stamp layer or wherein the pedestal layer comprises the same materials as the stamp layer but in different proportions.3. The stamp of or claim 1 , wherein at least one of the pedestal layer and the stamp layer is polydimethylsiloxane (PDMS).4. The stamp of any one of - claim 1 , wherein the support is glass claim 1 , metal claim 1 , ...

Metallic Interconnect, a Method of Manufacturing a Metallic Interconnect, a Semiconductor Arrangement and a Method of Manufacturing a Semiconductor Arrangement

A metallic interconnection and a semiconductor arrangement including the same are described, wherein a method of manufacturing the same may include: providing a first structure including a first metallic layer having protruding first microstructures; providing a second structure including a second metallic layer having protruding second microstructures; contacting the first and second microstructures to form a mechanical connection between the structures, the mechanical connection being configured to allow fluid penetration; removing one or more non-metallic compounds on the first metallic layer and the second metallic layer with a reducing agent that penetrates the mechanical connection and reacts with the one or more non-metallic compounds; and heating the first metallic layer and the second metallic layer at a temperature causing interdiffusion of the first metallic layer and the second metallic layer to form the metallic interconnection between the structures. 1. A method of forming a metallic interconnection between a first structure and a second structure , the method comprising:providing the first structure with a first metallic layer having first microstructures protruding from the first metallic layer;providing the second structure with a second metallic layer having second microstructures protruding from the second metallic layer;contacting the first microstructures and the second microstructures to form a mechanical connection between the first structure and the second structure, the mechanical connection being configured to allow fluid to penetrate the mechanical connection;removing one or more non-metallic compounds on the first metallic layer and the second metallic layer with a reducing agent that penetrates the mechanical connection and reacts with the one or more non-metallic compounds; andheating the first metallic layer and the second metallic layer at a temperature causing interdiffusion of the first metallic layer and the second metallic layer ...

SOLDER BUMP STRETCHING METHOD

A wafer-level pulling method includes securing a top holder to a plurality of chips. The method further includes securing a bottom holder to a wafer, wherein the plurality of chips are bonded to the wafer by a plurality of solder bumps. The method further includes softening the plurality of solder bumps. The method further includes stretching the plurality of softened solder bumps, wherein stretching the plurality of softened solder bumps comprises leveling the plurality of chips using a plurality of levelling devices separated from the plurality of chips, and a first levelling device of the plurality of levelling devices has a different structure from a second levelling device of the plurality of levelling devices. 1. A wafer-level pulling method , the method comprising:securing a top holder to a plurality of chips;securing a bottom holder to a wafer, wherein the plurality of chips are bonded to the wafer by a plurality of solder bumps;softening the plurality of solder bumps; andstretching the plurality of softened solder bumps, wherein stretching the plurality of softened solder bumps comprises leveling the plurality of chips using a plurality of levelling devices separated from the plurality of chips, and a first levelling device of the plurality of levelling devices has a different structure from a second levelling device of the plurality of levelling devices.2. The method of claim 1 , wherein the securing of the top holder to the plurality of chips comprises securing the top holder to the plurality of chips using a plurality of bonder heads claim 1 , and each bonder head of the plurality of bonder heads is secured to a corresponding chip of the plurality of chips.3. The method of claim 1 , wherein the securing of the top holder to the plurality of chips comprises securing the top holder to the plurality of chips using a plurality of bonder heads claim 1 , and each bonder head of the plurality of bonder heads comprises a corresponding levelling device of the at ...

MOUNTING STRUCTURE AND METHOD FOR MANUFACTURING SAME

A mounting structure includes a bonding material () that bonds second electrodes () of a circuit board () and bumps () of a semiconductor package (), the bonding material () being surrounded by a first reinforcing resin (). Moreover, a portion between the outer periphery of the semiconductor package () and the circuit board () is covered with a second reinforcing resin (). Even if the bonding material () is a solder material having a lower melting point than a conventional bonding material, high drop resistance is obtained. 1. A mounting structure comprising:a semiconductor package having first electrodes;a circuit board having second electrodes;a bonding material containing solder that is disposed between the second electrode and a bump formed on the first electrode and electrically bonds the bump and the second electrode;a first reinforcing resin covering a circumference of the bonding material; anda second reinforcing resin covering a portion between an outer periphery of the semiconductor package disposed on the circuit board and the circuit board,wherein a relationship is established: a melting point of the bump>a reaction starting temperature of the second reinforcing resin≧a reaction starting temperature of the first reinforcing resin>a melting point of the bonding material.2. The mounting structure according to claim 1 , wherein the bump contains a solder material.3. The mounting structure according to claim 1 , wherein the first reinforcing resin and the second reinforcing resin are in contact with each other.4. The mounting structure according to claim 1 , wherein the first reinforcing resin and the second reinforcing resin contain resin components with an identical composition and contain different curing agents.5. The mounting structure according to claim 1 , wherein the bump has an alloy composition of a Sn material claim 1 , and the bonding material is a Sn material.6. The mounting structure according to claim 1 , wherein the bump has an alloy ...

SEMICONDUCTOR PACKAGE AND FABRICATION METHOD THEREOF AND SUBSTRATE AND PACKAGING STRUCTURE

A method for fabricating a semiconductor package is disclosed, which includes the steps of: providing a first substrate; disposing a second substrate on the first substrate through a plurality of supporting elements, wherein the second substrate has at least a cleaning hole penetrating therethrough; and performing a cleaning process to clean space between the second substrate and the first substrate through the cleaning hole, thereby preventing a popcorn effect from occurring when the first substrate is heated and hence preventing delamination of the semiconductor package. Further, the cleaning hole facilitates to disperse thermal stresses so as to prevent warping of the first and second substrates during a chip-bonding or encapsulating process, thereby overcoming the conventional drawbacks of cracking of the supporting elements and a short circuit therebetween. 1. A method for fabricating a semiconductor package , comprising the steps of:providing a first substrate;disposing a second substrate on the first substrate through a plurality of supporting elements, wherein the second substrate has at least a cleaning hole penetrating therethrough; andperforming a cleaning process to clean space between the second substrate and the first substrate through the cleaning hole.2. The method of claim 1 , wherein the first substrate has at least a semiconductor element disposed thereon.3. The method of claim 1 , wherein the second substrate has a plurality of substrate units and the cleaning hole is formed at an edge of the substrate units.4. The method of claim 1 , wherein the second substrate further has a connecting portion formed between and connecting the substrate units.5. The method of claim 4 , wherein the connecting portion serves as a cutting path.6. The method of claim 4 , wherein the cleaning hole is formed on the connecting portion.7. The method of claim 1 , wherein the cleaning hole is of a cross shape claim 1 , a circular shape claim 1 , a strip shape or a ...

Interconnection Structure and Method of Forming Same

An embodiment bump on trace (BOT) structure includes a contact element supported by an integrated circuit, an under bump metallurgy (UBM) feature electrically coupled to the contact element, a metal ladder bump mounted on the under bump metallurgy feature, the metal ladder bump having a first tapering profile, and a substrate trace mounted on a substrate, the substrate trace having a second tapering profile and coupled to the metal ladder bump through direct metal-to-metal bonding. An embodiment chip-to-chip structure may be fabricated in a similar fashion. 1. A method of forming semiconductor device , the method comprising:mounting a substrate trace on a first substrate, the substrate trace having a first tapering profile; andcoupling a metal ladder bump on a second substrate and the substrate trace together through direct metal-to-metal bonding, the metal ladder bump having a second tapering profile, the first substrate and the second substrate being bonded without use of solder.2. The method of claim 1 , wherein mounting the substrate trace comprises using an electrolytic plating process.3. The method of claim 1 , wherein coupling the metal ladder bump and the substrate trace comprises using thermo-compression bonding.4. The method of claim 1 , further comprising subjecting the metal ladder bump and the substrate trace to an annealing processing using a temperature of about 100° C. to about 400° C. for about 1 hour to about 2 hours.5. The method of claim 1 , further comprising:forming a contact pad on the first substrate;forming one or more insulating layers over the contact pad, the one or more insulating layers having an opening exposing the contact pad; andforming an under bump metallization in the opening, the under bump metallization extending over an outermost surface of the one or more insulating layers, wherein the metal ladder bump is formed on the under bump metallization.6. The method of claim 5 , wherein the metal ladder bump extends into the opening ...

PACKAGING METHOD AND PACKAGE STRUCTURE OF WAFER-LEVEL SYSTEM-IN-PACKAGE

The present disclosure provides a wafer-level system-in-package (WLSiP) packaging method and a WLSiP package structure. The WLSiP package structure includes a device substrate including a substrate and a plurality of first chips on the substrate, an encapsulation layer, covering the device substrate, a plurality of second chips embedded in the encapsulation; and an electrical connection structure, electrically connecting at least one of the plurality of second chips with at least one of the plurality of first chips. The plurality of first chips and the plurality of second chips are staggered from each other. 1. A wafer-level system-in-package (WLSiP) package structure , comprising:a device substrate, including a substrate and a plurality of first chips on the substrate;an encapsulation layer, covering the device substrate;a plurality of second chips embedded in the encapsulation layer; andan electrical connection structure, electrically connecting at least one second chip of the plurality of second chips with at least one first chip of the plurality of first chips, wherein the plurality of first chips and the plurality of second chips are staggered from each other.2. The package structure of claim 1 , wherein the electrical connection structure comprises:plugs formed in the substrate and electrically connected to the plurality of first chips.3. The package structure of claim 2 , wherein the electrical connection structure further comprises:a rewiring between the plurality of first chips and the plurality of second chips or placed on tops of the plugs.4. The package structure of claim 3 , wherein the electrical connection structure further comprises:at least one conductive bump formed between the rewiring and the plurality of second chips.5. The package structure of wherein:the substrate has a front side and a back side, andthe encapsulating layer covers one of the front side and the back side of the substrate.6. The package structure of claim 2 , further comprising: ...

CHIP PACKAGE STRUCTURE WITH METAL-CONTAINING LAYER

A chip package structure is provided. The chip package structure includes a first wiring substrate including a substrate, a first pad, a second pad, and an insulating layer. The chip package structure includes a nickel-containing layer over the first pad. The chip package structure includes a conductive protection layer over the nickel-containing layer. The conductive protection layer includes tin, and a recess is surrounded by the conductive protection layer and the insulating layer over the first pad. The chip package structure includes a chip over the second surface of the substrate. The chip package structure includes a conductive bump between the second pad and the chip. 1. A chip package structure , comprising:a first wiring substrate comprising a substrate, a first pad, a second pad, and an insulating layer, wherein the first pad and the second pad are respectively over a first surface and a second surface of the substrate, the insulating layer is over the first surface and partially covers the first pad, and the first pad is wider than the second pad;a nickel-containing layer over the first pad;a conductive protection layer over the nickel-containing layer, wherein the conductive protection layer comprises tin, and a recess is surrounded by the conductive protection layer and the insulating layer over the first pad;a chip over the second surface of the substrate; anda conductive bump between the second pad and the chip.2. The chip package structure as claimed in claim 1 , further comprising:a second wiring substrate, wherein the first wiring substrate is over the second wiring substrate, the second wiring substrate comprises a second substrate and a resilient contact structure mounted to the second substrate, and the resilient contact structure is in direct contact with the conductive protection layer.3. The chip package structure as claimed in claim 2 , wherein the resilient contact structure is a resilient metal strip.4. The chip package structure as ...

DIE ATTACHED LEVELING CONTROL BY METAL STOPPER BUMPS

In some embodiments, the present disclosure relates to an integrated chip (IC), including a substrate, a first die disposed over the substrate, a metal wire attached to a frontside of the first die, and a first plurality of die stopper bumps disposed along a backside of the first die and configured to control an angle of operation of the first die. The first plurality of die stopper bumps directly contacts a backside surface of the first die. 1. An integrated chip (IC) , comprising:a substrate;a first die disposed over the substrate;a metal wire attached to a frontside of the first die; anda first plurality of die stopper bumps disposed along a backside of the first die, wherein the first plurality of die stopper bumps directly contacts the backside of the first die.2. The IC of claim 1 , further comprising:a housing structure disposed over the first die and surrounding sidewalls of the first die; anda plurality of housing stopper bumps directly contacting and disposed between the housing structure and the substrate, wherein the plurality of housing stopper bumps contacts a bottom surface of the housing structure and is configured to control an angle of operation of the housing structure.3. The IC of claim 2 , further comprising:a plurality of metal pads disposed along a lateral portion of an inner surface of the housing structure, wherein the lateral portion of the inner surface is above the bottom surface, wherein the backside of the first die is above the frontside of the first die, wherein the metal wire is attached to the plurality of metal pads, and wherein the first plurality of die stopper bumps directly contacts the plurality of metal pads.4. The IC of claim 1 , wherein each of the first plurality of die stopper bumps comprises a solder ball bump.5. The IC of claim 1 , wherein each of the first plurality of die stopper bumps comprises a stud bump claim 1 , wherein the stud bump comprises a lower portion and an upper portion claim 1 , wherein the lower ...

MODULE AND METHOD OF MANUFACTURING MODULE

A module includes a substrate, a plurality of components on an upper surface of the substrate, a component on a lower surface of the substrate, solder balls on the lower surface, sealing resin layers stacked on the upper surface and the lower surface of the substrate, and a shield film covering a side surface and an upper surface of the module. Part of each solder ball is exposed from a surface of the sealing resin layer, and the exposed parts are shaped to protrude from the sealing resin layer. The module can be connected to a mother substrate by connecting the protruding parts of the solder balls. There are gaps between the solder balls and the sealing resin layer, and the occurrence of cracks in the solder balls can be suppressed by reducing stress arising from a difference in thermal expansion coefficient between the solder and the resin. 1. A module comprising:a substrate;a connection electrode that is provided on one main surface of the substrate;a first component that is mounted on the one main surface of the substrate;an external connection terminal comprising a solder ball disposed on the one main surface of the substrate with the connection electrode interposed between the solder ball and the substrate; anda sealing resin layer that is provided on the one main surface of the substrate and seals the one main surface of the substrate and the first component;wherein part of the external connection terminal is exposed from a surface of the sealing resin layer that is opposite from a surface of the sealing resin layer facing the one main surface of the substrate,a height of the external connection terminal from the one main surface of the substrate is larger than a height of the sealing resin layer from the one main surface of the substrate,there is a gap between the external connection terminal and the sealing resin layer, anda surface of the sealing resin layer, which faces and surrounds the external connection terminal, is a curved surface that has a curved ...

Method for bonding semiconductor components

A method of bonding semiconductor components is described. In one aspect a first component, for example a semiconductor die, is bonded to a second component, for example a semiconductor wafer or another die, by direct metal-metal bonds between metal bumps on one component and corresponding bumps or contact pads on the other component. In addition, a number of solder bumps are provided on one of the components, and corresponding contact areas on the other component, and fast solidified solder connections are established between the solder bumps and the corresponding contact areas, without realizing the metal-metal bonds. The latter metal-metal bonds are established in a heating step performed after the soldering step. This enables a fast bonding process applied to multiple dies bonded on different areas of the wafer and/or stacked one on top of the other, followed by a single heating step for realizing metal-metal bonds between the respective dies and the wafer or between multiple stacked dies. The method allows to improve the throughput of the bonding process, as the heating step takes place only once for a plurality of dies and/or wafers.

METHOD FOR SHAPING A LAMINATE SUBSTRATE

A method including providing a laminate substrate, characterizing the laminate substrate for warpage characteristics, determining a horizontal plane distortion based on the warpage characteristics, and placing the laminate substrate into a fixture with an adjustment to correct the horizontal plane distortion, the adjustment being located in a center of the laminate substrate, wherein the adjustment contacts the laminate substrate. The method may further include fluxing the laminate substrate, placing a chip onto the laminate substrate, and placing the fixture into a reflow furnace to join the chip and the laminate substrate. 1. A method comprising:providing a laminate substrate;characterizing the laminate substrate for warpage characteristics;determining a horizontal plane distortion based on the warpage characteristics;placing the laminate substrate into a fixture with an adjustment to correct the horizontal plane distortion, the adjustment being located in a center of the laminate substrate, wherein the adjustment contacts the laminate substrate;fluxing the laminate substrate;placing a chip onto the laminate substrate; andplacing the fixture into a reflow furnace to join the chip and the laminate substrate.2. The method according to claim 1 , wherein the laminate substrate is characterized by using room temperature techniques.3. The method according to claim 1 , wherein the laminate substrate is characterized by using elevated temperature techniques.4. The method according to claim 1 , wherein the adjustment includes placing a shim between the fixture and the laminate substrate.5. The method according to claim 1 , further comprising removing the fixture from the reflow furnace and performing a warpage measurement on the joined chip and laminate substrate.6. The method according to claim 5 , wherein the warpage measurement is performed using room temperature techniques.7. The method according to claim 5 , wherein the warpage measurement is performed using elevated ...

METHOD FOR PRODUCING A CHIP MODULE

The invention concerns a method for producing a chip module having a carrier substrate and at least one chip arranged on the carrier substrate, as well as a contact conductor arrangement for connecting chip pads to contacts arranged on a contact face of the chip module, in which method the front face of the chip which is provided with the chip pads is secured to the carrier substrate and then the contact conductor arrangement is formed by structuring of a contact material layer of the carrier substrate. 1. A method for producing a chip module having a carrier substrate and at least one chip arranged on the carrier substrate , as well as a contact conductor arrangement for connecting chip terminal faces with terminal contacts arranged on a contact side of the chip module , in which method the chip is secured on the carrier substrate with its front side provided with the chip terminal faces and subsequently the forming of the contact conductor arrangement is effected by means of a structuring of a contact material layer of the carrier substrate ,wherein before the forming of the contact conductor arrangement for forming a cladding material layer encasing the chip, a cladding material is applied onto the carrier substrate,the cladding material layer is provided with at least one contact recess, starting from its upper side, said contact recess exposing the contact material for forming a contact surface on the contact material layer of the carrier substrate,the contact recess is backfilled with contact material for forming a contact column,and the cladding material layer is treated by material abrasion, starting from its upper side, for exposing a rear side of the chip, in such a way that the rear side of the chip and the contact column are aligned flush in a cladding material surface produced by said treatment,a contact material layer is applied onto the rear side of the chip and onto the cladding material surface,and the contact material layer is structured for ...

SYSTEMS AND METHODS FOR PACKAGE ON PACKAGE THROUGH MOLD INTERCONNECTS

Discussed generally herein are methods and devices for more reliable Package on Package (PoP) Through Mold Interconnects (TMIs). A device can include a first die package including a first conductive pad on or at least partially in the first die package, a dielectric mold material on the first die package, the mold material including a hole therethrough at least partially exposing the pad, a second die package including a second conductive pad on or at least partially in the second die package the second die package on the mold material such that the second conductive pad faces the first conductive pad through the hole, and a shape memory structure in the hole and forming a portion of a solder column electrical connection between the first die package and the second die package. 1. A device comprising:a first die package including a first conductive pad on or at least partially in the first die package;a dielectric mold material on the first die package, the mold material including a hole therethrough, the hole at least partially exposing the first conductive pad;a second die package including a second conductive pad on or at least partially in the second die package, the second die package on the mold material such that the second conductive pad faces the first conductive pad through the hole; anda shape memory structure in the hole and forming a portion of a solder column electrical connection between the first die package and the second die package, the shape memory structure formed of a shape memory alloy material that, when heated above an austenite temperature, reverts to a programmed shape.2. The device of claim 1 , wherein the shape memory structure includes a spring that is configured to expand in austenite phase claim 1 , the shape memory alloy material that includes two or more of nickel claim 1 , titanium claim 1 , silver claim 1 , cadmium claim 1 , copper claim 1 , aluminum claim 1 , tin claim 1 , iron claim 1 , zinc claim 1 , silicon claim 1 , platinum ...

Micro-led display panel and manufacturing method thereof

A micro-LED display panel including a substrate, an anisotropic conductive film, and a plurality of micro-LEDs is provided. The anisotropic conductive film is disposed on the substrate. The micro-LEDs and the anisotropic conductive film are disposed at the same side of the substrate, and the micro-LEDs are electrically connected to the substrate through the anisotropic conductive film. Each of the micro-LEDs includes an epitaxial layer and an electrode layer electrically connected to the epitaxial layer, and the electrode layers comprises a first electrode and a second electrode which are located between the substrate and the corresponding epitaxial layer. A ratio of a thickness of each of the electrode layers to a thickness of the corresponding epitaxial layer ranges from 0.1 to 0.5, and a gap between the first electrode and the second electrode of each of the micro-LEDs is in a range of 1 μm to 30 μm.

Semiconductor device and method of manufacturing the same

A semiconductor chip includes a chip body and a plurality of solder-including electrodes provided on an element-formation surface of the chip body. A packaging substrate includes a substrate body, and a plurality of wirings and a solder resist layer that are provided on a front surface of the substrate body. The plurality of solder-including electrodes include a plurality of first electrodes and a plurality of second electrodes. The plurality of first electrodes supply a first electric potential, and the plurality of second electrodes supply a second electric potential different from the first electric potential. The plurality of first electrodes and the plurality of second electrodes are disposed alternately in both a row direction and a column direction, in a central part of the chip body. The plurality of wirings include a plurality of first wirings and a plurality of second wirings. The plurality of first wirings connect the plurality of first electrodes, and the plurality of second wirings connect the plurality of second electrodes.

Light-reflective conductive particle, anisotropic conductive adhesive, and light-emitting device

A light-reflective conductive particle for an anisotropic conductive adhesive used for connecting a light-emitting element to a wiring board by anisotropic conductive connection includes a core particle covered with a metal material and a light reflecting layer formed of a light-reflective inorganic particle having a refractive index of 1.52 or greater on the surface of the core particle. Examples of the light-reflective inorganic particles having a refractive index of 1.52 or greater include a titanium oxide particle, a zinc oxide particle, and an aluminum oxide particle. The coverage of the light reflecting layer on the surface of the core particle is 70% or more.

Apparatus and method for stacking semiconductor devices

A method of directly transferring a first semiconductor device die to a substrate includes loading a wafer tape into a first frame, loading a substrate into a second frame, arranging at least one of the first frame or the second frame such that a surface of the substrate is adjacent to a first side of the wafer tape, and orienting a needle to a position adjacent to a second side of the wafer tape, the needle extending in a direction toward the wafer tape. The method also includes activating a needle actuator connected to the needle to move the needle to a die transfer position at which the needle contacts the second side of the wafer tape to press the first semiconductor device die into contact with the second semiconductor device die.

Tsv substrate structure and the stacked assembly thereof

The disclosure provides a TSV substrate structure and the stacked assembly of a plurality of the substrate structures, the TSV substrate structure including: a substrate comprising a first surface, a corresponding second surface, and a TSV communicating the first surface with the second surface through the substrate; and a conductor unit completely filling the TSV, the conductor unit comprising a conductor body which has a first and a second ends corresponding to the first and second surfaces of the substrate, respectively.

METHOD OF FABRICATING A SEMICONDUCTOR STRUCTURE HAVING CONDUCTIVE BUMPS WITH A PLURALITY OF METAL LAYERS

A conductive bump structure used to be formed on a substrate having a plurality of bonding pads. The conductive bump structure includes a first metal layer formed on the bonding pads, a second metal layer formed on the first metal layer, and a third metal layer formed on the second metal layer. The second metal layer has a second melting point higher than a third melting point of the third metal layer. Therefore, a thermal compression bonding process is allowed to be performed to the third metal layer first so as to bond the substrate to another substrate, and then a reflow process can be performed to melt the second metal layer and the third metal layer into each other so as to form an alloy portion, thus avoiding cracking of the substrate. 19-. (canceled)10. A method of fabricating a semiconductor structure , comprising:providing a carrier and a substrate having a plurality of bonding pads and a plurality of conductive bumps formed respectively on the bonding pads, wherein each of the conductive bumps has a first metal layer formed on a corresponding one of the bonding pads, a second metal layer formed on the first metal layer, and a third metal layer formed on the second metal layer, and the second metal layer has a second melting point higher than a third melting point of the third metal layer;heating the substrate and the carrier to a first temperature range, so as forthe third metal layer to be melted and thereby bonded with the carrier; andheating the substrate and the carrier to a second temperature range, so as forthe second metal layer to be melted to form an alloy portion with the third metal layer, and the first metal layer and the alloy portion to form a conductor for electrically connecting the carrier and the substrate.11. The method of claim 10 , wherein the substrate is made of a low-k material.12. The method of claim 10 , wherein the second melting point of the second metal layer is between 200° C. and 250° C.13. The method of claim 10 , wherein ...

PACKAGE SUBSTRATE, SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME

A package substrate and a semiconductor package are provided. The package substrate includes an insulating layer having opposing first and second surfaces; a first wiring layer formed in the insulating layer, exposed from the first surface of the insulating layer, and having a plurality of first conductive pads; a second wiring layer formed in the insulating layer, exposed from the second surface, and having a plurality of second conductive pads; a third wiring layer formed on the first surface and electrically connected with the first wiring layer; a plurality of first metal bumps formed on the first conductive pads corresponding; and at least one conductive via vertically embedded in the insulating layer and electrically connected to the second and third wiring layers. Therefore, the surfaces of first conductive pads are reduced, and the non-wetting between the first conductive pads and the solder materials formed on conductive bumps is avoided. 1. A package substrate , comprising:an insulating layer having opposing first and second surfaces;a first wiring layer embedded in the insulating layer, exposed from the first surface, and having a plurality of first conductive pads;a second wiring layer embedded in the insulating layer, exposed from the second surface, and having a plurality of second conductive pads;a third wiring layer formed on the first surface and electrically connected with the first wiring layer;a plurality of first metal bumps formed on the first conductive pads correspondingly; andat least one conductive via embedded in the insulating layer and electrically connected with the second wiring layer and the third wiring layer.2. The package substrate of claim 1 , wherein each of the first metal bumps has an area projected onto the first surface that is less than an area of a corresponding one of the first conductive pads.3. The package substrate of claim 1 , wherein the first wiring layer has an exposed surface lower than the first surface.4. The ...

3D IC METHOD AND DEVICE

A method of three-dimensionally integrating elements such as singulated die or wafers and an integrated structure having connected elements such as singulated dies or wafers. Either or both of the die and wafer may have semiconductor devices formed therein. A first element having a first contact structure is bonded to a second element having a second contact structure. First and second contact structures can be exposed at bonding and electrically interconnected as a result of the bonding. A via may be etched and filled after bonding to expose and form an electrical interconnect to interconnected first and second contact structures and provide electrical access to this interconnect from a surface. 1. A bonded structure comprising:a first substrate having a front side and a back side opposite the front side;a first non-metallic region located on the back side of the first substrate;a first contact structure comprising a conductive material filled in a first via extending through the first substrate, the conductive material comprising a via first structure;a second substrate;a second non-metallic region located on a front side of the second substrate and directly bonded to the first non-metallic region along an interface; anda second contact structure disposed on the second substrate proximate to the second non-metallic region, the second contact structure directly bonded to the first contact structure, the interface extending substantially to the bonded first and second contact structures.2. The bonded structure of claim 1 , wherein the conductive material is approximately coplanar with the first non-metallic region at the back side of the first substrate.3. The bonded structure of claim 1 , wherein the conductive material protrudes the back side of the first substrate and the dielectric sidewall protrudes the back side of the first substrate.4. The bonded structure of claim 1 , wherein the first contact structure comprises a first portion on the back side of the ...

ANISOTROPIC CONDUCTIVE FILM AND DISPLAY DEVICE USING THE SAME

An anisotropic conductive film includes a conductive layer; a first resin insulating layer over a first surface of the conductive layer; and a second resin insulating layer over a second surface of the conductive layer, wherein the conductive layer comprises a plurality of conductive particles and a nano fiber connecting the plurality of conductive particles to each other, each of the plurality of conductive particles comprising a plurality of needle-shaped protrusions having a conical shape, and wherein the first resin insulating layer and the second resin insulating layer comprise a same material and have different thicknesses. 1. An anisotropic conductive film comprising:a conductive layer;a first resin insulating layer over a first surface of the conductive layer; anda second resin insulating layer over a second surface of the conductive layer,wherein the conductive layer comprises a plurality of conductive particles and a nano fiber connecting the plurality of conductive particles to each other, each of the plurality of conductive particles comprising a plurality of needle-shaped protrusions each having a conical shape, andwherein the first resin insulating layer and the second resin insulating layer each comprise a same material and have different thicknesses from each other.2. The anisotropic conductive film of claim 1 ,wherein each of the plurality of conductive particles comprises a core having elasticity and a base portion including a metal material and surrounding the core, andwherein the plurality of needle-shaped protrusions are arranged over the base portion.3. The anisotropic conductive film of claim 2 , wherein the base portion and the plurality of needle-shaped protrusions are integrally formed and each comprise a same material.4. The anisotropic conductive film of claim 1 , wherein the plurality of conductive particles are spaced apart from each other.5. The anisotropic conductive film of claim 1 , wherein the nano fiber comprises a non-conductive ...

Semiconductor package and method of manufacturing semiconductor package

A semiconductor package includes a wiring substrate that includes a first conductive member; a semiconductor chip that is mounted on the wiring substrate and includes a second conductive member, the first conductive member and the second conductive member being positioned to face each other; and a bonding member that bonds and electrically connects the first conductive member and the second conductive member, at least one of the first conductive member and the second conductive member being a pillar-shaped terminal, the bonding member being bonded to an end surface of the pillar-shaped terminal and a portion of a side surface of the pillar-shaped terminal, an intermetallic compound layer being formed at an interface of the bonding member and the pillar-shaped terminal.