Mehrchip-Halbleitermodul und Herstellungsverfahren dafür

Ein Mehrchip-Halbleitermodul weist auf: ein Chipmontageteil mit einem ersten und zweiten Substrat, wobei das erste Substrat hat: eine entgegengesetzte erste und zweite Oberfläche, mehrere erste leitende Kontaktlöcher, die sich durch die erste und zweite Oberfläche erstrecken, und eine erste Schaltungsanordnung, die auf der zweiten Oberfläche strukturiert und mit den ersten leitenden Kontaktlöchern elektrisch verbunden ist, wobei das zweite Substrat hat: eine entgegengesetzte erste und zweite Oberfläche, mehrere zweite leitende Kontaktlöcher, die sich durch die erste und zweite Oberfläche des zweiten Substrats erstrecken, eine zweite Schaltungsanordnung, die auf der zweiten Oberfläche des zweiten Substrats strukturiert und mit den zweiten leitenden Kontaktlöchern elektrisch verbunden ist, und eine darin ausgebildete erste Chipaufnahmeöffnung, wobei die erste Oberfläche des zweiten Substrats auf der zweiten Oberfläche des ersten Substrats verbunden ist, so daß die zweite Schaltungsanordnung ...

Carrier for multilayer semiconductor device and process for manufacturing multilayer semiconductor device

Carrier for multilayer semiconductor device and process for manufacturing multilayer semiconductor device

A carrier for a multilayer semiconductor device comprising a lower stage carrier (3) having a first containing section (12) for containing a first semiconductor device (110) to be the lower side device, and an upper stage carrier (2) having a second containing section (14) for containing a second semiconductor device (120) to be stacked on the first semiconductor device (110) and arranging the second semiconductor device (120) at a specified position on the first semiconductor device (110). By having such a structure, no dedicated stacking device is required, and thus cost can be reduced.

SEMICONDUCTOR CHIP ARRANGEMENT AND PROCEDURE FOR YOUR PRODUCTION

PRODUCTION OF AN ELECTRONIC CIRCUIT UNIT, WHICH STACKING CONTAINS IC SITUATIONS WITH BYPASS LINES

SEMICONDUCTOR CHIP ARRANGEMENTS, MANUFACTURING METHODS AND COMPONENTS FOR THE SAME

SEMICONDUCTOR CHIP ARRANGEMENT AND PROCEDURE FOR YOUR PRODUCTION

SEMICONDUCTOR CHIP ARRANGEMENT AND PROCEDURE FOR YOUR PRODUCTION

SEMICONDUCTOR CHIP ARRANGEMENT AND PROCEDURE FOR YOUR PRODUCTION

SEMICONDUCTOR CHIP ARRANGEMENT AND PROCEDURE FOR YOUR PRODUCTION

SEMICONDUCTOR CHIP ARRANGEMENT AND PROCEDURE FOR YOUR PRODUCTION

SEMICONDUCTOR CHIP ARRANGEMENT AND PROCEDURE FOR YOUR PRODUCTION

SEMICONDUCTOR CHIP ARRANGEMENT AND PROCEDURE FOR YOUR PRODUCTION

SEMICONDUCTOR CHIP ARRANGEMENT AND PROCEDURE FOR YOUR PRODUCTION

SEMICONDUCTOR CHIP ARRANGEMENT AND PROCEDURE FOR YOUR PRODUCTION

SEMICONDUCTOR CHIP ARRANGEMENT AND PROCEDURE FOR YOUR PRODUCTION

A high density hybrid integrated circuit package having a flip-con structure

STACKED CHIP ASSEMBLY AND MANUFACTURING METHOD THEREFOR

Conductive epoxy flip-chip

Semiconductor package device and method of formation and testing

RECONFIGURABLE CONNECTIONS FOR STACKED SEMICONDUCTOR DEVICES

... 부분 실시예는 스택에 배열된 반도체 다이스, 다이스 사이에 통신을 제공하도록 구성된 복수의 커넥션, 적어도 하나의 다이스를 통과하는 적어도 하나의 부분과, 커넥션의 결함을 체크하고, 커넥션의 결함을 수리하도록 구성된 모듈을 포함하는 장치, 시스템, 방법을 포함한다.

SEMICONDUCTOR DEVICE

SEMICONDUCTOR SYSTEM

SEMICONDUCTOR CHIP AND STACK PACKAGE HAVING SAME

Disclosed are a semiconductor chip and a stack package having the same. The disclosed stack package may include: a substrate where a plurality of connection pads is formed; semiconductor chips, each of which includes circuit parts including at least one first circuit part used in a package level as being stacked on the substrate and at least one second circuit part not used in the package level, bonding pads which correspond to each circuit part and are connected to the corresponding circuit parts electrically, and a blocking circuit which is connected between the second circuit part and a bonding pad corresponding thereto and separates the second circuit part from the bonding pad corresponding thereto electrically in response to a dummy pad enable signal; and a bonding wire which connects a bonding pad corresponding to the first circuit part and the connection pad of the substrate electrically. The semiconductor chip and the stack package having the same according to the present invention ...

Semiconductor stacked package

Semiconductor device, semiconductor package, and method for testing semiconductor device

A semiconductor device (11) designed to facilitate testing. Superimposed first and second semiconductor chips (13, 14) each include a plurality of internal terminals (23-25, 27-30), an external terminal (22, 27). A plurality of wires (15) connect the internal terminals, the transistors, and the external terminals of the first and second semiconductor chips in series.

Module substrate that allows replacement of faulty chips, semiconductor module having the same, and method for manufacturing the semiconductor module

SEMICONDUCTOR PACKAGE DEVICE AND METHOD OF FORMATION AND TESTING

A package device (10, 100) has one integrated circuit (22, 122) in a cavity (20, 120) in a package substrate (12. 122) and electrically coupled to one side (50, 150) of the package substrate. A second integrated circuit (32, 132) is mounted on another side of the package device and electrically coupled to that side as well. A third integrated circuit (38, 138) or more may be mounted on the second integrated circuit. Pads (16, 116, 116) useful for testing are present on both sides of the package substrate. The integrated circuits may be tested before final encapsulation to reduce the risk of providing completed packages with non-functional integrated circuits therein.

ELECTRONIC MODULE COMPRISING A STACK OF IC CHIPS

An electronic module comprising a multiplicity of pre-stacked IC chips (30), such as memory chips, and an IC chip (34), referred to as an active substrate or active backplane, to which the access plane is directly secured. A multiplicity of aligned solder bumps (44) may interconnect the stack (32) and the substrate (34), providing electrical, mechanical and thermal interconnection. The active substrate is a silicon layer containing substantial amounts of integrated circuitry, which interfaces, on one side, with the integrated circuitry in the stacked chips, and, on the other side, with the external computer bus system. Some of the high priority circuitry which may be included in the substrate is used for control, fault-tolerance, buffering, and data management.

ARRAY SUBSTRATE, DETECTING METHOD AND DETECTING APPARATUS THEREOF

The present disclosure provides an array substrate comprising a structure to be detected disposed on a base substrate. An additional layer for detecting the structure to be detected is broken is disposed below the structure to be detected. The additional layer has a color different from that of the structure to be detected and a same pattern shape as that of the structure to be detected. The present disclosure also provides a detecting method and detecting apparatus of the array substrate described above. According to the array substrate, the detecting method and the detecting apparatus of the present disclosure, an early detection of the breakage defect occurred during the fabrication process of the array substrate can be achieved so as to discover and eliminate those defects as early as possible, which improves throughput and yield.

High density memory module

A memory module is built up from a power distribution assembly in the form of plates forming a capacitor of low inductance and a flexible circuit substrate. The circuit substrate is populated with precisely positioned contact pads for the power, read, write and address lines of memory chips that contact the substrate. Memory chips are fixed to heat spreaders and loaded into a chip holder which positions the chips for contact with the contact pads on the substrate. The substrate contact pads are plated to form dendritic crystals of palladium and the memory chips are provided with solder balls on the contact pads of the memory chip. The solder balls are held in contact with the contact pads by the compressive forces of clamping a heat sink over the heat spreaders for testing, and the assembly may be readily disassembled to replace any defective memory. The compression connection of the chips to the substrate may be relied on or the solder balls may be reflowed to establish permanent solder ...

Stacked chip assembly

A semiconductor chip assembly, comprises a first semiconductor chip having a front surface, a rear surface and contacts on the front surface and a second semiconductor chip having a front surface, a rear surface and contacts on the front surface. The rear surface of the second semiconductor chip is juxtaposed with the front surface of the first semiconductor chip. The assembly includes a first backing element having electrically conductive first terminals. The first backing element is juxtaposed with the rear surface of the first semiconductor chip so that at least some of the terminals overlie the rear surface of the first semiconductor chip. At least some of the contacts on the first and the second semiconductor chips are electrically connected to at least some of the terminals. The assembly includes a substrate having contact pads thereon. The first terminals are connected to the contact pads of the substrate. The substrate is adapted to connect the assembly with other elements of a ...

Stacked semiconductor memory device and semiconductor memory module containing the same

There is a trend to increase that area of a device requiring a memory of large capacity, which is occupied by a semiconductor memory. This trend obstructs reduction of the size of the device. The present invention contemplates to provide a memory which can have a high integration, a high density and a large capacity while minimizing the mounting area. In order to achieve this memory, the TAB (Tape Automated Bonding) of the prior art is mounted on an electrically conductive connector, and a plurality of structures composed of the TAB and the connector are stacked. Moreover, the connector mounting the TAB thereon is constructed such that the independent terminals of the stacked TABs may not be shorted.

Methods for stacking wire-bonded integrated circuit dice on flip-chip bonded integrated circuit dice

An inventive electronic device, such as a multi-chip module (MCM), a Single In-line Memory Module (SIMM), or a Dual In-line Memory Module (DIMM), includes a base, such as a printed circuit board, having a surface on which flip-chip pads and wire-bondable pads are provided. The flip-chip pads define an area on the surface of the base at least partially bounded by the wire-bondable pads. A first integrated circuit (IC) die is flip-chip bonded to the flip-chip pads, and a second IC die is back-side attached to the first IC die and then wire-bonded to the wire-bondable pads. As a result, the flip-chip mounted first IC die is stacked with the second IC die in a simple, novel manner.

Semiconductor package

A semiconductor package comprises a substrate having bond fingers on an upper surface thereof and ball lands on a lower surface thereof; at least two chip modules stacked on the upper surface of the substrate, each of the at least two chip modules including a plurality of semiconductor chips having first connection members and stacked in a manner such that the first connection members of the semiconductor chips are connected to one another, the chip modules being stacked in a zigzag pattern such that connection parts of the chip modules project sideward; and second connection members electrically connecting the connection parts of the respective chip modules to the bond fingers of the substrate.

Stair-stacked dice device in a system in package, and methods of making same

A system in package includes a stair-stacked memory module that is stacked vertically with respect to a processor die. A spacer is used adjacent to the processor die to create a bridge for the stair-stacked memory module. Each memory die in the stair-stacked memory module includes a vertical bond wire that emerges from a matrix for connection. The matrix encloses the stair-stacked memory module and at least a portion of the processor die.

Circuit board having bypass pad

An electronic device having a printed circuit board is provided. In one embodiment, the printed circuit board includes a plurality of external pads to be coupled with an external device and a plurality of bypass pads for testing an electric circuit. The external pads are exposed and at least one of the plurality of bypass pads are not exposed from an outer surface of the PCB. A system using the electronic device and a method of testing an electronic device are also provided.

Microelectronic component and assembly having leads with offset portions

A microelectronic component comprising a dielectric layer having an opening and leads extending across the opening is disclosed. The leads have an offset portion. A method of making a microelectronic assembly comprises connecting each of the leads to a contact on a microelectronic element. A semiconductor chip assembly has a microelectronic component with an opening and leads extending across the opening. The leads are connected to contacts on a semiconductor chip and have at least one twisted portion.

Wafer on wafer packaging and method of fabrication for full-wafer burn-in and testing

A semiconductor device wafer-on-support wafer package comprising a plurality of segmentable chip-scale packages and method of constructing, burning-in, and testing same. The wafer-on-wafer package can be burned-in and tested at the wafer level prior to segmenting, or singulating, the wafer-on-wafer package into a plurality of individual chip-scale packages.

Known good die using existing process infrastructure

An apparatus for testing a semiconductor die and the method wherein there is provided a package having a cavity therein with a plurality of terminals in the package disposed at the periphery of the cavity. A semiconductor die to be tested and having a plurality of bond pads thereon is disposed in the cavity and an interconnecting layer having electrically conductive paths thereon is also disposed in the cavity, each of the paths having first and second spaced apart regions thereon, the first region of each path being aligned with and contacting a bond pad. An interconnection is provided between the second spaced apart region of each of the paths and one of the plurality of terminals. The second spaced apart region of each of the paths is preferably a bump aligned with and contacting one of the plurality of terminals. A compliant layer is preferably disposed over the interconnecting layer and provides a force causing engagement of at least the first spaced apart regions and the bond pads ...

SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME

The present disclosure relates to a semiconductor package and a manufacturing method thereof. The method includes stacking semiconductor chips using a thermo-compression bonding (TCB) method, where defects are minimized for increased reliability. The semiconductor package includes an interface chip including a first test pad, a bump pad provided inside the first test pad, and a first through silicon via (TSV) provided between the first test pad and the bump pad; at least one memory chip, which is stacked on the interface chip and includes a second test pad, a dummy pad provided inside the second test pad, and a second TSV provided between the second test pad and the dummy pad; and an adhesive layer provided between the interface chip and the at least one memory chip. wherein no bump is provided on the first test pad and the second test pad.

SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE INSPECTION METHOD AND SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE

Integrated circuit layers 10, 20 to be stacked on top of each other are formed with a plurality of inspection rectifier device units 15, 25, respectively. The plurality of inspection rectifier device units 15 (25) including rectifier devices 15a, 15b (25a, 25b) are connected between a plurality of connection terminals 14 (24) and a positive power supply lead 13a (23a) and a grounding lead 13b (23b) and emit light in response to a current. After electrically connecting the plurality of connection terminals 14, 24 to each other, a bias voltage is applied between the positive power supply lead 13a (or grounding lead 13b) and the grounding lead 23b (or positive power supply lead 23a), and the connection state between the connection terminals 14, 24 is inspected according to a light emission of the inspection rectifier device unit 15 or 25. This makes it possible to inspect, in a short time every time a layer is stacked, whether or not an interlayer connection failure exists in a semiconductor ...

SEMICONDUCTOR CHIP ASSEMBLIES, METHODS OF MAKING SAME AND COMPONENTS FOR SAME

Semiconductor chip assemblies incorporating flexible, sheet-like elements (42) having terminals thereon overlying the front or rear face of the chip to provide a compact unit. The terminals (48) on the sheet-like element are movable with respect to the chip, so as to compensate for thermal expansion. A resilient element such as a compliant layer (42) interposed between the chip and terminals permits independent movement of the individual terminals toward the chip driving engagement with test probe assembly so as to permit reliable engagement despite tolerances.

SEMICONDUCTOR CHIP FOR EVALUATION, EVALUATION SYSTEM, AND REPAIRING METHOD OF THE SAME

PROBLEM TO BE SOLVED: To provide a technology of evaluating a semiconductor chip solving a problem wherein it cannot be heated during an evaluation test. SOLUTION: This semiconductor chip is formed by stacking, on one surface of a silicon substrate, at least one of a metal wiring film 101 as a resistance temperature sensing element consisting of a plurality of regions and a metal wiring film 102 as a heater consisting of one or a plurality of regions, and an electrode 103 for connecting the metal wiring film 101 and metal wiring film 102 to a mounting substrate. The semiconductor chip is mounted to the mounting substrate, and the metal wiring film 101 is electrically connected to an ammeter and voltmeter and the metal wiring film 102 is electrically connected to a power supply. Thus, the evaluation system capable of evaluating the temperature sensing, heating, and the temperature profile in each region of the semiconductor chip is provided. COPYRIGHT: (C)2012,JPO&INPIT ...

SEMICONDUCTOR CHIP ARRANGEMENTS, MANUFACTURING METHODS AND COMPONENTS FOR THE SAME

SEMICONDUCTOR CHIP ARRANGEMENT AND PROCEDURE FOR YOUR PRODUCTION

SEMICONDUCTOR CHIP ARRANGEMENT AND PROCEDURE FOR YOUR PRODUCTION

SEMICONDUCTOR CHIP ARRANGEMENT AND PROCEDURE FOR YOUR PRODUCTION

SEMICONDUCTOR CHIP ARRANGEMENT AND PROCEDURE FOR YOUR PRODUCTION

SEMICONDUCTOR CHIP ARRANGEMENT AND PROCEDURE FOR YOUR PRODUCTION

SEMICONDUCTOR CHIP ARRANGEMENT AND PROCEDURE FOR YOUR PRODUCTION

SEMICONDUCTOR CHIP ARRANGEMENT AND PROCEDURE FOR YOUR PRODUCTION

SEMICONDUCTOR DEVICE HAVING A BOND PAD AND METHOD FOR ITS FABRICATION

Integrated circuit lamination process

Silicon segment programming method and apparatus

SEMICONDUCTOR CHIP ASSEMBLIES, METHODS OF MAKING SAME AND COMPONENTS FOR SAME

System and methods for producing modular stacked integrated circuits

Semiconductor device

A semiconductor device includes a package substrate having a plurality of external connection terminals disposed on a first surface thereof and a plurality of internal connection terminals disposed on a second surface thereof and electrically connected with corresponding one of the external connection terminals, a first semiconductor chip stacked over the second surface of the package substrate and having a first flag pad for providing first information and a first internal circuit for adjusting a parameter by a first correction value in response to the first information provided from the first flag pad, and a second semiconductor chip stacked over the first semiconductor chip and having a second flag pad for providing second information and a second internal circuit for adjusting the parameter by a second correction value in response to the second information provided from the second flag pad.

MANUFACTORING PROCESS Of a DEVICE STACKING OF CHIPS SEMICONDUCTRICES HAS

L'invention concerne un procédé de fabrication d'un dispositif à empilement de puces semiconductrices, comportant les étapes suivantes : a) former une première matrice de connecteurs (11) sur une face d'une première puce semiconductrice (C1) ; b) former une seconde matrice de connecteurs (12) sur une face d'une seconde puce semiconductrice (C2), la seconde matrice comprenant plus de connecteurs que la première matrice et le pas de la première matrice étant un multiple du pas de la seconde matrice ; c) appliquer la première puce contre la seconde puce ; et d) établir des signaux de test entre les première (C1) et seconde (C2) puces pour déterminer l appariement entre les connecteurs (11) de la première matrice et les connecteurs (12) de la seconde matrice.

Method and device for three-dimensional encapsulation of semiconductor chips

L'invention a pour objet une encapsulation en trois dimensions de pastilles semi-conductrices, chacune contenant par exemple un circuit intégré, cette encapsulation visant à optimiser l'évacuation thermique par conduction. Selon l'invention, à chaque pastille (1) sont associés des moyens de connexion, permettant de prolonger les plots de pastilles vers trois côtés de la pastille et dégageant ainsi le quatrième côté. Les pastilles sont empilées les unes sur les autres puis reliées à des moyens d'évacuation thermique (9) par leur quatrième côté.

Multi chip package having increased reliability

SEMICONDUCTOR DEVICE, SEMICONDUCTOR PACKAGE, AND METHOD FOR TESTING SEMICONDUCTOR DEVICE

SEMICONDUCTOR DEVICE

A MULTI CHIP MODULE

PACKAGED SEMICONDUCTOR DIE USING PREDETERMINED TESTS FOR IMPROVING CORRESPONDING CAPABILITY TO MULTI-CHIP PACKAGE AND ENHANCING DESIGN FLEXIBILITY AND MANUFACTURING METHOD THEREOF

PURPOSE: A packaged semiconductor die and its manufacturing method are provided to enhance a corresponding capability to a multi-chip package and to improve design flexibility by using a known good package performed with predetermined tests. CONSTITUTION: A die substrate(220) with an insulating base member(221) and metal line patterns(223,224) on the insulating base member is provided. A known good package that undergoes predetermined tests is mounted on the die substrate. At this time, the known good package is electrically connected with the metal line patterns of the die substrate. The resultant structure is selectively encapsulated by using a molding member(240). © KIPO 2006 ...

MULTI-CHIP PACKAGE CAPABLE OF PREVENTING A STRAIN PHENOMENON OF A CONDUCTIVE WIRE, AND A MANUFACTURING METHOD THEREOF

PURPOSE: A multi-chip package and a manufacturing method thereof are provided to prevent the size increasing of a semiconductor chip and the multi-chip package without securing a separate dummy pad formation space in the semiconductor chip. CONSTITUTION: A package substrate(110) comprises an insulating substrate, a circuit pattern, and a pad(112). First to fourth semiconductor chips(120-150) are laminated on the upper side of the package substrate. A conductive connecting member(160) electrically connects first to fourth signal pads to the pad of the package substrate. A molding member(170) is formed on the upper side of the package substrate. An external connector(180) is mounted in the pad which is arranged on the lower side of the package substrate. COPYRIGHT KIPO 2012 ...

3di solder cup

A substrate or semiconductor device, semiconductor device assembly, and method of forming a semiconductor device assembly that includes a barrier on a solder cup. The semiconductor device assembly includes a substrate disposed over another substrate. At least one solder cup extends from one substrate towards an under bump metal (UBM) on the other substrate. The barrier on the exterior of the solder cup may be a standoff to control a bond line between the substrates. The barrier may reduce solder bridging during the formation of a semiconductor device assembly. The barrier may help to align the solder cup with a UBM when forming a semiconductor device assembly and may reduce misalignment due to lateral movement of substrates and/or semiconductor devices.

Semiconductor assemblies, stacked semiconductor devices, and methods of manufacturing semiconductor assemblies and stacked semiconductor devices

METHOD AND APPARATUS FOR PROVIDING THROUGH SILICON VIA (TSV) REDUNDANCY

An apparatus includes a first die having a first bus, a second die having a second bus stacked on the first die, a plurality of through silicon vias connecting the first bus to the second bus, and first control logic for sending data to indentified ones of the plurality of through silicon vias. Also, optionally, second control logic for determining a first set of the plurality of through silicon vias that are nonfunctional, wherein the second control logic is configured to send information to the first control logic identifying the first set of the plurality of through silicon vias or identifying a second set of through silicon vias that are functional. Also a method of sending signals through a plurality of through silicon vias.

Known good die using existing process infrastructure

An apparatus for testing a semiconductor die and the method wherein there is provided a package having a cavity therein with a plurality of terminals in the package disposed at the periphery of the cavity. A semiconductor die to be tested and having a plurality of bond pads thereon is disposed in the cavity and an interconnecting layer having electrically conductive paths thereon is also disposed in the cavity, each of the paths having first and second spaced apart regions thereon, the first region of each path being aligned with and contacting a bond pad. An interconnection is provided between the second spaced apart region of each of the paths and one of the plurality of terminals. The second spaced apart region of each of the paths is preferably a bump aligned with and contacting one of the plurality of terminals. A compliant layer is preferably disposed over the interconnecting layer and provides a force causing engagement of at least the first spaced apart regions and the bond pads ...

Semiconductor device and method of manufacturing the same

A semiconductor device comprises a square-shaped first semiconductor chip having a first LSI, a square-shaped second semiconductor chip having a second LSI, which is smaller in size than the first semiconductor chip and connected to the first semiconductor chip by face down bonding, and a square-shaped package made of a molding resin for packaging the first and second semiconductor chips. The respective centers of the first and second semiconductor chips are offset from each other, while the center of the second semiconductor chip is substantially coincident with the center of the molding resin.

Multi-layer integrated circuits having isolation cells for layer testing and related methods

Multi-layer integrated circuits having isolation cells for layer testing and related methods are disclosed. According to an aspect, an integrated circuit includes first and second layers that each have one or more electronic components. One or more electronic components of each layer can be electrically connected by a first via and a second via. The integrated circuit also includes an isolation cell operatively connected between the first via and the second via. The isolation cell is configured to controllably break electrical connection between the first via and the second via subsequent to testing of the at least one electronic component of the second layer. Example isolation cells include, but are not limited to, electronic fuses and tri-state flip-flops.

Semiconductor device including electronic component coupled to a backside of a chip

A semiconductor package includes a substrate, at least one chip including a first side and a backside opposite of the first side, the first side electrically coupled to the substrate, a conductive layer coupled to the backside of the at least one chip, and at least one electronic component coupled to the conductive layer and in electrical communication with the substrate.

Stacked Semiconductor Component Having Through Wire Interconnect And Method Of Fabrication

A stacked semiconductor component includes a plurality of semiconductor substrates in a stacked array and a continuous wire extending through aligned vias on the semiconductor substrates of the stacked array in electrical contact with contacts on the semiconductor substrates. A method for fabricating the semiconductor component includes the steps of stacking the semiconductor substrates in a stacked array with aligned vias; threading a wire through the aligned vias; and forming a plurality of electrical connections between the wire and the contacts on the semiconductor substrates.

Stacked integrated circuit and package system

A stacked integrated circuit and package system including attaching a first top integrated circuit over an upper surface of a top substrate, attaching a second top integrated circuit over a lower surface of the top substrate, forming top electrical connectors on the lower surface of the top substrate, and connecting a bottom package to the top electrical connectors.

Three-dimensional stack manufacture for integrated circuit devices and method of manufacture

An integrated circuit package assembly formed by stacking flip-chip mounted substrates interleaved with precisely dimensioned spacers and then bonded by injection molding the stack. The sides of the stack are sawed off to expose vias in the substrates, and multilevel-interconnect substrates are precisely aligned on the sides of the stack. Solder pads on the interconnect substrates are reflowed to form a solder connection to the exposed vias, allowing complex interconnection between diverse points along the edge connectors of each substrate. In one embodiment, solder balls are reflowed on ball-grid-array pads at the top of the stack to provide external electrical connections.

Packages for stacked integrated circuit chip cubes

This invention relates to three dimensional packaging of integrated circuit chips into stacks to form cuboid structures. Between adjacent chips in the stack, there is disposed an electrical interconnection means which is a first substrate having a plurality of conductors one end of which is electrically connected to chip contact locations and the other end of which extends to one side of the chip stack to form a plurality of pin-like electrical interconnection assemblies. The pin-like structures can be formed from projections of the first substrate having an electrical conductor on at least one side thereof extending from this side. Alternatively, the pin-like structures can be formed from conductors which cantilever from both sides of an edge of the first substrate and within which corresponding conductors from both sides are aligned and spaced apart by the first substrate thickness. The spaces contain solder and form solder loaded pin-like structures. The pin-like structures can be directly ...

Method and apparatus for directing the input/output connection of integrated circuit chip cube configurations

A technique is disclosed for forming a chip cube from a plurality of chips laminated together in front-to-back relationship, the edges of the chip forming a cube face having a set of connectors for each chip thereon. A number "X" of functional chips is required for the operation, and "X+Y" is the number of chips provided in the stack such that there is Y number of chips greater than the number of functional chips required. If any number of chips equal to Y or less are found to be defective, there are enough chips remaining to perform the required function. Thereafter X number of good chips are connected to output circuitry through an interposer. Electrical connectors are provided on all of the IC chips. Contact pads for all of the connectors are provided on one face, and outlet pads are provided on the opposite face of the interposer for at least Y number of outlets. The interposer has vias at least equal to the number of outlet pads. After assembly, the chips are burnt-in, and if there ...

SEMICONDUCTOR DEVICE

A semiconductor device includes a wiring board having: plural stacked insulating layers; test pads and external connection pads which are disposed on a face of the plural stacked insulating layers located on the side opposite to that where another wiring board is connected; first wiring patterns which electrically connect internal connection pads with the test pads; and second wiring patterns which electrically connect semiconductor element mounting pads with the external connection pads. The external connection pads are placed on the inner side of the test pads.

Vertical System Integration

The Vertical System Integration (VSI) invention herein is a method for integration of disparate electronic, optical and MEMS technologies into a single integrated circuit die or component and wherein the individual device layers used in the VSI fabrication processes are preferably previously fabricated components intended for generic multiple application use and not necessarily limited in its use to a specific application. The VSI method of integration lowers the cost difference between lower volume custom electronic products and high volume generic use electronic products by eliminating or reducing circuit design, layout, tooling and fabrication costs.

Data storage device having multi-stack chip package and operating method thereof

Disclosed is a data storage device including a controller and a multi-stack chip package, and a method of operating a data storage device. The multi-stack chip package includes a first semiconductor chip arranged on a package substrate, a second semiconductor chip arranged on the first semiconductor chip, and a third semiconductor chip is arranged between the first and second semiconductor chips. The controller can control the first to third semiconductor chips by using a feature parameter measured from each semiconductor chip and a target value that may be originally designed by a memory vendor.

Semiconductor components with through wire interconnects

A method for fabricating a semiconductor component with a through wire interconnect includes the step of providing a substrate having a circuit side, a back side, and a through via. The method also includes the steps of: threading a wire through the via, forming a contact on the wire on the back side, forming a bonded contact on the wire on the circuit side, and then severing the wire from the bonded contact. The through wire interconnect includes the wire in the via, the contact on the back side and the bonded contact on the circuit side. The contact on the back side, and the bonded contact on the circuit side, permit multiple components to be stacked with electrical connections between adjacent components. A system for performing the method includes the substrate with the via, and a wire bonder having a bonding capillary configured to thread the wire through the via, and form the contact and the bonded contact. The semiconductor component can be used to form chip scale components, wafer ...

Multi-chip package capable of testing internal signal lines

A multi-chip package capable of testing internal signal lines including a printed circuit board, a first semiconductor chip mounted on the printed circuit board and including a test circuit, and second semiconductor chips mounted on the printed circuit board and electrically connected to the first semiconductor chip via a plurality of internal signal lines may be provided. The test circuit may be configured to enable circuits of the first semiconductor chip connected to pads contacting the plurality of internal signal lines, transmit complementary data to at least two pads from among the pads, and form a current path in the circuits connected to the at least two pads, thereby detecting a short-circuit between the internal bonding wires.

Interwafer connection structure for coupling wafers in a wafer stack

An integrated circuit (IC) device is disclosed which includes at least a first hybrid bond interface layer disposed between adjacent wafers of a wafer stack. Routing within the hybrid bond interface layer allows test pads exposed on a top wafer of the wafer stack to electrically couple test keys within the wafer stack. By utilizing the routing within the hybrid bond interface layer to index electrical connections between adjacent wafers, IC dies stacked on the wafers may be fabricated with less mask sets as compared to conventional designs.

ELEKTRONISCHES MODUL MIT EINEM STAPEL VON IC-CHIPS

CHIP, CHIPBAUGRUPPE UND DIE

In verschiedenen Ausführungsformen ist ein Chip (12) für eine Chipbaugruppe (10) geschaffen. Der Chip (12) kann ein Substrat (14) und eine integrierte Schaltung über dem Substrat (14) enthalten. Die integrierte Schaltung kann eine Testschaltung, beispielsweise eine eingebaute Selbsttestschaltung, und eine Arbeitsschaltung, wobei die Testschaltung eine oder mehrere erste Treiberstufen enthält, von denen jede eine erste Treiberleistung aufweist, und die Arbeitsschaltung eine oder mehrere zweite Treiberstufen enthält, von denen jede eine zweite Treiberleistung, die sich von der ersten Treiberleistung unterscheidet, aufweist, erste elektrische Kontakte (40), die mit den ersten Treiberstufen elektrisch gekoppelt sind, und zweite elektrische Kontakte (42), die mit den zweiten Treiberstufen elektrisch gekoppelt sind, enthalten, wobei die Testschaltung und die ersten Kontakte (40) konfiguriert sind, eine Testbetriebsart zum Testen der integrierten Schaltung bereitzustellen, und wobei die Arbeitsschaltung ...

Integriertes DRAM mit niedrigem I/O-Spannungshub

System-in-Package, umfassend:einen Die-Träger, hergestellt aus Silikon, mit einer oder mehreren Redistributionsschichten (RDLs) aus entsprechenden Leiterbahnen, wobei die RDLs konfiguriert sind, um mindestens zwei integrierte Schaltkreis-Dies zu verbinden;einen Anwendungsprozessor (AP)-Die mit niedrigem Eingangs/Ausgangs-Spannungshub (LVSIO)-Schaltkreis, wobei der AP-Die, über Microbumps, an Pads der einen oder mehreren RDLs des Die-Trägers befestigt ist; undein dynamischer Direktzugriffsspeicher (DRAM)-Die mit einem anderen LVSIO-Schaltkreis, wobei der DRAM-Die über andere Microbumps an anderen Pads der einen oder der mehreren RDLs des Die-Trägers montiert ist und die entsprechenden Leiterbahnen der einen oder der mehreren RDLs einen Datenbus zwischen dem DRAM-Die und dem AP-Die bereitstellen.

PRÜFUNG UND INITIALISIERUNG VON KLEIN-CHIPS AUF WAFER-NIVEAU

Chip-Zwischenkörper (10), der aufweist:einen Halbleiterbereich (102), der eine Mehrzahl von Chip-Bereichen (101) aufweist, wobei die Chip-Bereiche jeweils als Halbleiterchips (9) heraus zu schneiden sind;einen Schneidebereich (121), der entlang von Rändern der Chip-Bereiche bereitgestellt ist, wobei der Schneidebereich zu schneiden ist, um die Halbleiterchips herauszuschneiden;einen Kontaktbereich (104), der über den Schneidebereich hinweg den Chip-Bereichen gegenüberliegend bereitgestellt ist, wobei der Kontaktbereich konfiguriert ist, durch eine Prüfspitze einer Prüfeinheit kontaktiert zu werden, um die Chip-Bereiche zu prüfen; undeine elektrische Verdrahtung (115) aus einer letzten LB-Metallschicht des Halbleiterbereichs, wobei die Verdrahtung durchgehend mit dem Schneidebereich bereitgestellt ist, um die Chip-Bereiche und den Kontaktbereich zu verbinden,wobei der Schneidebereich eine weitere elektrische Verdrahtung (131) aufweist, die zumindest die Chip-Bereiche miteinander verbindet ...

Semiconductor device and method of manufacturing the same

According to one embodiment, a semiconductor device includes a stacked chip includes semiconductor chips which are stacked, the semiconductor chips comprises semiconductor substrates and through electrodes formed in the semiconductor substrates, respectively, the through electrodes being electrically connected, and deactivating circuits provided in the semiconductor chips, respectively, and configured to deactivate a failed semiconductor chip.

Three-dimensional stacked semiconductor integrated circuit and tsv repair method thereof

Provided is a 3 D stacked semiconductor integrated circuit including a plurality of chips coupled through a plurality of TSVs. A first chip among the plurality of chips is configured to detect and repair a defective TSV among the plurality of TSVs, and transmit repair information to remaining chips other than the first chip, and the remaining chips other than the first chip are configured to repair the defective TSV in response to the repair information.

Stackable semiconductor chip with edge features and methods of fabricating and processing same

A method of performing a function on a three-dimensional semiconductor chip package as well as on individual chips in the package is disclosed. That method involves the creation of an operative relationship between a function performer and an edge feature on the chip or chips wherein the edge feature consists of one or more of an electrically conductive pad, thermally conductive pad, a probe pad, a fuse, a resistor, a capacitor, an inductor, an optical emitter, an optical receiver, a test pad, a bond pad, a contact pin, a heat dissipator, an alignment marker, a metrology feature and a function performer may be any one or more of a test probe, the laser, a programming device, an interrogation device, a loading device or a tuning device. In addition, a chip per se with edge features is disclosed along with a three-dimensional stack of such chips in either of several different configurations. The disclosure provides information regarding the formation of edge feature, the singulation of dice having incipient edge features, the stacking of dice and the handling or dice with edge features.

Through silicon via repair

Methods and systems for altering the electrical resistance of a wiring path. The electrical resistance of the wiring path is compared with a target electrical resistance value. If the electrical resistance of the wiring path exceeds the target electrical resistance value, an electrical current is selectively applied to the wiring path to physically alter a portion of the wiring path. The current may be selected to alter the wiring path such that the electrical resistance drops to a value less than or equal to the target electrical resistance value.

Test structure and methodology for three-dimensional semiconductor structures

A plurality of peripheral test structure substrate (PTSS) through vias is formed within a peripheral test structure substrate. A peripheral test structure layer and at least one functional layer are formed on one side of the plurality of the PTSS through vias. The other side of the plurality of the PTSS through vias is exposed throughout fabrication of the peripheral test structure layer and the at least one functional layer to provide access points for testing functionality of the various layers throughout the manufacturing sequence. C4 bonding may be performed after manufacture of all of the at least one functional layer is completed. A 3D assembly carrier or a C4 carrier substrate is not required since the peripheral test structure substrate has sufficient mechanical strength to support the peripheral test structure layer and the at least one functional layer.

Method for producing reconstituted wafers and method for producing semiconductor devices

In order to provide a method for producing semiconductor devices that can use the highly productive W to W method, and achieve a high yield, a method for producing semiconductor devices comprises a step (S 401 ) in which a reconstituted wafer is prepared by replacing defective chips with non-defective chips, a step (S 403 ) in which the reconstituted wafer and the base wafer are connected to one another by laminating, a step (S 406 ) in which through-electrodes are formed in the reconstituted wafer, and a step (S 409 ) in which a separate reconstituted wafer is laminated onto and connected to the reconstituted wafer having through-electrodes.

Semiconductor apparatus and stacked semiconductor apparatus

A semiconductor apparatus includes a TSV formed to be electrically connected with another chip and a TSV test unit configured to check a capacitance component of the TSV to generate a TSV abnormality signal.

Semiconductor die assemblies, semiconductor devices including same, and methods of fabrication

Methods of fabricating multi-die assemblies including a base semiconductor die bearing a peripherally encapsulated stack of semiconductor dice of lesser lateral dimensions, the dice vertically connected by conductive elements between the dice, resulting assemblies, and semiconductor devices comprising such assemblies.

Semiconductor integrated circuit device inspection method and semiconductor integrated circuit device

Integrated circuit layers to be stacked on top of each other are formed with a plurality of inspection rectifier device units, respectively. The plurality of inspection rectifier device units including rectifier devices are connected between a plurality of connection terminals and a positive power supply lead and a grounding lead and emit light in response to a current. After electrically connecting the plurality of connection terminals to each other, a bias voltage is applied between the positive power supply lead and the grounding lead, and the connection state between the connection terminals is inspected according to a light emission of the inspection rectifier device unit. This makes it possible to inspect, in a short time every time a layer is stacked, whether or not an interlayer connection failure exists in a semiconductor integrated circuit device constructed by stacking a plurality of integrated circuit layers in their thickness direction.

Stacked semiconductor devices

A stacked semiconductor device includes a first and a second semiconductor device. A first major surface of each of the first and second devices which includes the active circuitry directly face each other. The first major surface of each of the devices includes a beveled edge on at least one edge, and a probe pad which extends onto the beveled edge. A first opening is located between the beveled edges of the first and second devices on a vertical side of the stacked semiconductor device.

Integrated circuit packaging system with conductive pillars and method of manufacture thereof

A method of manufacture of an integrated circuit packaging system including: providing a package carrier; mounting an integrated circuit to the package carrier; mounting a circuit interposer above the integrated circuit; mounting a mounting integrated circuit above the circuit interposer; forming a conductive pillar to the circuit interposer adjacent to the mounting integrated circuit; connecting the circuit interposer to the package carrier; and forming an encapsulation on the package carrier.

Probing Chips during Package Formation

A method includes bonding a first package component on a first surface of a second package component, and probing the first package component and the second package component from a second surface of the second package component. The step of probing is performed by probing through connectors on the second surface of the second package component. The connectors are coupled to the first package component. After the step of probing, a third package component is bonded on the first surface of the second package component.

Edge connect wafer level stacking

A method of making a stacked microelectronic package by forming a microelectronic assembly by stacking a first subassembly including a plurality of microelectronic elements onto a second subassembly including a plurality of microelectronic elements, at least some of the plurality of microelectronic elements of said first subassembly and said second subassembly having traces that extend to respective edges of the microelectronic elements, then forming notches in the microelectronic assembly so as to expose the traces of at least some of the plurality of microelectronic elements, then forming leads at the side walls of the notches, the leads being in electrical communication with at least some of the traces and dicing the assembly into packages. Additional embodiments include methods for creating stacked packages using substrates and having additional traces that extend to both the top and bottom of the package.

System and method for electronic testing of partially processed devices

Systems and methods are provided for testing partially completed three-dimensional ICs. Example methods may incorporate one or more of the following features: design for testing (DFT); design for partial wafer test; design for partial probing; partial IC probecards; partial IC test equipment; partial IC quality determinations; partial IC test optimization; and partial test optimization. Other aspects may also be included. Systems and methods incorporating these features to test partially completed three-dimensional ICs may result in saved time and effort, and less scraped material, as the partial device is not built any further when a bad partial device is detected. This results in lower costs and higher yield.

SELF-REPAIR LOGIC FOR STACKED MEMORY ARCHITECTURE

Self-repair logic for stacked memory architecture. An embodiment of a memory device includes a memory stack having one or more memory die elements, including a first memory die element, and a system element coupled with the memory stack. The first memory die element includes multiple through silicon vias (TSVs), the TSVs including data TSVs and one or more spare TSVs, and self-repair logic to repair operation of a defective TSV of the plurality of data TSVs, the repair of operation of the defective TSV including utilization of the one or more spare TSVs. 1. A memory device comprising:a memory stack having one or more memory die elements, including a first memory die element; anda system element coupled with the memory stack; a plurality of through silicon vias (TSVs), the plurality of TSVs including a plurality of data TSVs and one or more spare TSVs, and', 'self-repair logic to repair operation of a defective TSV of the plurality of data TSVs, the repair of operation of the defective TSV including utilization of the one or more spare TSVs., 'wherein the first memory die element includes2. The memory device of claim 1 , wherein the self-repair logic includes an error correction code generator to generate an error correction code based on data for the data TSVs claim 1 , the error correction code to be transferred via the one or more spare TSVs.3. The memory device of claim 2 , wherein the self-repair logic further includes error correction logic to generate corrected data for the defective TSV.4. The memory device of claim 1 , wherein the self-repair logic includes a detection element to detect the defective TSV.5. The memory device of claim 4 , wherein the self-repair logic includes a multiplexer element to direct data intended for the defective TSV to a first spare TSV.6. The memory device of claim 5 , wherein the self-repair logic further includes a demultiplexer element to direct data received on the first spare TSV to a connection for the defective TSV.7. The ...

SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME

A method of manufacturing a semiconductor package includes forming at least two partial package chip stacks, each partial package chip stack including at least two semiconductor chips each including a plurality of through substrate vias (TSVs), and including a first mold layer surrounding side surfaces of the at least two semiconductor chips, and sequentially mounting the at least two partial package chip stacks on a package substrate in a direction vertical to a top surface of the package substrate, such that the at least two partial package chip stacks include a first partial package chip stack and a second partial package chip stack directly connected to the first partial package chip stack. 1. A method comprising:providing a first sub-package unit including at least two first semiconductor chips, which are vertically stacked, and a first mold layer surrounding side surfaces of the at least two first semiconductor chips; andproviding a second sub-package unit including at least two second semiconductor chips, which are vertically stacked, and a second mold layer that surrounds side surfaces of the at least two second semiconductor chips and is vertically spaced apart from the first mold layer, the second sub-package unit being disposed on the first sub-package unit,wherein the at least two first semiconductor chips and the at least two second semiconductor chips each include a through substrate via (TSV), andwherein a top-most semiconductor chip of the at least two first semiconductor chips is electrically connected to the bottom-most semiconductor chip of the at least two second semiconductor chips, without a package substrate therebetween; andproviding a package substrate on which the at least two first semiconductor chips and the at least two second semiconductor chips are vertically stacked to form a semiconductor package.2. The method claim 1 , further comprising:providing an upper connection pad on a top surface of a second semiconductor chip disposed in an ...

Semiconductor Device Package and Method

In an embodiment, a method includes: stacking a plurality of first dies to form a device stack; revealing testing pads of a topmost die of the device stack; testing the device stack using the testing pads of the topmost die; and after testing the device stack, forming bonding pads in the topmost die, the bonding pads being different from the testing pads.

METHOD AND DEVICE FOR CONTROLLING OPERATION USING TEMPERATURE DEVIATION IN MULTI-CHIP PACKAGE

A multi-chip package includes a first die having temperature sensors and a second die. The first die generates temperature deviation information of m (m Подробнее

SEMICONDUCTOR DEVICES INCLUDING THROUGH ELECTRODES

A semiconductor device includes a first semiconductor chip and a second semiconductor chip stacked on the first semiconductor chip and electrically connected to the first semiconductor chip by a first through electrode and a second through electrode. The first semiconductor chip may electrically connect the first through electrode to a third test resistor during a second test operation. The first semiconductor chip may detect a voltage level of the first internal node, which is determined by resistance values of the third test resistor and the first and second through electrodes, to test a short failure between the first and second through electrodes during the second test operation. 1. A semiconductor device comprising:a first semiconductor chip; anda second semiconductor chip stacked on the first semiconductor chip and electrically connected to the first semiconductor chip by a first through electrode and a second through electrode,wherein the first semiconductor chip electrically connects the first and second through electrodes to first and second test resistors during a first test operation, andwherein the first semiconductor chip detects voltage levels of first and second internal nodes coupled to the first and second through electrodes, respectively, the voltage levels of the first and second internal nodes are determined by resistance values of the first and second test resistors and the first and second through electrodes, to test open failures of the first and second through electrodes during the first test operation.2. The semiconductor device of claim 1 ,wherein the resistance value of the first test resistor is set to correspond to a resistance value of the first through electrode which is regarded as a normal through electrode without the open failure; andwherein the resistance value of the second test resistor is set to correspond to a resistance value of the second through electrode which is regarded as a normal through electrode without the open ...

SEMICONDUCTOR PACKAGES AND METHODS OF MANUFACTURING SEMICONDUCTOR PACKAGES

A semiconductor package including a mounting substrate, a first semiconductor chip mounted on an upper surface of the mounting substrate, a unit package stacked on the first semiconductor chip may be provided. The unit package includes a package substrate and a second semiconductor chip mounted on the package substrate. A plurality of bonding wires connects bonding pads of the mounting substrate and connection pads of the unit package, thereby electrically connecting the first and second semiconductor chips to each other. A molding member is provided on the mounting substrate to cover the first semiconductor chip and the unit package. 1. A method of manufacturing a semiconductor package , comprising:mounting a first semiconductor chip on an upper surface of a mounting substrate to form a preliminary package;testing the preliminary package;stacking a unit package on the first semiconductor chip, the unit package including a package substrate and a second semiconductor chip mounted thereon;connecting bonding pads of the mounting substrate and connection pads of the unit package using a plurality of bonding wires to electrically connect the first and second semiconductor chips to each other; andforming a molding member on the mounting substrate to cover the first semiconductor chip and the unit package.2. The method of claim 1 , wherein if the preliminary package passes the testing claim 1 , the stacking a unit package on the first semiconductor chip is performed.3. The method of claim 1 , wherein the stacking a unit package on the first semiconductor chip comprises:adhering a plurality of the preliminary packages on a carrier frame; andstacking a plurality of the unit packages on the preliminary packages, respectively.4. The method of claim 3 , wherein the molding member covers at least a side portion of the mounting substrate.5. The method of claim 1 , wherein the bonding pads of the mounting substrate comprises data signal_bonding pads and control signal_bonding ...

Test circuit and semiconductor apparatus including the same

A test circuit includes a through via test unit configured to be set to a first resistance value in response to a first test control signal and to a second resistance value in response to the first test control signal and a second test control signal, and form a current path including a through via that electrically connects a first chip and a second chip; and a test measurement unit configured to supply a test voltage to the through via and measure a current flowing through the through via.

FLIPPED DIE STACK

A microelectronic assembly includes a stack of semiconductor chips each having a front surface defining a respective plane of a plurality of planes. A chip terminal may extend from a contact at a front surface of each chip in a direction towards the edge surface of the respective chip. The chip stack is mounted to substrate at an angle such that edge surfaces of the chips face a major surface of the substrate that defines a second plane that is transverse to, i.e., not parallel to the plurality of parallel planes. An electrically conductive material electrically connects the chip terminals with corresponding substrate contacts. 1. A microelectronic assembly , comprising:a chip stack comprising a plurality of semiconductor chips having front surfaces, each front surface defining a respective plane of a plurality of planes, each chip having a plurality of contacts at the front surface, and an edge surface extending away from its front surface;a plurality of chip terminals each electrically coupled with a contact of a chip of the plurality of chips and extending in a direction towards the edge surface of the respective chip;a substrate having a plurality of substrate contacts at a major surface thereof, the major surface defining a second plane non-parallel to the plurality of parallel planes, wherein the chip stack is mounted to the substrate with the edge surfaces of the chips towards the major surface; andan electrically conductive material electrically connecting the chip terminals with corresponding substrate contacts.2. The microelectronic assembly as claimed in claim 1 , wherein one or more of the chips in the chip stack has an encapsulant region extending in a lateral direction beyond the edge surface of such chip.3. The microelectronic assembly as claimed in claim 1 , wherein the chip terminals are wire bonds.4. The microelectronic assembly as claimed in claim 1 , wherein the parallel planes are oriented in a direction orthogonal to the second plane.5. The ...

Semiconductor Device and Method of Manufacture

A semiconductor device and method that utilize a surface device are provided. In an embodiment a fuse line comprises an underbump metallization which has two separate, electrically isolated parts. The two parts are bridged by an external connector, such as a solder ball in order to electrically connect the surface device. When, after testing, the surface device is determined to be defective, the fuse line may be disconnected by removing the external connector from the two separate parts, electrically isolating the surface device. In another embodiment the surface is located beneath a package within an integrated fan out package or is part of a multi-fan out package. 1. A semiconductor device , comprising:a first redistribution layer (RDL) having a first portion and a second portion electrically isolated from the first portion of the first RDL;a first device coupled to a first side of the first RDL;a passivation layer disposed between the device and the first side of the first RDL;a second device coupled to a second side of the first RDL opposite the first side of the first RDL, the second device having first terminals bonded to the first portion of the first RDL, the second device having second terminals bonded to the second portion of the first RDL; anda semiconductor package disposed over the second device such that the second device is disposed between the passivation layer and the semiconductor package even when the second device has failed a device test.2. The semiconductor device of claim 1 , further comprising:vias that extend through an encapsulant and are laterally separated from the device by the encapsulant, the vias electrically coupling the first RDL to a second RDL.3. The semiconductor device of claim 2 , wherein the first device is disposed between the first RDL and the second RDL.4. The semiconductor device of claim 3 , further comprising a ball grid array located on a side of the second RDL directed away from the first device.5. The semiconductor ...

TOOLING FOR COUPLING MULTIPLE ELECTRONIC CHIPS

A method for use with multiple chips, each respectively having a bonding surface including electrical contacts and a surface on a side opposite the bonding surface involves bringing a hardenable material located on a body into contact with the multiple chips, hardening the hardenable material so as to constrain at least a portion of each of the multiple chips, moving the multiple chips from a first location to a second location, applying a force to the body such that the hardened, hardenable material will uniformly transfer a vertical force, applied to the body, to the chips so as to bring, under pressure, a bonding surface of each individual chip into contact with a bonding surface of an element to which the individual chips will be bonded, at the second location, without causing damage to the individual chips, element, or bonding surface. 1. A method comprising:constraining a portion of multiple chips adjacent a hardened material such that the hardened material and the multiple chips behave as a rigid body;transferring a force from the hardened material on the rigid body to the multiple chips to bring, under pressure, a bonding surface of each individual chip into contact with a bonding surface of an element, without causing damage to the multiple chips or the bonding surface of the element; andremoving the hardened material from contact with the multiple chips.2. The method of claim 1 , further comprising moving the multiple chips constrained by the hardened material from a first location to a second location.3. The method of claim 1 , further comprising bonding each of the multiple chips to the element.4. The method of claim 1 , further comprising removing the rigid body using at least one of a chemical process claim 1 , a mechanical process claim 1 , or a chemical-mechanical process.5. The method of claim 1 , further comprising removing at least a portion of the hardened material through at least one of a chemical process claim 1 , a mechanical process claim 1 ...

Semiconductor device and method of forming a curved image sensor

A semiconductor device has a semiconductor die containing a base material having a first surface and a second surface with an image sensor area. A masking layer with varying width openings is disposed over the first surface of the base material. The openings in the masking layer are larger in a center region of the semiconductor die and smaller toward edges of the semiconductor die. A portion of the first surface of the base material is removed by plasma etching to form a first curved surface. A metal layer is formed over the first curved surface of the base material. The semiconductor die is positioned over a substrate with the first curved surface oriented toward the substrate. Pressure and temperature is applied to assert movement of the base material to change orientation of the second surface with the image sensor area into a second curved surface.

TEST CIRCUIT FOR DETECTING PARASITIC CAPACITANCE OF TSV

Disclosed herein is an apparatus that includes a first semiconductor chip, and a first TSV penetrating the first semiconductor chip. The first semiconductor chip includes a first resistor coupled between a first power supply and a first node, a switch circuit coupled between the first node and the first TSV, a pad electrode operatively coupled to the first node, and a constant current source operatively coupled to either one of the first node and the pad electrode. 1. An apparatus comprising:a first semiconductor chip; anda first TSV penetrating the first semiconductor chip, a first resistor coupled between a first power supply and a first node;', 'a switch circuit coupled between the first node and the first TSV;', 'a pad electrode operatively coupled to the first node; and', 'a constant current source operatively coupled to either one of the first node and the pad electrode., 'wherein the first semiconductor chip includes2. The apparatus of claim 1 , wherein the first semiconductor chip further includes a first transistor coupled between the first node and the constant current source.3. The apparatus of claim 2 ,wherein the first transistor is configured to be brought into an ON state and the switch circuit is configured to be brought into an OFF state during a first operation so that a calibration voltage appears at the pad electrode, andwherein the first transistor is configured to be brought into an OFF state and the switch circuit is configured to be brought into an ON state and OFF state at a frequency during a second operation so that a measurement voltage appears at the pad electrode.4. The apparatus of claim 3 , wherein the first semiconductor chip further includes:a second transistor coupled between the first node and the pad electrode; anda third transistor coupled between a second node and the pad electrode, wherein the second node is between the first transistor and the constant current source.5. The apparatus of claim 4 , wherein the second and third ...

METHOD OF MANUFACTURING A SEMICONDUCTOR PACKAGE AND WIRE BONDING APPARATUS FOR PERFORMING THE SAME

In a method of manufacturing a semiconductor package, a first semiconductor chip is adhered to a package substrate. An end portion of a wire is bonded to a first bonding pad of the first semiconductor chip by using a capillary. An operating voltage of the first semiconductor chip is applied to the first bonding pad through the wire to detect a leakage current. A second end portion of the wire is bonded to the first connection pad by using the capillary, according to a result of the detection. 1. A method of manufacturing a semiconductor package , the method comprising:adhering a first semiconductor chip to a package substrate;bonding a first end portion of a wire to a first bonding pad of the first semiconductor chip by using a capillary;applying an operating voltage of the first semiconductor chip to the first bonding pad through the wire and determining whether a leakage current is detected; andbonding a second end portion of the wire to the first connection pad by using the capillary, based on a result of the determining.2. The method of claim 1 , wherein the first bonding pad comprises a power pad.3. The method of claim 1 , wherein the applying comprises applying the operating voltage of at least about 1.8 V to the first bonding pad.4. The method of claim 1 , further comprising:applying a current or a voltage to the first bonding pad through the wire to detect at least one of a wire open failure and a wire short failure, prior to the bonding the second end portion of the wire to the first connection pad.5. The method of claim 4 , wherein the applying the current or the voltage comprises:applying a first voltage to the first bonding pad to detect the wire open failure based on a current flowing through the first bonding pad; andapplying a second voltage greater than the first voltage to the first bonding pad to detect the wire short failure based on the current flowing through the first bonding pad.6. The method of claim 4 , wherein the applying the current or ...

Self-repair logic for stacked memory architecture

Self-repair logic for stacked memory architecture. An embodiment of a memory device includes a memory stack having one or more memory die elements, including a first memory die element, and a system element coupled with the memory stack. The first memory die element includes multiple through silicon vias (TSVs), the TSVs including data TSVs and one or more spare TSVs, and self-repair logic to repair operation of a defective TSV of the plurality of data TSVs, the repair of operation of the defective TSV including utilization of the one or more spare TSVs.

CONCURRENT TESTING OF A LOGIC DEVICE AND A MEMORY DEVICE WITHIN A SYSTEM PACKAGE

Testing packaged integrated circuit (IC) devices is difficult and time consuming. When multiple devices (dies) are packaged to produce a SiP (system in package) the devices should be tested for defects that may be introduced during the packaging process. With limited access to the inputs and outputs of the devices, test times increase compared with testing the devices before they are packaged. A CoWoS (chip on wafer on substrate) SiP includes a logic device and a memory device and has interfaces between the logic device and memory device that cannot be directly accessed at a package ball. Test programs are concurrently executed by the logic device and the memory device to reduce testing time. Each memory device includes a BIST (built-in self-test) module that is initialized and executes the memory test program while the one or more modules within the logic device are tested. 1. A computer-implemented method , comprising:initializing a memory device within a system package for testing, wherein the system package includes the memory device and a logic device, a first portion of signals between the memory device and a logic device are routed within an interposer or through silicon vias (TSVs) enclosed by the system package and a second portion of signals for the logic device are coupled to package balls of the system package;executing a first test program to test the memory device; andconcurrent with execution of the first test program, executing a second test program to test a first module within the logic device.2. The computer-implemented method of claim 1 , further comprising claim 1 , concurrent with execution of the first test program claim 1 , executing a third test program to test a second module within the logic device.3. The computer-implemented method of claim 2 , wherein the second test program and the third test program are executed concurrently.4. The computer-implemented method of claim 2 , wherein the second test program and the third test program are ...

APPARATUSES AND METHODS FOR TSV RESISTANCE AND SHORT MEASUREMENT IN A STACKED DEVICE

Examples described herein include apparatuses and methods TSV resistance and short measurement in a stacked device. An example apparatus may include a chip comprising semiconductor substrate including a first surface and a second surface opposite to the first surface. The chip may include a first terminal formed above the first surface, a second terminal formed above the second surface, a buffer circuit coupled between the first and second terminals, a first through-substrate via (TSV) penetrating the semiconductor substrate, and a first switch coupled between the first terminal and the first TSV. 1. A method comprising:providing a force signal from a force signal driver circuit to a first terminal of a first chip of a stacked semiconductor device via a first switch on the first chip;coupling a sense circuit to the first terminal via a second switch on the first chip to provide a sense signal;coupling the sense circuit to a second terminal on a second chip of the stacked semiconductor device to provide a sense feedback signal;sensing impedance between the first terminal and the second terminal based on the sense signal and the sense feedback signal.2. The method of claim 1 , further comprising:coupling the force signal driver circuit to the second terminal on the second chip of the stacked semiconductor device to provide a force feedback signal; andadjusting the force signal based on the force feedback signal.3. The method of claim 2 , wherein coupling the force signal driver circuit to the second terminal on the second chip of the stacked semiconductor device comprises enabling a third switch on the second chip.4. The method of claim 1 , wherein the first chip is separated from the second chip by at least one other chip of the stacked semiconductor device.5. The method of claim 1 , wherein the first terminal is along a first through-substrate via (TSV) column of the stacked semiconductor device and the second terminal is along a second TSV column of the stacked ...

SCAN TESTABLE THROUGH SILICON VIAs

The disclosure describes a novel method and apparatus for testing different types of TSVs in a single die or different types of TSV connections in a stack of die. The testing is facilitated by test circuitry associated with each type of TSV. The test circuitry includes a scan cell adapted for testing TSVs. 1. An integrated circuit comprising:(a) a die having a top surface and a bottom surface;(b) a top contact point on the top surface and a bottom contact point on the bottom surface;(c) a through silicon via in the die having a top end coupled to the top contact point and a bottom end coupled to the bottom contact point;(d) a three state buffer having an input coupled to one of the top contact point and the bottom contact point, an output coupled to one end of the through silicon via, and a control input; and(e) a scan cell having a reference voltage input, a serial data input, a control input, a stimulus output coupled to the output of the three state buffer and the one end of the through silicon via, a response input coupled to the other end of the through silicon via, and a serial data output.2. The integrated circuit of in which the top end of the though silicon via is coupled to the top contact point and the response input claim 1 , the three state buffer input is coupled to the bottom contact point claim 1 , and the three state buffer output is coupled to the bottom end of the through silicon via.3. The integrated circuit of in which the bottom end of the though silicon via is coupled to the bottom contact point and the response input claim 1 , the three state buffer input is coupled to the top contact point claim 1 , and the three state buffer output is coupled to the top end of the through silicon via.4. The integrated circuit of including a switch and a load resistor coupled in series between the response input and ground claim 1 , and the switch includes a load input.5. The integrated circuit of in which the scan cell includes a multiplexer and a flip-flop ...

SYSTEM AND METHODS FOR PRODUCING MODULAR STACKED INTEGRATED CIRCUITS

A system according to some examples herein includes a base chip which may include a plurality of attachment slots for attaching dies thereto. One or more of the attachment slots may be programmable attachment slots. The base chip may further include circuitry for interconnecting the dies attached to the base chip. For example, the base chip may include a plurality of cross bar switches, each of which is associated with respective ones of the plurality of attachment slots. The base chip may further include a configuration block, which is adapted to receive and transmit test signals for determining electrically connected signal lines of one or more attachment slots when one or more dies are attached to the base chip and which is further adapted to receive configuration data for programming signal (including power and ground) channels of the cross bar switches. 1. A system comprising: a plurality of attachment slots for attaching dies thereto;', 'a plurality of cross bar switches, each of the plurality of cross bar switches associated with respective ones of the plurality of attachment slots; and', 'a test and configuration block configured to receive and transmit test signals for determining electrically connected signal lines of one or more attachment slots when one or more dies are attached to the base chip and further configured to receive configuration data for programming one or more of the cross bar switches., 'a base chip including2. The system of claim 1 , wherein the test and configuration block comprises circuitry configured to generate the test signals for determining connectivity between metal contacts of the base chip and metal contacts of a die attached to the base chip.3. The system of claim 1 , wherein the test and configuration block comprises circuitry configured to determine connectivity between metal contacts of the base chip and metal contacts of a die attached to the base chip claim 1 , the metal contacts of the die having a different size or ...

STACKED SEMICONDUCTOR APPARATUS BEING ELECTRICALLY CONNECTED THROUGH THROUGH-VIA AND MONITORING METHOD

A semiconductor apparatus includes a plurality of stacked chips. Each of the plurality of stacked chips includes a delay chain. Each of the plurality of stacked chips comprises a plurality of Through-Vias, wherein one of the plurality of Through-Vias formed in a first one of the plurality of stacked chips and electrically coupled to a predetermined location of a first delay chain on the first one of the plurality of stacked chips and one of the plurality of Through-Vias formed in a neighboring one of the plurality of stacked chips and electrically coupled to a predetermined location of a delay chain on the neighboring one of the plurality of stacked chips are configured to electrically couple the first one of the plurality of stacked chips to the neighboring one of the plurality of stacked chips. A signal transmitted from a first one of the plurality of stacked chips generates a feedback signal to the first one of the plurality of stacked chips through one or more of the plurality of Through-Vias. 1. A monitoring method of a semiconductor apparatus including a plurality of delay portions and a plurality of chips electrically coupled to one another through a plurality of Through-Vias , the monitoring method comprising:setting a reference chip as a reference to form a oscillating path;forming an oscillating path passing through two or more Through-Vias coupled to two or more chips; andmonitoring characteristics of the two or more Through-Vias based on a signal provided through the oscillating path.2. The monitoring method of claim 1 , wherein the reference chip is set on the basis of a stacked chip information.3. The monitoring method of claim 1 , wherein the selecting of the oscillating path passing through the at least two of the plurality of Through-Vias is based on stacked chip information and path selection information.4. The monitoring method of claim 1 , wherein the characteristics of the two or more Through-Vias include a delay amount and a cross-talk effect ...

3DI Solder Cup

A substrate or semiconductor device, semiconductor device assembly, and method of forming a semiconductor device assembly that includes a barrier on a solder cup. The semiconductor device assembly includes a substrate disposed over another substrate. At least one solder cup extends from one substrate towards an under bump metal (UBM) on the other substrate. The barrier on the exterior of the solder cup may be a standoff to control a bond line between the substrates. The barrier may reduce solder bridging during the formation of a semiconductor device assembly. The barrier may help to align the solder cup with a UBM when forming a semiconductor device assembly and may reduce misalignment due to lateral movement of substrates and/or semiconductor devices. 1. A device comprising:a substrate;an electrical interconnect within the substrate;a barrier structure electrically connected to the electrical interconnect, the barrier structure having a funnel-shaped recess defined therein; andsolder positioned within the funnel-shaped recess of the barrier structure.2. The device of claim 1 , further comprising:a copper structure positioned within the funnel-shaped recess of the barrier structure; anda nickel structure positioned within the funnel-shaped recess of the barrier structure.3. The device of claim 1 , wherein the barrier structure comprises tantalum claim 1 , tungsten claim 1 , titanium nitride claim 1 , or combinations thereof.4. The device of claim 1 , further comprising:a semiconductor device having a via and an under bump metal (UBM) electrically connected to the via, and wherein the UBM is encased in the solder within the funnel-shaped recess of the barrier structure.5. The device of claim 4 , wherein the UBM includes angled sidewalls.6. The device of claim 5 , wherein the angled sidewalls of the UBM are configured to produce a wetting force between the substrate and the semiconductor device during thermal compression bonding.7. The device of claim 4 , wherein the ...

THROUGH-SILICON VIA (TSV) TEST CIRCUIT, TSV TEST METHOD AND INTEGRATED CIRCUITS (IC) CHIP

An integrated circuit (IC) with a TSV test circuit, a TSV test method are provided, pertaining to IC technologies. The IC may include a first TSV, a second TSV and a phase detector. A first end of the first TSV may be coupled to a predetermined signal output, and a second end of the first TSV may be coupled to a first end of the second TSV. A second end of the second TSV may be coupled to a first input of the phase detector, and a second input of the phase detector may be coupled to the predetermined signal output. The phase detector may be configured to determine a phase difference between signals at the first and the second inputs. In this IC, a defective TSV can be identified and segregated with a redundant TSV. This IC facilitates efficient fault correction and signal routing in the IC. 1. An integrated circuit (IC) with a through-silicon via (TSV) test circuit , comprising a first TSV , a second TSV and a phase detector ,a first end of the first TSV coupled to a predetermined signal output, and a second end of the first TSV coupled to a first end of the second TSV,a second end of the second TSV coupled to a first input of the phase detector,a second input of the phase detector coupled to the predetermined signal output,wherein the phase detector is configured to determine a phase difference between a signal at the first input of the phase detector and a signal at the second input of the phase detector, and wherein a test result is determined by comparing the phase difference with a predetermined threshold.2. The IC of claim 1 , wherein each of the first and the second TSVs connects two or more stacked tiers.3. The IC of claim 1 , further comprising:a first selector and a first distributor, the first selector comprising a first input, a second input, a control terminal and an output, the first distributor comprising an input, a control terminal, a first output and a second output,the first input of the first selector configured to receive a first operational ...

SEMICONDUCTOR DEVICE AND METHOD OF ALIGNING SEMICONDUCTOR WAFERS FOR BONDING

A semiconductor device has a first semiconductor wafer. The first semiconductor wafer is singulated to provide a first wafer section including at least one first semiconductor die or a plurality of first semiconductor die. The first wafer section is a fractional portion of the first semiconductor wafer. An edge support structure is formed around the first wafer section. A second wafer section includes at least one second semiconductor die. The second wafer section can be an entire second semiconductor wafer. The first semiconductor die is a first type of semiconductor device and the second semiconductor die is a second type of semiconductor device. An alignment opening is formed through the first wafer section and second wafer section with a light source projected through the opening. The first wafer section is bonded to the second wafer section with the first semiconductor die aligned with the second semiconductor die. 1. A method of making a semiconductor device , comprising:providing a first semiconductor wafer;singulating the first semiconductor wafer into a plurality of first wafer sections each with a plurality of first semiconductor die;providing a second wafer including a plurality of second semiconductor die; andbonding the first wafer sections to portions of the second wafer with the first semiconductor die each aligned respectively with the second semiconductor die.2. The method of claim 1 , wherein the first wafer sections are a fractional portion of the first semiconductor wafer.3. The method of claim 1 , wherein the first semiconductor die is a first type of semiconductor device and the second semiconductor die is a second type of semiconductor device.4. The method of claim 1 , wherein a size of the first semiconductor die is different than a size of the second semiconductor die.5. The method of claim 1 , further including forming an alignment opening through the first wafer sections and second wafer.6. The method of claim 1 , wherein the first wafer ...

EMBEDDED MEMORY DEVICE AND METHOD FOR EMBEDDING MEMORY DEVICE IN A SUBSTRATE

A system and method of providing high bandwidth and low latency memory architecture solutions for next generation processors is disclosed. The package contains a substrate, a memory device embedded in the substrate via EMIB processes and a processor disposed on the substrate partially over the embedded memory device. The I/O pads of the processor and memory device are vertically aligned to minimize the distance therebetween and electrically connected through EMIB uvias. An additional memory device is disposed on the substrate partially over the embedded memory device or on the processor. I/O signals are routed using a redistribution layer on the embedded memory device or an organic VHD redistribution layer formed over the embedded memory device when the additional memory device is laterally adjacent to the processor and the I/O pads of the processor and additional memory device are vertically aligned when the additional memory device is on the processor. 1. An electronic package comprising:a substrate comprising a cavity;a memory device embedded in the cavity and comprising input/output (I/O) memory device pads; anda processor disposed on the substrate and comprising I/O processor pads, the I/O processor and memory device pads vertically aligned and electrically connected.2. The package of claim 1 , wherein the memory device comprises a plurality of contact pads that include the I/O memory device pads claim 1 , ground pads connected with ground claim 1 , power pads connected with power and test pads to test and debug the memory device claim 1 , the test pads disposed on an opposite edge of the memory device as the I/O memory device pads.3. The package of claim 1 , wherein the memory device and the processor partially overlap such that the memory device and the processor extend laterally in opposite directions from the I/O processor and memory device pads.4. The package of claim 1 , further comprising power and ground strips disposed on a surface of the substrate ...

SEMICONDUCTOR MEMORY DEVICE

According to one embodiment, a semiconductor memory device includes a memory cell, a first voltage generator and a second voltage generator. The memory cell is provided above a substrate. The first voltage generator is provided between the substrate and the memory cell. The first voltage generator is configured to generate a first voltage to be supplied to the memory cell. The second voltage generator is provided between the substrate and the memory cell. The second voltage generator is configured to generate the first voltage and have a circuit configuration equivalent to the first voltage generator. 1. A semiconductor memory device comprising:a memory cell above a substrate;a first voltage generator between the substrate and the memory cell, the first voltage generator being configured to generate a first voltage to be supplied to the memory cell; anda second voltage generator between the substrate and the memory cell, the second voltage generator being configured to generate the first voltage and having a circuit configuration equivalent to the first voltage generator.2. The semiconductor memory device according to claim 1 , further comprising:a word line electrically connected to a gate of the memory cell;a bit line electrically connected to an end of the memory cell;a first row logic control circuit between the substrate and the memory cell, the first row logic control circuit being configured to select the word line based on a row address and control a voltage to be supplied to the selected word line;a second row logic control circuit between the substrate and the memory cell, the second row logic control circuit having a circuit configuration equivalent to the first row logic control circuit;a first column logic control circuit between the substrate and the memory cell, the first column logic control circuit being configured to select the bit line based on a column address and control a voltage to be supplied to the selected bit line; anda second column logic ...

Semiconductor device and method of forming micro interconnect structures

A semiconductor device has a first semiconductor die and second semiconductor die with a conductive layer formed over the first semiconductor die and second semiconductor die. The second semiconductor die is disposed adjacent to the first semiconductor die with a side surface and the conductive layer of the first semiconductor die contacting a side surface and the conductive layer of the second semiconductor die. An interconnect, such as a conductive material, is formed across a junction between the conductive layers of the first and second semiconductor die. The conductive layer may extend down the side surface of the first semiconductor die and further down the side surface of the second semiconductor die. An extension of the side surface of the first semiconductor die can interlock with a recess of the side surface of the second semiconductor die. The conductive layer extends over the extension and into the recess.

Semiconductor device and method of forming cantilevered protrusion on a semiconductor die

A semiconductor device has a first semiconductor die with a base material. A covering layer is formed over a surface of the base material. The covering layer can be made of an insulating material or metal. A trench is formed in the surface of the base material. The covering layer extends into the trench to provide the cantilevered protrusion of the covering layer. A portion of the base material is removed by plasma etching to form a cantilevered protrusion extending beyond an edge of the base material. The cantilevered protrusion can be formed by removing the base material to the covering layer, or the cantilevered protrusion can be formed within the base material under the covering layer. A second semiconductor die is disposed partially under the cantilevered protrusion. An interconnect structure is formed between the cantilevered protrusion and second semiconductor die.

SEMICONDUCTOR PACKAGE DEVICE

A semiconductor package may include a first chip located over a substrate. The semiconductor package may include a second chip located over the substrate and adjacent to the first chip. The semiconductor package may include a test micro-bump located at a layer below the first chip and above the substrate, and electrically coupled to an external connection member through a first path. The semiconductor package may include a normal micro-bump located at a layer below the first chip and above the substrate, and electrically coupled to the second chip through a second path. 1. A semiconductor package device comprising:a first chip located over a substrate;a second chip located over the substrate and adjacent to the first chip on the same layer as in the first chip;a test micro-bump located at a layer below the first chip and above the substrate, and electrically coupled to an external connection member through a first path;a normal micro-bump located at a layer below the first chip and above the substrate, and electrically coupled to the second chip through a second path; anda molding member molded into a predetermined region of an outer wall of the first chip, and formed over the test micro-bump and the normal micro-bump.2. The semiconductor package device according to claim 1 , wherein the second chip is a System On Chip (SOC).3. The semiconductor package device according to claim 1 , wherein the first chip includes a Dynamic Random Access Memory (DRAM).4. The semiconductor package device according to claim 1 , further comprising:a plurality of micro-bumps located between a lower region of the second chip and the substrate.5. (canceled)6. The semiconductor package device according to claim 1 , further comprising:a first re-distribution layer (RDL) configured to couple the test micro-bump to the first chip through the molding member.7. The semiconductor package device according to claim 1 , further comprising:a second re-distribution layer (RDL) configured to couple ...

SEMICONDUCTOR DEVICE AND METHOD OF ALIGNING SEMICONDUCTOR WAFERS FOR BONDING

A semiconductor device has a first semiconductor wafer. The first semiconductor wafer is singulated to provide a first wafer section including at least one first semiconductor die or a plurality of first semiconductor die. The first wafer section is a fractional portion of the first semiconductor wafer. An edge support structure is formed around the first wafer section. A second wafer section includes at least one second semiconductor die. The second wafer section can be an entire second semiconductor wafer. The first semiconductor die is a first type of semiconductor device and the second semiconductor die is a second type of semiconductor device. An alignment opening is formed through the first wafer section and second wafer section with a light source projected through the opening. The first wafer section is bonded to the second wafer section with the first semiconductor die aligned with the second semiconductor die. 1. A method of making a semiconductor device , comprising:providing a first semiconductor wafer;singulating the first semiconductor wafer to provide a first wafer section including at least one first semiconductor die;providing a second wafer section including at least one second semiconductor die; andbonding the first wafer section to the second wafer section with the first semiconductor die aligned with the second semiconductor die.2. The method of claim 1 , wherein the first wafer section is a fractional portion of the first semiconductor wafer.3. The method of claim 1 , wherein the first semiconductor die is a first type of semiconductor device and the second semiconductor die is a second type of semiconductor device.4. The method of claim 1 , wherein the second wafer section is an entire second semiconductor wafer.5. The method of claim 1 , further including forming an alignment opening through the first wafer section and second wafer section.6. The method of claim 1 , further including forming an edge support structure around the first wafer ...

Replication of a first interface onto a second interface and related systems, methods, and devices

Disclosed herein are systems, methods, and devices that enable access to a first interface control circuit via test probes of a second interface. In some embodiments a memory device includes a first interface including first ports that are inaccessible to a test probe. The memory device also includes a first interface control circuit configured to control operation of the first interface. The memory device further includes a second interface including second ports. At least a portion of the second ports include test pads that are accessible to the test probe. In addition, the memory device includes a multiplexer configured to operably couple the first interface and at least a portion of the second interface to the first interface control circuit. The multiplexer is configured to selectively enable test probe access to the first interface control circuit via the test pads.

INTEGRATED CIRCUIT PACKAGE ASSEMBLY WITH WIRE END ABOVE A TOPMOST COMPONENT

Embodiments of the present disclosure describe integrated circuit (IC) package assemblies having one or more wires that extend beyond a topmost component in the IC package assembly, computing devices incorporating the IC package assemblies, methods for formation of the IC package assemblies, and associated configurations. An IC package assembly may include a substrate having a first side and a second side opposite the first side, an IC die having a first side and a second side opposite the first side, where the first side of the IC die faces the first side of the substrate, a wire electrically coupled with the IC die, where an end of the wire extends beyond a topmost component in the IC package assembly, and an overmold coupled with the topmost component. Other embodiments may be described and/or claimed. 1. An integrated circuit (IC) package assembly comprising:a substrate having a first side and a second side opposite the first side;an IC die having a first side and a second side opposite the first side, wherein the first side of the IC die faces the first side of the substrate; anda wire electrically coupled with the IC die, wherein an end of the wire extends beyond a topmost component in the IC package assembly, to provide electrical access to circuitry residing in the IC package assembly, wherein the topmost component is the component in the IC package assembly having a surface located the farthest from the substrate of any components other than one or more testing wires in the IC package assembly, wherein the wire is one of the one or more testing wires.2. The IC package assembly of claim 1 , further comprising an overmold coupled with the topmost component.3. The IC package assembly of claim 2 , wherein the topmost component is the IC die.4. The IC package assembly of claim 2 , wherein the IC die is a first IC die claim 2 , the wire is a first wire claim 2 , and the IC package assembly further comprises:a second IC die between the first IC die and the ...

PACKAGE STRUCTURE AND METHOD OF MANUFACTURING THE SAME

A package structure and a method of manufacturing the same are provided. The package structure includes a die, a redistribution layer (RDL) structure, a through integrated fan-out via (TIV) and a first connector. The RDL structure is connected to the die and includes a plurality of RDLs. The TIV is aside the die and penetrates through the RDL structure. The first connector is in electrical contact with the TIV and electrically connected to the die. The TIV is in electrical contact with the RDLs of the RDL structure. 1. A package structure , comprising:a die;a redistribution line (RDL) structure connected to the die, wherein the RDL structure comprises a plurality of RDLs;a through integrated fan-out via (TIV) aside the die and penetrating through the RDL structure; anda first connector in electrical contact with the TIV and electrically connected to the die,wherein the TIV is in electrical contact with the RDLs of the RDL structure.2. The package structure of claim 1 , wherein the TIV comprises a first seed layer and a conductive post claim 1 , and the conductive post is in electrical contact with the first connector.3. The package structure of claim 2 , wherein a portion of sidewalls of the conductive post is covered by the fist seed layer.4. The package structure of claim 3 , wherein an end of the TIV has a stepped shape.5. The package structure of claim 4 , wherein the first seed layer and an end of the conductive post have stepped shapes.6. The package structure of claim 2 , wherein the RDLs comprises a second seed layer and a conductive layer.7. The package structure of claim 6 , wherein a bottom surface of the first connector is in electrical contact with the first seed layer and the conductive post of the TIV and the conductive layer of the RDLs claim 6 , and sidewalls of the first connector are in electrical contact with the second seed layer of the RDLs.8. The package structure of claim 6 , further comprises a second connector disposed over the die claim 6 ...

Packaged integrated circuit device with cantilever structure

Techniques and mechanisms to facilitate connection with one or more integrated circuit (IC) dies of a packaged device. In an embodiment, the packaged device includes a first substrate coupled to a first side of a package, and a second substrate coupled to a second side of the package opposite the first side. Circuitry, coupled via the first substrate to one or more IC dies disposed in the package, includes a circuit structure disposed at a cantilever portion of the first substrate. The cantilever portion extends past one or both of an edge of the first side and an edge of the second side. In another embodiment, a hardware interface disposed on the second substrate enables coupling of the packaged device to another device.

MULTI-CHIP PACKAGE, TEST SYSTEM AND METHOD OF OPERATING THE SAME

A multi-chip package includes: a plurality of semiconductor chips that are coupled with each other through normal through silicon vias and repair through silicon vias; a state detection device suitable for detecting connection states of the normal through silicon vias and the repair through silicon vias; and a repair control device suitable for comparing the connection state of the normal through silicon vias with the connection state of the repair through silicon vias, and controlling whether to perform a repair operation. 1. A multi-chip package comprising:a plurality of semiconductor chips that are coupled with each other through normal through silicon vias and repair through silicon vias;a state detection device suitable for detecting connection states of the normal through silicon vias and the repair through silicon vias; anda repair control device suitable for comparing the connection states of the normal through silicon vias with the connection states of the repair through silicon vias, and controlling whether to perform a repair operation.2. The multi-chip package of claim 1 , wherein test data is applied to each of the normal through silicon vias and the repair through silicon vias during a test operation.3. The multi-chip package of claim 1 , wherein the state detection device includes:a first normal/failed detector suitable for receiving test data transmitted through the normal through silicon vias and generating a first detection signal; anda second normal/failed detector suitable for receiving test data transmitted through the repair through silicon vias and generating a second detection signal.4. The multi-chip package of claim 1 , wherein the repair control device includes:a normal/failed counter suitable for receiving an output signal of the state detection device and counting a number of normal through silicon vias that are failed and a number of repair through silicon vias that operate normally;an enable controller suitable for comparing the number ...

A STACKED SEMICONDUCTOR PACKAGE HAVING FAULT DETECTION AND A METHOD FOR IDENTIFYING A FAULT IN A STACKED PACKAGE

A stacked semiconductor package comprising a functional silicon die having embedded thereupon a Wide Input/Output 2 (WIO2) interface, and two or more memory dies forming a corresponding two or more memory layers of the stacked semiconductor package. A plurality of Through Silicon Vias (TSVs) are formed through the two or more memory dies, wherein each of the plurality of TSVs traverse through the two or more memory layers to the functional silicon die via the WIO2 interface of the functional silicon die. A test port interface receives test signals from an external tester and routes the test signals through a steering logic communicably interfaced with the two or more memory dies. The steering logic shifts data into and out of the two or more memory dies through the plurality of TSVs. 1. A stacked semiconductor package , comprising:a functional silicon die having embedded thereupon a Wide Input/Output 2 (WIO2) interface, the functional silicon die forming a first layer of the stacked semiconductor package;two or more memory dies forming a corresponding two or more memory layers of the stacked semiconductor package;a plurality of Through Silicon Vias (TSVs) formed through the two or more memory dies, wherein each of the plurality of TSVs traverse through the two or more memory layers to the functional silicon die at the first layer of the stacked semiconductor package via the WIO2 interface of the functional silicon die;a test port interface to receive test signals from an external tester and route the test signals through a steering logic communicably interfaced with the two or more memory dies;wherein the steering logic is to shift data into the two or more memory dies through the plurality of TSVs pursuant to the received test signals from the external tester; andwherein the steering logic is to further shift the data out of the two or more memory dies as output data and return the output data to the external tester via the test port interface.2. The stacked ...

SEMICONDUCTOR DEVICE HAVING CHIP-TO-CHIP BONDING STRUCTURE

A semiconductor device includes a first chip, divided into a plurality of regions, including a plurality of first pads and a plurality of first test pads in each of the plurality of regions; and a second chip including a plurality of second pads corresponding to the plurality of first pads and a plurality of second test pads corresponding to the plurality of first test pads, and bonded onto the first chip such that the plurality of second pads are coupled to the plurality of first pads. The second chip includes a voltage generation circuit linked to the plurality of second pads, that provides a compensated voltage to the plurality of second pads for each of the plurality of regions, based on a voltage drop value for each region due to a contact resistance between the plurality of first test pads and the plurality of second test pads. 1. A semiconductor device comprising:a first chip, divided into a plurality of regions, including a plurality of first pads and a plurality of first test pads in each of the plurality of regions; anda second chip including a plurality of second pads corresponding to the plurality of first pads and a plurality of second test pads corresponding to the plurality of first test pads, and bonded onto the first chip such that the plurality of second pads are coupled to the plurality of first pads,wherein the second chip includes a voltage generation circuit, linked to the plurality of second pads, that provides a compensated voltage to the plurality of second pads for each of the plurality of regions, based on a voltage drop value for each region due to a contact is resistance between the plurality of first test pads and the plurality of second test pads.2. The semiconductor device according to claim 1 , wherein the voltage generation circuit comprises:a plurality of reference voltage compensators respectively corresponding to the plurality of regions, and each of the plurality of reference voltage compensators configured to generate a ...

SEMICONDUCTOR PACKAGE INCLUDING TEST BUMPS

Disclosed is a semiconductor package comprising a first semiconductor chip and at least one second semiconductor chip on the first semiconductor chip. The second semiconductor chip includes first and second test bumps that are adjacent to an edge of the second semiconductor chip and are on a bottom surface of the second semiconductor chip. The first and second test bumps are adjacent to each other. The second semiconductor chip also includes a plurality of data bumps that are adjacent to a center of the second semiconductor chip and are on the bottom surface of the second semiconductor chip. A first interval between the second test bump and one of the data bumps is greater than a second interval between the first test bump and the second test bump. The one of the data bumps is most adjacent to the second test bump. 1. A semiconductor package , comprising:a first semiconductor chip;at least one second semiconductor chip stacked on the first semiconductor chip;a mold layer covering the first semiconductor chip and the second semiconductor chip,wherein the first semiconductor chip has a width greater than a width of the second semiconductor chip, a plurality of outer bumps on a bottom surface of the second semiconductor chip and being adjacent to an edge of the second semiconductor chip;', 'a plurality of inner bumps on the bottom surface of the second semiconductor chip and being adjacent to a center of the second semiconductor chip', 'a plurality of first through electrodes penetrating the second semiconductor chip and connected with the outer bumps; and', 'a plurality of second through electrodes penetrating the second semiconductor chin and connected with the inner bumps,, 'wherein the second semiconductor chip includeswherein a first interval between one of the outer bumps and one of the plurality of inner bumps that in moot adjacent to each other being greater than a second interval between the outer bumps, andwherein the outer bumps have a width equal to or ...

APPARATUSES AND METHODS FOR TSV RESISTANCE AND SHORT MEASUREMENT IN A STACKED DEVICE

Examples described herein include apparatuses and methods TSV resistance and short measurement in a stacked device. An example apparatus may include a chip comprising semiconductor substrate including a first surface and a second surface opposite to the first surface. The chip may include a first terminal formed above the first surface, a second terminal formed above the second surface, a buffer circuit coupled between the first and second terminals, a first through-substrate via (TSV) penetrating the semiconductor substrate, and a first switch coupled between the first terminal and the first TSV. 1. An apparatus comprising: a semiconductor substrate including a first surface and a second surface opposite to the first surface;', 'a first terminal formed above the first surface;', 'a second terminal formed above the second surface;', 'a buffer circuit coupled between the first and second terminals;', 'a first through-substrate via (TSV) penetrating the semiconductor substrate; and', 'a first switch coupled between the first terminal and the first TSV., 'a chip comprising2. The apparatus of claim 1 , wherein the chip comprises:second, third, and fourth TSVs penetrating the semiconductor substrate;a second switch coupled between the first terminal and the second TSV;a third switch coupled between the second terminal and the third TSV; anda fourth switch coupled between the second terminal and the fourth TSV.3. The apparatus of claim 1 , wherein the second terminal is arranged to shift in a vertical direction without arranging above the first terminal in the vertical direction.4. The apparatus of claim 1 , further comprising a control circuit configured to turn on the first switch in the at least one of the plurality of stacked chips in a test mode and turn off the first switch in each of the plurality of stacked chips in a normal mode.5. The apparatus of claim 1 , wherein the buffer circuit is configured to provide signals between the first and second terminals in ...

APPARATUSES FOR SELECTIVE TSV BLOCK TESTING

Embodiments of the disclosure are drawn to apparatuses and methods for testing through silicon vias (TSVs) which may be used, for example, to couple layers of a semiconductor memory device. The TSVs and/or the die around the TSVs may require testing. A switch circuit may be used to selectively couple one or more test circuits to an amplifier. The test circuits may generate a voltage that is related to one or more parameters of the TSV being tested. The amplifier may amplify the voltage, which may be used to determine if the TSV passes the particular test determined by the test circuit selected by the switch circuit. The switch circuit and/or other components of the test circuits may be controlled by control signals to determine the operation of a particular test. 1. An apparatus comprising:an interface (IF) die; andat least one memory die, wherein the at least one memory die is stacked over the IF die through a plurality of through substrate vias (TSVs);wherein the IF die comprises an instrumentation amplifier configured to be coupled to selected one or ones of the plurality of TSVs to perform at least one of:a first test to measure a first voltage drop related to a voltage drop between a target TSV of the plurality of TSVs and one or more other TSVs of the plurality of TSVs;a second test to measure a second voltage drop related to a voltage drop between a target TSV of the plurality of TSVs and a first power supply line;a third test to measure a third voltage drop related to a voltage drop between a target TSV of the plurality of TSVs and a second power supply line; anda fourth test to measure a fourth voltage drop related to a voltage drop across a conductive line formed around the plurality of TSVs.2. The apparatus of claim 1 ,wherein the instrumentation amplifier includes first and second input nodes; and flowing a current through the target TSV and the one or more other TSVs,', 'coupling the first input node of the instrumentation amplifier to the target TSV, ...

Through silicon via repair circuit

A through silicon via (TSV) repair circuit is provided. The TSV repair circuit includes at least two transmission control switches and at least two transmission path modules. Two transmission control switches transmit an input signal of a first chip or a second chip to one of two terminals in each of the transmission path modules according to a switch signal. Each transmission path module includes at least two data path circuits and corresponding TSVs. Each data path circuit includes an input driving circuit, a short-circuit detection circuit and a leakage current cancellation circuit. The short-circuit detection circuit detects whether to detect whether short-circuit on the TSV and a silicon substrate is present and generate a short-circuit detection output signal. The leakage current cancellation circuit to avoid a leakage current generated by a first level voltage to flow into the silicon substrate according to the short-circuit detection output signal.

ELECTRONIC SYSTEM HAVING INCREASED COUPLING BY USING HORIZONTAL AND VERTICAL COMMUNICATION CHANNELS

An electronic system supports superior coupling by implementing a communication mechanism that provides at least for horizontal communication for example, on the basis of wired and/or wireless communication channels, in the system. Hence, by enhancing vertical and horizontal communication capabilities in the electronic system, a reduced overall size may be achieved, while nevertheless reducing complexity in printed circuit boards coupled to the electronic system. In this manner, overall manufacturing costs and reliability of complex electronic systems may be enhanced. 1. An apparatus , comprising:an integrated circuit die comprising a semiconductor substrate and a metallization structure;wherein the semiconductor substrate includes integrated circuits and has a top surface and an oppositely arranged bottom surface and a side surface where the integrated circuit die was singulated from a wafer;wherein the metallization structure is mounted above the top surface of the semiconductor substrate and includes at least one contact pad and an electrical connection between the at least one contact pad and the integrated circuits; anda dielectric layer disposed in contact with a top surface of the metallization structure and the side surface of the semiconductor substrate;wherein the dielectric layer comprises a first communication pad that is electrically connected to said at least one contact pad and a second communication pad that is electrically connected to said at least one contact pad;wherein the first communication pad is disposed on a first face of the dielectric layer extending parallel to the top surface of the metallization structure and the second communication pad is disposed on a second face of the dielectric layer extending parallel to the side surface of the semiconductor substrate.2. The apparatus of claim 1 , wherein the second communication pad is electrically insulated from the side surface of the semiconductor substrate by said dielectric layer and ...

STACKED SEMICONDUCTOR APPARATUS BEING ELECTRICALLY CONNECTED THROUGH THROUGH-VIA AND MONITORING METHOD

A semiconductor apparatus includes a plurality of stacked chips. Each of the plurality of stacked chips includes a delay chain. Each of the plurality of stacked chips comprises a plurality of Through-Vias, wherein one of the plurality of Through-Vias formed in a first one of the plurality of stacked chips and electrically coupled to a predetermined location of a first delay chain on the first one of the plurality of stacked chips and one of the plurality of Through-Vias formed in a neighboring one of the plurality of stacked chips and electrically coupled to a predetermined location of a delay chain on the neighboring one of the plurality of stacked chips are configured to electrically couple the first one of the plurality of stacked chips to the neighboring one of the plurality of stacked chips. A signal transmitted from a first one of the plurality of stacked chips generates a feedback signal to the first one of the plurality of stacked chips through one or more of the plurality of Through-Vias. 1. A semiconductor apparatus comprising:an oscillating control portion disposed in a first chip, and configured to generate a transmission signal by receiving an input signal and a feedback signal;first and second Through-Vias configured to electrically couple the first chip and a second chip;a first delay portion disposed in the first chip, and coupled to the first and second Through-Vias;a second delay portion disposed in the second chip, and coupled to the first and second Through-Vias; anda first switching portion configured to electrically couple the first chip to the first and second Through-Vias based on a first switch control signal.2. The semiconductor apparatus of claim 1 , wherein claim 1 , when the first switching portion electrically couples the first chip to the first and second Through-Vias claim 1 , the oscillating portion transmits the transmission signal to the first Through-Via and receives the feedback signal from the second Through-Via.3. The ...

SCAN TESTABLE THROUGH SILICON VIAs

The disclosure describes a novel method and apparatus for testing different types of TSVs in a single die or different types of TSV connections in a stack of die. The testing is facilitated by test circuitry associated with each type of TSV. The test circuitry includes a scan cell adapted for testing TSVs. 1. An integrated circuit comprising:(a) a die having a top surface and a bottom surface;(b) a top contact point on the top surface and a bottom contact point on the bottom surface;(c) a through silicon via in the die having a top end coupled to the top contact point and a bottom end coupled to the bottom contact point;(d) a first switch having a first lead connected to the top contact point, a second lead connected to the top end of the through silicon via, a response lead, and a control input; and(e) a scan cell having a reference voltage input, a serial data input, a control input, a stimulus output coupled to between bottom top contact point and the bottom end of the through silicon via, a response input connected to the response lead, and a serial data output.2. The integrated circuit of in which the bottom end of the though silicon via is connected to the bottom contact point and the stimulus input.3. The integrated circuit of including a switch and a load resistor coupled in series between the response input and ground claim 1 , and the switch includes a load input.4. The integrated circuit of in which the scan cell includes a multiplexer and a flip-flop connected in series between the serial data input and the serial data output. This application is a Divisional of prior application Ser. No. 15/182,817, filed Jun. 15, 2016, currently pending;Which was a divisional of prior application Ser. No. 13/712,459, filed Dec. 12, 2012; now abandoned;And claims priority from Provisional Application No. 61/577,401, filed Dec. 19, 2011.This disclosure is related to pending TI patent TI-71609 which is incorporated herein by reference.This disclosure relates generally to ...

SEMICONDUCTOR DEVICE USING WIRES AND STACKED SEMICONDUCTOR PACKAGE

Disclosed are a semiconductor device and a stacked semiconductor package. The semiconductor device may include a semiconductor chip and a plurality of chip pads disposed on the semiconductor chip in a second horizontal direction perpendicular to a first horizontal direction. The plurality of chip pads may include: a first chip pad connected to a wire extending in the first horizontal direction, when seen from the top; and a second chip pad connected to a diagonal wire extending in a direction at an angle to the first and second horizontal directions, when seen from the top. The width of the first chip pad in the second horizontal direction may be smaller than the width of the second chip pad in the second horizontal direction. 1. A semiconductor device comprising:a semiconductor chip; anda plurality of chip pads disposed on the semiconductor chip in a second horizontal direction perpendicular to a first horizontal direction,wherein the plurality of chip pads comprises:a first chip pad connected to a wire extending in the first horizontal direction, when seen from the top; anda second chip pad connected to a diagonal wire, the diagonal wire extending in a direction at an angle to the first and second horizontal directions, when seen from the top,wherein the width of the first chip pad in the second horizontal direction is smaller than the width of the second chip pad in the second horizontal direction.2. The semiconductor device of claim 1 , wherein the length of the second chip pad in the first horizontal direction is equal to the width of the second chip pad in the second horizontal direction.3. The semiconductor device of claim 1 , wherein the length of the first chip pad in the first horizontal direction is equal to the length of the second chip pad in the first horizontal direction.4. The semiconductor device of claim 1 , further comprising a third chip pad disposed on the semiconductor chip not connected to a wire claim 1 ,wherein the width of the third chip ...

Semiconductor die for determining load of through silicon via and semiconductor device including the same

A semiconductor die may include a first delay circuit formed on a substrate and configured to delay a test signal, the first delay circuit including first delay stages connected in series, a second delay circuit formed on the substrate and configured to delay the test signal, the second delay circuit including second delay stages connected in series, at least one through silicon via connected to at least one output terminal of output terminals of the first delay stages, the at least one through silicon via penetrating through the substrate, and a load determinator configured to compare a first delay signal output from one of the first delay stages with a second delay signal output from one of the second delay stages and determine a load of the at least one through silicon via.

WAFER SCALE TESTING AND INITIALIZATION OF SMALL DIE CHIPS

A chip intermediate body includes a semiconductor region including plural chip areas. The chip areas respectively are cut out as semiconductor chips. A cut region is provided along edges of the chip areas, the cut region being cut to cut out the semiconductor chips. A contact region is provided opposite to the chip areas across the cut region, the contact region being configured to be contacted by a probe of a test unit to test the chip areas, and electric wiring is provided continuously with the cut region to connect the chip areas and the contact region. 1. A chip intermediate body , comprising:a semiconductor region cut from a wafer, with the semiconductor region including a plurality of chip areas, the chip areas respectively being cut out as semiconductor chips;a cut region provided along edges of the chip areas, the cut region being cut to cut out the semiconductor chips;a contact region provided opposite to the chip areas across the cut region, the contact region being configured to be contacted by a probe of a test unit to test the chip areas; andan insulating layer with embedded electric wiring provided continuously with the cut region to connect the chip areas and the contact region.2. The chip intermediate body of claim 1 , wherein each of the chip areas includes bumps on a surface of the chip area.3. The chip intermediate body of claim 2 , whereinthe contact region includes a plurality of test pads,the test pads are configured to be contacted by respective contact points of the probe of the test unit, andeach of the test pads has a larger area than each of the bumps.4. The chip intermediate body of claim 1 , wherein the cut region includes other electric wiring that at least interconnects the chip areas and connects the chip areas and the contact region.5. The chip intermediate body of claim 4 , wherein the other electric wiring is electrically connected with the electric wiring.6. The chip intermediate body of claim 4 , wherein each of the chip areas ...

WAFER SCALE TESTING AND INITIALIZATION OF SMALL DIE CHIPS

A chip intermediate body includes a semiconductor region including plural chip areas. The chip areas respectively are cut out as semiconductor chips. A cut region is provided along edges of the chip areas, the cut region being cut to cut out the semiconductor chips. A contact region is provided opposite to the chip areas across the cut region, the contact region being configured to be contacted by a probe of a test unit to test the chip areas, and electric wiring is provided continuously with the cut region to connect the chip areas and the contact region. 1. A method for testing a chip area comprising:fabricating a chip intermediate body including a semiconductor region, a cut region, a contact region, a test area, and electric wiring, the semiconductor region including a plurality of chip areas arranged as an array and respectively cut out as semiconductor chips, the cut region being provided along edges of the chip areas, the cut region being cut to cut out the semiconductor chips, the contact region being provided opposite to the chip areas across the cut region with a contact pad corresponding to each row of chip areas in the array, the test area including a test circuit corresponding to each column of chip areas in the array, the electric wiring being provided continuously with the cut region to connect the chip areas and the contact region; andtesting the chip areas in parallel with a probe of a test unit contacting the contact region.2. A method for fabricating a semiconductor chip comprising:testing a semiconductor region provided on a chip intermediate body with a probe of a test unit, the chip intermediate body including the semiconductor region, a cut region, a contact region, a test area, and electric wiring, the semiconductor region including a plurality of chip areas arranged as an array and respectively cut out as semiconductor chips, the cut region being provided along edges of the chip areas, the cut region being cut to cut out the semiconductor ...

Semiconductor structure and method for forming the same

A semiconductor structure and a method for forming the same are provided. The method includes following steps. A first wafer is provided, which includes a first region, a second region, and a first semiconductor device disposed in the first region. No semiconductor device is disposed in the second region. A second wafer is provided, which includes a third region, a fourth region and a second semiconductor device disposed in the third region. No semiconductor device is disposed in the fourth region. The first region of the first wafer is overlapped with the fourth region of the second wafer. The second region of the first wafer is overlapped with the third region of the second wafer. A first conductive through via is formed to pass through the fourth region of the second wafer and the first region of the first wafer to electrically connect to the first semiconductor device.

SEMICONDUCTOR DEVICE

A semiconductor device according to the present invention includes: a through via formed to penetrate a semiconductor substrate; first and second buffer circuits; a wiring forming layer formed in an upper layer of the semiconductor substrate; a connecting wiring portion formed in an upper portion of the through via assuming that a direction from the semiconductor substrate to the wiring forming layer is an upward direction, the connecting wiring portion being formed on a chip inner end face that faces the upper portion of the semiconductor substrate at an end face of the through via; a first path connecting the first buffer circuit and the through via; and a second path connecting the second buffer circuit and the through via. The first path and the second path are electrically connected through the connecting wiring portion. 1. A semiconductor device comprising:a through via formed to penetrate a semiconductor substrate;a first buffer circuit and a second buffer circuit;a wiring forming layer formed in an upper layer of the semiconductor substrate;a connecting wiring portion formed in an upper portion of the through via, wherein a direction from the semiconductor substrate to the wiring forming layer is an upward direction, the connecting wiring portion being formed on a chip inner end face that faces the upper portion of the semiconductor substrate at an end face of the through via;a first path connecting the first buffer circuit and the through via; anda second path connecting the second buffer circuit and the through via,wherein the first path and the second path are electrically connected via the connecting wiring portion andone of the first and second buffer circuits causes a current to flow to the other buffer circuit through the connecting wiring portion.2. The semiconductor device according to claim 1 , wherein the connecting wiring portion is a wiring region formed with an area equal to or smaller than an area of the chip inner end face of the through via. ...

SEMICONDUCTOR DEVICES HAVING HYBRID STACKING STRUCTURES AND METHODS OF FABRICATING THE SAME

A semiconductor device having a chip stack and an interconnection terminal is provided. The chip stack includes a first semiconductor chip, a second semiconductor chip and a third semiconductor chip stacked on each other. The interconnection terminal is electrically coupled to the chip stack. The first semiconductor chip includes a first front surface and a first backside surface. The second semiconductor chip includes a second front surface, a second backside surface, a second circuit layer and a through-electrode which is electrically coupled to the second circuit layer and penetrates the second semiconductor chip. The third semiconductor chip includes a third front surface, a third backside surface opposite to the third front surface and a third circuit layer adjacent to the third front surface. The first front surface and the second front surface face each other. The third front surface and the second backside surface face each other. 1 wherein the first semiconductor chip includes a first front surface, a first backside surface opposite to the first front surface and a first circuit layer adjacent to the first front surface, and', 'the second semiconductor chip includes a second front surface, a second backside surface opposite to the second front surface, a second circuit layer adjacent to the second front surface and a through-electrode which is electrically coupled to the second circuit layer and spaced apart from the second backside surface, and', 'wherein the first front surface and the second front surface face each other;, 'stacking a first semiconductor chip and a second semiconductor chip,'}grinding the second backside surface to expose the through-electrode of the second semiconductor chip;grinding the first backside surface to reduce the first semiconductor chip to a first reduced thickness; wherein the third semiconductor chip includes a third front surface, a third backside surface opposite to the third front surface and a third circuit layer ...

SYSTEM AND METHOD FOR CALIBRATING CHIPS IN A 3D CHIP STACK ARCHITECTURE

A system and method is disclosed for adaptively adjusting a duty cycle of a signal between a first and second chip in a 3D architecture/stack for adaptively calibrating a chip in a 3D architecture/stack. In one embodiment, the system includes a first chip and a second chip located within the 3D chip stack, wherein the first chip generates a calibration signal, the second chip receives the calibration signal and compares it to a reference signal to generate a comparison signal that further compared to a reference duty signal to generate a reference duty comparison signal, that is then provided to the first chip to generate a drive signal that adjusts a duty cycle of the calibration signal. 1. A system for calibrating a chip in a 3D chip stack , the system comprising:a first chip and a second chip located within the 3D chip stack; a first driver circuit for generating a first calibration signal; and', 'a driver control circuit for generating a first drive signal for controlling operation of the first driver circuit;, 'the first chip comprising a first comparator circuit having a first input for receiving the first calibration signal, a second input for receiving a first reference signal, and an output for outputting a first comparison signal;', 'a duty generator counter circuit for generating a first reference duty signal; and', 'a second comparator circuit having a first input for receiving the first comparison signal or signal representative of the first comparison signal, a second input for receiving the first reference duty signal or a signal representative of the first reference duty signal, and an output for outputting a first reference duty comparison signal,, 'the second chip comprisingwherein the driver control circuit receives the first reference duty comparison signal, and generates the drive signal based at least in part on the first reference duty comparison signal, and wherein the drive signal adjusts a duty cycle of a signal communicated between the ...

METHOD AND DEVICE FOR CONTROLLING OPERATION USING TEMPERATURE DEVIATION IN MULTI-CHIP

A multi-chip package includes a first die having temperature sensors and a second die. The first die generates temperature deviation information of m (m Подробнее

CHIP PACKAGE STRUCTURE WITH MOLDING LAYER

A chip package structure is provided. The chip package structure includes a first chip, a second chip, and a third chip. The second chip is between the first chip and the third chip. The chip package structure includes a first molding layer surrounding the first chip. The chip package structure includes a second molding layer surrounding the second chip. The chip package structure includes an insulating layer between the first molding layer and the second molding layer and between the first chip and the second chip. A side wall of the first molding layer, a side wall of the second molding layer, and a side wall of the insulating layer are substantially coplanar. The chip package structure includes a third molding layer surrounding the third chip, the first molding layer, the second molding layer, and the insulating layer. 1. A chip package structure , comprising:a first chip, a second chip, and a third chip, wherein the second chip is between the first chip and the third chip;a first molding layer surrounding the first chip;a second molding layer surrounding the second chip;an insulating layer between the first molding layer and the second molding layer and between the first chip and the second chip, wherein a side wall of the first molding layer, a side wall of the second molding layer, and a side wall of the insulating layer are substantially coplanar; anda third molding layer surrounding the third chip, the first molding layer, the second molding layer, and the insulating layer.2. The chip package structure as claimed in claim 1 , wherein a bottom surface of the first chip claim 1 , a bottom surface of the first molding layer claim 1 , and a bottom surface of the third molding layer are coplanar.3. The chip package structure as claimed in claim 1 , wherein a side wall of the first molding layer and a side wall of the second molding layer are coplanar.4. The chip package structure as claimed in claim 1 , wherein the first insulating layer separates the first ...

METHODS OF FABRICATING SEMICONDUCTOR DIE ASSEMBLIES

Methods of fabricating multi-die assemblies including a base semiconductor die bearing a peripherally encapsulated stack of semiconductor dice of lesser lateral dimensions, the dice vertically connected by conductive elements between the dice, resulting assemblies, and semiconductor devices comprising such assemblies. 1. A method of forming a semiconductor die assembly , comprising:stacking at least one level of semiconductor dice having conductive through vias over unsingulated, laterally separated semiconductor die locations of a wafer;stacking another level of semiconductor dice without conductive through vias over uppermost semiconductor dice of the at least one level;vertically connecting semiconductor dice in each level and an associated unsingulated semiconductor die location with conductive elements;placing a dielectric material between the semiconductor dice of each stack and the associated unsingulated die location;substantially simultaneously covering at least a periphery of each stack of semiconductor dice with encapsulant material between the stacks and onto the wafer; andsingulating the stacks of semiconductor dice through the encapsulant material between the stacks of semiconductor dice and through the wafer.2. The method of claim 1 , wherein stacking at least one level of semiconductor dice comprises stacking more than one level of semiconductor dice.3. The method of claim 1 , wherein stacking another level of semiconductor dice without conductive through vias comprises stacking semiconductor dice with active surfaces facing toward the wafer.4. The method of claim 3 , wherein substantially simultaneously covering at least a periphery of each stack of semiconductor dice on the wafer comprises: placing encapsulant material over and around each stack of semiconductor dice; and removing encapsulant material from over the another level of semiconductor dice.5. The method of claim 4 , further comprising reducing a thickness of the semiconductor dice of the ...

SCAN TESTABLE THROUGH SILICON VIAs

The disclosure describes a novel method and apparatus for testing different types of TSVs in a single die or different types of TSV connections in a stack of die. The testing is facilitated by test circuitry associated with each type of TSV. The test circuitry includes a scan cell adapted for testing TSVs. 1. An integrated circuit comprising:(a) a die having a top surface and a bottom surface;(b) a top contact point on the top surface and a bottom contact point on the bottom surface;(c) a through silicon via in the die having a top end coupled to the top contact point and a bottom end coupled to the bottom contact point;(d) a buffer having an input coupled to one of the top end and the bottom end of the through silicon via and having an output coupled to a contact point;(e) a switch having a first terminal coupled to the buffer input, a second terminal coupled to the buffer output, a third terminal, and a control input; and(f) a scan cell having a reference voltage input, a serial data input, a control input, a stimulus output coupled to the other one of the top end and the bottom end of the through silicon via, a response input coupled to the third terminal, and a serial data output.2. The integrated circuit of in which the buffer input is coupled to the top end of the though silicon via and the buffer output is coupled to the top contact point.3. The integrated circuit of in which the buffer input is coupled to the bottom end of the though silicon via and the buffer output is coupled to the bottom contact point.4. The integrated circuit of including a switch and a load resistor coupled in series between the third terminal and ground claim 1 , and the switch includes a control input.5. The integrated circuit of in which the scan cell includes a multiplexer and a flip-flop connected in series between the serial data input and the serial data output.6. The integrated circuit of in which the scan cell includes a multiplexer and a flip-flop connected in series between ...

FAN-OUT PACKAGE STRUCTURE AND METHOD OF MANUFACTURING THE SAME

A package structure and a method of manufacturing the same are provided. The package structure includes a die, a redistribution layer (RDL) structure, a through integrated fan-out via (TIV) and a conductive terminal. The RDL structure is disposed on and electrically connected to the die. The TIV is laterally aside the die and extends to contact a bottom surface and a sidewall of a redistribution layer of the RDL structure. The conductive terminal is electrically connected to the die through the RDL structure and the TIV. 1. A package structure , comprising:a die;a redistribution layer (RDL) structure disposed on and electrically connected to the die;a through integrated fan-out via (TIV) laterally aside the die and extending to contact a bottom surface and a sidewall of a redistribution layer of the RDL structure; anda conductive terminal, electrically connected to the die through the RDL structure and the TIV.2. The package structure of claim 1 , wherein the RDL structure further comprises a dielectric layer claim 1 , and the redistribution layer is embedded in the dielectric layer claim 1 , a portion of the dielectric layer is vertically sandwiched between the redistribution layer and the TIV.3. The package structure of claim 2 , wherein a bottom corner of the dielectric layer is covered by the TIV.4. The package structure of claim 1 , wherein the redistribution layer comprises a first seed layer and a conductive layer claim 1 , and a portion of the conductive layer is separated from the first seed layer.5. The package structure of claim 4 , wherein there is free of seed layer between the conductive terminal and the conductive layer of the redistribution layer.6. The package structure of claim 1 , wherein the TIV comprises a second seed layer and a conductive post claim 1 , the second seed layer and the conductive post are in physical contact with the conductive terminal.7. The package structure of claim 6 , wherein a portion of the second seed layer is laterally ...

SEMICONDUCTOR SYSTEM

A semiconductor system may include first semiconductor device including a first pad, a second pad and a first test input pad, and suitable for storing data inputted in series through the first test input pad and outputting the stored data in parallel through the first pad and the second pad; a second semiconductor device including a third pad, a fourth pad and a second test output pad, and suitable for storing data inputted in parallel through the third pad and the fourth pad, a first through via connecting the first pad and the third pad so that the stored data outputted in parallel through the first pad is inputted in parallel through the third pad; and a second through via connecting the second pad and the fourth pad so that the stored data outputted in parallel through the second pad is inputted in parallel through the fourth pad. 1. A semiconductor system comprising:a first semiconductor device including a first pad, a second pad and a first test input pad, and suitable for storing data inputted in series through the first test input pad and outputting the stored data in parallel through the first pad and the second pad;a second semiconductor device including a third pad, a fourth pad and a second test output pad, and suitable for storing data inputted in parallel through the third pad and the fourth pad;a first through via connecting the first pad and the third pad; anda second through via connecting the second pad and the fourth pad.2. The semiconductor system according to claim 1 , wherein the second semiconductor device outputs in series the stored data through the second test output pad.3. The semiconductor system according to claim 2 , wherein the data inputted to the first semiconductor device through the first test input pad and the data outputted from the second semiconductor device through the second test output pad are compared.4. The semiconductor system according to claim 1 , wherein the first semiconductor device further comprises:a first test ...

METHOD FOR ESTIMATING THE DIFFUSION LENGTH OF METALLIC SPECIES WITHIN A THREE-DIMENSIONAL INTEGRATED STRUCTURE, AND CORRESPONDING THREE-DIMENSIONAL INTEGRATED STRUCTURE

A three-dimensional integrated structure may include two assembled integrated circuits respectively including two metallic lines, and at least two cavities passing through one of the integrated circuits and opening onto two locations respectively in electrical contact with the two metallic lines. The cavities may be sized to place a measuring apparatus at the bottom of the cavities, and in electrical contact with the two locations. 110-. (canceled)11. An integrated structure comprising:a pair of integrated circuits (ICs) having upper faces joined together with each IC including a respective one of a pair of metallic lines, a first IC of said pair of ICs having a plurality of cavities passing therethrough and opening onto respective electrical contact locations in electrical contact with said pair of metallic lines;the plurality of cavities each having a width greater than 80 microns.12. The integrated structure according to claim 11 , wherein the plurality of cavities each have a height greater than 5 microns.13. The integrated structure according to claim 11 , wherein the plurality of cavities each have a height less than 15 microns.14. The integrated structure according to claim 11 , wherein the first IC has a thickness less than a thickness of the second IC.15. The integrated structure according to claim 11 , wherein the plurality of cavities each has a plurality of walls extending from a bottom; and further comprising a conductive layer at the bottom and on said plurality of walls.16. The integrated structure according to claim 11 , wherein said pair of ICs comprises a pair of assembled ICs.17. An integrated structure comprising:a pair of integrated circuits (ICs) having upper faces joined together with each IC including a respective one of a pair of conductive lines, a first IC of said pair of ICs having a plurality of cavities passing therethrough and opening onto respective electrical contact locations in electrical contact with said pair of conductive lines; ...

ELECTRONIC SYSTEM HAVING INCREASED COUPLING BY USING HORIZONTAL AND VERTICAL COMMUNICATION CHANNELS

An electronic system supports superior coupling by implementing a communication mechanism that provides at least for horizontal communication for example, on the basis of wired and/or wireless communication channels, in the system. Hence, by enhancing vertical and horizontal communication capabilities in the electronic system, a reduced overall size may be achieved, while nevertheless reducing complexity in printed circuit boards coupled to the electronic system. In this manner, overall manufacturing costs and reliability of complex electronic systems may be enhanced. 1. An apparatus , comprising:a first integrated circuit die singulated from a wafer and comprising a first semiconductor substrate and a first metallization structure mounted to the first semiconductor substrate, wherein the first metallization structure includes a first contact pad;a second integrated circuit die singulated from a wafer and comprising a second semiconductor substrate and a second metallization structure mounted to the second semiconductor substrate, wherein the second metallization structure includes a second contact pad;a first dielectric layer disposed in contact with the first metallization structure and a side surface of the first semiconductor substrate, said first dielectric layer including a first communication pad that is electrically connected to said first contact pad;a second dielectric layer disposed in contact with the second metallization structure and a side surface of the second semiconductor substrate, said second dielectric layer including a second communication pad that is electrically connected to said second contact pad;wherein the first dielectric layer is positioned in physical contact with the second dielectric layer, andwherein the first communication pad is positioned for direct mechanical and electrical connection with the second communication pad.2. The apparatus of claim 1 , wherein the first communication pad is disposed on a face of the first dielectric ...

Chip-on-Wafer Process Control Monitoring for Chip-on-Wafer-on-Substrate Packages

An embodiment method includes providing a standardized testing structure design for a chip-on-wafer (CoW) structure, wherein the standardized testing structure design comprises placing a testing structure in a pre-selected area a top die in the CoW structure, and electrically testing a plurality of microbumps in the CoW structure by applying a universal testing probe card to the testing structure. 1. A method for testing a package structure comprising: first testing structures on a first substrate; and', 'first functional circuitry on the first substrate and independent from the first testing structures; and, 'electrically testing a first plurality of conductive connectors in a first package, wherein the first plurality of conductive connectors bonds a first package component to a second package component, and wherein the first package component comprises second testing structures on a second substrate and having a same circuit layout as the first testing structures, wherein a first electrical signal sent through the first testing structures during electrically testing the first plurality of conductive connectors is a same signal as a second electrical signal sent through the second testing structures during electrically testing the second plurality of conductive connectors; and', 'second functional circuitry on the second substrate and independent from the second testing structures, wherein the second functional circuitry has a different circuit layout as the first functional circuitry., 'electrically testing a second plurality of conductive connectors in a second package, wherein the second plurality of conductive connectors bonds a third package component to a fourth package component, and wherein the third package component comprises2. The method of claim 1 , wherein the second package component comprises a first probing pad electrically connected to the first testing structures claim 1 , wherein electrically testing the first plurality of conductive connectors ...

Vertical system integration

The Vertical System Integration (VSI) invention herein is a method for integration of disparate electronic, optical and MEMS technologies into a single integrated circuit die or component and wherein the individual device layers used in the VSI fabrication processes are preferably previously fabricated components intended for generic multiple application use and not necessarily limited in its use to a specific application. The VSI method of integration lowers the cost difference between lower volume custom electronic products and high volume generic use electronic products by eliminating or reducing circuit design, layout, tooling and fabrication costs.

Vertical system integration

The Vertical System Integration (VSI) invention herein is a method for integration of disparate electronic, optical and MEMS technologies into a single integrated circuit die or component and wherein the individual device layers used in the VSI fabrication processes are preferably previously fabricated components intended for generic multiple application use and not necessarily limited in its use to a specific application. The VSI method of integration lowers the cost difference between lower volume custom electronic products and high volume generic use electronic products by eliminating or reducing circuit design, layout, tooling and fabrication costs. 120.-. (canceled)21. A method of making a stacked integrated circuit , comprising:stacking a plurality of closely-coupled integrated circuit layers in relation to one another; andinterconnecting at least two of the plurality of closely-coupled integrated circuit layers using a plurality of vertical interconnections in a standardized placement, wherein the plurality of closely-coupled integrated circuit layers comprise at least a logic layer and a memory layer that have a same standardized placement interconnection pattern as corresponding logic layer and memory layer integrated circuit layers of at least one different stacked integrated circuit having a different design than said stacked integrated circuit;wherein a unique integrated circuit layer is present in only one of the stack of integrated circuits and the different stacked integrated circuit, and wherein the unique integrated circuit layer, the stacked integrated circuit and the different stacked integrated circuit share a same standardized placement interconnection pattern.22. The method of claim 21 , wherein claim 21 , in said stacking step claim 21 , the closely-coupled integrated circuit layers comprise first stacked integrated circuit layers that are instances of a set of designs of different mutually interchangeable stacked integrated circuit layers ...

INTERPOSER, METHOD OF MANUFACTURING INTERPOSER, AND METHOD OF MANUFACTURING SEMICONDUCTOR PACKAGE

An interposer includes a substrate having a mounting area and a test area, first conductive plugs separate from each other, the first conductive plugs being disposed along a first direction and into the test area of the substrate, a first line pattern group including first non-conductive patterns disposed on first centers of the first conductive plugs, and first conductive patterns disposed to bridge first peripheries of a first adjacent pair of the first conductive plugs, and first pads connected to the first conductive patterns at both first ends of the first line pattern group. 1. An interposer comprising:a substrate having a mounting area and a test area;first conductive plugs separate from each other, the first conductive plugs being disposed along a first direction and into the test area of the substrate;a first line pattern group comprising first non-conductive patterns disposed on first centers of the first conductive plugs, and first conductive patterns disposed to bridge first peripheries of a first adjacent pair of the first conductive plugs; andfirst pads connected to the first conductive patterns at both first ends of the first line pattern group.2. The interposer of claim 1 , wherein the first non-conductive patterns and the first conductive patterns are alternately and repeatedly disposed along the first direction claim 1 , andwherein the first conductive patterns and the first conductive plugs are alternately and repeatedly disposed along the first direction.3. The interposer of claim 1 , wherein a length of each of the first non-conductive patterns in the first direction is less than a diameter of each of the first conductive plugs.4. The interposer of claim 1 , wherein the first conductive plugs are separate from each other by a distance claim 1 , andwherein a length of each of the first conductive patterns in the first direction is greater than the distance and is less than a sum of the distance and a diameter of each of the first conductive plugs ...

Die stack structure and method of fabricating the same

Provided is a die stack structure including a first die, a second die, a first bonding structure, and a second bonding structure. The first bonding structure is disposed on a back side of the first die. The second bonding structure is disposed on a front side of the second die. The first die and the second die are bonded together via the first bonding structure and the second bonding structure and a bondable topography variation of a surface of the first bonding structure bonding with the second bonding structure is less than less than 1 μm per 1 mm range. A method of manufacturing the die stack structure is also provided.

Die stack structure and method of fabricating the same and package

Provided is a die stack structure including a first die and a second die. The first die and the second die are bonded together through a hybrid bonding structure. At least one of a first test pad of the first die or a second test pad of the second die has a protrusion of the at least one of the first test pad or the second test pad, and a bonding insulating layer of the hybrid bonding structure covers and contacts with the protrusion, so that the first test pad and the second test pad are electrically isolated from each other.

METHOD OF MANUFACTURING SEMICONDUCTOR PACKAGE STRUCTURE

A method of manufacturing a semiconductor package structure includes the following steps. A die is bonded to a wafer. A dielectric material layer is formed on the wafer and the die. The dielectric material layer covers a top surface and sidewalls of the die. At least one planarization process is performed to remove a portion of the dielectric material layer and a portion of the die, such that the top surface of the die is exposed and a dielectric layer aside the die is formed. The dielectric layer surrounds and covers the sidewalls of the die. 1. A method of manufacturing a semiconductor package structure , comprising:bonding a die to a wafer;forming a dielectric material layer on the wafer and the die, wherein the dielectric material layer covers a top surface and sidewalls of the die; andperforming at least one planarization process to remove a portion of the dielectric material layer and a portion of the die, such that the top surface of the die is exposed and a dielectric layer aside the die is formed,wherein the dielectric layer surrounds and covers the sidewalls of the die.2. The method of claim 1 , wherein the die and the wafer are configured as face to face.3. The method of claim 1 , wherein the die and the wafer are bonded by a hybrid bonding claim 1 , a fusion bonding claim 1 , a combination thereof or connected by a plurality of connectors.4. The method of claim 1 , wherein the dielectric material layer is formed of a molding compound claim 1 , a molding underfill claim 1 , a resin claim 1 , or a combination thereof by a molding process claim 1 , a molding underfilling (MUF) process claim 1 , or a combination thereof.5. The method of claim 1 , wherein the dielectric material layer is formed of an inorganic material claim 1 , an organic material claim 1 , or a combination thereof by a deposition process.6. The method of claim 1 , whereinthe at least one planarization process comprises a first planarization process and a second planarization process;the ...

Semiconductor substrate evaluating method, semiconductor substrate for evaluation, and semiconductor device

On an EP substrate 1 , an EP layer 2 having a conductivity type different from that of the EP substrate 1 is grown. With ion implantation, a well 5 having the same conductivity type as the EP layer 2 is formed, and a channel stop layer 10 is also formed. A dopant having a conductivity type different from that of the well 5 is diffused in the well 5 to form a pn junction 7 in the well 5 . A plurality of cells 20 each having the diffusion layer 6 as one electrode and a rear surface 1 a as the other electrode are formed as a TEG. Using the TEG, junction leakage currents from two depletion layers, a depletion layer 8 in the well and a depletion layer 4 at an interface between the EP layer 2 and the EP substrate 1 , are measured.

PACKAGED INTEGRATED CIRCUIT DEVICE WITH CANTILEVER STRUCTURE

Techniques and mechanisms to facilitate connection with one or more integrated circuit (IC) dies of a packaged device. In an embodiment, the packaged device includes a first substrate coupled to a first side of a package, and a second substrate coupled to a second side of the package opposite the first side. Circuitry, coupled via the first substrate to one or more IC dies disposed in the package, includes a circuit structure disposed at a cantilever portion of the first substrate. The cantilever portion extends past one or both of an edge of the first side and an edge of the second side. In another embodiment, a hardware interface disposed on the second substrate enables coupling of the packaged device to another device. 1. A method comprising:forming a first package, including disposing a package material around one or more integrated circuit (IC) dies, wherein the first package includes a first side, a second side, and a sidewall structure extending between a first edge of the first side and a second edge of the second side;disposing a first substrate on the first side, wherein one of the first side and the second side is offset from a line extending from a first cantilever portion of the first substrate in a direction perpendicular to the first sidecoupling the one or more IC dies via the first substrate to circuitry disposed on the first substrate, the first circuitry including a circuit structure disposed on the first cantilever portion; anddisposing a second substrate on the second side.2. The method of claim 1 , wherein only one of the first side and the second side is offset from the line.3. The method of claim 1 , wherein the circuit structure is an interface contact.4. The method of claim 1 , wherein coupling the one or more IC dies to the circuitry includes disposing the circuit structure on a side of the first cantilever portion that faces toward the second substrate.5. The method of claim 1 , wherein the first substrate forms a second cantilever ...

Semiconductor Device and Method of Manufacture

A semiconductor device and method that utilize a surface device are provided. In an embodiment a fuse line comprises an underbump metallization which has two separate, electrically isolated parts. The two parts are bridged by an external connector, such as a solder ball in order to electrically connect the surface device. When, after testing, the surface device is determined to be defective, the fuse line may be disconnected by removing the external connector from the two separate parts, electrically isolating the surface device. In another embodiment the surface is located beneath a package within an integrated fan out package or is part of a multi-fan out package. 1. A method of manufacturing a semiconductor device , the method comprising:applying a first external connector to a first underbump metallization over a substrate:applying a second external connector to a first terminal underbump metallization, wherein the second external connector electrically bridges a first section of the first terminal underbump metallization and a second section of the first terminal underbump metallization that were electrically isolated prior to the applying the second external connector;removing the second external connector without removing the first external connector; andbonding an external device to the first external connector after the removing the second external connector, wherein the bonding is performed while the first section and the second section are electrically isolated from each other.2. The method of claim 1 , further comprising bonding a surface device in electrical connection with the second section of the terminal underbump metallization claim 1 , prior to the removing the second external connector.3. The method of claim 2 , further comprising testing the surface device after the bonding the surface device and before the removing the second external connector claim 2 , wherein the removing the second external connector is performed when the surface device ...

Microelectronic package with stacked microelectronic units and method for manufacture thereof

A microelectronic package may include a first microelectronic unit including a semiconductor chip having first chip contacts, an encapsulant contacting an edge of the semiconductor chip, and first unit contacts exposed at a surface of the encapsulant and electrically connected with the first chip contacts. The package may include a second microelectronic unit including a semiconductor chip having second chip contacts at a surface thereof, and an encapsulant contacting an edge of the chip of the second unit and having a surface extending away from the edge. The surfaces of the chip and the encapsulant of the second unit define a face of the second unit. Package terminals at the face may be electrically connected with the first unit contacts through bond wires electrically connected with the first unit contacts, and the second chip contacts through metallized vias and traces formed in contact with the second chip contacts.

INTERCONNECT RETIMER ENHANCEMENTS

A test mode signal is generated to include a test pattern and an error reporting sequence. The test mode signal is sent on link that includes one or more extension devices and two or more sublinks. The test mode signal is to be sent on a particular one of the sublinks and is to be used by a receiving device to identify errors on the particular sublink. The error reporting sequence is to be encoded with error information to describe error status of sublinks in the plurality of sublinks. 133.-. (canceled)34. An apparatus comprising: a first pseudo port to connect to a first segment of a link, wherein the link is to connect a first endpoint device to a second endpoint device, and the retimer is to be positioned between the first and second endpoint devices on the link, wherein the first pseudo port is to receive an instance of a SKP ordered set (OS) sent on the first segment of the link, the SKP OS comprises a plurality of fields to identify data integrity on the link, and a particular one of the plurality of fields is to identify data integrity associated with the retimer;', determine whether an error is present in a data sequence sent on the first segment of the link; and', 'set a value in the particular field of the SKP OS, wherein the value is for use by one of the first or second endpoint devices to determine data integrity of the link, and the value is set to generate a modified instance of the SKP OS; and, 'protocol circuitry to, 'a second pseudo port to connect to a second segment of the link and send the modified instance of the SKP OS on the second segment of the link., 'a retimer comprising35. The apparatus of claim 34 , wherein the link is compatible with a Peripheral Component Interconnect Express (PCIe)-based protocol.36. The apparatus of claim 35 , wherein the SKP OS has a format defined by the PCIe-based protocol.37. The apparatus of claim 34 , wherein determining the error comprises detecting a difference in the data sequence from an expected version ...

ELECTRICAL OVERLAY MEASUREMENT METHODS AND STRUCTURES FOR WAFER-TO-WAFER BONDING

Alignment of a first wafer bonded to a second wafer can be determined using electrical wafer alignment methods. A wafer stack can be formed by overlaying a second wafer over a first wafer such that second metal bonding pads of the second wafer contact first metal bonding pads of the first wafer. A leakage current or a capacitance measurement step is performed between first alignment diagnostic structures in the first wafer and second alignment diagnostic structures in the second wafer for multiple mating pairs of first semiconductor dies in the first wafer and second semiconductor dies in the second wafer to determine the alignment. 1. A method of bonding a first wafer and a second wafer , comprising:providing a first wafer including a first two-dimensional array of first semiconductor dies, wherein each of the first semiconductor dies comprises a respective set of first metal bonding pads and a respective set of first alignment diagnostic structures located at a same level as the first metal bonding pads;providing a second wafer including a second two-dimensional array of second semiconductor dies, wherein each of the second semiconductor dies comprises a respective set of second metal bonding pads and a respective set of second alignment diagnostic structures located at a same level as the second metal bonding pads;forming a wafer stack by overlaying the second wafer over the first wafer such that the second metal bonding pads contact the first metal bonding pads and the first alignment diagnostic structures and the second alignment diagnostic structures are offset from each other;measuring at least one of a leakage current or a capacitance between the first alignment diagnostic structures and the second alignment diagnostic structures for multiple mating pairs of the first semiconductor dies and the second semiconductor dies; andbonding the second wafer to the first wafer.2. The method of claim 1 , wherein the step of bonding the second wafer to the first wafer ...

Electrical overlay measurement methods and structures for wafer-to-wafer bonding

A method includes providing a first wafer including a respective set of first metal bonding pads and at least one first alignment diagnostic structure, providing a second wafer including a respective set of second metal bonding pads and a respective set of second alignment diagnostic structures, overlaying the first wafer and the second wafer, measuring at least one of a current, voltage or contact resistance between the first alignment diagnostic structures and the second alignment diagnostic structures to determine an overlay offset, and bonding the second wafer to the first wafer.

WAFER SCALE TESTING AND INITIALIZATION OF SMALL DIE CHIPS

A chip intermediate body includes a semiconductor region including plural chip areas. The chip areas respectively are cut out as semiconductor chips. A cut region is provided along edges of the chip areas, the cut region being cut to cut out the semiconductor chips. A contact region is provided opposite to the chip areas across the cut region, the contact region being configured to be contacted by a probe of a test unit to test the chip areas, and electric wiring is provided continuously with the cut region to connect the chip areas and the contact region. 1. A chip intermediate body , comprising:a super-die separated from a wafer, the super-die including a plurality of small-dies, the small-dies respectively being cut out as semiconductor chips;a cut region provided along edges of the small-dies, the cut region being cut to separate the semiconductor chips;a contact region provided opposite to the chip areas across the cut region, the contact region being configured to be contacted on a plurality of test pads by a probe of a test unit to test the small-dies; andelectric wiring provided continuously with the cut region to connect the small-dies of the super-die and the contact region.2. The chip intermediate body of claim 1 , wherein each of the small-dies includes bumps on a surface of the small-dies.3. The chip intermediate body of claim 2 , whereinthe test pads are configured to be contacted by respective contact points of the probe of the test unit, andeach of the test pads has a larger area than each of the bumps.4. The chip intermediate body of claim 1 , wherein the cut region includes other electric wiring that at least interconnects the small-dies and connects the small-dies and the contact region.5. The chip intermediate body of claim 4 , wherein the other electric wiring is electrically connected with the electric wiring.6. The chip intermediate body of claim 4 , wherein each of the small-dies includes circuit wiring claim 4 , andthe other electric wiring ...

PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF

A package structure includes an insulating encapsulation, at least one first chip, a redistribution layer and a bonding layer. The at least one first chip is encapsulated in the insulating encapsulation. The redistribution layer is located on the insulating encapsulation and the at least one first chip and electrically connected to the at least one first chip. The bonding layer mechanically connects the redistribution layer and the at least one first chip. 1. A package structure , comprising:an insulating encapsulation;at least one first chip, encapsulated in the insulating encapsulation;a redistribution layer, located on the insulating encapsulation and the at least one first chip and electrically connected to the at least one first chip; anda bonding layer, having two opposite sides physically connected to the redistribution layer and the at least one first chip, respectively.2. The package structure of claim 1 , further comprising a metal layer comprising a first portion and a second portion physically separated from the first portion claim 1 , wherein the first portion of the metal layer surrounds the at least one first chip claim 1 , and the at least one first chip is separated from the insulating encapsulation by the first portion of the metal layer.3. The package structure of claim 2 , wherein the at least one first chip comprises contact pads and a protection layer partially covering the contact pads claim 2 , wherein a surface of the protection layer is substantially levelled with and coplanar to a surface of the first portion of the metal layer.4. The package structure of claim 2 , wherein the second portion of the metal layer partially covers a surface of the bonding layer and penetrates through the bonding layer.5. The package structure of claim 4 , further comprising a plurality of vias encapsulated in the insulating encapsulation claim 4 , wherein the plurality of vias penetrate through the insulating encapsulation and the bonding layer claim 4 , and ...

Semiconductor Device and Method of Manufacture

A semiconductor device including a test pad contact and a method of manufacturing the semiconductor device are disclosed. In an embodiment, a semiconductor device may include a first metal feature and a second metal feature disposed in a single top metal layer over a substrate. A test pad may be formed over and electrically connected to the first metal feature. A first passivation layer may be formed over the second metal feature and the test pad and may cover top and side surfaces of the test pad. A first via may be formed penetrating the first passivation layer and contacting the test pad and a second via may be formed penetrating the first passivation layer and contacting the second metal feature. 1. A semiconductor device comprising:a first conductive feature and a second conductive feature over a semiconductor substrate, the first conductive feature and the second conductive feature comprising copper, wherein a top surface of the first conductive feature is level with a top surface of the second conductive feature;a third conductive feature over and electrically coupled to the first conductive feature, the third conductive feature comprising aluminum;a bond layer over the third conductive feature and the second conductive feature;a first bond pad extending through the bond layer and electrically coupled to the third conductive feature; anda second bond pad extending through the bond layer and electrically coupled to the second conductive feature, wherein a top surface of the second bond pad is level with a top surface of the first bond pad and a top surface of the bond layer, and wherein the first bond pad has a first height less than a second height of the second bond pad.2. The semiconductor device of claim 1 , wherein a bottom surface of the first bond pad is disposed below a top surface of the third conductive feature.3. The semiconductor device of claim 1 , further comprising a via electrically coupled the third conductive feature to the first conductive ...

MEMORY WITH TSV HEALTH MONITOR CIRCUITRY

Memory devices and systems with TSV health monitor circuitry, and associated methods, are disclosed herein. In one embodiment, a memory device includes a plurality of memory dies, a plurality of through-silicon vias (TSVs) in electrical communication with the memory dies; and circuitry. In some embodiments, the circuitry is configured to electrically couple a pair of TSVs of the plurality of TSVs to form a passive circuit. For example, the circuitry can activate a transistor electrically positioned between TSVs of the pair of TSVs to electrically couple the pair of TSVs. In these and other embodiments, the circuitry applies a test voltage to the pair of TSVs using the passive circuit to determine whether a TSV of the pair of TSVs includes degradation. 1. A memory device , comprising:a plurality of memory dies;a plurality of through-silicon vias (TSVs), each TSV in electrical communication with each of the plurality of memory dies; and electrically couple a pair of TSVs of the plurality of TSVs to form a passive circuit, and', 'apply a test voltage to the passive circuit formed between each pair of coupled TSVs., 'circuitry configured to2. The memory device of claim 1 , wherein the circuitry includes at least one transistor configured to couple the pair of TSVs.3. The memory device of claim 2 , wherein the at least one transistor includes a first transistor in a first memory die of the plurality of memory dies and a second transistor in a second memory die of the plurality of memory dies.4. The memory device of claim 1 , wherein the circuitry includes bypass transistors claim 1 , and wherein each bypass transistor is electrically connected directly to a respective TSV of the pair of TSVs such that the passive circuit bypasses input buffers electrically coupled to the plurality of TSVs.5. The memory device of claim 1 , wherein claim 1 , using the test voltage claim 1 , the circuitry is further configured to measure a current flow across the passive circuit.6. The ...

Self-test capable integrated circuit apparatus and method of self-testing an integrated circuit

A self-test capable integrated circuit apparatus includes a pattern generator, a results store and testable logic. The testable logic includes a plurality of scan channels, each of the channels being respectively coupled between the pattern generator and the results store. A self-test controller is arranged to supervise a self-test in respect of the testable logic to generate self-test result data, the self-test result data being stored in the results store. A processing resource is coupled to the self-test controller and coupled between the pattern generator and the results store, the processing resource being capable of evaluating the self-test result data stored in the results store. The testable logic includes the processing resource, arranged to cooperate with the self-test controller. The processing resource is able, subsequent to the self-test, to evaluate the self-test result data.

SEMICONDUCTOR DEVICES HAVING STACKED STRUCTURES AND METHODS FOR FABRICATING THE SAME

Semiconductor devices having stacked structures and methods for fabricating the same are provided. A semiconductor device includes at least one single block including a first semiconductor chip and a second semiconductor chip stacked thereon. Each of the first and second semiconductor chips includes a semiconductor substrate including a through-electrode, a circuit layer on a front surface of the semiconductor substrate, and a front pad that is provided in the circuit layer and is electrically connected to the through-electrode. The surfaces of the semiconductor substrates face each other. The circuit layers directly contact each other such that the semiconductor chips are bonded to each other. 1. A semiconductor device comprising:at least one single block including a first semiconductor chip and a second semiconductor chip stacked thereon, a first semiconductor substrate including a first through-electrode;', 'a first circuit layer on a front surface of the first semiconductor substrate; and', 'a first front pad in the first circuit layer and is electrically connected to the first through-electrode,, 'wherein the first semiconductor chip comprises a second semiconductor substrate including a second through-electrode;', 'a second circuit layer on a front surface of the second semiconductor substrate; and', 'a second front pad in the second circuit layer and is electrically connected to the second through-electrode,, 'wherein the second semiconductor chip compriseswherein the front surface of the first semiconductor substrate faces the front surface of the second semiconductor substrate, andwherein the first circuit layer directly contacts the second circuit layer such that the first semiconductor chip is bonded to the second semiconductor chip.2. The device of claim 1 , whereinthe first semiconductor chip further comprises at least one first test pad that is electrically connected to the first through-electrode and is configured to electrically test the first ...

SEMICONDUCTOR DEVICE AND SEMICONDUCTOR INTEGRATED SYSTEM

A semiconductor device is provided where it is possible to access and test a memory chip by a simple method. 1. A semiconductor device that mounts a plurality of chips in a common package , the semiconductor device comprising:a logic chip having a predetermined function; anda memory chip that is coupled with the logic chip and stores data,wherein the memory chip includesa memory chip testing circuit that performs an operation test of the memory chip, anda serial bus interface circuit for transmitting and receiving data between the memory chip testing circuit and a serial bus provided outside the package.2. The semiconductor device according to claim 1 ,wherein the memory chip includes a plurality of stacked type memory dies which are electrically coupled together by a through electrode, andwherein the memory chip testing circuit and the serial bus interface circuit are provided to at least one of the memory dies.3. The semiconductor device according to claim 1 ,wherein the memory chip includesa base die provided at a lowest layer, anda plurality of stacked type memory dies which are provided above the base die and electrically coupled together by a through electrode, andwherein the memory chip testing circuit and the serial bus interface circuit are provided to the memory die.4. The semiconductor device according to claim 3 , wherein the base die further includes a bump that is used for external coupling.5. The semiconductor device according to claim 1 , wherein the logic chip and the memory chip are coupled through a silicon interposer.6. The semiconductor device according to claim 1 ,wherein the serial bus interface circuit includesa clock buffer for a clock signal, anda data buffer for a data signal.7. A semiconductor integrated system comprising:a system board;an entire control unit that is provided over the system board and controls the entire system board;a plurality of semiconductor devices provided over the system board; anda serial bus that couples the ...

Semiconductor Device and Method of Manufacture

A semiconductor device including a test pad contact and a method of manufacturing the semiconductor device are disclosed. In an embodiment, a semiconductor device may include a first metal feature and a second metal feature disposed in a single top metal layer over a substrate. A test pad may be formed over and electrically connected to the first metal feature. A first passivation layer may be formed over the second metal feature and the test pad and may cover top and side surfaces of the test pad. A first via may be formed penetrating the first passivation layer and contacting the test pad and a second via may be formed penetrating the first passivation layer and contacting the second metal feature. 1. A semiconductor device comprising:a first conductive feature and a second conductive feature over a semiconductor substrate, wherein a top surface of the first conductive feature is level with a top surface of the second conductive feature;a test pad over and electrically connected to the first conductive feature;a bond layer over the test pad and the second conductive feature;a first bond pad extending through the bond layer and electrically connected to the test pad; anda second bond pad extending through the bond layer and electrically connected to the second conductive feature.2. The semiconductor device of claim 1 , further comprising a passivation layer between the bond layer and both the first conductive feature and the second conductive feature claim 1 , wherein the second bond pad extends through the passivation layer.3. The semiconductor device of claim 2 , further comprising a via extending through the passivation layer and electrically connecting the test pad to the first conductive feature.4. The semiconductor device of claim 1 , wherein the first conductive feature and the second conductive feature comprise a first conductive material claim 1 , and wherein the test pad comprises a second conductive material different from the first conductive material.5 ...

Semiconductor Device Assembly with Pillar Array

A semiconductor device assembly and method of forming a semiconductor device assembly that includes a first substrate, a second substrate disposed over the first substrate, at least one interconnect between the substrates, and at least one pillar extending from the bottom surface of the first substrate. The pillar is electrically connected to the interconnect and is located adjacent to a side of the first substrate. The pillar is formed by filling a via through the substrate with a conductive material. The first substrate may include an array of pillars extending from the bottom surface adjacent to a side of the substrate that are formed from a plurality of filled vias. The substrate may include a test pad located on the bottom surface or located on the top surface. The pillars may include a removable coating enabling the pillars to be probed without damaging the inner conductive portion of the pillar. 1. A semiconductor device assembly comprising:a first substrate having a top surface and a bottom surface opposite the top surface;a second substrate having a top surface and a bottom surface opposite the top surface, the second substrate being disposed over the first substrate;an interconnect between the first sub state and the second substrate that electrically connects the first substrate with the second substrate;an array of pillars of conductive material that extend from the bottom surface of the first substrate, the array of pillars being positioned adjacent to a first side of the first substrate and wherein a portion of the array of pillars is positioned within the first substrate;at least one pad on the top surface of the substrate, the at least one pad being positioned adjacent to the first side of the first substrate;a plurality of interconnections within the first substrate, the plurality of interconnections electrically connecting the array of pillars with the interconnect between the first substrate and the second substrate, the at least one pad with the ...

INTEGRATED CIRCUIT DEVICE COMPRISING ENVIRONMENT-HARDENED DIE AND LESS-ENVIRONMENT-HARDENED DIE

An integrated circuit device has at least one environment-hardened die and at least one less-environment-hardened die. Environment-hardened circuitry on the environment-hardened die is more resistant to the degradation when exposed to a predetermined environmental condition than the less-environment-hardened circuitry on the environment-hardened die. The dice are combined using a 3D or 2.5D integrated circuit technology. This is very useful for testing circuits at adverse environmental conditions (e.g. high temperature), or for providing circuits to operate at such conditions. 2. The integrated circuit device according to claim 1 , wherein the integrated circuit device comprises a 3D integrated circuit comprising said plurality of vertically stacked dice.3. The integrated circuit device according to claim 1 , wherein the integrated circuit device comprises a 2.5D integrated circuit comprising the at least one environment-hardened die and the at least one less-environment-hardened die mounted on said interposer.4. The integrated circuit device according to claim 1 , wherein the less-environment-hardened circuitry comprises a test subject circuit and the environment-hardened circuitry comprises a testing circuit to perform testing of the test subject circuit.5. The integrated circuit device according to claim 4 , wherein the testing comprises reliability testing for testing degradation of the test subject circuit when exposed to said at least one predetermined environmental condition.6. The integrated circuit device according to claim 5 , wherein the reliability testing is for testing degradation of the test subject circuit due to at least one of:electromigration;time dependent dielectric breakdown;bias temperature instability;hot carrier injection;electrical stress; andambient radiation.7. The integrated circuit device according to claim 4 , wherein the test subject circuit comprises a plurality of devices under test (DUTs) claim 4 , and the testing circuit comprises ...

INTEGRATED CIRCUIT PACKAGE STRUCTURE AND TESTING METHOD USING THE SAME

An integrated circuit package structure includes a device die having a plurality of metal pillars, a molding material directly in contact with at least one side surface of the device die, a first dielectric layer disposed on the device die and on the molding material, and a testing pad disposed in the first dielectric layer and directly in contact with an interface between the device die and the molding material. The testing pad is electrical isolated from the metal pillars. 1. An integrated circuit package structure , comprising:a device die comprising a plurality of metal pillars;a molding material directly in contact with at least one side surface of the device die;a first dielectric layer disposed on the device die and on the molding material; anda testing pad disposed in the first dielectric layer and directly in contact with an interface between the device die and the molding material, wherein the testing pad is electrical isolated from the metal pillars.2. The integrated circuit package structure of claim 1 , further comprising:at least one second dielectric layer disposed on the testing pad and on the first dielectric layer; andtwo vias disposed in the second dielectric layer, wherein the vias are connected to two opposite ends of the testing pad, respectively.3. The integrated circuit package structure of claim 1 , further comprising:a plurality of redistribution lines disposed above the first dielectric layer, wherein the redistribution lines are respectively connected to the metal pillars of the device die, and the redistribution lines and the interface are spaced by the first dielectric layer.4. The integrated circuit package structure of claim 3 , further comprising:at least one second dielectric layer disposed on the first dielectric layer, wherein the redistribution lines are disposed in the second dielectric layer and are electrical isolated from the testing pad.5. The integrated circuit package structure of claim 4 , further comprising:a plurality ...

MULTI-CHIP PACKAGE CAPABLE OF TESTING INTERNAL SIGNAL LINES

A multi-chip package capable of testing internal signal lines including a printed circuit board, a first semiconductor chip mounted on the printed circuit board and including a test circuit, and second semiconductor chips mounted on the printed circuit board and electrically connected to the first semiconductor chip via a plurality of internal signal lines may be provided. The test circuit may be configured to enable circuits of the first semiconductor chip connected to pads contacting the plurality of internal signal lines, transmit complementary data to at least two pads from among the pads, and form a current path in the circuits connected to the at least two pads, thereby detecting a short-circuit between the internal bonding wires. 1. A multi-chip package comprising:a printed circuit board;a first semiconductor chip on the printed circuit board, the first semiconductor chip including a test circuit; andsecond semiconductor chips on the printed circuit board, the second semiconductor chips electrically connected to the first semiconductor chip via a plurality of internal signal lines,wherein the test circuit is configured to enable circuits of the first semiconductor chip connected to pads contacting the plurality of internal signal lines, transmit complementary data to at least two pads from among the pads, and form a current path in the circuits connected to the at least two pads.2. The multi-chip package of claim 1 , whereinthe plurality of internal signal lines comprise bonding wires, andthe pads contacting the plurality of internal signal lines comprise bonding pads.3. The multi-chip package of claim 1 , wherein the circuits connected to the at least two pads comprise output drivers configured to transmit data to the second semiconductor chips via the plurality of internal signal lines.4. The multi-chip package of claim 3 , wherein the test circuit comprises:a path selection circuit configured to enable the output drivers; anda pattern generator configured ...

Stacked dram device and method of manufacture

A memory device includes a first dynamic random access memory (DRAM) integrated circuit (IC) chip including first memory core circuitry, and first input/output (I/O) circuitry. A second DRAM IC chip is stacked vertically with the first DRAM IC chip. The second DRAM IC chip includes second memory core circuitry, and second I/O circuitry. Solely one of the first DRAM IC chip or the second DRAM IC chip includes a conductive path that electrically couples at least one of the first memory core circuitry or the second memory core circuitry to solely one of the first I/O circuitry or the second I/O circuitry, respectively.

HIGH BANDWIDTH MEMORIES AND SYSTEMS INCLUDING THE SAME

High bandwidth memories and systems including the same may include a buffer die, a plurality of memory dies stacked on the buffer die, a plurality of dummy bump groups in edge regions of the buffer die and the plurality of memory dies, and a plurality of signal line groups. Each of the plurality of dummy bump groups includes dummy bumps spaced apart from each other between each pair of adjacent dies and configured to connect the two adjacent dies to each other. Each of the signal line groups includes a plurality of signal lines configured to transmit a corresponding signal among an input signal and a plurality of bump crack detection signals applied to an input dummy bump of each of the plurality of dummy bump groups via sequential transmission through the plurality of dummy bumps to an output dummy bump during a bump crack test operation. 1. A high bandwidth memory comprising:a buffer die;a plurality of memory dies stacked on the buffer die;a plurality of dummy bump groups in edge regions of the buffer die and the plurality of memory dies, wherein each of the plurality of dummy bump groups comprises the plurality of dummy bumps spaced apart from each other between each pair of adjacent dies and configured to connect the two adjacent dies to each other; anda plurality of signal line groups, each comprising a plurality of signal lines configured to transmit a corresponding signal among an input signal and a plurality of bump crack detection signals, applied to an input dummy bump of the plurality of dummy bumps of each of the plurality of dummy bump groups, to an output dummy bump of the plurality of dummy bumps via sequential transmission through the plurality of dummy bumps during a bump crack test operation,wherein a scan input signal applied to a first terminal of the buffer die is generated as the input signal, signals output through the output dummy bumps of the plurality of dummy bump groups are generated as the plurality of bump crack detection signals, and ...