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Небесная энциклопедия

Космические корабли и станции, автоматические КА и методы их проектирования, бортовые комплексы управления, системы и средства жизнеобеспечения, особенности технологии производства ракетно-космических систем

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Мониторинг СМИ

Мониторинг СМИ и социальных сетей. Сканирование интернета, новостных сайтов, специализированных контентных площадок на базе мессенджеров. Гибкие настройки фильтров и первоначальных источников.

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Поддерживает ввод нескольких поисковых фраз (по одной на строку). При поиске обеспечивает поддержку морфологии русского и английского языка
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Применить Всего найдено 5503. Отображено 100.
12-01-2012 дата публикации

Resin-Encapsulated Semiconductor Device

Номер: US20120007247A1
Автор: Motoharu Haga, Shoji Yasunaga, Yasumasa Kasuya
Принадлежит: ROHM CO LTD

A resin-sealed semiconductor device includes a semiconductor chip including a silicon substrate; a die pad on which the semiconductor chip is secured via a solder layer; a sealing resin layer sealing the semiconductor chip; and lead terminals connected electrically with the semiconductor chip. One end portion of the lead terminals is covered by the sealing resin layer. The die pad and the lead terminals are formed of copper and a copper alloy, and the die pad is formed with a thickness larger than a thickness of the lead terminals, which is a thickness of 0.25 mm or more.

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Номер записи: 1
09-02-2012 дата публикации

Semiconductor device, electronic apparatus, and method of manufacturing semiconductor device

Номер: US20120032298A1
Автор: Hideki Fujii, Kenji Furuya, Yuichi Miyagawa
Принадлежит: Renesas Electronics Corp

A semiconductor chip is mounted on a first surface of an interconnect substrate, and has a multilayer interconnect layer. A first inductor is formed over the multilayer interconnect layer, and a wiring axis direction thereof is directed in a horizontal direction to the interconnect substrate. A second inductor is formed on the multilayer interconnect layer, and a wiring axis direction thereof is directed in the horizontal direction to the interconnect substrate. The second inductor is opposite to the first inductor. A sealing resin seals at least the first surface of the interconnect substrate and the semiconductor chip. A groove is formed over the whole area of a portion that is positioned between the at least first inductor and the second inductor of a boundary surface of the multilayer interconnect layer and the sealing resin.

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Номер записи: 2
08-03-2012 дата публикации

Method for manufacturing electronic parts device and resin composition for electronic parts encapsulation

Номер: US20120055015A1
Автор: Eiji Toyoda, Shigetomi KIDO
Принадлежит: Nitto Denko Corp

The present invention relates to a method for manufacturing an electronic parts device allowing for easy overmolding and underfilling without requiring a jig for preventing leakage of the melted resin composition, and a resin composition sheet for electronic parts encapsulation used therein.

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Номер записи: 3
15-03-2012 дата публикации

Manufacturing method of substrate for a semiconductor package, manufacturing method of semiconductor package, substrate for a semiconductor package and semiconductor package

Номер: US20120064666A1
Автор: Shigeru Hosomomi, Yoichiro Hamada
Принадлежит: SUMITOMO METAL MINING CO LTD

A manufacturing method of a substrate for a semiconductor package includes a resist layer forming step to form a resist layer on a surface of a conductive substrate; an exposure step to expose the resist layer using a glass mask with a mask pattern including a transmission area, a light shielding area, and an intermediate transmission area, wherein transmittance of the intermediate transmission area is lower than that of the transmission area and is higher than that of the light shielding area; a development step to form a resist pattern including a hollow with a side shape including a slope part decreasing in hollow circumference as the hollow circumference approaches the substrate; and a plating step to plate on an exposed area to form a metal layer with a side shape including a slope part decreasing in circumference as the circumference approaches the substrate.

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Номер записи: 4
03-05-2012 дата публикации

Semiconductor module

Номер: US20120104631A1
Автор: Nam-Seog Kim, Seung-Duk Baek, Sun-Won Kang, Tae-Gyeong Chung, Young-hee Song
Принадлежит: Individual

A semiconductor module may include a circuit substrate with a first die on the circuit substrate and a second die on the first die. The first die may include at least one first data input/output pad on a first peripheral portion of the first die and at least one first control/address pad on a third peripheral portion, the third peripheral portion being separate from the first peripheral portion of the first die. The second die may include at least one second data input/output pad on a second peripheral portion and at least one second control/address pad on a fourth peripheral portion. The second peripheral portion of the second die is not overlapped with the first peripheral portion of the first die in plan view. The fourth peripheral portion of the second die overlaps at least a portion of the third peripheral portion of the first die.

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Номер записи: 5
03-05-2012 дата публикации

Method for manufacturing semiconductor device

Номер: US20120108013A1
Автор: Atsushi Fujisawa, Hiroshi Fujii
Принадлежит: Renesas Electronics Corp

In QFN packages for vehicles which are required to have high reliability, the side surface of leads is mostly covered with lead-to-lead resin protrusions, which prevent smooth formation of solder fillets during reflow mounting. When the lead-to-lead protrusions are mechanically removed using a punching die, there is a high possibility of causing cracks of the main body of the package or terminal deformation. When a spacing is provided between the punching die and the main body of the package in order to avoid such damages, a resin residue is produced to hinder complete removal of this lead-to-lead resin protrusion. The present invention provides a method for manufacturing semiconductor device of a QFN type package using multiple leadframes having a dam bar for tying external end portions of a plurality of leads. This method includes a step of removing a sealing resin filled between the circumference of a mold cavity and the dam bar by using laser and then carrying out surface treatment, for example, solder plating.

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Номер записи: 6
17-05-2012 дата публикации

Microelectronic devices and methods for manufacturing microelectronic devices

Номер: US20120119344A1
Автор: Teck Kheng Lee
Принадлежит: Micron Technology Inc

Microelectronic devices and methods for manufacturing microelectronic devices are disclosed herein. One such method includes forming a plurality of apertures in a substrate with the apertures arranged in an array, and, after forming the apertures, attaching the substrate to a lead frame having a plurality of pads with the apertures in the substrate aligned with corresponding pads in the lead frame. Another method includes providing a partially cured substrate, coupling the partially cured substrate to a plurality of leads, attaching a microelectronic die to the leads, and electrically connecting the microelectronic die to the leads.

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Номер записи: 7
05-07-2012 дата публикации

Semiconductor package and method of fabricating the same

Номер: US20120168919A1
Автор: Joo-yang Eom, Joon-Seo Son
Принадлежит: Individual

A semiconductor package and a method of manufacturing the same, and more particularly, to a package of a power module semiconductor and a method of manufacturing the same. The semiconductor package includes a substrate including a plurality of conductive patterns spaced apart from one another; a plurality of semiconductor chips disposed on the conductive patterns; a connecting member for electrically connecting the conductive patterns to each other, for electrically connecting the semiconductor chips to each other, or for electrically connecting the conductive pattern and the semiconductor chip; and a sealing member for covering the substrate, the semiconductor chips, and the connecting member, wherein a lower surface of the substrate and an upper surface of the connecting member are exposed to the outside by the sealing member.

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Номер записи: 8
18-10-2012 дата публикации

Integrated circuit package system with removable backing element having plated terminal leads and method of manufacture thereof

Номер: US20120261808A1
Автор: Dioscoro A. Merilo, Henry Descalzo Bathan, Lionel Chien Hui Tay, Zigmund Ramirez Camacho
Принадлежит: Individual

A method of manufacture of an integrated circuit package system includes: attaching a first die to a first die pad; connecting electrically a second die to the first die through a die interconnect positioned between the first die and the second die; connecting a first lead adjacent the first die pad to the first die; connecting a second lead to the second die, the second lead opposing the first lead and adjacent the second die; and providing a molding material around the first die, the second die, the die interconnect, the first lead and the second lead, with a portion of the first lead exposed.

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Номер записи: 9
27-12-2012 дата публикации

Semiconductor device package and method of manufacturing thereof

Номер: US20120329207A1
Автор: Arun Virupaksha Gowda, Paul Alan McConnelee, Richard Alfred Beaupre, Thomas Bert Gorczyca
Принадлежит: General Electric Co

A semiconductor device package includes a semiconductor device having connection pads formed thereon, with the connection pads being formed on first and second surfaces of the semiconductor device with edges of the semiconductor device extending therebetween. A first passivation layer is applied on the semiconductor device and a base dielectric laminate is affixed to the first surface of the semiconductor device that has a thickness greater than that of the first passivation layer. A second passivation layer having a thickness greater than that of the first passivation layer is applied over the first passivation layer and the semiconductor device to cover the second surface and the edges of the semiconductor device, and metal interconnects are coupled to the connection pads, with the metal interconnects extending through vias formed through the first and second passivation layers and the base dielectric laminate sheet to form a connection with the connection pads.

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Номер записи: 10
10-01-2013 дата публикации

Conductive chip disposed on lead semiconductor package and methods of making the same

Номер: US20130009309A1
Автор: David Chong, Jatinder Kumar
Принадлежит: Individual

In one implementation, an apparatus includes a semiconductor die, a lead, a non-conductive epoxy, and a conductive epoxy. The semiconductor die includes an upper surface and a lower surface opposite the upper surface. The lead is electrically coupled to the upper surface of the semiconductor die. The non-conductive epoxy is disposed on a first portion of the lower surface of the semiconductor die. The conductive epoxy is disposed on a second portion of the lower surface of the semiconductor die. In some implementations, a conductive wire extends from the lead to the upper surface of the semiconductor die to electrically couple the lead to the upper surface of the semiconductor die.

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Номер записи: 11
28-02-2013 дата публикации

Semiconductor Device and Method of Manufacturing a Semiconductor Device Including Grinding Steps

Номер: US20130049205A1
Автор: David O'Sullivan, Klaus Reingruber, Thorsten Meyer
Принадлежит: Intel Mobile Communications GmbH

A method of manufacturing a device includes providing a semiconductor chip having a first face and a second face opposite to the first face with a contact pad arranged on the first face. The semiconductor chip is placed on a carrier with the first face facing the carrier. The semiconductor chip is encapsulated with an encapsulation material. The carrier is removed and the semiconductor material is removed from the second face of the first semiconductor chip without removing encapsulation material at the same time.

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Номер записи: 12
07-03-2013 дата публикации

Die package including encapsulated die and method of manufacturing the same

Номер: US20130056141A1
Автор: Hong Won Kim, Jingli Yuan, Joon Seok Kang, Young Do Kweon
Принадлежит: Samsung Electro Mechanics Co Ltd

Disclosed herein is a die package including an encapsulated die, including: a die including pads on one side thereof; an encapsulation layer covering lateral sides of the die; a support layer covering the encapsulation layer and one side of the die; a passivation layer formed on the other side of the die such that the pads are exposed therethrough; and a redistribution layer formed on the passivation layer such that one part thereof is connected with the pad. Here, since one side of the die is supported by the support layer and the encapsulation layer is formed on only the lateral side of the die, the warpage of the die package due to the difference in thermal expansion coefficient can be minimized

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Номер записи: 13
04-04-2013 дата публикации

RESIN SEALING METHOD OF SEMICONDUCTOR DEVICE

Номер: US20130082378A1
Автор: CHINO Teruaki
Принадлежит: SHINKO ELECTRIC INDUSTRIES CO., LTD.

A resin sealing method of a semiconductor device includes: positioning semiconductor devices at predetermined positions of an adhesive layer formed on a support body and adhering the semiconductor devices thereto, sealing a part of each of the semiconductor devices with resin by curing a first seal resin in a fluidization state so as to fix the semiconductor devices adhered to the predetermined positions of the adhesive layer formed on the support body, setting the semiconductor devices fixed to the predetermined positions of the adhesive layer formed on the support body in a mold and sealing the exposure parts of the semiconductor devices exposed from the first seal resin with a second seal resin, and removing the support body and the adhesive layer from the semiconductor devices sealed with the resin. 1. A semiconductor package , comprising:a multilayer wiring structure comprising a plurality of wiring layers and a plurality of insulating layers, the multilayer wiring structure comprising a first surface and a second surface opposite to the first surface;an external connection terminal on the first surface of the multilayer wiring structure;a semiconductor device on the second surface of the multilayer wiring structure and comprising an electrode thereon, wherein the electrode is electrically connected to the multilayer wiring structure;a first sealing resin on the second surface of the multilayer wiring structure and partially covering the semiconductor device; anda second sealing resin on the first sealing resin and partially covering the semiconductor device, wherein a physical property of the first sealing resin is different from that of the second sealing resin,wherein the semiconductor device is embedded in the first and second sealing resins.2. The semiconductor package of claim 1 , wherein a thickness of the first sealing resin is equal to or smaller than a half of a thickness of the semiconductor device.3. The semiconductor package of claim 1 , wherein a ...

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Номер записи: 14
18-04-2013 дата публикации

OPTICAL MODULE WITH A LENS ENCAPSULATED WITHIN SEALANT AND METHOD FOR MANUFACTURING THE SAME

Номер: US20130093071A1
Автор: Koguchi Keitaro, Mii Kazuaki, Sano Tomomi, Takagi Toshio, Tanaka Kazunori
Принадлежит: Sumitomo Electric Industries, Ltd.

A method to manufacture an optical module is disclosed, wherein the optical module has an optically active device on a lead frame and a lens co-molded with the active device and the lead frame by a transparent resin as positioning the lens with respect to the lead frame. The molding die of the present invention has a positioning pin to support the lens during the molding. Because the lead frame is aligned with the molding die, the precise alignment between the active device on the lead frame and the lens is not spoiled during the molding. 1. An optical module , comprising:a semiconductor optical device;a lead frame for mounting said semiconductor optical device;a lens optically coupled with said semiconductor optical device; anda sealant for enclosing said semiconductor optical device, said lens and a portion of said lead frame, said sealant being transparent for light characterizing said semiconductor optical device,wherein said sealant has at least a via penetrating from a surface of said sealant to said lens.2. The optical module of claim 1 ,wherein said lead frame has a cut to set said lens therein.3. The optical module of claim 1 ,wherein said via has a cross section of a truncated cone.4. The optical module of claim 1 ,wherein said via has a cross section of a trapezoid.5. The optical module of claim 1 ,wherein said via is filled with a metal.6. The optical module of claim 1 ,wherein said sealant has an optically active outer surface in a portion crossing an axis connecting said semiconductor optical device to said lens.7. The optical module of claim 1 ,wherein said sealant has a pair of vias putting an axis connecting said semiconductor optical device with said lens therebetween.8. The optical module of claim 1 ,wherein said via passes through said sealant to expose said lens in a midway of said via.9. A method to manufacture an optical module claim 1 , comprising steps of:setting a lead frame on a molding die, wherein said read frame mounts a semiconductor ...

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Номер записи: 15
18-04-2013 дата публикации

SEALING FILM AND A SEMICONDUCTOR DEVICE USING THE SAME

Номер: US20130093105A1
Автор: IMAI Takuya, Kawakami Hiroyuki, NIIJIMA Katsuyasu, TAKEMORI Daichi, TOMORI Naoki
Принадлежит:

A method for sealing electrodes on a semiconductor device using a sealing film which includes a resin layer having a flow within the range of 150 to 1800 μm at 80° C., or having a resin layer with a viscosity within the range of 10,000 to 100,000 Pa·s in a B-stage state at 50 to 100° C. in thermosetting viscoelasticity measurement, and containing: (A) both (a1) a high-molecular-weight component including crosslinking functional groups and having a weight-average molecular weight of 100,000 or more and a Tg within the range of −50 to 50° C. and (a2) a thermosetting component including an epoxy resin as a main component, (B) a filler having an average particle size within the range of 1 to 30 μm, and (C) a colorant. 1. A method for sealing electrodes on a semiconductor using a sealing film , comprising the steps of:providing a sealing film which comprises a resin layer containing the following (A), (B) and (C) and having a flow within the range of 150 to 1800 μm at 80° C.:(A) a resin component containing (a1) a high-molecular-weight component comprising crosslinking functional groups and having a weight-average molecular weight of 100,000 or more and a Tg within the range of −50 to 50° C. and (a2) a thermosetting component comprising an epoxy resin as a main component,(B) a filler having an average particle size within the range of 1 to 30 μm, and(C) a colorant, andwherein the sealing film contains 1 to 300 parts by mass of the filler (B) and 0.01 to 10 parts by mass of the colorant (C), based on 10 parts by mass of the resin component (A) containing 5 to 85% by mass of the high-molecular-weight component (a1) and 15 to 95% by mass of the thermosetting component (a2);laminating the sealing film by a lamination roll to contact the resin layer with an electrode surface of the semiconductor substrate; andsealing the electrodes on the semiconductor substrate.2. A method for sealing electrodes on a semiconductor using a sealing film , comprising the steps of:providing a ...

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Номер записи: 16
25-04-2013 дата публикации

Semiconductor Device and Method of Forming Interposer Frame Electrically Connected to Embedded Semiconductor Die

Номер: US20130099378A1
Автор: HanGil Shin, HeeJo Chi, NamJu Cho
Принадлежит: Stats Chippac Pte Ltd

A semiconductor device has an interposer frame mounted over a carrier. A semiconductor die has an active surface and bumps formed over the active surface. The semiconductor die can be mounted within a die opening of the interposer frame or over the interposer frame. Stacked semiconductor die can also be mounted within the die opening of the interposer frame or over the interposer frame. Bond wires or bumps are formed between the semiconductor die and interposer frame. An encapsulant is deposited over the interposer frame and semiconductor die. An interconnect structure is formed over the encapsulant and bumps of the first semiconductor die. An electronic component, such as a discrete passive device, semiconductor die, or stacked semiconductor die, is mounted over the semiconductor die and interposer frame. The electronic component has an I/O count less than an I/O count of the semiconductor die.

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Номер записи: 17
02-05-2013 дата публикации

Semiconductor package including semiconductor chip with through opening

Номер: US20130105988A1
Автор: Chang-Cheol Lee, Hyun-Jun Kim, In-Young Lee, Ki-Kwon Jeong
Принадлежит: SAMSUNG ELECTRONICS CO LTD

A semiconductor package comprises a substrate having a first opening formed therethrough, a first semiconductor chip stacked on the substrate in a flip chip manner and having a second opening formed therethrough, a second semiconductor chip stacked on the first semiconductor chip in a flip chip manner and having a third opening formed therethrough, and a molding material covering the first semiconductor chip and the second semiconductor chip and filling up a space between the substrate and the first semiconductor chip, a space between the first semiconductor chip and the second semiconductor chip, and filling each of the first opening, the second opening, and the third opening.

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Номер записи: 18
09-05-2013 дата публикации

RESIN COMPOSITION, RESIN FILM, SEMICONDUCTOR DEVICE, AND PRODUCTION METHOD THEREOF

Номер: US20130113083A1
Автор: Kondo Kazunori, SUGO Michihiro
Принадлежит: SHIN-ETSU CHEMICAL CO., LTD.

A resin composition which can be formed into a film for use in molding a large diameter thin film wafer is provided. The composition comprises components (A) a silicone resin containing repeating units represented by the following formulae (1-1), (1-2), and (1-3) and having a weight average molecular weight as measured by GPC in terms of polystyrene of 3,000 to 500,000, 4. A resin composition according to wherein the amount of the component (B) is 5 to 100 parts by weight in relation to 100 parts by weight of the component (A) claim 1 , and the weight ratio of the component (C) in relation to the entire weight is 30 to 85% by weight.5. A resin composition according to wherein the thermosetting resin is an epoxy resin.6. A resin composition according to further comprising at least one member selected from epoxy resin curing agents and epoxy resin curing accelerators.7. A resin composition according to wherein the filler is a silica.8. A resin film prepared by using the resin composition of .9. A method for producing a semiconductor device comprising the steps of attaching the resin composition or the resin film of to a semiconductor wafer to mold the semiconductor wafer claim 1 , and singulating the molded semiconductor wafer.10. A semiconductor device having a heat cured film claim 1 , which is produced by singulating a semiconductor wafer molded with a heat cured film prepared by heat curing the resin composition or the resin film of . This non-provisional application claims priority under 35 U.S.C. §119 (a) on Patent Application No. 2011-243359 filed in Japan on Nov. 7, 2011, the entire contents of which are hereby incorporated by reference.This invention relates to a resin composition and a resin film. This invention also relates to a semiconductor device produced by using such resin film and its production method.Recently, wafers used in the production of a semiconductor device have increased diameter and reduced thickness, and there is a high demand for a ...

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Номер записи: 19
20-06-2013 дата публикации

Method for Securing a Carrier by Gas Pressurization to Inhibit Warpage of the Carrier

Номер: US20130152363A1
Автор: Chih-Horng Horng
Принадлежит: Individual

This invention relates to a method for securing a carrier by gas pressurization to inhibit warpage of the carrier. The method includes following steps: provide a carrier with an upper surface and a lower surface which are opposite to each other; providing an evacuable jig with an apertured surface on which a plurality of apertures are provided; placing and securing one of the upper and lower surfaces of the carrier on the apertured surface in a manner of facing the apertured surface, wherein the surface of the carrier faced to the apertured surface is defined as a first surface, and the other surface opposed to the first surface is defined as a second surface; and gas pressurizing a chamber and evacuating the jig positioned in the chamber, to form a pressure difference between the first surface and the second surface of the carrier, whereby the carrier is pressed on the jig, wherein the chamber is pressurized to a predetermined pressure greater than a standard atmospheric pressure.

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Номер записи: 20
20-06-2013 дата публикации

ENCAPSULATED FLEXIBLE ELECTRONIC DEVICE, AND CORRESPONDING MANUFACTURING METHOD

Номер: US20130153030A1
Автор: Accardi Corrado, LOVERSO Stella, RAVESI SEBASTIANO, SPARTA NOEMI GRAZIANA
Принадлежит: STMICROELECTRONICS S.R.L.

The disclosure relates to an encapsulated flexible electronic device comprising a flexible electronic device, wherein the flexible electronic device is protected by a protective coating layer, a first cover sheet and a second cover sheet being made of patterned and developed dry photoresist films. The encapsulated flexible electronic device may be used to directly realize different type of electronic devices, such as smart sensor devices. 1. An encapsulated flexible electronic device comprising:a flexible electronic device; anda protective coating layer, a first cover sheet, and a second cover sheet on the flexible electronic, each of the protective coating layer, first cover sheet, and second cover sheet being a patterned and developed dry photoresist film.2. An encapsulated flexible electronic device according to claim 1 , wherein each of the protective coating layer claim 1 , first cover sheet claim 1 , and second cover sheet is a negative claim 1 , transparent claim 1 , and permanent solvent dry photoresist film.3. An encapsulated flexible electronic device according to claim 1 , wherein said protective coating layer claim 1 , said first cover sheet and said second cover sheet have a modulable thickness.4. An encapsulated flexible electronic device according to claim 1 , wherein said flexible electronic device is a flexible photovoltaic cell.5. An encapsulated flexible electronic device according to claim 1 , wherein said flexible electronic device is a touch screen.6. An encapsulated flexible electronic device according to claim 1 , wherein said first and second cover sheets are respectively back and front sheets of said flexible electronic device and are configured to fully protect the flexible electronic device from mechanical stress.7. A method for manufacturing an encapsulated flexible electronic device claim 1 , the method comprising:providing a flexible electronic device;forming a protective coating layer, a first cover sheet, and a second cover sheet on ...

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Номер записи: 21
20-06-2013 дата публикации

DRIVING SUBSTRATE, DISPLAY DEVICE, PLANARIZING METHOD, AND METHOD OF MANUFACTURING DRIVING SUBSTRATE

Номер: US20130154063A1
Автор: Akamatsu Keiichi, Kato Yuichi, Masuda Kenta
Принадлежит: SONY CORPORATION

A driving substrate includes: a protective layer including an etching surface; and a film layer including one or more convex portions on a surface thereof, the film layer being in contact with a rear surface of the protective layer, the one or more convex portions each having a surface being flush with the etching surface. 1. A driving substrate comprising:a protective layer including an etching surface; anda film layer including one or more convex portions on a surface thereof, the film layer being in contact with a rear surface of the protective layer, the one or more convex portions each having a surface being flush with the etching surface.2. The driving substrate according to claim 1 , wherein the protective layer is buried between the one or more convex portions of the film layer.3. The driving substrate according to claim 1 , wherein the film layer and the protective layer have substantially same etching resistance.4. The driving substrate according to claim 1 , wherein a material configuring the protective layer and a material configuring the film layer have a same skeleton.5. The driving substrate according to claim 1 , wherein the protective layer is made of a resist.6. The driving substrate according to claim 1 , further comprising a thin film transistor as a driving circuit on the etching surface.7. A display device with a driving substrate and a display layer claim 1 , the driving substrate comprising:a protective layer including an etching surface; anda film layer including one or more convex portions on a surface thereof, the film layer being in contact with a rear surface of the protective layer, the one or more convex portions each having a surface being flush with the etching surface.8. A planarizing method comprising:forming a substrate by providing a protective layer on a film layer, the protective layer and the film layer having substantially same etching resistance, and the film layer including one or more convex portions on a surface thereof; ...

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Номер записи: 22
04-07-2013 дата публикации

MODULE PACKAGE AND PRODUCTION METHOD

Номер: US20130168876A1
Автор: Bart Rudolf, Rehme Frank, Reitlinger Claus
Принадлежит: EPCOS AG

The invention relates to a module package which comprises a module substrate , a chip applied using the flip chip process, and an encapsulation layer , and to a method for producing same. The chip has component structures on the top side thereof. Said top said faces the module carrier , wherein a gap is formed between the top side of the chip and the module carrier . A filler is added to the encapsulation layer . The encapsulation layer partly fills underneath the chip , wherein at most the part of the chip , on which no component structures are present, is underfilled, and at a minimum the material of the encapsulation layer completely encloses the sides of the chip 1. A module package comprising;a module substrate;at least one chip which has component structures on its top side and the top side of which faces the module carrier, wherein a gap is formed between the chip top side and the module carrier; andan encapsulation layer, with which a filler is admixed and which partly underfills the chip, wherein as a maximum the part of the chip on which no component structures are situated is underfilled, and as a minimum the encapsulation layer terminates virtually flush with the side areas of the chip.2. The module package according to claim 1 , wherein the filler forms at least 75 percent by mass of the encapsulation layer.3. The module package according to or claim 1 , wherein the filler has a particle size distribution in which at least one third of the filler particles have a diameter greater than the height of the gap between the chip top side and the module carrier.4. The module package according to claim 1 , wherein the filler comprises silicon oxide.5. The module package according to claim 1 , wherein the filler particles have angular outer surfaces.6. The module package according to claim 1 , wherein the module carrier or chip has a supporting structure that narrows the gap between the chip and the module carrier.7. The module package according to claim 1 , ...

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Номер записи: 23
11-07-2013 дата публикации

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE

Номер: US20130175703A1
Автор: ASAKURA Daisuke, Furukawa Motoyuki, Murai Hiroaki, Namiki Kazushige, Naruse Mikio, Takaragi Shinichi
Принадлежит:

A semiconductor device includes an electric conduction portion having a flat plate shape, a semiconductor element being arranged vertically over the electric conduction portion and being electrically connected thereto, a casing whose lower portion of an inner wall has a coupling portion coupled with a circumferential edge portion of the electric conduction portion and whose upper portion of the inner wall surrounds the whole circumference of the electric conduction portion and a sealing material that vertically downwardly encapsulates the semiconductor element and the electric conduction portion. The electric conduction portion and the casing are integrally molded, and a space having a shape coupled to a circumferential edge portion of the electric conduction portion is provided in the lower portion of the inner wall of the casing as the coupling portion. 16-. (canceled)7. A semiconductor device comprising:an electric conduction portion having a flat plate shape, a semiconductor element being arranged vertically over the electric conduction portion and being electrically connected thereto;a casing whose lower portion of an inner wall has a coupling portion coupled with a circumferential edge portion of the electric conduction portion and whose upper portion of the inner wall surrounds the whole circumference of the electric conduction portion; anda sealing material that vertically downwardly encapsulates the semiconductor element and the electric conduction portion,wherein the electric conduction portion and the casing are integrally molded, a space having a shape coupled to a circumferential edge portion of the electric conduction portion is provided in the lower portion of the inner wall of the casing as the coupling portion, and a contraction rate of a material of the casing is higher than that of a material of the electric conduction portion.8. The semiconductor device according to claim 7 , wherein a thickness of the circumferential edge portion of the electric ...

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Номер записи: 24
25-07-2013 дата публикации

SENSOR MODULE, PRODUCTION METHOD OF A SENSOR MODULE, AND INJECTION MOLD FOR ENCAPSULATING A SENSOR MODULE

Номер: US20130187295A1
Автор: Reitmeier Willibald, Wildgen Andreas
Принадлежит: Continental Automotive GmbH

A sensor module an injection mold for covering the sensor module, and to a production method for a covered sensor module including a chip carrier and a sensor chip disposed thereon. A channel is formed between the chip carrier and the sensor chip, by which a medium can be fed to the sensor chip. 113.-. (canceled)14. A sensor module comprising:a chip carrier having a first side and a second side opposite the first side;a sensor chip arranged at least partly on the first side of the chip carrier and is electrically supplied by the chip carrier; anda channel arranged between the sensor chip and the chip carrier by which a medium is fed to the sensor chip.15. The sensor module as claimed in claim 14 , wherein the channel extends from the first side of the chip carrier to the second side of the chip carrier.16. The sensor module as claimed claim 15 , wherein the chip carrier is a printed circuit board.17. The sensor module as claimed claim 14 , wherein the sensor chip has two sensor regions opposite one another claim 14 , wherein one of the sensor regions can be connected to an environment of the sensor module via the channel.18. The sensor module as claimed in claim 14 , further comprising at least a partial covering.19. The sensor module as claimed in claim 18 , wherein the channel extends through the covering.20. An injection mold for covering a chip carrier having a first side and a second side opposite the first side claim 18 , a sensor chip arranged at least partly on the first side of the chip carrier and is electrically supplied by the chip carrier claim 18 , and a channel arranged between the sensor chip and the chip carrier by which a medium is fed to the sensor chip claim 18 , comprising:a first mold half; anda second mold half,wherein at least one of the mold halves has an opening, such that the channel being formed between the chip carrier and the sensor chip is connected to an environment of the injection mold via the opening.21. The injection mold as ...

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Номер записи: 25
08-08-2013 дата публикации

Semiconductor Device and Method of Forming Pre-Molded Substrate to Reduce Warpage During Die Molding

Номер: US20130200527A1
Автор: Kim MinJung, Kim Seungwon, Yang Daewook
Принадлежит: STATS CHIPPAC, LTD.

A semiconductor device has a substrate with a plurality of conductive vias formed through the substrate and conductive layer formed over the substrate. A first encapsulant is deposited over the substrate outside a die attach area of the substrate. The first encapsulant surrounds each die attach area over the substrate and the die attach area is devoid of the first encapsulant. A channel connecting adjacent die attach areas is also devoid of the first encapsulant. A first semiconductor die is mounted over the substrate within the die attach area after forming the first encapsulant. A second semiconductor die is mounted over the first die within the die attach area. An underfill material can be deposited under the first and second die. A second encapsulant is deposited over the first and second die and first encapsulant. The first encapsulant reduces warpage of the substrate during die mounting. 1. A semiconductor device , comprising:a substrate including a first encapsulant disposed over a surface of the substrate outside a die attach area of the substrate, wherein the die attach area is devoid of the first encapsulant;a first semiconductor die disposed over the substrate within the die attach area; anda second encapsulant deposited over the first semiconductor die.2. The semiconductor device of claim 1 , further including an underfill material deposited between the first semiconductor die and substrate.3. The semiconductor device of claim 1 , wherein the second encapsulant extends under the first semiconductor die.4. The semiconductor device of claim 1 , further including a second semiconductor die disposed over the first semiconductor die.5. The semiconductor device of claim 4 , further including a plurality of conductive vias formed through the first semiconductor die and electrically connected to the second semiconductor die.6. The semiconductor device of claim 1 , further including a channel through the first encapsulant connecting adjacent die attach areas.7. A ...

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Номер записи: 26
08-08-2013 дата публикации

Circuit Board, Method for Fabricating the Same and Semiconductor Package Using the Same

Номер: US20130200531A1
Автор: Kim Chul-Woo, Kim Yong-Hoon, KIM Young-bae, Lee Hee-Seok, Myung Bok-Sik, Na Kyung-Tae
Принадлежит: SAMSUNG ELECTRONICS CO., LTD.

A circuit board is provided including a core insulation film having a thickness and including a first surface and an opposite second surface, an upper stack structure and a lower stack structure. The upper stack structure has a thickness and has an upper conductive pattern having a thickness and an overlying upper insulation film stacked on the first surface of the core insulation film. The lower stack structure has a thickness and has a lower conductive pattern having a thickness and an overlying lower insulation film stacked on the second surface of the core insulation film. A ratio P of a sum of the thicknesses of the upper conductive pattern and the lower conductive pattern to a sum of the thicknesses of the core insulation film, the upper stack structure and the lower stack structure is in a range from about 0.05 to about 0.2. 1. A circuit board comprising:a core insulation film having a thickness and including a first surface and an opposite second surface;an upper stack structure having a thickness and having an upper conductive pattern having a thickness and an overlying upper insulation film stacked on the first surface of the core insulation film; anda lower stack structure having a thickness and having a lower conductive pattern having a thickness and an overlying lower insulation film stacked on the second surface of the core insulation film, wherein a ratio P of a sum of the thicknesses of the upper conductive pattern and the lower conductive pattern to a sum of the thicknesses of the core insulation film, the upper stack structure and the lower stack structure is in a range from about 0.05 to about 0.25.2. The circuit board of claim 1 , wherein the upper conductive pattern and the upper insulation film comprise a plurality of layers sequentially and repeatedly stacked on the first surface and the lower conductive pattern and the lower conductive pattern and the lower insulation film comprise a plurality of layers sequentially and repeatedly stacked on ...

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Номер записи: 27
22-08-2013 дата публикации

Semiconductor Device and Method of Forming Bond-on-Lead Interconnection for Mounting Semiconductor Die in FO-WLCSP

Номер: US20130214409A1
Автор: Koo Jun Mo, Pagaila Reza A., Pendse Rajendra D.
Принадлежит: STATS CHIPPAC, LTD.

A semiconductor die has a conductive layer including a plurality of trace lines formed over a carrier. The conductive layer includes a plurality of contact pads electrically continuous with the trace lines. A semiconductor die has a plurality of contact pads and bumps formed over the contact pads. A plurality of conductive pillars can be formed over the contact pads of the semiconductor die. The bumps are formed over the conductive pillars. The semiconductor die is mounted to the conductive layer with the bumps directly bonded to an end portion of the trace lines to provide a fine pitch interconnect. An encapsulant is deposited over the semiconductor die and conductive layer. The conductive layer contains wettable material to reduce die shifting during encapsulation. The carrier is removed. An interconnect structure is formed over the encapsulant and semiconductor die. An insulating layer can be formed over the conductive layer. 1. A semiconductor device , comprising:a conductive layer including a plurality of trace lines;a semiconductor die including a plurality of contact pads disposed over the trace lines;a plurality of bumps bonding the contact pads of the semiconductor die to the trace lines, wherein a width of the bump is greater than a width of trace line;an encapsulant deposited over the semiconductor die; andan interconnect structure formed over the encapsulant and semiconductor die.2. The semiconductor device of claim 1 , wherein the bumps are bonded to an end portion of the trace lines.3. The semiconductor device of claim 1 , wherein the bumps are bonded to an intermediate portion of the trace lines.4. The semiconductor device of claim 1 , further including a plurality of conductive pillars formed over the contact pads of the semiconductor die.5. The semiconductor device of claim 1 , further including an insulating layer formed over the conductive layer.6. The semiconductor device of claim 5 , wherein the insulating layer includes a no-flow underfill ...

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Номер записи: 28
22-08-2013 дата публикации

Epoxy encapsulating and lamination adhesive and method of making same

Номер: US20130214435A1
Автор: Paul Alan McConnelee, Thomas Bert Gorczyca
Принадлежит: General Electric Co

An adhesive includes an epoxy resin and a hardener. The hardener includes trioxdiamine, diaminodicyclohexylmethane, toluene diamine, and bisphenol-A dianhydride.

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Номер записи: 29
29-08-2013 дата публикации

METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE

Номер: US20130221440A1
Автор: MORI Shigeru
Принадлежит:

A semiconductor device in which a semiconductor layer is formed on an insulating substrate with a front-end insulating layer interposed between the semiconductor layer and the insulating substrate is provided which is capable of preventing action of an impurity contained in the insulating substrate on the semiconductor layer and of improving reliability of the semiconductor device. In a TFT (Thin Film Transistor), boron is made to be contained in a region located about 100 nm or less apart from a surface of the insulating substrate so that boron concentration decreases at an average rate being about 1/1000-fold per 1 nm from the surface of the insulating substrate toward the semiconductor layer. 1. A semiconductor device comprising:{'sup': 22', '3', '19', '3, 'a semiconductor layer formed on an insulating substrate with a front-end insulating layer being interposed between said semiconductor layer and said insulating substrate, boron or aluminum being contained as an impurity in said front-end insulating layer, wherein impurity concentration is set to be about 1×10(atom/cm) or less on a surface of said insulating substrate, wherein said impurity concentration in a region of said front-end insulating layer located about 100 nm or more apart from said surface of said insulating substrate is set to be about 10(atom/cm) or less, and wherein said impurity concentration gradually decreases from said surface of said insulating substrate toward said semiconductor layer.'}2. The semiconductor device according to claim 1 , wherein said impurity concentration in a region of said front-end insulating layer located about 100 nm apart from said surface of said insulating substrate is set to be 1/100000-fold or less in reference to that on said surface of said insulating substrate.3. The semiconductor device according to claim 1 , wherein said region of said front-end insulating layer where said impurity concentration gradually decreases from said surface of said insulating ...

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Номер записи: 30
29-08-2013 дата публикации

MOLDING DIE, MICROCHIP MANUFACTURED BY USING MOLDING DIE, AND MANUFACTURING APPARATUS FOR MANUFACTURING MICROCHIP

Номер: US20130221544A1
Автор: Sekihara Kanji
Принадлежит: KONICA MINOLTA, INC.

A molding die for molding a substrate to be included in a microchip includes a first die and a second die contactable with and separable from the first die. A molding space for molding the substrate and a gate for introducing resin into the molding space are formed between the first die and the second die. A molding surface of the first die includes a first-die substrate molding region which molds the one surface of the substrate, a gate-defining region which defines the gate, and a rising region which is located between the gate-defining region and the first-die substrate molding region and extends from an edge of the first-die substrate molding region toward the second die. The gate-defining region is closer to the second die than the first-die substrate molding region. A microchip and a manufacturing apparatus also are provided. 1. A molding die for molding a substrate to be included in a microchip , the molding die comprising:a first die; anda second die contactable with and separable from the first die, the microchip is formed by forming a fluid passage groove on one surface of the substrate and attaching a cover to the one surface,', 'a molding space for molding the substrate and a gate for introducing resin into the molding space are formed between the first die and the second die,, 'wherein'} a first-die substrate molding region which molds the one surface of the substrate;', 'a gate-defining region which defines the gate; and', 'a rising region which is located between the gate-defining region and the first-die substrate molding region and extends from an edge of the first-die substrate molding region toward the second die, and, 'a molding surface of the first die includesthe gate-defining region is closer to the second die than the first-die substrate molding region.2. The molding die of claim 1 , wherein a parting line of the molding space and the first-die substrate molding region are located on a single plane.3. The molding die of claim 1 , whereina ...

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Номер записи: 31
05-09-2013 дата публикации

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

Номер: US20130228907A1
Автор: HOZOUJI Hiroshi, KAJIWARA Ryoichi, MOTOWAKI Sigehisa, NAKAJO Takuya, OKAWA Keiichi, Takahashi Yasushi, Tamura Masaki
Принадлежит: RENESAS ELECTRONICS CORPORATION

Conventional surface roughening plating technology cannot always improve the adhesion between a leadframe and a plating film and it depends on the material used for surface roughening plating. Conventional surface roughening technology by etching can only be used for leadframes made of limited materials. Improved adhesion cannot therefore be achieved between a metal member such as leadframe and a sealing resin. 1. A method of manufacturing a semiconductor device , comprising the steps of:preparing a metal member obtained by partially removing an insulating film from a surface of a base material having an external coupling terminal, selectively plating the surface of the base material with Zn, and heat-treating the Zn-plated base material in a non-oxidizing atmosphere or a reducing atmosphere to conduct an alloying treatment of the Zn and the base material;bonding a semiconductor element to the metal member;electrically coupling an electrode of the semiconductor element to the external coupling terminal of the metal member, andcovering the semiconductor element and the metal member with a sealing resin.2. The method of manufacturing a semiconductor device according to claim 1 , wherein the alloying treatment is achieved by interdiffusion of the Zn and a metal of the base material.3. The method of manufacturing a semiconductor device according to claim 2 , wherein the interdiffusion between the Zn and the metal of the base material is achieved by partial progress of the interdiffusion on the surface of the base material.4. The method of manufacturing a semiconductor device according to claim 2 , wherein the base material has Cu as a main component.5. The method of manufacturing a semiconductor device according to claim 1 , wherein the alloying treatment forms an alloy layer having a markedly irregular surface.6. The method of manufacturing a semiconductor device according to claim 1 , wherein the alloying treatment forms an alloy layer having surface irregularities ...

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Номер записи: 32
12-09-2013 дата публикации

Flip-chip packaging techniques and configurations

Номер: US20130234344A1
Автор: Frank J. Juskey, Paul D. Bantz, Robert C. Hartmann
Принадлежит: Triquint Semiconductor Inc

Embodiments of the present disclosure flip-chip packaging techniques and configurations. An apparatus may include a package substrate having a plurality of pads formed on the package substrate, the plurality of pads being configured to receive a corresponding plurality of interconnect structures formed on a die and a fluxing underfill material disposed on the package substrate, the fluxing underfill material comprising a fluxing agent configured to facilitate formation of solder bonds between individual interconnect structures of the plurality of interconnect structures and individual pads of the plurality of pads and an epoxy material configured to harden during formation of the solder bonds to mechanically strengthen the solder bonds. Other embodiments may also be described and/or claimed.

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Номер записи: 33
26-09-2013 дата публикации

Semiconductor package, semiconductor apparatus and method for manufacturing semiconductor package

Номер: US20130249075A1
Автор: Akihiko Tateiwa, Akio Rokugawa, Masato Tanaka
Принадлежит: Shinko Electric Industries Co Ltd

A semiconductor package includes: a metal plate including a first surface, a second surface and a side surface; a semiconductor chip on the first surface of the metal plate, the semiconductor chip comprising a first surface, a second surface and a side surface; a first insulating layer that covers the second surface of the metal plate; a second insulating layer that covers the first surface of the metal plate, and the first surface and the side surface of the semiconductor chip; and a wiring structure on the second insulating layer and including: a wiring layer electrically connected to the semiconductor chip; and an interlayer insulating layer on the wiring layer. A thickness of the metal plate is thinner than that of the semiconductor chip, and the side surface of the metal plate is covered by the first insulating layer or the second insulating layer.

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Номер записи: 34
26-09-2013 дата публикации

Integrated circuit packaging system with terminals and method of manufacture thereof

Номер: US20130249077A1
Автор: Arnel Senosa Trasporto, Byung Tai Do, Linda Pei Ee CHUA
Принадлежит: Stats Chippac Pte Ltd

A method of manufacture of an integrated circuit packaging system includes: providing a leadframe having a mounting platform; applying an attach layer on the mounting platform; mounting an integrated circuit die on the attach layer; forming an encapsulation on the integrated circuit die and the attach layer, the mounting platform exposed from the encapsulation; and forming a terminal having a terminal protrusion from the leadframe, the terminal protrusion below a horizontal plane of the mounting platform.

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Номер записи: 35
03-10-2013 дата публикации

INTEGRATED CIRCUIT PACKAGING SYSTEM WITH ROUTABLE CIRCUITRY AND METHOD OF MANUFACTURE THEREOF

Номер: US20130256861A1
Автор: Chua Linda Pei Ee, Do Byung Tai, Trasporto Arnel Senosa
Принадлежит: STATS CHIPPAC LTD.

An integrated circuit packaging system, and a method of manufacture therefor, including: electrical terminals; circuitry protective material around the electrical terminals and formed to have recessed pad volumes; routable circuitry on the top surface of the circuitry protective material; and an integrated circuit die electrically connected to the electrical terminals. 1. A method of manufacture of an integrated circuit packaging system comprising:providing a lead frame;forming routable circuitry on the top surface of the lead frame;attaching an integrated circuit die over the lead frame;processing the bottom surface of the lead frame for forming electrical terminals; andplacing circuitry protective material around the electrical terminals for forming recessed pad volumes in the circuitry protective material.2. The method as claimed in wherein processing the bottom surface of the lead frame includes:providing a bottom pattern on the bottom surface of the lead frame for forming the electrical terminals,removing a portion of the lead frame using the bottom pattern for forming the electrical terminals, andremoving the bottom pattern.3. The method as claimed in further comprising forming fusible material in the circuitry protective material in the recessed pad volumes and extending out from the circuitry protective material.4. The method as claimed in further comprising forming top pads over the electrical terminals and connected to the routable circuitry.5. The method as claimed in further comprising wire or fusible interconnects electrically connecting the die to the electrical terminals.6. The method as claimed in further comprising forming solder wettable material on the bottom surfaces of the electrical terminals.7. The method as claimed in further comprising forming electrical terminals under die.8. The method as claimed in wherein processing the bottom surface of the lead frame includes processing for forming a die attach paddle.9. The method as claimed in ...

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Номер записи: 36
03-10-2013 дата публикации

Semiconductor module

Номер: US20130256865A1
Автор: Akihiro UMEKI, Yoichi Hiruta
Принадлежит: Individual

In the semiconductor module comprising a package substrate, a first semiconductor package, and a semiconductor bare chip, such problems as the occurrence of a wire short caused by warpage of the first semiconductor package and non-filling and the like at the time of resin sealing can be solved. A semiconductor module 10 , having: a semiconductor package 6 , which is obtained by mounting and resin-sealing a semiconductor bare chip on a first package substrate; a semiconductor bare chip 2 ; and a second package substrate 12 , the semiconductor module being characterized in that the semiconductor package 6 is mounted on the second package substrate 12 and the semiconductor bare chip 2 is mounted on the semiconductor package 6.

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Номер записи: 37
03-10-2013 дата публикации

Semiconductor Device and Method of Forming Reconstituted Wafer With Larger Carrier to Achieve More EWLB Packages Per Wafer with Encapsulant Deposited Under Temperature and Pressure

Номер: US20130256923A1
Автор: Hsiao Yung Kuan, Phua Yoke Hor
Принадлежит:

A semiconductor wafer has a plurality of semiconductor die distributed over a surface area. The semiconductor die are singulated from the semiconductor wafer. The semiconductor die are mounted to a carrier to form a reconstituted semiconductor wafer. The carrier has a surface area 10-50% larger than the surface area of the semiconductor wafer. The number of semiconductor die mounted to the carrier is greater than a number of semiconductor die singulated from the semiconductor wafer. The reconstituted wafer is mounted within a chase mold. The chase mold is closed with the semiconductor die disposed within a cavity of the chase mold. An encapsulant is dispersed around the semiconductor die within the cavity under temperature and pressure. The encapsulant can be injected into the cavity of the chase mold. The reconstituted wafer is removed from the chase mold. An interconnect structure is formed over the reconstituted wafer. 1. A semiconductor device , comprising:a semiconductor wafer;a plurality of semiconductor die singulated from the semiconductor wafer;a carrier including a surface area larger than a surface area of the semiconductor wafer, wherein the semiconductor die are disposed side-by-side over the carrier to form a reconstituted wafer and a number of semiconductor die disposed over the carrier is greater than a total number of semiconductor die singulated from the semiconductor wafer; andan encapsulant deposited over the semiconductor die.2. The semiconductor device of claim 1 , wherein the encapsulant is planarized to expose a surface of the semiconductor die.3. The semiconductor device of claim 1 , further including:an upper mold support including the cavity; anda lower mold support with spring-loaded lifter pins, wherein the reconstituted wafer is disposed over the spring-loaded lifter pins between the upper mold support and lower mold support.4. The semiconductor device of claim 1 , wherein the surface area of the carrier is 10-50% greater than the ...

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Номер записи: 38
24-10-2013 дата публикации

Laminate Structure for a Chip Card and Method for the Production Thereof

Номер: US20130277432A1
Автор: Edith Genevieve Therese Dangeard, Egon Konopitzky, Mitchell Peter Deyoung, Rungnattha Katworapattra
Принадлежит: Smartrac IP BV

The invention relates to a laminate structure ( 30 ) for a chip card ( 31 ), comprising a base layer ( 35 ), a chip module ( 32 ) accommodated at least partially in the base layer, and at least one cover layer ( 39 ) that covers the base layer, wherein an intermediate space ( 61 ) formed between the chip module and the cover layer as well as between the chip module and the base layer is filled with an adhesive material, wherein the adhesive material generates adhesive forces with respect to the wetted surfaces of the base layer and of the cover layer and generates adhesive forces with respect to the wetted surfaces of the chip module as well.

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Номер записи: 39
31-10-2013 дата публикации

Method for producing semiconductor device

Номер: US20130288428A1
Автор: Eiji Toyoda, Kosuke Morita, Takashi Oda
Принадлежит: Nitto Denko Corp

A method for producing a semiconductor device, including a semiconductor chip, for improving production efficiency and the flexibility of production design is provided. The method comprises: preparing a semiconductor chip having a first main surface on which an electroconductive member is formed; preparing a supporting structure in which, over a support configured to transmit radiation, a radiation curable pressure-sensitive adhesive layer and a first thermosetting resin layer are laminated in this order; arranging the semiconductor chips on the first thermosetting resin layer to face the first thermosetting resin layer to a second main surface of the semiconductor chips opposite to the first main surface; laminating a second thermosetting resin layer over the first thermosetting resin layer to cover the semiconductor chips; and curing the radiation curable pressure-sensitive adhesive layer by irradiating from the support side to peel the radiation curable pressure-sensitive adhesive layer from the first thermosetting resin layer.

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Номер записи: 40
07-11-2013 дата публикации

CONNECTION OF A CHIP PROVIDED WITH THROUGH VIAS

Номер: US20130292824A1
Автор: Bar Pierre, Joblot Sylvain
Принадлежит: STMICROELECTRONICS SA

A chip provided with through vias wherein the vias are formed of an opening with insulated walls coated with a conductive material and filled with an easily deformable insulating material, elements of connection to another chip being arranged in front of the easily deformable insulating material. 1. A device comprising:a substrate that includes a through via defined by sidewalls;a conductive material over the sidewalls of the through via;a deformable insulating material located on the conductive material and filling the through via; andconnection elements arranged at opposite ends of the deformable insulating material.2. The device of claim 1 , wherein said conductive material is copper.3. The device of claim 1 , wherein said deformable insulating material is a polysiloxane polymer.4. The device of claim 1 , wherein the connection elements are pads or metal areas configured to be connected to bumps.5. The device of claim 1 , wherein the connection elements are pillars of a conductive material.6. The device of claim 1 , wherein the connection elements are pillars of copper configured to be connected to bumps.7. The device of claim 1 , wherein at least some of the conductive material extends beyond the through via.8. The device of claim 7 , wherein the connection elements are coupled to the conductive material that extends beyond the through via.9. The device of claim 1 , wherein the substrate is silicon.10. The device of claim 1 , further comprising an insulating layer located on the sidewalls of the through via under the conductive material.11. A method comprising:etching through holes in a substrate, each through hole having sidewalls;depositing a conductive material in the through holes;forming an opening in the conductive material of each through hole by etching a center portion of the conductive material;filling each of the openings with a deformable insulating material.12. The method of claim 11 , wherein the substrate is silicon.13. The method of claim 11 , ...

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Номер записи: 41
14-11-2013 дата публикации

MICROELECTRONIC PACKAGE WITH STACKED MICROELECTRONIC ELEMENTS AND METHOD FOR MANUFACTURE THEREOF

Номер: US20130300000A1
Автор: Haba Belgacem, Masuda Norihito, Mohammed Ilyas, Sato Hiroaki
Принадлежит:

A microelectronic package may include a stacked microelectronic unit including at least first and second vertically stacked microelectronic elements each having a front face facing a top surface of the package. The front face of the first element may be adjacent the top surface, and the first element may overlie the front face of the second element such that at least a portion of the front face of the second element having an element contact thereon extends beyond an edge of the first element. A conductive structure may electrically connect a first terminal at the top surface to an element contact at the front face of the second element, and include a continuous monolithic metal feature extending along the top surface and through at least a portion of an encapsulant, which is between the top surface and the front face of the second element, towards the element contact. 1a stacked microelectronic unit including at least first and second vertically stacked microelectronic elements each having a front face facing the top surface and a rear face remote from the front face, wherein the front face of the first microelectronic element is adjacent the top surface, wherein the first microelectronic element overlies the front face of the second microelectronic element such that at least a portion of the front face of the second microelectronic element having at least one element contact thereon extends beyond an edge of the first microelectronic element;an encapsulant between the top surface and the front face of the second microelectronic element;at least one first package terminal at the top surface, the first terminal usable to connect the package to a contact of a first microelectronic component external to the package; anda conductive structure electrically connecting the first terminal to at least one element contact at the front face of the second microelectronic element, the conductive structure including a continuous monolithic metal feature extending along the top ...

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Номер записи: 42
14-11-2013 дата публикации

RESIN SEALED MODULE

Номер: US20130300002A1
Автор: Kitaichi Tetsuya, Yokoyama Yasuo
Принадлежит:

A resin-sealed module is provided which reduces the warpage of a substrate and the detachment between a sealing resin and the substrate which occur during re-reflow, has the excellent flatness of the top and bottom surfaces, and reduces the occurrence of the short failures. A resin layer made of a thermoplastic resin is arranged on top of a substrate, and a resin layer made of a thermosetting resin is arranged on top of this resin layer, thereby reducing the warpage of the substrate and the detachment between the sealing resin and the substrate which occur during re-reflow. 1. A resin-sealed module comprising:a substrate including an external electrode;an electronic component arranged on the substrate, and mounted onto the substrate by a solder;a first resin layer arranged on the substrate, wherein at least the solder is embedded in the first resin layer, and the first resin layer comprises a thermoplastic resin containing an inorganic filler; anda second resin layer arranged on the first resin layer, wherein the second resin layer comprises a thermosetting resin containing an inorganic filler.2. The resin-sealed module according to claim 1 , wherein a softening temperature of the thermoplastic resin equal to or lower than a melting point of the solder. 1. Field of the InventionThe present invention relates to a resin-sealed module in which electronic components are sealed with the resin.2. Description of the Related ArtAs a resin-sealed module according to the related art, for example, a module described in Patent Document 1 is known. Hereinafter, the resin-sealed module described in Patent Document 1 will be illustrated with reference to . is a cross-sectional view of the resin-sealed module.A resin-sealed module includes an insulating substrate , and a sealing resin layer made of a thermosetting resin. An IC chip and an electronic component mounted onto the insulating substrate as described below are embedded in the sealing resin layer . A wiring conductor is ...

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Номер записи: 43
21-11-2013 дата публикации

SEMICONDUCTOR DEVICE

Номер: US20130306991A1
Автор: Hiramatsu Seiki, Ikuta Hiroya, Nishimura Takashi, Ota Tatsuo, Terai Mamoru
Принадлежит: Mitsubishi Electric Corporation

A semiconductor device includes: a semiconductor-element substrate in which a front-surface electrode pattern is formed on a surface of an insulating substrate and a back-surface electrode is formed on another surface; semiconductor elements affixed to the surface of the front-surface electrode pattern opposite the insulating substrate; and a sealing resin member which covers the semiconductor element and the semiconductor-element substrate, wherein at a position of the front-surface electrode pattern where the position has potential equivalent to that of the front-surface electrode pattern at a position where a semiconductor element is bonded, an insulating terminal table formed with a conductive relay terminal and an insulating member that insulates the relay terminal and the front-surface electrode pattern from each other are provided, and wiring from the semiconductor element to the outside is led out via the relay terminal. 1. A semiconductor device , comprising:a semiconductor-element substrate in which a front-surface electrode pattern is formed on a surface of an insulating substrate and a back-surface electrode is formed on another surface of the insulating substrate;a semiconductor element affixed, via a bonding material, to the surface of the electrode pattern opposite the insulating substrate; anda first sealing resin member which covers the semiconductor element and the semiconductor-element substrate,wherein at a position of the front-surface electrode pattern where the position has electric potential equivalent to electric potential of the front-surface electrode pattern at a position where the semiconductor element is bonded, an insulating terminal table which is formed with a conductive relay terminal and an insulating member that insulates the relay terminal and the front-surface electrode pattern from each other is provided, and wiring from the semiconductor element to the outside is led out via the relay terminal.2. A semiconductor device ...

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Номер записи: 44
21-11-2013 дата публикации

Conductive chip disposed on lead semiconductor package and methods of making the same

Номер: US20130307134A1
Автор: David Chong, Jatinder Kumar
Принадлежит: Fairchild Semiconductor Corp

In one implementation, a method of forming a conductive device can include depositing a non-conductive epoxy on a first portion of a lower surface of a semiconductor die, and can include depositing a conductive epoxy on a second portion of the lower surface of the semiconductor die.

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Номер записи: 45
21-11-2013 дата публикации

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

Номер: US20130307163A1
Автор: Inoue Akinobu, SORIMACHI HARUO
Принадлежит: SHINKO ELECTRIC INDUSTRIES CO., LTD.

A semiconductor device includes a wiring substrate, a semiconductor chip whose connection terminal is connected to the wiring substrate, an underfill resin formed from a clearance between the wiring substrate and the semiconductor chip to a periphery area of the semiconductor chip, wherein the underfill resin in the periphery area is formed at a same height as an upper surface of the semiconductor chip, an auxiliary member fixed on the semiconductor chip by an adhesive layer, and including a protruding portion which protrudes to an outside from the semiconductor chip, and the protruding portion arranged at least on the underfill resin via the adhesive layer, and a sealing resin sealing the underfill resin and at least side faces of the auxiliary member, wherein respective coefficients of thermal expansion of the auxiliary member and the adhesive layer are larger than a coefficient of thermal expansion of the semiconductor chip. 1. A semiconductor device , comprising:a wiring substrate;a semiconductor chip whose connection terminal is connected to the wiring substrate;an underfill resin formed from a clearance between the wiring substrate and the semiconductor chip to a periphery area of the semiconductor chip, wherein the underfill resin in the periphery area is formed at a same height as an upper surface of the semiconductor chip;an auxiliary member fixed on the semiconductor chip by an adhesive layer, and including a protruding portion which protrudes to an outside from the semiconductor chip, and the protruding portion arranged at least on the underfill resin via the adhesive layer; anda sealing resin sealing the underfill resin and at least side faces of the auxiliary member;wherein respective coefficients of thermal expansion of the auxiliary member and the adhesive layer are larger than a coefficient of thermal expansion of the semiconductor chip.2. A semiconductor device according to claim 1 , wherein the coefficient of thermal expansion of the auxiliary ...

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Номер записи: 46
21-11-2013 дата публикации

Manufacturing method of substrate for a semiconductor package, manufacturing method of semiconductor package, substrate for a semiconductor package and semiconductor package

Номер: US20130309818A1
Автор: Shigeru Hosomomi, Yoichiro Hamada
Принадлежит: SUMITOMO METAL MINING CO LTD

A manufacturing method of a substrate for a semiconductor package includes a resist layer forming step to form a resist layer on a surface of a conductive substrate; an exposure step to expose the resist layer using a glass mask with a mask pattern including a transmission area, a light shielding area, and an intermediate transmission area, wherein transmittance of the intermediate transmission area is lower than that of the transmission area and is higher than that of the light shielding area; a development step to form a resist pattern including a hollow with a side shape including a slope part decreasing in hollow circumference as the hollow circumference approaches the substrate; and a plating step to plate on an exposed area to form a metal layer with a side shape including a slope part decreasing in circumference as the circumference approaches the substrate.

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Номер записи: 47
26-12-2013 дата публикации

Soi substrate, method for manufacturing soi substrate, and method for manufacturing semiconductor device

Номер: US20130341755A1
Автор: Kazuo Kokumai
Принадлежит: Canon Inc

An insulating portion has a first region, a second region, and a third region in the stated order from the silicon portion side, the nitrogen concentration of the first region is lower than the nitrogen concentration of the second region and the oxygen concentration of the first region, the nitrogen concentration of the third region is lower than the nitrogen concentration of the second region and the oxygen concentration of the third region, and the thickness of the first region is larger than the thickness of the third region.

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Номер записи: 48
26-12-2013 дата публикации

Method of fabricating wafer level package

Номер: US20130344627A1
Автор: Eun-Kyoung Choi, Ji-Seok HONG, Jong-Youn Kim, Sang-uk Han, Sang-Won Kim
Принадлежит: SAMSUNG ELECTRONICS CO LTD

A method of fabricating a wafer level package includes preparing a wafer including a plurality of first semiconductor chips, mounting a plurality of second semiconductor chips on the wafer, disposing the wafer on a lower mold and disposing an upper mold so as to surround edges of a top surface of the wafer, dispensing a molding member on the wafer, and pressurizing the molding member by using a plunger so as to fabricate a wafer level package in which a top surface of each of the plurality of second semiconductor chips is exposed.

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Номер записи: 49
02-01-2014 дата публикации

ENCAPSULATING LAYER-COVERED SEMICONDUCTOR ELEMENT, PRODUCING METHOD THEREOF, AND SEMICONDUCTOR DEVICE

Номер: US20140001656A1
Автор: EBE Yuki, FUKE Kazuhiro, KATAYAMA Hiroyuki, KIMURA Ryuichi, ONISHI Hidenori
Принадлежит:

A method for producing an encapsulating layer-covered semiconductor element includes the steps of preparing a support sheet including a hard support board; disposing a semiconductor element at one side in a thickness direction of the support sheet; disposing an encapsulating layer formed from an encapsulating resin composition containing a curable resin at the one side in the thickness direction of the support sheet so as to cover the semiconductor element; curing the encapsulating layer to encapsulate the semiconductor element by the encapsulating layer that is flexible; cutting the encapsulating layer that is flexible corresponding to the semiconductor element to produce an encapsulating layer-covered semiconductor element; and peeling the encapsulating layer-covered semiconductor element from the support sheet. 1. A method for producing an encapsulating layer-covered semiconductor element comprising:a preparing step of preparing a support sheet including a hard support board;a semiconductor element disposing step of disposing a semiconductor element at one side in a thickness direction of the support sheet;a layer disposing step of, after the semiconductor element disposing step, disposing an encapsulating layer formed from an encapsulating resin composition containing a curable resin at the one side in the thickness direction of the support sheet so as to cover the semiconductor element;an encapsulating step of curing the encapsulating layer to encapsulate the semiconductor element by the encapsulating layer that is flexible;a cutting step of after the encapsulating step, cutting the encapsulating layer that is flexible corresponding to the semiconductor element to produce an encapsulating layer-covered semiconductor element including the semiconductor element and the encapsulating layer covering the semiconductor element; anda semiconductor element peeling step of after the cutting step, peeling the encapsulating layer-covered semiconductor element from the ...

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Номер записи: 50
02-01-2014 дата публикации

ENCAPSULATING LAYER-COVERED SEMICONDUCTOR ELEMENT, PRODUCING METHOD THEREOF, AND SEMICONDUCTOR DEVICE

Номер: US20140001657A1
Автор: EBE Yuki, FUKE Kazuhiro, KATAYAMA Hiroyuki, KIMURA Ryuichi, ONISHI Hidenori
Принадлежит:

A method for producing an encapsulating layer-covered semiconductor element includes the steps of preparing a support sheet including a hard support board formed with a through hole passing through in a thickness direction and a pressure-sensitive adhesive layer laminated on a surface at one side in the thickness direction of the support board so as to cover the through hole; disposing a semiconductor element on a surface at one side in the thickness direction of the pressure-sensitive adhesive layer in opposed to the through hole in the thickness direction; covering the semiconductor element with an encapsulating layer to produce an encapsulating layer-covered semiconductor element; and inserting a pressing member into the through hole from the other side in the thickness direction to peel the encapsulating layer-covered semiconductor element from the pressure-sensitive adhesive layer. 1. A method for producing an encapsulating layer-covered semiconductor element comprising:a preparing step of preparing a support sheet including a hard support board formed with a through hole passing through in a thickness direction and a pressure-sensitive adhesive layer laminated on a surface at one side in the thickness direction of the support board so as to cover the through hole;a semiconductor element disposing step of disposing a semiconductor element on a surface at one side in the thickness direction of the pressure-sensitive adhesive layer in opposed to the through hole in the thickness direction;a semiconductor element covering step of covering the semiconductor element with an encapsulating layer to produce an encapsulating layer-covered semiconductor element including the semiconductor element and the encapsulating layer covering the semiconductor element; anda semiconductor element peeling step of inserting a pressing member into the through hole from the other side in the thickness direction to press the pressure-sensitive adhesive layer corresponding to the through ...

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Номер записи: 51
09-01-2014 дата публикации

DIE UP FULLY MOLDED FAN-OUT WAFER LEVEL PACKAGING

Номер: US20140008809A1
Автор: Scanlan Christopher M.
Принадлежит: Deca Technologies, Inc.

A method of manufacturing a semiconductor chip comprising placing a plurality of die units each having an active front surface and a back surface facing front surface up on an encapsulant layer, encapsulating the plurality of die units on the active surface of the encapsulant layer with an encapsulant covering a front surface and four side surfaces of each of the plurality of die units, and exposing, through the encapsulation on the front surface, conductive interconnects electrically connecting a die bond pad to a redistribution layer. 1. A method of making a semiconductor package , comprising:placing a plurality of die units face up on a carrier, each die unit having an active front surface oriented away from the carrier and a back surface opposing the active front surface, the active front surface and the back surface joined by at least four side surfaces;forming at least one conductive interconnect coupled to each of the plurality of die units; andencapsulating the plurality of die units and the at least one conductive interconnects with an encapsulant that covers the active front surface and the at least four side surfaces of each of the plurality of die units.2. The method of claim 1 , further comprising encapsulating the plurality of die units and the at least one conductive interconnects in a single step.3. The method of claim 1 , further comprising exposing the at least one conductive interconnect through removal of a portion of the encapsulant covering the active front surface.4. The method of claim 1 , further comprising forming the encapsulant as a polymer layer or dielectric film positioned between the plurality of die units and the carrier.5. The method of claim 1 , further comprising disposing a dielectric film over the back surface of the plurality of die units comprising a thickness between a ratio of 5:1 and 1:5 compared with a thickness of the encapsulant covering the active front surface.6. The method of claim 1 , further comprising encapsulating ...

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Номер записи: 52
16-01-2014 дата публикации

Electronic device packages and methods of manufacturing the same

Номер: US20140015072A1
Автор: Tae Jim KANG
Принадлежит: SK hynix Inc

The electronic device package includes a package substrate including a frame portion and a cantilever portion surrounded by the frame portion, at least one semiconductor chip mounted on the cantilever portion, and a molding member disposed on the package substrate to cover the at least one semiconductor chip. The cantilever portion has a first edge connected to the frame portion and declines from the first edge toward a second edge located opposite to the first edge. Related methods are also provided.

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Номер записи: 53
16-01-2014 дата публикации

Semiconductor chips having improved solidity, semiconductor packages including the same and methods of fabricating the same

Номер: US20140015115A1
Автор: Jong Hyun Nam
Принадлежит: SK hynix Inc

Semiconductor chips are provided. The semiconductor chip includes a semiconductor chip body having an arch-shaped groove in a backside thereof and a non-conductive material pattern filling the arch-shaped groove. Related methods are also provided.

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Номер записи: 54
16-01-2014 дата публикации

SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME

Номер: US20140015148A1
Автор: LYU Ju-hyun
Принадлежит:

A semiconductor package and a method of manufacturing the same are provided. The semiconductor package includes a circuit board, at least one semiconductor chip mounted on the circuit board, a spacer disposed on the at least one semiconductor chip, the spacer having a thickness of about 5 μm to about 110 μm, and an upper surface of the spacer exposed externally; and an encapsulant covering the at least one semiconductor chip. The semiconductor package may have a small thickness and may prevent incomplete molding that causes exposure of an active surface of a semiconductor chip. 1. A semiconductor package comprising:a circuit board;at least one semiconductor chip mounted on the circuit board;a spacer disposed on the at least one semiconductor chip, an upper surface of the spacer exposed externally; andan encapsulant covering side surfaces of the at least one semiconductor chip and the spacer.2. The semiconductor package of claim 1 , wherein the spacer has a thickness of abour 5 μm to about 110 μm3. The semiconductor package of claim 1 , wherein the upper surface of the spacer and an upper surface of the encapsulant are substantially coplanar.4. The semiconductor package of claim 1 , wherein a horizontal distance between an edge of the spacer and an edge of the at least one semiconductor chip is equal to or less than about 200 μm.5. The semiconductor package of claim 4 , wherein at least a portion of the edge of the spacer protrudes outside the at least one semiconductor chip.6. The semiconductor package of claim 4 , wherein at least a portion of the edge of the spacer is disposed on an upper surface of the at least one semiconductor chip.7. The semiconductor package of claim 1 , wherein at least a portion of side surfaces of the spacer is inclined inward in a direction away from the at least one semiconductor chip.8. The semiconductor package of claim 1 , wherein a transverse width of the spacer is reduced in a direction away from the at least one semiconductor chip. ...

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Номер записи: 55
23-01-2014 дата публикации

Semiconductor package with single sided substrate design and manufacturing methods thereof

Номер: US20140021636A1
Автор: Bernd Karl Appelt, Chia-Cheng Chen, Kuang-Hsiung Chen, Ming Chiang LEE, Pao-Ming Hsieh, Shih-Fu Huang, Tzu-Hui Chen, Yuan-Chang Su
Принадлежит: Advanced Semiconductor Engineering Inc

A multilayer substrate includes a first outer conductive patterned layer, a first insulating layer exposing a portion of the first outer conductive patterned layer to define a first set of pads, a second outer conductive patterned layer, and a second insulating layer exposing a portion of the second outer conductive patterned layer to define a second set of pads. The multilayer substrate further includes inner layers each with an inner conductive patterned layer, multiple inner conductive posts formed adjacent to the inner conductive patterned layer, and an inner dielectric layer, where the inner conductive patterned layer and the inner conductive posts are embedded in the inner dielectric layer, and a top surface of each of the inner conductive posts is exposed from the inner dielectric layer.

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Номер записи: 56
30-01-2014 дата публикации

Semiconductor device and method for manufacturing the same

Номер: US20140027920A1
Автор: Takeshi Kodama
Принадлежит: Fujitsu Semiconductor Ltd

A semiconductor device includes a first semiconductor chip including a first surface and a plurality of first electrodes disposed on the first surface; a second semiconductor chip including a second surface which faces the first surface, a plurality of second electrodes each of which includes at least one end disposed on the second surface, and a plurality of first protrusions each of which surrounds the one end of each of the second electrodes on an electrode by electrode basis; a plurality of conductive joint materials each of which joins a third electrode included in the first electrodes to the one end of an electrode which faces the third electrode among the second electrodes; and a plurality of first underfill resins each of which is disposed inside one of the first protrusions and covers one of the conductive joint materials on a material by material basis.

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Номер записи: 57
30-01-2014 дата публикации

SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME

Номер: US20140027926A1
Автор: Chan Mu-Hsuan, Chen Wang-Ting, Lai Yi-Che, Liao Yi-Chian, Lin Chun-Tang
Принадлежит: SILICONWARE PRECISION INDUSTRIES CO., LTD.

A semiconductor package is provided, including: a carrier; at least an interposer disposed on the carrier; an encapsulant formed on the carrier for encapsulating the interposer while exposing a top side of the interposer; a semiconductor element disposed on the top side of the interposer; and an adhesive formed between the interposer and the semiconductor element. By encapsulating the interposer with the encapsulant, warpage of the interposer is avoided and a planar surface is provided for the semiconductor element to be disposed thereon, thereby improving the reliability of electrical connection between the interposer and the semiconductor element. 1. A semiconductor package , comprising:a carrier;at least an interposer having opposite first and second sides and disposed on the carrier through the first side thereof;an encapsulant formed on the carrier for encapsulating the interposer, the encapsulant having a side flush with a side of the interposer;a semiconductor element disposed on the second side of the interposer; andan adhesive formed between the second side of the interposer and the semiconductor element.2. The semiconductor package of claim 1 , wherein the carrier is a packaging substrate.3. The semiconductor package of claim 1 , further comprising a plurality of conductive through holes formed in the interposer to communicate the first and second sides of the interposer.4. The semiconductor package of claim 3 , wherein the conductive through holes are electrically connected to the carrier.5. The semiconductor package of claim 3 , further comprising a redistribution layer (RDL) structure formed at the second side of the interposer for electrically connecting the conductive through holes and the semiconductor element.6. The semiconductor package of claim 1 , wherein the second side of the interposer is flush with a surface of the encapsulant.7. The semiconductor package of claim 1 , wherein the semiconductor element is electrically connected to the ...

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Номер записи: 58
06-02-2014 дата публикации

SEMICONDUCTOR PACKAGE AND METHOD OF FORMING THE SAME

Номер: US20140035137A1
Автор: CHEON SEUNGJIN, KWON Heungkyu
Принадлежит: SAMSUNG ELECTRONICS CO., LTD.

Semiconductor packages are disclosed. In a semiconductor package, a package board may include a hole. A mold layer may cover an upper portion of the package board and extend through the hole to cover at least a portion of a bottom surface of the package board. Each of the sidewalls of a lower mold portion may have a symmetrical structure with respect to the hole penetrating the package board, such that a warpage phenomenon of the semiconductor package may be reduced. 1. A semiconductor package comprising:a package board including at least one hole;at least one semiconductor chip mounted on the package board by a flip chip bonding method;a mold layer having an upper mold portion covering the at least one semiconductor chip and the package board and a lower mold portion connected to the upper mold portion through the hole, the lower mold portion covering at least a portion of a bottom surface of the package board; andlower solder balls disposed on the bottom surface of the package board, wherein the lower solder balls are not covered by the lower mold portion, andwherein a plurality of outermost sidewalls of the lower mold portion are disposed at a substantially equal distance from a center of the hole.2. The semiconductor package of claim 1 , wherein each of the plurality of outermost sidewalls of the lower mold portion are disposed at an equal distance from corresponding sidewalls of the package board.3. The semiconductor package of claim 1 , wherein the lower mold portion comprises:a center pattern overlapped by the hole;at least one edge pattern spaced apart from the center pattern with at least one of the lower solder balls disposed therebetween; anda plurality of connection patterns connecting the center pattern to the edge pattern, wherein each of said connection patterns is disposed between adjacent ones of the lower solder balls.4. The semiconductor package of claim 3 , wherein the center pattern has a circular or polygonal shape having a width equal to or ...

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Номер записи: 59
06-02-2014 дата публикации

SEMICONDUCTOR DEVICE AND PROGRAMMING METHOD

Номер: US20140035170A1
Автор: ONODERA Masanori, TAYA Koji
Принадлежит: SPANSION LLC

The present invention include a semiconductor device and a method therefor, the method includes disposing a sheet-shaped resin at a side opposite to the chip mounting portion mounting semiconductor chips to be mounted on the chip mounting portion, and forming a resin sealing portion between the sheet-shaped resin and the chip mounting portion, to seal the semiconductor chips. According to an aspect of the present invention, it is possible to provide a semiconductor device and a fabrication method therefor, by which it is possible to reduce the size of the package and to prevent the generation of an unfilled portion in a resin sealing portion or a filler-removed portion or to prevent the exposure of wire from the resin sealing portion. 1. A method for fabricating a semiconductor device comprising:mounting a semiconductor chip on a chip mounting portion;disposing a sheet-shaped resin in contact with the semiconductor chip;coupling a wire between the semiconductor chip and the chip mounting portion, wherein the wire is partially embedded in the sheet-shaped resin; andforming a resin sealing portion between the sheet-shaped resin and the chip mounting portion, to seal the semiconductor chip.2. The method as claimed in claim 1 , wherein disposing the sheet-shaped resin comprises disposing the sheet-shaped resin on a surface of a die to seal the semiconductor chip claim 1 , the surface opposing the semiconductor chip.3. The method as claimed in claim 2 , wherein forming the resin sealing portion includes:disposing an uncured resin between the sheet-shaped resin and the semiconductor chip; andsealing the semiconductor chip with the uncured resin.4. The method as claimed in claim 1 , wherein forming the resin sealing portion comprises forming the resin sealing portion by transfer molding.5. The method as claimed in claim 1 , wherein the sheet-shaped resin does not include a filler.6. The method as claimed in claim 1 , wherein forming the resin sealing portion comprises ...

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Номер записи: 60
06-02-2014 дата публикации

Semiconductor package and method of fabricating the same

Номер: US20140038354A1
Автор: Min gi HONG
Принадлежит: SAMSUNG ELECTRONICS CO LTD

Disclosed are semiconductor packages and methods of fabricating the same. A method may include preparing a wiring board including a mounting region and a molding region surrounding the mounting region; forming a through-hole penetrating through the wiring board at the mounting region; mounting a semiconductor chip on the mounting region of the wiring board by a flip chip bonding method; and forming a molding covering the molding region of the wiring board and the semiconductor chip and filling the through-hole and a space between the semiconductor chip and the wiring board. The wiring board may have a first surface on which the semiconductor chip is mounted, and a second surface opposite to the first surface. A portion of the molding filling the through-hole has a surface coplanar with the second surface of the wiring board.

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Номер записи: 61
13-02-2014 дата публикации

RESIN SHEET FOR SEALING ELECTRONIC COMPONENT, RESIN-SEALED TYPE SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING RESIN-SEALED TYPE SEMICONDUCTOR DEVICE

Номер: US20140042645A1
Автор: MATSUMURA Takeshi, SHIMIZU Yusaku, Torinari Tsuyoshi, Toyoda Eiji
Принадлежит: NITTO DENKO CORPORATION

An electronic-component-sealing resin sheet capable of restraining the warp amount of a package obtained by use of the sheet, a resin-sealed type semiconductor device high in reliability, and a method for producing the device are provided. The present invention relates to a resin sheet for sealing an electronic component, wherein after the resin sheet is hot-pressed onto an iron nickel alloy plate containing 42% by weight of nickel and having a shape 90 mm square and a thickness of 0.15 mm to give a thickness 0.2 mm and the resultant hot-pressed unit is cured at 150° C., the unit exhibits a warp amount of 5 mm or less. 1. An electronic-component-sealing resin sheet , wherein after the electronic-component-sealing resin sheet is hot-pressed onto an iron nickel alloy plate containing 42% by weight of nickel and having a shape 90 mm square and a thickness of 0.15 mm to give a thickness 0.2 mm and a resultant hot-pressed unit is cured at 150° C. , the hot-pressed unit exhibits a warp amount of 5 mm or less.2. The electronic-component-sealing resin sheet according to claim 1 , wherein a content by percentage of silica in the electronic-component-sealing resin sheet is from 85% by weight to 93% by weight.3. The electronic-component-sealing resin sheet according to claim 1 , which is produced by kneading extrusion.4. The electronic-component-sealing resin sheet according to claim 1 , wherein after the electronic-component-sealing resin sheet is hot-pressed onto a glass fabric based epoxy resin having a shape 90 mm square and a thickness of 0.3 mm to give a thickness 0.2 mm and the resultant hot-pressed unit is cured at 150° C. claim 1 , the hot-pressed unit exhibits a warp amount of 4 mm or less.5. The electronic-component-sealing resin sheet according to claim 1 , which has claim 1 , after curing claim 1 , a linear expansion coefficient of 10 ppm/K or less at temperatures lower than a glass transition temperature of the cured electronic-component-sealing resin sheet.6. ...

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Номер записи: 62
27-02-2014 дата публикации

SEMICONDUCTOR MEMORY DEVICE AND FABRICATION METHOD THEREOF

Номер: US20140054752A1
Автор: CHAE Su Jin, KIM Jin Hyock, Kwon Young Seok
Принадлежит: SK HYNIX INC.

A semiconductor memory device and a fabrication method thereof capable of improving electric contact characteristic between an access device and a lower electrode are provided. The semiconductor memory device includes an access device formed in a pillar shape on a semiconductor substrate, a first conductive layer formed over the access device, a protection layer formed on an edge of the first conductive layer to a predetermined thickness, and a lower electrode connected to the first conductive layer. 1. A semiconductor memory device , comprising:{'i': 'ate;', 'an access device formed in a pillar shape on a semiconductor subs'}a first conductive layer formed over the access device;a protection layer formed on an edge of the first conductive layer to a predetermined thickness; anda lower electrode connected to the first conductive layer.2. The semiconductor memory device of claim 1 , further comprising a spacer formed on the protection layer to surround an outer circumference of the lower electrode.3. The semiconductor memory device of claim 2 , wherein the protection layer is comprised of substantially the same material as the spacer.4. The semiconductor memory device of claim 2 , wherein the protection layer includes a material having the same or similar etching properties as the protection layer.5. A method of fabricating a semiconductor memory device claim 2 , the method comprising:sequentially forming an access device, a first conductive layer, a protection layer, and a sacrificial layer on a semiconductor substrate;patterning, in a pillar shape, the sacrificial layer, the protection layer, the first conductive layer, and the access device, burying an insulating layer between pillar type structures, and performing planarization on the insulating layer to expose a surface of the sacrificial layer;removing the sacrificial layer; andremoving the protection layer.6. The method of claim 5 , wherein removing the protection layer further includes forming a spacer ...

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Номер записи: 63
27-02-2014 дата публикации

Method of manufacturing semiconductor device

Номер: US20140054759A1
Автор: Hiroyoshi Taya, Tadatoshi Danno, Yoshiharu Shimizu
Принадлежит: Renesas Electronics Corp

A non-leaded semiconductor device comprises a sealing body for sealing a semiconductor chip, a tab in the interior of the sealing body, suspension leads for supporting the tab, leads having respective surfaces exposed to outer edge portions of a back surface of the sealing body, and wires connecting pads formed on the semiconductor chip and the leads. End portions of the suspension leads positioned in an outer periphery portion of the sealing body are unexposed to the back surface of the sealing body, but are covered with the sealing body. Stand-off portions of the suspending leads are not formed in resin molding. When cutting the suspending leads, corner portions of the back surface of the sealing body are supported by a flat portion of a holder portion in a cutting die having an area wider than a cutting allowance of the suspending leads, whereby chipping of the resin is prevented.

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Номер записи: 64
27-02-2014 дата публикации

ELECTRONIC COMPONENT BUILT-IN SUBSTRATE AND METHOD OF MANUFACTURING THE SAME

Номер: US20140054773A1
Автор: IIZUKA Hajime, Koyama Tetsuya, KURASHIMA Nobuyuki, TANAKA Koichi
Принадлежит:

An electronic component built-in substrate, includes a lower wiring substrate, an electronic component mounted on the lower wiring substrate, an intermediate wiring substrate including an opening portion in which the electronic component is mounted, and arranged in a periphery of the electronic component, and connected to the lower wiring substrate via a first conductive ball, an upper wiring substrate arranged over the electronic component and the intermediate wiring substrate, and connected to the intermediate wiring substrate via a second conductive ball, and a resin filled into respective areas between the lower wiring substrate, the intermediate wiring substrate, and the upper wiring substrate, and sealing the electronic component, wherein the first conductive ball and the second conductive ball are arranged in displaced positions mutually. 1. An electronic component built-in substrate , comprising:a lower wiring substrate;an electronic component mounted on the lower wiring substrate;an intermediate wiring substrate including an opening portion in which the electronic component is mounted, and arranged in a periphery of the electronic component, and connected to the lower wiring substrate via a first conductive ball;an upper wiring substrate arranged over the electronic component and the intermediate wiring substrate, and connected to the intermediate wiring substrate via a second conductive ball; anda resin filled into respective areas between the lower wiring substrate, the intermediate wiring substrate, and the upper wiring substrate, and sealing the electronic component;wherein the first conductive ball and the second conductive ball are arranged in displaced positions mutually.2. An electronic component built-in substrate according to claim 1 , wherein the first conductive ball and the second conductive ball are arranged in positions that are not overlapped mutually claim 1 , when viewed from a top.3. An electronic component built-in substrate according to ...

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Номер записи: 65
27-02-2014 дата публикации

Semiconductor Device and Method of Forming RDL Using UV-Cured Conductive Ink Over Wafer Level Package

Номер: US20140054802A1
Автор: Koo Jun Mo, Shim Il Kwon
Принадлежит: STATS CHIPPAC, LTD.

A semiconductor device has a semiconductor die and first insulating layer formed over the semiconductor die. A patterned trench is formed in the first insulating layer. A conductive ink is deposited in the patterned trench by disposing a stencil over the first insulating layer with an opening aligned with the patterned trench and depositing the conductive ink through the opening in the stencil into the patterned trench. 1. A method of making a semiconductor device , comprising:providing a semiconductor die;forming a first insulating layer over the semiconductor die;forming a patterned trench in the first insulating layer;depositing a conductive ink in the patterned trench; andcuring the conductive ink by ultraviolet light.2. The method of claim 1 , further including curing the conductive ink at room temperature.3. The method of claim 1 , wherein depositing the conductive ink includes:disposing a stencil over the first insulating layer with an opening in the stencil aligned with the patterned trench; anddepositing the conductive ink through the opening in the stencil into the patterned trench.4. The method of claim 1 , wherein depositing the conductive ink includes dispensing the conductive ink through a nozzle into the patterned trench.5. The method of claim 1 , further including:forming a second insulating layer over the first insulating layer and conductive ink; andforming an interconnect structure over the conductive ink.6. The method of claim 1 , further including:depositing an encapsulant around the semiconductor die;forming the patterned trench in the encapsulant; anddepositing the conductive ink in the patterned trench in the encapsulant.7. A method of making a semiconductor device claim 1 , comprising:providing a substrate;forming a first insulating layer over the substrate;forming a trench in the first insulating layer;depositing a conductive ink in the trench; andcuring the conductive ink.8. The method of claim 7 , further including curing the conductive ...

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Номер записи: 66
06-03-2014 дата публикации

SEMICONDUCTOR STRUCTURE AND METHOD OF MANUFACTURING THE SAME

Номер: US20140061904A1
Автор: LIAO TSUNG JEN
Принадлежит: CHIPMOS TECHNOLOGIES INC

A method of manufacturing a chip fan-out structure, said method includes forming a dry film with a predetermined pattern. Providing a chip wherein the distribution of the pad is corresponding to the dry film's predetermined pattern. Contacting the surface of the pad with the dry film. Forming a molding compound to encapsulate the chip, and removing the dry film to expose the pads. 1. A method for manufacturing a semiconductor package structure , comprising:forming a dry film with a predetermined pattern;providing a chip, the distribution of a pad of the chip being corresponding to the predetermined pattern of the dry film;contacting a surface of the pad of the chip with the dry film;forming a molding compound to encapsulate the chip; andremoving the dry film to expose the surface of the pad.2. The manufacturing method according to claim 1 , wherein the chip only has the surface of the pad in contact with the dry film.3. The manufacturing method according to claim 1 , further comprising:forming a conducting column in the molding compound, one end of the conducting column extending to a first surface of the molding compound and being electrically connected to the surface of the pad of the chip.4. The manufacturing method according to claim 2 , further comprising: providing a substrate to carry the dry film.5. The manufacturing method according to claim 4 , further comprising:placing a conducting layer on the substrate.6. The manufacturing method according to claim 5 , further comprising:patterning the conducting layer to form the conducting column.7. The manufacturing method according to claim 6 , wherein the chip only has the surface of the pad in contact with the dry film.8. The manufacturing method according to claim 1 , further comprising: forming a circuit layer on the surface of the pad of the chip.9. The manufacturing method according to claim 8 , further comprising:extending the circuit layer to the first surface of the molding compound.10. The manufacturing ...

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Номер записи: 67
20-03-2014 дата публикации

ENCAPSULATION OF CLOSELY SPACED GATE ELECTRODE STRUCTURES

Номер: US20140077308A1
Автор: Baars Peter, Carter Richard, Wei Andy
Принадлежит: GLOBAL FOUNDRIES Inc.

A semiconductor device includes a plurality of NMOS transistor elements, each including a first gate electrode structure above a first active region, at least two of the plurality of first gate electrode structures including a first encapsulating stack having a first dielectric cap layer and a first sidewall spacer stack. The semiconductor device also includes a plurality of PMOS transistor elements, each including a second gate electrode structure above a second active region, wherein at least two of the plurality of second gate electrode structures include a second encapsulating stack having a second dielectric cap layer and a second sidewall spacer stack. Additionally, the first and second sidewall spacer stacks each include at least three dielectric material layers, wherein each of the three dielectric material layers of the first and second sidewall spacer stacks include the same dielectric material. 117.-. (canceled)18. A semiconductor device , comprising:a plurality of NMOS transistor elements, wherein each of said plurality of NMOS transistor elements comprises a first gate electrode structure above a first active region of a semiconductor substrate, at least two of said plurality of first gate electrode structures comprise a first encapsulating stack, said first encapsulating stack comprises a first dielectric cap layer and a first sidewall spacer stack, and said first sidewall spacer stack comprises at least three dielectric material layers; anda plurality of PMOS transistor elements, wherein each of said plurality of PMOS transistor elements comprises a second gate electrode structure above a second active region of said semiconductor substrate, at least two of said plurality of second gate electrode structures comprise a second encapsulating stack, said second encapsulating stack comprises a second dielectric cap layer and a second sidewall spacer stack, and said second sidewall spacer stack comprises at least three dielectric material layers, wherein ...

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Номер записи: 68
20-03-2014 дата публикации

SEMICONDUCTOR PACKAGE, METHOD AND MOLD FOR PRODUCING SAME, INPUT AND OUTPUT TERMINALS OF SEMICONDUCTOR PACKAGE

Номер: US20140077345A1
Автор: Ikeda Hikaru, Iwata Motoyoshi, Kamiyama Tomohide, Naitou Hiroshi, UNO TAKASHI, Yahata Kazuhiro
Принадлежит: Panasonic Corporation

A semiconductor package according to the present invention includes: a semiconductor element where a high frequency signal is input or output; a planar lead terminal having an end electrically connected to an input terminal or an output terminal of the semiconductor element; an encapsulation resin for encapsulating the lead terminal and the semiconductor element, the lead terminal having another end exposed from the resin; and a ground enhancing metal body encapsulated in the encapsulation resin, having a first main surface facing the lead terminal and a second main surface exposed from the encapsulation resin, wherein the ground enhancing metal body has a shape with a cross section parallel to the second main surface and having a smaller area than an area of the first main surface. 122-. (canceled)23. A semiconductor package comprising:a semiconductor element where a high frequency signal is input and/or output;a planar lead for transmitting the high frequency signal to the semiconductor element or an external circuit, the lead having an end electrically connected to an input terminal or an output terminal of the semiconductor element;a resin for encapsulating the lead and the semiconductor element, the lead having another end exposed from the resin; andan electric conductor for ground enhancement having a first main surface and a second main surface opposite to the first main surface, and encapsulated in the resin, the first main surface facing the lead with the resin therebetween, the second main surface being exposed from the resin,wherein the electric conductor has a shape with a cross section parallel to the second main surface and having a smaller area than an area of the first main surface.24. The semiconductor package according to claim 23 , further comprisinga planar die pad having a top surface on which the semiconductor element is disposed,wherein the die pad is encapsulated in the resin such that at least a portion of an undersurface of the die pad is ...

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Номер записи: 69
20-03-2014 дата публикации

Semiconductor Device and Method of Forming Dual-Sided Interconnect Structures in Fo-WLCSP

Номер: US20140077363A1
Автор: Chen Kang, Lin Yaojian
Принадлежит: STATS CHIPPAC, LTD.

A semiconductor device has a substrate including first and second conductive layers formed over first and second opposing surfaces of the substrate. A plurality of wire studs or stud bumps is formed over the substrate. A semiconductor die is mounted to the substrate between the wire studs. A first encapsulant is deposited around the semiconductor die. A first interconnect structure is formed over the semiconductor die and first encapsulant. A second encapsulant is deposited over the substrate, semiconductor die, and first interconnect structure. The second encapsulant can be formed over a portion of the semiconductor die and side surface of the substrate. A portion of the second encapsulant is removed to expose the substrate and first interconnect structure. A second interconnect structure is formed over the second encapsulant and first interconnect structure and electrically coupled to the wire studs. A discrete semiconductor device can be formed on the interconnect structure. 1. A method of making a semiconductor device , comprising:providing a substrate including first and second conductive layers formed over first and second opposing surfaces of the substrate;forming a plurality of wire studs over the substrate;mounting a semiconductor die to the substrate between the wire studs;forming a first interconnect structure over the semiconductor die;depositing a first encapsulant over the substrate, semiconductor die, and first interconnect structure; andforming a second interconnect structure over the first encapsulant and first interconnect structure and electrically coupled to the wire studs.2. The method of claim 1 , further including:forming a second encapsulant around the semiconductor die; andforming the first interconnect structure over the semiconductor die and second encapsulant.3. The method of claim 1 , further including removing a portion of the first encapsulant to expose the first interconnect structure.4. The method of claim 1 , further including ...

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Номер записи: 70
20-03-2014 дата публикации

Semiconductor Device and Method of Forming FO-WLCSP with Multiple Encapsulants

Номер: US20140077381A1
Автор: Hin Hwa Goh, Jose A. Caparas, KANG Chen, Yaojian Lin
Принадлежит: Stats Chippac Pte Ltd

A semiconductor device has a first semiconductor die including TSVs mounted to a carrier with a thermally releasable layer. A first encapsulant having a first coefficient of thermal expansion CTE is deposited over the first semiconductor die. The first encapsulant includes an elevated portion in a periphery of the first encapsulant that reduces warpage. A surface of the TSVs is exposed. A second semiconductor die is mounted to the surface of the TSVs and forms a gap between the first and second semiconductor die. A second encapsulant having a second CTE is deposited over the first and second semiconductor die and within the gap. The first CTE is greater than the second CTE. In one embodiment, the first and second encapsulants are formed in a chase mold. An interconnect structure is formed over the first and second semiconductor die.

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Номер записи: 71
27-03-2014 дата публикации

Resin-encapsulated semiconductor device and method of manufacturing the same

Номер: US20140084435A1
Автор: Noriyuki Kimura
Принадлежит: Seiko Instruments Inc

A resin-encapsulated semiconductor device includes: a semiconductor element mounted on a die pad portion; a plurality of lead portions disposed so that distal end parts thereof are opposed to the die pad portion; a metal thin wire for connecting an electrode of the semiconductor element to the lead portion; and an encapsulating resin for partially encapsulating those components. A bottom surface part of the die pad portion, and a bottom surface part, an outer surface part, and an upper end part of the lead portion are exposed from the encapsulating resin. A plated layer is formed on the exposed lead bottom surface part and the exposed lead upper end part.

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Номер записи: 72
27-03-2014 дата публикации

SEMICONDUCTOR PACKAGES, METHODS OF MANUFACTURING SEMICONDUCTOR PACKAGES, AND SYSTEMS INCLUDING SEMICONDUCTOR PACKAGES

Номер: US20140084456A1
Автор: Hong Ji-Seok, Kang Myun-sung, KIM Won-keun, Ko Jung-Min, Park Sang-Sick
Принадлежит:

A semiconductor package comprises a first semiconductor chip, a second semiconductor chip on the first semiconductor chip, a third semiconductor chip on the second semiconductor chip and a fourth semiconductor chip on the third semiconductor chip. A first underfill layer is positioned between the second semiconductor chip and the first semiconductor chip; a second underfill layer is positioned between the third semiconductor chip and the second semiconductor chip, and a third underfill layer is positioned between the fourth semiconductor chip and the third semiconductor chip. In some embodiments, the second underfill layer comprises a material that is different than the first and third underfill layers. 1. A semiconductor package comprising:a first semiconductor chip, a second semiconductor chip on the first semiconductor chip, a third semiconductor chip on the second semiconductor chip and a fourth semiconductor chip on the third semiconductor chip, anda first underfill layer between the second semiconductor chip and the first semiconductor chip; a second underfill layer between the third semiconductor chip and the second semiconductor chip, and a third underfill layer between the fourth semiconductor chip and the third semiconductor chip;wherein the second underfill layer comprises a material that is different than the first and third underfill layers.2. The semiconductor package of wherein the first and second semiconductor chips claim 1 , the second and third semiconductor chips and the third and fourth semiconductor chips each have a plurality of corresponding conductive contacts that are in contact with each other claim 1 , respectively.3. The semiconductor package of wherein the conductive contacts of one or more of the first claim 2 , second claim 2 , third and fourth semiconductor chips are connected to through-electrodes that pass from an upper surface of the chip to a lower surface of the chip.4. The semiconductor package ofwherein the first semiconductor ...

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Номер записи: 73
03-04-2014 дата публикации

Semiconductor Device and Method of Using a Standardized Carrier in Semiconductor Packaging

Номер: US20140091455A1
Автор: Lin Yaojioan, Marimuthu Pandi C., Pricolo Damien M., Shim Il Kwon, Strothmann Thomas J., Wirtz Heinz-Peter, Yoon Seung Wook
Принадлежит: STATS CHIPPAC, LTD.

A semiconductor device has a carrier with a fixed size. A plurality of first semiconductor die is singulated from a first semiconductor wafer. The first semiconductor die are disposed over the carrier. The number of first semiconductor die on the carrier is independent from the size and number of first semiconductor die singulated from the first semiconductor wafer. An encapsulant is deposited over and around the first semiconductor die and carrier to form a reconstituted panel. An interconnect structure is formed over the reconstituted panel while leaving the encapsulant devoid of the interconnect structure. The reconstituted panel is singulated through the encapsulant. The first semiconductor die are removed from the carrier. A second semiconductor die with a size different from the size of the first semiconductor die is disposed over the carrier. The fixed size of the carrier is independent of a size of the second semiconductor die. 1. A method of making a semiconductor device , comprising:providing a carrier including a fixed size; anddisposing a plurality of first semiconductor die over the carrier, the fixed size of the carrier independent of a size of the first semiconductor die.2. The method of claim 1 , further including:providing a first semiconductor wafer including the plurality of first semiconductor die; andsingulating the first semiconductor wafer to separate the first semiconductor die, wherein a number of first semiconductor die disposed over the carrier is independent from a number of first semiconductor die singulated from the first semiconductor wafer.3. The method of claim 2 , further including:providing a second semiconductor wafer including a plurality of second semiconductor die;singulating the second semiconductor wafer to separate the second semiconductor die; anddisposing the second semiconductor die over the carrier, wherein a number of second semiconductor die disposed over the carrier is independent from a number of second semiconductor ...

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Номер записи: 74
03-04-2014 дата публикации

ENCAPSULATED WAFER-LEVEL CHIP SCALE (WLSCP) PEDESTAL PACKAGING

Номер: US20140091458A1
Автор: Buenning Hartmut, KAMPHUIS Tonny, van Gemert Leonardus Antonius Elisabeth, Zenz Christian
Принадлежит: NXP B.V.

Consistent with an example embodiment, there is semiconductor device assembled to resist mechanical damage. The semiconductor device comprises an active circuit defined on a top surface, contact areas providing electrical connection to the active circuit. There is a pedestal structure upon which the active circuit is mounted on an opposite bottom surface; the pedestal structure has an area smaller than the area of the active device. An encapsulation, consisting of a molding compound, surrounds the sides and the underside of the active device and it surrounds the contact areas. The encapsulation provides a resilient surface protecting the active device from mechanical damage. A feature of the embodiment is that the contact areas may have solder bumps defined thereon. 1. A method for assembling a wafer level chip scale processed (WLCSP) device having solder bumps defined thereon , the method comprising:defining a pedestal mounting strip per WLCSP device die thickness and surface area, the pedestal mounting strip have a topside and an underside;fabricating the pedestal mounting strip out of a molding compound, the pedestal mounting strip having a grid of pedestals on the topside, each one of the grid pedestals having a surface area smaller than the surface area of the underside of the WLCSP device;die attaching the WLCSP device onto the surface of each one of the grid pedestals, the WLCSP device forming an overhang on each one of the grid pedestals; andencapsulating each one of the WLCSP devices on the pedestal mounting strip, and assuring that the encapsulant surrounds the WLCSP devices and flows under the overhang of each WLCSP device.2. The method as recited in claim 2 , wherein during the fabricating of the pedestal mounting strip claim 2 , a metal shield is attached to the underside.3. The method as recited in further comprising claim 1 ,protecting the solder bumps with a release foil before encapsulating each one the WLCSP devices; andremoving the release foil ...

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Номер записи: 75
03-04-2014 дата публикации

Semiconductor Device and Method of Depositing Encapsulant Along Sides and Surface Edge of Semiconductor Die in Embedded WLCSP

Номер: US20140091482A1
Автор: Lin Yaojian, Marimuthu Pandi C., Wirtz Heinz-Peter, Yoon Seung Wook
Принадлежит: STATS CHIPPAC, LTD.

A semiconductor device has a semiconductor wafer including a plurality of semiconductor die. An insulating layer is formed over the semiconductor wafer. A portion of the insulating layer is removed by LDA to expose a portion of an active surface of the semiconductor die. A first conductive layer is formed over a contact pad on the active surface of the semiconductor die. The semiconductor wafer is singulated to separate the semiconductor die. The semiconductor die is disposed over a carrier with the active surface of the semiconductor die offset from the carrier. An encapsulant is deposited over the semiconductor die and carrier to cover a side of the semiconductor die and the exposed portion of the active surface. An interconnect structure is formed over the first conductive layer. Alternatively, a MUF material is deposited over a side of the semiconductor die and the exposed portion of the active surface. 1. A method of making a semiconductor device , comprising:providing a semiconductor wafer including a plurality of semiconductor die;forming an insulating layer over the semiconductor wafer;removing a portion of the insulating layer to expose a portion of an active surface of the semiconductor die;singulating the semiconductor wafer to separate the semiconductor die; anddepositing an encapsulant over the semiconductor die to cover a side of the semiconductor die and the exposed portion of the active surface of the semiconductor die.2. The method of claim 1 , further including:providing a carrier;disposing the semiconductor die over the carrier with the active surface of the semiconductor die offset from the carrier;depositing the encapsulant over the semiconductor die and carrier to cover the side of the semiconductor die and the exposed portion of the active surface of the semiconductor die; andremoving the carrier.3. The method of claim 1 , further including forming a conductive layer over a contact pad on the active surface of the semiconductor die.4. The ...

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Номер записи: 76
03-04-2014 дата публикации

METHOD OF MANUFACTURING SEMICONDUCTOR APPARATUS AND SEMICONDUCTOR APPARATUS

Номер: US20140091483A1
Автор: AKIBA Hideki, SEKIGUCHI Susumu, SHIOBARA Toshio
Принадлежит: SHIN-ETSU CHEMICAL CO., LTD.

A method of manufacturing a semiconductor apparatus includes: a charging step of charging the thermosetting resin in excess of an amount necessary for forming the sealing layer to fill the inside of the first cavity with the thermosetting resin and discharging an excess of the thermosetting resin from the first cavity; an integrating step of integrating the substrate on which the semiconductor device is mounted, the substrate on which no semiconductor device is mounted and the sealing layer by molding the thermosetting resin while pressurizing the upper mold and the lower mold; and a dicing step of extracting the integrated substrates from the molding mold and dicing the integrated substrates to obtain an individual semiconductor apparatus. 1. A method of manufacturing a semiconductor apparatus with a forming mold having an upper mold and a lower mold comprising:a preparing step of preparing the forming mold having a first cavity for integrating a substrate on which a semiconductor device is mounted, a substrate on which no semiconductor device is mounted, and a sealing layer to be formed of a thermosetting resin between the substrates;an arranging step of heating the first cavity to a temperature ranging from a room temperature to 200° C., disposing the substrate on which the semiconductor device is mounted on one of the upper mold and the lower mold of the forming mold, and disposing the substrate on which no semiconductor device is mounted on the other of the upper mold and the lower mold;a charging step of charging the thermosetting resin in excess of an amount necessary for forming the sealing layer to fill the inside of the first cavity with the thermosetting resin and discharging an excess of the thermosetting resin from the first cavity;an integrating step of integrating the substrate on which the semiconductor device is mounted, the substrate on which no semiconductor device is mounted and the sealing layer by molding the thermosetting resin while ...

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Номер записи: 77
01-01-2015 дата публикации

PACKAGED SEMICONDUCTOR DEVICE

Номер: US20150001691A1
Автор: HIGGINS, III LEO M.
Принадлежит:

A packaged semiconductor device includes a lead frame having a plurality of leads; a semiconductor die mounted onto the lead frame; and an encapsulant surrounding the semiconductor die. At least a portion of each of the leads is surrounded by the encapsulant, wherein, each lead includes a thin portion external to the encapsulant and a thick portion that is surrounded by the encapsulant, wherein the thin portion is thinner than the thick portion. 1. A packaged semiconductor device , comprising:a lead frame having a plurality of leads;a semiconductor die mounted onto the lead frame; andan encapsulant surrounding the semiconductor die, wherein at least a portion of each of the leads is surrounded by the encapsulant, wherein, each lead comprises a thin portion external to the encapsulant and a thick portion that is surrounded by the encapsulant, wherein the thin portion is thinner than the thick portion.2. The packaged semiconductor device of claim 1 , wherein claim 1 , for each lead claim 1 , a knee region of the lead extends external to the encapsulant.3. The packaged semiconductor device of claim 2 , wherein claim 2 , for each lead claim 2 , the knee region comprises the thin portion of the lead.4. The packaged semiconductor device of claim 3 , wherein for each lead claim 3 , the thin portion extends an entire length of the knee region.5. The packaged semiconductor device of claim 2 , wherein claim 2 , for each lead claim 2 , the thin portion is located between the knee region and a foot portion.6. The packaged semiconductor device of claim 1 , wherein for each lead claim 1 , a thickness of the thin portion is approximately 50% of a thickness of the thick portion.7. The packaged semiconductor device of claim 1 , wherein claim 1 , for each lead claim 1 , a thickness of the thin portion is in a range of 50-90% of a thickness of the thick portion.8. A method for forming a packaged semiconductor device claim 1 , comprising:attaching a semiconductor die to a lead frame ...

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Номер записи: 78
01-01-2015 дата публикации

SEMICONDUCTOR MODULE AND SEMICONDUCTOR DEVICE

Номер: US20150001702A1
Автор: Kawauchi Yuki, Kitai Kiyofumi
Принадлежит: Mitsubishi Electric Corporation

To obtain a semiconductor module that can fix itself onto a fixing object while enabling further miniaturization, in addition to alleviating load applied on a molded resin, a semiconductor module includes: a semiconductor element; a placing frame on which the semiconductor element is placed; a control substrate onto which a control component for controlling the semiconductor element is mounted; and a molded resin in which the semiconductor element, the placing frame, and the control substrate are integrally molded. Fixing bases exposed from the molded resin are provided on the control substrate for fixing the semiconductor module onto a chassis. 1. A semiconductor module comprising:a semiconductor element;a placing frame on which the semiconductor element is placed;a control substrate onto which a control component for controlling the semiconductor element is mounted; anda molded resin in which the semiconductor element, the placing frame, and the control substrate are integrally molded, whereina fixing base exposed from the molded resin is provided on the control substrate for fixing the semiconductor module onto a chassis.2. The semiconductor module according to claim 1 , whereinthe fixing bases are provided in plurality at least on one side and another side of the molded resin and are exposed from the molded resin.3. The semiconductor module according to claim 1 , whereina threaded hole is formed through the fixing base.4. The semiconductor module according to claim 1 , whereinthe semiconductor element is a wide-bandgap semiconductor element.5. The semiconductor module according to claim 1 , whereinthe placing frame is arranged on an opposite surface side of a surface of the control substrate onto which the control component is mounted, whereina solid pattern is formed on the opposite surface of a surface of the control substrate onto which the control component is mounted.6. The semiconductor module according to claim 5 , whereinthe solid pattern is connected to ...

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Номер записи: 79
06-01-2022 дата публикации

Module, terminal assembly, and method for producing module

Номер: US20220007499A1
Автор: Kazushige Sato, Kazuya Okamoto, Masayoshi Takagi, Takashi Haga
Принадлежит: Murata Manufacturing Co Ltd

A module according to the present disclosure includes a circuit board, an electronic component on one of two principal surfaces of the circuit board, a connection conductor on the principal surface of the circuit board, and sealing resin on the principal surface of the circuit board. The electronic component and the connection conductor are covered with the sealing resin. The connection conductor includes a plate-shaped conductor and terminal sections. The plate-shaped conductor is disposed upright on the principal surface of the circuit board. The terminal sections extend from the plate-shaped conductor and away from the principal surface of the circuit board and are arranged side by side. Tip portions of the terminal sections are exposed at a surface of the sealing resin.

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Номер записи: 80
07-01-2021 дата публикации

Semiconductor Package and Method

Номер: US20210005554A1
Автор: Hao-Yi Tsai, Hsiu-Jen Lin, Ming Hung TSENG, Tin-Hao Kuo, Tsung-Hsien Chiang, Tzu-Sung Huang, Yen-Liang Lin
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

In an embodiment, a device includes: a back-side redistribution structure including: a metallization pattern on a first dielectric layer; and a second dielectric layer on the metallization pattern; a through via extending through the first dielectric layer to contact the metallization pattern; an integrated circuit die adjacent the through via on the first dielectric layer; a molding compound on the first dielectric layer, the molding compound encapsulating the through via and the integrated circuit die; a conductive connector extending through the second dielectric layer to contact the metallization pattern, the conductive connector being electrically connected to the through via; and an intermetallic compound at the interface of the conductive connector and the metallization pattern, the intermetallic compound extending only partially into the metallization pattern.

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Номер записи: 81
02-01-2020 дата публикации

MODULE

Номер: US20200006172A1
Автор: OTSUBO Yoshihito
Принадлежит:

A module with a high degree of design flexibility and excellent radiation characteristics is provided. The module includes a multilayer wiring substrate, mounting components mounted on an upper surface of the multilayer wiring substrate, a sealing resin layer sealing the mounting components, a plurality of depressions in an upper surface of the sealing resin layer, and radiators set in the depressions. The mounting components are components whose amounts of heat generated are smaller than those of the mounting components. A gap between a bottom of each of the depressions arranged in a region overlapping each of the mounting components and the mounting component is shorter than a gap between the bottom of each of the depressions arranged in a region overlapping each of the mounting components and the mounting component as seen from a direction perpendicular to the upper surface of the multilayer wiring substrate. 1. A module comprising:a wiring substrate;a first component and a second component mounted on a principal surface of the wiring substrate;a sealing resin layer having a contact surface in contact with the wiring substrate and an opposed surface opposed to the contact surface, the sealing resin layer sealing the first component and the second component;at least two depressions at the opposed surface of the sealing resin layer; anda radiating member set in each of the depressions, each radiating member including at least one radiator element,wherein an amount of heat generated from the second component is smaller than an amount of heat generated from the first component,the radiating member has a first region overlapping the first component and a second region overlapping the second component as seen from a direction perpendicular to the principal surface of the wiring substrate,the depressions reach neither the first component nor the second component, anda distance from a bottom of the depression in the first region to the first component is shorter than a ...

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Номер записи: 82
02-01-2020 дата публикации

Integrated Circuit Package and Method of Forming Same

Номер: US20200006173A1
Автор: Chen Hsien-Wei, Chen Ming-Fa, Yu Chen-Hua
Принадлежит:

A package and a method of forming the same are provided. The package includes: a die stack bonded to a carrier, the die stack including a first integrated circuit die, the first integrated circuit die being a farthest integrated circuit die of the die stack from the carrier, a front side of the first integrated circuit die facing the carrier; a die structure bonded to the die stack, the die structure including a second integrated circuit die, a backside of the first integrated circuit die being in physical contact with a backside of the second integrated circuit die, the backside of the first integrated circuit die being opposite the front side of the first integrated circuit die; a heat dissipation structure bonded to the die structure adjacent the die stack; and an encapsulant extending along sidewalls of the die stack and sidewalls of the heat dissipation structure. 1. A method comprising:forming a first encapsulated integrated circuit die over a carrier;forming a second encapsulated integrated circuit die over the first encapsulated integrated circuit die;bonding a third encapsulated integrated circuit die to the second encapsulated integrated circuit die;bonding a first dummy die to the third encapsulated integrated circuit die, the first dummy die and the second encapsulated integrated circuit die being on a same side of the third encapsulated integrated circuit die; andencapsulating the carrier, the first encapsulated integrated circuit die, the second encapsulated integrated circuit die, and the first dummy die in a first encapsulant.2. The method of claim 1 , wherein the first dummy die is configured as a heat dissipation structure.3. The method of claim 1 , wherein an exposed surface of the carrier is substantially level with an exposed surface of the first encapsulant.4. The method of claim 1 , wherein an exposed surface of the carrier is substantially level with an exposed surface of the first dummy die.5. The method of claim 1 , wherein a width of the ...

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Номер записи: 83
07-01-2021 дата публикации

MAGNETICALLY COUPLED GALVANICALLY ISOLATED COMMUNICATION USING LEAD FRAME

Номер: US20210006167A1
Автор: Balakrishnan Balu, Matthews David Michael Hugh
Принадлежит: POWER INTEGRATIONS, INC.

An integrated circuit package includes a lead frame and an encapsulation that substantially encloses the lead frame. The lead frame further includes a first conductor comprising a first conductive loop and a second conductor galvanically isolated from the first conductor, proximate to and magnetically coupled to the first conductive loop to provide a communication link between the first and second conductor. The second conductor includes a first conductive portion, a second conductive portion, and a wire coupling together the first conductive portion and the second conductive portion. 1. An integrated circuit package , comprising:an encapsulation; and a first conductive loop disposed substantially within the encapsulation;', 'a second conductive loop disposed substantially within the encapsulation and substantially all of the second conductive loop is outside of the first conductive loop; and', 'wherein the first and second conductive loops are configured to form a magnetically coupled communication link.', 'a galvanic isolator coupled to the first conductive loop such that there is galvanic isolation between the first and the second conductive loops,'}], 'a lead frame, a portion of the lead frame disposed within the encapsulation, the lead frame comprising2. The integrated circuit package of claim 1 , further comprising:a first circuit coupled to the first conductive loop; and wherein one of the first and second circuits is configured to control properties of a transmitter current to produce a changing magnetic field in proximity to a corresponding one of the first and second conductive loops, thereby inducing a voltage that is generated across an other one of the first and second conductive loops that is subjected to the changing magnetic field and results in a current flow in the other one of the inner and outer conductive loops, and', 'wherein the other one of the first and second circuits is configured to receive an electrical parameter induced by the one of ...

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Номер записи: 84
08-01-2015 дата публикации

Method and Structure of Packaging Semiconductor Devices

Номер: US20150008583A1
Автор: Gerber Mark A.
Принадлежит:

A method for fabricating packaged semiconductor devices; attaching a batch-sized metallic grid with openings onto an adhesive tape having an insulating clear core covered by a layer of UV-releasable adhesive, the openings sized larger than a semiconductor chip; attaching a semiconductor chip onto the tape of each window, the chip terminals facing the adhesive surface; laminating insulating material of low coefficient of thermal expansion to fill gaps between each chip and respective grid; turning over assembly to place a carrier under backside of chips and lamination and to remove the tape; plasma-cleaning the assembly front side and sputtering uniform at least one metal layer across the assembly; optionally plating metal layers; and patterning the metal layers to form rerouting traces and extended contact pads for assembly. 1. A method for fabricating packaged semiconductor devices , comprising:providing a flat carrier sheet secured in a frame to restrain warpage, the carrier having an insulating core of clear laminate material and a surface covered by a layer of a UV-releasable adhesive, the frame having lateral dimensions comparable to a semiconductor wafer;attaching the surface of a metallic window frame onto the adhesive panel surface, the frame including a plurality of rectangular windows bordered by a metal grid and sized larger than a semiconductor chip;attaching a plurality of semiconductor chips to the adhesive carrier surfaces in respective windows, the chip terminals facing the adhesive surface;compression-molding a compliant insulating material to cohesively fill gaps between chips and grid sidewalls, the material having a coefficient of thermal expansion approaching the coefficient of the semiconductor chips, thereby creating an assembly;using UV irradiation, separating the carrier sheet and frame from the assembly, thereby exposing the surfaces of the chips with terminals and the grid metals;plasma-cleaning the carrier and attached chips uniformly in ...

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Номер записи: 85
09-01-2020 дата публикации

Electronic device and connection body

Номер: US20200011904A1
Автор: Soichiro UMEDA, Yuji MORINAGA
Принадлежит: Shindengen Electric Manufacturing Co Ltd

An electronic device has a sealing part 90 , a first main terminal 11 protruding outward from the sealing part 90 , a second main terminal 12 protruding outwardly from the sealing part, an electronic element 95 provided in the sealing part and having a front surface electrically connected to the first main terminal 11 and a back surface electrically connected to the second main terminal 12 , a head part 40 connected to the front surface of the electronic element 95 , a sensing terminal 13 protruding to an outside from the sealing part 90 and used for sensing and a connection part 35 integrally formed with the head part 40 and electrically connected to the sensing terminal 13 . A current flowing through the sensing terminal 13 and the connection part 35 among a sensing current path does not overlap a main current path flowing through the second main terminal 12 , the electronic element 95 and the first main terminal 11.

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Номер записи: 86
14-01-2016 дата публикации

SUBSTRATE STRUCTURE AND DEVICE EMPLOYING THE SAME

Номер: US20160013111A1
Автор: Chuang Kun-Lin, Wei Hsiao-Fen
Принадлежит: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE

A substrate structure and a device employing the same are disclosed. An embodiment of the disclosure provides the substrate structure including a flexible substrate and a first barrier layer. The flexible substrate has a top surface, a side surface, and a bottom surface. The first barrier layer is disposed on and contacting the top surface of the flexible substrate, wherein the first barrier layer consists of Si, N, and Z atoms, wherein the Z atom is selected from a group of H, C, and 0 atoms, and wherein Si of the first barrier layer is present in an amount from 35 to 42 atom %, N of the first barrier layer is present in an amount from 10 to 52 atom %, and Z of the first barrier layer is present in an amount from 6 to 48 atom %. 1. A substrate structure , comprising:a flexible substrate having a top surface, a side surface, and a bottom surface; anda first barrier layer disposed on and contacting the top surface of the flexible substrate, wherein the first barrier layer consists of Si, N, and Z atoms, wherein the Z atom is selected from a group of H, C, and O atoms, and wherein Si of the first barrier layer is present in an amount from 35 to 42 atom %, N of the first barrier layer is present in an amount from 10 to 52 atom %, and Z of the first barrier layer is present in an amount from 6 to 48 atom %.2. The substrate structure as claimed in claim 1 , wherein an adhesion strength between the flexible substrate and the first barrier layer is 5B measured according to ASTM D3330.3. The substrate structure as claimed in claim 1 , wherein the first barrier layer exhibits a water vapor transmission rate (WVTR) of less than 0.1 g/mday claim 1 , as determined by ASTM F1249-06 at 60° C. and 90% RH.4. The substrate structure as claimed in claim 1 , wherein the first barrier layer has a thickness between 30 nm and 10 μm.5. The substrate structure as claimed in claim 1 , wherein the first barrier layer has a visible light transmittance equal to or more than 80%.6. The ...

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Номер записи: 87
15-01-2015 дата публикации

MICROELECTRONIC ASSEMBLIES WITH STACK TERMINALS COUPLED BY CONNECTORS EXTENDING THROUGH ENCAPSULATION

Номер: US20150014847A1
Автор: Haba Belgacem, Mohammed Ilyas
Принадлежит:

A microelectronic assembly or package can include first and second support elements and a microelectronic element between inwardly facing surfaces of the support elements. First connectors and second connectors such as solder balls, metal posts, stud bumps, or the like face inwardly from the respective support elements and are aligned with and electrically coupled with one another in columns. An encapsulation separates respective pairs of coupled first and second connectors from one another and may encapsulate the microelectronic element and fill spaces between the support elements. The first connectors, the second connectors or both may be partially encapsulated prior to electrically coupling respective pairs of first and second connectors in columns. 1. A microelectronic assembly , comprising:first and second support elements each having first and second oppositely facing surfaces;a microelectronic element mounted to the second surface of a support element of the first and second support elements;electrically conductive first connectors projecting above the second surface of the first support element;electrically conductive second connectors projecting above the second surface of the second support element and coupled to ends of the first connectors; andmonolithic first encapsulation formed in contact with the second surface of a support element of the first and second support elements, and being formed in contact with at least one of: the second surface of another support element of the first and second support elements; or a monolithic second encapsulation formed in contact with the second surface of the another support element,wherein first package terminals at the first surface of the first support element are electrically coupled with corresponding second package terminals at the first surface of the second support element through pairs of said first connectors aligned with and joined with said second connectors, andat least one of: the first connectors and ...

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Номер записи: 88
15-01-2015 дата публикации

MICROELECTRONIC ASSEMBLIES HAVING REINFORCING COLLARS ON CONNECTORS EXTENDING THROUGH ENCAPSULATION

Номер: US20150014856A1
Автор: Haba Belgacem, Mohammed Ilyas
Принадлежит:

A microelectronic assembly or package can include first and second support elements and a microelectronic element between inwardly facing surfaces of the support elements. First connectors and second connectors such as solder balls, metal posts, stud bumps, or the like face inwardly from the respective support elements and are aligned with and electrically coupled with one another in columns. Dielectric reinforcing collars are provided on outer surfaces of the first connectors, second connectors or both, and an encapsulation separates pairs of coupled connectors from one another and may fill spaces between support elements. 1. A microelectronic assembly , comprising:first and second support elements each having first and second oppositely facing surfaces;a microelectronic element mounted to the second surface of a support element of the first and second support elements;electrically conductive first connectors projecting above the second surface of the first support element;electrically conductive second connectors projecting above the second surface of the second support element and coupled to ends of the first connectors;dielectric reinforcing collars surrounding portions of at least some of one or more of: the first connectors, or the second connectors, the dielectric collars configured to substantially prevent collapse of the connectors reinforced thereby when the connectors reinforced thereby are joined with other connectors in forming the assembly, such that the assembly has increased height, and connections between the first and second support elements have increased aspect ratio; anda first encapsulation overlying surfaces of the reinforcing collars, the first encapsulation being formed in contact with at least one of: the second surface of at least one of the first or second support elements; or a second encapsulation formed in contact with the second surface of the another support element,the microelectronic assembly having terminals at the first surface ...

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Номер записи: 89
15-01-2015 дата публикации

SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME

Номер: US20150014864A1
Автор: Chen Wan-Ting, Lai Yi-Che, Lin Chun-Tang
Принадлежит: SILICONWARE PRECISION INDUSTRIES CO., LTD.

The present invention provides a semiconductor package and a method of fabricating the same. The semiconductor package includes a substrate, a package unit mounted on and electrically connected to the substrate, and a second encapsulant formed on the substrate and encapsulating the package unit. The package unit includes an interposer, a semiconductor chip mounted on the interposer in a flip-chip manner, and a first encapsulant formed on the interposer and encapsulating the semiconductor chip. The present invention reduces the fabricating time and increases the yield of the final product.

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Номер записи: 90
03-02-2022 дата публикации

METAL MEMBER AND MANUFACTURING METHOD FOR METAL MEMBER

Номер: US20220032399A1
Автор: Furukawa Masashi, NAKATA Hiromichi, UCHIMURA Masahiro
Принадлежит: TOYOTA JIDOSHA KABUSHIKI KAISHA

A manufacturing method for a metal member includes irradiating a first region of a surface of the base material, the surface having at least any one of Cu, Al, Sn, Ti, and Fe, as a main component, with a laser beam to melt the first region; generating metal particles from a vapor or plasma of a metal released to a predetermined atmosphere by melting the surface of the base material in the first region, and depositing the metal particles in the first region; irradiating a second region adjacent to the first region with a laser beam to melt the second region; and generating metal particles from a vapor or plasma of a metal released to a predetermined atmosphere by melting the surface of the base material in the second region, and depositing the metal particles in each of the first region and the second region. 1. A manufacturing method for a metal member that includes a base material of which at least a surface is made of a material containing at least any one of Cu , Al , Sn , Ti , and Fe , as a main component , and an uneven portion having an uneven shape , which is formed on the surface of the base material , the manufacturing method comprising forming the uneven portion , irradiating a first region of the surface of the base material with a pulse-oscillating laser beam to melt the surface of the base material in the first region,', 'generating metal particles from a vapor or plasma of a metal released to a predetermined atmosphere by melting the surface of the base material in the first region, and depositing the metal particles in the first region,', 'irradiating a second region of the surface of the base material with the pulse-oscillating laser beam, the second region being adjacent to the first region, to melt the surface of the base material in the second region, and', 'generating metal particles from a vapor or plasma of a metal released to the predetermined atmosphere by melting the surface of the base material in the second region, and depositing the metal ...

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Номер записи: 91
17-01-2019 дата публикации

Fan-out semiconductor package

Номер: US20190019757A1
Автор: Chang Bae Lee, Ji Hyun Lee, Jin Gu Kim, Jin Su Kim
Принадлежит: Samsung Electro Mechanics Co Ltd

A fan-out semiconductor package includes: a semiconductor chip; an encapsulant encapsulating at least portions of the semiconductor chip; and a first connection member disposed on the semiconductor chip and including a first redistribution layer electrically connected to the connection pads and a second redistribution layer electrically connected to the connection pads and disposed on the first redistribution layer. The first redistribution layer includes a first pattern having a plurality of degassing holes, the second redistribution layer includes a second pattern having a first line portion having a first line width and a second line portion connected to the first line portion and having a second line width greater than the first line width, and the second line portion overlaps at least one of the plurality of degassing holes when being projected in a direction perpendicular to the active surface.

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Номер записи: 92
16-01-2020 дата публикации

THERMALLY CONDUCTIVE AND PROTECTIVE COATING FOR ELECTRONIC DEVICE

Номер: US20200019750A1
Автор: Troccoli Matias N., Xiao Tian
Принадлежит: NEXT BIOMETRICS GROUP ASA

A protective coating layer, an electronic device including such a protective coating layer, and the methods of making the same are provided. The electronic device includes a substrate, a thin film circuit layer disposed over the substrate, and a protective coating layer disposed over the thin film circuit layer. The protective coating layer includes a first coating and a second coating disposed over the first coating. Each coating has a cross-plane thermal conductivity in a direction normal to a respective coating surface equal to or higher than 0.5 W/(m*K). The first coating and the second coating have different crystal structures, or different crystalline orientations, or different compositions, or a combination thereof to provide different nanoindentation hardness. The first coating has a hardness lower than that of the second coating. 1. An electronic device , comprising:a substrate;a thin film circuit layer disposed over the substrate; and a first coating; and', 'a second coating disposed over the first coating, wherein', 'each of the first coating and the second coating has a cross-plane thermal conductivity in a direction normal to a respective coating surface equal to or higher than 0.5 W/(m*K),', 'the first coating and the second coating have different crystal structures, or different crystalline orientations, or different compositions, or a combination thereof to provide different hardness measured using nanoindentation, and', 'the first coating has a hardness lower than that of the second coating., 'a protective coating layer disposed over the thin film circuit layer, the protective coating layer comprising2. The electronic device of claim 1 , wherein each of the first coating and the second coating is made a material selected from the group consisting of diamond-like carbon (DLC) claim 1 , silicon nitride claim 1 , silicon oxynitride claim 1 , boron nitride claim 1 , boron oxynitride claim 1 , aluminum nitride claim 1 , aluminum oxynitride claim 1 , ...

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Номер записи: 93
16-01-2020 дата публикации

SEMICONDUCTOR DEVICE

Номер: US20200020669A1
Автор: AMANO Ayana, Hayakawa Ken, Ikebe Reishuku, Sugo Yuki, Uchida Yuki, Watanabe Takeshi
Принадлежит: Toshiba Memory Corporation

A semiconductor device according to an embodiment comprises a substrate and a first semiconductor chip provided above the substrate. A second semiconductor chip is provided above the first semiconductor chip. A spacer chip is provided between the first semiconductor chip and the second semiconductor chip with regard to a direction orthogonal to a mount surface of the substrate, the spacer chip being made of a first resin material. A first adhesive material is provided between the spacer chip and the substrate or the first semiconductor chip. A second adhesive material is provided between the spacer chip and the second semiconductor chip. A second resin material covers the first and second semiconductor chips and the spacer chip. 1. A semiconductor device comprising:a substrate;a first semiconductor chip provided above the substrate;a second semiconductor chip provided above the first semiconductor chip;a spacer chip provided between the first semiconductor chip and the second semiconductor chip with regard to a direction orthogonal to a mount surface of the substrate, the spacer chip being made of a first resin material;a first adhesive material provided between the spacer chip and the substrate or the first semiconductor chip;a second adhesive material provided between the spacer chip and the second semiconductor chip; anda second resin material covering the first and second semiconductor chips and the spacer chip.2. The device of claim 1 , wherein the first resin material is a same material as the second resin material.3. The device of claim 1 , further comprising a plurality of first supporting pillars provided between the spacer chip and the substrate and made of the first resin material.4. The device of claim 3 , further comprising a second supporting pillar provided between the spacer chip and the first semiconductor chip and made of the first resin material.5. The device of claim 4 , wherein the second supporting pillar and the second resin material are ...

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Номер записи: 94
21-01-2021 дата публикации

INTEGRATED FAN-OUT PACKAGE

Номер: US20210020575A1
Автор: Hu Yu-Hsiang, Kuo Hung-Jui, LIAO SIH-HAO, Tu Meng-Che
Принадлежит: Taiwan Semiconductor Manufacturing Co., Ltd.

An integrated fan-out (InFO) package includes a first redistribution structure, a die, an encapsulant, a plurality of through insulating vias (TIV), a plurality of dipole antennas, and a second redistribution structure. The die is disposed on the first redistribution structure. The encapsulant encapsulates the die. The TIVs and the dipole antennas are embedded in the encapsulant. Each dipole antenna includes a pair of antenna elements. Each antenna element has a first folded-sidewall and a second folded-sidewall opposite to the first folded-sidewall. A portion of each second folded-sidewall in the pair of antenna elements face each other. Each first folded-sidewall includes at least three sub-sidewalls connected to each other. The adjacent sub-sidewalls form an obtuse angle. The second redistribution structure is disposed on the die, the TIVs, the dipole antennas, and the encapsulant. 1. An integrated fan-out (InFO) package , comprising:a first redistribution structure;a die disposed on the first redistribution structure;an encapsulant encapsulating the die;a plurality of through insulating vias (TIV) and a plurality of dipole antennas embedded in the encapsulant, wherein each dipole antenna comprises a pair of antenna elements, each antenna element has a first folded-sidewall and a second folded-sidewall opposite to the first folded-sidewall, a portion of each second folded-sidewall in the pair of antenna elements face each other, each first folded-sidewall comprises at least three sub-sidewalls connected to each other, and the adjacent sub-sidewalls form an obtuse angle; anda second redistribution structure disposed on the die, the plurality of TIVs, the plurality of dipole antennas, and the encapsulant.2. The InFO package according to claim 1 , further comprising:an insulating layer disposed on the first redistribution structure opposite to the die; anda plurality of conductive patches on the insulating layer.3. The InFO package according to claim 1 , further ...

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Номер записи: 95
21-01-2021 дата публикации

SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF

Номер: US20210020581A1
Автор: Hsieh Ching-Hua, Kuan Hsaing-Pin, Lan Chun-Yen, Lin Chih-Wei, Lin Chun-Cheng, LIN Yu-Wei
Принадлежит: Taiwan Semiconductor Manufacturing Co., Ltd.

A semiconductor structure and a manufacturing method thereof are provided. A semiconductor structure includes a first semiconductor die, an insulating encapsulation laterally encapsulating the first semiconductor die, an electromagnetic shielding structure enclosing the first semiconductor die and a first portion of the insulating encapsulation, and a redistribution structure. The electromagnetic shielding structure includes a first conductive layer and a dielectric frame laterally covering the first conductive layer. The first conductive layer surrounds the first portion of the insulating encapsulation and extends to cover a first side of the first semiconductor die. The dielectric frame includes a first surface substantially leveled with the first conductive layer. The redistribution structure is disposed on a second side of the first semiconductor die opposing to the first side, and the redistribution structure is electrically coupled to the first semiconductor die and the first conductive layer of the electromagnetic shielding structure. 1. A semiconductor structure , comprising:a first semiconductor die;an insulating encapsulation laterally encapsulating the first semiconductor die; a first conductive layer surrounding the first portion of the insulating encapsulation and extending to cover a first side of the first semiconductor die; and', 'a dielectric frame laterally covering the first conductive layer and comprising a first surface substantially leveled with the first conductive layer; and, 'an electromagnetic shielding structure enclosing the first semiconductor die and a first portion of the insulating encapsulation, the electromagnetic shielding structure comprisinga redistribution structure disposed on a second side of the first semiconductor die opposing to the first side, and the redistribution structure electrically coupled to the first semiconductor die and the first conductive layer of the electromagnetic shielding structure.2. The semiconductor ...

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Номер записи: 96
21-01-2021 дата публикации

CHIP PACKAGE AND METHOD OF FORMING THE SAME

Номер: US20210020607A1
Автор: Chiang Kai-Ming, Hsieh Ching-Hua, Kuan Hsaing-Pin, Lan Chun-Yen, Lin Chih-Wei, Lin Ching-Yao
Принадлежит: Taiwan Semiconductor Manufacturing Co., Ltd.

A chip package including a first semiconductor die, conductive pillars, a dielectric structure, a second semiconductor die and insulating encapsulant is provided. The first semiconductor die includes a top surface having a first region and a second region. The conductive pillars are disposed over the second region of the first semiconductor die. The dielectric structure includes a first support portion disposed on the first region of the semiconductor die, and a second support portion physically separated from the first semiconductor die. The second semiconductor die is stacked over the first support portion and the second support portion, and is electrically connected to the first semiconductor die through the conductive pillars. The insulating encapsulant encapsulates the first semiconductor die, the second semiconductor die, the dielectric structure and the conductive pillars. 1. A chip package , comprising:a first semiconductor die comprising a top surface having a first region and a second region;conductive pillars disposed over the second region of the first semiconductor die;a dielectric structure comprising a first support portion and a second support portion, the first support portion being disposed on the first region of the first semiconductor die, and the second support portion being physically separated from the first semiconductor die;a second semiconductor die stacked over the first support portion and the second support portion, and the second semiconductor being electrically connected to the first semiconductor die through the conductive pillars; andan insulating encapsulant encapsulating the first semiconductor die, the second semiconductor die, the dielectric structure and the conductive pillars.2. The chip package according to claim 1 , wherein the first semiconductor die and the second support portion are spaced apart by a portion of the insulating encapsulant claim 1 , and a portion of a bottom surface of the second semiconductor die contacts ...

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Номер записи: 97
16-01-2020 дата публикации

RADIO-FREQUENCY MODULE

Номер: US20200022250A1
Автор: OTSUBO Yoshihito
Принадлежит:

A radio-frequency module includes a multilayer circuit board, a plurality of components mounted on a top surface of the multilayer circuit board, a sealing resin layer laminated on the top surface of the multilayer circuit board and sealing a plurality of components, and a shield wall disposed in a groove formed in the sealing resin layer between the component and the component. The shield wall has a region that overlaps the component when viewed in a direction perpendicular to the top surface of the multilayer circuit board. The groove in the overlapped region is formed with a depth that does not reach the component. In the component, a terminal electrode that covers the entire surfaces of side surfaces, and part of a top surface, a bottom surface, and side surfaces is formed. 1. A radio-frequency module comprising:a circuit board;a first component, a second component, and a third component, wherein the first component, the second component, and the third component are mounted on a main surface of the circuit board;a sealing resin layer laminated on the main surface of the circuit board, the sealing resin layer sealing the first component, the second component, and the third component; anda shield wall disposed in a groove provided in the sealing resin layer, whereinthe groove has a first region disposed between the first component and the second component and a second region overlapping the third component, when viewed in a direction perpendicular to the main surface of the circuit board,a portion of the groove in the second region is provided with a depth not reaching the third component,the third component has a first surface facing the main surface of the circuit board, a second surface opposed to the first surface, and a side surface connecting the first surface and the second surface,one electrode is provided on the side surface of the third component, andthe one electrode of the third component and the shield wall are connected to a ground.2. The radio- ...

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Номер записи: 98
28-01-2016 дата публикации

PACKAGE STRUCTURE AND METHOD FOR FABRICATING THE SAME

Номер: US20160027740A1
Автор: Chang Cho-Hsin, Chen Chia-Yang, Chiu Chih-Hsien, Chung Hsin-Lung, Yang Chao-Ya
Принадлежит:

A package structure includes a carrier, an electronic component disposed on the carrier, an encapsulant formed on the carrier for encapsulating the electronic component, a first shielding layer formed on the encapsulant, and a second shielding layer formed on the first shielding layer. The first and second shielding layers are made of different materials. With the multiple shielding layers formed on the encapsulating layer, the electronic component is protected from electromagnetic interferences. The present invention also provides a method for fabricating the package structure. 1. A package structure , comprising:a carrier;at least one electronic component disposed on the carrier;an encapsulant formed on the carrier for encapsulating the electronic component;a first shielding layer formed on the encapsulant; andat least one second shielding layer formed on the first shielding layer,wherein the first shielding layer and the at least one second shielding layer are made of different materials, and the at least one second shielding layer is in direct contact with the first shielding layer.2. The package structure of claim 1 , wherein the electronic component is a radio frequency chip.3. The package structure of claim 1 , wherein the first shielding layer is made of an insulative material or a conductive material.4. The package structure of claim 1 , wherein the at least one second shielding layer is made of a conductive material.5. The package structure of claim 1 , wherein the first shielding layer is further formed on the carrier.6. The package structure of claim 1 , wherein the carrier has a step-like periphery.7. The package structure of claim 6 , wherein the first shielding layer further covers the step-like periphery claim 6 , the first shielding layer has a step-like portion corresponding to the step-like periphery claim 6 , and the second shielding layer covers a side surface of the carrier.8. The package structure of claim 6 , wherein the first shielding layer ...

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Номер записи: 99
10-02-2022 дата публикации

THERMALLY CONDUCTIVE AND PROTECTIVE COATING FOR ELECTRONIC DEVICE

Номер: US20220044000A1
Автор: Troccoli Matias N., Xiao Tian
Принадлежит: NEXT BIOMETRICS GROUP ASA

A protective coating layer, an electronic device including such a protective coating layer, and the methods of making the same are provided. The electronic device includes a substrate, a thin film circuit layer disposed over the substrate, and a protective coating layer disposed over the thin film circuit layer. The protective coating layer includes a first coating and a second coating disposed over the first coating. Each coating has a cross-plane thermal conductivity in a direction normal to a respective coating surface equal to or higher than 0.5 W/(m*K). The first coating and the second coating have different crystal or amorphous structures, different crystalline orientations, different compositions, or a combination thereof to provide different nanoindentation hardness. The first coating has a hardness lower than that of the second coating. 1. An electronic device , comprising:a substratea thin film circuit layer disposed over the substrate; and a first coating; and', wherein', 'the first coating and the second coating are thermally conductive, each of the first coating and second coating has a cross-plane thermal conductivity in a direction normal to a respective coating surface-equal to or higher than 0.5 W/(m*K),', 'the first coating and the second coating are each made of a material comprising substantially same chemical element or elements but having different crystal or amorphous structures, different crystalline orientations, or a combination thereof, and', 'the first coating has a hardness lower than that of the second coating., 'a second coating disposed over the first coating,'}], 'a protective coating layer disposed over the thin film circuit layer, the protective coating layer comprising2. The electronic device of claim 1 , wherein the material for the first coating and the second coating is selected from the group consisting of diamond like carbon (DLC) claim 1 , silicon nitride claim 1 , silicon oxynitride claim 1 , boron nitride claim 1 , boron ...

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Номер записи: 100