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Небесная энциклопедия

Космические корабли и станции, автоматические КА и методы их проектирования, бортовые комплексы управления, системы и средства жизнеобеспечения, особенности технологии производства ракетно-космических систем

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Мониторинг СМИ

Мониторинг СМИ и социальных сетей. Сканирование интернета, новостных сайтов, специализированных контентных площадок на базе мессенджеров. Гибкие настройки фильтров и первоначальных источников.

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Применить Всего найдено 30671. Отображено 100.

05-01-2012 дата публикации

Active energy ray-curable pressure-sensitive adhesive for re-release and dicing die-bonding film

Номер: US20120003470A1

Автор: Chie Kitano, Hironao OTAKE, Katsuhiko Kamiya, Masatsugu KOSO, Mika Okada, Shuhei Murata, Takeshi Matsumura, Tomokazu Takahashi

Принадлежит: Nitto Denko Corp

Provided is an active energy ray-curable pressure-sensitive adhesive for re-release, which has a small influence on an environment or a human body, can be easily handled, can largely change its pressure-sensitive adhesiveness before and after irradiation with an active energy ray, and can express high pressure-sensitive adhesiveness before the irradiation with the active energy ray and express high releasability after the irradiation with the active energy ray. The active energy ray-curable pressure-sensitive adhesive for re-release includes an active energy ray-curable polymer (P), in which the polymer (P) includes one of a polymer obtained by causing a carboxyl group-containing polymer (P3) and an oxazoline group-containing monomer (m3) to react with each other, and a polymer obtained by causing an oxazoline group-containing polymer (P4) and a carboxyl group-containing monomer (m2) to react with each other.

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Номер записи: 1

12-01-2012 дата публикации

Method for molecular adhesion bonding with compensation for radial misalignment

Номер: US20120006463A1

Автор: Gweltaz Gaudin

Принадлежит: Soitec SA

A method for bonding a first wafer on a second wafer by molecular adhesion, where the wafers have an initial radial misalignment between them. The method includes bringing the two wafers into contact so as to initiate the propagation of a bonding wave between the two wafers while a predefined bonding curvature is imposed on at least one of the two wafers during the contacting step as a function of the initial radial misalignment.

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Номер записи: 2

12-01-2012 дата публикации

Power semiconductor module and fabrication method

Номер: US20120009733A1

Автор: Eladio Clemente Delgado, Ernest Wayne Balch, Kevin Matthew Durocher, Paul Alan McConnelee, Raymond Albert Fillion, Richard Alfred Beaupre, Stephen Daley Arthur

Принадлежит: General Electric Co

A power semiconductor module includes: an interconnect layer including an electrical conductor patterned on a dielectric layer, the electrical conductor including a power coupling portion having a thickness sufficient to carry power currents and a control coupling portion having a thickness thinner than that of the power coupling portion; and a semiconductor power device physically coupled to the interconnect layer and electrically coupled to the power coupling portion of the electrical conductor.

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Номер записи: 3

19-01-2012 дата публикации

Conductive Sidewall for Microbumps

Номер: US20120012998A1

Автор: Arvind Chandrasekaran, Christine S. Hay-Riege, Shiqun Gu

Принадлежит: Qualcomm Inc

Electromigration in microbump connections causes voids in the microbumps, which reduces the lifetime of an integrated circuit containing the microbump. Electromigration lifetime may be increased in microbumps by forming a copper shell around the solder. The copper shell of one microbump contacts the copper shell of a second microbump to enclose the solder of the microbump connection. The copper shell allows higher current densities through the microbump. Thus, smaller microbumps may be manufactured on a smaller pitch without suffering failure from electromigration. Additionally, the copper shell reduces shorting or bridging between microbump connections on a substrate.

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Номер записи: 4

26-01-2012 дата публикации

Stack package and method for manufacturing the same

Номер: US20120018879A1

Автор: Cheol-Ho JOH, Eun-Hye DO, Hee-Min SHIN, Ji-Eun Kim, Kyu-Won Lee

Принадлежит: Hynix Semiconductor Inc

A stack package includes a cover film, a first package having a first semiconductor chip which is attached to the cover film, a first adhesive member which is formed to seal the first semiconductor chip and a surface of the cover film, and a first circuit pattern which is disposed over the first adhesive member and electrically connected with the first semiconductor chip; a second package disposed over the first package, having a second semiconductor chip which is electrically connected with the first circuit pattern, a second adhesive member which is formed to seal the second semiconductor chip, and a second circuit pattern which is formed over the second adhesive member, and a via formed to pass through the second circuit pattern and the second adhesive member and to be electrically connected with the first circuit pattern and the second circuit pattern.

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Номер записи: 5

02-02-2012 дата публикации

Process for electrodeposition of copper chip to chip, chip to wafer and wafer to wafer interconnects in through-silicon vias (tsv) with heated substrate and cooled electrolyte

Номер: US20120024713A1

Автор: Robert F. Preisser

Принадлежит: Individual

Process of electrodepositing a metal in a high aspect ratio via in a silicon substrate to form a through-silicon-via (TSV), utilizing an electrolytic bath including a redox mediator, in an electrolytic metal plating system including a chuck adapted to hold the silicon substrate and to heat the silicon substrate to a first temperature, a temperature control device to maintain temperature of the electrolytic bath at a second temperature, in which the first temperature is maintained in a range from about 30° C. to about 60° C. and the second temperature is maintained at a temperature (a) at least 5° C. lower than the first temperature and (b) in a range from about 15° C. to about 35° C.

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Номер записи: 6

02-02-2012 дата публикации

Laminated semiconductor substrate, laminated chip package and method of manufacturing the same

Номер: US20120025354A1

Автор: Atsushi Iijima, Hiroyuki Ito, Yoshitaka Sasaki

Принадлежит: Headway Technologies Inc, SAE Magnetics HK Ltd

In a laminated semiconductor substrate, a plurality of semiconductor substrates are laminated. Each of the semiconductor substrate has a plurality of scribe-groove parts formed along scribe lines. Further, each of the semiconductor substrate has a plurality of device regions insulated from each other and has a semiconductor device formed therein. Further, an uppermost substrate and a lowermost substrate have an electromagnetic shielding layer formed using a ferromagnetic body. The electromagnetic shielding layer is formed in a shielding region except the extending zone. The extending zone is set a part which the wiring electrode crosses, in a peripheral edge part of the device region.

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Номер записи: 7

09-02-2012 дата публикации

Semiconductor device, electronic apparatus, and method of manufacturing semiconductor device

Номер: US20120032298A1

Автор: Hideki Fujii, Kenji Furuya, Yuichi Miyagawa

Принадлежит: Renesas Electronics Corp

A semiconductor chip is mounted on a first surface of an interconnect substrate, and has a multilayer interconnect layer. A first inductor is formed over the multilayer interconnect layer, and a wiring axis direction thereof is directed in a horizontal direction to the interconnect substrate. A second inductor is formed on the multilayer interconnect layer, and a wiring axis direction thereof is directed in the horizontal direction to the interconnect substrate. The second inductor is opposite to the first inductor. A sealing resin seals at least the first surface of the interconnect substrate and the semiconductor chip. A groove is formed over the whole area of a portion that is positioned between the at least first inductor and the second inductor of a boundary surface of the multilayer interconnect layer and the sealing resin.

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Номер записи: 8

16-02-2012 дата публикации

Method for molecular adhesion bonding at low pressure

Номер: US20120038027A1

Автор: Marcel Broekaart

Принадлежит: Soitec SA

The present invention relates to a method for molecular adhesion bonding between at least a first wafer and a second wafer involving aligning the first and second wafers, placing the first and second wafers in an environment having a first pressure (P 1 ) greater than a predetermined threshold pressure; bringing the first wafer and the second wafer into alignment and contact; and initiating the propagation of a bonding wave between the first and second wafer after the wafers are aligned and in contact by reducing the pressure within the environment to a second pressure (P 2 ) below the threshold pressure. The invention also relates to the three-dimensional composite structure that is obtained by the described method of adhesion bonding.

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Номер записи: 9

16-02-2012 дата публикации

Stitch bump stacking design for overall package size reduction for multiple stack

Номер: US20120038059A1

Автор: Foong Yue Ho, Kevin Guan, Koo Eng LUON, Lai Nguk Chin, Sally Foong, Wong Kwet Nam

Принадлежит: Individual

A method for die stacking is disclosed. In one embodiment a first die is formed overlying a substrate. A first wire is bonded to the first die and to a bond finger of the substrate, wherein the first wire is bonded to the bond finger with a first bond. A first stitch bump is formed overlying the first stitch bond, wherein the first stitch bump is formed from a molten ball of conductive material. A second die is formed overlying the first die. A second wire is bonded to the second die and to the first stitch bump, wherein the second wire is bonded to the first stitch bump with a second bond.

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Номер записи: 10

01-03-2012 дата публикации

Process for assembling two parts of a circuit

Номер: US20120052629A1

Автор: Patrick Lamontagne, Perceval Coudrain, Yacine Felk

Принадлежит: STMICROELECTRONICS SA

A three-dimensional integrated structure is fabricated by assembling at least two parts together, wherein each part contains at least one metallic line covered with a covering region and having a free side. A cavity is formed in the covering region of each part, that cavity opening onto the metallic line. The two parts are joined together with the free sides facing each other and the cavities in each covering region aligned with each other. The metallic lines are then electrically joined to each other through an electromigration of the metal within at least one of the metallic lines, the electromigrated material filling the aligned cavities.

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Номер записи: 11

08-03-2012 дата публикации

Multi-chip package with offset die stacking

Номер: US20120056335A1

Автор: Peter B. Gillingham

Принадлежит: Mosaid Technologies Inc

A semiconductor device has a plurality of stacked semiconductor dice mounted on a substrate. Each die has similar dimensions. Each die has a first plurality of bonding pads arranged along a bonding edge of the die. A first group of the dice are mounted to the substrate with the bonding edge oriented in a first direction. A second group of the dice are mounted to the substrate with the bonding edge oriented in a second direction opposite the first direction. Each die is laterally offset in the second direction relative to the remaining dice by a respective lateral offset distance such that the bonding pads of each die are not disposed between the substrate and any portion of the remaining dice in a direction perpendicular to the substrate. A plurality of bonding wires connects the bonding pads to the substrate. A method of manufacturing a semiconductor device is also disclosed.

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Номер записи: 12

15-03-2012 дата публикации

Semiconductor chip, stacked chip semiconductor package including the same, and fabricating method thereof

Номер: US20120061834A1

Автор: Tae Min Kang

Принадлежит: Hynix Semiconductor Inc

A semiconductor chip includes a silicon wafer formed with a via hole, a metal wire disposed in the via hole, and a filler that exposes a part of an upper portion of the metal wire while filing the via hole.

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Номер записи: 13

15-03-2012 дата публикации

Method of manufacture of integrated circuit packaging system with stacked integrated circuit

Номер: US20120064668A1

Автор: Henry Descalzo Bathan, Jairus Legaspi Pisigan, Zigmund Ramirez Camacho

Принадлежит: Individual

A method of manufacture of an integrated circuit packaging system includes: forming a base lead having an outer protrusion and an inner protrusion with a recess in between; forming a stack lead having an elongated portion; mounting a base integrated circuit over the inner protrusion or under the elongated portion; mounting the stack lead over the base lead and the base integrated circuit; connecting a stack integrated circuit and the stack lead with the stack integrated circuit over the base integrated circuit; and encapsulating at least a portion of both the base integrated circuit and the stack integrated circuit with the base lead and the stack lead exposed.

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Номер записи: 14

29-03-2012 дата публикации

Semiconductor package with through electrodes and method for manufacturing the same

Номер: US20120074529A1

Автор: Jin-Ho Bae, Ki-Young Kim, Myung-Geun PARK

Принадлежит: Hynix Semiconductor Inc

A semiconductor package may include a substrate with a first surface over which bond fingers are formed. At least two semiconductor chips may be stacked on the first surface of the substrate and each chip may have via holes. The semiconductor chips may be stacked such that the respective via holes expose the respective bond fingers of the substrate. Through electrodes may be formed in the via holes. The through electrodes may comprise carbon nanotubes grown from the exposed bond fingers of the substrate, where the through electrodes may be electrically connected with the semiconductor chips.

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Номер записи: 15

05-04-2012 дата публикации

Off-chip vias in stacked chips

Номер: US20120080807A1

Автор: Belgacem Haba, David Ovrutsky, Ilyas Mohammed, Laura Wills Mirkarimi, Vage Oganesian

Принадлежит: Tessera LLC

A microelectronic assembly includes first and second stacked microelectronic elements, each having spaced apart traces extending along a front face and beyond at least a first edge thereof. An insulating region can contact the edges of each microelectronic element and at least portions of the traces of each microelectronic element extending beyond the respective first edges. The insulating region can define first and second side surfaces adjacent the first and second edges of the microelectronic elements. A plurality of spaced apart openings can extend along a side surface of the microelectronic assembly. Electrical conductors connected with respective traces can have portions disposed in respective openings and extending along the respective openings. The electrical conductors may extend to pads or solder balls overlying a face of one of the microelectronic elements.

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Номер записи: 16

12-04-2012 дата публикации

Chip stacked structure

Номер: US20120086119A1

Автор: Ming-Che Wu

Принадлежит: Universal Global Scientific Industrial Co Ltd, Universal Scientific Industrial Shanghai Co Ltd

A chip stacked structure is provided. The chip stacked structure includes a first die and a second die stacked on the first die. The first die has a plurality of connection structures each which has a through hole, a connection pad and a solder bump. The connection pad has a terminal connected to the through hole. The solder bump is disposed on the connection pad and located around the through hole. The second die has a plurality of through holes which are aligned and bonded to the solder bump respectively. The chip stacked structure may simplify the process and improve the process yield rate.

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Номер записи: 17

19-04-2012 дата публикации

Pass-through 3d interconnect for microelectronic dies and associated systems and methods

Номер: US20120094443A1

Автор: David S. Pratt, Dewali Ray, Kyle K. Kirby

Принадлежит: Micron Technology Inc

Pass-through 3D interconnects and microelectronic dies and systems of stacked dies that include such interconnects are disclosed herein. In one embodiment, a system of stacked dies includes a first microelectronic die having a substrate, a metal substrate pad, and a first integrated circuit electrically coupled to the substrate pad. A pass-through 3D interconnect extends between front and back sides of the substrate, including through the substrate pad. The pass-through interconnect is electrically isolated from the substrate pad and electrically coupled to a second integrated circuit of a second microelectronic die attached to the back side of the substrate. In another embodiment, the first integrated circuit is a first memory device and the second integrated circuit is a second memory device, and the system uses the pass-through interconnect as part of an independent communication path to the second memory device.

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Номер записи: 18

26-04-2012 дата публикации

Power/ground layout for chips

Номер: US20120098127A1

Автор: Albert Wu, Chuan-Cheng Cheng, Chung Chyung Han, Sehat Sutardja, Shuhua Yu, Weidan Li

Принадлежит: MARVELL WORLD TRADE LTD

Embodiments of the present disclosure provide a chip that comprises a base metal layer formed over a first semiconductor die and a first metal layer formed over the base metal layer. The first metal layer includes a plurality of islands configured to route at least one of (i) a ground signal or (ii) a power signal in the chip. The chip further comprises a second metal layer formed over the first metal layer. The second metal layer includes a plurality of islands configured to route at least one of (i) the ground signal or (ii) the power signal in the chip.

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Номер записи: 19

03-05-2012 дата публикации

Device and method for mounting electronic components

Номер: US20120102726A1

Автор: Hideki Sumi, Kenichi Kaida, Kenichirou Ishimoto, Masahiro Kihara, Noboru Higashi

Принадлежит: Panasonic Corp

An object is to provide an electronic component mounting method in which an adequate component mounting work to which a check result is correctly reflected is enabled and it is possible to satisfy both reduction of the failure occurrence rate and improvement of the working efficiency. An electronic component mounting apparatus in which an appearance checking section which checks a board to detect existence or non-existence of a failure item, and a component mounting section which transfers and mounts an allocated mounting object component to the board in which the check is ended are integrally disposed includes a mounting availability determination processing section 28 d which determines an availability of an execution of an operation of mounting the mounting object component, based on a result of detection of a failure item. In a mounting availability determining process, an availability of an execution of a mounting operation for the mounting object component is automatically determined based on preset failure patterns of the detection result.

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Номер записи: 20

03-05-2012 дата публикации

Three-dimensional stacked semiconductor integrated circuit and tsv repair method thereof

Номер: US20120104388A1

Автор: Min Seok Choi, Sang Jin Byeon, Young Jun KU

Принадлежит: Hynix Semiconductor Inc

Provided is a 3 D stacked semiconductor integrated circuit including a plurality of chips coupled through a plurality of TSVs. A first chip among the plurality of chips is configured to detect and repair a defective TSV among the plurality of TSVs, and transmit repair information to remaining chips other than the first chip, and the remaining chips other than the first chip are configured to repair the defective TSV in response to the repair information.

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Номер записи: 21

24-05-2012 дата публикации

System comprising a semiconductor device and structure

Номер: US20120129301A1

Автор: Brian Cronquist, Deepak C. Sekar, Israel Beinglass, Paul Lim, Ze'ev Wurman, Zvi Or-Bach

Принадлежит: Monolithic 3D Inc

A method of manufacturing a semiconductor device, the method including, providing a first monocrystalline layer including semiconductor regions, overlaying the first monocrystalline layer with an isolation layer, transferring a second monocrystalline layer comprising semiconductor regions to overlay the isolation layer, wherein the first monocrystalline layer and the second monocrystalline layer are formed from substantially different crystal materials; and subsequently etching the second monocrystalline layer as part of forming at least one transistor in the second monocrystalline layer.

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Номер записи: 22

31-05-2012 дата публикации

Tsv substrate structure and the stacked assembly thereof

Номер: US20120133030A1

Автор: Cha-Hsin Lin, Chung-Chih Wang, Pei-Jer Tzeng, Tzu-Kun Ku

Принадлежит: Industrial Technology Research Institute ITRI

The disclosure provides a TSV substrate structure and the stacked assembly of a plurality of the substrate structures, the TSV substrate structure including: a substrate comprising a first surface, a corresponding second surface, and a TSV communicating the first surface with the second surface through the substrate; and a conductor unit completely filling the TSV, the conductor unit comprising a conductor body which has a first and a second ends corresponding to the first and second surfaces of the substrate, respectively.

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Номер записи: 23

21-06-2012 дата публикации

Tsv for 3d packaging of semiconductor device and fabrication method thereof

Номер: US20120153496A1

Автор: Chang-woo Lee, Jae-hak Lee, Joon-Yub Song, Tae-Ho Ha

Принадлежит: Korea Institute of Machinery and Materials KIMM

The present invention relates to a through silicon via (TSV) for 3D packaging to integrate a semiconductor device and a method for manufacturing the same, and more particularly, to a through silicon via (TSV) for 3D packaging of a semiconductor device that is capable of improving production efficiency, having very high electric conductivity, and minimizing electrical signal delay, without using a carrier wafer by self-aligning substrates in a low temperature state and sequentially bonding a plurality of semiconductor dies (or semiconductor chips), and a method of manufacturing the same.

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Номер записи: 24

21-06-2012 дата публикации

Semiconductor package and manufacturing method therefor

Номер: US20120153509A1

Автор: Akihiko Tateiwa, Masahiro Kyozuka, Toru Hizume

Принадлежит: Shinko Electric Industries Co Ltd

According to one embodiment, there is provided a semiconductor package including: a semiconductor chip; a resin portion formed to cover the semiconductor chip; a wiring structure formed on the resin portion and electrically connected to the semiconductor chip; and a warpage preventing member provided above the resin portion to have a thermal expansion coefficient closer to that of the semiconductor chip than to that of the wiring structure.

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Номер записи: 25

28-06-2012 дата публикации

Trap Rich Layer for Semiconductor Devices

Номер: US20120161310A1

Автор: Chris BRINDLE, Michael A. Stuber, Stuart B. Molin

Принадлежит: IO Semiconductor Inc

An integrated circuit chip is formed with an active layer and a trap rich layer. The active layer is formed with an active device layer and a metal interconnect layer. The trap rich layer is formed above the active layer. In some embodiments, the active layer is included in a semiconductor wafer, and the trap rich layer is included in a handle wafer.

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Номер записи: 26

28-06-2012 дата публикации

Method of manufacturing semiconductor device including plural semiconductor chips stacked together

Номер: US20120164788A1

Автор: Akira Ide

Принадлежит: Elpida Memory Inc

Such a method is disclosed that includes preparing first and second semiconductor chips, the first semiconductor chip including a first electrode formed on one surface thereof and a second electrode formed on the other surface thereof so as to overlap the first electrode as viewed from a stacking direction, and the second semiconductor chip including a third electrode formed on one surface thereof and a fourth electrode formed on the other surface thereof so as not to overlap the third electrode as viewed from the stacking direction, and stacking the first and second semiconductor chips in the stacking direction so that the second electrode is connected to the third electrode by using a bonding tool including a concave at a position corresponding to the fourth electrode.

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Номер записи: 27

28-06-2012 дата публикации

Three-Dimensional Semiconductor Device

Номер: US20120164789A1

Автор: David Ding-Chung Lu, Wen-Chih Chiou

Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

A three-dimensional semiconductor device using redundant bonding-conductor structures to make inter-level electrical connections between multiple semiconductor chips is disclosed. A first chip, or other semiconductor substrate, forms a first active area on its upper surface, and a second chip or other semiconductor substrate forms a second active area on its upper surface. According to the present invention, when the second chip has been mounted above the first chip, either face-up or face-down, the first active area is coupled to the second active area by at least one redundant bonding-conductor structure. In one embodiment, each redundant bonding-conductor structure includes at least one via portion that extends completely through the second chip to perform this function. In another, the redundant bonding-conductor structure extends downward to the top level interconnect. The present invention also includes a method for making such a device.

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Номер записи: 28

12-07-2012 дата публикации

Methods And Materials Useful For Chip Stacking, Chip And Wafer Bonding

Номер: US20120175721A1

Автор: Andrew Bell, Chris Apanius, Hendra Ng, Phil Neal, Robert A. Shick, Wei Zhang

Принадлежит: PROMERUS LLC

Materials, and methods that use such materials, that are useful for forming chip stacks, chip and wafer bonding and wafer thinning are disclosed. Such methods and materials provide strong bonds while also being readily removed with little or no residues.

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Номер записи: 29

19-07-2012 дата публикации

Semiconductor Device and Method of Forming Bond Wires and Stud Bumps in Recessed Region of Peripheral Area around the Device for Electrical Interconnection to Other Devices

Номер: US20120181689A1

Автор: Byung Tai Do, Linda Pei Ee CHUA, Reza A. Pagaila

Принадлежит: Stats Chippac Pte Ltd

A semiconductor wafer contains a plurality of semiconductor die each having a peripheral area around the die. A recessed region with angled or vertical sidewall is formed in the peripheral area. A conductive layer is formed in the recessed region. A first stud bump is formed over a contact pad of the semiconductor die. A second stud bump is formed over the first conductive layer within the recessed region. A bond wire is formed between the first and second stud bumps. A third stud bump is formed over the bond wire and first stud bump. A dicing channel partially formed through the peripheral area. The semiconductor wafer undergoes backgrinding to the dicing channel to singulate the semiconductor wafer and separate the semiconductor die. The semiconductor die can be disposed in a semiconductor package with other components and electrically interconnected through the bond wire and stud bumps.

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Номер записи: 30

19-07-2012 дата публикации

Method of transferring and electrically joining a high density multilevel thin film to a circuitized and flexible organic substrate and associated devices

Номер: US20120182701A1

Автор: David Nicol, Louis Joseph Rendek, Jr., Michael Weatherspoon

Принадлежит: HARRIS CORP

A method is for making an electronic device and includes forming an interconnect layer stack on a sacrificial substrate and having a plurality of patterned electrical conductor layers, and a dielectric layer between adjacent patterned electrical conductor layers. The method also includes laminating and electrically joining through an intermetallic bond a liquid crystal polymer (LCP) substrate to the interconnect layer stack on a side thereof opposite the sacrificial substrate. The method further includes removing the sacrificial substrate to expose a lowermost patterned electrical conductor layer, and electrically coupling at least one first device to the lowermost patterned electrical conductor layer.

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Номер записи: 31

26-07-2012 дата публикации

Direct Edge Connection for Multi-Chip Integrated Circuits

Номер: US20120187577A1

Автор: James L. Speidell, John U. Knickerbocker, Matthew J. Farinelli, Peter A. Gruber, Sherif A. Goma, Steven A. Cordes

Принадлежит: International Business Machines Corp

The present invention allows for direct chip-to-chip connections using the shortest possible signal path.

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Номер записи: 32

26-07-2012 дата публикации

Through silicon via repair

Номер: US20120190133A1

Автор: Christopher S. Putnam, Junjun Li, Michel J. Abou-Khalil, Robert J. Gauthier, Jr., Souvick Mitra, Tom C. Lee

Принадлежит: International Business Machines Corp

Methods and systems for altering the electrical resistance of a wiring path. The electrical resistance of the wiring path is compared with a target electrical resistance value. If the electrical resistance of the wiring path exceeds the target electrical resistance value, an electrical current is selectively applied to the wiring path to physically alter a portion of the wiring path. The current may be selected to alter the wiring path such that the electrical resistance drops to a value less than or equal to the target electrical resistance value.

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Номер записи: 33

02-08-2012 дата публикации

Semiconductor device and method of fabricating the same

Номер: US20120193779A1

Автор: Chung-Sun Lee, Hyun-jung SONG, Jung-Hwan Kim, Sun-pil Youn, Tae-Hong Min

Принадлежит: SAMSUNG ELECTRONICS CO LTD

A stack of semiconductor chips, a semiconductor device, and a method of manufacturing are disclosed. The stack of semiconductor chips may comprise a first chip of the stack, a second chip of the stack over the first chip, conductive bumps, a homogeneous integral underfill material, and a molding material. The conductive bumps may extend between an upper surface of the first chip and a lower surface of the second chip. The homogeneous integral underfill material may be interposed between the first chip and the second chip, encapsulate the conductive bumps, and extend along sidewalls of the second chip. The homogeneous integral underfill material may have an upper surface extending in a direction parallel to an upper surface of the second chip and located adjacent the upper surface of the second chip. The molding material may be on outer side surfaces of the homogeneous integral underfill material above the upper surface of the first chip, wherein, in view of a first cross sectional profile, the molding material is separated from sidewalls of the second chip by the homogeneous integral underfill material such that the molding material does not contact sidewalls of the second chip.

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Номер записи: 34

09-08-2012 дата публикации

Semiconductor device and method of fabricating the semiconductor device

Номер: US20120199981A1

Автор: Ho-geon Song, Jae-hyun PHEE, Ju-Il Choi, Se-young Jeong

Принадлежит: SAMSUNG ELECTRONICS CO LTD

A semiconductor device includes a first device including a first substrate and a first external connection terminal for connecting outside the first device; a second device stacked on the first device, the second device including a second substrate and a second external connection terminal for connecting outside the second device; an adhesive pattern disposed between the first device and second device, the adhesive pattern disposed in locations other than locations where the first external connection terminal and second external connection terminal are disposed, and the adhesive pattern causing the first device and second device, when stacked, to be spaced apart by a predetermined distance; and a plated layer disposed between and electrically and physically connecting the first external connection terminal and the second external connection terminal.

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Номер записи: 35

30-08-2012 дата публикации

Bonded Semiconductor Structure With Pyramid-Shaped Alignment Openings and Projections

Номер: US20120217610A1

Автор: Luu Nguyen, Peter J. Hopper, Peter Johnson, Peter Smeys

Принадлежит: National Semiconductor Corp

A bonded semiconductor structure is formed in a method that first forms a female semiconductor structure with pyramid-shaped openings and a male semiconductor structure with pyramid-shaped projections, and then inserts the projections into the openings to align the male semiconductor structure to the female semiconductor structure for bonding.

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Номер записи: 36

30-08-2012 дата публикации

Semiconductor Device and Method of Forming a Wafer Level Package Structure Using Conductive Via and Exposed Bump

Номер: US20120217629A1

Автор: Daesik Choi, Joonyoung Choi, SungWon Cho

Принадлежит: Stats Chippac Pte Ltd

A semiconductor device has a carrier. A semiconductor wafer including a semiconductor die is mounted to the carrier with an active surface of the semiconductor die facing away from the carrier. A plurality of bumps is formed over the active surface of the semiconductor die. An opening is formed in a periphery of the semiconductor die. An encapsulant is deposited over the carrier and semiconductor die, in the opening, and around the plurality of bumps such that an exposed portion of the plurality of bumps is devoid of encapsulant. A conductive via is formed through the encapsulant, within the opening, and extends to the carrier. A conductive layer is formed over the encapsulant and electrically connects to the conductive via and the exposed portion of the plurality of bumps. The carrier is removed to expose an end of the conductive via.

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Номер записи: 37

30-08-2012 дата публикации

Semiconductor Device and Method of Forming Bond Wires Between Semiconductor Die Contact Pads and Conductive TOV in Peripheral Area Around Semiconductor Die

Номер: US20120217643A1

Автор: Byung Tai Do, Dioscoro A. Merilo, Reza A. Pagaila

Принадлежит: Stats Chippac Pte Ltd

A semiconductor wafer has a plurality of semiconductor die with contact pads. An organic material is deposited in a peripheral region around the semiconductor die. A portion of the organic material is removed to form a plurality of vias. A conductive material is deposited in the vias to form conductive TOV. The conductive TOV can be recessed with respect to a surface of the semiconductor die. Bond wires are formed between the contact pads and conductive TOV. The bond wires can be bridged in multiple sections across the semiconductor die between the conductive TOV and contact pads. An insulating layer is formed over the bond wires and semiconductor die. The semiconductor wafer is singulated through the conductive TOV or organic material between the conductive TOV to separate the semiconductor die. A plurality of semiconductor die can be stacked and electrically connected through the bond wires and conductive TOV.

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Номер записи: 38

30-08-2012 дата публикации

Semiconductor devices and methods of manufacturing semiconductor devices

Номер: US20120217652A1

Автор: David S. Pratt

Принадлежит: Micron Technology Inc

Semiconductor devices and methods of manufacturing semiconductor devices. One example of a method of fabricating a semiconductor device comprises forming a conductive feature extending through a semiconductor substrate such that the conductive feature has a first end and a second end opposite the first end, and wherein the second end projects outwardly from a surface of the substrate. The method can further include forming a dielectric layer over the surface of the substrate and the second end of the conductive feature such that the dielectric layer has an original thickness. The method can also include removing a portion of the dielectric layer to an intermediate depth less than the original thickness such that at least a portion of the second end of the conductive feature is exposed.

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Номер записи: 39

13-09-2012 дата публикации

Semiconductor device and manufacturing method of the same

Номер: US20120228762A1

Автор: Hiroshi Watabe, Masatoshi Fukuda

Принадлежит: Toshiba Corp

A semiconductor device, includes: a wiring substrate, a stacked body mounted on the wiring substrate, an underfill layer filled into gaps between respective semiconductor chips of the stacked body; and a molding body made up of a molding resin covered and formed at outside of the stacked body and so on. The underfill layer is made up of a cured product of a resin material containing an amine-based curing agent, and the cured product has a Tg of 65° C. or more and 100° C. or less.

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Номер записи: 40

18-10-2012 дата публикации

Test structure and methodology for three-dimensional semiconductor structures

Номер: US20120262197A1

Автор: Christopher M. Durham, Donald L. Wheater, Jerome L. Cann, Kerry Bernstein, Paul D. Kartschoke, Peter J. Klim

Принадлежит: International Business Machines Corp

A plurality of peripheral test structure substrate (PTSS) through vias is formed within a peripheral test structure substrate. A peripheral test structure layer and at least one functional layer are formed on one side of the plurality of the PTSS through vias. The other side of the plurality of the PTSS through vias is exposed throughout fabrication of the peripheral test structure layer and the at least one functional layer to provide access points for testing functionality of the various layers throughout the manufacturing sequence. C4 bonding may be performed after manufacture of all of the at least one functional layer is completed. A 3D assembly carrier or a C4 carrier substrate is not required since the peripheral test structure substrate has sufficient mechanical strength to support the peripheral test structure layer and the at least one functional layer.

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Номер записи: 41

01-11-2012 дата публикации

Three-dimensional system-in-a-package

Номер: US20120273933A1

Автор: Belgacem Haba, Craig Mitchell, Ilyas Mohammed, Piyush Savalia, Vage Oganesian

Принадлежит: TESSERA RESEARCH LLC

A microelectronic assembly can include first, second and third stacked substantially planar elements, e.g., of dielectric or semiconductor material, and which may have a CTE of less than 10 ppm/° C. The assembly may be a microelectronic package and may incorporate active semiconductor devices in one, two or more of the first, second or third elements to function cooperatively as a system-in-a-package. In one example, an electrically conductive element having a minimum thickness less than 10 microns, may be formed by plating, and may electrically connect two or more of the first, second or third elements. The conductive element may entirely underlie a surface of another one of the substantially planar elements.

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Номер записи: 42

01-11-2012 дата публикации

Contact Metal for Hybridization and Related Methods

Номер: US20120273951A1

Автор: Aaron M. Ramirez, Andreas Hampp, Jonathan GETTY, Scott S. Miller

Принадлежит: Raytheon Co

A contact structure for interconnecting a first substrate to an indium interconnect structure on a second substrate. The contact structure comprises a diffusive layer and a non-oxidizing layer, with a thickness of less than approximately 150 nm, positioned on the diffusive layer for alignment with the indium interconnect.

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Номер записи: 43

01-11-2012 дата публикации

Method for manufacturing semiconductor device

Номер: US20120276733A1

Автор: Nobuaki Hoshi, Yoshihiro Saeki

Принадлежит: Elpida Memory Inc

In order to provide a semiconductor device that includes a conductive layer on one surface of a semiconductor substrate with an insulating layer therebetween, a bump on the other surface of the semiconductor substrate, and a through-electrode through the semiconductor substrate connecting the conductive layer with the bump, a through-hole is formed from the other surface of the semiconductor substrate to be connected to the conductive layer, a seed metal film is formed on the through-hole and the other surface, a photoresist is formed thereon, a mask layer is formed by processing the photoresist with a pattern larger than the through-hole, a plated film is grown by electrolytic plating so as to integrally form the through-electrode and a part of the bump.

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Номер записи: 44

08-11-2012 дата публикации

Method of manufacturing chip-stacked semiconductor package

Номер: US20120282735A1

Автор: Chang-seong Jeon, Dong-Hyeon Jang, Ho-geon Song, Jung-seok Ahn, Sang-sick Park, Sung-Jun IM, Teak-Hoon LEE

Принадлежит: SAMSUNG ELECTRONICS CO LTD

A method of manufacturing a chip-stacked semiconductor package, the method including preparing a base wafer including a plurality of first chips each having a through-silicon via (TSV); bonding the base wafer including the plurality of first chips to a supporting carrier; preparing a plurality of second chips; forming stacked chips by bonding the plurality of second chips to the plurality of first chips; sealing the stacked chips with a sealing portion; and separating the stacked chips from each other.

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Номер записи: 45

22-11-2012 дата публикации

Methods and structures for forming integrated semiconductor structures

Номер: US20120292748A1

Автор: Mariam Sadaka, Radu Ionut

Принадлежит: Soitec SA

The invention provides methods and structures for fabricating a semiconductor structure and particularly for forming a semiconductor structure with improved planarity for achieving a bonded semiconductor structure comprising a processed semiconductor structure and a number of bonded semiconductor layers. Methods for forming semiconductor structures include forming a dielectric layer over a non-planar surface of a processed semiconductor structure, planarizing a surface of the dielectric layer on a side thereof opposite the processed semiconductor structure, and attaching a semiconductor structure to the planarized surface of the dielectric layer. Semiconductor structures include a dielectric layer overlaying a non-planar surface of a processed semiconductor structure, and a masking layer overlaying the dielectric layer on a side thereof opposite the processed semiconductor structure. The masking layer includes a plurality of mask openings over conductive regions of the non-planar surface of the processed semiconductor structure.

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Номер записи: 46

29-11-2012 дата публикации

Stacked wafer level package having a reduced size

Номер: US20120299169A1

Автор: Jong Hoon Kim, Min Suk Suh, Seung Hyun Lee, Seung Taek Yang, Tae Min Kang

Принадлежит: SK hynix Inc

A stacked wafer level package includes a first semiconductor chip having a first bonding pad and a second semiconductor chip having a second bonding pad. Both bonding pads of the semiconductor chips face the same direction. The second semiconductor chip is disposed in parallel to the first semiconductor chip. A third semiconductor chip is disposed over the first and second semiconductor chips acting as a supporting substrate. The third semiconductor chip has a third bonding pad that is exposed between the first and the second semiconductor chips upon attachment. Finally, a redistribution structure is electrically connected to the first, second, and third bonding pads.

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Номер записи: 47

29-11-2012 дата публикации

Distributed semiconductor device methods, apparatus, and systems

Номер: US20120302006A1

Автор: Hussein I. Hanafi, Paul A. Farrar

Принадлежит: Individual

Some embodiments include a device having a number of memory cells and associated circuitry for accessing the memory cells. The memory cells of the device may be formed in one or more memory cell dice. The associated circuitry of the device may also be formed in one or more dice, optionally separated from the memory cell dice.

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Номер записи: 48

13-12-2012 дата публикации

3D Integrated Microelectronic Assembly With Stress Reducing Interconnects And Method Of Making Same

Номер: US20120313209A1

Автор: Vage Oganesian

Принадлежит: Optiz Inc

A microelectronic assembly and method of making, which includes a first microelectronic element (including a substrate with first and second opposing surfaces, a semiconductor device, and conductive pads at the first surface which are electrically coupled to the semiconductor device) and a second microelectronic element (including a handier with first and second opposing surfaces, a second semiconductor device, and conductive pads at the handler first surface which are electrically coupled to the second semiconductor device). The first and second microelectronic elements are integrated such that the second surfaces face each other. The first microelectronic element includes conductive elements each extending from one of its conductive pads, through the substrate to the second surface. The second microelectronic element includes conductive elements each extending between the handler first and second surfaces. The conductive elements of the first microelectronics element are electrically coupled to the conductive elements of the second microelectronics element.

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Номер записи: 49

13-12-2012 дата публикации

Semiconductor device structures

Номер: US20120313248A1

Автор: Mark E. Tuttle

Принадлежит: Micron Technology Inc

The present invention relates to methods for forming through-wafer interconnects in semiconductor substrates and the resulting structures. In one embodiment, a method for forming a through-wafer interconnect includes providing a substrate having a pad on a surface thereof, depositing a passivation layer over the pad and the surface of the substrate, and forming an aperture through the passivation layer and the pad using a substantially continuous process. An insulative layer is deposited in the aperture followed by a conductive layer and a conductive fill. In another embodiment of the invention, a semiconductor device is formed including a first interconnect structure that extends through a conductive pad and is electrically coupled with the conductive pad while a second interconnect structure is formed through another conductive pad while being electrically isolated therefrom. Semiconductor devices and assemblies produced with the methods are also disclosed.

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Номер записи: 50

13-12-2012 дата публикации

Layered chip package and method of manufacturing same

Номер: US20120313260A1

Автор: Atsushi Iijima, Hiroshi Ikejima, Hiroyuki Ito, Yoshitaka Sasaki

Принадлежит: Headway Technologies Inc, SAE Magnetics HK Ltd

A layered chip package includes a main body and wiring. The main body includes: a main part having a top surface and a bottom surface and including three or more layer portions stacked on one another; a plurality of first terminals disposed on the top surface of the main part; and a plurality of second terminals disposed on the bottom surface of the main part. Each layer portion includes a semiconductor chip having first and second surfaces, and a plurality of electrodes electrically connected to the wiring. The plurality of electrodes are disposed on a side of the first surface of the semiconductor chip. A first layer portion located closest to the top surface of the main part and a second layer portion located closest to the bottom surface of the main part are arranged so that the second surfaces of their respective semiconductor chips face toward each other. The plurality of first terminals are formed by using the plurality of electrodes of the first layer portion. The plurality of second terminals are formed by using the plurality of electrodes of the second layer portion.

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Номер записи: 51

13-12-2012 дата публикации

Semiconductor package

Номер: US20120313265A1

Автор: Norio Yamanishi

Принадлежит: Shinko Electric Industries Co Ltd

A semiconductor package includes a plurality of connection pads, which are electrically connected to connection terminals of a mounted component that is mounted on the semiconductor package, and recognition marks. The recognition marks are formed respectively within the area of each of at least two of the connection pads. Each recognition mark has an area that is smaller than the area of the connection mark in which it is formed.

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Номер записи: 52

13-12-2012 дата публикации

Method for producing reconstituted wafers and method for producing semiconductor devices

Номер: US20120315710A1

Автор: Kazuyuki Hozawa, Kenichi Takeda, Mayu Aoki

Принадлежит: HITACHI LTD

In order to provide a method for producing semiconductor devices that can use the highly productive W to W method, and achieve a high yield, a method for producing semiconductor devices comprises a step (S 401 ) in which a reconstituted wafer is prepared by replacing defective chips with non-defective chips, a step (S 403 ) in which the reconstituted wafer and the base wafer are connected to one another by laminating, a step (S 406 ) in which through-electrodes are formed in the reconstituted wafer, and a step (S 409 ) in which a separate reconstituted wafer is laminated onto and connected to the reconstituted wafer having through-electrodes.

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Номер записи: 53

20-12-2012 дата публикации

Hermetically sealed wafer packages

Номер: US20120319261A1

Автор: Cody B. Moody

Принадлежит: Raytheon Co

Hermetically sealed semiconductor wafer packages that include a first bond ring on a first wafer facing a complementary surface of a second bond ring on a second wafer. The package includes first and second standoffs of a first material, having a first thickness, formed on a surface of the first bond ring. The package also includes a eutectic alloy (does not have to be eutectic, typically it will be an alloy not specific to the eutectic ratio of the elements) formed from a second material and the first material to create a hermetic seal between the first and second wafer, the eutectic alloy formed by heating the first and second wafers to a temperature above a reflow temperature of the second material and below a reflow temperature of the first material, wherein the eutectic alloy fills a volume between the first and second standoffs and the first and second bond rings, and wherein the standoffs maintain a prespecified distance between the first bond ring and the second bond ring.

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Номер записи: 54

20-12-2012 дата публикации

Flip chip assembly process for ultra thin substrate and package on package assembly

Номер: US20120319276A1

Автор: A. Vethanayagam Rudge, Bok Sim Lim, Kang Eu Ong, Mun Leong Loke, Sih Fei Lim, Tean Wee One, Weng Khoon Mong

Принадлежит: Individual

In some embodiments, selective electroless plating for electronic substrates is presented. In this regard, a method is introduced including receiving a coreless substrate strip, attaching solder balls to a backside of the coreless substrate strip, and forming a backside stiffening mold amongst the solder balls. Other embodiments are also disclosed and claimed.

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Номер записи: 55

27-12-2012 дата публикации

Through wafer vias and method of making same

Номер: US20120329219A1

Автор: Alvin Jose Joseph, Anthony Kendall Stamper, Hanyi Ding

Принадлежит: International Business Machines Corp

A method of forming and structure for through wafer vias and signal transmission lines formed of through wafer vias. The method of forming through wafer vias includes forming an array of through wafer vias comprising at least one electrically conductive through wafer via and at least one electrically non-conductive through wafer via through a semiconductor substrate having a top surface and an opposite bottom surface, each through wafer via of the array of through wafer vias extending from the top surface of the substrate to the bottom surface of the substrate.

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Номер записи: 56

03-01-2013 дата публикации

Semiconductor apparatus and stacked semiconductor apparatus

Номер: US20130001548A1

Автор: Chun Seok Jeong, Jae Jin Lee

Принадлежит: Hynix Semiconductor Inc

A semiconductor apparatus includes a TSV formed to be electrically connected with another chip and a TSV test unit configured to check a capacitance component of the TSV to generate a TSV abnormality signal.

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Номер записи: 57

17-01-2013 дата публикации

Interconnection and assembly of three-dimensional chip packages

Номер: US20130015578A1

Автор: Ashok V. Krishnamoorthy, Hiren D. Thacker, Ivan Shubin, John E. Cunningham

Принадлежит: Oracle International Corp

In a chip package, semiconductor dies in a vertical stack of semiconductor dies or chips (which is referred to as a ‘plank stack’) are aligned by positive features that are mechanically coupled to negative features recessed below the surfaces of adjacent semiconductor dies. Moreover, the chip package includes an interposer plate at approximately a right angle to the plank stack, which is electrically coupled to the semiconductor dies along an edge of the plank stack. In particular, electrical pads proximate to a surface of the interposer plate (which are along a stacking direction of the plank stack) are electrically coupled to pads that are proximate to edges of the semiconductor dies by an intervening conductive material, such as solder balls or spring connectors. Note that the chip package may facilitate high-bandwidth communication of signals between the semiconductor dies and the interposer plate.

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Номер записи: 58

17-01-2013 дата публикации

Semiconductor device and test method

Номер: US20130015587A1

Автор: Akihiko Okutsu, Hitoshi Saito, Yoshiaki Okano

Принадлежит: Fujitsu Semiconductor Ltd

A semiconductor device includes a semiconductor substrate including an element region, an inner sealing and an outer sealing which are formed on the element region and have a first opening part and a second opening part, respectively, a multilayer interconnection structure which is formed on the substrate and stacks multiple inter-layer insulation films each including a wiring layer, a moisture resistant film formed between a first inter-layer insulation film and a second inter-layer insulation film which are included in the multilayer interconnection structure, a first portion which extended from a first side of the moisture resistant film and passes the first opening part, a second portion which extended from a second side of the moisture resistant film and passes through the second opening part, and a wiring pattern including a via plug which penetrates the moisture resistant film and connects the first portion and the second portion.

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Номер записи: 59

17-01-2013 дата публикации

Semiconductor device having through electrode and method of fabricating the same

Номер: US20130015588A1

Автор: Hyun-Kyoung Kim, Kang-Wook Lee, Ki-tae Park

Принадлежит: SAMSUNG ELECTRONICS CO LTD

A semiconductor device includes a substrate, and a through electrode passing through the substrate. The semiconductor device has a pad region and a through electrode region. A pad covers the pad region, extends into the through electrode region, and delimits an opening in the through electrode region. A through electrode extends through the semiconductor substrate below the hole in the pad in the through region.

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Номер записи: 60

24-01-2013 дата публикации

Semiconductor packages and methods of forming the same

Номер: US20130020720A1

Автор: Chul-Yong JANG, JONGHO LEE, Taehoon Kim, Young Lyong Kim

Принадлежит: SAMSUNG ELECTRONICS CO LTD

A semiconductor package may include a substrate including a substrate connection terminal, at least one semiconductor chip stacked on the substrate and having a chip connection terminal, a first insulating layer covering at least portions of the substrate and the at least one semiconductor chip, and/or an interconnection penetrating the first insulating layer to connect the substrate connection terminal to the chip connection terminal. A semiconductor package may include stacked semiconductor chips, edge portions of the semiconductor chips constituting a stepped structure, and each of the semiconductor chips including a chip connection terminal; at least one insulating layer covering at least the edge portions of the semiconductor chips; and/or an interconnection penetrating the at least one insulating layer to connect to the chip connection terminal of each of the semiconductor chips.

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Номер записи: 61

31-01-2013 дата публикации

Semiconductor device, semiconductor module structure configured by vertically stacking semiconductor devices, and manufacturing method thereof

Номер: US20130026650A1

Автор: Akio Katsumata, Hiroshi Inoue, Osamu Yamagata, Satoru Itakura, Shigenori Sawachi, Yasuhiro Yamaji

Принадлежит: Individual

A semiconductor device is made up of an organic substrate; through vias which penetrate the organic substrate in its thickness direction; external electrodes and internal electrodes provided to the front and back faces of the organic substrate and electrically connected to the through vias; a semiconductor element mounted on one main surface of the organic substrate via a bonding layer, with an element circuit surface thereof facing upward; an insulating material layer for sealing the semiconductor element and a periphery thereof; a metal thin film wiring layer provided in the insulating material layer, with a part of this metal thin film wiring layer being exposed on an external surface; metal vias provided in the insulating material layer and electrically connected to the metal thin film wiring layer; and external electrodes formed on the metal thin film wiring layer.

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Номер записи: 62

31-01-2013 дата публикации

TCE Compensation for Package Substrates for Reduced Die Warpage Assembly

Номер: US20130029457A1

Автор: Margaret Simmons-Matthews

Принадлежит: Texas Instruments Inc

A method for assembling die packages includes attaching contacts on a first side of a plurality of first die to substrate pads on a top surface of a composite carrier. The composite carrier includes a package substrate including at least one embedded metal layer having its bottom surface secured to a semiconductor wafer. The composite carrier minimizes effects of the CTE mismatch between the die and the package substrate during assembly reduces warpage of the die. After the attaching, the semiconductor wafer is removed from the package substrate. Electrically conductive connectors are attached to the bottom surface of the package substrate, and the package substrate is sawed to form a plurality of singulated die packages.

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Номер записи: 63

07-02-2013 дата публикации

Laser-assisted cleaving of a reconstituted wafer for stacked die assemblies

Номер: US20130032946A1

Автор: Jeffrey Alan West, Margaret Simmons-Matthews, Raymundo M. Camenforte

Принадлежит: Texas Instruments Inc

A method of forming stacked die devices includes attaching first semiconductor die onto a wafer to form a reconstituted wafer, and then bonding second semiconductor die onto the first semiconductor die to form a plurality of singulated stacked die devices on the wafer. A support tape is attached to a bottomside of the second semiconductor die. A dicing tape is attached to the wafer. The wafer is laser irradiated before or after attachment of the dicing tape at intended dicing lanes that align with gaps between the first semiconductor die to mechanically weaken the wafer at the intended dicing lanes, but not cut through the wafer. The dicing tape is pulled to cleave the wafer into a plurality of singulated portions to form a plurality of singulated stacked die devices attached to the singulated wafer portions by the dicing tape. The support tape is removed prior to cleaving.

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Номер записи: 64

07-02-2013 дата публикации

Method for assembling at least one chip using a fabric, and fabric including a chip device

Номер: US20130033879A1

Автор: Dominique Vicard, Jean Brun

Принадлежит: Commissariat a lEnergie Atomique et aux Energies Alternatives CEA

A method for assembling a device on two substantially parallel taut threads. The device includes an electronic chip and two substantially parallel grooves open on opposite sides of the device. The distance separating the grooves corresponds to the distance separating the threads. The device presents a penetrating shape along an axis perpendicular to the plane of the grooves, having a base at the level of the grooves and an apex of smaller size than the distance separating the threads. The method includes the steps consisting in placing the apex of the device between the two threads; in moving the device between the two threads resulting in the threads being separated from one another by the penetrating shape of the device; and in continuing movement of the device until the threads penetrate into the grooves reverting to their initial separation distance.

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Номер записи: 65

14-02-2013 дата публикации

Semiconductor die assemblies, semiconductor devices including same, and methods of fabrication

Номер: US20130037802A1

Автор: Luke G. England, Michel Koopmans, Paul A. Silvestri

Принадлежит: Micron Technology Inc

Methods of fabricating multi-die assemblies including a base semiconductor die bearing a peripherally encapsulated stack of semiconductor dice of lesser lateral dimensions, the dice vertically connected by conductive elements between the dice, resulting assemblies, and semiconductor devices comprising such assemblies.

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Номер записи: 66

21-02-2013 дата публикации

Package-on-package structures

Номер: US20130043587A1

Автор: Huahung Kao, Shiann-Ming Liou

Принадлежит: MARVELL WORLD TRADE LTD

Embodiments of the present disclosure provide a package on package arrangement comprising a bottom package and a second package. The first package includes a substrate layer including (i) a top side and (ii) a bottom side that is opposite to the top side. Further, the top side defines a substantially flat surface. The first package also includes a die coupled to the bottom side of the substrate layer. The second package includes a plurality of rows of solder balls, and the second package is attached to the substantially flat surface of the substrate layer via the plurality of rows of solder balls.

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Номер записи: 67

07-03-2013 дата публикации

System in package and method of fabricating same

Номер: US20130056880A1

Автор: Chien-Hsiun Lee, Tsung-Ding Wang

Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

An assembly has at least one integrated circuit (IC) die fixed in a medium. The assembly has a redistribution layer over the IC die. The redistribution layer has conductors connecting first pads on active faces of the IC die to second pads at an exposed surface of the assembly. A die unit is provided over the IC die. The die unit has a bottom die interconnected to a package substrate. Respective portions of the redistribution layer corresponding to each of the at least one IC die partially underlie the bottom die, and extend beyond the bottom die. The package substrate has contacts connected to the ones of the second pads corresponding to the at least one IC die.

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Номер записи: 68

07-03-2013 дата публикации

Method and A System for Producing a Semi-Conductor Module

Номер: US20130059402A1

Автор: Andreas Jakob, Thomas Kaiser

Принадлежит: INTERPOSERS GMBH

In a method for producing a semi-conductor module ( 10 ) comprising at least two semi-conductor chips ( 12, 14 ) and an interposer ( 20 ) which has electrically conductive structures ( 28 ) connecting the semi-conductor chips ( 12, 14 ) to one another, the interposer ( 20 ) is printed directly onto a first ( 12 ) of the semi-conductor chips. When the interposer ( 20 ) is printed on, the electrically conductive structures ( 28 ) are produced by means of electrically conductive ink ( 68 ). The second semi-conductor chip ( 14 ) is mounted on the interposer ( 20 ) such that the two semi-conductor chips ( 12, 14 ) are arranged one above the other and that the interposer ( 20 ) forms an intermediate layer between the two semi-conductor chips ( 12, 14 ).

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Номер записи: 69

28-03-2013 дата публикации

Integrated circuit packaging system with external wire connection and method of manufacture thereof

Номер: US20130075916A1

Автор: Daesik Choi

Принадлежит: Individual

A method of manufacture of an integrated circuit packaging system includes: providing a package carrier; mounting an integrated circuit to the package carrier; forming an external wire on the package carrier and adjacent to the integrated circuit; forming an encapsulation on the package carrier over the external wire; and forming a hole in the encapsulation with the external wire and a portion of the package carrier exposed from the encapsulation.

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Номер записи: 70

28-03-2013 дата публикации

Semiconductor Device and Method of Forming Stacked Vias Within Interconnect Structure for FO-WLCSP

Номер: US20130075924A1

Автор: Gu Yu, KANG Chen, Rui Huang, Yaojian Lin

Принадлежит: Stats Chippac Pte Ltd

A semiconductor device has a semiconductor die mounted to a carrier. An encapsulant is deposited over the semiconductor die and carrier. The carrier is removed. A first insulating layer is formed over the encapsulant and semiconductor die. First vias are formed through the first insulating layer to expose contact pads of the semiconductor die. A first conductive layer is formed over the first insulating layer and into the first vias to electrically connect to the contact pads of the semiconductor die. A second insulating layer is formed over the first insulating layer and first conductive layer. Second vias are formed through the second insulating layer by laser direct ablation and aligned or offset with the first vias to expose the first conductive layer. A second conductive layer is formed over the second insulating layer and into the second vias. Conductive vias can be formed through the encapsulant.

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Номер записи: 71

28-03-2013 дата публикации

Multi-chip semiconductor package and method of fabricating the same

Номер: US20130078763A1

Автор: Jong-Gi Lee, Kwang-Yong Lee, Min-Ho Lee

Принадлежит: SAMSUNG ELECTRONICS CO LTD

A first semiconductor chip having a first projection electrode formed on an upper surface thereof is prepared. A second semiconductor chip having a second projection electrode is mounted on the first semiconductor chip to expose the first projection electrode. An insulating film is formed between the first projection electrode and the second projection electrode. A groove is formed in the insulating film. An interconnection configured to fill an inside of the groove and connected to the first projection electrode and the second projection electrode is formed.

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Номер записи: 72

04-04-2013 дата публикации

Semiconductor integrated circuit device inspection method and semiconductor integrated circuit device

Номер: US20130082260A1

Автор: Tomonori Nakamura

Принадлежит: Hamamatsu Photonics KK

Integrated circuit layers to be stacked on top of each other are formed with a plurality of inspection rectifier device units, respectively. The plurality of inspection rectifier device units including rectifier devices are connected between a plurality of connection terminals and a positive power supply lead and a grounding lead and emit light in response to a current. After electrically connecting the plurality of connection terminals to each other, a bias voltage is applied between the positive power supply lead and the grounding lead, and the connection state between the connection terminals is inspected according to a light emission of the inspection rectifier device unit. This makes it possible to inspect, in a short time every time a layer is stacked, whether or not an interlayer connection failure exists in a semiconductor integrated circuit device constructed by stacking a plurality of integrated circuit layers in their thickness direction.

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Номер записи: 73

04-04-2013 дата публикации

Discontinuous thin semiconductor wafer surface features

Номер: US20130084686A1

Автор: Arvind Chandrasekaran

Принадлежит: Qualcomm Inc

A semiconductor wafer has a semiconductor substrate and films on the substrate. The substrate and/or the films have at least one etch line creating a discontinuous surface that reduces residual stress in the wafer. Reducing residual stress in the semiconductor wafer reduces warpage of the wafer when the wafer is thin. Additionally, isolation plugs may be used to fill a portion of the etch lines to prevent shorting of the layers.

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Номер записи: 74

11-04-2013 дата публикации

Methods of Packaging Semiconductor Devices and Structures Thereof

Номер: US20130087916A1

Автор: Jing-Cheng Lin, Jui-Pin Hung, Tsan-Hua Tung, Yi-Hang Lin

Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

Methods of packaging semiconductor devices and structures thereof are disclosed. In one embodiment, a method of packaging a semiconductor device includes providing a carrier wafer, providing a plurality of dies, and forming a die cave material over the carrier wafer. A plurality of die caves is formed in the die cave material. At least one of the plurality of dies is placed within each of the plurality of die caves in the die cave material. A plurality of packages is formed, each of the plurality of packages being formed over a respective at least one of the plurality of dies.

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Номер записи: 75

11-04-2013 дата публикации

Stacked semiconductor devices

Номер: US20130088255A1

Автор: Kevin J. Hess, Michael B. McShane, Perry H. Pelley

Принадлежит: Individual

A stacked semiconductor device includes a first and a second semiconductor device. A first major surface of each of the first and second devices which includes the active circuitry directly face each other. The first major surface of each of the devices includes a beveled edge on at least one edge, and a probe pad which extends onto the beveled edge. A first opening is located between the beveled edges of the first and second devices on a vertical side of the stacked semiconductor device.

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Номер записи: 76

25-04-2013 дата публикации

Semiconductor device and fabrication method therefore

Номер: US20130100318A1

Автор: Junji Tanaka, Kouichi Meguro, Masanori Onodera

Принадлежит: SPANSION LLC

Various embodiments of the present invention include a semiconductor device and a fabrication method therefore, the semiconductor device including a first semiconductor chip disposed on a substrate, a first sealing resin sealing the first semiconductor chip, a built-in semiconductor device disposed on the first sealing resin, and a second sealing resin sealing the first sealing resin and the built-in semiconductor device and covering a side surface of the substrate. According to an aspect of the present invention, it is possible to provide a high-quality semiconductor device and a fabrication method therefore, in which downsizing and cost reduction can be realized.

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Номер записи: 77

02-05-2013 дата публикации

Semiconductor Device and Method of Forming Interposer Frame Over Semiconductor Die to Provide Vertical Interconnect

Номер: US20130105989A1

Автор: Reza A. Pagaila, Seng Guan Chow, Seung Uk Yoon

Принадлежит: Stats Chippac Pte Ltd

A semiconductor device has a first semiconductor die mounted over a carrier. An interposer frame has an opening in the interposer frame and a plurality of conductive pillars formed over the interposer frame. The interposer is mounted over the carrier and first die with the conductive pillars disposed around the die. A cavity can be formed in the interposer frame to contain a portion of the first die. An encapsulant is deposited through the opening in the interposer frame over the carrier and first die. Alternatively, the encapsulant is deposited over the carrier and first die and the interposer frame is pressed against the encapsulant. Excess encapsulant exits through the opening in the interposer frame. The carrier is removed. An interconnect structure is formed over the encapsulant and first die. A second semiconductor die can be mounted over the first die or over the interposer frame.

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Номер записи: 78

09-05-2013 дата публикации

System in package process flow

Номер: US20130113115A1

Автор: Chien-Hsiun Lee, Tsung-Ding Wang

Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

A method comprises connecting a substrate having a plurality of integrated circuit (IC) dies to a package substrate, so that the package substrate extends beyond at least two edges of the substrate, leaving first and second edge portions of the package substrate having exposed contacts. The first and second edge portions meet at a first corner of the package substrate. At least a first upper die package is placed over the substrate, so that first and second edge portions of the first upper die package extend beyond the at least two edges of the substrate. Pads on the first and second edge portions of the first upper die package are connected to the contacts of the first and second edge portions of the package substrate.

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Номер записи: 79

09-05-2013 дата публикации

Methods of manufacturing semiconductor device assemblies including face-to-face semiconductor dice

Номер: US20130115734A1

Автор: Choon Kuan Lee, Swee Seng Eric Tan

Принадлежит: Micron Technology Inc

Methods of manufacturing semiconductor device assemblies include attaching a back side of a first semiconductor die to a substrate and structurally and electrically coupling a first end of laterally extending conductive elements to conductive terminals on or in a surface of the substrate. Second ends of the laterally extending conductive elements are structurally and electrically coupled to bond pads on or in an active surface of the first semiconductor die. Conductive structures are structurally and electrically coupled to bond pads of a second semiconductor die. At least some of the conductive structures are aligned with at least some of the bond pads of the first semiconductor die. An active surface of the second semiconductor die faces an active surface of the first semiconductor die. At least some of the conductive structures are structurally and electrically coupled to at least some of the bond pads of the first semiconductor die.

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Номер записи: 80

16-05-2013 дата публикации

Semiconductor die assemblies with enhanced thermal management, semiconductor devices including same and related methods

Номер: US20130119527A1

Автор: JIAN Li, Shijian Luo, XIAO Li

Принадлежит: Micron Technology Inc

A semiconductor die assembly comprises a plurality of semiconductor dice in a stack. Another semiconductor die is adjacent to the stack and has a region, which may comprise a relatively higher power density region, extends peripherally beyond the stack. Conductive elements extend between and electrically interconnect integrated circuits of semiconductor dice in the stack and of the other semiconductor die. Thermal pillars are interposed between semiconductor dice of the stack, and a heat dissipation structure, such as a lid, is in contact with an uppermost die of the stack and the high power density region of the other semiconductor die. Other die assemblies, semiconductor devices and methods of managing heat transfer within a semiconductor die assembly are also disclosed.

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Номер записи: 81

16-05-2013 дата публикации

Method for Forming Chip-on-Wafer Assembly

Номер: US20130119552A1

Автор: Chen-Hua Yu, Cheng-Lin Huang, Jing-Cheng Lin, Jui-Pin Hung, Shin-puu Jeng, Szu Wei Lu

Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

A device includes a bottom chip and an active top die bonded to the bottom chip. A dummy die is attached to the bottom chip. The dummy die is electrically insulated from the bottom chip.

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Номер записи: 82

16-05-2013 дата публикации

Stacked Package And Method Of Manufacturing The Same

Номер: US20130122653A1

Автор: LEE Seok-Chan, LEE Won-Hwa

Принадлежит:

In one embodiment, the method includes disposing a first chip over a package substrate. The first chip has at least one first chip pad. The method further includes forming a first bonding wire connected to the first chip pad and the package substrate, and disposing a second chip over at least a portion of the first chip. The second chip has at least one second chip bonding pad. A first bonding wire is formed electrically connected to the second chip bonding pad and the first bonding wire. 1. (canceled)2. A stacked package , comprising:a first chip disposed over a package substrate, the first chip having at least one first chip pad;a first bonding wire connecting the first chip pad and the package substrate;a second chip disposed over at least a portion of the first chip, the second chip having at least one second chip bonding pad; anda second bonding wire electrically and physically connecting the second chip bonding pad and the first bonding wire.3. The stacked package according to claim 2 , further comprising:a first protective layer covering the first chip and a second protective layer covering the second chip.4. The stacked package according to claim 3 , wherein an interface is formed between the first protective layer and the second protective layer.5. The stacked package according to claim 4 , wherein the first protective layer exposes at least a portion of the first bonding wire.6. The stacked package according to claim 5 , wherein the portion of the first bonding wire is exposed at the interface.7. The stacked package according to claim 5 , wherein the second bonding wire is directly connected to a portion of the first bonding wire claim 5 , the portion being exposed by the first protective layer.8. The stacked package according to claim 5 , wherein the portion of the first bonding wire exposed by the first protective layer has the same level with the upper surface of the first protective layer.9. A stacked package claim 5 , comprising:a first chip disposed ...

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Номер записи: 83

23-05-2013 дата публикации

Semiconductor device and manufacturing method therefor

Номер: US20130127050A1

Автор: Takehiko Maeda, Yuichi Miyagawa

Принадлежит: Renesas Electronics Corp

A semiconductor device includes a substrate having a main surface and a back surface opposite to the main surface, a first semiconductor chip having an upper surface and a lower surface opposite to the first surface with a side surface provided therebetween, the first semiconductor chip being mounted on the main surface of the substrate, a plurality of bumps provided between the main surface of the substrate and the lower surface of the first semiconductor chip, a second semiconductor chip having an upper surface and a lower surface opposite to the first surface with a side surface provided therebetween, the second semiconductor chip being mounted on the upper surface of the first semiconductor chip such that the side surface of the second semiconductor chip is positioned outward from the side surface of the first semiconductor chip.

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Номер записи: 84

06-06-2013 дата публикации

Semiconductor device and method for production of semiconductor device

Номер: US20130140699A1

Автор: Atsushi Okuyama

Принадлежит: Sony Corp

A semiconductor device with a connection pad in a substrate, the connection pad having an exposed surface made of a metallic material that diffuses less readily into a dielectric layer than does a metal of a wiring layer connected thereto.

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Номер записи: 85

20-06-2013 дата публикации

STACKED DIE IN DIE BGA PACKAGE

Номер: US20130154117A1

Автор: Chew Beng Chye, Lim Thiam Chye, Neo Chee Peng, Pour Cheng Poh, Tan Hock Chuan, Tan Michael Kian Shing, Tan Victor Cher Khng

Принадлежит: MICRON TECHNOLOGY, INC.

Die assemblies may include a first die abutting a substrate comprising a recess adjacent to the substrate. An adhesive element may be contained within the recess to attach the first die to the substrate. A height of the adhesive element may not contribute to an overall height of the die assembly. In some embodiments, a second die comprising a non-rectangular cross-sectional shape may be situated on the first die. Die assemblies ma also comprise a first die on a substrate and comprising a cavity on a side of the first die opposing a side on which the support substrate is located. A second die may be at least partially disposed in the cavity. Die assemblies may also comprise a first die secured to a substrate and partially inserted into a recess of a second die on a side opposing a side on which the substrate is located. 1. A die assembly , comprising:a first die comprising a surface abutting a substrate and recess adjacent to the substrate, wherein the recess extends from the surface into the first die and is defined by at least two sides and an end surface, an edge defining a perimeter of the recess is defined by an intersection of the at least two sides of the recess with the surface of the first die, and the perimeter of the recess does not extend to a perimeter of the first die;an adhesive element contained within the recess and attaching the first die to the substrate, wherein a height of the adhesive element does not contribute to an overall height of the die assembly; anda second die situated on the first die, the second die comprising a non-rectangular cross-sectional shape.2. A die assembly , comprising:a first die mounted to a substrate, the first die comprising a recess extending from a surface of the first die on a side opposing a side on which the substrate is located into the first die, the recess being defined by at least two sides and a bottom surface;a second die at least partially received within the recess and secured to the first die; anda third ...

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Номер записи: 86

20-06-2013 дата публикации

CHIP ON WAFER BONDER

Номер: US20130157412A1

Автор: Chiou Wen-Chih, Hung Jui-Pin, Wang Jean, Wu Weng-Jin, Yu Chen-Hua

Принадлежит: Taiwan Semiconductor Manufacturing Company, Ltd.

The present disclosure provides a bonding apparatus. The bonding apparatus includes a cleaning module designed for cleaning chips; and a chip-to-wafer bonding chamber configured to receive the chips from the cleaning module and designed for bonding the chips to a wafer. 1. A chip-to-wafer bonding method , comprising: a cleaning module designed for cleaning the plurality of chips; and', 'a chip-to-wafer bonding chamber configured to receive the plurality of chips from the cleaning module and designed to bond the plurality of chips to a wafer;, 'loading a plurality of chips to a chip-to-wafer bonding apparatus havingcleaning the plurality of chips; andbonding the plurality of chips to a wafer.2. The chip-to-wafer bonding method of claim 1 , further comprising performing a wafer level bonding to the plurality of chips bonded to the wafer in a wafer level bonding chamber integrated with the chip-to-wafer bonding apparatus.3. The chip-to-wafer bonding method of claim 1 , wherein cleaning the plurality of chips includes performing one of a wet cleaning process and a dry cleaning process.4. The chip-to-wafer bonding method of claim 1 , wherein the cleaning module is separate from the chip-to-wafer bonding chamber claim 1 , andwherein cleaning the plurality of chips includes cleaning the plurality of chips within the cleaning module by providing a cleaning gas that removes oxide from the plurality of chips and by providing a protective gas that protects the plurality of chips from oxidation occurring on the plurality of chips.5. The chip-to-wafer bonding method of claim 1 , wherein the cleaning module is separate from the chip-to-wafer bonding chamber claim 1 , andwherein cleaning the plurality of chips includes cleaning the plurality of chips within the cleaning module by providing a protective gas at a proximal portion and a distal portion of the cleaning and by providing a cleaning gas between the proximal and distal portions, wherein the cleaning gas removes oxide from ...

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Номер записи: 87

20-06-2013 дата публикации

SEMICONDUCTOR PACKAGE INCLUDING FLIP CHIP CONTROLLER AT BOTTOM OF DIE STACK

Номер: US20130157413A1

Автор: Takiar Hem, Upadhyayula Suresh

Принадлежит: SANDISK TECHNOLOGIES INC.

A semiconductor package including a plurality of stacked semiconductor die, and methods of forming the semiconductor package, are disclosed. In order to ease wirebonding requirements on the controller die, the controller die may be mounted directly to the substrate in a flip chip arrangement requiring no wire bonds or footprint outside of the controller die. Thereafter, a spacer layer may be affixed to the substrate around the controller die to provide a level surface on which to mount one or more flash memory die. The spacer layer may be provided in a variety of different configurations. 1. A method of forming a semiconductor package , comprising the steps of:(a) forming a conductance pattern on a surface of a substrate, the conductance pattern including a cluster of contact pads;(b) affixing a controller die to the surface of the substrate in a flip chip arrangement with a cluster of die bond pads on the controller die electrically coupling with the cluster of contact pads on the substrate;(c) affixing a first flash memory die directly to the surface of the substrate, the first flash memory die positioned next to the controller die;(d) affixing at least a second flash memory die on top of the controller die and first flash memory die bonded in said steps (b) and (c);(e) wirebonding the at least second flash memory die affixed in said step (d) to the substrate; and(f) encapsulating the flip chip controller die, the first flash memory die and the at least second flash memory die in a molding compound.2. A method as recited in claim 1 , said step (c) comprising the step of affixing the first flash memory die to the substrate with a flip-chip electrical bond.3. A method as recited in claim 1 , wherein said step (c) comprises mounting the flash memory die to the substrate side-by-side with the controller die.4. A method as recited in claim 3 , the step (c) of mounting a flash memory die to the substrate side-by-side with the controller die comprising the step of ...

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Номер записи: 88

04-07-2013 дата публикации

Semiconductor device having a through-substrate via

Номер: US20130168850A1

Автор: Arkadii V. Samoilov, Larry Y. Wang, Tyler Parent

Принадлежит: Maxim Integrated Products Inc

Semiconductor devices are described that include a via that extends only partially through the substrate. Through-substrate vias (TSV) furnish electrical interconnectivity to electronic components formed in the substrates. In implementations, the semiconductor devices are fabricated by first bonding a semiconductor wafer to a carrier wafer with an adhesive material. The semiconductor wafer includes an etch stop disposed within the wafer (e.g., between a first surface a second surface of the wafer). One or more vias are formed through the wafer. The vias extend from the second surface to the etch stop.

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Номер записи: 89

11-07-2013 дата публикации

Semiconductor package

Номер: US20130175702A1

Автор: Tae-Je Cho, Yun-seok Choi

Принадлежит: SAMSUNG ELECTRONICS CO LTD

A semiconductor package includes a first semiconductor package, a second semiconductor package, and a package-connecting member. The first semiconductor package includes a first substrate, a chip stacking portion disposed on the first substrate and including a plurality of first semiconductor chips, and a first sealant for surrounding the chip stacking portion on the first substrate. The second semiconductor package includes a second substrate, at least one second semiconductor chip disposed on the second substrate, and a second sealant for surrounding the second semiconductor chip on the second substrate. The package-connecting member electrically connects the first semiconductor package and the second semiconductor package. The plurality of first semiconductor chips include a first chip including through silicon vias (TSVs) and a second chip electrically connected to the first chip via the TSVs, and the chip stacking portion includes an internal sealant for filling a space between the first chip and the second chip and extending to a side of the second chip.

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Номер записи: 90

25-07-2013 дата публикации

Multi-Layer Integrated Circuit Package

Номер: US20130187211A1

Автор: Ejury Jens

Принадлежит: INFINEON TECHNOLOGIES AG

A multi-layer integrated circuit package includes a switched-mode power supply circuit including a plurality of transistors which form part of a main current loop of the switched-mode power supply circuit. The plurality of transistors are arranged in one or more layers of the integrated circuit package. The package further includes a conductive plate arranged in a different layer of the integrated circuit package than the plurality of transistors. The conductive plate is in close enough proximity to at least part of the main current loop so that a current can be electromagnetically induced in the conductive plate responsive to a change in current in the main current loop. 1. An integrated circuit package , comprising:a switched-mode power supply circuit including a plurality of transistors and a capacitor coupled together to form a main current loop having a parasitic loop inductance; anda conductive plate spaced apart from the plurality of transistors and capacitor by one or more insulator layers of the integrated circuit package, the conductive plate positioned within the integrated circuit package over at least a portion of the main current loop, the conductive plate configured to reduce the parasitic loop inductance of the main current loop without carrying current flowing in the main current loop.2. The integrated circuit package of claim 1 , wherein the conductive plate is configured to generate a magnetic field responsive to a current induced in the conductive plate by a magnetic field generated based on changes in the current flowing in the main current loop.3. The integrated circuit package of claim 1 , wherein the switched-mode power supply circuit is a power converter circuit comprising a high-side MOSFET and a low-side MOSFET claim 1 , and wherein the conductive plate is positioned over at least a portion of the high-side MOSFET and at least a portion of the low-side MOSFET.4. The integrated circuit package of claim 3 , wherein the high-side MOSFET and ...

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Номер записи: 91

25-07-2013 дата публикации

Semiconductor Packaging Structure and Method

Номер: US20130187268A1

Автор: Cheng-Ting Chen, Chun-Cheng Lin, Chung-Shi Liu, Kuei-Wei Huang, Ming-Da Cheng, Wei-Hung Lin

Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

A system and method for packaging semiconductor dies is provided. An embodiment comprises a first package with a first contact and a second contact. A post-contact material is formed on the first contact in order to adjust the height of a joint between the contact pad a conductive bump. In another embodiment a conductive pillar is utilized to control the height of the joint between the contact pad and external connections.

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Номер записи: 92

25-07-2013 дата публикации

COMPUTER READABLE MEDIUM ENCODED WITH A PROGRAM FOR FABRICATING A 3D INTEGRATED CIRCUIT STRUCTURE

Номер: US20130189813A1

Автор: Farooq Mukta G., Hannon Robert, Iyer Subramanian S., Koester Steven J., Liu Fei, Purushothaman Sampath, Young Albert M., Yu Roy R.

Принадлежит: INTERNATIONAL BUSINESS MACHINES CORPORATION

A computer readable medium encoded with a program for fabricating a 3D integrated circuit structure is provided. The program includes instructions for performing the following process. A first active circuitry layer wafer that includes active circuitry is provided, and a first portion of the first active circuitry layer wafer is removed such that a second portion of the first active circuitry layer wafer remains. Another wafer that includes active circuitry is provided, and the other wafer is bonded to the second portion of the first active circuitry layer wafer. 1. A non-transitory computer readable medium encoded with a program for fabricating a 3D integrated circuit structure , the program comprising instructions for performing the steps of:providing an interface wafer, the interface wafer including a first wiring layer and through-silicon vias;providing a first active circuitry layer wafer including active circuitry, a second wiring layer, and through-silicon vias;bonding the first active circuitry layer wafer face down to the interface wafer, the second wiring layer of the first active circuitry layer wafer being directly bonded to the first wiring layer of the interface wafer;after bonding the first active circuitry layer wafer face down to the interface wafer, removing a first portion of the first active circuitry layer wafer such that a second portion of the first active circuitry layer wafer remains attached to the interface wafer;after removing the first portion of the first active circuitry layer wafer, fabricating a third wiring layer on the second portion of the first active circuitry layer wafer;providing a second active circuitry layer wafer including active circuitry and a fourth wiring layer;bonding the second active circuitry layer wafer face down to the third wiring layer, the fourth wiring layer of the second active circuitry layer wafer being directly bonded to the third wiring layer of the first active circuitry layer wafer;after bonding the ...

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Номер записи: 93

25-07-2013 дата публикации

Design system for semiconductor device, method for manufacturing semiconductor device, semiconductor device and method for bonding substrates

Номер: US20130191806A1

Автор: Isao Sugaya, Kazuya Okamoto, Takahiro Horikoshi

Принадлежит: Nikon Corp

The terminals that oppose each other when substrates are bonded are designed to be reliably joined. Comprised in a semiconductor device design system are a numerical value acquiring part, which acquires the respective numerical values of a plurality of calculation parameters, a junction estimating part, which, in the case in which a plurality of substrates has been pressed at a prescribed pressure so that the bump front end faces come into contact, estimates whether or not the respective mutually opposing bumps will be joined based on the respective numerical values of the calculation parameters acquired by the numerical value acquiring part, and a change processing part, which, in the case in which it has been estimated by the junction estimating part that any of the bumps will not be joined, gives a warning or performs processing so as to change the numerical value of at least one calculation parameter among the plurality of calculation parameters.

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Номер записи: 94

01-08-2013 дата публикации

3d chip stack having encapsulated chip-in-chip

Номер: US20130193574A1

Автор: Kangguo Cheng, Louis Lu-Chen Hsu, Mukta G. Farooq

Принадлежит: International Business Machines Corp

A method of forming a three-dimensional (3D) chip is provided in which a second chip is present embedded within a first chip. In one embodiment, the method includes forming a first chip including first electrical devices and forming a recess extending from a surface of the first chip. A second chip is formed having second electrical devices. The second chip is then encapsulated within the recess of the first chip. Interconnects are then formed through the first chip into electrical communication with at least one of the second devices on the second chip. A three-dimensional (3D) chip is also provided in which a second chip is embedded within a first chip.

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Номер записи: 95

08-08-2013 дата публикации

Package-on-package type semiconductor packages and methods for fabricating the same

Номер: US20130200524A1

Автор: Hyun-cheol Kim, Seungchan Han

Принадлежит: SAMSUNG ELECTRONICS CO LTD

A method of forming a semiconductor package may include providing a first package including a first semiconductor chip mounted on a first package substrate having a via-hole and molded by a first mold layer, providing a second package including a second semiconductor chip mounted on a second package substrate having a connection pad and molded by a second mold layer, stacking the first package on the second package to vertically align the via-hole with the connection pad, forming a through-hole penetrating the first and second packages and exposing the connection pad, and forming an electrical connection part in the through-hole. The electrical connection part may electrically connect the first package and the second package to each other.

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Номер записи: 96

08-08-2013 дата публикации

Semiconductor Device Packaging Methods and Structures Thereof

Номер: US20130200529A1

Автор: I-Hsuan Peng, Jing-Cheng Lin, Szu Wei Lu

Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

Semiconductor device packaging methods and structures thereof are disclosed. In one embodiment, a method of packaging semiconductor devices includes coupling a plurality of second dies to a top surface of a first die, and determining a distance between each of the plurality of second dies and the first die. The method also includes determining an amount of underfill material to dispose between the first die and each of the plurality of second dies based on the determined distance, and disposing the determined amount of the underfill material under each of the plurality of second dies.

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Номер записи: 97

15-08-2013 дата публикации

Methods of of improving bump allocation for semiconductor devices and semiconductor devices with improved bump allocation

Номер: US20130207107A1

Автор: Yung-Hsin Kuo

Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

In a method of improving bump allocation for a semiconductor device and a semiconductor device with improved bump allocation, a predetermined signal bump is surrounded with at least three bumps, each being a ground bump or a paired differential signal bump.

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Номер записи: 98

15-08-2013 дата публикации

Packaging an Integrated Circuit Die

Номер: US20130207246A1

Автор: Slavov Nedyalko

Принадлежит: ST-Ericsson SA

An electronic device () comprises an integrated circuit die () mounted on a substrate (). An electrical terminal () of the integrated circuit die () is coupled to an electrical terminal () of the substrate () by means of a wire () embedded in an electrically non-conductive moulded housing (). The integrated circuit die () is also embedded in the electrically non-conductive moulded housing (). There is an electrically conductive material () on a surface () of the moulded housing (), and a connection means () for coupling the electrically conductive material () to a reference voltage. The electrically conductive material () and the substrate () in combination enclose the first integrated circuit die () and the first wire (). There is a second integrated circuit die () mounted on the first electrically conductive material () and separated from the first wire () by the first electrically conductive material (). 121-. (canceled)22. An electronic device comprising:a first integrated circuit die mounted on a substrate;a first wire coupling a first electrical terminal of the first integrated circuit die to a first electrical terminal of the substrate;a first electrically non-conductive moulded housing in which the first wire and the first integrated circuit die are embedded;a first electrically conductive material on a surface of the first electrically non-conductive moulded housing, wherein the first electrically conductive material and the substrate in combination enclose the first integrated circuit die and the first wire;first reference terminals configured to couple the first electrically conductive material to a reference voltage; anda second integrated circuit die mounted on the first electrically conductive material and separated from the first wire by the first electrically conductive material.23. The electronic device of comprising:a second wire coupling a second electrical terminal of the second integrated circuit die to a second electrical terminal of the ...

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Номер записи: 99

22-08-2013 дата публикации

Package-in-Package Using Through-Hole Via Die on Saw Streets

Номер: US20130214385A1

Автор: Byung Tai Do, Heap Hoe Kuan, Seng Guan Chow

Принадлежит: Stats Chippac Pte Ltd

A semiconductor device includes a first die having top, bottom, and peripheral surfaces. A bond pad is formed over the top surface. An organic material is connected to the first die and disposed around the peripheral surface. A via hole is formed in the organic material. A metal trace connects the via hole to the bond pad. A conductive material is deposited in the via hole. A redistribution layer (RDL) has an interconnection pad disposed over the top surface of the first die.

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Номер записи: 100