Integrierte Halbleiterschaltung mit einer Verzögerungsschaltung, die eine zu der Betriebsspannungspannung proportionale Verzögerung aufweist

Integrierter elektronischer Stromkreis

Elektronische Vorrichtung mit wenigstens einem integrierten Stromkreis

SEMICONDUCTOR DEVICE

ON BOARD INTEGRATED CIRCUIT CHIP SIGNAL SOURCE ABSTRACT OF THE DISCLOSURE

SYSTEM FOR ELIMINATING SUBSTRATE BIAS EFFECT IN FIELD EFFECT TRANSISTOR CIRCUITS

... 1452160 Integrated circuits RCA CORPORATION 7 March 1974 [23 Feb 1973] 10232/74 Heading H1K [Also in Division H3] In an integrated circuit including p channel IGFETs P10, P20 formed directly in an n type substrate 60 and n channel IGFETs N10, N20 formed in respective p type well regions 67, 70, the substrate 60 is connected to a source of reference potential V DD , each of the well regions 67, 70 is connected to a different voltage level Vi, V 2 and the source region of each IGFET is connected to the corresponding substrate or wall region in which the IGFET is located. This arrangement eliminates any reverse bias associated with the source regions while allowing different parts of the circuit to operate at different voltage levels. Fig.2 shows a circuit employing the invention, comprising three complementary inverters 10, 20, 30 which level-shift the output of logic or analogue circuit 12, operating from a 1.5 volt power source V 1 , to make it suitable to drive circuit 14, operating from ...

MULTI-FUNCTION CIRCUIT INTO BLURRED LOGIC.

Dispositif électronique comprenant au moins un circuit électronique intégré

Dispositif électronique comprenant au moins un circuit électronique intégré

Integrated circuit device having defined gate spacing and method of designing and fabricating thereof

SYSTEME INTEGRE DE PRODUCTION DE TENSION A REGULATION DU TEMPS DE MONTEE ET PROCEDE D'EXPLOITATION DE CE SYSTEME

LA PRESENTE INVENTION CONCERNE UN SYSTEME A CIRCUITS INTEGRES 10 POUR PRODUIRE UNE IMPULSION DE TENSION ELEVEE A UN NIVEAU COMMANDE ET A TEMPS DE MONTEE REGLE, COMPORTANT UN DISPOSITIF 18 DELIVRANT UN SIGNAL MULTIPHASE DE POMPAGE DE CHARGES, UN DISPOSITIF 12 DE POMPAGE DE CHARGE UTILISANT CE SIGNAL POUR DELIVRER UN POTENTIEL DE SORTIE DEPASSANT UN POTENTIEL DU SIGNAL DE POMPAGE DE CHARGES ET UN SECOND POTENTIEL DE SORTIE DEPASSANT LE POTENTIEL DE POMPAGE APPLIQUE, UN DISPOSITIF 650 LIMITANT UNE VALEUR DE REFERENCE PREDETERMINEE DU POTENTIEL DE SORTIE DU DISPOSITIF 12 DE POMPAGE DE CHARGES ET UN DISPOSITIF 354, 356 COMMANDANT LE TEMPS DE MONTEE DU POTENTIEL DE SORTIE PAR COMMANDE DE LA CADENCE DE CHARGE DU DISPOSITIF 12 DE POMPAGE DE CHARGES. APPLICATION NOTAMMENT A LA COMMANDE DE SYSTEMES DE MEMOIRES REMANENTES A CIRCUITS INTEGRES.

INTEGRATED SYSREME POWER SUPPLY

MONOLITHIC SEMICONDUCTOR CIRCUIT ARRANGEMENT

Electronic device including/understanding at least an integrated electronic circuit

IMPROVEMENTS WITH THE LOGICAL DOORS HAS TRANSISTORS MOS MULTIDRAINS

PERFECTIONNEMENTS AUX PORTES LOGIQUES A STRUCTURE INTEGREE MOS

LA PORTE COMPREND UN TRANSISTOR DE CHARGE 40 DONT LA SOURCE EST RELIEE A LA GRILLE 43 DE PLUSIEURS TRANSISTORS DE COMMANDE A STRUCTURE INTEGREE MOS MONOCANAL. LES SOURCES 44 ET LES DRAINS 45 DES TRANSISTORS SONT MENAGES A UN PREMIER NIVEAU D'IMPLANTATION SUR UN SUBSTRAT SEMI-CONDUCTEUR, LES GRILLES 43 DES TRANSISTORS INVERSEURS CONSTITUENT, AVEC LA GRILLE DU TRANSISTOR DE CHARGE 40, UNE ZONE UNIQUE SITUEE A UN SECOND NIVEAU D'IMPLANTATION SEPARE PAR UNE COUCHE ISOLANTE MINCE DU PREMIER NIVEAU, ET UN CONTACT OHMIQUE EST MENAGE DU PREMIER AU SECOND NIVEAU ENTRE LA GRILLE ET LA SOURCE DU TRANSISTOR DE CHARGE 40 DONT LA GRILLE EST CONSTITUEE PAR UNE PARTIE TERMINALE DE LADITE ZONE UNIQUE.

Number 1 voltage boosting an integrated circuit with circuits

Integrated circuit

An integrated circuit includes a first standard cell having a first pFET and a first nFET integrated, and having a first dielectric gate on a first standard cell boundary. The integrated circuit further includes a second standard cell being adjacent to the first standard cell, having a second pFET and a second nFET integrated, and having a second dielectric gate on a second standard cell boundary. The integrated circuit also includes a first filler cell configured between the first and second standard cells, and having a one-pitch dimension P. The first pFET and the second pFET are formed on a first continuous active region. The first nFET and the second nFET are formed on a second continuous active region. The first filler cell includes a third dielectric gate on a first filler cell boundary and a fourth dielectric gate on a second filler cell boundary.

SEMICONDUCTEUR INTEGRATED CIRCUIT

A semiconductor integrated circuit in which an external power source voltage is received from outside a semiconductor chip via external power source terminals, the external power source voltage is dropped through voltage-dropping means provided in the semiconductor chip, and the dropped voltage is supplied as an internal power source voltage to the semiconducteur chip, wherein a plurality of voltage-dropping means are provided for a plurality of semiconductor circuit blocks in the semiconductor chip respectively, in order to effectively suppress the voltage change of the internal power source in operation circuits requiring large currents.

Gate array integrated device having mixed single column type and matrix type arrays

A gate array integrated device including a plurality of single column type arrays, a plurality of matrix type arrays such as double column type arrays (BC2), and longitudinal connection areas (CH) provided between the single column type arrays and the matrix type arrays. One of the single column type arrays facing at least one side of each of the matrix type arrays.

INTEGRABLE IGFET CIRCUIT

Power supply decoupling mechanism for integrated circuits

An integrated circuit is formed in a semiconductor chip and connected to at least a first source of voltage and at least a second source of voltage, negative with respect to the first source of voltage. A number of integrated circuit components are activated by the first and second sources of voltage and are interconnected to provide desired functions. An integrated circuit capacitive element in the form of the gate capacitance of a field effect transistor and in the form of a reversed biased diode is connected between the first and second sources of voltage to decouple integrated circuit inherent inductance in series with the first and second sources of voltage.

Full swing power down buffer circuit with multiple power supply isolation

A full swing CMOS output buffer circuit (20,30,40,50) isolates incompatible power supply circuits such as 3.3 v standard and 5 v standard subcircuits, and isolates power supply rails of quiet or powered down buffer circuits from the common external bus. The pullup output transistor (PMOS1) is fabricated in a well (NWELL) of N type carrier semiconductor material formed in a substrate (PSUB) of P type carrier semiconductor material. A P channel NWELL isolation switch transistor (PW1) has a primary current path coupled between the well (NWELL) and high potential power rail (VCC) and a control gate node coupled to the control gate node of the pullup output transistor (PMOS1) for operating substantially in phase. The NWELL isolation switch transistor (PW1) isolates the pullup output transistor (PMOS1) well (NWELL) from the high potential power rail (VCC). An N channel control node isolation transistor (N1) has a control node coupled to the high potential power rail (VCC) for isolating the control ...

MOSFET and Memory Cell Having Improved Drain Current Through Back Bias Application

A semiconductor metal-oxide-semiconductor field effect transistor (MOSFET) transistor with increased on-state current obtained through intrinsic bipolar junction transistor (BJT) of MOSFET has been described. Methods of operating the MOS transistor are provided. 1. A semiconductor device configured to function as a semiconductor memory device or a transistor with increased on-state drain current , said semiconductor device comprising:a substrate having a first conductivity type selected from p-type conductivity type and n-type conductivity type;a buried layer having a second conductivity type selected from said p-type conductivity type and said n-type conductivity type and being different from said first conductivity type;a body having said first conductivity type;a source region and a drain region each having said second conductivity type and being separated by said body; anda gate positioned in between said source region and said drain region;wherein said semiconductor device is configured to function as a memory device having at least two stable states, or as a transistor with increased on-state drain current, but with no change in off-state drain current, depending on biases that are applied to said semiconductor device.2. The semiconductor device of claim 1 , wherein whether said semiconductor device functions as said memory device having at least two stable states claim 1 , or as said transistor with increased on-state drain current claim 1 , but with no change in off-state drain current is governed by an amount of voltage applied to said buried layer.3. The semiconductor device of claim 1 , wherein a relatively low voltage applied to said buried layer governs said semiconductor device to function as a MOSFET (metal-oxide-semiconductor field effect transistor) and wherein a relatively high voltage applied to said buried layer governs said semiconductor device to function as said memory device having at least two stable states.4. The semiconductor device of ...

BIAS VOLTAGE GENERATION CIRCUIT FOR AN SOI RADIO FREQUENCY SWITCH

Voltage divider for high-speed high-precision signal converting unit

A voltage divider comprises a string of resistive elements (RN0 to RNn) implemented by an elongated n-type impurity region (14) formed in a lightly doped p-type semiconductor substrate (11), and n-channel type switching transistors (QN1 to QNn) with a short channel length formed in a heavily doped p-type well (12) in the semiconductor substrate and associated with the resistive elements for coupling one of the associated resistive elements to an output node (OUT). The lightly doped semiconductor substrate (11) decreases parasitic capacitance coupled to the elongated n-type impurity region (14) so that the string of the resistive elements is improved in propagation speed and bias dependency. ...

Semiconductor for integrated device including a power supply voltage conversion circuit and protection means

SEMICONDUCTOR INTEGRATED CIRCUIT

PURPOSE: To obtain an IC which works stably with a high level of power supply voltage by providing a voltage limiter circuit containing a specific element into a chip of a semiconductor IC and applying the voltage of an external power supply to some circuit after dropping down the voltage. CONSTITUTION: For a chip 10 of a semiconductor IC, a minute element is used for a circuit A which decides the substantial integration density and an element of a comparatively large size is used for a driving circuit B containing an input/output interface, for example, which does not contribute so much to the integration density. Then the external power supply voltage VCC is applied to actuate the chip 10. In this case, the circuit A works on the voltage VL obtained by dropping down the voltage VCC by a voltage limiter 13. Said voltage limiter is controlled by an element, e.g., an MOS transistor which responds to the output voltage of a circuit containing an element having rectifying characteristics with ...

SEMICONDUCTOR DEVICE

PURPOSE:To reduce an area on a wafer required to obtain a capacitance value identical to the conventional capacitance by a method wherein a groove is made in a silicon substrate, the substrate is used as a first electrode for the capacitance, an insulating film is formed on side walls and a bottom face of the groove made in the substrate, the groove is filled with a conductor and the conductor is used as a second electrode for the capacitance. CONSTITUTION:A groove is made in a silicon substrate 1; the substrate 1 is used as a first electrode 6 for the capacitance; an insulating film 7 is formed on side walls and a bottom face of the groove made in the substrate 1; the groove is filled with a conductor; this conductor is used as a second electrode 8 for the capacitance. Although an area for the formed capacitance by piling up the first electrode 6 and the second electrode 8 is large, a plane area on the wafer 1 is small. By this setup, it is possible to obtain a high-capacitance value even ...

USING METHOD FOR SEMICONDUCTOR DEVICE

PURPOSE: To increase the withstanding voltage of an element of a semiconductor device by fixing the electrical potential of a second semiconductor substrate higher than a minimum potential inside the element region of a first semiconductor substrate. CONSTITUTION: A composite semiconductor substrate is fabricated wherein an N-type first semiconductor substrate 12 and an N-type second semiconductor substrate 11 are interconnected together with an oxidizing film 13 sandwiched therebetween. A separation channel 5, which is made up of an insulating material, is provided in such a manner as to start from the main surface of the first semiconductor substrate 12, to proceed to the oxidizing film 13, and to surround an element region 14. The electrical potential of the second semiconductor substrate 12, which depends on the thickness of the element region 14, is fixed higher than a minimum potential inside the element region 14 of the first semiconductor substrate 11. Thereby, the field strength ...

Halbleiterspeichereinrichtung mit einer Komponente mit verbesserten Durchschlagsspannungseigenschaften

Integrierte Halbleiterschaltungsanordnung

Semiconductor device with reduced-noise output buffer

The current supply lines (142a,b) and earthing lines (14a,b) are separately provided for an internal circuit (102) and an output buffer circuit (104). A stabilising capacitor (C1) is fitted only between current supply and earthing lines for the internal circuit. If no capacitive coupling exists between the current supply and earthing lines for the output buffer circuit, while during the latter operation a current supply noise is generated and its current supply voltage is reduced, the earthing voltage is not reduced and held constant, thus the current supply noise generated during the output buffer circuit operation affects another internal circuit.

HALBLEITERCHIP

Gemäß einer Ausführungsform ist ein Halbleiterchip beschrieben, der Folgendes umfasst: einen Chip mit wenigstens einen p-Kanal-Feldeffekttransistor (FET), wenigstens einem n-Kanal-FET, einem ersten und einem zweiten Leistungsversorgungsanschluss, wobei der wenigstens eine n-Kanal-FET, falls er mit dem oberen Versorgungspotential an seinem Gate versorgt wird, das untere Versorgungspotential an das Gate des wenigstens einen p-Kanal-FET liefert, und der wenigstens eine p-Kanal-FET, falls er mit dem unteren Versorgungspotential an seinem Gate versorgt wird, das obere Versorgungspotential an das Gate des wenigstens einen n-Kanal-FET liefert, einen Vorladungsschaltkreis, der zum Vorladen des Schaltkreises in einen ersten Zustand konfiguriert ist, in dem das Potential an dem Gate des wenigstens einen n-Kanal-FET niedriger als das obere Versorgungspotential ist und das Potential an dem Gate des wenigstens einen p-Kanal-FET höher als das untere Versorgungspotential ist, und einen Detektionsschaltkreis ...

SEMICONDUCTOR MEMORY DEVICES

IGFET with controlled gate threshold voltage

An IGFET, which may be in the form of a thin film transistor, has a bias element 30 and a capacitive element 40. A potentiual for controlling the gate threshold voltage is applied to the bias element whilst a signal of the same phase is supplied to the capacitive element. The bias element is either directly adjacent to the channel region or in the form of an additional second gate (figure 12A).

Connections in semiconductor memory devices

PURPOSE: To provide a method for wiring power and ground line for preventing the formation of a noise path, due to a parasitic impedance component induced between the power lines or ground lines of the input edge and output edge of a semiconductor memory device. CONSTITUTION: Rather a power line 43 of an output edge, a power line 42 of another circuit is tap-processed to an (n)<+> -guard ring region, with which a power line 45 of an input edge is brought into contact.

SEMICONDUCTOR DEVICE HAVING PREVENTIVE MEANS AGAINST ERRORS

This invention relates to a semiconductor device formed on a semiconductor chip which is provided with at least a voltage transformation arrangement for transforming an external power supply voltage into an internal power supply voltage. At least a portion of circuits formed in the chip operate by using the internal power supply voltage rather than the external power supply voltage. Semiconductor devices, in particular DRAMs (dynamic random access memories), in which said internal power supply voltage is supplied are controlled so that the starting time of the internal power supply voltage at the moment of the switch-on of the external power supply is later than the starting time of the external power supply voltage, and/or the time necessary for the internal power supply voltage to increase to a predetermined operational level at said moment is longer than that required for said external power supply voltage to increase to a predetermined operational level.

SEMICONDUCTOR INTEGRATED CIRCUITS

Semiconductor structures

A semiconductor structure for use in logic circuits comprising a planar insulated- gate field-effect transistor (5- 13) and at least one V-groove insulated- gate field-effect transistor 23-33 formed on a common substrate (1, 3) the drain of the V-groove transistor being constituted by a region (23 or 25) of the same conductivity type as the substrate formed within the drain region (7) of the planar transistor so that the substrate forms the V-groove transistor source region and part (31 or 33) of the drain region of the planar transistor forms the V-groove transistor channel region. The structure is adapted for use as a so- called integrated-injection logic (I<2>L) structure. ...

Integrated rise time regulated voltage generator systems

... integrated circuit system for generating a rise time regulated and level controlled high voltage pulse utilizing a plurality of diode-connected stages driven by capacitively coupled low voltage clocks phi 1, phi 2. The maximum output voltage at 200, may be controlled by a gated diode reference device 650, which provides a reference voltage independent of power supply voltage. A feedback circuit VFB may be provided which controls the high voltage rise time by modulating the effective low voltage clock amplitude driving the high voltage generator. A MOS logic level interface circuit may also be provided for sensing achievement of the predetermined high voltage level. ...

SEMICONDUCTOR INTEGRATED CIRCUITS

LOW-VOLTAGE ELEMENT IN A SUBSTRATE FOR HIGH TENSIONS

INTEGRATED CMOS CIRCUIT

SYSTEM FOR ELIMINATING SUBSTRATE BIAS EFFECT IN FIELD EFFECT TRANSISTOR CIRCUITS

MOS I/O PROTECTION USING SWITCHED BODY CIRCUIT DESIGN

MOS I/O PROTECTION USING SWITCHED BODY CIRCUIT DESIGN Switched body circuitry is provided to prevent a system I/O from being effected by the loss of power supply or ground to an MOS integrated circuit within the system. A semiconductor substrate of a first conductivity type has formed therein a well region of a second conductivity type opposite to that of the first conductivity type. First, second, third and fourth spaced-apart shallow diffusion regions of the first conductivity type are formed at the surface of the well region. The first and fourth of these regions are electrically connected to the well region through ohmic contacts. A first gate electrode, which overlies a first channel region between the second diffusion region and the third diffusion region, is connected to provide the proper logic function on the data line. This first gate electrode and the second and third diffusion regions combine to form an MOS transistor which is either an input pull up or pull down device or an ...

INTEGRABLE CIRCUIT FOR MONITORING A SUPPLY VOLTAGE

INTEGRATED CIRCUIT RESISTANCE VDMOS/LOGIC COMPRISING A VERTICAL TRANSISTOR AND A ZENER DIODE [...]

CARRY LOGICAL HAS TRANSISTOR MOS MULTIDRAIN

INTEGRATED CIRCUIT VDMOS/LOGIQUE INCLUDING/UNDERSTANDING A VERTICAL TRANSISTOR DEPLETE AND A ZENER DIODE

Optimized power bus structure

An arrangement for providing power to a semiconductor array of cells on a substrate in which the metal 2 power conductors are truncated into short lengths sufficient only to reach between the metal 1 power conductors of adjacent rows of cells, the metal 2 power conductors are placed under the metal 4 power conductors at each side to reduce the current through the metal 3 power conductors, and the metal 3 power conductors are narrowed to the level necessary to carry the reduced current and placed adjacent upper or lower edges of the cells. The arrangement increases the amount of space available for access to the external connection nodes of the devices in the cells of a group on a substrate while reducing the size of the metal overlays necessary to carry power to the cells.

Low-power comparator which tolerates high-slew-rate incoming signals and deriving power from the incoming signals

An integrated circuit which includes switching logic to select its negative power supply voltage from the more negative of two signals (preferably ground and an input signal). Special MOS clamp diodes are used to prevent sharp transients from collapsing the voltage drop of the internal power supply lines (and so disabling the chip).

INTEGRATED CIRCUIT AND SYSTEM OF MANUFACTURING THE SAME

An integrated circuit includes a first and second set of gate structures. A center of each of the first set of gate structures is separated from a center of an adjacent gate of the first set of gate structures in a first direction by a first pitch. A center of each of the second set of gate structures is separated from a center of an adjacent gate of the second set of gate structures in the first direction by the first pitch. The first and second set of gate structures extend in a second direction. A gate of the first set of gate structures is aligned in the second direction with a corresponding gate of the second set of gate structures. The gate of the first set of gate structures is separated from the corresponding gate of second set of gate structures in the second direction by a first distance.

Semiconductor device with electromagnetic radiation reduced

In a semiconductor device in which power is supplied from an external power supply system, a first power supply system (11, 12) is connected to first terminals (1, 2) of power supply and ground and a digital inner circuit (8). The inner circuit (8) includes a clock signal generating circuit, a driver for the clock signal, and circuits operating in response to the clock signal. A second power supply system (13, 14) is connected to second terminals (3, 4) of power supply and ground, the input terminal (6), the output terminal (5), and a digital interface circuit (9). The second power supply system (13, 14) is independent of the first power supply system (11, 12). The interface circuit (9) includes a MOS transistor (7) for pulling up or down the input terminal (6) and an output circuit which includes a MOS transistor driving a output terminal. The first power supply system (11, 12) is separated from the second power supply system (13, 14), and the inner circuit (8) is connected to the interface ...

SEMICONDUCTOR MEMORY DEVICE

PURPOSE: To improve the reliability of capacity for stabilizing a high voltage for word wire driver. CONSTITUTION: In a semiconductor memory device containing a step-up circuit 400 constantly generating a high voltage and a word wire drive circuit (WDi) for transmitting a high voltage from the step-up circuit to a selection word wire 3, the capacitor for stabilizing the high voltage generated by the step-up circuit is made of a series body of a capacitive element utilizing FET having a gate insulation film thickness equivalent to an insulation gate type field effect transistor (FET) within the memory device. COPYRIGHT: (C)1994,JPO&Japio ...

SOI (Silizium auf Isolator)-Logikschaltung mit niedriger Spannung

Bezugsspannungsgeneratorschaltung mit Temperaturkompensation der Ausgangsspannung

VOLTAGE GENERATOR SYSTEMS

PROCEDURE FOR THE CONTROL OF A FIELD-EFFECT TRANSISTOR

INTEGRATED CIRCUIT IN COMPLEMENTARY CIRCUIT TECHNOLOGY WITH A SUBSTRATE PRE-LOADING A GENERATOR AND A SCHOTTKY DIODE.

TRANSVERSE FILTER HAS TRANSFER OF CHARGE ELECTRIC

IMPROVEMENTS WITH THE LOGICAL DOORS HAS TRANSISTORS MOS MULTIDRAINS

INTEGRABLE CIRCUIT FOR MONITORING A SUPPLY VOLTAGE

ROW DECODER AND DRIVER WITH SWITCHED-BIAS BULK REGIONS

A row decoder/driver circuit (300) in which switched bias voltages are applied to the bulk regions in order to minimize the maximum voltage differential appearing across transistor devices. This allows the decoder/driver circuit to be conveniently fabricated and designed to allow normal transistors rather than more complex and expensive high voltage transistors, to form the row decoder/driver. The bulk regions (310, 311) containing the pull-up (307) and pull-down (308, 309) transistors are biased by voltages which are switched during erasure depending on wether the row line (305) is selected or deselected in order to assure that excessive voltages do not appear across the transistors based upon the voltage levels applied to them.

Semiconductor device for reducing effects of noise on an internal circuit

Semiconductor device according to the present invention includes package frame, bonding wire, pad, first internal power supply line, second internal power supply line, internal circuit, stabilize circuit, GND package frame, GND bonding wire, GND pad, and internal GND line. Bonding wire, pad, and first and second internal power supply lines function as a filter. As a result, noise generated by operation of the internal circuit is absorbed in propagating to the stabilize circuit through first internal power supply line, pad, and the second internal power supply line. Therefore, effects of noise given to the stabilize circuit are small.

Programmable integrated circuit having metal plate capacitors that provide local switching energy

Certain digital logic elements within the core of a field programmable integrated gate array (FPGA) require relatively large spikes of supply current when they switch. Local integrated metal plate bypass capacitors are provided in the core of the FPGA near the digital logic elements. The local integrated bypass capacitors provide the digital logic elements with a substantial portion of the required spikes of supply current. The magnitude of supply current spikes drawn over resistive and/or inductive power leads from the edges of the FPGA is therefore reduced and associated drops in supply voltage at the core are reduced.

Integrated logic circuit having insulated gate field effect transistors

A semiconductor device includes insulated gate field effect transistors, with which logic gate circuits having a satisfactory switching speed and a high packing density can be realized. The logic gate circuits are composed of transistor structures having a common source zone (22), which each comprise a gate (33), a second semiconductor zone (25) and one or more drain zones (28) and are manufactured in DMOS technology. The gates are strip-shaped or have at least a strip-shaped part. The gate circuits can be integrated in a simple manner with one or more high-voltage transistors manufactured in DMOS technology.

Lay-out structure of power source potential lines and grand potential lines for semiconductor integrated circuit

Among power supply lines for the standard cells provided nearby the corner part of an outer peripheral power supply line (the grand potential, for example) of a macro cell, the power supply line of the power source potential, for example, is connected to an inner peripheral power supply line (the power source potential) through an auxiliary power supply line provided on said corner part. The auxiliary power supply line is formed in L-shape with the first metal layer line and the perpendicular extending second metal layer line connected each other through a contact. Further, the first metal layer line of the auxiliary power supply line is provided so as to cross over the second metal layer line of the outer peripheral power supply line with an insulating layer therebetween. Therefore, the auxiliary power supply line can connect the inner peripheral power supply line and the power source potential line for the standard cell without electrical contact with the outer peripheral power supply ...

BODY-BIAS VOLTAGE ROUTING STRUCTURES

Body-bias voltage routing structures. In an embodiment, doped well structures distribute body biasing voltages to a plurality of body biasing wells of an integrated circuit. 1. A semiconductor device comprising:two physically separate conductive regions beneath a surface of the semiconductor device configured to route a body-bias voltage; anda conductive structure above the surface configured to couple the two conductive regions.2. The semiconductor device of claim 1 , wherein each conductive region has an N-type doping.3. The semiconductor device of claim 1 , wherein each conductive region has a P-type doping.4. The semiconductor device of claim 1 , wherein each conductive region has a strip shape.5. The semiconductor device of claim 1 , wherein the metal structure has a metal wire shape.6. The semiconductor device of claim 1 , wherein the metal structure passes over a region of a second conductivity type.7. A semiconductor device comprising:two physically separate conductive deep well regions of first conduction type beneath a surface of the semiconductor device that do not reach the surface, configured to route a body-bias voltage;a conductive region of the first conduction type above each of the conductive deep well regions coupling each of the conductive deep well regions to said surface; anda conductive structure above the surface configured to couple the two conductive regions.8. The semiconductor device of claim 7 , wherein each deep well has an N-type doping.9. The semiconductor device of claim 7 , wherein each deep well has a P-type doping.10. The semiconductor device of claim 7 , wherein at least one of the deep wells has a strip shape.11. The semiconductor device of claim 7 , wherein the conductive structure has a metal wire shape.12. The semiconductor device of claim 7 , wherein the conductive structure passes over a well of a second conductivity type.13. A semiconductor device comprising:two conductive regions of a first conductivity formed beneath a ...

SEMICONDUCTOR WAFER

PURPOSE: To widen the wiring width of a power supply line and a grounding line while preventing a short circuit between the lines. CONSTITUTION: A large number of integrated-circuit forming regions, in which integrated circuits are formed, are arranged on a semiconductor wafer. A silicon oxide film 5 is formed onto a silicon substrate 4, and a conductor 6 for a grounding line is formed onto the silicon oxide film 5. The conductor 6 for the grounding line is extended on a scribing line. An inter-layer insulating film 7 consisting of the silicon oxide film is laminated on the silicon oxide film 5 containing the upper section of the conductor 6 for the grounding line, and a conductor 8 for a power supply line is formed onto the inter-layer insulating film 7. The conductor 8 for the power supply line is extended on the scribing line. A pad 10 for a power supply and the conductor 8 for the power supply line are connected electrically in an integrated-circuit forming region. A pad for grounding ...

Verfahren zum Herstellen einer Mehrzahl von Transistoren in einem Substrat

Semiconductor storage (memory) device

Published without abstract.

Monolitisch integrierte Leistungsschaltung in Semibrückenkonfiguration, insbesondere für die Steuerung elektrischer Motoren

Halbleiteranordnung und Verfahren zur Erhöhung der Durchbruchspannung einer Halbleiteranordnung

Vorrichtung zur Erzeugung eines Zwischenpotentials, insb. geeignet für Halbleiterspeichereinrichtungen

Halbleiterwafer zum Durchführen eines Burn-In-Tests

Halbleiterwafer mit: einer Mehrzahl von Chipbereichen (2), die in einem Halbleiterwafer (1) angeordnet sind, wobei jeweilige Chipbereiche (2) eine integrierte Schaltung aufweisen; einem Schneidelinienbereich (3), der zwischen den Chipbereichen (2) angeordnet ist; und einer Energieversorgungsleitung (8) und einer Masseleitung (6) zum Zuführen von Energie zu den jeweiligen Chipbereichen (2) während eines Burn-In-Testens, wobei die Energieversorgungsleitung (8) und die Masseleitung (6) in den Schneidelinienbereichen (3) ausgebildet und an die jeweiligen Chipbereiche (2) angeschlossen sind, dadurch gekennzeichnet, dass die Energieversorgungsleitung (8) und die Masseleitung (6) sich gegenseitig in vertikaler Richtung überlappen; und mindestens die Energieversorgungsleitung (8) oder die Masseleitung (6) einen Bereich hoher Störstellenkonzentration aufweist, der auf der rückseitigen Oberfläche des Wafers ausgebildet ist.

SUPPLY VOLTAGE ADJUSTING CIRCUIT OF A FIELD EFFECT TYPE SEMICONDUCTOR DEVICE

ELECTRICAL ISOLATION IN INTEGRATED CIRCUITS

... 2124687 9409515 PCTABS00032 A back biasing technique is provided for increasing the field inversion voltage between adjacent MOS transistors and for reducing parasitic capacitances in an integrated circuit. The use of a charge pump is avoided by connecting the body portion (11) of the MOS transistors to ground and the sources (22) of the MOS transistors to the anode (27) of a diode, the cathode (26) of which are connected to a reference voltage such as to ground. In this manner, the sources are back biased relative to the material in which they are formed by a diode forward voltage drop. This technique is particularly applicable to CMOS circuits operating form a 3.3 volt supply, with p-well (15) doping densities in excess of 1x1017 atoms/cm3.

JUST SYSTEM OF PRODUCTION OF TENSION HAS REGULATION OF the BOARDING TIME AND PROCESS Of OPERATION OF THIS SYSTEM

LA PRESENTE INVENTION CONCERNE UN SYSTEME A CIRCUITS INTEGRES 10 POUR PRODUIRE UNE IMPULSION DE TENSION ELEVEE A UN NIVEAU COMMANDE ET A TEMPS DE MONTEE REGLE, COMPORTANT UN DISPOSITIF 18 DELIVRANT UN SIGNAL MULTIPHASE DE POMPAGE DE CHARGES, UN DISPOSITIF 12 DE POMPAGE DE CHARGE UTILISANT CE SIGNAL POUR DELIVRER UN POTENTIEL DE SORTIE DEPASSANT UN POTENTIEL DU SIGNAL DE POMPAGE DE CHARGES ET UN SECOND POTENTIEL DE SORTIE DEPASSANT LE POTENTIEL DE POMPAGE APPLIQUE, UN DISPOSITIF 650 LIMITANT UNE VALEUR DE REFERENCE PREDETERMINEE DU POTENTIEL DE SORTIE DU DISPOSITIF 12 DE POMPAGE DE CHARGES ET UN DISPOSITIF 354, 356 COMMANDANT LE TEMPS DE MONTEE DU POTENTIEL DE SORTIE PAR COMMANDE DE LA CADENCE DE CHARGE DU DISPOSITIF 12 DE POMPAGE DE CHARGES. APPLICATION NOTAMMENT A LA COMMANDE DE SYSTEMES DE MEMOIRES REMANENTES A CIRCUITS INTEGRES. THE PRESENT INVENTION CONCERNS A SYSTEM WITH INTEGRATED CIRCUITS 10 FOR PRODUCING A HIGH VOLTAGE PULSE AT A CONTROL LEVEL AND AT A SET RISE TIME, INCLUDING A DEVICE 18 DELIVERING A MULTIPHASE LOAD PUMPING SIGNAL, A LOAD PUMPING DEVICE 12 SIGNAL TO DELIVER AN OUTPUT POTENTIAL EXCEEDING A POTENTIAL OF THE LOAD PUMPING SIGNAL AND A SECOND OUTPUT POTENTIAL EXCEEDING THE APPLIED PUMPING POTENTIAL, A 650 DEVICE LIMITING A PREDETERMINED REFERENCE VALUE OF THE LOADING POTENTIAL AND 12 POTENTIAL DEVICE A DEVICE 354, 356 CONTROLLING THE RISE OF THE OUTPUT POTENTIAL BY CONTROL OF THE LOAD RATE OF THE LOAD PUMPING DEVICE 12. APPLICATION IN PARTICULAR TO THE CONTROL OF REMANENT MEMORY SYSTEMS WITH INTEGRATED CIRCUITS.

MONOLITHIC SEMICONDUCTOR CIRCUIT ARRANGEMENT

IMPROVEMENTS WITH THE LOGICAL DOORS HAS STRUCTURE INTEGREE MOS

sHIFT REGISTER ARRANGEMENT

CIRCUIT INTEGRE D'ALIMENTATION EN COURANT

L'invention se rapporte à un circuit intégré d'alimentation en courant. Il comporte cqmme interrupteur de courant un élément lambda réalisé selon la technique du canal unique et constitué par deux transistors à effet de champ. La partie inverseuse de l'élément lambda est montée en parallèle sur l'entrée du circuit, alors qu'un condensateur de lissage et situé du côté de la sortie, en série avec le transistor représentant l'interrupteur, est relié aux bornes terminales de l'inverseur. Application aux circuits à semi-conducteurs à alimentation en courant intégré.

Integrated circuit and manufacturing method of the same

Semiconductor integrated circuit device

A semiconductor integrated circuit device which substantially reduces drop in a supply voltage generated by a regulator and ensures stable supply of a supply voltage with high efficiency and high accuracy. In the device, a memory power supply includes a plurality of transistors and an error amplifier. In the transistors, source pads and drain pads are alternately arranged in a row along one edge of a semiconductor chip in a peripheral area of the chip. Transistor gates are formed in parallel with the alternately arranged source pads and drain pads (so that the longitudinal direction of the gates is parallel to the direction of the arrangement of the source pads and drain pads). Consequently, the length of wirings coupled to drains and sources is shortened and the sheet resistance is decreased.

MOS LOGIC IN BICMOS CIRCUITS

In BICMOS circuits, the complementary MOS logic requires more transistor functions than does a I2L logic in bipolar circuits. By means of an improved MOS gate structure similar to that of I2L (CWL logic), the space requirements of the MOS logic are considerably reduced, while maintaining the noise-voltage sensitivity at the same level as in prior art CMOS logics. Because of the slower logic behaviour, the analog circuit structures are exposed to lower levels of noise radiation.

Power supply wiring for semiconductor device

Ground lines 2 are disposed so as to sandwich a power supply line 1. A gate oxide film 3 and a gate 4 are formed below the power supply line 1. An n-type area 8 is formed adjacent to the end of the gate oxide film to set the ground potential thereto. A p-type area 9 is formed at most of the remaining part below the ground line to make it contact the substrate. Since the potential of the gate equals that of the power source, an inversion layer is formed below the oxide film, where the ground potential results through the n-type area. By sandwiching the gate oxide film between the gate and the inversion layer, a capacitor is formed. The size of the capacitor is half in length as large as the width of the power supply wiring, and the width substantially equals the length of the power supply wiring, the parasitic resistance generated at the gate or inversion layer is suppressed small, and the gate capacitance approximately corresponding to the area of master power supply wiring is interposed ...

Semiconductor integrated circuit

In order to permit reduced component size without reduction of an external power supply voltage, a semiconductor integrated circuit includes at least three circuits. The first of these three circuits converts the external power source voltage to an internal power source voltage which is smaller than the external power voltage. A second circuit is supplied with the external power source voltage and is responsive to first signals which regulate an operation of the integrated circuit. This second circuit generates second signals which control the integrated circuit so that the integrated circuit performs the desired regulated operation. To carry this out, the second circuit includes at least first transistors which are supplied with the external power source voltage and responsive to the first signals. The second signals generated by the second circuit have amplitudes smaller than those of the first signals. The third circuit is supplied with the internal power source voltage and responsive ...

Low voltage device in a high voltage substrate

A semiconductor or substrate of a first conductivity type includes a well structure of a second conductivity type formed therein. A first low voltage MOS transistor includes spaced apart source and drain regions of the first conductivity type in the well. A first transistor gate lies above a channel region which is disposed between the source and drain regions of the first low voltage MOS transistor and is separated therefrom by a gate dielectric having a first thickness. A second high voltage transistor includes spaced apart source and drain regions of the first conductivity type in the well. A second transistor gate lies above a channel region which is disposed between the source and drain regions of the second high voltage transistor and is separated therefrom by a gate dielectric having a second thickness which is greater than the thickness of the gate dielectric of the first low voltage MOS transistor. A first contact diffusion, having the same conductivity type as the well, is located ...

Semiconductor integrated circuit device

A semiconductor integratedd circuit device adopting a master slice scheme, having a cell array in which basic cells are arrayed in a matrix shape and on which first power source wiring lines, second power source wiring lines and third power source wiring lines are respectively stacked in succession from a lowermost layer toward an uppermost layer, the first power source wiring lines and the third power source wiring lines being both extended in a column direction while the second power source wiring lines are extended in a row direction; wherein second contact holes for connecting the second power source wiring line and the third power source wiring line are arranged, when viewed in plan, around first contact holes for connecting the first power source wiring line and the second power source wiring line, in a region in which the first power source wiring line, the second power source wiring line and the third power source wiring line intersect. The second contact holes are not arranged ...

Integrated Standard Cell Structure

An integrated circuit includes a first standard cell having a first pFET and a first nFET integrated, and having a first dielectric gate on a first standard cell boundary. The integrated circuit further includes a second standard cell being adjacent to the first standard cell, having a second pFET and a second nFET integrated, and having a second dielectric gate on a second standard cell boundary. The integrated circuit also includes a first filler cell configured between the first and second standard cells, and spanning from the first dielectric gate to the second dielectric gate. The first pFET and the second pFET are formed on a first continuous active region. The first nFET and the second nFET are formed on a second continuous active region.

Semiconductor memory device

Disclosed is a semiconductor device, such as a semiconductor memory device, having structure wherein invasion of minority carriers from the semiconductor substrate into components of the device, formed on the substrate, can be avoided. The semiconductor memory device can be an SRAM or DRAM, for example, and includes a memory array and peripheral circuit on a substrate. In one aspect of the present invention, a buried layer of the same conductivity type as that of the substrate, but with a higher impurity concentration than that of the substrate, is provided beneath at least one of the peripheral circuit and memory array. A further region can extend from the buried layer, for example, to the surface of the semiconductor substrate, the buried layer and further region in combination acting as a shield to prevent minority carriers from penetrating to the device elements. As a second aspect of the present invention, first carrier absorbing areas (to absorb minority carriers) are located between ...

Semiconductor memory device having novel layout pattern

A semiconductor memory device laid out to have a deep well of a second conductivity type formed in a semiconductor substrate of a first conductivity type, a cell array well of the first conductivity type formed on said deep well, and an isolation well of the second conductivity type formed around said cell array well to reach said deep well so as to incorporate said cell array well, thereby isolating said cell array well from said semiconductor substrate through said isolation well, wherein a circuit element for driving said cell array is formed in said isolation well.

Complementary integrated circuit with a substrate bias voltage generator and a Schottky diode

An integrated circuit in complementary circuit technology comprising a substrate bias voltage generator which applies a negative (positive) substrate bias voltage to the p(n) substrate in which n(p) tubs are inserted. The source regions of the n(p)-channel FETs arranged in the substrate lie at ground potential. In order to avoid "latch-up" effects, an output of the substrate bias voltage generator is connected via a Schottky diode to a circuit point that lies at ground potential.

DYNAMIC SEMICONDUCTOR STORAGE DEVICE

PURPOSE: To provide a DRAM which has compatible characteristics of a high speed operation and a low power consumption. CONSTITUTION: A memory cell array 2 on which dynamic type memory cells are placed, core circuits 3 and 4 which include address decoders and sense amplifiers, a peripheral circuit 5 which performs data input and output control and a bias circuit 6, which generates bias potentials for each circuit section, are provided. The bias circuit 6 has at least the capability in which different base plate biases are supplied to MOS transistors used in the peripheral circuit 5 during an active period and a precharge period. COPYRIGHT: (C)1992,JPO&Japio ...

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREFOR

PROBLEM TO BE SOLVED: To provide a semiconductor device, having a SON structure that can be made thin and to provide a manufacturing method of the device. SOLUTION: The device is provided with the semiconductor substrate 10, plate-like hollows 11 formed in the semiconductor substrate 10 and element isolation regions 12 formed on a surface of the semiconductor substrate 10 so that they are brought into contact with end parts in the in-plane directions of the hollows 11. COPYRIGHT: (C)2004,JPO ...

SEMICONDUCTOR DEVICE

When a semiconductor device is provided with an inverter comprising a transistor having a first gate and a second gate, the semiconductor device does not require a circuit for generating a potential to be input to the second gate of the transistor and has a small number of wirings. Moreover, a semiconductor device having high reliability is provided. The semiconductor device includes a plurality of stages of circuits each provided with two inverter circuits in parallel. Two inverter circuits in a given stage output respective signals of opposite polarities, which is utilized for interchanging signals output from inverter circuits in the previous stage. Thus, an inverted signal is input to the second gate of the transistor included in each of two inverter circuits in the subsequent stage. 1. A semiconductor device comprising:a plurality of inverter stages each comprising a first inverter circuit and a second inverter circuit connected in parallel to each other, each of the first inverter circuit and the second inverter circuit comprising a transistor having a first gate and second gate,wherein the first inverter circuit and the second inverter circuit are configured to output respective signals of opposite polarities and to interchange signals output from two inverter circuits in a previous stage,wherein an input signal for the first inverter circuit is the same as a signal input to the second gate of the transistor included in the second inverter circuit, andwherein an input signal for the second inverter circuit is the same as a signal input to the second gate of the transistor included in the first inverter circuit.2. The semiconductor device according to claim 1 , wherein a channel region of the transistor comprises an oxide semiconductor.3. The semiconductor device according to claim 1 , wherein the semiconductor device is one of a ring oscillator and an inverter chain.4. A semiconductor device comprising an odd number of inverter stages each comprising a first ...

SEMICONDUCTOR CHIP

A semiconductor chip may have at least one p-channel field effect transistor (FET), at least one n-channel FET, a first and a second power supply terminal, wherein the at least one n-channel FET, if supplied with the upper supply potential at its gate, supplies the lower supply potential to the gate of the at least one p-channel FET and the at least one p-channel FET, if supplied with the lower supply potential at its gate, supplies the upper supply potential to the gate of the at least one n-channel FET, a precharge circuit to precharge the circuit to a first state, and a detection circuit configured to output an alarm signal if the circuit enters a second state. 1. A semiconductor chip comprising: at least one p-channel field effect transistor;', 'at least one n-channel field effect transistor;', 'a first power supply terminal configured to receive a first supply voltage with an upper supply potential; and', 'a second power supply terminal configured to receive a second supply voltage with a lower supply potential;', the at least one n-channel field effect transistor, if supplied with the upper supply potential at its gate, supplies the lower supply potential to the gate of the at least one p-channel field effect transistor; and', 'the at least one p-channel field effect transistor, if supplied with the lower supply potential at its gate, supplies the upper supply potential to the gate of the at least one n-channel field effect transistor;, 'wherein the at least one p-channel field effect transistor and the at least one n-channel field effect transistor are connected such that'}], 'a circuit comprising'}a precharge circuit configured to precharge the circuit to a first state in which the potential at the gate of the at least one n-channel field effect transistor is lower than the upper supply potential and the potential at the gate of the at least one p-channel field effect transistor is higher than the lower supply potential; anda detection circuit configured to ...

A MOSFET and Memory Cell Having Improved Drain Current Through Back Bias Application

A semiconductor metal-oxide-semiconductor field effect transistor (MOSFET) transistor with increased on-state current obtained through intrinsic bipolar junction transistor (BJT) of MOSFET has been described. Methods of operating the MOS transistor are provided. 115-. (canceled)16. A method of selectively operating a semiconductor device as a semiconductor memory device or a transistor with increased on-state drain current , said method comprising:providing said semiconductor device comprising a substrate having a first conductivity type selected from p-type conductivity type and n-type conductivity type; a buried layer having a second conductivity type selected from said p-type conductivity type and said n-type conductivity type and being different from said first conductivity type; a body having said first conductivity type; a source region and a drain region each having said second conductivity type and being separated by said body; and a gate positioned in between said source region and said drain region; andselectively operating said semiconductor device as said semiconductor memory device or said transistor, wherein said selectively operating comprises:applying a relatively low voltage to said buried layer to operate said semiconductor device as an ordinary transistor;applying a relatively high voltage to said buried layer to operate said semiconductor device as said semiconductor memory device, wherein said semiconductor memory device has at least two stable states; andapplying an intermediate high voltage higher than said relatively low voltage but lower than said relatively high voltage to said buried layer to operate said semiconductor device as said transistor with increased on-state drain current.17. The method of claim 16 , wherein said relatively high voltage is sufficiently high to turn on a vertical bipolar junction transistor (BJT) formed by said buried layer claim 16 , said body and one of said source region or said drain region.18. The method of ...

SEMICONDUCTOR DEVICE STRUCTURES WITH A SUBSTRATE BIASING SCHEME

Semiconductor device structures with substrate biasing, methods of forming a semiconductor device structure with substrate biasing, and methods of operating a semiconductor device structure with substrate biasing. A substrate contact is coupled to a portion of a bulk semiconductor substrate in a device region. The substrate contact is configured to be biased with a negative bias voltage. A field-effect transistor includes a semiconductor body in the device region of the bulk semiconductor substrate. The semiconductor body is electrically isolated from the portion of the bulk semiconductor substrate. 1. A structure comprising:a bulk semiconductor substrate including a first device region;a first substrate contact coupled to a first portion of the bulk semiconductor substrate in the first device region, the first substrate contact configured to be biased with a first negative bias voltage; anda first field-effect transistor including a first semiconductor body in the first device region of the bulk semiconductor substrate, the first semiconductor body electrically isolated from the first portion of the bulk semiconductor substrate.2. The structure of further comprising:an isolation layer positioned between the first semiconductor body and the first portion of the bulk semiconductor substrate.3. The structure of wherein the isolation layer comprises a polycrystalline semiconductor material.4. The structure of wherein the isolation layer has an electrical resistivity within a range of about 10 claim 2 ,000 ohm-cm to about 1 claim 2 ,000 claim 2 ,000 ohm-cm.5. The structure of further comprising:a power supply coupled to the first substrate contact, the power supply configured to supply the first negative bias voltage to the first substrate contact.6. The structure of wherein the first negative bias voltage is within a range of about −1 volts to about −4 volts.7. The structure of wherein the bulk semiconductor substrate includes a second device region claim 1 , the bulk ...

Integrated circuit fin layout method, system, and structure

A method of operating an IC manufacturing system includes determining whether an n-type active region of a cell or a p-type active region of the cell is a first active region based on a timing critical path of the cell, positioning the first active region along a cell height direction in an IC layout diagram of a cell, the first active region having a first total number of fins extending in a direction perpendicular to the cell height direction. The method also includes positioning a second active region in the cell along the cell height direction, the second active region being the n-type or p-type opposite the n-type or p-type of the first active region and having a second total number of fins less than the first total number of fins and extending in the direction, and storing the IC layout diagram of the cell in a cell library.

MOSFET and Memory Cell Having Improved Drain Current Through Back Bias Application

A semiconductor metal-oxide-semiconductor field effect transistor (MOSFET) transistor with increased on-state current obtained through intrinsic bipolar junction transistor (BJT) of MOSFET has been described. Methods of operating the MOS transistor are provided.

Semiconductor device

A semiconductor device includes an input clock generation circuit able to shift a write command in synchronization with a clock, and generating first and second input clocks. The semiconductor device also includes a write leveling control circuit able to divide a frequency of the clock in response to a write leveling control signal, and generating first to fourth write clocks. The semiconductor device includes a signal transfer circuit able to transfer the first and second input clocks as first and second transfer clocks in a write operation, and transferring the first to fourth write clocks as first to fourth transfer clocks in a write leveling operation.

Semiconductor Chip Including Integrated Circuit Having Cross-Coupled Transistor Configuration and Method for Manufacturing the Same

A first conductive structure forms gate electrodes of a first transistor of a first transistor type and a first transistor of a second transistor type. A second conductive structure forms a gate electrode of a second transistor of the first transistor type. A third conductive structure forms a gate electrode of a second transistor of the second transistor type. A fourth conductive structure forms a gate electrode of a third transistor of the first transistor type. A fifth conductive structure forms a gate electrode of a third transistor of the second transistor type. A sixth conductive structure forms gate electrodes of a fourth transistor of the first transistor type and a fourth transistor of the second transistor type. The second and third transistors of the first transistor type and the second and third transistors of the second transistor type are electrically connected to form a cross-coupled transistor configuration. 1a first conductive structure forming a gate electrode of a first transistor of a first transistor type; anda second conductive structure forming a gate electrode of a second transistor of the first transistor type,wherein both the first transistor of the first transistor type and the second transistor of the first transistor type are part of cross-coupled transistor configuration, andwherein a diffusion region of the first transistor of a first transistor type is physically separated from a diffusion region of the second transistor of the first transistor type.. A semiconductor chip, comprising: This application is a continuation application under 35 U.S.C. 120 of prior U.S. application Ser. No. 15/389,883, filed Dec. 23, 2016, issued as U.S. Pat. No. 9,871,056, on Jan. 16, 2018, which is a continuation application under 35 U.S.C. 120 of prior U.S. application Ser. No. 14/945,361, filed Nov. 18, 2015, issued as U.S. Pat. No. 9,536,899, on Jan. 3, 2017, which is a continuation application under 35 U.S.C. 120 of prior U.S. application Ser. No. 14/ ...

BIASING BULK OF A TRANSISTOR

A circuit comprises a first transistor of a first type, a second transistor of a second type, and a third transistor of the first type or the second type. The first transistor and the second transistor form an inverter. The third transistor is coupled with an output of the inverter. The circuit includes at least one of the following voltage sources: a first voltage source, a second voltage source, and a third voltage source. The first voltage source is coupled with a bulk of the first transistor, and is different from a first supply voltage source of the first transistor. T second voltage source is coupled with a bulk of the second transistor, and is different from a second supply voltage of the second transistor. The third voltage source is coupled with a bulk of the third transistor. 1. A circuit comprising:a first transistor of a first type;a second transistor of a second type;a third transistor of the first type or the second type; andat least one of a first voltage source, a second voltage source, or a third voltage source, the first transistor and the second transistor form an inverter;', 'the third transistor is coupled with an output of the inverter;', 'the first voltage source is coupled with a bulk of the first transistor and is different from a first supply voltage source of the first transistor;', 'the second voltage source is coupled with a bulk of the second transistor, and is different from a second supply voltage of the second transistor; and', 'the third voltage source is coupled with a bulk of the third transistor., 'wherein'}2. The circuit of claim 1 , whereinthe third voltage source is different from the first supply voltage source.3. The circuit of claim 1 , whereinthe third voltage source is the same as the first supply voltage source.4. The circuit of claim 1 , whereinthe third voltage source is different from the second supply voltage source.5. The circuit of claim 1 , whereinthe third voltage source is the same as the first supply voltage ...

CONDUCTIVE LAYER STRUCTURES FOR SUBSTRATES

An example substrate includes a surface, a plurality of thin film layers disposed on the surface, and a conductive layer disposed on the surface. The conductive layer includes a bending structure. The bending structure includes a plurality of openings, where a shape of at least one opening of the plurality of openings has a first curved portion. 1. A display device , comprising:a substrate including a surface;a thin film transistor layer disposed on the surface;a light emitting unit disposed on the surface and electrically connected to the thin film transistor layer; anda conductive layer disposed on the surface, the conductive layer including a bending structure, the bending structure including a plurality of openings, where a shape of at least one opening of the plurality of openings has a first curved portion, wherein the conductive layer includes a first layer and a second layer disposed on the first layer, and a thickness of the first layer is different than a thickness of the second layer.2. The display device of claim 1 , wherein the at least one opening has an area between 5 μmand 500 μm.3. The display device of claim 1 , wherein the at least one opening further includes a second curved portion claim 1 , where a curvature of the first curved portion is different than a curvature of the second curved portion.4. The display device of claim 1 , wherein the bending structure further includes an undulating edge.5. The display device of claim 1 , wherein the conductive layer further includes:a conductive line extending along a first direction, the conductive line including a wiring portion, a connecting portion, and the bending structure, the connecting portion disposed between the bending structure and the wiring portion, the connecting portion having a first width along a second direction substantially perpendicular to the first direction, the wiring portion having a second width along the second direction, and the first width being greater than the second width ...

FERROELECTRIC RESONATOR

Describe is a resonator that uses ferroelectric (FE) material in a capacitive structure. The resonator includes a first plurality of metal lines extending in a first direction; an array of capacitors comprising ferroelectric material; a second plurality of metal lines extending in the first direction, wherein the array of capacitors is coupled between the first and second plurality of metal lines; and a circuitry to switch polarization of at least one capacitor of the array of capacitors. The switching of polarization regenerates acoustic waves. In some embodiments, the acoustic mode of the resonator is isolated using phononic gratings all around the resonator using metal lines above and adjacent to the FE based capacitors. 1. An apparatus comprising:a first metal line;a second metal line parallel to the first metal line;a capacitor comprising ferroelectric (FE) structure, wherein the capacitor is coupled between the first and second metal lines; andcircuitry to switch direction of polarization of the capacitor.2. The apparatus of claim 1 , wherein the FE structure includes O and Hf.3. The apparatus of claim 2 , wherein the FE structure is doped by a dopant including one of: silicon claim 2 , zirconium claim 2 , lanthanum claim 2 , or aluminum.4. The apparatus of claim 3 , wherein the dopant has a concentration between about 3% and 30% by weight.5. The apparatus of claim 1 , wherein the circuitry comprises one or more transistors to switch direction of polarization of the FE material of the capacitor to mechanically resonate the capacitor at a frequency generate periodic acoustic wave between the first and second metal lines.6. The apparatus of claim 1 , wherein the capacitor includes one of: metal-insulator-metal (MIM) capacitors or capacitor-on-bitline (COB) capacitor.7. The apparatus of claim 1 , wherein the capacitor is positioned in a backend of a die claim 1 , and wherein the circuitry is fabricated in a frontend of the die.8. The apparatus of comprising:a ...

CONDUCTIVE LAYER STRUCTURES FOR SUBSTRATES

An example substrate includes a surface, a plurality of thin film layers disposed on the surface, and a conductive layer disposed on the surface. The conductive layer includes a bending structure. The bending structure includes a wavy edge and includes a plurality of openings, where a shape of at least one opening of the plurality of openings has a contour having a first curved portion, and a curvature of a portion of the wavy edge is different from a curvature of the first curved portion. 1. A display device , comprising:a substrate including a surface;a thin film transistor layer disposed on the surface;a light emitting unit disposed on the surface and electrically connected to the thin film transistor layer; anda conductive layer disposed on the surface, the conductive layer including a bending structure, the bending structure comprising a wavy edge and including a plurality of openings where a shape of at least one opening of the plurality of openings has a contour having a first curved portion,wherein a curvature of a portion of the wavy edge is different from a curvature of the first curved portion.2. The display device of claim 1 , wherein the at least one opening has an area between 5 μmand 500 μm.3. The display device of claim 1 , wherein the at least one opening further includes a second curved portion claim 1 , where a curvature of the first curved portion is different than a curvature of the second curved portion.4. The display device of claim 1 , wherein the bending structure further includes an undulating edge.5. The display device of claim 1 , wherein the conductive layer further includes:a conductive line extending along a first direction, the conductive line including a wiring portion, a connecting portion, and the bending structure, the connecting portion disposed between the bending structure and the wiring portion, the connecting portion having a first width along a second direction substantially perpendicular to the first direction, the wiring ...

DISPLAY DEVICE

A display device includes a light-emitting unit and a light conversion layer disposed on the light-emitting unit. The light conversion layer includes plural quantum dot portions and a first shielding portion surrounding the plural quantum dot portions. One of the plural quantum dot portions has a surface, and at least a part of the surface is a curved surface. A first thickness of the first shielding portion is greater than a maximum thickness of one of the plural quantum dot portions. 1. A display device , comprising:a light-emitting unit; anda light conversion layer, disposed on the light-emitting unit, the light conversion layer including plural quantum dot portions and a first shielding portion surrounding the plural quantum dot portions,wherein one of the plural quantum dot portions has a surface, at least a part of the surface is a curved surface, and a first thickness of the first shielding portion is greater than a maximum thickness of one of the plural quantum dot portions.2. The display device of claim 1 , wherein the one of the plural quantum dot portions comprises different thicknesses.3. The display device of claim 2 , wherein a lowest point of the curved surface is disposed between a highest point of the curved surface and the first shielding portion.4. The display device of claim 1 , further comprising:a substrate; anda transistor disposed on the substrate.5. The display device of claim 4 , wherein the light-emitting unit is electrically connected to the transistor.6. The display device of claim 1 , further comprising a second shielding portion disposed between the light-emitting unit and the first shielding portion claim 1 , wherein the second shielding portion overlaps the first shielding portion claim 1 , and a first width of the first shielding portion is less than a second width of the second shielding portion.7. The display device of claim 6 , wherein at least one of the first shielding portion and the second shielding portion overlaps the ...

Semiconductor Chip Including Integrated Circuit Having Cross-Coupled Transistor Configuration and Method for Manufacturing the Same

A first conductive structure forms gate electrodes of a first transistor of a first transistor type and a first transistor of a second transistor type. A second conductive structure forms a gate electrode of a second transistor of the first transistor type. A third conductive structure forms a gate electrode of a second transistor of the second transistor type. A fourth conductive structure forms a gate electrode of a third transistor of the first transistor type. A fifth conductive structure forms a gate electrode of a third transistor of the second transistor type. A sixth conductive structure forms gate electrodes of a fourth transistor of the first transistor type and a fourth transistor of the second transistor type. The second and third transistors of the first transistor type and the second and third transistors of the second transistor type are electrically connected to form a cross-coupled transistor configuration.

BODY-BIAS VOLTAGE ROUTING STRUCTURES

Body-bias voltage routing structures. In an embodiment, doped well structures distribute body biasing voltages to a plurality of body biasing wells of an integrated circuit. 1. A semiconductor device comprising:two conductive regions of a first conductivity type formed beneath a surface of the semiconductor device, wherein the two conductive regions are configured to route a body-bias voltage, and wherein the two conductive regions do not reach the surface; anda metal structure formed above the surface, wherein the metal structure is coupled to the two conductive regions.2. The semiconductor device of claim 1 , wherein each conductive region has an N-type doping.3. The semiconductor device of claim 1 , wherein each conductive region has a P-type doping.4. The semiconductor device of claim 1 , wherein each conductive region has a strip shape.5. The semiconductor device of claim 1 , wherein the metal structure has a metal wire shape.6. The semiconductor device of claim 1 , wherein the metal structure passes over a region of a second conductivity type.7. A semiconductor device comprising:two deep wells of a first conductivity type, wherein each deep well is formed beneath a surface of the semiconductor device, wherein the two deep wells are operable to route a body-bias voltage, and wherein the two deep wells do not reach the surface;two other deep wells of the first conductivity type, wherein each of the two other deep wells is formed beneath the surface, wherein the two other deep wells are operable to route the body-bias voltage, wherein the two other deep wells do not reach the surface, and wherein the two other deep wells are physically separate; anda conductive structure formed above the surface, wherein the conductive structure couples at least one of the two deep wells and at least one of the two other deep wells.8. The semiconductor device of claim 7 , wherein each deep well has an N-type doping.9. The semiconductor device of claim 7 , wherein each deep well ...

Integrated circuit and method for manufacturing the same

An integrated circuit includes a first and second set of gate structures. A center of each of the first set of gate structures is separated from a center of an adjacent gate of the first set of gate structures in a first direction by a first pitch. A center of each of the second set of gate structures is separated from a center of an adjacent gate of the second set of gate structures in the first direction by the first pitch. The first and second set of gate structures extend in a second direction. A gate of the first set of gate structures is aligned in the second direction with a corresponding gate of the second set of gate structures. The gate of the first set of gate structures is separated from the corresponding gate of second set of gate structures in the second direction by a first distance.

DISPLAY ASSEMBLY

A display assembly includes a display component and a flexible stratum. The flexible stratum includes a first side coupled to the display component and a second side opposite to the first side. The second side includes protruding portions separate apart from each other, and one of the protruding portions includes a side section, a top section, and a tapering section extending from the side section to the top section and having a curved surface. 2. The flexible display assembly of claim 1 , wherein claim 1 , in a plan view claim 1 , the first protrusions and the second protrusions have different shapes.3. The flexible display assembly of claim 1 , wherein claim 1 , in a plan view claim 1 , the one of the first protrusions has a first area and the one of the second protrusions has a second area claim 1 , and the first area is greater than the second area.4. The flexible display assembly of claim 1 , wherein the display component includes a driving circuit layer and a display layer electrically connected to the driving circuit layer.5. The flexible display assembly of claim 1 , wherein claim 1 , in a plan view claim 1 , the one of the first protrusions or the one of the second protrusions includes at least a rounded corner.6. The flexible display assembly of claim 1 , wherein the one of the first protrusions has a first thickness along a direction from the first side toward the second side in the cross-sectional view claim 1 , the one of the second protrusions has a second thickness along the direction from the first side toward the second side in the cross-sectional view claim 1 , and the first thickness is greater than the second thickness.7. The flexible display assembly of claim 1 , wherein the flexible stratum includes a recessed portion spacing the one of the first protrusions and the one of the second protrusions.8. The flexible display assembly of claim 1 , further comprising a cover layer disposed on the display component claim 1 , wherein the display ...

High voltage charge pump using low voltage type transistors

An integrated circuit includes an N isolation buried layer underlying high density and low voltage type P channel and N channel transistors to define islands of arbitrary voltage on the substrate. Thus such transistors, which otherwise are capable only of low voltage operation, become capable of operating at high voltage relative to the substrate. This allows integration, on a single chip, of high voltage circuit elements with low voltage and high density transistors all formed by the same fabrication process sequence. In one example this allows creation of an 18 volt range charge pump using a CMOS process which normally provides only 3 volt operating range transistors. This then allows integration on a single integrated circuit chip of a complex digital logic function such as a UART (universal asynchronous receiver and transmitter) with a high voltage function such as an RS-232 interface, including integrated capacitors for the RS-232 interface charge pump.

Body-contacted semiconductor structures and methods of fabricating such body-contacted semiconductor structures

A semiconductor structure for a dynamic random access memory (DRAM) cell array that includes a plurality of vertical memory cells built on a semiconductor-on-insulator (SOI) wafer and a body contact in the buried dielectric layer of the SOI wafer. The body contact electrically couples a semiconductor body with a channel region of the access device of one vertical memory cell and a semiconductor substrate of the SOI wafer. The body contact provides a current leakage path that reduces the impact of floating body effects upon the vertical memory cell. The body contact may be formed by an ion implantation process that modifies the stoichiometry of a region of the buried dielectric layer so that the modified region becomes electrically conductive with a relatively high resistance.

저 전압형 트랜지스터를 사용하는 고 전압 전하 펌프(high voltage charge pump using low voltage type transistors)

Apparatus and method for forming dielectric layers

CVD 방법과 ALD 방법 모두가 채용된 유전막 형성 장치 및 방법을 개시한다. 유전막 형성 장치는 웨이퍼 상에 제 1 유전막을 화학기상증착 방식으로 형성하는 제 1 챔버와, 제 1 유전막 상에 제 2 유전막을 원자층 증착 방식으로 형성하는 제 2 챔버를 포함한다. 반대로, 제 1 챔버에서 제 1 유전막을 원자층 증착 방식으로 형성하고, 제 2 챔버에서 제 2 유전막을 화학기상증착 방식으로 형성할 수도 있다. 따라서, 이중의 유전막을 화학기상증착법과 원자층 증착법으로 형성함으로써, 화학기상증착법으로 빠른 시간 내에 형성된 제 1 유전막 상에 제 2 유전막을 원자층 증착법을 이용해서 웨이퍼 상의 넓은 영역에 걸쳐서 균일한 두께로 빠르게 형성할 수가 있게 된다. Disclosed are a dielectric film forming apparatus and method employing both a CVD method and an ALD method. The dielectric film forming apparatus includes a first chamber for forming a first dielectric film on a wafer by chemical vapor deposition, and a second chamber for forming a second dielectric film on the first dielectric film by atomic layer deposition. Conversely, the first dielectric film may be formed by an atomic layer deposition method in a first chamber, and the second dielectric film may be formed by a chemical vapor deposition method in a second chamber. Therefore, by forming the double dielectric film by chemical vapor deposition and atomic layer deposition, the second dielectric film is formed on the first dielectric film formed by the chemical vapor deposition method in a short time by using atomic layer deposition to a uniform thickness over a large area on the wafer. It can be formed quickly.

Full Swing Power-Down Buffer Circuit with Multiple Power Isolation

본 발명은 풀스윙 CMOS 출력 버퍼 회로 (20, 30, 40, 50) 에 관한 것으로, 예컨대 3.3 V 표준규격 및 5 V 표준규격 부분회로와 같이 호환가능하지 않은 전원 회로를 분리시키고, 공통 외부버스로부터 휴지 상태에 있거나 또는 파워 다운된 버퍼 회로의 전원 레일을 분리시킨다. 풀업 출력 트랜지스터 (PMOS1) 는, P 형 캐리어 반도체 재료의 기판 (PSUB) 에 형성된 N 형 캐리어 반도체 재료의 웰 (NWELL) 에 제조된다. P 채널 NWELL 분리 스위치 트랜지스터 (PW1) 는, 상기 웰 (NWELL) 과 고전위 전원 레일 (VCC) 사이에 결합된 1 차 전류 경로 및 실질적으로 동기하여 동작하기 위하여 풀업 출력 트랜지스터 (PMOS1) 의 제어 게이트 노드에 결합된 제어 게이트 노드를 지닌다. NWELL 분리 스위치 트랜지스터 (PW1) 는, 풀업 출력 트랜지스터 (PMOS1) 웰 (NWELL) 을 고전위 전원 레일 (VCC) 로부터 분리시킨다. N 채널 제어 노드 분리 트랜지스터 (N1) 는, 파워 다운하는 동안 출력 트랜지스터 (PMOS1, NMOS1) 의 제어 노드를 상호간에 분리시키기 위하여 고전위 전원 레일 (VCC) 에 결합된 제어 노드를 지닌다. P 채널 피드백 턴오프 트랜지스터 (PP1) 는, 출력 (V OUT ) 에 나타나는 고전위 레벨 신호에 응답하여 출력 트랜지스터 (PMOS1) 를 턴오프하기 위하여 고전위 전원 레일 (VCC) 에 결합된 제어 노드를 지닌다. 지연 방전 회로 (DDC) 는, 파워 다운하는 동안 과도 전하를 고전위 전원 레일 (VCC) 로부터 방전한다. The present invention relates to a full swing CMOS output buffer circuit (20, 30, 40, 50), which isolates incompatible power supply circuits, such as 3.3 V standard and 5 V standard subcircuits, Disconnect the power rails of the buffer circuit that are at rest or powered down. The pull-up output transistor PMOS1 is manufactured in the well NWELL of the N-type carrier semiconductor material formed on the substrate PSUB of the P-type carrier semiconductor material. P-channel NWELL isolation switch transistor PW1 is a control gate node of pull-up output transistor PMOS1 for operating substantially synchronously with the primary current path coupled between the well NWELL and the high potential power rail VCC. It has a control gate node coupled to it. The NWELL isolation switch transistor PW1 isolates the pull-up output transistor PMOS1 well NWELL from the high potential power rail VCC. The N-channel control node disconnect transistor N1 has a control node coupled to the high potential power rail VCC to isolate the control nodes of the output transistors PMOS1, NMOS1 from each other during power down. P-channel feedback turn-off transistor PP1 has a control node coupled to high- ...

ゲ−トアレイ装置及び入力回路及び出力回路及び降圧回路

Semiconductor memory device

내용 없음. No content.

반도체 집적회로(Semiconductor Integrated Circuit Having Reduced Current Leakage and High Speed)

본 발명은 반도체 집적회로는; 제1전원 전압이 공급되고 고임계 전압을 갖는 제1MOS 트랜지스터; 제2전원 전압이 공급되고 고임계 전압을 갖는 제2 MOS트랜지스터; 제1트랜지스터와 제2트랜지스터 간에 접속되며, 저임계 전압을 갖는 다수의 MOS 트랜지스터를 포함하는 논리회로; 논리회로가 대기 상태에 있는 제어 신호를 발생하는 제어회로; 제1 전원 전압보다 큰 제1전압과 제2전원 전압보다 작은 제2전압을 발생하여, 논리회로가 대기 상태에 있는 때 제1전압을 제1 MOS 트랜지스터의 게이트에 공급하고 제2전압을 제2 MOS트랜지스터의 게이트에 공급함으로써, 대기 상태에서 제1 및 제2트랜지스터를 통한 그리고 논리회로를 통한 누설 전류가 감소되게 하는 전압 발생회로를 포함한다.

Semiconductor device

(57)【要約】本公報は電子出願前の出願データであるた め要約のデータは記録されません。

Semiconductor memory device, internal power supply voltage generation circuit, internal high voltage generation circuit, intermediate voltage generation circuit, constant current source, and reference voltage generation circuit

Semiconductor storage device

Semiconductor device with electromagnetic radiation reduced

외부 전원 시스템으로부터 전력이 공급되는 반도체 장치에서, 제1전원 시스템은 제1읜 전원 및 단자와 디지털 내부 회로에 공급된다. 내부 회로는 클락 신호 발생 회로와, 클락 신호용 구동기와, 클락 신호에 응답하여 동작하는 회로를 포함한다. 제2전원 시스템은 제2의 전원 및 접지 단자와 입력 단자와 출력 단자와 디지털 인터페이스 회로에 연결된다. 제2전원 시스템은 제1전원 시스템과는 무관하다. 인터페이스 회로는 입력 단자를 풀업 또는 풀다운시키는 MOS 트랜지스터와 출력 단자를 구동시키는 MOS 트랜지스터를 포함하는 출력 회로를 포함한다. 제1전원 시스템은 제2전원 시스템과 분리되며, 내부 회로는 신호 라인을 톨해서만 인터페이스 회로와 연결된다. In the semiconductor device powered by the external power supply system, the first power supply system is supplied to the first power supply and terminal and the digital internal circuit. The internal circuit includes a clock signal generating circuit, a clock signal driver, and a circuit operating in response to a clock signal. The second power system is connected to the second power and ground terminal, the input terminal, the output terminal and the digital interface circuit. The second power system is independent of the first power system. The interface circuit includes an output circuit including a MOS transistor for pulling up or pulling down the input terminal and a MOS transistor for driving the output terminal. The first power system is separated from the second power system, and the internal circuit is connected to the interface circuit only by charging the signal line.

Semiconductor integral circuit with reduced current leakage and high speed

半导体集成电路包括：加有第一电源电压并有高阈电压的第一MOS晶体管，加有第二电源电压并有高阈电压的第二MOS晶体管，连接在第一和第二晶体管之间并有多个低阈电压的MOS晶体管的逻辑电路，当逻辑电路处在备用状态时产生控制信号的控制电路，及产生第一电压和第二电压的电压产生电路，当逻辑电路在备用状态时把第一电压加到第一MOS晶体管和把第二电压加到第二MOS晶体管，从而减小备用状态时通过第一和第二晶体管及逻辑电路的漏电流。

Insulated gate transistor element and drive method thereof

(57)【要約】 【課題】論理構造に対応した個別の回路設計を必要とせ ず、低電源電圧での動作が可能であり、しかも、ゲート 閾値電圧の温度変化、ロット間のばらつき、ウエハ内の 面内ばらつきによっても動作不良が生じることがなく、 高速動作が可能な絶縁ゲートトランジスタ素子を提供す る。 【解決手段】絶縁ゲートトランジスタ素子は、チャネル 形成領域２２と、ソース／ドレイン領域２３，２４と、 ゲート領域２１と、バイアス付与手段３０と、容量性素 子４０から構成されており、チャネル形成領域２２に は、不動作時の絶縁ゲートトランジスタ素子のゲート閾 値電圧を制御するための電位がバイアス付与手段３０を 介して印加され、且つ、ゲート領域２１に供給される信 号と略同相の信号が容量性素子４０を介して供給され る。

Semiconductor integrated circuit device having power reduction mechanism

PURPOSE: To provide the high-speed and low power consumption semiconductor integrated circuit. CONSTITUTION: Between a MOS transistor circuit (LGn) and power sources (VCC and VSS), a means (SWHn) for controlling the power supply of large and small currents is inserted. The control of this SWHn is performed along the flow of signals from an input IN, and the current is supplied to the MOS transistor circuit (LGn) while being switched large and small. At the time of standby, the small current is supplied so as to provide low power consumption and at the time of operations, the large current is supplied so as to provide high speed. Further, even at the time of the switching operation, the high speed is not lost.

Semiconductor integrated circuit device

내용없음. None.

Semiconductor integrated circuit

본 발명의 반도체 집적회로는: 제1 전원 전압이 공급되고 고임계 전압을 갖는 제1 MOS 트랜지스터; 제2 전원 전압이 공급되고 고임계 전압을 갖는 제2 MOS 트랜지스터; 제1 트랜지스터와 제2 트랜지스터 간에 접속되며, 저임계 전압을 갖는 다수의 MOS 트랜지스터를 포함하는 논리회로; 논리회로가 대기 상태에 있는 제어신호를 발생하는 제어회로; 제1 전원 전압보다 큰 제1 전압과 제2 전원 전압보다 작은 제2 전압을 발생하여, 논리회로가 대기 상태에 있는 때 제1 전압을 제1 MOS 트랜지스터의 게이트에 공급하고 제2 전압을 제2 MOS 트랜지스터의 게이트에 공급함으로써, 대기 상태에서 제1 및 제2 트랜지스터를 통한 그리고 논리회로를 통한 누설 전류가 감소되게 하는 전압 발생회로를 포함한다. A semiconductor integrated circuit of the present invention includes: a first MOS transistor to which a first power supply voltage is supplied and which has a high threshold voltage; A second MOS transistor to which a second power supply voltage is supplied and has a high threshold voltage; A logic circuit connected between the first transistor and the second transistor and including a plurality of MOS transistors having a low threshold voltage; A control circuit for generating a control signal in which the logic circuit is in a standby state; A first voltage higher than the first power supply voltage and a second voltage lower than the second power supply voltage to supply a first voltage to the gate of the first MOS transistor when the logic circuit is in the standby state and a second voltage to the second And a voltage generation circuit for supplying leakage current to the gate of the MOS transistor through the first and second transistors in the standby state and through the logic circuit.

Voltage drop circuit of semiconductor device

Semiconductor device

N-channel mos integrated circuit device

(57)【要約】本公報は電子出願前の出願データであるた め要約のデータは記録されません。

Integrated semiconductor circuit arrangement

Silicon on insulator master slice semiconductor integrated circuit

A master slice semiconductor IC has a SOI substrate and a plurality of basic cells arranged in a matrix on the SOI substrate. The basic cell includes a two-input NAND gate and a diode forward biased between one of power supply lines and the NAND gate. The diode has a P-N junction extending between the top surface of a semiconductor layer and the insulator layer underlying the semiconductor layer. The diode reduces the supply voltage by the forward drop voltage thereof to reduce power consumption in the NAND gate, and the SOI structure of the basic cell prevents reduction of integration density and operational speed.

Semiconductor integrated circuit

In a semiconductor integrated circuit including, as a power-supply voltage converter for converting an external power-supply voltage into a lower internal power-supply voltage and supplying the converted voltage to the internal circuit, a reference voltage generator and an internal power-supply voltage supplier for outputting an internal power-supply voltage according to the reference voltage output from the reference voltage generator, the external power supply systems for the reference voltage generator and the internal power-supply voltage supplier are isolated from each other on the high level side, low level side, or both.

COMPENSATOR IN LSI TECHNOLOGY TO REMEDY FOR VARIATIONS IN CERTAIN PARAMETERS DUE TO THE MANUFACTURING PROCESS

Integrated circuit e.g. Dynamic RAM cell, has bit line located under structure that acts as gate to control channel, and capacitor includes electrode that comprises common layer with part of source and/or drain region of transistor

The circuit has a transistor formed in an active region e.g. lower and upper doping zones (9, 11), and an intermediate zone (10). The transistor has source and/or drain regions (50, 51) connected by a channel outside a substrate (1). A structure (185) acts as a gate to control the channel. A capacitor has an insulating layer (53) between a structure (195) and an electrode. A conducting line (19) i.e. electrode line, is connected to the structure (195), and a bit line is located under the structure (185). The electrode has a common layer with a part of the region (51). An independent claim is also included for a method for manufacturing an integrated circuit.

Patent FR2292280B1

REMANENT STATIC MEMORY SYSTEM WITH DIRECT ACCESS

LA PRESENTE INVENTION CONCERNE UN SYSTEME DE MEMOIRE REMANENTE INTEGREE A ACCES DIRECT DE TYPE MOS UTILISANT DES ELEMENTS DE CIRCUIT A GRILLE FLOTTANTE INTEGRES ET DES DISPOSITIFS INTEGRES DE PRODUCTION ET DE COMMANDE DE TENSIONS ELEVEES POUR LA REALISATION DE SYSTEMES INDEPENDANTS DE MEMOIRE RAM STATIQUES, REMANENTS ET MODIFIABLES ELECTRIQUEMENT. APPLICATION NOTAMMENT AUX MICROCALCULATEURS INSENSIBLES AUX DEFAILLANCES. THE PRESENT INVENTION CONCERNS A REMANENT INTEGRATED MEMORY SYSTEM WITH DIRECT ACCESS OF THE MOS TYPE USING INTEGRATED FLOATING GRID CIRCUIT ELEMENTS AND INTEGRATED DEVICES FOR THE PRODUCTION AND CONTROL OF HIGH TENSIONS FOR THE REALIZATION OF INDEPENDENT AND STATIONARY MEMORY SYSTEMS. ELECTRICALLY MODIFIABLE. APPLICATION IN PARTICULAR TO MICROCALCULATORS INSENSITIVE TO FAILURES.

Semiconductor integrated circuit

Abstract: A semiconductor integrated circuit for use as a highly dense memory comprises a first circuit receptive to a first power source voltage for generating a predetermined second power source voltage lower than the first power source voltage. There is also a second circuit receptive to the first power source voltage for generating a second pulse signal for use with the second power source voltage in response to a first pulse signal that varies within the same voltage range as that of the first power source voltage. A third circuit receptive to the second power source voltage and responsive to the second pulse signal has circuit elements of smaller size than those of the first circuit. This arrangement enables very dense packing of the elements while avoiding a need to reduce the voltage that can be applied to avoid risk of di-electric breakdown.

Cmos integrated circuit

PHN 13996 16.06.1992 ABSTRACT: CMOS integrated circuit. An important problem in large integrated circuits is constituted by noise superimposed on the supply. This noise is particularly caused by switching of switching elements such as flipflops, and by heavily loaded output stages. These elements cause current peaks which may give rise to comparatively great fluctuations in the voltage. This problem is solved at least to a great extent in CMOS circuits with standard cells or with custom layout blocks by means of an additional decoupling capacitance in the form of an extra well in the routing channels The decoupling capacitance may be positioned immediately adjacent the switching element, which is favourable for suppressing the supply noise. Since the routing channels are generally not used anyway for providing circuit elements, the chip surface area is not or substantially not increased by this extra capacitance. Fig. 3.

DYNAMIC ISOLATION CIRCUIT OF INTEGRATED CIRCUITS.

La présente invention concerne un circuit d'isolation dynamique faisant partie d'un circuit intégré monolithique comprenant des transistors latéraux et des transistors verticaux, reliée à un potentiel d'isolement (Viso ), ces transistors latéraux étant connectés à des tensions d'une première polarité par rapport à une tension de référence (GND), la borne de puissance connectée à la face arrière étant normalement à un potentiel (Vout ) de la première polarité par rapport à la tension de référence. Ce circuit comprend des moyens de détection (D) du signe du potentiel de la face arrière par rapport à la tension de référence, au moins un transistor latéral (S1) pour relier le potentiel d'isolement au potentiel de référence quand le potentiel de la face arrière est de la première polarité par rapport au potentiel de référence, et au moins un transistor vertical (S2) pour relier le potentiel d'isolement au potentiel de la face arrière quand le potentiel de la face arrière est de la deuxième polarité par rapport au potentiel de référence. The present invention relates to a dynamic isolation circuit forming part of a monolithic integrated circuit comprising side transistors and vertical transistors, connected to an isolation potential (Viso), these side transistors being connected to voltages of a first polarity with respect to a reference voltage (GND), the power terminal connected to the rear face being normally at a potential (Vout) of the first polarity with respect to the reference voltage. This circuit comprises means for detecting (D) the sign of the potential of the rear face with respect to the reference voltage, at least one lateral transistor (S1) for connecting the isolation potential to the reference potential when the potential of the rear face is of the first polarity with respect to the reference potential, and at least one vertical transistor (S2) for connecting the isolation potential to the potential of the rear face when the ...

High voltage charge pump using low voltage transistor

집적회로는 기판상에 임의 전압의 아일랜드를 한정하도록 고 밀도 및 저 전압형 P 채널 및 N 채널 트랜지스터의 하부에 놓인 N 분리 매몰층을 포함한다. 따라서, 달리 단지 저 전압 동작만이 가능한 그러한 트랜지스터는 상기 기판에 대해 고 전압에서 동작할 수 있다. 이는 동일 제조순서에 의해 형성되는 저 전압 및 고 밀도 트랜지스터 모두와 고 진압 회로 요소의 단일 칩상에서의 통합을 허용한다. 한 예에서, 이는 대개 단지 3 볼트 동작범위 트랜지스터만을 제공하는 CMOS 공정을 사용하는 18 볼트 범위 전하 펌프의 형성을 허용한다. 그때, 이는 RS - 232 인터페이스 전하 펌프용 집적된 캐패시터를 포함하는 RS - 232 인터페이스와 같은 고 전압 기능부와 UART ( 만능 비동기식 수신기 및 송신기 ; universal asynchronous receiver and transmitter ) 와 같은 복잡한 디자털 논리 기능의 단일 집적회로 칩상에서의 통합을 허용한다. The integrated circuit includes an N isolation buried layer underlying the high density and low voltage P-channel and N-channel transistors to define islands of arbitrary voltage on the substrate. Thus, such a transistor, which is otherwise only capable of low voltage operation, can operate at high voltages relative to the substrate. This allows the integration on a single chip of both low voltage and high density transistors and high suppression circuit elements formed by the same manufacturing sequence. In one example, this allows the formation of an 18 volt range charge pump using a CMOS process that usually provides only a 3 volt operating range transistor. At that time, it is a high voltage function such as an RS-232 interface with an integrated capacitor for an RS-232 interface charge pump and a single, complex digital logic function such as a UART (universal asynchronous receiver and transmitter). Allow integration on integrated circuit chips.

MULTIDRAIN MOS TRANSISTOR LOGIC DOOR

A.PORTE LOGIQUE A STRUCTURE INTEGREE MOS MONOCANALE COMPRENANT UN TRANSISTOR INVERSEUR DU TYPE A ENRICHISSEMENT ET UN TRANSISTOR DE CHARGE. B.LE TRANSISTOR INVERSEUR COMPORTE UNE PLURALITE DE ZONES DE DRAIN EN NOMBRE EGAL A LA SORTANCE DE LA PORTE. LA ZONE DE GRILLE DU TRANSISTOR INVERSEUR ENTOURE COMPLETEMENT CHAQUE ZONE DE DRAIN CONSTITUANT L'UNE DES SORTIES DE LA PORTE LOGIQUE, EST ENTOUREE COMPLETEMENT PAR LA ZONE DE SOURCE DU TRANSISTOR INVERSEUR, EST RELIEE AU MOINS A LA ZONE DE SOURCE DU TRANSISTOR DE CHARGE ET CONSTITUE PAR SON CONTACT L'ENTREE UNIQUE DE LADITE PORTE LOGIQUE. LES CONNEXIONS DE LIAISONS EXTERNES A L'ENTREE ET AUX SORTIES DE LA PORTE REALISENT DES ET CABLES. C.CIRCUIT INTEGRE DU TYPE MOS. A. LOGIC DOOR WITH INTEGRATED MOS SINGLE-CHANNEL STRUCTURE INCLUDING AN ENRICHING-TYPE INVERTING TRANSISTOR AND A LOAD TRANSISTOR. B. THE INVERTER TRANSISTOR CONTAINS A PLURALITY OF DRAIN ZONES IN NUMBER EQUAL TO THE EXIT OF THE DOOR. THE INVERTER TRANSISTOR GRID ZONE COMPLETELY SURROUNDED EACH DRAIN ZONE CONSTITUTING ONE OF THE OUTPUTS OF THE LOGIC GATE, IS COMPLETELY SURROUNDED BY THE INVERTER TRANSISTOR SOURCE ZONE, IS CONNECTED AT LEAST TO THE LOAD TRANSISTOR SOURCE ZONE AND CONSTITUTES THROUGH ITS CONTACT THE SINGLE ENTRY OF THE SAID LOGIC DOOR. THE CONNECTIONS OF EXTERNAL LINKS TO THE INPUT AND OUTPUTS OF THE DOOR REALIZE AND CABLES. C. INTEGRATED MOS TYPE CIRCUIT.

Integrated circuit module having on-chip surge capacitors

A SIMM (single in-line memory module) board is provided with a plurality of integrated semiconductor memory or other integrated semiconductor circuit devices which include, as a part of each integrated circuit device, a current spike leveling capacitor. The capacitor is on the die side of circuitry connecting the device to the board. By connecting the on chip capacitors of the integrated circuit devices in parallel, sufficient capacitance is provided to stabilize current to all of the circuit devices.

INTEGRATED POWER SUPPLY SYSREME

L'invention concerne un système intégré d'alimentation en courant Dans ce circuit d'alimentation en courant, comportant au moins un redresseur 6 et un condensateur 7, le circuit redresseur 6 et le circuit 8 devant être alimentés en courant sont intégrés sur une microplaquette commune 9, tandis que le condensateur 7 est disposé en dehors de cette microplaquette et que le redresseur 6 est constitué par un élément bloquant pour des tensions négatives, passant pour des tensions positives et bloquant à nouveau pour des tensions positives supérieures. Application notamment aux dispositifs réalisés suivant la technologie SOS-ESFI.

Semiconductor device and semiconductor storage device

Semiconductor device structured to be less susceptible to power supply noise

A semiconductor device comprises an MOS transistor, as a capacitive element, formed at the surface of a semiconductor substrate. A first power supply interconnection, above the substrate, applies a first power supply potential to the source and drain of the transistor. A second power supply interconnection, above the first interconnection, applies a second potential to the gate of the transistor. A third power supply interconnection is formed above, in parallel with and connected to the second power supply interconnection. An externally sourced potential is down-converted to be applied appropriately to the first, second and third power supply interconnections. This configuration achieves a semiconductor device that is less susceptible to power supply noise.

Semiconductor integrated circuit device

Multifunction fuzzy logical circuit

(57)【要約】本公報は電子出願前の出願データであるた め要約のデータは記録されません。

CMOS integrated circuit

大型集成电路中的重要问题是叠加到电源上的因触发器等开关元件的开关过程和输出级过负荷引起的噪音。这些元件造成电流峰值而使电压波动较大。在带标准元件或带定制的电路块的CMOS电路中，通过在走线通道中呈额外的阱的形式的附加去耦电容较有效地解决上述问题。紧靠开关元件设置去耦电容对抑制电源噪音有利。因为走线通道并不供电路元件使用，所以芯片的表面积不致因该额外电容而增加。

Method of forming multi-threshold voltage devices and devices so formed

A method provides a gate structure for a plurality of components of a semiconductor device. A silicate layer is provided. In one aspect, the silicate layer is provided on a channel of a CMOS device. A high dielectric constant layer is provided on the silicate layer. The method also includes providing a work function metal layer on the high dielectric constant layer. A low temperature anneal is performed after the high dielectric constant layer is provided. A contact metal layer is provided on the work function metal layer.

Semiconductor device

On board integrated circuit chip signal source

ON BOARD INTEGRATED CIRCUIT CHIP SIGNAL SOURCE ABSTRACT OF THE DISCLOSURE An on-board integrated circuit chip signal source which allows operation of the chip form previously incompatible and excessively high amplitude signal sources, and as well powers the chip from such sources as the input signal, a click, etc. The invention utilizes a 3 plate capacitor, with the bottom plate formed of a heavily doped region of the silicon substrate. Signal is applied between the outside plates of the capacitor and a proportion of the signal is received between the centre plate and one of the outside plates. A diode clamp connected between the centre plate and a reference potential fixes the derived peak and average signal levels.

MOSFET circuit and CMOS logic circuit using the same

A MOSFET circuit achieving high speed operation and low power consumption for a wide supply voltage range. MOSFET circuits (111 and 112) are connected between a low threshold voltage CMOS circuit (3) and a supply voltage (VDD) and ground, as a power controller for switching power supply in response to sleep/active modes. High threshold voltage MOSFETs (M1 and M3) in the MOSFET circuits (111 and 112) are gate biased by low threshold voltage MOSFETs (M2 and M4), thereby preventing a current from flowing across the backgate terminal and the source terminal.

Master slice semiconductor integrated circuit

SOI 기판과 SOI 기판 상에 매트릭스에 배열된 다수의 기본 셀을 갖는 마스터 슬라이스 반도체 집적 회로. 기본 셀은, 2-입력 NAND 게이트와, 전력 공급 라인중의 하나와 NAND 게이트 사이에 앞쪽으로 바이어스된 다이오드를 포함한다. 다이오드는 반도체 층의 상부 표면과 반도체 층 아래의 절연층 사이에 연장되는 P-N 접합을 갖는다. 이 다이오드는 NAND 게이트의 전력 소모를 감소시키도록 그의 하강 전압만큼 공급 전압을 감소시키고, 기본 셀의 SOI 구조는 집적 밀도와 동작 속도의 감소를 방지한다.

INTEGRATED POWER CIRCUIT.

Metal oxide semiconductor type integrated circuit

(57)【要約】本公報は電子出願前の出願データであるた め要約のデータは記録されません。

An integrated circuit self-protected against reversal of the supply battery polarity

An integrated circuit (1) self-protected agianst reversal of the supply battery (2) polarity comprises a first DMOS power transistor (T1) connected with its source electrode (S1) side to an electric load (R1) to be driven toward ground, and a second, protective DMOS transistor (T2) which is connected with its source electrode (S2) side to a positive pole (Vc) of the battery (2) and with its drain electrode (D2) side to the drain electrode (D1) of the first transistor (T1). The first T1) and second (T2) transistors have in common the drain region formed on a single pod (9) in the semiconductor substrate (4).

Semiconductor device with a plurality of transistors

一种半导体器件包括：衬底，包括第一有源图案和第二有源图案；栅电极，包括位于所述第一有源图案上的第一栅电极和位于所述第二有源图案上的第二栅电极；栅极切割图案，位于所述第一栅电极和所述第二栅电极之间；栅极间隔物，位于所述栅电极的相对的侧表面上；以及栅极覆盖图案，位于所述栅电极的顶表面、所述栅极切割图案的顶表面和所述栅极间隔物的顶表面上并且在所述第一方向上延伸。所述栅极切割图案包括在与所述第一方向交叉的第二方向上彼此相对的第一侧表面和第二侧表面。所述第一侧表面和所述第二侧表面与所述栅极间隔物中的相应的栅极间隔物接触，并且所述栅极切割图案的所述顶表面比成对的所述栅极间隔物的所述顶表面更靠近所述衬底。

Four rail circuit architecture for ultra-low power and voltage CMOS circuit design

A circuit architecture is disclosed wherein power is supplied to a CMOS circuit through a first pair of voltage rails, including a first voltage rail (12) providing a first voltage and a second voltage rail (14) providing a second voltage, and a second pair of voltage rails, including a third voltage rail (16) providing a third voltage and a fourth voltage rail (18) providing a fourth voltage. Components (20, 22) comprising two circuit portions are connected across either the first or second pair of voltage rails. The voltage difference across each pair of voltage rails is less than the threshold voltage of the groups of component (20, 22) so that very little current is drawn. Because the voltage offset between the first and second pairs of rails is greater than the threshold voltage of the groups of components (20, 22), sufficient voltage is provided for switching. Circuitry may be provided for monitoring the voltage of one of the rails to insure that its value provides the proper off current and for biasing both the substrate and wells to compensate for variations amongst components. The four rail architecture of the present invention may be combined with a Class B output buffer or the four rail circuit itself may be designed as a Class B circuit to reduce power consumption.

Electrical isolation in integrated circuits

A back biasing technique is provided for increasing the field inversion voltage between adjacent MOS transistors and for reducing parasitic capacitances in an integrated circuit. The use of a charge pump is avoided by connecting the body portions of the MOS transistors to ground and the sources of the MOS transistors to the anode of a diode, the cathode of which are connected to a reference voltage such as to ground. In this manner, the sources are back biased relative to the material in which they are formed by a diode forward voltage drop. This technique is particularly applicable to CMOS circuits operating from a 3.3 volt supply, with p-well doping densities in excess of 1×10 17 atoms/cm 3 .

Semiconductor integrated circuit device

(57)【要約】本公報は電子出願前の出願データであるた め要約のデータは記録されません。

Mos semiconductor device

(57)【要約】本公報は電子出願前の出願データであるた め要約のデータは記録されません。

Semiconductor device

Boosting circuit improved to operate in a wider range of power supply voltage, and a semiconductor memory and a semiconductor integrated circuit device using the same

A boosting circuit is provided applicable in various semiconductor integrated circuits such as a word line boosting circuit in a semiconductor memory. Because a backgate electrode of a PMOS transistor connected between power supply potential and an output node is connected to the output node, the output node is precharged to the Vcc level during a boosting term. Therefore, the boosting condition by a MOS capacitor is alleviated in comparison with a conventional boosting circuit. Proper boosting operation can be carried out even at a lower level of a supplied power supply voltage. Therefore, operable margin of power supply voltage is enlarged.

High voltage charge pump using low voltage type transistors

An integrated circuit includes an N isolation buried layer underlying high density and low voltage type P channel and N channel transistors to define islands of arbitrary voltage on the substrate. Thus such transistors, which otherwise are capable only of low voltage operation, become capable of operating at high voltage relative to the substrate. This allows integration, on a single chip, of high voltage circuit elements with low voltage and high density transistors all formed by the same fabrication process sequence. In one example this allows creation of an 18 volts range charge pump using a CMOS process which normally provides only 3 volt operating range transistors. This then allows integration on a single integrated circuit chip of a complex digital logic function such as a UART (universal asynchronous receiver and transmitter) with a high voltage function such as an RS-232 interface, including integrated capacitors for the RS-232 interface charge pump.

Patent JPS6334708B2

Semiconductor device

기판전위 발생회로를 구비하고 있어도 동작속도를 저하시키지 않으면서도, 래치업 (latch up) 내성 및 정전파괴 내성의 확보를 도모할 수 있는 반도체 장치를 제공한다. Provided is a semiconductor device capable of securing latch up resistance and electrostatic breakdown resistance without lowering the operation speed even with a substrate potential generating circuit. P 형 기판 (10) 에 전위를 인가하는 기판전위 발생회로 (80), CMOS 내부회로 (12), 정전파괴방지 보호소자 (74) 및 래치업 방지 보호소자 (84) 를 구비하고 있으며, 이 보호소자 (84) 는 P형 기판 (10) 에 N형의 제 1 확산영역 (90)을 구비하며, 이 제 1 확산영역 (90) 에 입력단자에 접속된 N 형의 제 2 확산영역 (92) 및 전원전압 (V CC ) 이 인가된 P형의 제 3 확산영역 (94) 을 구비하고, 이 제 1 확산영역 (96) 의 주위에, 접지전압 (V SS ) 이 인가된 N 형의 제 4 확산영역 (96) 을 평면패턴으로 보아 당해 제 1 확산영역 (90) 을 둘러싸듯이 설치되어 있다. A substrate potential generating circuit 80, a CMOS internal circuit 12, an electrostatic breakdown protection device 74, and a latchup protection device 84 for applying a potential to the P-type substrate 10 are provided. The element 84 has an N-type first diffusion region 90 in the P-type substrate 10, and an N-type second diffusion region 92 connected to the input terminal in the first diffusion region 90. And a P-type third diffusion region 94 to which a power supply voltage V CC is applied, and an N-type fourth to which a ground voltage V SS is applied around the first diffusion region 96. The diffusion region 96 is viewed in a planar pattern so as to surround the first diffusion region 90.

Semiconductor integrated circuit device having power reduction mechanism

A semiconductor integrated circuit device is composed of logic gates each provided with at least two MOS transistors. The logic gates are connected to a first potential point and a second potential point. The semiconductor integrated circuit device includes a current control device connected between the logic gate and the first potential point and/or between the logic gate and the second potential point for controlling a value of a current flowing in the logic gate depending on an operating state of the logic gate. The circuit can be used in devices that cycle in operation between high and low power consumption modes, such as microprocessors that have both an operation mode and a low power back-up or sleep mode used for power reduction.

Semiconductor module with built-in noise reduction circuit

The module includes an internal circuit (21), a stabilisation circuit (23), two voltage current supply lines (13,15), and a contact block (11). The current supply lines supply current at the same a particular voltage to the respective internal and stabilisation circuits. The contact block interconnects the two current supply lines. Pref. a third current potential supply line (3) feeds the current supply potential into the two current supply, potential supply lines. The third current potential supply line has an inductivity and is linked to the contact block as a wire.

Semiconductor device

Semiconductor memory device and manufacturing method thereof

MOSFET and memory cell having improved drain current through back bias application

A semiconductor metal-oxide-semiconductor field effect transistor (MOSFET) transistor with increased on-state current obtained through intrinsic bipolar junction transistor (BJT) of MOSFET has been described. Methods of operating the MOS transistor are provided.

Semiconductor memory device

본원의 목적은 신뢰성이 높은 반도체 기억 장치를 제공하는 것에 있다. 반도체 기억 장치는, p형 불순물을 제1 농도로 포함하는 실리콘 기판(109)과, 실리콘 기판(109)에 형성되고, 제1 농도보다 낮은 제2 농도로 p형 불순물을 갖는 에피택셜층(108)과, 에피택셜층(108) 상에 형성되는 기억 영역(191)과, 에피택셜층(108) 상에서 기억 영역(191)과 다른 위치에 형성되는 논리 회로 영역(192)을 포함한다. 기억 영역(191)은, p형 웰(105)과, n형 웰(113)과, 보텀 웰(102)을 포함한다. 논리 회로 영역(192)은 상보형 전계 효과형 트랜지스터를 포함한다. An object of the present application is to provide a highly reliable semiconductor memory device. The semiconductor memory device includes a silicon substrate 109 including p-type impurities at a first concentration, and an epitaxial layer 108 formed on the silicon substrate 109 and having p-type impurities at a second concentration lower than the first concentration. ), A storage region 191 formed on the epitaxial layer 108, and a logic circuit region 192 formed at a position different from the storage region 191 on the epitaxial layer 108. The storage region 191 includes a p-type well 105, an n-type well 113, and a bottom well 102. Logic circuit region 192 includes complementary field effect transistors.

Semiconductor device

(57)【要約】本公報は電子出願前の出願データであるた め要約のデータは記録されません。

Semiconductor structures with body contacts and fabrication methods thereof

A semiconductor structure for a dynamic random access memory (DRAM) cell array that includes a plurality of vertical memory cells built on a semiconductor-on-insulator (SOI) wafer and a body contact electrically coupling a semiconductor body and a semiconductor substrate of the SOI wafer. The semiconductor body includes a channel region for the access device of one of the vertical memory cells. The body contact, which extends through a buried dielectric layer of the SOI wafer, provides a current leakage path that reduces the impact of floating body effects upon the vertical memory cell. The body contact may be formed by etching a via that extends through the semiconductor body and buried dielectric layer of the SOI wafer and extends into the substrate and partially filling the via with a conductive material that electrically couples the semiconductor body with the substrate.

Method of forming multi-threshold voltage devices and devices so formed

A method provides a gate structure for a plurality of components of a semiconductor device. A silicate layer is provided. In one aspect, the silicate layer is provided on a channel of a CMOS device. A high dielectric constant layer is provided on the silicate layer. The method also includes providing a work function metal layer on the high dielectric constant layer. A low temperature anneal is performed after the high dielectric constant layer is provided. A contact metal layer is provided on the work function metal layer.

Compact trench capacitor memory cell with body contact

A semiconductor device includes at least two active areas, each active area surrounding a corresponding trench in a substrate. The trenches each include a capacitor in a lower portion of the trench and a gate in an upper portion of the trench. A vertical transistor is formed adjacent to the trench in the upper portion for charging and discharging the capacitor. A body contact is formed between the at least two active areas. The body contact connects to the at least two active areas and to a diffusion well of the substrate for preventing floating body effects in the vertical transistor.

INTEGRATED ELECTRIC POWER CIRCUIT.

Semiconductor integrated circuit device

Cmos substrate biasing for threshold voltage control

반도체장치는 PMOS트랜지스터(101)와 NMOS트랜지스터(103)를 포함한다. The semiconductor device includes a PMOS transistor 101 and an NMOS transistor 103. 스텐바이상태에서, PMOS트랜지스터의 기판에는 Vcc레벨의 전위가 인가되고, NMOS트랜지스터의 기판에는 Vss레벨의 전위가 인가된다. In the standby state, the potential of the Vcc level is applied to the substrate of the PMOS transistor, and the potential of the Vss level is applied to the substrate of the NMOS transistor. 그러므로, P 및 NMOS트랜지스터의 소스-기판사이의 전압은 0V로 된다. Therefore, the voltage between the source and substrate of the P and NMOS transistors becomes 0V. 액티브상태에서, 빌트인포텐셜보다 낮은 소스-기판사이의 전압으로 되는 전위가 P 및 NMOS트랜지스터의 각 기판에 인가된다. In the active state, a potential that results in a voltage between the source and the substrate lower than the built-in potential is applied to each substrate of the P and NMOS transistors. 그러므로, 트랜지스터의 한계치전압은 스텐바이상태에서보다 액티브상태에서 더 낮게 되어, 소스-기판사이에는 리이크전류가 거의 흐르지 않는다. Therefore, the threshold voltage of the transistor is lower in the active state than in the standby state, so that little leakage current flows between the source and the substrate.

Semiconductor memory device having novel layout pattern

본 발명은 제 1 도전형의 반도체 기판내에 형성된 제 2 도전형의 깊은 웰, 상기 깊은 웰상에 형성된 제 1 도전형의 셀 어레이용 웰, 및 내부영역에 상기 셀 어레이용 웰을 수용하도록 하기 위해 상기 깊은 웰에 도달하도록 상기 셀 어레이용 웰의 주변에 형성된 제 2 도전형의 분리용 웰을 구비하여, 상기 분리용 웰에 의해 상기 셀 어레이용 웰을 상기 반도체 기판과 분리시키고, 상기 분리용 웰에 상기 셀 어레이를 구동하기 위한 회로소자가 형성되어 있는 것을 특징으로 하는 반도체 기억장치를 제공한다. The present invention provides a second well type deep well formed in a semiconductor substrate of a first conductivity type, a cell array well of a first conductivity type formed on the deep well, and an inner region for accommodating the cell array well. A second conductivity type separation well formed around the cell array well so as to reach a deep well, wherein the cell well is separated from the semiconductor substrate by the separation well. There is provided a semiconductor memory device characterized in that a circuit element for driving the cell array is formed.

Multifunction fuzzy logical circuit

(57)【要約】本公報は電子出願前の出願データであるた め要約のデータは記録されません。

Improved integrated circuit structure containinh current bus and nanufacture of the same

(57)【要約】本公報は電子出願前の出願データであるた め要約のデータは記録されません。

Semiconductor device

Semiconductor memory device

The present invention contemplates a highly reliable semiconductor memory device. The semiconductor memory device includes a silicon substrate containing a p impurity of a first concentration, an epitaxial layer formed at the silicon substrate and containing a p impurity having a second concentration lower than the first concentration, a memory region provided on the epitaxial layer, and a logic circuit region provided on the epitaxial layer at a location different from the memory region. The memory region includes a p well, an n well and a bottom well. The logic circuit region includes a complementary field effect transistor.

High voltage integrated circuit

Integrated circuit in complementary circuit technology comprising a substrate bias voltage generator and a Schottky diode

An integrated circuit in complementary circuit technology comprising a substrate bias voltage generator which applies a negative (positive) substrate bias voltage to the p(n) substrate in which n(p) tubs are inserted. The source regions of the n(p)-channel FETs arranged in the substrate lie at ground potential. In order to avoid "latch-up" effects, an output of the substrate bias voltage generator is connected via a Schottky diode to a circuit point that lies at ground potential.

An all-CMOS high-impedance output buffer for a bus driven by multiple power-supply voltages

An all-CMOS output buffer drives a bus that can operate at 3 volts and 5 volts. When in a high-impedance state, the output buffer draws little or no current. If the bus is driven to 5 volts by an external device, the high impedance output buffer is in danger of latch-up and distortion of the bus logic level since it only has a 3-volt power supply and does not use a charge pump or an extra 5-volt supply. A biasing circuit couples an N-well that contains p-channel transistors and a driver transistor to the bus driven to 5 volts. Thus the N-well is also driven to 5 volts, the voltage on the bus. The gate of the p-channel driver transistor in the high-impedance output buffer is also coupled to the N-well by another p-channel transistor, raising the gate potential to 5 volts. Thus the gate and body of the p-channel driver transistor is at 5 volts, eliminating reversing current and latch-up problems. A transmission gate isolates the gate of the p-channel driver transistor from the rest of the device's circuitry. The p-channel transistors of the transmission gate, bias circuitry, and driver transistor are located in the N-well, which is biased up to 5 volts only when necessary. Thus during normal operation, the N-well of the driver transistor is at 3 volts, eliminating a performance loss from the body effect. A logic gate increases the well bias and isolates the driver's gate only when necessary, when the bus is high and driven by a 5-volt device, and the output buffer is in high-impedance.